[ExportVerilog] Unpacked array assignment to wire

[teqdruid]

hw.module @top() {
  %10 = hw.aggregate_constant [120 : i8, -38 : i8] : !hw.uarray<2xi8>
  hw.instance "e" @Ext(a: %10: !hw.uarray<2xi8>) -> ()
  hw.output
}
hw.module.extern @Ext(in %a: !hw.uarray<2xi8>)

Run through --export-verilog produces:

module top();	// test.mlir:1:1
  wire [7:0] _GEN[0:1] = '{8'h78, 8'hDA};	// test.mlir:2:9
  Ext e (	// test.mlir:3:3
    .a (_GEN)	// test.mlir:2:9
  );
endmodule

Which Verilator (4.110 and 5.018) chokes on:

%Error: test.sv:3:24: syntax error, unexpected '=', expecting ',' or ';'
    3 |   wire [7:0] _GEN[0:1] = '{8'h78, 8'hDA};

Changing wire to logic or reg eliminates that error message.

This may just be Verilator. Questa likes it, but Questa is very permissive. Icarus (iverilog) doesn't like assigning unpacked arrays at all so I have to break out all of the individual assignments to get it to not complain. I don't know what the spec says (but it doesn't matter). Do other simulators accept this?

[uenoku]

Yeah, VCS accepts this. had a PR to make verilator happy #4548 so I'll rebase it.