Anyone with any experience on increasing SPI size?

[ThePlexus]

Following on from #545 im trying to get a larger SPI chip working with the P8H61-M Pro. Swapping out the chip and setting coreboot to a 16mb image, along with modification of the VSCC table to include the new JID0 does not seem to be working well for me. have validated opcodes and granularity in VSCC0 are correct.

Does anyone have any pointers or references they could point me to? I thought id ask here before asking upstream in coreboot.

thanks folks.

[ThePlexus]

This is probably a good place to start

https://www.coreboot.org/Board:lenovo/x220#Bigger_SPI_ROM

My problem was my SPI was a different manufacturer. Despite changing the correct parts of the ROM to use the new chips identifiers and sizes.

i got some Winbonds on backorder and will update this when i figure it out. closing for now

[ThePlexus]

So this was achieved. My P8H61-m pro now rocks coreboot on a 16MB SPI. There was a problem using the method linked above, but the correct result was not far off. A word of warning, when using ifdtool to --newlayout, it likes to copy the data not just adjust the layout. Which means if you build a 16MB coreboot image and then ifdtool the layout, you are likely going to get a CBFS full of nothing but 0xFF

What i did was as follows;

1. build a coreboot image using the flash descriptor gained from the factory stock rom. Ensure to have 16MB selected under Mainboard->ROM chip siz

2. in hex editor of choice, edit the VSCC table starting at 0xDF0 and set to match your new chip ID. I used the SPI driver from linux kernel in openSUSE git repo as a reference. I went from w25q32 to w25q128 so I looked for 0xEF4016 and changed to 0xEF4018. Heres the list, buried in this code , line 1725 onwards https://github.com/openSUSE/kernel/blob/master/drivers/mtd/spi-nor/spi-nor.c

3. use ifdtool -D 16 coreboot.rom to set the density of the chip (of course, set it relative to your own chip)

4. mv coreboot.rom.new coreboot.rom

5. dump the layout and edit. ifdtool --layout layout.txt coreboot.rom . You then edit layout.txt and set the bios region endpoint to match your chip. mine was
   00180000:003fffff bios
   I set to
   00180000:00ffffff bios
   If you have a 8Mb chip you would set it to
   00180000:007fffff bios

6. Write the new layout to the flash descriptor. WARNING, this will now try to move partitions also and write 0xFF all over your CBFS. This is expected. we dont need the CBFS data at this stage.
   ifdtool --newlayout layout.txt coreboot.rom

7. mv coreboot.rom.new coreboot.rom

8. now extract the newly constructed firmware descriptor
   ifdtool -x coreboot.rom
   you get a file like 'flashregion_0_flashdescriptor.bin'

9. edit your coreboot config and set Chipset->Path and filename of descriptor.bin file. This should be pointed to flashregion_0_flashdescriptor.bin that you got in step 9

10. make coreboot. Flash 16MB rom to SPI and plug it into the system.

Voila. One 16 MB capacity upgrade.

Note: you may want to play with the CBFS size rather than stick with the standard. Mainboard->Size of CBFS filesystem in ROM coreboot menu item. I set mine to CONFIG_CBFS_SIZE=0x700000