diff --git a/Makefile b/Makefile
index 275c6a6..c46768e 100644
--- a/Makefile
+++ b/Makefile
@@ -17,7 +17,7 @@ $(PROJ).json: LighthouseTopLevel.v
 	yosys -p 'read_verilog LighthouseTopLevel.v; read_verilog  blackboxes.v; synth_ice40 -top LighthouseTopLevel; write_json $@'
 
 %.asc: %.json $(PIN_DEF)
-	nextpnr-ice40 --seed 18 --up5k --json $< --asc $@ --pcf $(PIN_DEF)
+	nextpnr-ice40 --seed 19 --up5k --json $< --asc $@ --pcf $(PIN_DEF)
 	python3 tools/update_bitstream_comment.py $@ "$(VERSION)"
 
 %.bin: %.asc
diff --git a/rtl/ts4231Configurator.v b/rtl/ts4231Configurator.v
index 4f465e2..098ea28 100644
--- a/rtl/ts4231Configurator.v
+++ b/rtl/ts4231Configurator.v
@@ -47,6 +47,7 @@ module ts4231Configurator (
   reg [5:0] config_bit_counter = 0;
   reg [14:0] config_value = {14'h392b, 1'b0};
   reg config_bit = 0;
+  reg [4:0] config_wait_counter = 0;
   always @(posedge clk) begin
     if (config_enable) begin
       prev_reconfigure <= reconfigure;
@@ -55,7 +56,10 @@ module ts4231Configurator (
       case (config_state)
         CONFIG_IDLE: if (prev_reconfigure == 0 && reconfigure == 1) config_state <= CONFIG_WAIT_PULSE;
         CONFIG_WAIT_PULSE: if (config_prev_d == 1 && d_in == 0) config_state <= CONFIG_START_CFG;
-        CONFIG_START_CFG: config_state <= CONFIG_WRITE_START;
+        CONFIG_START_CFG: begin
+          if (config_wait_counter == 4) config_state <= CONFIG_WRITE_START;
+          config_wait_counter = config_wait_counter + 1;
+        end
         CONFIG_WRITE_START: begin
           config_bit_counter <= 0;
           config_state <= CONFIG_WRITE_E_LOW;
@@ -87,8 +91,8 @@ module ts4231Configurator (
     (* parallel_case *)
     case (config_state)
       CONFIG_START_CFG: begin
-        e_out = 1;
-        e_oe  = 1;
+        e_out = (config_wait_counter == 4);
+        e_oe  = (config_wait_counter == 4);
         d_out = 0;
         d_oe  = 0;
       end
@@ -142,4 +146,4 @@ module ts4231Configurator (
       end
     endcase
   end
-endmodule
\ No newline at end of file
+endmodule