diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMD21/TARGET_SAMD21J18A/TOOLCHAIN_GCC_ARM/samd21j18a.ld b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMD21/TARGET_SAMD21J18A/TOOLCHAIN_GCC_ARM/samd21j18a.ld
index 218f7deedca..d80cded0c3c 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMD21/TARGET_SAMD21J18A/TOOLCHAIN_GCC_ARM/samd21j18a.ld
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMD21/TARGET_SAMD21J18A/TOOLCHAIN_GCC_ARM/samd21j18a.ld
@@ -3,19 +3,17 @@ OUTPUT_ARCH(arm)
SEARCH_DIR(.)
/* Memory Spaces Definitions */
-MEMORY
-{
- rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000
- ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
-}
+MEMORY {
+ rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
+ }
-/* The stack size used by the application. NOTE: you need to adjust according to your application. */
-STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
+ /* The stack size used by the application. NOTE: you need to adjust according to your application. */
+ STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
-/* Section Definitions */
-SECTIONS
-{
- .text :
+ /* Section Definitions */
+ SECTIONS {
+.text :
{
. = ALIGN(4);
_sfixed = .;
@@ -66,23 +64,24 @@ SECTIONS
/* .ARM.exidx is sorted, so has to go in its own output section. */
PROVIDE_HIDDEN (__exidx_start = .);
- .ARM.exidx :
+.ARM.exidx :
{
- *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > rom
PROVIDE_HIDDEN (__exidx_end = .);
. = ALIGN(4);
_etext = .;
-
- .dvectors (NOLOAD) :
- {
- _sdvectors = .;
- . = . + 0xB0;
- _edvectors = .;
- } > ram
-
- .relocate : AT (_etext)
+
+ .dvectors (NOLOAD) :
+ {
+ _sdvectors = .;
+ . = . + 0xB0;
+ _edvectors = .;
+ } > ram
+
+.relocate :
+ AT (_etext)
{
. = ALIGN(4);
_srelocate = .;
@@ -105,12 +104,12 @@ SECTIONS
_ezero = .;
} > ram
- .heap (NOLOAD) :
- {
- . = ALIGN(4);
- __end__ = . ;
- . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE;
- } > ram
+ .heap (NOLOAD) :
+ {
+ . = ALIGN(4);
+ __end__ = . ;
+ . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE;
+ } > ram
/* stack section */
.stack (NOLOAD):
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_GCC_ARM/samr21g18a.ld b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_GCC_ARM/samr21g18a.ld
index 218f7deedca..d80cded0c3c 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_GCC_ARM/samr21g18a.ld
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_GCC_ARM/samr21g18a.ld
@@ -3,19 +3,17 @@ OUTPUT_ARCH(arm)
SEARCH_DIR(.)
/* Memory Spaces Definitions */
-MEMORY
-{
- rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000
- ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
-}
+MEMORY {
+ rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
+ }
-/* The stack size used by the application. NOTE: you need to adjust according to your application. */
-STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
+ /* The stack size used by the application. NOTE: you need to adjust according to your application. */
+ STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
-/* Section Definitions */
-SECTIONS
-{
- .text :
+ /* Section Definitions */
+ SECTIONS {
+.text :
{
. = ALIGN(4);
_sfixed = .;
@@ -66,23 +64,24 @@ SECTIONS
/* .ARM.exidx is sorted, so has to go in its own output section. */
PROVIDE_HIDDEN (__exidx_start = .);
- .ARM.exidx :
+.ARM.exidx :
{
- *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > rom
PROVIDE_HIDDEN (__exidx_end = .);
. = ALIGN(4);
_etext = .;
-
- .dvectors (NOLOAD) :
- {
- _sdvectors = .;
- . = . + 0xB0;
- _edvectors = .;
- } > ram
-
- .relocate : AT (_etext)
+
+ .dvectors (NOLOAD) :
+ {
+ _sdvectors = .;
+ . = . + 0xB0;
+ _edvectors = .;
+ } > ram
+
+.relocate :
+ AT (_etext)
{
. = ALIGN(4);
_srelocate = .;
@@ -105,12 +104,12 @@ SECTIONS
_ezero = .;
} > ram
- .heap (NOLOAD) :
- {
- . = ALIGN(4);
- __end__ = . ;
- . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE;
- } > ram
+ .heap (NOLOAD) :
+ {
+ . = ALIGN(4);
+ __end__ = . ;
+ . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE;
+ } > ram
/* stack section */
.stack (NOLOAD):
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_IAR/startup_samr21.c b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_IAR/startup_samr21.c
index 297ef249c41..8fab8a8ea98 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_IAR/startup_samr21.c
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_IAR/startup_samr21.c
@@ -42,7 +42,10 @@
#include "samr21.h"
typedef void (*intfunc) (void);
-typedef union { intfunc __fun; void * __ptr; } intvec_elem;
+typedef union {
+ intfunc __fun;
+ void * __ptr;
+} intvec_elem;
void __iar_program_start(void);
int __low_level_init(void);
@@ -116,89 +119,89 @@ void Dummy_Handler(void);
#pragma section = ".intvec"
#pragma location = ".intvec"
const DeviceVectors __vector_table[] = {
- __sfe("CSTACK"),
- (void*) __iar_program_start,
- (void*) NMI_Handler,
- (void*) HardFault_Handler,
- (void*) (0UL), /* Reserved */
- (void*) (0UL), /* Reserved */
- (void*) (0UL), /* Reserved */
- (void*) (0UL), /* Reserved */
- (void*) (0UL), /* Reserved */
- (void*) (0UL), /* Reserved */
- (void*) (0UL), /* Reserved */
- (void*) SVC_Handler,
- (void*) (0UL), /* Reserved */
- (void*) (0UL), /* Reserved */
- (void*) PendSV_Handler,
- (void*) SysTick_Handler,
-
- /* Configurable interrupts */
- (void*) PM_Handler, /* 0 Power Manager */
- (void*) SYSCTRL_Handler, /* 1 System Control */
- (void*) WDT_Handler, /* 2 Watchdog Timer */
- (void*) RTC_Handler, /* 3 Real-Time Counter */
- (void*) EIC_Handler, /* 4 External Interrupt Controller */
- (void*) NVMCTRL_Handler, /* 5 Non-Volatile Memory Controller */
- (void*) DMAC_Handler, /* 6 Direct Memory Access Controller */
+ __sfe("CSTACK"),
+ (void*) __iar_program_start,
+ (void*) NMI_Handler,
+ (void*) HardFault_Handler,
+ (void*) (0UL), /* Reserved */
+ (void*) (0UL), /* Reserved */
+ (void*) (0UL), /* Reserved */
+ (void*) (0UL), /* Reserved */
+ (void*) (0UL), /* Reserved */
+ (void*) (0UL), /* Reserved */
+ (void*) (0UL), /* Reserved */
+ (void*) SVC_Handler,
+ (void*) (0UL), /* Reserved */
+ (void*) (0UL), /* Reserved */
+ (void*) PendSV_Handler,
+ (void*) SysTick_Handler,
+
+ /* Configurable interrupts */
+ (void*) PM_Handler, /* 0 Power Manager */
+ (void*) SYSCTRL_Handler, /* 1 System Control */
+ (void*) WDT_Handler, /* 2 Watchdog Timer */
+ (void*) RTC_Handler, /* 3 Real-Time Counter */
+ (void*) EIC_Handler, /* 4 External Interrupt Controller */
+ (void*) NVMCTRL_Handler, /* 5 Non-Volatile Memory Controller */
+ (void*) DMAC_Handler, /* 6 Direct Memory Access Controller */
#ifdef ID_USB
- (void*) USB_Handler, /* 7 Universal Serial Bus */
+ (void*) USB_Handler, /* 7 Universal Serial Bus */
#else
- (void*) (0UL), /* Reserved*/
+ (void*) (0UL), /* Reserved*/
#endif
- (void*) EVSYS_Handler, /* 8 Event System Interface */
- (void*) SERCOM0_Handler, /* 9 Serial Communication Interface 0 */
- (void*) SERCOM1_Handler, /* 10 Serial Communication Interface 1 */
- (void*) SERCOM2_Handler, /* 11 Serial Communication Interface 2 */
- (void*) SERCOM3_Handler, /* 12 Serial Communication Interface 3 */
+ (void*) EVSYS_Handler, /* 8 Event System Interface */
+ (void*) SERCOM0_Handler, /* 9 Serial Communication Interface 0 */
+ (void*) SERCOM1_Handler, /* 10 Serial Communication Interface 1 */
+ (void*) SERCOM2_Handler, /* 11 Serial Communication Interface 2 */
+ (void*) SERCOM3_Handler, /* 12 Serial Communication Interface 3 */
#ifdef ID_SERCOM4
- (void*) SERCOM4_Handler, /* 13 Serial Communication Interface 4 */
+ (void*) SERCOM4_Handler, /* 13 Serial Communication Interface 4 */
#else
- (void*) (0UL), /* Reserved*/
+ (void*) (0UL), /* Reserved*/
#endif
#ifdef ID_SERCOM5
- (void*) SERCOM5_Handler, /* 14 Serial Communication Interface 5 */
+ (void*) SERCOM5_Handler, /* 14 Serial Communication Interface 5 */
#else
- (void*) (0UL), /* Reserved*/
-#endif
- (void*) TCC0_Handler, /* 15 Timer Counter Control 0 */
- (void*) TCC1_Handler, /* 16 Timer Counter Control 1 */
- (void*) TCC2_Handler, /* 17 Timer Counter Control 2 */
- (void*) TC3_Handler, /* 18 Basic Timer Counter 0 */
- (void*) TC4_Handler, /* 19 Basic Timer Counter 1 */
- (void*) TC5_Handler, /* 20 Basic Timer Counter 2 */
+ (void*) (0UL), /* Reserved*/
+#endif
+ (void*) TCC0_Handler, /* 15 Timer Counter Control 0 */
+ (void*) TCC1_Handler, /* 16 Timer Counter Control 1 */
+ (void*) TCC2_Handler, /* 17 Timer Counter Control 2 */
+ (void*) TC3_Handler, /* 18 Basic Timer Counter 0 */
+ (void*) TC4_Handler, /* 19 Basic Timer Counter 1 */
+ (void*) TC5_Handler, /* 20 Basic Timer Counter 2 */
#ifdef ID_TC6
- (void*) TC6_Handler, /* 21 Basic Timer Counter 3 */
+ (void*) TC6_Handler, /* 21 Basic Timer Counter 3 */
#else
- (void*) (0UL), /* Reserved*/
+ (void*) (0UL), /* Reserved*/
#endif
#ifdef ID_TC7
- (void*) TC7_Handler, /* 22 Basic Timer Counter 4 */
+ (void*) TC7_Handler, /* 22 Basic Timer Counter 4 */
#else
- (void*) (0UL), /* Reserved*/
+ (void*) (0UL), /* Reserved*/
#endif
#ifdef ID_ADC
- (void*) ADC_Handler, /* 23 Analog Digital Converter */
+ (void*) ADC_Handler, /* 23 Analog Digital Converter */
#else
- (void*) (0UL), /* Reserved*/
+ (void*) (0UL), /* Reserved*/
#endif
#ifdef ID_AC
- (void*) AC_Handler, /* 24 Analog Comparators */
+ (void*) AC_Handler, /* 24 Analog Comparators */
#else
- (void*) (0UL), /* Reserved*/
+ (void*) (0UL), /* Reserved*/
#endif
#ifdef ID_DAC
- (void*) DAC_Handler, /* 25 Digital Analog Converter */
+ (void*) DAC_Handler, /* 25 Digital Analog Converter */
#else
- (void*) (0UL), /* Reserved*/
+ (void*) (0UL), /* Reserved*/
#endif
#ifdef ID_PTC
- (void*) PTC_Handler, /* 26 Peripheral Touch Controller */
+ (void*) PTC_Handler, /* 26 Peripheral Touch Controller */
#else
- (void*) (0UL), /* Reserved*/
+ (void*) (0UL), /* Reserved*/
#endif
- (void*) I2S_Handler, /* 27 Inter-IC Sound Interface */
- (void*) (0UL), /* Reserved */
+ (void*) I2S_Handler, /* 27 Inter-IC Sound Interface */
+ (void*) (0UL), /* Reserved */
};
/**------------------------------------------------------------------------------
@@ -207,11 +210,11 @@ const DeviceVectors __vector_table[] = {
*------------------------------------------------------------------------------*/
int __low_level_init(void)
{
- uint32_t *pSrc = __section_begin(".intvec");
+ uint32_t *pSrc = __section_begin(".intvec");
- SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
+ SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
- return 1; /* if return 0, the data sections will not be initialized */
+ return 1; /* if return 0, the data sections will not be initialized */
}
/**------------------------------------------------------------------------------
@@ -220,20 +223,20 @@ int __low_level_init(void)
*------------------------------------------------------------------------------*/
void Reset_Handler(void)
{
- /* Change default QOS values to have the best performance and correct USB behaviour */
- SBMATRIX->SFR[SBMATRIX_SLAVE_HMCRAMC0].reg = 2;
+ /* Change default QOS values to have the best performance and correct USB behaviour */
+ SBMATRIX->SFR[SBMATRIX_SLAVE_HMCRAMC0].reg = 2;
#if defined(ID_USB)
- USB->DEVICE.QOSCTRL.bit.CQOS = 2;
- USB->DEVICE.QOSCTRL.bit.DQOS = 2;
+ USB->DEVICE.QOSCTRL.bit.CQOS = 2;
+ USB->DEVICE.QOSCTRL.bit.DQOS = 2;
#endif
- DMAC->QOSCTRL.bit.DQOS = 2;
- DMAC->QOSCTRL.bit.FQOS = 2;
- DMAC->QOSCTRL.bit.WRBQOS = 2;
+ DMAC->QOSCTRL.bit.DQOS = 2;
+ DMAC->QOSCTRL.bit.FQOS = 2;
+ DMAC->QOSCTRL.bit.WRBQOS = 2;
- /* Overwriting the default value of the NVMCTRL.CTRLB.MANW bit (errata reference 13134) */
- NVMCTRL->CTRLB.bit.MANW = 1;
+ /* Overwriting the default value of the NVMCTRL.CTRLB.MANW bit (errata reference 13134) */
+ NVMCTRL->CTRLB.bit.MANW = 1;
- __iar_program_start();
+ __iar_program_start();
}
/**
@@ -241,6 +244,6 @@ void Reset_Handler(void)
*/
void Dummy_Handler(void)
{
- while (1) {
- }
+ while (1) {
+ }
}
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_ac.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_ac.h
index 7d133bfc643..55f0b63ce67 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_ac.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_ac.h
@@ -59,14 +59,14 @@
/* -------- AC_CTRLA : (AC Offset: 0x00) (R/W 8) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t SWRST:1; /*!< bit: 0 Software Reset */
- uint8_t ENABLE:1; /*!< bit: 1 Enable */
- uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */
- uint8_t :4; /*!< bit: 3.. 6 Reserved */
- uint8_t LPMUX:1; /*!< bit: 7 Low-Power Mux */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable */
+ uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */
+ uint8_t :4; /*!< bit: 3.. 6 Reserved */
+ uint8_t LPMUX:1; /*!< bit: 7 Low-Power Mux */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} AC_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -87,16 +87,16 @@ typedef union {
/* -------- AC_CTRLB : (AC Offset: 0x01) ( /W 8) Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t START0:1; /*!< bit: 0 Comparator 0 Start Comparison */
- uint8_t START1:1; /*!< bit: 1 Comparator 1 Start Comparison */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t START:2; /*!< bit: 0.. 1 Comparator x Start Comparison */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t START0:1; /*!< bit: 0 Comparator 0 Start Comparison */
+ uint8_t START1:1; /*!< bit: 1 Comparator 1 Start Comparison */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t START:2; /*!< bit: 0.. 1 Comparator x Start Comparison */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} AC_CTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -115,25 +115,25 @@ typedef union {
/* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t COMPEO0:1; /*!< bit: 0 Comparator 0 Event Output Enable */
- uint16_t COMPEO1:1; /*!< bit: 1 Comparator 1 Event Output Enable */
- uint16_t :2; /*!< bit: 2.. 3 Reserved */
- uint16_t WINEO0:1; /*!< bit: 4 Window 0 Event Output Enable */
- uint16_t :3; /*!< bit: 5.. 7 Reserved */
- uint16_t COMPEI0:1; /*!< bit: 8 Comparator 0 Event Input */
- uint16_t COMPEI1:1; /*!< bit: 9 Comparator 1 Event Input */
- uint16_t :6; /*!< bit: 10..15 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint16_t COMPEO:2; /*!< bit: 0.. 1 Comparator x Event Output Enable */
- uint16_t :2; /*!< bit: 2.. 3 Reserved */
- uint16_t WINEO:1; /*!< bit: 4 Window x Event Output Enable */
- uint16_t :3; /*!< bit: 5.. 7 Reserved */
- uint16_t COMPEI:2; /*!< bit: 8.. 9 Comparator x Event Input */
- uint16_t :6; /*!< bit: 10..15 Reserved */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t COMPEO0:1; /*!< bit: 0 Comparator 0 Event Output Enable */
+ uint16_t COMPEO1:1; /*!< bit: 1 Comparator 1 Event Output Enable */
+ uint16_t :2; /*!< bit: 2.. 3 Reserved */
+ uint16_t WINEO0:1; /*!< bit: 4 Window 0 Event Output Enable */
+ uint16_t :3; /*!< bit: 5.. 7 Reserved */
+ uint16_t COMPEI0:1; /*!< bit: 8 Comparator 0 Event Input */
+ uint16_t COMPEI1:1; /*!< bit: 9 Comparator 1 Event Input */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t COMPEO:2; /*!< bit: 0.. 1 Comparator x Event Output Enable */
+ uint16_t :2; /*!< bit: 2.. 3 Reserved */
+ uint16_t WINEO:1; /*!< bit: 4 Window x Event Output Enable */
+ uint16_t :3; /*!< bit: 5.. 7 Reserved */
+ uint16_t COMPEI:2; /*!< bit: 8.. 9 Comparator x Event Input */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
} AC_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -164,20 +164,20 @@ typedef union {
/* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */
- uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */
- uint8_t :2; /*!< bit: 2.. 3 Reserved */
- uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */
- uint8_t :3; /*!< bit: 5.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */
- uint8_t :2; /*!< bit: 2.. 3 Reserved */
- uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */
- uint8_t :3; /*!< bit: 5.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */
+ uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} AC_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -201,20 +201,20 @@ typedef union {
/* -------- AC_INTENSET : (AC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */
- uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */
- uint8_t :2; /*!< bit: 2.. 3 Reserved */
- uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */
- uint8_t :3; /*!< bit: 5.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */
- uint8_t :2; /*!< bit: 2.. 3 Reserved */
- uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */
- uint8_t :3; /*!< bit: 5.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */
+ uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} AC_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -238,20 +238,20 @@ typedef union {
/* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */
- uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */
- uint8_t :2; /*!< bit: 2.. 3 Reserved */
- uint8_t WIN0:1; /*!< bit: 4 Window 0 */
- uint8_t :3; /*!< bit: 5.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x */
- uint8_t :2; /*!< bit: 2.. 3 Reserved */
- uint8_t WIN:1; /*!< bit: 4 Window x */
- uint8_t :3; /*!< bit: 5.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */
+ uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t WIN0:1; /*!< bit: 4 Window 0 */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t WIN:1; /*!< bit: 4 Window x */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} AC_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -275,18 +275,18 @@ typedef union {
/* -------- AC_STATUSA : (AC Offset: 0x08) (R/ 8) Status A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */
- uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */
- uint8_t :2; /*!< bit: 2.. 3 Reserved */
- uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */
+ uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} AC_STATUSA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -314,17 +314,17 @@ typedef union {
/* -------- AC_STATUSB : (AC Offset: 0x09) (R/ 8) Status B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t READY0:1; /*!< bit: 0 Comparator 0 Ready */
- uint8_t READY1:1; /*!< bit: 1 Comparator 1 Ready */
- uint8_t :5; /*!< bit: 2.. 6 Reserved */
- uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t READY:2; /*!< bit: 0.. 1 Comparator x Ready */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t READY0:1; /*!< bit: 0 Comparator 0 Ready */
+ uint8_t READY1:1; /*!< bit: 1 Comparator 1 Ready */
+ uint8_t :5; /*!< bit: 2.. 6 Reserved */
+ uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t READY:2; /*!< bit: 0.. 1 Comparator x Ready */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} AC_STATUSB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -345,18 +345,18 @@ typedef union {
/* -------- AC_STATUSC : (AC Offset: 0x0A) (R/ 8) Status C -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */
- uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */
- uint8_t :2; /*!< bit: 2.. 3 Reserved */
- uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */
+ uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} AC_STATUSC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -384,12 +384,12 @@ typedef union {
/* -------- AC_WINCTRL : (AC Offset: 0x0C) (R/W 8) Window Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t WEN0:1; /*!< bit: 0 Window 0 Mode Enable */
- uint8_t WINTSEL0:2; /*!< bit: 1.. 2 Window 0 Interrupt Selection */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t WEN0:1; /*!< bit: 0 Window 0 Mode Enable */
+ uint8_t WINTSEL0:2; /*!< bit: 1.. 2 Window 0 Interrupt Selection */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} AC_WINCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -414,26 +414,26 @@ typedef union {
/* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t ENABLE:1; /*!< bit: 0 Enable */
- uint32_t SINGLE:1; /*!< bit: 1 Single-Shot Mode */
- uint32_t SPEED:2; /*!< bit: 2.. 3 Speed Selection */
- uint32_t :1; /*!< bit: 4 Reserved */
- uint32_t INTSEL:2; /*!< bit: 5.. 6 Interrupt Selection */
- uint32_t :1; /*!< bit: 7 Reserved */
- uint32_t MUXNEG:3; /*!< bit: 8..10 Negative Input Mux Selection */
- uint32_t :1; /*!< bit: 11 Reserved */
- uint32_t MUXPOS:2; /*!< bit: 12..13 Positive Input Mux Selection */
- uint32_t :1; /*!< bit: 14 Reserved */
- uint32_t SWAP:1; /*!< bit: 15 Swap Inputs and Invert */
- uint32_t OUT:2; /*!< bit: 16..17 Output */
- uint32_t :1; /*!< bit: 18 Reserved */
- uint32_t HYST:1; /*!< bit: 19 Hysteresis Enable */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t FLEN:3; /*!< bit: 24..26 Filter Length */
- uint32_t :5; /*!< bit: 27..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t ENABLE:1; /*!< bit: 0 Enable */
+ uint32_t SINGLE:1; /*!< bit: 1 Single-Shot Mode */
+ uint32_t SPEED:2; /*!< bit: 2.. 3 Speed Selection */
+ uint32_t :1; /*!< bit: 4 Reserved */
+ uint32_t INTSEL:2; /*!< bit: 5.. 6 Interrupt Selection */
+ uint32_t :1; /*!< bit: 7 Reserved */
+ uint32_t MUXNEG:3; /*!< bit: 8..10 Negative Input Mux Selection */
+ uint32_t :1; /*!< bit: 11 Reserved */
+ uint32_t MUXPOS:2; /*!< bit: 12..13 Positive Input Mux Selection */
+ uint32_t :1; /*!< bit: 14 Reserved */
+ uint32_t SWAP:1; /*!< bit: 15 Swap Inputs and Invert */
+ uint32_t OUT:2; /*!< bit: 16..17 Output */
+ uint32_t :1; /*!< bit: 18 Reserved */
+ uint32_t HYST:1; /*!< bit: 19 Hysteresis Enable */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t FLEN:3; /*!< bit: 24..26 Filter Length */
+ uint32_t :5; /*!< bit: 27..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} AC_COMPCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -519,11 +519,11 @@ typedef union {
/* -------- AC_SCALER : (AC Offset: 0x20) (R/W 8) Scaler n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t VALUE:6; /*!< bit: 0.. 5 Scaler Value */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t VALUE:6; /*!< bit: 0.. 5 Scaler Value */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} AC_SCALER_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -538,22 +538,22 @@ typedef union {
/** \brief AC hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO AC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
- __O AC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B */
- __IO AC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 16) Event Control */
- __IO AC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */
- __IO AC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */
- __IO AC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */
- RoReg8 Reserved1[0x1];
- __I AC_STATUSA_Type STATUSA; /**< \brief Offset: 0x08 (R/ 8) Status A */
- __I AC_STATUSB_Type STATUSB; /**< \brief Offset: 0x09 (R/ 8) Status B */
- __I AC_STATUSC_Type STATUSC; /**< \brief Offset: 0x0A (R/ 8) Status C */
- RoReg8 Reserved2[0x1];
- __IO AC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x0C (R/W 8) Window Control */
- RoReg8 Reserved3[0x3];
- __IO AC_COMPCTRL_Type COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */
- RoReg8 Reserved4[0x8];
- __IO AC_SCALER_Type SCALER[2]; /**< \brief Offset: 0x20 (R/W 8) Scaler n */
+ __IO AC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
+ __O AC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B */
+ __IO AC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 16) Event Control */
+ __IO AC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */
+ __IO AC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */
+ __IO AC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */
+ RoReg8 Reserved1[0x1];
+ __I AC_STATUSA_Type STATUSA; /**< \brief Offset: 0x08 (R/ 8) Status A */
+ __I AC_STATUSB_Type STATUSB; /**< \brief Offset: 0x09 (R/ 8) Status B */
+ __I AC_STATUSC_Type STATUSC; /**< \brief Offset: 0x0A (R/ 8) Status C */
+ RoReg8 Reserved2[0x1];
+ __IO AC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x0C (R/W 8) Window Control */
+ RoReg8 Reserved3[0x3];
+ __IO AC_COMPCTRL_Type COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */
+ RoReg8 Reserved4[0x8];
+ __IO AC_SCALER_Type SCALER[2]; /**< \brief Offset: 0x20 (R/W 8) Scaler n */
} Ac;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_adc.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_adc.h
index fbd0bdba1b1..65ea3e1aced 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_adc.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_adc.h
@@ -59,13 +59,13 @@
/* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 8) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t SWRST:1; /*!< bit: 0 Software Reset */
- uint8_t ENABLE:1; /*!< bit: 1 Enable */
- uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable */
+ uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} ADC_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -83,12 +83,12 @@ typedef union {
/* -------- ADC_REFCTRL : (ADC Offset: 0x01) (R/W 8) Reference Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t REFSEL:4; /*!< bit: 0.. 3 Reference Selection */
- uint8_t :3; /*!< bit: 4.. 6 Reserved */
- uint8_t REFCOMP:1; /*!< bit: 7 Reference Buffer Offset Compensation Enable */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t REFSEL:4; /*!< bit: 0.. 3 Reference Selection */
+ uint8_t :3; /*!< bit: 4.. 6 Reserved */
+ uint8_t REFCOMP:1; /*!< bit: 7 Reference Buffer Offset Compensation Enable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} ADC_REFCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -115,12 +115,12 @@ typedef union {
/* -------- ADC_AVGCTRL : (ADC Offset: 0x02) (R/W 8) Average Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t SAMPLENUM:4; /*!< bit: 0.. 3 Number of Samples to be Collected */
- uint8_t ADJRES:3; /*!< bit: 4.. 6 Adjusting Result / Division Coefficient */
- uint8_t :1; /*!< bit: 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t SAMPLENUM:4; /*!< bit: 0.. 3 Number of Samples to be Collected */
+ uint8_t ADJRES:3; /*!< bit: 4.. 6 Adjusting Result / Division Coefficient */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} ADC_AVGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -160,11 +160,11 @@ typedef union {
/* -------- ADC_SAMPCTRL : (ADC Offset: 0x03) (R/W 8) Sampling Time Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t SAMPLEN:6; /*!< bit: 0.. 5 Sampling Time Length */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t SAMPLEN:6; /*!< bit: 0.. 5 Sampling Time Length */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} ADC_SAMPCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -179,17 +179,17 @@ typedef union {
/* -------- ADC_CTRLB : (ADC Offset: 0x04) (R/W 16) Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t DIFFMODE:1; /*!< bit: 0 Differential Mode */
- uint16_t LEFTADJ:1; /*!< bit: 1 Left-Adjusted Result */
- uint16_t FREERUN:1; /*!< bit: 2 Free Running Mode */
- uint16_t CORREN:1; /*!< bit: 3 Digital Correction Logic Enabled */
- uint16_t RESSEL:2; /*!< bit: 4.. 5 Conversion Result Resolution */
- uint16_t :2; /*!< bit: 6.. 7 Reserved */
- uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler Configuration */
- uint16_t :5; /*!< bit: 11..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t DIFFMODE:1; /*!< bit: 0 Differential Mode */
+ uint16_t LEFTADJ:1; /*!< bit: 1 Left-Adjusted Result */
+ uint16_t FREERUN:1; /*!< bit: 2 Free Running Mode */
+ uint16_t CORREN:1; /*!< bit: 3 Digital Correction Logic Enabled */
+ uint16_t RESSEL:2; /*!< bit: 4.. 5 Conversion Result Resolution */
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler Configuration */
+ uint16_t :5; /*!< bit: 11..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} ADC_CTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -239,11 +239,11 @@ typedef union {
/* -------- ADC_WINCTRL : (ADC Offset: 0x08) (R/W 8) Window Monitor Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t WINMODE:3; /*!< bit: 0.. 2 Window Monitor Mode */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t WINMODE:3; /*!< bit: 0.. 2 Window Monitor Mode */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} ADC_WINCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -268,12 +268,12 @@ typedef union {
/* -------- ADC_SWTRIG : (ADC Offset: 0x0C) (R/W 8) Software Trigger -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t FLUSH:1; /*!< bit: 0 ADC Conversion Flush */
- uint8_t START:1; /*!< bit: 1 ADC Start Conversion */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t FLUSH:1; /*!< bit: 0 ADC Conversion Flush */
+ uint8_t START:1; /*!< bit: 1 ADC Start Conversion */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} ADC_SWTRIG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -289,17 +289,17 @@ typedef union {
/* -------- ADC_INPUTCTRL : (ADC Offset: 0x10) (R/W 32) Input Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t MUXPOS:5; /*!< bit: 0.. 4 Positive Mux Input Selection */
- uint32_t :3; /*!< bit: 5.. 7 Reserved */
- uint32_t MUXNEG:5; /*!< bit: 8..12 Negative Mux Input Selection */
- uint32_t :3; /*!< bit: 13..15 Reserved */
- uint32_t INPUTSCAN:4; /*!< bit: 16..19 Number of Input Channels Included in Scan */
- uint32_t INPUTOFFSET:4; /*!< bit: 20..23 Positive Mux Setting Offset */
- uint32_t GAIN:4; /*!< bit: 24..27 Gain Factor Selection */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t MUXPOS:5; /*!< bit: 0.. 4 Positive Mux Input Selection */
+ uint32_t :3; /*!< bit: 5.. 7 Reserved */
+ uint32_t MUXNEG:5; /*!< bit: 8..12 Negative Mux Input Selection */
+ uint32_t :3; /*!< bit: 13..15 Reserved */
+ uint32_t INPUTSCAN:4; /*!< bit: 16..19 Number of Input Channels Included in Scan */
+ uint32_t INPUTOFFSET:4; /*!< bit: 20..23 Positive Mux Setting Offset */
+ uint32_t GAIN:4; /*!< bit: 24..27 Gain Factor Selection */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} ADC_INPUTCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -408,15 +408,15 @@ typedef union {
/* -------- ADC_EVCTRL : (ADC Offset: 0x14) (R/W 8) Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event In */
- uint8_t SYNCEI:1; /*!< bit: 1 Synchronization Event In */
- uint8_t :2; /*!< bit: 2.. 3 Reserved */
- uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */
- uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event In */
+ uint8_t SYNCEI:1; /*!< bit: 1 Synchronization Event In */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */
+ uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} ADC_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -436,14 +436,14 @@ typedef union {
/* -------- ADC_INTENCLR : (ADC Offset: 0x16) (R/W 8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */
- uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */
- uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */
- uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
- uint8_t :4; /*!< bit: 4.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */
+ uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */
+ uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */
+ uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} ADC_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -463,14 +463,14 @@ typedef union {
/* -------- ADC_INTENSET : (ADC Offset: 0x17) (R/W 8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */
- uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */
- uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */
- uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
- uint8_t :4; /*!< bit: 4.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */
+ uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */
+ uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */
+ uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} ADC_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -490,14 +490,14 @@ typedef union {
/* -------- ADC_INTFLAG : (ADC Offset: 0x18) (R/W 8) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t RESRDY:1; /*!< bit: 0 Result Ready */
- uint8_t OVERRUN:1; /*!< bit: 1 Overrun */
- uint8_t WINMON:1; /*!< bit: 2 Window Monitor */
- uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */
- uint8_t :4; /*!< bit: 4.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t RESRDY:1; /*!< bit: 0 Result Ready */
+ uint8_t OVERRUN:1; /*!< bit: 1 Overrun */
+ uint8_t WINMON:1; /*!< bit: 2 Window Monitor */
+ uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} ADC_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -517,11 +517,11 @@ typedef union {
/* -------- ADC_STATUS : (ADC Offset: 0x19) (R/ 8) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t :7; /*!< bit: 0.. 6 Reserved */
- uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t :7; /*!< bit: 0.. 6 Reserved */
+ uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} ADC_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -535,10 +535,10 @@ typedef union {
/* -------- ADC_RESULT : (ADC Offset: 0x1A) (R/ 16) Result -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t RESULT:16; /*!< bit: 0..15 Result Conversion Value */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t RESULT:16; /*!< bit: 0..15 Result Conversion Value */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} ADC_RESULT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -553,10 +553,10 @@ typedef union {
/* -------- ADC_WINLT : (ADC Offset: 0x1C) (R/W 16) Window Monitor Lower Threshold -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t WINLT:16; /*!< bit: 0..15 Window Lower Threshold */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t WINLT:16; /*!< bit: 0..15 Window Lower Threshold */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} ADC_WINLT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -571,10 +571,10 @@ typedef union {
/* -------- ADC_WINUT : (ADC Offset: 0x20) (R/W 16) Window Monitor Upper Threshold -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t WINUT:16; /*!< bit: 0..15 Window Upper Threshold */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t WINUT:16; /*!< bit: 0..15 Window Upper Threshold */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} ADC_WINUT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -589,11 +589,11 @@ typedef union {
/* -------- ADC_GAINCORR : (ADC Offset: 0x24) (R/W 16) Gain Correction -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t GAINCORR:12; /*!< bit: 0..11 Gain Correction Value */
- uint16_t :4; /*!< bit: 12..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t GAINCORR:12; /*!< bit: 0..11 Gain Correction Value */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} ADC_GAINCORR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -608,11 +608,11 @@ typedef union {
/* -------- ADC_OFFSETCORR : (ADC Offset: 0x26) (R/W 16) Offset Correction -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t OFFSETCORR:12; /*!< bit: 0..11 Offset Correction Value */
- uint16_t :4; /*!< bit: 12..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t OFFSETCORR:12; /*!< bit: 0..11 Offset Correction Value */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} ADC_OFFSETCORR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -627,12 +627,12 @@ typedef union {
/* -------- ADC_CALIB : (ADC Offset: 0x28) (R/W 16) Calibration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t LINEARITY_CAL:8; /*!< bit: 0.. 7 Linearity Calibration Value */
- uint16_t BIAS_CAL:3; /*!< bit: 8..10 Bias Calibration Value */
- uint16_t :5; /*!< bit: 11..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t LINEARITY_CAL:8; /*!< bit: 0.. 7 Linearity Calibration Value */
+ uint16_t BIAS_CAL:3; /*!< bit: 8..10 Bias Calibration Value */
+ uint16_t :5; /*!< bit: 11..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} ADC_CALIB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -650,11 +650,11 @@ typedef union {
/* -------- ADC_DBGCTRL : (ADC Offset: 0x2A) (R/W 8) Debug Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} ADC_DBGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -668,32 +668,32 @@ typedef union {
/** \brief ADC hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO ADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
- __IO ADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x01 (R/W 8) Reference Control */
- __IO ADC_AVGCTRL_Type AVGCTRL; /**< \brief Offset: 0x02 (R/W 8) Average Control */
- __IO ADC_SAMPCTRL_Type SAMPCTRL; /**< \brief Offset: 0x03 (R/W 8) Sampling Time Control */
- __IO ADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 16) Control B */
- RoReg8 Reserved1[0x2];
- __IO ADC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x08 (R/W 8) Window Monitor Control */
- RoReg8 Reserved2[0x3];
- __IO ADC_SWTRIG_Type SWTRIG; /**< \brief Offset: 0x0C (R/W 8) Software Trigger */
- RoReg8 Reserved3[0x3];
- __IO ADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x10 (R/W 32) Input Control */
- __IO ADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x14 (R/W 8) Event Control */
- RoReg8 Reserved4[0x1];
- __IO ADC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x16 (R/W 8) Interrupt Enable Clear */
- __IO ADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x17 (R/W 8) Interrupt Enable Set */
- __IO ADC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) Interrupt Flag Status and Clear */
- __I ADC_STATUS_Type STATUS; /**< \brief Offset: 0x19 (R/ 8) Status */
- __I ADC_RESULT_Type RESULT; /**< \brief Offset: 0x1A (R/ 16) Result */
- __IO ADC_WINLT_Type WINLT; /**< \brief Offset: 0x1C (R/W 16) Window Monitor Lower Threshold */
- RoReg8 Reserved5[0x2];
- __IO ADC_WINUT_Type WINUT; /**< \brief Offset: 0x20 (R/W 16) Window Monitor Upper Threshold */
- RoReg8 Reserved6[0x2];
- __IO ADC_GAINCORR_Type GAINCORR; /**< \brief Offset: 0x24 (R/W 16) Gain Correction */
- __IO ADC_OFFSETCORR_Type OFFSETCORR; /**< \brief Offset: 0x26 (R/W 16) Offset Correction */
- __IO ADC_CALIB_Type CALIB; /**< \brief Offset: 0x28 (R/W 16) Calibration */
- __IO ADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x2A (R/W 8) Debug Control */
+ __IO ADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
+ __IO ADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x01 (R/W 8) Reference Control */
+ __IO ADC_AVGCTRL_Type AVGCTRL; /**< \brief Offset: 0x02 (R/W 8) Average Control */
+ __IO ADC_SAMPCTRL_Type SAMPCTRL; /**< \brief Offset: 0x03 (R/W 8) Sampling Time Control */
+ __IO ADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 16) Control B */
+ RoReg8 Reserved1[0x2];
+ __IO ADC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x08 (R/W 8) Window Monitor Control */
+ RoReg8 Reserved2[0x3];
+ __IO ADC_SWTRIG_Type SWTRIG; /**< \brief Offset: 0x0C (R/W 8) Software Trigger */
+ RoReg8 Reserved3[0x3];
+ __IO ADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x10 (R/W 32) Input Control */
+ __IO ADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x14 (R/W 8) Event Control */
+ RoReg8 Reserved4[0x1];
+ __IO ADC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x16 (R/W 8) Interrupt Enable Clear */
+ __IO ADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x17 (R/W 8) Interrupt Enable Set */
+ __IO ADC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) Interrupt Flag Status and Clear */
+ __I ADC_STATUS_Type STATUS; /**< \brief Offset: 0x19 (R/ 8) Status */
+ __I ADC_RESULT_Type RESULT; /**< \brief Offset: 0x1A (R/ 16) Result */
+ __IO ADC_WINLT_Type WINLT; /**< \brief Offset: 0x1C (R/W 16) Window Monitor Lower Threshold */
+ RoReg8 Reserved5[0x2];
+ __IO ADC_WINUT_Type WINUT; /**< \brief Offset: 0x20 (R/W 16) Window Monitor Upper Threshold */
+ RoReg8 Reserved6[0x2];
+ __IO ADC_GAINCORR_Type GAINCORR; /**< \brief Offset: 0x24 (R/W 16) Gain Correction */
+ __IO ADC_OFFSETCORR_Type OFFSETCORR; /**< \brief Offset: 0x26 (R/W 16) Offset Correction */
+ __IO ADC_CALIB_Type CALIB; /**< \brief Offset: 0x28 (R/W 16) Calibration */
+ __IO ADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x2A (R/W 8) Debug Control */
} Adc;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_dac.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_dac.h
index e1f64354117..968f00463e2 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_dac.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_dac.h
@@ -59,13 +59,13 @@
/* -------- DAC_CTRLA : (DAC Offset: 0x0) (R/W 8) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t SWRST:1; /*!< bit: 0 Software Reset */
- uint8_t ENABLE:1; /*!< bit: 1 Enable */
- uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable */
+ uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} DAC_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -83,16 +83,16 @@ typedef union {
/* -------- DAC_CTRLB : (DAC Offset: 0x1) (R/W 8) Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t EOEN:1; /*!< bit: 0 External Output Enable */
- uint8_t IOEN:1; /*!< bit: 1 Internal Output Enable */
- uint8_t LEFTADJ:1; /*!< bit: 2 Left Adjusted Data */
- uint8_t VPD:1; /*!< bit: 3 Voltage Pump Disable */
- uint8_t BDWP:1; /*!< bit: 4 Bypass DATABUF Write Protection */
- uint8_t :1; /*!< bit: 5 Reserved */
- uint8_t REFSEL:2; /*!< bit: 6.. 7 Reference Selection */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t EOEN:1; /*!< bit: 0 External Output Enable */
+ uint8_t IOEN:1; /*!< bit: 1 Internal Output Enable */
+ uint8_t LEFTADJ:1; /*!< bit: 2 Left Adjusted Data */
+ uint8_t VPD:1; /*!< bit: 3 Voltage Pump Disable */
+ uint8_t BDWP:1; /*!< bit: 4 Bypass DATABUF Write Protection */
+ uint8_t :1; /*!< bit: 5 Reserved */
+ uint8_t REFSEL:2; /*!< bit: 6.. 7 Reference Selection */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} DAC_CTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -123,12 +123,12 @@ typedef union {
/* -------- DAC_EVCTRL : (DAC Offset: 0x2) (R/W 8) Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event Input */
- uint8_t EMPTYEO:1; /*!< bit: 1 Data Buffer Empty Event Output */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event Input */
+ uint8_t EMPTYEO:1; /*!< bit: 1 Data Buffer Empty Event Output */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} DAC_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -144,13 +144,13 @@ typedef union {
/* -------- DAC_INTENCLR : (DAC Offset: 0x4) (R/W 8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */
- uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */
- uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready Interrupt Enable */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */
+ uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */
+ uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready Interrupt Enable */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} DAC_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -168,13 +168,13 @@ typedef union {
/* -------- DAC_INTENSET : (DAC Offset: 0x5) (R/W 8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */
- uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */
- uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready Interrupt Enable */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */
+ uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */
+ uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready Interrupt Enable */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} DAC_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -192,13 +192,13 @@ typedef union {
/* -------- DAC_INTFLAG : (DAC Offset: 0x6) (R/W 8) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t UNDERRUN:1; /*!< bit: 0 Underrun */
- uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty */
- uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t UNDERRUN:1; /*!< bit: 0 Underrun */
+ uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty */
+ uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} DAC_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -216,11 +216,11 @@ typedef union {
/* -------- DAC_STATUS : (DAC Offset: 0x7) (R/ 8) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t :7; /*!< bit: 0.. 6 Reserved */
- uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy Status */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t :7; /*!< bit: 0.. 6 Reserved */
+ uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy Status */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} DAC_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -234,10 +234,10 @@ typedef union {
/* -------- DAC_DATA : (DAC Offset: 0x8) (R/W 16) Data -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t DATA:16; /*!< bit: 0..15 Data value to be converted */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t DATA:16; /*!< bit: 0..15 Data value to be converted */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} DAC_DATA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -252,10 +252,10 @@ typedef union {
/* -------- DAC_DATABUF : (DAC Offset: 0xC) (R/W 16) Data Buffer -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t DATABUF:16; /*!< bit: 0..15 Data Buffer */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t DATABUF:16; /*!< bit: 0..15 Data Buffer */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} DAC_DATABUF_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -270,17 +270,17 @@ typedef union {
/** \brief DAC hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO DAC_CTRLA_Type CTRLA; /**< \brief Offset: 0x0 (R/W 8) Control A */
- __IO DAC_CTRLB_Type CTRLB; /**< \brief Offset: 0x1 (R/W 8) Control B */
- __IO DAC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x2 (R/W 8) Event Control */
- RoReg8 Reserved1[0x1];
- __IO DAC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */
- __IO DAC_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */
- __IO DAC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */
- __I DAC_STATUS_Type STATUS; /**< \brief Offset: 0x7 (R/ 8) Status */
- __IO DAC_DATA_Type DATA; /**< \brief Offset: 0x8 (R/W 16) Data */
- RoReg8 Reserved2[0x2];
- __IO DAC_DATABUF_Type DATABUF; /**< \brief Offset: 0xC (R/W 16) Data Buffer */
+ __IO DAC_CTRLA_Type CTRLA; /**< \brief Offset: 0x0 (R/W 8) Control A */
+ __IO DAC_CTRLB_Type CTRLB; /**< \brief Offset: 0x1 (R/W 8) Control B */
+ __IO DAC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x2 (R/W 8) Event Control */
+ RoReg8 Reserved1[0x1];
+ __IO DAC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */
+ __IO DAC_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */
+ __IO DAC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */
+ __I DAC_STATUS_Type STATUS; /**< \brief Offset: 0x7 (R/ 8) Status */
+ __IO DAC_DATA_Type DATA; /**< \brief Offset: 0x8 (R/W 16) Data */
+ RoReg8 Reserved2[0x2];
+ __IO DAC_DATABUF_Type DATABUF; /**< \brief Offset: 0xC (R/W 16) Data Buffer */
} Dac;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_dmac.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_dmac.h
index 8ce0656b94a..7f187915a09 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_dmac.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_dmac.h
@@ -59,23 +59,23 @@
/* -------- DMAC_CTRL : (DMAC Offset: 0x00) (R/W 16) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t SWRST:1; /*!< bit: 0 Software Reset */
- uint16_t DMAENABLE:1; /*!< bit: 1 DMA Enable */
- uint16_t CRCENABLE:1; /*!< bit: 2 CRC Enable */
- uint16_t :5; /*!< bit: 3.. 7 Reserved */
- uint16_t LVLEN0:1; /*!< bit: 8 Priority Level 0 Enable */
- uint16_t LVLEN1:1; /*!< bit: 9 Priority Level 1 Enable */
- uint16_t LVLEN2:1; /*!< bit: 10 Priority Level 2 Enable */
- uint16_t LVLEN3:1; /*!< bit: 11 Priority Level 3 Enable */
- uint16_t :4; /*!< bit: 12..15 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint16_t :8; /*!< bit: 0.. 7 Reserved */
- uint16_t LVLEN:4; /*!< bit: 8..11 Priority Level x Enable */
- uint16_t :4; /*!< bit: 12..15 Reserved */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint16_t DMAENABLE:1; /*!< bit: 1 DMA Enable */
+ uint16_t CRCENABLE:1; /*!< bit: 2 CRC Enable */
+ uint16_t :5; /*!< bit: 3.. 7 Reserved */
+ uint16_t LVLEN0:1; /*!< bit: 8 Priority Level 0 Enable */
+ uint16_t LVLEN1:1; /*!< bit: 9 Priority Level 1 Enable */
+ uint16_t LVLEN2:1; /*!< bit: 10 Priority Level 2 Enable */
+ uint16_t LVLEN3:1; /*!< bit: 11 Priority Level 3 Enable */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t :8; /*!< bit: 0.. 7 Reserved */
+ uint16_t LVLEN:4; /*!< bit: 8..11 Priority Level x Enable */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
} DMAC_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -104,14 +104,14 @@ typedef union {
/* -------- DMAC_CRCCTRL : (DMAC Offset: 0x02) (R/W 16) CRC Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t CRCBEATSIZE:2; /*!< bit: 0.. 1 CRC Beat Size */
- uint16_t CRCPOLY:2; /*!< bit: 2.. 3 CRC Polynomial Type */
- uint16_t :4; /*!< bit: 4.. 7 Reserved */
- uint16_t CRCSRC:6; /*!< bit: 8..13 CRC Input Source */
- uint16_t :2; /*!< bit: 14..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t CRCBEATSIZE:2; /*!< bit: 0.. 1 CRC Beat Size */
+ uint16_t CRCPOLY:2; /*!< bit: 2.. 3 CRC Polynomial Type */
+ uint16_t :4; /*!< bit: 4.. 7 Reserved */
+ uint16_t CRCSRC:6; /*!< bit: 8..13 CRC Input Source */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} DMAC_CRCCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -146,10 +146,10 @@ typedef union {
/* -------- DMAC_CRCDATAIN : (DMAC Offset: 0x04) (R/W 32) CRC Data Input -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t CRCDATAIN:32; /*!< bit: 0..31 CRC Data Input */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t CRCDATAIN:32; /*!< bit: 0..31 CRC Data Input */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DMAC_CRCDATAIN_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -164,10 +164,10 @@ typedef union {
/* -------- DMAC_CRCCHKSUM : (DMAC Offset: 0x08) (R/W 32) CRC Checksum -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t CRCCHKSUM:32; /*!< bit: 0..31 CRC Checksum */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t CRCCHKSUM:32; /*!< bit: 0..31 CRC Checksum */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DMAC_CRCCHKSUM_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -182,12 +182,12 @@ typedef union {
/* -------- DMAC_CRCSTATUS : (DMAC Offset: 0x0C) (R/W 8) CRC Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t CRCBUSY:1; /*!< bit: 0 CRC Module Busy */
- uint8_t CRCZERO:1; /*!< bit: 1 CRC Zero */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t CRCBUSY:1; /*!< bit: 0 CRC Module Busy */
+ uint8_t CRCZERO:1; /*!< bit: 1 CRC Zero */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} DMAC_CRCSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -203,11 +203,11 @@ typedef union {
/* -------- DMAC_DBGCTRL : (DMAC Offset: 0x0D) (R/W 8) Debug Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} DMAC_DBGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -221,13 +221,13 @@ typedef union {
/* -------- DMAC_QOSCTRL : (DMAC Offset: 0x0E) (R/W 8) QOS Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t WRBQOS:2; /*!< bit: 0.. 1 Write-Back Quality of Service */
- uint8_t FQOS:2; /*!< bit: 2.. 3 Fetch Quality of Service */
- uint8_t DQOS:2; /*!< bit: 4.. 5 Data Transfer Quality of Service */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t WRBQOS:2; /*!< bit: 0.. 1 Write-Back Quality of Service */
+ uint8_t FQOS:2; /*!< bit: 2.. 3 Fetch Quality of Service */
+ uint8_t DQOS:2; /*!< bit: 4.. 5 Data Transfer Quality of Service */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} DMAC_QOSCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -272,26 +272,26 @@ typedef union {
/* -------- DMAC_SWTRIGCTRL : (DMAC Offset: 0x10) (R/W 32) Software Trigger Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SWTRIG0:1; /*!< bit: 0 Channel 0 Software Trigger */
- uint32_t SWTRIG1:1; /*!< bit: 1 Channel 1 Software Trigger */
- uint32_t SWTRIG2:1; /*!< bit: 2 Channel 2 Software Trigger */
- uint32_t SWTRIG3:1; /*!< bit: 3 Channel 3 Software Trigger */
- uint32_t SWTRIG4:1; /*!< bit: 4 Channel 4 Software Trigger */
- uint32_t SWTRIG5:1; /*!< bit: 5 Channel 5 Software Trigger */
- uint32_t SWTRIG6:1; /*!< bit: 6 Channel 6 Software Trigger */
- uint32_t SWTRIG7:1; /*!< bit: 7 Channel 7 Software Trigger */
- uint32_t SWTRIG8:1; /*!< bit: 8 Channel 8 Software Trigger */
- uint32_t SWTRIG9:1; /*!< bit: 9 Channel 9 Software Trigger */
- uint32_t SWTRIG10:1; /*!< bit: 10 Channel 10 Software Trigger */
- uint32_t SWTRIG11:1; /*!< bit: 11 Channel 11 Software Trigger */
- uint32_t :20; /*!< bit: 12..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t SWTRIG:12; /*!< bit: 0..11 Channel x Software Trigger */
- uint32_t :20; /*!< bit: 12..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SWTRIG0:1; /*!< bit: 0 Channel 0 Software Trigger */
+ uint32_t SWTRIG1:1; /*!< bit: 1 Channel 1 Software Trigger */
+ uint32_t SWTRIG2:1; /*!< bit: 2 Channel 2 Software Trigger */
+ uint32_t SWTRIG3:1; /*!< bit: 3 Channel 3 Software Trigger */
+ uint32_t SWTRIG4:1; /*!< bit: 4 Channel 4 Software Trigger */
+ uint32_t SWTRIG5:1; /*!< bit: 5 Channel 5 Software Trigger */
+ uint32_t SWTRIG6:1; /*!< bit: 6 Channel 6 Software Trigger */
+ uint32_t SWTRIG7:1; /*!< bit: 7 Channel 7 Software Trigger */
+ uint32_t SWTRIG8:1; /*!< bit: 8 Channel 8 Software Trigger */
+ uint32_t SWTRIG9:1; /*!< bit: 9 Channel 9 Software Trigger */
+ uint32_t SWTRIG10:1; /*!< bit: 10 Channel 10 Software Trigger */
+ uint32_t SWTRIG11:1; /*!< bit: 11 Channel 11 Software Trigger */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t SWTRIG:12; /*!< bit: 0..11 Channel x Software Trigger */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} DMAC_SWTRIGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -330,21 +330,21 @@ typedef union {
/* -------- DMAC_PRICTRL0 : (DMAC Offset: 0x14) (R/W 32) Priority Control 0 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t LVLPRI0:4; /*!< bit: 0.. 3 Level 0 Channel Priority Number */
- uint32_t :3; /*!< bit: 4.. 6 Reserved */
- uint32_t RRLVLEN0:1; /*!< bit: 7 Level 0 Round-Robin Scheduling Enable */
- uint32_t LVLPRI1:4; /*!< bit: 8..11 Level 1 Channel Priority Number */
- uint32_t :3; /*!< bit: 12..14 Reserved */
- uint32_t RRLVLEN1:1; /*!< bit: 15 Level 1 Round-Robin Scheduling Enable */
- uint32_t LVLPRI2:4; /*!< bit: 16..19 Level 2 Channel Priority Number */
- uint32_t :3; /*!< bit: 20..22 Reserved */
- uint32_t RRLVLEN2:1; /*!< bit: 23 Level 2 Round-Robin Scheduling Enable */
- uint32_t LVLPRI3:4; /*!< bit: 24..27 Level 3 Channel Priority Number */
- uint32_t :3; /*!< bit: 28..30 Reserved */
- uint32_t RRLVLEN3:1; /*!< bit: 31 Level 3 Round-Robin Scheduling Enable */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t LVLPRI0:4; /*!< bit: 0.. 3 Level 0 Channel Priority Number */
+ uint32_t :3; /*!< bit: 4.. 6 Reserved */
+ uint32_t RRLVLEN0:1; /*!< bit: 7 Level 0 Round-Robin Scheduling Enable */
+ uint32_t LVLPRI1:4; /*!< bit: 8..11 Level 1 Channel Priority Number */
+ uint32_t :3; /*!< bit: 12..14 Reserved */
+ uint32_t RRLVLEN1:1; /*!< bit: 15 Level 1 Round-Robin Scheduling Enable */
+ uint32_t LVLPRI2:4; /*!< bit: 16..19 Level 2 Channel Priority Number */
+ uint32_t :3; /*!< bit: 20..22 Reserved */
+ uint32_t RRLVLEN2:1; /*!< bit: 23 Level 2 Round-Robin Scheduling Enable */
+ uint32_t LVLPRI3:4; /*!< bit: 24..27 Level 3 Channel Priority Number */
+ uint32_t :3; /*!< bit: 28..30 Reserved */
+ uint32_t RRLVLEN3:1; /*!< bit: 31 Level 3 Round-Robin Scheduling Enable */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DMAC_PRICTRL0_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -376,18 +376,18 @@ typedef union {
/* -------- DMAC_INTPEND : (DMAC Offset: 0x20) (R/W 16) Interrupt Pending -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t ID:4; /*!< bit: 0.. 3 Channel ID */
- uint16_t :4; /*!< bit: 4.. 7 Reserved */
- uint16_t TERR:1; /*!< bit: 8 Transfer Error */
- uint16_t TCMPL:1; /*!< bit: 9 Transfer Complete */
- uint16_t SUSP:1; /*!< bit: 10 Channel Suspend */
- uint16_t :2; /*!< bit: 11..12 Reserved */
- uint16_t FERR:1; /*!< bit: 13 Fetch Error */
- uint16_t BUSY:1; /*!< bit: 14 Busy */
- uint16_t PEND:1; /*!< bit: 15 Pending */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t ID:4; /*!< bit: 0.. 3 Channel ID */
+ uint16_t :4; /*!< bit: 4.. 7 Reserved */
+ uint16_t TERR:1; /*!< bit: 8 Transfer Error */
+ uint16_t TCMPL:1; /*!< bit: 9 Transfer Complete */
+ uint16_t SUSP:1; /*!< bit: 10 Channel Suspend */
+ uint16_t :2; /*!< bit: 11..12 Reserved */
+ uint16_t FERR:1; /*!< bit: 13 Fetch Error */
+ uint16_t BUSY:1; /*!< bit: 14 Busy */
+ uint16_t PEND:1; /*!< bit: 15 Pending */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} DMAC_INTPEND_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -414,26 +414,26 @@ typedef union {
/* -------- DMAC_INTSTATUS : (DMAC Offset: 0x24) (R/ 32) Interrupt Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t CHINT0:1; /*!< bit: 0 Channel 0 Pending Interrupt */
- uint32_t CHINT1:1; /*!< bit: 1 Channel 1 Pending Interrupt */
- uint32_t CHINT2:1; /*!< bit: 2 Channel 2 Pending Interrupt */
- uint32_t CHINT3:1; /*!< bit: 3 Channel 3 Pending Interrupt */
- uint32_t CHINT4:1; /*!< bit: 4 Channel 4 Pending Interrupt */
- uint32_t CHINT5:1; /*!< bit: 5 Channel 5 Pending Interrupt */
- uint32_t CHINT6:1; /*!< bit: 6 Channel 6 Pending Interrupt */
- uint32_t CHINT7:1; /*!< bit: 7 Channel 7 Pending Interrupt */
- uint32_t CHINT8:1; /*!< bit: 8 Channel 8 Pending Interrupt */
- uint32_t CHINT9:1; /*!< bit: 9 Channel 9 Pending Interrupt */
- uint32_t CHINT10:1; /*!< bit: 10 Channel 10 Pending Interrupt */
- uint32_t CHINT11:1; /*!< bit: 11 Channel 11 Pending Interrupt */
- uint32_t :20; /*!< bit: 12..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t CHINT:12; /*!< bit: 0..11 Channel x Pending Interrupt */
- uint32_t :20; /*!< bit: 12..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t CHINT0:1; /*!< bit: 0 Channel 0 Pending Interrupt */
+ uint32_t CHINT1:1; /*!< bit: 1 Channel 1 Pending Interrupt */
+ uint32_t CHINT2:1; /*!< bit: 2 Channel 2 Pending Interrupt */
+ uint32_t CHINT3:1; /*!< bit: 3 Channel 3 Pending Interrupt */
+ uint32_t CHINT4:1; /*!< bit: 4 Channel 4 Pending Interrupt */
+ uint32_t CHINT5:1; /*!< bit: 5 Channel 5 Pending Interrupt */
+ uint32_t CHINT6:1; /*!< bit: 6 Channel 6 Pending Interrupt */
+ uint32_t CHINT7:1; /*!< bit: 7 Channel 7 Pending Interrupt */
+ uint32_t CHINT8:1; /*!< bit: 8 Channel 8 Pending Interrupt */
+ uint32_t CHINT9:1; /*!< bit: 9 Channel 9 Pending Interrupt */
+ uint32_t CHINT10:1; /*!< bit: 10 Channel 10 Pending Interrupt */
+ uint32_t CHINT11:1; /*!< bit: 11 Channel 11 Pending Interrupt */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t CHINT:12; /*!< bit: 0..11 Channel x Pending Interrupt */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} DMAC_INTSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -472,26 +472,26 @@ typedef union {
/* -------- DMAC_BUSYCH : (DMAC Offset: 0x28) (R/ 32) Busy Channels -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t BUSYCH0:1; /*!< bit: 0 Busy Channel 0 */
- uint32_t BUSYCH1:1; /*!< bit: 1 Busy Channel 1 */
- uint32_t BUSYCH2:1; /*!< bit: 2 Busy Channel 2 */
- uint32_t BUSYCH3:1; /*!< bit: 3 Busy Channel 3 */
- uint32_t BUSYCH4:1; /*!< bit: 4 Busy Channel 4 */
- uint32_t BUSYCH5:1; /*!< bit: 5 Busy Channel 5 */
- uint32_t BUSYCH6:1; /*!< bit: 6 Busy Channel 6 */
- uint32_t BUSYCH7:1; /*!< bit: 7 Busy Channel 7 */
- uint32_t BUSYCH8:1; /*!< bit: 8 Busy Channel 8 */
- uint32_t BUSYCH9:1; /*!< bit: 9 Busy Channel 9 */
- uint32_t BUSYCH10:1; /*!< bit: 10 Busy Channel 10 */
- uint32_t BUSYCH11:1; /*!< bit: 11 Busy Channel 11 */
- uint32_t :20; /*!< bit: 12..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t BUSYCH:12; /*!< bit: 0..11 Busy Channel x */
- uint32_t :20; /*!< bit: 12..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t BUSYCH0:1; /*!< bit: 0 Busy Channel 0 */
+ uint32_t BUSYCH1:1; /*!< bit: 1 Busy Channel 1 */
+ uint32_t BUSYCH2:1; /*!< bit: 2 Busy Channel 2 */
+ uint32_t BUSYCH3:1; /*!< bit: 3 Busy Channel 3 */
+ uint32_t BUSYCH4:1; /*!< bit: 4 Busy Channel 4 */
+ uint32_t BUSYCH5:1; /*!< bit: 5 Busy Channel 5 */
+ uint32_t BUSYCH6:1; /*!< bit: 6 Busy Channel 6 */
+ uint32_t BUSYCH7:1; /*!< bit: 7 Busy Channel 7 */
+ uint32_t BUSYCH8:1; /*!< bit: 8 Busy Channel 8 */
+ uint32_t BUSYCH9:1; /*!< bit: 9 Busy Channel 9 */
+ uint32_t BUSYCH10:1; /*!< bit: 10 Busy Channel 10 */
+ uint32_t BUSYCH11:1; /*!< bit: 11 Busy Channel 11 */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t BUSYCH:12; /*!< bit: 0..11 Busy Channel x */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} DMAC_BUSYCH_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -530,26 +530,26 @@ typedef union {
/* -------- DMAC_PENDCH : (DMAC Offset: 0x2C) (R/ 32) Pending Channels -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t PENDCH0:1; /*!< bit: 0 Pending Channel 0 */
- uint32_t PENDCH1:1; /*!< bit: 1 Pending Channel 1 */
- uint32_t PENDCH2:1; /*!< bit: 2 Pending Channel 2 */
- uint32_t PENDCH3:1; /*!< bit: 3 Pending Channel 3 */
- uint32_t PENDCH4:1; /*!< bit: 4 Pending Channel 4 */
- uint32_t PENDCH5:1; /*!< bit: 5 Pending Channel 5 */
- uint32_t PENDCH6:1; /*!< bit: 6 Pending Channel 6 */
- uint32_t PENDCH7:1; /*!< bit: 7 Pending Channel 7 */
- uint32_t PENDCH8:1; /*!< bit: 8 Pending Channel 8 */
- uint32_t PENDCH9:1; /*!< bit: 9 Pending Channel 9 */
- uint32_t PENDCH10:1; /*!< bit: 10 Pending Channel 10 */
- uint32_t PENDCH11:1; /*!< bit: 11 Pending Channel 11 */
- uint32_t :20; /*!< bit: 12..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t PENDCH:12; /*!< bit: 0..11 Pending Channel x */
- uint32_t :20; /*!< bit: 12..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t PENDCH0:1; /*!< bit: 0 Pending Channel 0 */
+ uint32_t PENDCH1:1; /*!< bit: 1 Pending Channel 1 */
+ uint32_t PENDCH2:1; /*!< bit: 2 Pending Channel 2 */
+ uint32_t PENDCH3:1; /*!< bit: 3 Pending Channel 3 */
+ uint32_t PENDCH4:1; /*!< bit: 4 Pending Channel 4 */
+ uint32_t PENDCH5:1; /*!< bit: 5 Pending Channel 5 */
+ uint32_t PENDCH6:1; /*!< bit: 6 Pending Channel 6 */
+ uint32_t PENDCH7:1; /*!< bit: 7 Pending Channel 7 */
+ uint32_t PENDCH8:1; /*!< bit: 8 Pending Channel 8 */
+ uint32_t PENDCH9:1; /*!< bit: 9 Pending Channel 9 */
+ uint32_t PENDCH10:1; /*!< bit: 10 Pending Channel 10 */
+ uint32_t PENDCH11:1; /*!< bit: 11 Pending Channel 11 */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t PENDCH:12; /*!< bit: 0..11 Pending Channel x */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} DMAC_PENDCH_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -588,22 +588,22 @@ typedef union {
/* -------- DMAC_ACTIVE : (DMAC Offset: 0x30) (R/ 32) Active Channel and Levels -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t LVLEX0:1; /*!< bit: 0 Level 0 Channel Trigger Request Executing */
- uint32_t LVLEX1:1; /*!< bit: 1 Level 1 Channel Trigger Request Executing */
- uint32_t LVLEX2:1; /*!< bit: 2 Level 2 Channel Trigger Request Executing */
- uint32_t LVLEX3:1; /*!< bit: 3 Level 3 Channel Trigger Request Executing */
- uint32_t :4; /*!< bit: 4.. 7 Reserved */
- uint32_t ID:5; /*!< bit: 8..12 Active Channel ID */
- uint32_t :2; /*!< bit: 13..14 Reserved */
- uint32_t ABUSY:1; /*!< bit: 15 Active Channel Busy */
- uint32_t BTCNT:16; /*!< bit: 16..31 Active Channel Block Transfer Count */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t LVLEX:4; /*!< bit: 0.. 3 Level x Channel Trigger Request Executing */
- uint32_t :28; /*!< bit: 4..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t LVLEX0:1; /*!< bit: 0 Level 0 Channel Trigger Request Executing */
+ uint32_t LVLEX1:1; /*!< bit: 1 Level 1 Channel Trigger Request Executing */
+ uint32_t LVLEX2:1; /*!< bit: 2 Level 2 Channel Trigger Request Executing */
+ uint32_t LVLEX3:1; /*!< bit: 3 Level 3 Channel Trigger Request Executing */
+ uint32_t :4; /*!< bit: 4.. 7 Reserved */
+ uint32_t ID:5; /*!< bit: 8..12 Active Channel ID */
+ uint32_t :2; /*!< bit: 13..14 Reserved */
+ uint32_t ABUSY:1; /*!< bit: 15 Active Channel Busy */
+ uint32_t BTCNT:16; /*!< bit: 16..31 Active Channel Block Transfer Count */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t LVLEX:4; /*!< bit: 0.. 3 Level x Channel Trigger Request Executing */
+ uint32_t :28; /*!< bit: 4..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} DMAC_ACTIVE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -634,10 +634,10 @@ typedef union {
/* -------- DMAC_BASEADDR : (DMAC Offset: 0x34) (R/W 32) Descriptor Memory Section Base Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t BASEADDR:32; /*!< bit: 0..31 Descriptor Memory Base Address */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t BASEADDR:32; /*!< bit: 0..31 Descriptor Memory Base Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DMAC_BASEADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -652,10 +652,10 @@ typedef union {
/* -------- DMAC_WRBADDR : (DMAC Offset: 0x38) (R/W 32) Write-Back Memory Section Base Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t WRBADDR:32; /*!< bit: 0..31 Write-Back Memory Base Address */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t WRBADDR:32; /*!< bit: 0..31 Write-Back Memory Base Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DMAC_WRBADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -670,11 +670,11 @@ typedef union {
/* -------- DMAC_CHID : (DMAC Offset: 0x3F) (R/W 8) Channel ID -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t ID:4; /*!< bit: 0.. 3 Channel ID */
- uint8_t :4; /*!< bit: 4.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t ID:4; /*!< bit: 0.. 3 Channel ID */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} DMAC_CHID_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -689,12 +689,12 @@ typedef union {
/* -------- DMAC_CHCTRLA : (DMAC Offset: 0x40) (R/W 8) Channel Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t SWRST:1; /*!< bit: 0 Channel Software Reset */
- uint8_t ENABLE:1; /*!< bit: 1 Channel Enable */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Channel Software Reset */
+ uint8_t ENABLE:1; /*!< bit: 1 Channel Enable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} DMAC_CHCTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -710,19 +710,19 @@ typedef union {
/* -------- DMAC_CHCTRLB : (DMAC Offset: 0x44) (R/W 32) Channel Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t EVACT:3; /*!< bit: 0.. 2 Event Input Action */
- uint32_t EVIE:1; /*!< bit: 3 Channel Event Input Enable */
- uint32_t EVOE:1; /*!< bit: 4 Channel Event Output Enable */
- uint32_t LVL:2; /*!< bit: 5.. 6 Channel Arbitration Level */
- uint32_t :1; /*!< bit: 7 Reserved */
- uint32_t TRIGSRC:6; /*!< bit: 8..13 Peripheral Trigger Source */
- uint32_t :8; /*!< bit: 14..21 Reserved */
- uint32_t TRIGACT:2; /*!< bit: 22..23 Trigger Action */
- uint32_t CMD:2; /*!< bit: 24..25 Software Command */
- uint32_t :6; /*!< bit: 26..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t EVACT:3; /*!< bit: 0.. 2 Event Input Action */
+ uint32_t EVIE:1; /*!< bit: 3 Channel Event Input Enable */
+ uint32_t EVOE:1; /*!< bit: 4 Channel Event Output Enable */
+ uint32_t LVL:2; /*!< bit: 5.. 6 Channel Arbitration Level */
+ uint32_t :1; /*!< bit: 7 Reserved */
+ uint32_t TRIGSRC:6; /*!< bit: 8..13 Peripheral Trigger Source */
+ uint32_t :8; /*!< bit: 14..21 Reserved */
+ uint32_t TRIGACT:2; /*!< bit: 22..23 Trigger Action */
+ uint32_t CMD:2; /*!< bit: 24..25 Software Command */
+ uint32_t :6; /*!< bit: 26..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DMAC_CHCTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -789,13 +789,13 @@ typedef union {
/* -------- DMAC_CHINTENCLR : (DMAC Offset: 0x4C) (R/W 8) Channel Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t TERR:1; /*!< bit: 0 Transfer Error Interrupt Enable */
- uint8_t TCMPL:1; /*!< bit: 1 Transfer Complete Interrupt Enable */
- uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t TERR:1; /*!< bit: 0 Transfer Error Interrupt Enable */
+ uint8_t TCMPL:1; /*!< bit: 1 Transfer Complete Interrupt Enable */
+ uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} DMAC_CHINTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -813,13 +813,13 @@ typedef union {
/* -------- DMAC_CHINTENSET : (DMAC Offset: 0x4D) (R/W 8) Channel Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t TERR:1; /*!< bit: 0 Transfer Error Interrupt Enable */
- uint8_t TCMPL:1; /*!< bit: 1 Transfer Complete Interrupt Enable */
- uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t TERR:1; /*!< bit: 0 Transfer Error Interrupt Enable */
+ uint8_t TCMPL:1; /*!< bit: 1 Transfer Complete Interrupt Enable */
+ uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} DMAC_CHINTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -837,13 +837,13 @@ typedef union {
/* -------- DMAC_CHINTFLAG : (DMAC Offset: 0x4E) (R/W 8) Channel Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t TERR:1; /*!< bit: 0 Transfer Error */
- uint8_t TCMPL:1; /*!< bit: 1 Transfer Complete */
- uint8_t SUSP:1; /*!< bit: 2 Channel Suspend */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t TERR:1; /*!< bit: 0 Transfer Error */
+ uint8_t TCMPL:1; /*!< bit: 1 Transfer Complete */
+ uint8_t SUSP:1; /*!< bit: 2 Channel Suspend */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} DMAC_CHINTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -861,13 +861,13 @@ typedef union {
/* -------- DMAC_CHSTATUS : (DMAC Offset: 0x4F) (R/ 8) Channel Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t PEND:1; /*!< bit: 0 Channel Pending */
- uint8_t BUSY:1; /*!< bit: 1 Channel Busy */
- uint8_t FERR:1; /*!< bit: 2 Fetch Error */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t PEND:1; /*!< bit: 0 Channel Pending */
+ uint8_t BUSY:1; /*!< bit: 1 Channel Busy */
+ uint8_t FERR:1; /*!< bit: 2 Fetch Error */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} DMAC_CHSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -885,18 +885,18 @@ typedef union {
/* -------- DMAC_BTCTRL : (DMAC Offset: 0x00) (R/W 16) Block Transfer Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t VALID:1; /*!< bit: 0 Descriptor Valid */
- uint16_t EVOSEL:2; /*!< bit: 1.. 2 Event Output Selection */
- uint16_t BLOCKACT:2; /*!< bit: 3.. 4 Block Action */
- uint16_t :3; /*!< bit: 5.. 7 Reserved */
- uint16_t BEATSIZE:2; /*!< bit: 8.. 9 Beat Size */
- uint16_t SRCINC:1; /*!< bit: 10 Source Address Increment Enable */
- uint16_t DSTINC:1; /*!< bit: 11 Destination Address Increment Enable */
- uint16_t STEPSEL:1; /*!< bit: 12 Step Selection */
- uint16_t STEPSIZE:3; /*!< bit: 13..15 Address Increment Step Size */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t VALID:1; /*!< bit: 0 Descriptor Valid */
+ uint16_t EVOSEL:2; /*!< bit: 1.. 2 Event Output Selection */
+ uint16_t BLOCKACT:2; /*!< bit: 3.. 4 Block Action */
+ uint16_t :3; /*!< bit: 5.. 7 Reserved */
+ uint16_t BEATSIZE:2; /*!< bit: 8.. 9 Beat Size */
+ uint16_t SRCINC:1; /*!< bit: 10 Source Address Increment Enable */
+ uint16_t DSTINC:1; /*!< bit: 11 Destination Address Increment Enable */
+ uint16_t STEPSEL:1; /*!< bit: 12 Step Selection */
+ uint16_t STEPSIZE:3; /*!< bit: 13..15 Address Increment Step Size */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} DMAC_BTCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -967,10 +967,10 @@ typedef union {
/* -------- DMAC_BTCNT : (DMAC Offset: 0x02) (R/W 16) Block Transfer Count -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t BTCNT:16; /*!< bit: 0..15 Block Transfer Count */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t BTCNT:16; /*!< bit: 0..15 Block Transfer Count */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} DMAC_BTCNT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -984,10 +984,10 @@ typedef union {
/* -------- DMAC_SRCADDR : (DMAC Offset: 0x04) (R/W 32) Transfer Source Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SRCADDR:32; /*!< bit: 0..31 Transfer Source Address */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SRCADDR:32; /*!< bit: 0..31 Transfer Source Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DMAC_SRCADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1001,10 +1001,10 @@ typedef union {
/* -------- DMAC_DSTADDR : (DMAC Offset: 0x08) (R/W 32) Transfer Destination Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t DSTADDR:32; /*!< bit: 0..31 Transfer Destination Address */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t DSTADDR:32; /*!< bit: 0..31 Transfer Destination Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DMAC_DSTADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1018,10 +1018,10 @@ typedef union {
/* -------- DMAC_DESCADDR : (DMAC Offset: 0x0C) (R/W 32) Next Descriptor Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t DESCADDR:32; /*!< bit: 0..31 Next Descriptor Address */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t DESCADDR:32; /*!< bit: 0..31 Next Descriptor Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DMAC_DESCADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1035,49 +1035,49 @@ typedef union {
/** \brief DMAC APB hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO DMAC_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) Control */
- __IO DMAC_CRCCTRL_Type CRCCTRL; /**< \brief Offset: 0x02 (R/W 16) CRC Control */
- __IO DMAC_CRCDATAIN_Type CRCDATAIN; /**< \brief Offset: 0x04 (R/W 32) CRC Data Input */
- __IO DMAC_CRCCHKSUM_Type CRCCHKSUM; /**< \brief Offset: 0x08 (R/W 32) CRC Checksum */
- __IO DMAC_CRCSTATUS_Type CRCSTATUS; /**< \brief Offset: 0x0C (R/W 8) CRC Status */
- __IO DMAC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0D (R/W 8) Debug Control */
- __IO DMAC_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x0E (R/W 8) QOS Control */
- RoReg8 Reserved1[0x1];
- __IO DMAC_SWTRIGCTRL_Type SWTRIGCTRL; /**< \brief Offset: 0x10 (R/W 32) Software Trigger Control */
- __IO DMAC_PRICTRL0_Type PRICTRL0; /**< \brief Offset: 0x14 (R/W 32) Priority Control 0 */
- RoReg8 Reserved2[0x8];
- __IO DMAC_INTPEND_Type INTPEND; /**< \brief Offset: 0x20 (R/W 16) Interrupt Pending */
- RoReg8 Reserved3[0x2];
- __I DMAC_INTSTATUS_Type INTSTATUS; /**< \brief Offset: 0x24 (R/ 32) Interrupt Status */
- __I DMAC_BUSYCH_Type BUSYCH; /**< \brief Offset: 0x28 (R/ 32) Busy Channels */
- __I DMAC_PENDCH_Type PENDCH; /**< \brief Offset: 0x2C (R/ 32) Pending Channels */
- __I DMAC_ACTIVE_Type ACTIVE; /**< \brief Offset: 0x30 (R/ 32) Active Channel and Levels */
- __IO DMAC_BASEADDR_Type BASEADDR; /**< \brief Offset: 0x34 (R/W 32) Descriptor Memory Section Base Address */
- __IO DMAC_WRBADDR_Type WRBADDR; /**< \brief Offset: 0x38 (R/W 32) Write-Back Memory Section Base Address */
- RoReg8 Reserved4[0x3];
- __IO DMAC_CHID_Type CHID; /**< \brief Offset: 0x3F (R/W 8) Channel ID */
- __IO DMAC_CHCTRLA_Type CHCTRLA; /**< \brief Offset: 0x40 (R/W 8) Channel Control A */
- RoReg8 Reserved5[0x3];
- __IO DMAC_CHCTRLB_Type CHCTRLB; /**< \brief Offset: 0x44 (R/W 32) Channel Control B */
- RoReg8 Reserved6[0x4];
- __IO DMAC_CHINTENCLR_Type CHINTENCLR; /**< \brief Offset: 0x4C (R/W 8) Channel Interrupt Enable Clear */
- __IO DMAC_CHINTENSET_Type CHINTENSET; /**< \brief Offset: 0x4D (R/W 8) Channel Interrupt Enable Set */
- __IO DMAC_CHINTFLAG_Type CHINTFLAG; /**< \brief Offset: 0x4E (R/W 8) Channel Interrupt Flag Status and Clear */
- __I DMAC_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x4F (R/ 8) Channel Status */
+ __IO DMAC_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) Control */
+ __IO DMAC_CRCCTRL_Type CRCCTRL; /**< \brief Offset: 0x02 (R/W 16) CRC Control */
+ __IO DMAC_CRCDATAIN_Type CRCDATAIN; /**< \brief Offset: 0x04 (R/W 32) CRC Data Input */
+ __IO DMAC_CRCCHKSUM_Type CRCCHKSUM; /**< \brief Offset: 0x08 (R/W 32) CRC Checksum */
+ __IO DMAC_CRCSTATUS_Type CRCSTATUS; /**< \brief Offset: 0x0C (R/W 8) CRC Status */
+ __IO DMAC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0D (R/W 8) Debug Control */
+ __IO DMAC_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x0E (R/W 8) QOS Control */
+ RoReg8 Reserved1[0x1];
+ __IO DMAC_SWTRIGCTRL_Type SWTRIGCTRL; /**< \brief Offset: 0x10 (R/W 32) Software Trigger Control */
+ __IO DMAC_PRICTRL0_Type PRICTRL0; /**< \brief Offset: 0x14 (R/W 32) Priority Control 0 */
+ RoReg8 Reserved2[0x8];
+ __IO DMAC_INTPEND_Type INTPEND; /**< \brief Offset: 0x20 (R/W 16) Interrupt Pending */
+ RoReg8 Reserved3[0x2];
+ __I DMAC_INTSTATUS_Type INTSTATUS; /**< \brief Offset: 0x24 (R/ 32) Interrupt Status */
+ __I DMAC_BUSYCH_Type BUSYCH; /**< \brief Offset: 0x28 (R/ 32) Busy Channels */
+ __I DMAC_PENDCH_Type PENDCH; /**< \brief Offset: 0x2C (R/ 32) Pending Channels */
+ __I DMAC_ACTIVE_Type ACTIVE; /**< \brief Offset: 0x30 (R/ 32) Active Channel and Levels */
+ __IO DMAC_BASEADDR_Type BASEADDR; /**< \brief Offset: 0x34 (R/W 32) Descriptor Memory Section Base Address */
+ __IO DMAC_WRBADDR_Type WRBADDR; /**< \brief Offset: 0x38 (R/W 32) Write-Back Memory Section Base Address */
+ RoReg8 Reserved4[0x3];
+ __IO DMAC_CHID_Type CHID; /**< \brief Offset: 0x3F (R/W 8) Channel ID */
+ __IO DMAC_CHCTRLA_Type CHCTRLA; /**< \brief Offset: 0x40 (R/W 8) Channel Control A */
+ RoReg8 Reserved5[0x3];
+ __IO DMAC_CHCTRLB_Type CHCTRLB; /**< \brief Offset: 0x44 (R/W 32) Channel Control B */
+ RoReg8 Reserved6[0x4];
+ __IO DMAC_CHINTENCLR_Type CHINTENCLR; /**< \brief Offset: 0x4C (R/W 8) Channel Interrupt Enable Clear */
+ __IO DMAC_CHINTENSET_Type CHINTENSET; /**< \brief Offset: 0x4D (R/W 8) Channel Interrupt Enable Set */
+ __IO DMAC_CHINTFLAG_Type CHINTFLAG; /**< \brief Offset: 0x4E (R/W 8) Channel Interrupt Flag Status and Clear */
+ __I DMAC_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x4F (R/ 8) Channel Status */
} Dmac;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief DMAC Descriptor SRAM registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO DMAC_BTCTRL_Type BTCTRL; /**< \brief Offset: 0x00 (R/W 16) Block Transfer Control */
- __IO DMAC_BTCNT_Type BTCNT; /**< \brief Offset: 0x02 (R/W 16) Block Transfer Count */
- __IO DMAC_SRCADDR_Type SRCADDR; /**< \brief Offset: 0x04 (R/W 32) Transfer Source Address */
- __IO DMAC_DSTADDR_Type DSTADDR; /**< \brief Offset: 0x08 (R/W 32) Transfer Destination Address */
- __IO DMAC_DESCADDR_Type DESCADDR; /**< \brief Offset: 0x0C (R/W 32) Next Descriptor Address */
+ __IO DMAC_BTCTRL_Type BTCTRL; /**< \brief Offset: 0x00 (R/W 16) Block Transfer Control */
+ __IO DMAC_BTCNT_Type BTCNT; /**< \brief Offset: 0x02 (R/W 16) Block Transfer Count */
+ __IO DMAC_SRCADDR_Type SRCADDR; /**< \brief Offset: 0x04 (R/W 32) Transfer Source Address */
+ __IO DMAC_DSTADDR_Type DSTADDR; /**< \brief Offset: 0x08 (R/W 32) Transfer Destination Address */
+ __IO DMAC_DESCADDR_Type DESCADDR; /**< \brief Offset: 0x0C (R/W 32) Next Descriptor Address */
} DmacDescriptor
#ifdef __GNUC__
- __attribute__ ((aligned (8)))
+__attribute__ ((aligned (8)))
#endif
;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_dsu.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_dsu.h
index fc7b5ec4f3d..450f3444e5b 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_dsu.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_dsu.h
@@ -59,15 +59,15 @@
/* -------- DSU_CTRL : (DSU Offset: 0x0000) ( /W 8) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t SWRST:1; /*!< bit: 0 Software Reset */
- uint8_t :1; /*!< bit: 1 Reserved */
- uint8_t CRC:1; /*!< bit: 2 32-bit Cyclic Redundancy Check */
- uint8_t MBIST:1; /*!< bit: 3 Memory Built-In Self-Test */
- uint8_t CE:1; /*!< bit: 4 Chip Erase */
- uint8_t :3; /*!< bit: 5.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t :1; /*!< bit: 1 Reserved */
+ uint8_t CRC:1; /*!< bit: 2 32-bit Cyclic Redundancy Check */
+ uint8_t MBIST:1; /*!< bit: 3 Memory Built-In Self-Test */
+ uint8_t CE:1; /*!< bit: 4 Chip Erase */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} DSU_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -87,15 +87,15 @@ typedef union {
/* -------- DSU_STATUSA : (DSU Offset: 0x0001) (R/W 8) Status A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DONE:1; /*!< bit: 0 Done */
- uint8_t CRSTEXT:1; /*!< bit: 1 CPU Reset Phase Extension */
- uint8_t BERR:1; /*!< bit: 2 Bus Error */
- uint8_t FAIL:1; /*!< bit: 3 Failure */
- uint8_t PERR:1; /*!< bit: 4 Protection Error */
- uint8_t :3; /*!< bit: 5.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DONE:1; /*!< bit: 0 Done */
+ uint8_t CRSTEXT:1; /*!< bit: 1 CPU Reset Phase Extension */
+ uint8_t BERR:1; /*!< bit: 2 Bus Error */
+ uint8_t FAIL:1; /*!< bit: 3 Failure */
+ uint8_t PERR:1; /*!< bit: 4 Protection Error */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} DSU_STATUSA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -117,20 +117,20 @@ typedef union {
/* -------- DSU_STATUSB : (DSU Offset: 0x0002) (R/ 8) Status B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t PROT:1; /*!< bit: 0 Protected */
- uint8_t DBGPRES:1; /*!< bit: 1 Debugger Present */
- uint8_t DCCD0:1; /*!< bit: 2 Debug Communication Channel 0 Dirty */
- uint8_t DCCD1:1; /*!< bit: 3 Debug Communication Channel 1 Dirty */
- uint8_t HPE:1; /*!< bit: 4 Hot-Plugging Enable */
- uint8_t :3; /*!< bit: 5.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t :2; /*!< bit: 0.. 1 Reserved */
- uint8_t DCCD:2; /*!< bit: 2.. 3 Debug Communication Channel x Dirty */
- uint8_t :4; /*!< bit: 4.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t PROT:1; /*!< bit: 0 Protected */
+ uint8_t DBGPRES:1; /*!< bit: 1 Debugger Present */
+ uint8_t DCCD0:1; /*!< bit: 2 Debug Communication Channel 0 Dirty */
+ uint8_t DCCD1:1; /*!< bit: 3 Debug Communication Channel 1 Dirty */
+ uint8_t HPE:1; /*!< bit: 4 Hot-Plugging Enable */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t :2; /*!< bit: 0.. 1 Reserved */
+ uint8_t DCCD:2; /*!< bit: 2.. 3 Debug Communication Channel x Dirty */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} DSU_STATUSB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -155,11 +155,11 @@ typedef union {
/* -------- DSU_ADDR : (DSU Offset: 0x0004) (R/W 32) Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t :2; /*!< bit: 0.. 1 Reserved */
- uint32_t ADDR:30; /*!< bit: 2..31 Address */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t :2; /*!< bit: 0.. 1 Reserved */
+ uint32_t ADDR:30; /*!< bit: 2..31 Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DSU_ADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -174,11 +174,11 @@ typedef union {
/* -------- DSU_LENGTH : (DSU Offset: 0x0008) (R/W 32) Length -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t :2; /*!< bit: 0.. 1 Reserved */
- uint32_t LENGTH:30; /*!< bit: 2..31 Length */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t :2; /*!< bit: 0.. 1 Reserved */
+ uint32_t LENGTH:30; /*!< bit: 2..31 Length */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DSU_LENGTH_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -193,10 +193,10 @@ typedef union {
/* -------- DSU_DATA : (DSU Offset: 0x000C) (R/W 32) Data -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t DATA:32; /*!< bit: 0..31 Data */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t DATA:32; /*!< bit: 0..31 Data */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DSU_DATA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -211,10 +211,10 @@ typedef union {
/* -------- DSU_DCC : (DSU Offset: 0x0010) (R/W 32) Debug Communication Channel n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t DATA:32; /*!< bit: 0..31 Data */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t DATA:32; /*!< bit: 0..31 Data */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DSU_DCC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -229,16 +229,16 @@ typedef union {
/* -------- DSU_DID : (DSU Offset: 0x0018) (R/ 32) Device Identification -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t DEVSEL:8; /*!< bit: 0.. 7 Device Select */
- uint32_t REVISION:4; /*!< bit: 8..11 Revision */
- uint32_t DIE:4; /*!< bit: 12..15 Die Identification */
- uint32_t SERIES:6; /*!< bit: 16..21 Product Series */
- uint32_t :1; /*!< bit: 22 Reserved */
- uint32_t FAMILY:5; /*!< bit: 23..27 Product Family */
- uint32_t PROCESSOR:4; /*!< bit: 28..31 Processor */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t DEVSEL:8; /*!< bit: 0.. 7 Device Select */
+ uint32_t REVISION:4; /*!< bit: 8..11 Revision */
+ uint32_t DIE:4; /*!< bit: 12..15 Die Identification */
+ uint32_t SERIES:6; /*!< bit: 16..21 Product Series */
+ uint32_t :1; /*!< bit: 22 Reserved */
+ uint32_t FAMILY:5; /*!< bit: 23..27 Product Family */
+ uint32_t PROCESSOR:4; /*!< bit: 28..31 Processor */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DSU_DID_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -267,13 +267,13 @@ typedef union {
/* -------- DSU_ENTRY : (DSU Offset: 0x1000) (R/ 32) Coresight ROM Table Entry n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t EPRES:1; /*!< bit: 0 Entry Present */
- uint32_t FMT:1; /*!< bit: 1 Format */
- uint32_t :10; /*!< bit: 2..11 Reserved */
- uint32_t ADDOFF:20; /*!< bit: 12..31 Address Offset */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t EPRES:1; /*!< bit: 0 Entry Present */
+ uint32_t FMT:1; /*!< bit: 1 Format */
+ uint32_t :10; /*!< bit: 2..11 Reserved */
+ uint32_t ADDOFF:20; /*!< bit: 12..31 Address Offset */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DSU_ENTRY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -292,10 +292,10 @@ typedef union {
/* -------- DSU_END : (DSU Offset: 0x1008) (R/ 32) Coresight ROM Table End -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t END:32; /*!< bit: 0..31 End Marker */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t END:32; /*!< bit: 0..31 End Marker */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DSU_END_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -310,11 +310,11 @@ typedef union {
/* -------- DSU_MEMTYPE : (DSU Offset: 0x1FCC) (R/ 32) Coresight ROM Table Memory Type -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SMEMP:1; /*!< bit: 0 System Memory Present */
- uint32_t :31; /*!< bit: 1..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SMEMP:1; /*!< bit: 0 System Memory Present */
+ uint32_t :31; /*!< bit: 1..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DSU_MEMTYPE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -328,12 +328,12 @@ typedef union {
/* -------- DSU_PID4 : (DSU Offset: 0x1FD0) (R/ 32) Peripheral Identification 4 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t JEPCC:4; /*!< bit: 0.. 3 JEP-106 Continuation Code */
- uint32_t FKBC:4; /*!< bit: 4.. 7 4KB Count */
- uint32_t :24; /*!< bit: 8..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t JEPCC:4; /*!< bit: 0.. 3 JEP-106 Continuation Code */
+ uint32_t FKBC:4; /*!< bit: 4.. 7 4KB Count */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DSU_PID4_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -351,11 +351,11 @@ typedef union {
/* -------- DSU_PID0 : (DSU Offset: 0x1FE0) (R/ 32) Peripheral Identification 0 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t PARTNBL:8; /*!< bit: 0.. 7 Part Number Low */
- uint32_t :24; /*!< bit: 8..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t PARTNBL:8; /*!< bit: 0.. 7 Part Number Low */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DSU_PID0_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -370,12 +370,12 @@ typedef union {
/* -------- DSU_PID1 : (DSU Offset: 0x1FE4) (R/ 32) Peripheral Identification 1 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t PARTNBH:4; /*!< bit: 0.. 3 Part Number High */
- uint32_t JEPIDCL:4; /*!< bit: 4.. 7 Low part of the JEP-106 Identity Code */
- uint32_t :24; /*!< bit: 8..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t PARTNBH:4; /*!< bit: 0.. 3 Part Number High */
+ uint32_t JEPIDCL:4; /*!< bit: 4.. 7 Low part of the JEP-106 Identity Code */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DSU_PID1_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -393,13 +393,13 @@ typedef union {
/* -------- DSU_PID2 : (DSU Offset: 0x1FE8) (R/ 32) Peripheral Identification 2 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t JEPIDCH:3; /*!< bit: 0.. 2 JEP-106 Identity Code High */
- uint32_t JEPU:1; /*!< bit: 3 JEP-106 Identity Code is used */
- uint32_t REVISION:4; /*!< bit: 4.. 7 Revision Number */
- uint32_t :24; /*!< bit: 8..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t JEPIDCH:3; /*!< bit: 0.. 2 JEP-106 Identity Code High */
+ uint32_t JEPU:1; /*!< bit: 3 JEP-106 Identity Code is used */
+ uint32_t REVISION:4; /*!< bit: 4.. 7 Revision Number */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DSU_PID2_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -419,12 +419,12 @@ typedef union {
/* -------- DSU_PID3 : (DSU Offset: 0x1FEC) (R/ 32) Peripheral Identification 3 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t CUSMOD:4; /*!< bit: 0.. 3 ARM CUSMOD */
- uint32_t REVAND:4; /*!< bit: 4.. 7 Revision Number */
- uint32_t :24; /*!< bit: 8..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t CUSMOD:4; /*!< bit: 0.. 3 ARM CUSMOD */
+ uint32_t REVAND:4; /*!< bit: 4.. 7 Revision Number */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DSU_PID3_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -442,11 +442,11 @@ typedef union {
/* -------- DSU_CID0 : (DSU Offset: 0x1FF0) (R/ 32) Component Identification 0 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t PREAMBLEB0:8; /*!< bit: 0.. 7 Preamble Byte 0 */
- uint32_t :24; /*!< bit: 8..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t PREAMBLEB0:8; /*!< bit: 0.. 7 Preamble Byte 0 */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DSU_CID0_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -461,12 +461,12 @@ typedef union {
/* -------- DSU_CID1 : (DSU Offset: 0x1FF4) (R/ 32) Component Identification 1 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t PREAMBLE:4; /*!< bit: 0.. 3 Preamble */
- uint32_t CCLASS:4; /*!< bit: 4.. 7 Component Class */
- uint32_t :24; /*!< bit: 8..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t PREAMBLE:4; /*!< bit: 0.. 3 Preamble */
+ uint32_t CCLASS:4; /*!< bit: 4.. 7 Component Class */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DSU_CID1_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -484,11 +484,11 @@ typedef union {
/* -------- DSU_CID2 : (DSU Offset: 0x1FF8) (R/ 32) Component Identification 2 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t PREAMBLEB2:8; /*!< bit: 0.. 7 Preamble Byte 2 */
- uint32_t :24; /*!< bit: 8..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t PREAMBLEB2:8; /*!< bit: 0.. 7 Preamble Byte 2 */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DSU_CID2_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -503,11 +503,11 @@ typedef union {
/* -------- DSU_CID3 : (DSU Offset: 0x1FFC) (R/ 32) Component Identification 3 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t PREAMBLEB3:8; /*!< bit: 0.. 7 Preamble Byte 3 */
- uint32_t :24; /*!< bit: 8..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t PREAMBLEB3:8; /*!< bit: 0.. 7 Preamble Byte 3 */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DSU_CID3_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -522,30 +522,30 @@ typedef union {
/** \brief DSU hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __O DSU_CTRL_Type CTRL; /**< \brief Offset: 0x0000 ( /W 8) Control */
- __IO DSU_STATUSA_Type STATUSA; /**< \brief Offset: 0x0001 (R/W 8) Status A */
- __I DSU_STATUSB_Type STATUSB; /**< \brief Offset: 0x0002 (R/ 8) Status B */
- RoReg8 Reserved1[0x1];
- __IO DSU_ADDR_Type ADDR; /**< \brief Offset: 0x0004 (R/W 32) Address */
- __IO DSU_LENGTH_Type LENGTH; /**< \brief Offset: 0x0008 (R/W 32) Length */
- __IO DSU_DATA_Type DATA; /**< \brief Offset: 0x000C (R/W 32) Data */
- __IO DSU_DCC_Type DCC[2]; /**< \brief Offset: 0x0010 (R/W 32) Debug Communication Channel n */
- __I DSU_DID_Type DID; /**< \brief Offset: 0x0018 (R/ 32) Device Identification */
- RoReg8 Reserved2[0xFE4];
- __I DSU_ENTRY_Type ENTRY[2]; /**< \brief Offset: 0x1000 (R/ 32) Coresight ROM Table Entry n */
- __I DSU_END_Type END; /**< \brief Offset: 0x1008 (R/ 32) Coresight ROM Table End */
- RoReg8 Reserved3[0xFC0];
- __I DSU_MEMTYPE_Type MEMTYPE; /**< \brief Offset: 0x1FCC (R/ 32) Coresight ROM Table Memory Type */
- __I DSU_PID4_Type PID4; /**< \brief Offset: 0x1FD0 (R/ 32) Peripheral Identification 4 */
- RoReg8 Reserved4[0xC];
- __I DSU_PID0_Type PID0; /**< \brief Offset: 0x1FE0 (R/ 32) Peripheral Identification 0 */
- __I DSU_PID1_Type PID1; /**< \brief Offset: 0x1FE4 (R/ 32) Peripheral Identification 1 */
- __I DSU_PID2_Type PID2; /**< \brief Offset: 0x1FE8 (R/ 32) Peripheral Identification 2 */
- __I DSU_PID3_Type PID3; /**< \brief Offset: 0x1FEC (R/ 32) Peripheral Identification 3 */
- __I DSU_CID0_Type CID0; /**< \brief Offset: 0x1FF0 (R/ 32) Component Identification 0 */
- __I DSU_CID1_Type CID1; /**< \brief Offset: 0x1FF4 (R/ 32) Component Identification 1 */
- __I DSU_CID2_Type CID2; /**< \brief Offset: 0x1FF8 (R/ 32) Component Identification 2 */
- __I DSU_CID3_Type CID3; /**< \brief Offset: 0x1FFC (R/ 32) Component Identification 3 */
+ __O DSU_CTRL_Type CTRL; /**< \brief Offset: 0x0000 ( /W 8) Control */
+ __IO DSU_STATUSA_Type STATUSA; /**< \brief Offset: 0x0001 (R/W 8) Status A */
+ __I DSU_STATUSB_Type STATUSB; /**< \brief Offset: 0x0002 (R/ 8) Status B */
+ RoReg8 Reserved1[0x1];
+ __IO DSU_ADDR_Type ADDR; /**< \brief Offset: 0x0004 (R/W 32) Address */
+ __IO DSU_LENGTH_Type LENGTH; /**< \brief Offset: 0x0008 (R/W 32) Length */
+ __IO DSU_DATA_Type DATA; /**< \brief Offset: 0x000C (R/W 32) Data */
+ __IO DSU_DCC_Type DCC[2]; /**< \brief Offset: 0x0010 (R/W 32) Debug Communication Channel n */
+ __I DSU_DID_Type DID; /**< \brief Offset: 0x0018 (R/ 32) Device Identification */
+ RoReg8 Reserved2[0xFE4];
+ __I DSU_ENTRY_Type ENTRY[2]; /**< \brief Offset: 0x1000 (R/ 32) Coresight ROM Table Entry n */
+ __I DSU_END_Type END; /**< \brief Offset: 0x1008 (R/ 32) Coresight ROM Table End */
+ RoReg8 Reserved3[0xFC0];
+ __I DSU_MEMTYPE_Type MEMTYPE; /**< \brief Offset: 0x1FCC (R/ 32) Coresight ROM Table Memory Type */
+ __I DSU_PID4_Type PID4; /**< \brief Offset: 0x1FD0 (R/ 32) Peripheral Identification 4 */
+ RoReg8 Reserved4[0xC];
+ __I DSU_PID0_Type PID0; /**< \brief Offset: 0x1FE0 (R/ 32) Peripheral Identification 0 */
+ __I DSU_PID1_Type PID1; /**< \brief Offset: 0x1FE4 (R/ 32) Peripheral Identification 1 */
+ __I DSU_PID2_Type PID2; /**< \brief Offset: 0x1FE8 (R/ 32) Peripheral Identification 2 */
+ __I DSU_PID3_Type PID3; /**< \brief Offset: 0x1FEC (R/ 32) Peripheral Identification 3 */
+ __I DSU_CID0_Type CID0; /**< \brief Offset: 0x1FF0 (R/ 32) Component Identification 0 */
+ __I DSU_CID1_Type CID1; /**< \brief Offset: 0x1FF4 (R/ 32) Component Identification 1 */
+ __I DSU_CID2_Type CID2; /**< \brief Offset: 0x1FF8 (R/ 32) Component Identification 2 */
+ __I DSU_CID3_Type CID3; /**< \brief Offset: 0x1FFC (R/ 32) Component Identification 3 */
} Dsu;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_eic.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_eic.h
index 8c324a4b6c0..7ea6fe2833e 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_eic.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_eic.h
@@ -59,12 +59,12 @@
/* -------- EIC_CTRL : (EIC Offset: 0x00) (R/W 8) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t SWRST:1; /*!< bit: 0 Software Reset */
- uint8_t ENABLE:1; /*!< bit: 1 Enable */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} EIC_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -80,11 +80,11 @@ typedef union {
/* -------- EIC_STATUS : (EIC Offset: 0x01) (R/ 8) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t :7; /*!< bit: 0.. 6 Reserved */
- uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t :7; /*!< bit: 0.. 6 Reserved */
+ uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} EIC_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -98,12 +98,12 @@ typedef union {
/* -------- EIC_NMICTRL : (EIC Offset: 0x02) (R/W 8) Non-Maskable Interrupt Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t NMISENSE:3; /*!< bit: 0.. 2 Non-Maskable Interrupt Sense */
- uint8_t NMIFILTEN:1; /*!< bit: 3 Non-Maskable Interrupt Filter Enable */
- uint8_t :4; /*!< bit: 4.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t NMISENSE:3; /*!< bit: 0.. 2 Non-Maskable Interrupt Sense */
+ uint8_t NMIFILTEN:1; /*!< bit: 3 Non-Maskable Interrupt Filter Enable */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} EIC_NMICTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -132,11 +132,11 @@ typedef union {
/* -------- EIC_NMIFLAG : (EIC Offset: 0x03) (R/W 8) Non-Maskable Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t NMI:1; /*!< bit: 0 Non-Maskable Interrupt */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t NMI:1; /*!< bit: 0 Non-Maskable Interrupt */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} EIC_NMIFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -150,30 +150,30 @@ typedef union {
/* -------- EIC_EVCTRL : (EIC Offset: 0x04) (R/W 32) Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t EXTINTEO0:1; /*!< bit: 0 External Interrupt 0 Event Output Enable */
- uint32_t EXTINTEO1:1; /*!< bit: 1 External Interrupt 1 Event Output Enable */
- uint32_t EXTINTEO2:1; /*!< bit: 2 External Interrupt 2 Event Output Enable */
- uint32_t EXTINTEO3:1; /*!< bit: 3 External Interrupt 3 Event Output Enable */
- uint32_t EXTINTEO4:1; /*!< bit: 4 External Interrupt 4 Event Output Enable */
- uint32_t EXTINTEO5:1; /*!< bit: 5 External Interrupt 5 Event Output Enable */
- uint32_t EXTINTEO6:1; /*!< bit: 6 External Interrupt 6 Event Output Enable */
- uint32_t EXTINTEO7:1; /*!< bit: 7 External Interrupt 7 Event Output Enable */
- uint32_t EXTINTEO8:1; /*!< bit: 8 External Interrupt 8 Event Output Enable */
- uint32_t EXTINTEO9:1; /*!< bit: 9 External Interrupt 9 Event Output Enable */
- uint32_t EXTINTEO10:1; /*!< bit: 10 External Interrupt 10 Event Output Enable */
- uint32_t EXTINTEO11:1; /*!< bit: 11 External Interrupt 11 Event Output Enable */
- uint32_t EXTINTEO12:1; /*!< bit: 12 External Interrupt 12 Event Output Enable */
- uint32_t EXTINTEO13:1; /*!< bit: 13 External Interrupt 13 Event Output Enable */
- uint32_t EXTINTEO14:1; /*!< bit: 14 External Interrupt 14 Event Output Enable */
- uint32_t EXTINTEO15:1; /*!< bit: 15 External Interrupt 15 Event Output Enable */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t EXTINTEO:16; /*!< bit: 0..15 External Interrupt x Event Output Enable */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t EXTINTEO0:1; /*!< bit: 0 External Interrupt 0 Event Output Enable */
+ uint32_t EXTINTEO1:1; /*!< bit: 1 External Interrupt 1 Event Output Enable */
+ uint32_t EXTINTEO2:1; /*!< bit: 2 External Interrupt 2 Event Output Enable */
+ uint32_t EXTINTEO3:1; /*!< bit: 3 External Interrupt 3 Event Output Enable */
+ uint32_t EXTINTEO4:1; /*!< bit: 4 External Interrupt 4 Event Output Enable */
+ uint32_t EXTINTEO5:1; /*!< bit: 5 External Interrupt 5 Event Output Enable */
+ uint32_t EXTINTEO6:1; /*!< bit: 6 External Interrupt 6 Event Output Enable */
+ uint32_t EXTINTEO7:1; /*!< bit: 7 External Interrupt 7 Event Output Enable */
+ uint32_t EXTINTEO8:1; /*!< bit: 8 External Interrupt 8 Event Output Enable */
+ uint32_t EXTINTEO9:1; /*!< bit: 9 External Interrupt 9 Event Output Enable */
+ uint32_t EXTINTEO10:1; /*!< bit: 10 External Interrupt 10 Event Output Enable */
+ uint32_t EXTINTEO11:1; /*!< bit: 11 External Interrupt 11 Event Output Enable */
+ uint32_t EXTINTEO12:1; /*!< bit: 12 External Interrupt 12 Event Output Enable */
+ uint32_t EXTINTEO13:1; /*!< bit: 13 External Interrupt 13 Event Output Enable */
+ uint32_t EXTINTEO14:1; /*!< bit: 14 External Interrupt 14 Event Output Enable */
+ uint32_t EXTINTEO15:1; /*!< bit: 15 External Interrupt 15 Event Output Enable */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t EXTINTEO:16; /*!< bit: 0..15 External Interrupt x Event Output Enable */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} EIC_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -220,30 +220,30 @@ typedef union {
/* -------- EIC_INTENCLR : (EIC Offset: 0x08) (R/W 32) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 Enable */
- uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 Enable */
- uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 Enable */
- uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 Enable */
- uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 Enable */
- uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 Enable */
- uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 Enable */
- uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 Enable */
- uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 Enable */
- uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 Enable */
- uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 Enable */
- uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 Enable */
- uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 Enable */
- uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 Enable */
- uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 Enable */
- uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 Enable */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x Enable */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 Enable */
+ uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 Enable */
+ uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 Enable */
+ uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 Enable */
+ uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 Enable */
+ uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 Enable */
+ uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 Enable */
+ uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 Enable */
+ uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 Enable */
+ uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 Enable */
+ uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 Enable */
+ uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 Enable */
+ uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 Enable */
+ uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 Enable */
+ uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 Enable */
+ uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 Enable */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x Enable */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} EIC_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -290,30 +290,30 @@ typedef union {
/* -------- EIC_INTENSET : (EIC Offset: 0x0C) (R/W 32) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 Enable */
- uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 Enable */
- uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 Enable */
- uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 Enable */
- uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 Enable */
- uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 Enable */
- uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 Enable */
- uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 Enable */
- uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 Enable */
- uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 Enable */
- uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 Enable */
- uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 Enable */
- uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 Enable */
- uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 Enable */
- uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 Enable */
- uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 Enable */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x Enable */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 Enable */
+ uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 Enable */
+ uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 Enable */
+ uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 Enable */
+ uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 Enable */
+ uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 Enable */
+ uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 Enable */
+ uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 Enable */
+ uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 Enable */
+ uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 Enable */
+ uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 Enable */
+ uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 Enable */
+ uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 Enable */
+ uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 Enable */
+ uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 Enable */
+ uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 Enable */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x Enable */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} EIC_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -360,30 +360,30 @@ typedef union {
/* -------- EIC_INTFLAG : (EIC Offset: 0x10) (R/W 32) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 */
- uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 */
- uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 */
- uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 */
- uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 */
- uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 */
- uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 */
- uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 */
- uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 */
- uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 */
- uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 */
- uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 */
- uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 */
- uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 */
- uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 */
- uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 */
+ uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 */
+ uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 */
+ uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 */
+ uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 */
+ uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 */
+ uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 */
+ uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 */
+ uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 */
+ uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 */
+ uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 */
+ uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 */
+ uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 */
+ uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 */
+ uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 */
+ uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} EIC_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -430,30 +430,30 @@ typedef union {
/* -------- EIC_WAKEUP : (EIC Offset: 0x14) (R/W 32) Wake-Up Enable -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t WAKEUPEN0:1; /*!< bit: 0 External Interrupt 0 Wake-up Enable */
- uint32_t WAKEUPEN1:1; /*!< bit: 1 External Interrupt 1 Wake-up Enable */
- uint32_t WAKEUPEN2:1; /*!< bit: 2 External Interrupt 2 Wake-up Enable */
- uint32_t WAKEUPEN3:1; /*!< bit: 3 External Interrupt 3 Wake-up Enable */
- uint32_t WAKEUPEN4:1; /*!< bit: 4 External Interrupt 4 Wake-up Enable */
- uint32_t WAKEUPEN5:1; /*!< bit: 5 External Interrupt 5 Wake-up Enable */
- uint32_t WAKEUPEN6:1; /*!< bit: 6 External Interrupt 6 Wake-up Enable */
- uint32_t WAKEUPEN7:1; /*!< bit: 7 External Interrupt 7 Wake-up Enable */
- uint32_t WAKEUPEN8:1; /*!< bit: 8 External Interrupt 8 Wake-up Enable */
- uint32_t WAKEUPEN9:1; /*!< bit: 9 External Interrupt 9 Wake-up Enable */
- uint32_t WAKEUPEN10:1; /*!< bit: 10 External Interrupt 10 Wake-up Enable */
- uint32_t WAKEUPEN11:1; /*!< bit: 11 External Interrupt 11 Wake-up Enable */
- uint32_t WAKEUPEN12:1; /*!< bit: 12 External Interrupt 12 Wake-up Enable */
- uint32_t WAKEUPEN13:1; /*!< bit: 13 External Interrupt 13 Wake-up Enable */
- uint32_t WAKEUPEN14:1; /*!< bit: 14 External Interrupt 14 Wake-up Enable */
- uint32_t WAKEUPEN15:1; /*!< bit: 15 External Interrupt 15 Wake-up Enable */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t WAKEUPEN:16; /*!< bit: 0..15 External Interrupt x Wake-up Enable */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t WAKEUPEN0:1; /*!< bit: 0 External Interrupt 0 Wake-up Enable */
+ uint32_t WAKEUPEN1:1; /*!< bit: 1 External Interrupt 1 Wake-up Enable */
+ uint32_t WAKEUPEN2:1; /*!< bit: 2 External Interrupt 2 Wake-up Enable */
+ uint32_t WAKEUPEN3:1; /*!< bit: 3 External Interrupt 3 Wake-up Enable */
+ uint32_t WAKEUPEN4:1; /*!< bit: 4 External Interrupt 4 Wake-up Enable */
+ uint32_t WAKEUPEN5:1; /*!< bit: 5 External Interrupt 5 Wake-up Enable */
+ uint32_t WAKEUPEN6:1; /*!< bit: 6 External Interrupt 6 Wake-up Enable */
+ uint32_t WAKEUPEN7:1; /*!< bit: 7 External Interrupt 7 Wake-up Enable */
+ uint32_t WAKEUPEN8:1; /*!< bit: 8 External Interrupt 8 Wake-up Enable */
+ uint32_t WAKEUPEN9:1; /*!< bit: 9 External Interrupt 9 Wake-up Enable */
+ uint32_t WAKEUPEN10:1; /*!< bit: 10 External Interrupt 10 Wake-up Enable */
+ uint32_t WAKEUPEN11:1; /*!< bit: 11 External Interrupt 11 Wake-up Enable */
+ uint32_t WAKEUPEN12:1; /*!< bit: 12 External Interrupt 12 Wake-up Enable */
+ uint32_t WAKEUPEN13:1; /*!< bit: 13 External Interrupt 13 Wake-up Enable */
+ uint32_t WAKEUPEN14:1; /*!< bit: 14 External Interrupt 14 Wake-up Enable */
+ uint32_t WAKEUPEN15:1; /*!< bit: 15 External Interrupt 15 Wake-up Enable */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t WAKEUPEN:16; /*!< bit: 0..15 External Interrupt x Wake-up Enable */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} EIC_WAKEUP_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -500,25 +500,25 @@ typedef union {
/* -------- EIC_CONFIG : (EIC Offset: 0x18) (R/W 32) Configuration n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SENSE0:3; /*!< bit: 0.. 2 Input Sense 0 Configuration */
- uint32_t FILTEN0:1; /*!< bit: 3 Filter 0 Enable */
- uint32_t SENSE1:3; /*!< bit: 4.. 6 Input Sense 1 Configuration */
- uint32_t FILTEN1:1; /*!< bit: 7 Filter 1 Enable */
- uint32_t SENSE2:3; /*!< bit: 8..10 Input Sense 2 Configuration */
- uint32_t FILTEN2:1; /*!< bit: 11 Filter 2 Enable */
- uint32_t SENSE3:3; /*!< bit: 12..14 Input Sense 3 Configuration */
- uint32_t FILTEN3:1; /*!< bit: 15 Filter 3 Enable */
- uint32_t SENSE4:3; /*!< bit: 16..18 Input Sense 4 Configuration */
- uint32_t FILTEN4:1; /*!< bit: 19 Filter 4 Enable */
- uint32_t SENSE5:3; /*!< bit: 20..22 Input Sense 5 Configuration */
- uint32_t FILTEN5:1; /*!< bit: 23 Filter 5 Enable */
- uint32_t SENSE6:3; /*!< bit: 24..26 Input Sense 6 Configuration */
- uint32_t FILTEN6:1; /*!< bit: 27 Filter 6 Enable */
- uint32_t SENSE7:3; /*!< bit: 28..30 Input Sense 7 Configuration */
- uint32_t FILTEN7:1; /*!< bit: 31 Filter 7 Enable */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SENSE0:3; /*!< bit: 0.. 2 Input Sense 0 Configuration */
+ uint32_t FILTEN0:1; /*!< bit: 3 Filter 0 Enable */
+ uint32_t SENSE1:3; /*!< bit: 4.. 6 Input Sense 1 Configuration */
+ uint32_t FILTEN1:1; /*!< bit: 7 Filter 1 Enable */
+ uint32_t SENSE2:3; /*!< bit: 8..10 Input Sense 2 Configuration */
+ uint32_t FILTEN2:1; /*!< bit: 11 Filter 2 Enable */
+ uint32_t SENSE3:3; /*!< bit: 12..14 Input Sense 3 Configuration */
+ uint32_t FILTEN3:1; /*!< bit: 15 Filter 3 Enable */
+ uint32_t SENSE4:3; /*!< bit: 16..18 Input Sense 4 Configuration */
+ uint32_t FILTEN4:1; /*!< bit: 19 Filter 4 Enable */
+ uint32_t SENSE5:3; /*!< bit: 20..22 Input Sense 5 Configuration */
+ uint32_t FILTEN5:1; /*!< bit: 23 Filter 5 Enable */
+ uint32_t SENSE6:3; /*!< bit: 24..26 Input Sense 6 Configuration */
+ uint32_t FILTEN6:1; /*!< bit: 27 Filter 6 Enable */
+ uint32_t SENSE7:3; /*!< bit: 28..30 Input Sense 7 Configuration */
+ uint32_t FILTEN7:1; /*!< bit: 31 Filter 7 Enable */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} EIC_CONFIG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -666,16 +666,16 @@ typedef union {
/** \brief EIC hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO EIC_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 8) Control */
- __I EIC_STATUS_Type STATUS; /**< \brief Offset: 0x01 (R/ 8) Status */
- __IO EIC_NMICTRL_Type NMICTRL; /**< \brief Offset: 0x02 (R/W 8) Non-Maskable Interrupt Control */
- __IO EIC_NMIFLAG_Type NMIFLAG; /**< \brief Offset: 0x03 (R/W 8) Non-Maskable Interrupt Flag Status and Clear */
- __IO EIC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 32) Event Control */
- __IO EIC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 32) Interrupt Enable Clear */
- __IO EIC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0C (R/W 32) Interrupt Enable Set */
- __IO EIC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x10 (R/W 32) Interrupt Flag Status and Clear */
- __IO EIC_WAKEUP_Type WAKEUP; /**< \brief Offset: 0x14 (R/W 32) Wake-Up Enable */
- __IO EIC_CONFIG_Type CONFIG[2]; /**< \brief Offset: 0x18 (R/W 32) Configuration n */
+ __IO EIC_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 8) Control */
+ __I EIC_STATUS_Type STATUS; /**< \brief Offset: 0x01 (R/ 8) Status */
+ __IO EIC_NMICTRL_Type NMICTRL; /**< \brief Offset: 0x02 (R/W 8) Non-Maskable Interrupt Control */
+ __IO EIC_NMIFLAG_Type NMIFLAG; /**< \brief Offset: 0x03 (R/W 8) Non-Maskable Interrupt Flag Status and Clear */
+ __IO EIC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 32) Event Control */
+ __IO EIC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 32) Interrupt Enable Clear */
+ __IO EIC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0C (R/W 32) Interrupt Enable Set */
+ __IO EIC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x10 (R/W 32) Interrupt Flag Status and Clear */
+ __IO EIC_WAKEUP_Type WAKEUP; /**< \brief Offset: 0x14 (R/W 32) Wake-Up Enable */
+ __IO EIC_CONFIG_Type CONFIG[2]; /**< \brief Offset: 0x18 (R/W 32) Configuration n */
} Eic;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_evsys.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_evsys.h
index f4aa3ae09e9..5f28cf416b0 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_evsys.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_evsys.h
@@ -59,13 +59,13 @@
/* -------- EVSYS_CTRL : (EVSYS Offset: 0x00) ( /W 8) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t SWRST:1; /*!< bit: 0 Software Reset */
- uint8_t :3; /*!< bit: 1.. 3 Reserved */
- uint8_t GCLKREQ:1; /*!< bit: 4 Generic Clock Requests */
- uint8_t :3; /*!< bit: 5.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t :3; /*!< bit: 1.. 3 Reserved */
+ uint8_t GCLKREQ:1; /*!< bit: 4 Generic Clock Requests */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} EVSYS_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -81,18 +81,18 @@ typedef union {
/* -------- EVSYS_CHANNEL : (EVSYS Offset: 0x04) (R/W 32) Channel -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t CHANNEL:4; /*!< bit: 0.. 3 Channel Selection */
- uint32_t :4; /*!< bit: 4.. 7 Reserved */
- uint32_t SWEVT:1; /*!< bit: 8 Software Event */
- uint32_t :7; /*!< bit: 9..15 Reserved */
- uint32_t EVGEN:7; /*!< bit: 16..22 Event Generator Selection */
- uint32_t :1; /*!< bit: 23 Reserved */
- uint32_t PATH:2; /*!< bit: 24..25 Path Selection */
- uint32_t EDGSEL:2; /*!< bit: 26..27 Edge Detection Selection */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t CHANNEL:4; /*!< bit: 0.. 3 Channel Selection */
+ uint32_t :4; /*!< bit: 4.. 7 Reserved */
+ uint32_t SWEVT:1; /*!< bit: 8 Software Event */
+ uint32_t :7; /*!< bit: 9..15 Reserved */
+ uint32_t EVGEN:7; /*!< bit: 16..22 Event Generator Selection */
+ uint32_t :1; /*!< bit: 23 Reserved */
+ uint32_t PATH:2; /*!< bit: 24..25 Path Selection */
+ uint32_t EDGSEL:2; /*!< bit: 26..27 Edge Detection Selection */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} EVSYS_CHANNEL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -132,13 +132,13 @@ typedef union {
/* -------- EVSYS_USER : (EVSYS Offset: 0x08) (R/W 16) User Multiplexer -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t USER:5; /*!< bit: 0.. 4 User Multiplexer Selection */
- uint16_t :3; /*!< bit: 5.. 7 Reserved */
- uint16_t CHANNEL:5; /*!< bit: 8..12 Channel Event Selection */
- uint16_t :3; /*!< bit: 13..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t USER:5; /*!< bit: 0.. 4 User Multiplexer Selection */
+ uint16_t :3; /*!< bit: 5.. 7 Reserved */
+ uint16_t CHANNEL:5; /*!< bit: 8..12 Channel Event Selection */
+ uint16_t :3; /*!< bit: 13..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} EVSYS_USER_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -158,43 +158,43 @@ typedef union {
/* -------- EVSYS_CHSTATUS : (EVSYS Offset: 0x0C) (R/ 32) Channel Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t USRRDY0:1; /*!< bit: 0 Channel 0 User Ready */
- uint32_t USRRDY1:1; /*!< bit: 1 Channel 1 User Ready */
- uint32_t USRRDY2:1; /*!< bit: 2 Channel 2 User Ready */
- uint32_t USRRDY3:1; /*!< bit: 3 Channel 3 User Ready */
- uint32_t USRRDY4:1; /*!< bit: 4 Channel 4 User Ready */
- uint32_t USRRDY5:1; /*!< bit: 5 Channel 5 User Ready */
- uint32_t USRRDY6:1; /*!< bit: 6 Channel 6 User Ready */
- uint32_t USRRDY7:1; /*!< bit: 7 Channel 7 User Ready */
- uint32_t CHBUSY0:1; /*!< bit: 8 Channel 0 Busy */
- uint32_t CHBUSY1:1; /*!< bit: 9 Channel 1 Busy */
- uint32_t CHBUSY2:1; /*!< bit: 10 Channel 2 Busy */
- uint32_t CHBUSY3:1; /*!< bit: 11 Channel 3 Busy */
- uint32_t CHBUSY4:1; /*!< bit: 12 Channel 4 Busy */
- uint32_t CHBUSY5:1; /*!< bit: 13 Channel 5 Busy */
- uint32_t CHBUSY6:1; /*!< bit: 14 Channel 6 Busy */
- uint32_t CHBUSY7:1; /*!< bit: 15 Channel 7 Busy */
- uint32_t USRRDY8:1; /*!< bit: 16 Channel 8 User Ready */
- uint32_t USRRDY9:1; /*!< bit: 17 Channel 9 User Ready */
- uint32_t USRRDY10:1; /*!< bit: 18 Channel 10 User Ready */
- uint32_t USRRDY11:1; /*!< bit: 19 Channel 11 User Ready */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t CHBUSY8:1; /*!< bit: 24 Channel 8 Busy */
- uint32_t CHBUSY9:1; /*!< bit: 25 Channel 9 Busy */
- uint32_t CHBUSY10:1; /*!< bit: 26 Channel 10 Busy */
- uint32_t CHBUSY11:1; /*!< bit: 27 Channel 11 Busy */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t USRRDY:8; /*!< bit: 0.. 7 Channel x User Ready */
- uint32_t CHBUSY:8; /*!< bit: 8..15 Channel x Busy */
- uint32_t USRRDYp8:4; /*!< bit: 16..19 Channel x+8 User Ready */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t CHBUSYp8:4; /*!< bit: 24..27 Channel x+8 Busy */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t USRRDY0:1; /*!< bit: 0 Channel 0 User Ready */
+ uint32_t USRRDY1:1; /*!< bit: 1 Channel 1 User Ready */
+ uint32_t USRRDY2:1; /*!< bit: 2 Channel 2 User Ready */
+ uint32_t USRRDY3:1; /*!< bit: 3 Channel 3 User Ready */
+ uint32_t USRRDY4:1; /*!< bit: 4 Channel 4 User Ready */
+ uint32_t USRRDY5:1; /*!< bit: 5 Channel 5 User Ready */
+ uint32_t USRRDY6:1; /*!< bit: 6 Channel 6 User Ready */
+ uint32_t USRRDY7:1; /*!< bit: 7 Channel 7 User Ready */
+ uint32_t CHBUSY0:1; /*!< bit: 8 Channel 0 Busy */
+ uint32_t CHBUSY1:1; /*!< bit: 9 Channel 1 Busy */
+ uint32_t CHBUSY2:1; /*!< bit: 10 Channel 2 Busy */
+ uint32_t CHBUSY3:1; /*!< bit: 11 Channel 3 Busy */
+ uint32_t CHBUSY4:1; /*!< bit: 12 Channel 4 Busy */
+ uint32_t CHBUSY5:1; /*!< bit: 13 Channel 5 Busy */
+ uint32_t CHBUSY6:1; /*!< bit: 14 Channel 6 Busy */
+ uint32_t CHBUSY7:1; /*!< bit: 15 Channel 7 Busy */
+ uint32_t USRRDY8:1; /*!< bit: 16 Channel 8 User Ready */
+ uint32_t USRRDY9:1; /*!< bit: 17 Channel 9 User Ready */
+ uint32_t USRRDY10:1; /*!< bit: 18 Channel 10 User Ready */
+ uint32_t USRRDY11:1; /*!< bit: 19 Channel 11 User Ready */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t CHBUSY8:1; /*!< bit: 24 Channel 8 Busy */
+ uint32_t CHBUSY9:1; /*!< bit: 25 Channel 9 Busy */
+ uint32_t CHBUSY10:1; /*!< bit: 26 Channel 10 Busy */
+ uint32_t CHBUSY11:1; /*!< bit: 27 Channel 11 Busy */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t USRRDY:8; /*!< bit: 0.. 7 Channel x User Ready */
+ uint32_t CHBUSY:8; /*!< bit: 8..15 Channel x Busy */
+ uint32_t USRRDYp8:4; /*!< bit: 16..19 Channel x+8 User Ready */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t CHBUSYp8:4; /*!< bit: 24..27 Channel x+8 Busy */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} EVSYS_CHSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -266,43 +266,43 @@ typedef union {
/* -------- EVSYS_INTENCLR : (EVSYS Offset: 0x10) (R/W 32) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */
- uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */
- uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */
- uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */
- uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */
- uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */
- uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */
- uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */
- uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection Interrupt Enable */
- uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection Interrupt Enable */
- uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection Interrupt Enable */
- uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection Interrupt Enable */
- uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection Interrupt Enable */
- uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection Interrupt Enable */
- uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection Interrupt Enable */
- uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection Interrupt Enable */
- uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun Interrupt Enable */
- uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun Interrupt Enable */
- uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun Interrupt Enable */
- uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun Interrupt Enable */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */
- uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */
- uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */
- uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun Interrupt Enable */
- uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection Interrupt Enable */
- uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun Interrupt Enable */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection Interrupt Enable */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */
+ uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */
+ uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */
+ uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */
+ uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */
+ uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */
+ uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */
+ uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */
+ uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection Interrupt Enable */
+ uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection Interrupt Enable */
+ uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection Interrupt Enable */
+ uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection Interrupt Enable */
+ uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection Interrupt Enable */
+ uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection Interrupt Enable */
+ uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection Interrupt Enable */
+ uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection Interrupt Enable */
+ uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun Interrupt Enable */
+ uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun Interrupt Enable */
+ uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun Interrupt Enable */
+ uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun Interrupt Enable */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */
+ uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */
+ uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */
+ uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun Interrupt Enable */
+ uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection Interrupt Enable */
+ uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun Interrupt Enable */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection Interrupt Enable */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} EVSYS_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -374,43 +374,43 @@ typedef union {
/* -------- EVSYS_INTENSET : (EVSYS Offset: 0x14) (R/W 32) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */
- uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */
- uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */
- uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */
- uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */
- uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */
- uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */
- uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */
- uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection Interrupt Enable */
- uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection Interrupt Enable */
- uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection Interrupt Enable */
- uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection Interrupt Enable */
- uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection Interrupt Enable */
- uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection Interrupt Enable */
- uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection Interrupt Enable */
- uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection Interrupt Enable */
- uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun Interrupt Enable */
- uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun Interrupt Enable */
- uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun Interrupt Enable */
- uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun Interrupt Enable */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */
- uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */
- uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */
- uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun Interrupt Enable */
- uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection Interrupt Enable */
- uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun Interrupt Enable */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection Interrupt Enable */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */
+ uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */
+ uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */
+ uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */
+ uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */
+ uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */
+ uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */
+ uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */
+ uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection Interrupt Enable */
+ uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection Interrupt Enable */
+ uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection Interrupt Enable */
+ uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection Interrupt Enable */
+ uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection Interrupt Enable */
+ uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection Interrupt Enable */
+ uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection Interrupt Enable */
+ uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection Interrupt Enable */
+ uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun Interrupt Enable */
+ uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun Interrupt Enable */
+ uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun Interrupt Enable */
+ uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun Interrupt Enable */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */
+ uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */
+ uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */
+ uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun Interrupt Enable */
+ uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection Interrupt Enable */
+ uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun Interrupt Enable */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection Interrupt Enable */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} EVSYS_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -482,43 +482,43 @@ typedef union {
/* -------- EVSYS_INTFLAG : (EVSYS Offset: 0x18) (R/W 32) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun */
- uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun */
- uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun */
- uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun */
- uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun */
- uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun */
- uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun */
- uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun */
- uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection */
- uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection */
- uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection */
- uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection */
- uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection */
- uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection */
- uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection */
- uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection */
- uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun */
- uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun */
- uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun */
- uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection */
- uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection */
- uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection */
- uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun */
- uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection */
- uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun */
+ uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun */
+ uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun */
+ uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun */
+ uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun */
+ uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun */
+ uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun */
+ uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun */
+ uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection */
+ uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection */
+ uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection */
+ uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection */
+ uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection */
+ uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection */
+ uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection */
+ uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection */
+ uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun */
+ uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun */
+ uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun */
+ uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection */
+ uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection */
+ uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection */
+ uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun */
+ uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection */
+ uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} EVSYS_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -590,15 +590,15 @@ typedef union {
/** \brief EVSYS hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __O EVSYS_CTRL_Type CTRL; /**< \brief Offset: 0x00 ( /W 8) Control */
- RoReg8 Reserved1[0x3];
- __IO EVSYS_CHANNEL_Type CHANNEL; /**< \brief Offset: 0x04 (R/W 32) Channel */
- __IO EVSYS_USER_Type USER; /**< \brief Offset: 0x08 (R/W 16) User Multiplexer */
- RoReg8 Reserved2[0x2];
- __I EVSYS_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x0C (R/ 32) Channel Status */
- __IO EVSYS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x10 (R/W 32) Interrupt Enable Clear */
- __IO EVSYS_INTENSET_Type INTENSET; /**< \brief Offset: 0x14 (R/W 32) Interrupt Enable Set */
- __IO EVSYS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 32) Interrupt Flag Status and Clear */
+ __O EVSYS_CTRL_Type CTRL; /**< \brief Offset: 0x00 ( /W 8) Control */
+ RoReg8 Reserved1[0x3];
+ __IO EVSYS_CHANNEL_Type CHANNEL; /**< \brief Offset: 0x04 (R/W 32) Channel */
+ __IO EVSYS_USER_Type USER; /**< \brief Offset: 0x08 (R/W 16) User Multiplexer */
+ RoReg8 Reserved2[0x2];
+ __I EVSYS_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x0C (R/ 32) Channel Status */
+ __IO EVSYS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x10 (R/W 32) Interrupt Enable Clear */
+ __IO EVSYS_INTENSET_Type INTENSET; /**< \brief Offset: 0x14 (R/W 32) Interrupt Enable Set */
+ __IO EVSYS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 32) Interrupt Flag Status and Clear */
} Evsys;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_gclk.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_gclk.h
index 77f17fb677a..2d2348f3c5b 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_gclk.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_gclk.h
@@ -59,11 +59,11 @@
/* -------- GCLK_CTRL : (GCLK Offset: 0x0) (R/W 8) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t SWRST:1; /*!< bit: 0 Software Reset */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} GCLK_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -77,11 +77,11 @@ typedef union {
/* -------- GCLK_STATUS : (GCLK Offset: 0x1) (R/ 8) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t :7; /*!< bit: 0.. 6 Reserved */
- uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy Status */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t :7; /*!< bit: 0.. 6 Reserved */
+ uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy Status */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} GCLK_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -95,15 +95,15 @@ typedef union {
/* -------- GCLK_CLKCTRL : (GCLK Offset: 0x2) (R/W 16) Generic Clock Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t ID:6; /*!< bit: 0.. 5 Generic Clock Selection ID */
- uint16_t :2; /*!< bit: 6.. 7 Reserved */
- uint16_t GEN:4; /*!< bit: 8..11 Generic Clock Generator */
- uint16_t :2; /*!< bit: 12..13 Reserved */
- uint16_t CLKEN:1; /*!< bit: 14 Clock Enable */
- uint16_t WRTLOCK:1; /*!< bit: 15 Write Lock */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t ID:6; /*!< bit: 0.. 5 Generic Clock Selection ID */
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ uint16_t GEN:4; /*!< bit: 8..11 Generic Clock Generator */
+ uint16_t :2; /*!< bit: 12..13 Reserved */
+ uint16_t CLKEN:1; /*!< bit: 14 Clock Enable */
+ uint16_t WRTLOCK:1; /*!< bit: 15 Write Lock */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} GCLK_CLKCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -215,20 +215,20 @@ typedef union {
/* -------- GCLK_GENCTRL : (GCLK Offset: 0x4) (R/W 32) Generic Clock Generator Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t ID:4; /*!< bit: 0.. 3 Generic Clock Generator Selection */
- uint32_t :4; /*!< bit: 4.. 7 Reserved */
- uint32_t SRC:5; /*!< bit: 8..12 Source Select */
- uint32_t :3; /*!< bit: 13..15 Reserved */
- uint32_t GENEN:1; /*!< bit: 16 Generic Clock Generator Enable */
- uint32_t IDC:1; /*!< bit: 17 Improve Duty Cycle */
- uint32_t OOV:1; /*!< bit: 18 Output Off Value */
- uint32_t OE:1; /*!< bit: 19 Output Enable */
- uint32_t DIVSEL:1; /*!< bit: 20 Divide Selection */
- uint32_t RUNSTDBY:1; /*!< bit: 21 Run in Standby */
- uint32_t :10; /*!< bit: 22..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t ID:4; /*!< bit: 0.. 3 Generic Clock Generator Selection */
+ uint32_t :4; /*!< bit: 4.. 7 Reserved */
+ uint32_t SRC:5; /*!< bit: 8..12 Source Select */
+ uint32_t :3; /*!< bit: 13..15 Reserved */
+ uint32_t GENEN:1; /*!< bit: 16 Generic Clock Generator Enable */
+ uint32_t IDC:1; /*!< bit: 17 Improve Duty Cycle */
+ uint32_t OOV:1; /*!< bit: 18 Output Off Value */
+ uint32_t OE:1; /*!< bit: 19 Output Enable */
+ uint32_t DIVSEL:1; /*!< bit: 20 Divide Selection */
+ uint32_t RUNSTDBY:1; /*!< bit: 21 Run in Standby */
+ uint32_t :10; /*!< bit: 22..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} GCLK_GENCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -276,13 +276,13 @@ typedef union {
/* -------- GCLK_GENDIV : (GCLK Offset: 0x8) (R/W 32) Generic Clock Generator Division -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t ID:4; /*!< bit: 0.. 3 Generic Clock Generator Selection */
- uint32_t :4; /*!< bit: 4.. 7 Reserved */
- uint32_t DIV:16; /*!< bit: 8..23 Division Factor */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t ID:4; /*!< bit: 0.. 3 Generic Clock Generator Selection */
+ uint32_t :4; /*!< bit: 4.. 7 Reserved */
+ uint32_t DIV:16; /*!< bit: 8..23 Division Factor */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} GCLK_GENDIV_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -300,11 +300,11 @@ typedef union {
/** \brief GCLK hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO GCLK_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */
- __I GCLK_STATUS_Type STATUS; /**< \brief Offset: 0x1 (R/ 8) Status */
- __IO GCLK_CLKCTRL_Type CLKCTRL; /**< \brief Offset: 0x2 (R/W 16) Generic Clock Control */
- __IO GCLK_GENCTRL_Type GENCTRL; /**< \brief Offset: 0x4 (R/W 32) Generic Clock Generator Control */
- __IO GCLK_GENDIV_Type GENDIV; /**< \brief Offset: 0x8 (R/W 32) Generic Clock Generator Division */
+ __IO GCLK_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */
+ __I GCLK_STATUS_Type STATUS; /**< \brief Offset: 0x1 (R/ 8) Status */
+ __IO GCLK_CLKCTRL_Type CLKCTRL; /**< \brief Offset: 0x2 (R/W 16) Generic Clock Control */
+ __IO GCLK_GENCTRL_Type GENCTRL; /**< \brief Offset: 0x4 (R/W 32) Generic Clock Generator Control */
+ __IO GCLK_GENDIV_Type GENDIV; /**< \brief Offset: 0x8 (R/W 32) Generic Clock Generator Division */
} Gclk;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_hmatrixb.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_hmatrixb.h
index 0b4c0100f24..21647a68bfa 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_hmatrixb.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_hmatrixb.h
@@ -59,7 +59,7 @@
/* -------- HMATRIXB_PRAS : (HMATRIXB Offset: 0x080) (R/W 32) PRS Priority A for Slave -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} HMATRIXB_PRAS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -71,7 +71,7 @@ typedef union {
/* -------- HMATRIXB_PRBS : (HMATRIXB Offset: 0x084) (R/W 32) PRS Priority B for Slave -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} HMATRIXB_PRBS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -83,10 +83,10 @@ typedef union {
/* -------- HMATRIXB_SFR : (HMATRIXB Offset: 0x110) (R/W 32) Special Function -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SFR:32; /*!< bit: 0..31 Special Function Register */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SFR:32; /*!< bit: 0..31 Special Function Register */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} HMATRIXB_SFR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -101,18 +101,18 @@ typedef union {
/** \brief HmatrixbPrs hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO HMATRIXB_PRAS_Type PRAS; /**< \brief Offset: 0x000 (R/W 32) Priority A for Slave */
- __IO HMATRIXB_PRBS_Type PRBS; /**< \brief Offset: 0x004 (R/W 32) Priority B for Slave */
+ __IO HMATRIXB_PRAS_Type PRAS; /**< \brief Offset: 0x000 (R/W 32) Priority A for Slave */
+ __IO HMATRIXB_PRBS_Type PRBS; /**< \brief Offset: 0x004 (R/W 32) Priority B for Slave */
} HmatrixbPrs;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief HMATRIXB hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- RoReg8 Reserved1[0x80];
- HmatrixbPrs Prs[16]; /**< \brief Offset: 0x080 HmatrixbPrs groups */
- RoReg8 Reserved2[0x10];
- __IO HMATRIXB_SFR_Type SFR[16]; /**< \brief Offset: 0x110 (R/W 32) Special Function */
+ RoReg8 Reserved1[0x80];
+ HmatrixbPrs Prs[16]; /**< \brief Offset: 0x080 HmatrixbPrs groups */
+ RoReg8 Reserved2[0x10];
+ __IO HMATRIXB_SFR_Type SFR[16]; /**< \brief Offset: 0x110 (R/W 32) Special Function */
} Hmatrixb;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_i2s.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_i2s.h
index d10f5d44a56..da7b7a0e3ef 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_i2s.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_i2s.h
@@ -59,22 +59,22 @@
/* -------- I2S_CTRLA : (I2S Offset: 0x00) (R/W 8) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t SWRST:1; /*!< bit: 0 Software Reset */
- uint8_t ENABLE:1; /*!< bit: 1 Enable */
- uint8_t CKEN0:1; /*!< bit: 2 Clock Unit 0 Enable */
- uint8_t CKEN1:1; /*!< bit: 3 Clock Unit 1 Enable */
- uint8_t SEREN0:1; /*!< bit: 4 Serializer 0 Enable */
- uint8_t SEREN1:1; /*!< bit: 5 Serializer 1 Enable */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t :2; /*!< bit: 0.. 1 Reserved */
- uint8_t CKEN:2; /*!< bit: 2.. 3 Clock Unit x Enable */
- uint8_t SEREN:2; /*!< bit: 4.. 5 Serializer x Enable */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable */
+ uint8_t CKEN0:1; /*!< bit: 2 Clock Unit 0 Enable */
+ uint8_t CKEN1:1; /*!< bit: 3 Clock Unit 1 Enable */
+ uint8_t SEREN0:1; /*!< bit: 4 Serializer 0 Enable */
+ uint8_t SEREN1:1; /*!< bit: 5 Serializer 1 Enable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t :2; /*!< bit: 0.. 1 Reserved */
+ uint8_t CKEN:2; /*!< bit: 2.. 3 Clock Unit x Enable */
+ uint8_t SEREN:2; /*!< bit: 4.. 5 Serializer x Enable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} I2S_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -104,26 +104,26 @@ typedef union {
/* -------- I2S_CLKCTRL : (I2S Offset: 0x04) (R/W 32) Clock Unit n Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SLOTSIZE:2; /*!< bit: 0.. 1 Slot Size */
- uint32_t NBSLOTS:3; /*!< bit: 2.. 4 Number of Slots in Frame */
- uint32_t FSWIDTH:2; /*!< bit: 5.. 6 Frame Sync Width */
- uint32_t BITDELAY:1; /*!< bit: 7 Data Delay from Frame Sync */
- uint32_t FSSEL:1; /*!< bit: 8 Frame Sync Select */
- uint32_t :2; /*!< bit: 9..10 Reserved */
- uint32_t FSINV:1; /*!< bit: 11 Frame Sync Invert */
- uint32_t SCKSEL:1; /*!< bit: 12 Serial Clock Select */
- uint32_t :3; /*!< bit: 13..15 Reserved */
- uint32_t MCKSEL:1; /*!< bit: 16 Master Clock Select */
- uint32_t :1; /*!< bit: 17 Reserved */
- uint32_t MCKEN:1; /*!< bit: 18 Master Clock Enable */
- uint32_t MCKDIV:5; /*!< bit: 19..23 Master Clock Division Factor */
- uint32_t MCKOUTDIV:5; /*!< bit: 24..28 Master Clock Output Division Factor */
- uint32_t FSOUTINV:1; /*!< bit: 29 Frame Sync Output Invert */
- uint32_t SCKOUTINV:1; /*!< bit: 30 Serial Clock Output Invert */
- uint32_t MCKOUTINV:1; /*!< bit: 31 Master Clock Output Invert */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SLOTSIZE:2; /*!< bit: 0.. 1 Slot Size */
+ uint32_t NBSLOTS:3; /*!< bit: 2.. 4 Number of Slots in Frame */
+ uint32_t FSWIDTH:2; /*!< bit: 5.. 6 Frame Sync Width */
+ uint32_t BITDELAY:1; /*!< bit: 7 Data Delay from Frame Sync */
+ uint32_t FSSEL:1; /*!< bit: 8 Frame Sync Select */
+ uint32_t :2; /*!< bit: 9..10 Reserved */
+ uint32_t FSINV:1; /*!< bit: 11 Frame Sync Invert */
+ uint32_t SCKSEL:1; /*!< bit: 12 Serial Clock Select */
+ uint32_t :3; /*!< bit: 13..15 Reserved */
+ uint32_t MCKSEL:1; /*!< bit: 16 Master Clock Select */
+ uint32_t :1; /*!< bit: 17 Reserved */
+ uint32_t MCKEN:1; /*!< bit: 18 Master Clock Enable */
+ uint32_t MCKDIV:5; /*!< bit: 19..23 Master Clock Division Factor */
+ uint32_t MCKOUTDIV:5; /*!< bit: 24..28 Master Clock Output Division Factor */
+ uint32_t FSOUTINV:1; /*!< bit: 29 Frame Sync Output Invert */
+ uint32_t SCKOUTINV:1; /*!< bit: 30 Serial Clock Output Invert */
+ uint32_t MCKOUTINV:1; /*!< bit: 31 Master Clock Output Invert */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} I2S_CLKCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -200,31 +200,31 @@ typedef union {
/* -------- I2S_INTENCLR : (I2S Offset: 0x0C) (R/W 16) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 Interrupt Enable */
- uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 Interrupt Enable */
- uint16_t :2; /*!< bit: 2.. 3 Reserved */
- uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 Interrupt Enable */
- uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 Interrupt Enable */
- uint16_t :2; /*!< bit: 6.. 7 Reserved */
- uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 Interrupt Enable */
- uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 Interrupt Enable */
- uint16_t :2; /*!< bit: 10..11 Reserved */
- uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 Interrupt Enable */
- uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 Interrupt Enable */
- uint16_t :2; /*!< bit: 14..15 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x Interrupt Enable */
- uint16_t :2; /*!< bit: 2.. 3 Reserved */
- uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x Interrupt Enable */
- uint16_t :2; /*!< bit: 6.. 7 Reserved */
- uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x Interrupt Enable */
- uint16_t :2; /*!< bit: 10..11 Reserved */
- uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x Interrupt Enable */
- uint16_t :2; /*!< bit: 14..15 Reserved */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 Interrupt Enable */
+ uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 Interrupt Enable */
+ uint16_t :2; /*!< bit: 2.. 3 Reserved */
+ uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 Interrupt Enable */
+ uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 Interrupt Enable */
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 Interrupt Enable */
+ uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 Interrupt Enable */
+ uint16_t :2; /*!< bit: 10..11 Reserved */
+ uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 Interrupt Enable */
+ uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 Interrupt Enable */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x Interrupt Enable */
+ uint16_t :2; /*!< bit: 2.. 3 Reserved */
+ uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x Interrupt Enable */
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x Interrupt Enable */
+ uint16_t :2; /*!< bit: 10..11 Reserved */
+ uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x Interrupt Enable */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
} I2S_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -264,31 +264,31 @@ typedef union {
/* -------- I2S_INTENSET : (I2S Offset: 0x10) (R/W 16) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 Interrupt Enable */
- uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 Interrupt Enable */
- uint16_t :2; /*!< bit: 2.. 3 Reserved */
- uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 Interrupt Enable */
- uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 Interrupt Enable */
- uint16_t :2; /*!< bit: 6.. 7 Reserved */
- uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 Interrupt Enable */
- uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 Interrupt Enable */
- uint16_t :2; /*!< bit: 10..11 Reserved */
- uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 Interrupt Enable */
- uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 Interrupt Enable */
- uint16_t :2; /*!< bit: 14..15 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x Interrupt Enable */
- uint16_t :2; /*!< bit: 2.. 3 Reserved */
- uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x Interrupt Enable */
- uint16_t :2; /*!< bit: 6.. 7 Reserved */
- uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x Interrupt Enable */
- uint16_t :2; /*!< bit: 10..11 Reserved */
- uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x Interrupt Enable */
- uint16_t :2; /*!< bit: 14..15 Reserved */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 Interrupt Enable */
+ uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 Interrupt Enable */
+ uint16_t :2; /*!< bit: 2.. 3 Reserved */
+ uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 Interrupt Enable */
+ uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 Interrupt Enable */
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 Interrupt Enable */
+ uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 Interrupt Enable */
+ uint16_t :2; /*!< bit: 10..11 Reserved */
+ uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 Interrupt Enable */
+ uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 Interrupt Enable */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x Interrupt Enable */
+ uint16_t :2; /*!< bit: 2.. 3 Reserved */
+ uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x Interrupt Enable */
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x Interrupt Enable */
+ uint16_t :2; /*!< bit: 10..11 Reserved */
+ uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x Interrupt Enable */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
} I2S_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -328,31 +328,31 @@ typedef union {
/* -------- I2S_INTFLAG : (I2S Offset: 0x14) (R/W 16) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 */
- uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 */
- uint16_t :2; /*!< bit: 2.. 3 Reserved */
- uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 */
- uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 */
- uint16_t :2; /*!< bit: 6.. 7 Reserved */
- uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 */
- uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 */
- uint16_t :2; /*!< bit: 10..11 Reserved */
- uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 */
- uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 */
- uint16_t :2; /*!< bit: 14..15 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x */
- uint16_t :2; /*!< bit: 2.. 3 Reserved */
- uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x */
- uint16_t :2; /*!< bit: 6.. 7 Reserved */
- uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x */
- uint16_t :2; /*!< bit: 10..11 Reserved */
- uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x */
- uint16_t :2; /*!< bit: 14..15 Reserved */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 */
+ uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 */
+ uint16_t :2; /*!< bit: 2.. 3 Reserved */
+ uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 */
+ uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 */
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 */
+ uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 */
+ uint16_t :2; /*!< bit: 10..11 Reserved */
+ uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 */
+ uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x */
+ uint16_t :2; /*!< bit: 2.. 3 Reserved */
+ uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x */
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x */
+ uint16_t :2; /*!< bit: 10..11 Reserved */
+ uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
} I2S_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -392,27 +392,27 @@ typedef union {
/* -------- I2S_SYNCBUSY : (I2S Offset: 0x18) (R/ 16) Synchronization Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Status */
- uint16_t ENABLE:1; /*!< bit: 1 Enable Synchronization Status */
- uint16_t CKEN0:1; /*!< bit: 2 Clock Unit 0 Enable Synchronization Status */
- uint16_t CKEN1:1; /*!< bit: 3 Clock Unit 1 Enable Synchronization Status */
- uint16_t SEREN0:1; /*!< bit: 4 Serializer 0 Enable Synchronization Status */
- uint16_t SEREN1:1; /*!< bit: 5 Serializer 1 Enable Synchronization Status */
- uint16_t :2; /*!< bit: 6.. 7 Reserved */
- uint16_t DATA0:1; /*!< bit: 8 Data 0 Synchronization Status */
- uint16_t DATA1:1; /*!< bit: 9 Data 1 Synchronization Status */
- uint16_t :6; /*!< bit: 10..15 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint16_t :2; /*!< bit: 0.. 1 Reserved */
- uint16_t CKEN:2; /*!< bit: 2.. 3 Clock Unit x Enable Synchronization Status */
- uint16_t SEREN:2; /*!< bit: 4.. 5 Serializer x Enable Synchronization Status */
- uint16_t :2; /*!< bit: 6.. 7 Reserved */
- uint16_t DATA:2; /*!< bit: 8.. 9 Data x Synchronization Status */
- uint16_t :6; /*!< bit: 10..15 Reserved */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Status */
+ uint16_t ENABLE:1; /*!< bit: 1 Enable Synchronization Status */
+ uint16_t CKEN0:1; /*!< bit: 2 Clock Unit 0 Enable Synchronization Status */
+ uint16_t CKEN1:1; /*!< bit: 3 Clock Unit 1 Enable Synchronization Status */
+ uint16_t SEREN0:1; /*!< bit: 4 Serializer 0 Enable Synchronization Status */
+ uint16_t SEREN1:1; /*!< bit: 5 Serializer 1 Enable Synchronization Status */
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ uint16_t DATA0:1; /*!< bit: 8 Data 0 Synchronization Status */
+ uint16_t DATA1:1; /*!< bit: 9 Data 1 Synchronization Status */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t :2; /*!< bit: 0.. 1 Reserved */
+ uint16_t CKEN:2; /*!< bit: 2.. 3 Clock Unit x Enable Synchronization Status */
+ uint16_t SEREN:2; /*!< bit: 4.. 5 Serializer x Enable Synchronization Status */
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ uint16_t DATA:2; /*!< bit: 8.. 9 Data x Synchronization Status */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
} I2S_SYNCBUSY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -449,37 +449,37 @@ typedef union {
/* -------- I2S_SERCTRL : (I2S Offset: 0x20) (R/W 32) Serializer n Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SERMODE:2; /*!< bit: 0.. 1 Serializer Mode */
- uint32_t TXDEFAULT:2; /*!< bit: 2.. 3 Line Default Line when Slot Disabled */
- uint32_t TXSAME:1; /*!< bit: 4 Transmit Data when Underrun */
- uint32_t CLKSEL:1; /*!< bit: 5 Clock Unit Selection */
- uint32_t :1; /*!< bit: 6 Reserved */
- uint32_t SLOTADJ:1; /*!< bit: 7 Data Slot Formatting Adjust */
- uint32_t DATASIZE:3; /*!< bit: 8..10 Data Word Size */
- uint32_t :1; /*!< bit: 11 Reserved */
- uint32_t WORDADJ:1; /*!< bit: 12 Data Word Formatting Adjust */
- uint32_t EXTEND:2; /*!< bit: 13..14 Data Formatting Bit Extension */
- uint32_t BITREV:1; /*!< bit: 15 Data Formatting Bit Reverse */
- uint32_t SLOTDIS0:1; /*!< bit: 16 Slot 0 Disabled for this Serializer */
- uint32_t SLOTDIS1:1; /*!< bit: 17 Slot 1 Disabled for this Serializer */
- uint32_t SLOTDIS2:1; /*!< bit: 18 Slot 2 Disabled for this Serializer */
- uint32_t SLOTDIS3:1; /*!< bit: 19 Slot 3 Disabled for this Serializer */
- uint32_t SLOTDIS4:1; /*!< bit: 20 Slot 4 Disabled for this Serializer */
- uint32_t SLOTDIS5:1; /*!< bit: 21 Slot 5 Disabled for this Serializer */
- uint32_t SLOTDIS6:1; /*!< bit: 22 Slot 6 Disabled for this Serializer */
- uint32_t SLOTDIS7:1; /*!< bit: 23 Slot 7 Disabled for this Serializer */
- uint32_t MONO:1; /*!< bit: 24 Mono Mode */
- uint32_t DMA:1; /*!< bit: 25 Single or Multiple DMA Channels */
- uint32_t RXLOOP:1; /*!< bit: 26 Loop-back Test Mode */
- uint32_t :5; /*!< bit: 27..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :16; /*!< bit: 0..15 Reserved */
- uint32_t SLOTDIS:8; /*!< bit: 16..23 Slot x Disabled for this Serializer */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SERMODE:2; /*!< bit: 0.. 1 Serializer Mode */
+ uint32_t TXDEFAULT:2; /*!< bit: 2.. 3 Line Default Line when Slot Disabled */
+ uint32_t TXSAME:1; /*!< bit: 4 Transmit Data when Underrun */
+ uint32_t CLKSEL:1; /*!< bit: 5 Clock Unit Selection */
+ uint32_t :1; /*!< bit: 6 Reserved */
+ uint32_t SLOTADJ:1; /*!< bit: 7 Data Slot Formatting Adjust */
+ uint32_t DATASIZE:3; /*!< bit: 8..10 Data Word Size */
+ uint32_t :1; /*!< bit: 11 Reserved */
+ uint32_t WORDADJ:1; /*!< bit: 12 Data Word Formatting Adjust */
+ uint32_t EXTEND:2; /*!< bit: 13..14 Data Formatting Bit Extension */
+ uint32_t BITREV:1; /*!< bit: 15 Data Formatting Bit Reverse */
+ uint32_t SLOTDIS0:1; /*!< bit: 16 Slot 0 Disabled for this Serializer */
+ uint32_t SLOTDIS1:1; /*!< bit: 17 Slot 1 Disabled for this Serializer */
+ uint32_t SLOTDIS2:1; /*!< bit: 18 Slot 2 Disabled for this Serializer */
+ uint32_t SLOTDIS3:1; /*!< bit: 19 Slot 3 Disabled for this Serializer */
+ uint32_t SLOTDIS4:1; /*!< bit: 20 Slot 4 Disabled for this Serializer */
+ uint32_t SLOTDIS5:1; /*!< bit: 21 Slot 5 Disabled for this Serializer */
+ uint32_t SLOTDIS6:1; /*!< bit: 22 Slot 6 Disabled for this Serializer */
+ uint32_t SLOTDIS7:1; /*!< bit: 23 Slot 7 Disabled for this Serializer */
+ uint32_t MONO:1; /*!< bit: 24 Mono Mode */
+ uint32_t DMA:1; /*!< bit: 25 Single or Multiple DMA Channels */
+ uint32_t RXLOOP:1; /*!< bit: 26 Loop-back Test Mode */
+ uint32_t :5; /*!< bit: 27..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :16; /*!< bit: 0..15 Reserved */
+ uint32_t SLOTDIS:8; /*!< bit: 16..23 Slot x Disabled for this Serializer */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} I2S_SERCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -602,10 +602,10 @@ typedef union {
/* -------- I2S_DATA : (I2S Offset: 0x30) (R/W 32) Data n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t DATA:32; /*!< bit: 0..31 Sample Data */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t DATA:32; /*!< bit: 0..31 Sample Data */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} I2S_DATA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -620,20 +620,20 @@ typedef union {
/** \brief I2S hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO I2S_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
- RoReg8 Reserved1[0x3];
- __IO I2S_CLKCTRL_Type CLKCTRL[2]; /**< \brief Offset: 0x04 (R/W 32) Clock Unit n Control */
- __IO I2S_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 16) Interrupt Enable Clear */
- RoReg8 Reserved2[0x2];
- __IO I2S_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 16) Interrupt Enable Set */
- RoReg8 Reserved3[0x2];
- __IO I2S_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 16) Interrupt Flag Status and Clear */
- RoReg8 Reserved4[0x2];
- __I I2S_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x18 (R/ 16) Synchronization Status */
- RoReg8 Reserved5[0x6];
- __IO I2S_SERCTRL_Type SERCTRL[2]; /**< \brief Offset: 0x20 (R/W 32) Serializer n Control */
- RoReg8 Reserved6[0x8];
- __IO I2S_DATA_Type DATA[2]; /**< \brief Offset: 0x30 (R/W 32) Data n */
+ __IO I2S_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
+ RoReg8 Reserved1[0x3];
+ __IO I2S_CLKCTRL_Type CLKCTRL[2]; /**< \brief Offset: 0x04 (R/W 32) Clock Unit n Control */
+ __IO I2S_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 16) Interrupt Enable Clear */
+ RoReg8 Reserved2[0x2];
+ __IO I2S_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 16) Interrupt Enable Set */
+ RoReg8 Reserved3[0x2];
+ __IO I2S_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 16) Interrupt Flag Status and Clear */
+ RoReg8 Reserved4[0x2];
+ __I I2S_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x18 (R/ 16) Synchronization Status */
+ RoReg8 Reserved5[0x6];
+ __IO I2S_SERCTRL_Type SERCTRL[2]; /**< \brief Offset: 0x20 (R/W 32) Serializer n Control */
+ RoReg8 Reserved6[0x8];
+ __IO I2S_DATA_Type DATA[2]; /**< \brief Offset: 0x30 (R/W 32) Data n */
} I2s;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_mtb.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_mtb.h
index 579300a0caf..75c35112211 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_mtb.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_mtb.h
@@ -59,12 +59,12 @@
/* -------- MTB_POSITION : (MTB Offset: 0x000) (R/W 32) MTB Position -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t :2; /*!< bit: 0.. 1 Reserved */
- uint32_t WRAP:1; /*!< bit: 2 Pointer Value Wraps */
- uint32_t POINTER:29; /*!< bit: 3..31 Trace Packet Location Pointer */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t :2; /*!< bit: 0.. 1 Reserved */
+ uint32_t WRAP:1; /*!< bit: 2 Pointer Value Wraps */
+ uint32_t POINTER:29; /*!< bit: 3..31 Trace Packet Location Pointer */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_POSITION_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -80,17 +80,17 @@ typedef union {
/* -------- MTB_MASTER : (MTB Offset: 0x004) (R/W 32) MTB Master -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t MASK:5; /*!< bit: 0.. 4 Maximum Value of the Trace Buffer in SRAM */
- uint32_t TSTARTEN:1; /*!< bit: 5 Trace Start Input Enable */
- uint32_t TSTOPEN:1; /*!< bit: 6 Trace Stop Input Enable */
- uint32_t SFRWPRIV:1; /*!< bit: 7 Special Function Register Write Privilege */
- uint32_t RAMPRIV:1; /*!< bit: 8 SRAM Privilege */
- uint32_t HALTREQ:1; /*!< bit: 9 Halt Request */
- uint32_t :21; /*!< bit: 10..30 Reserved */
- uint32_t EN:1; /*!< bit: 31 Main Trace Enable */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t MASK:5; /*!< bit: 0.. 4 Maximum Value of the Trace Buffer in SRAM */
+ uint32_t TSTARTEN:1; /*!< bit: 5 Trace Start Input Enable */
+ uint32_t TSTOPEN:1; /*!< bit: 6 Trace Stop Input Enable */
+ uint32_t SFRWPRIV:1; /*!< bit: 7 Special Function Register Write Privilege */
+ uint32_t RAMPRIV:1; /*!< bit: 8 SRAM Privilege */
+ uint32_t HALTREQ:1; /*!< bit: 9 Halt Request */
+ uint32_t :21; /*!< bit: 10..30 Reserved */
+ uint32_t EN:1; /*!< bit: 31 Main Trace Enable */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_MASTER_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -117,13 +117,13 @@ typedef union {
/* -------- MTB_FLOW : (MTB Offset: 0x008) (R/W 32) MTB Flow -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t AUTOSTOP:1; /*!< bit: 0 Auto Stop Tracing */
- uint32_t AUTOHALT:1; /*!< bit: 1 Auto Halt Request */
- uint32_t :1; /*!< bit: 2 Reserved */
- uint32_t WATERMARK:29; /*!< bit: 3..31 Watermark value */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t AUTOSTOP:1; /*!< bit: 0 Auto Stop Tracing */
+ uint32_t AUTOHALT:1; /*!< bit: 1 Auto Halt Request */
+ uint32_t :1; /*!< bit: 2 Reserved */
+ uint32_t WATERMARK:29; /*!< bit: 3..31 Watermark value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_FLOW_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -142,7 +142,7 @@ typedef union {
/* -------- MTB_BASE : (MTB Offset: 0x00C) (R/ 32) MTB Base -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_BASE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -152,7 +152,7 @@ typedef union {
/* -------- MTB_ITCTRL : (MTB Offset: 0xF00) (R/W 32) MTB Integration Mode Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_ITCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -162,7 +162,7 @@ typedef union {
/* -------- MTB_CLAIMSET : (MTB Offset: 0xFA0) (R/W 32) MTB Claim Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_CLAIMSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -172,7 +172,7 @@ typedef union {
/* -------- MTB_CLAIMCLR : (MTB Offset: 0xFA4) (R/W 32) MTB Claim Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_CLAIMCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -182,7 +182,7 @@ typedef union {
/* -------- MTB_LOCKACCESS : (MTB Offset: 0xFB0) (R/W 32) MTB Lock Access -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_LOCKACCESS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -192,7 +192,7 @@ typedef union {
/* -------- MTB_LOCKSTATUS : (MTB Offset: 0xFB4) (R/ 32) MTB Lock Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_LOCKSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -202,7 +202,7 @@ typedef union {
/* -------- MTB_AUTHSTATUS : (MTB Offset: 0xFB8) (R/ 32) MTB Authentication Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_AUTHSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -212,7 +212,7 @@ typedef union {
/* -------- MTB_DEVARCH : (MTB Offset: 0xFBC) (R/ 32) MTB Device Architecture -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_DEVARCH_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -222,7 +222,7 @@ typedef union {
/* -------- MTB_DEVID : (MTB Offset: 0xFC8) (R/ 32) MTB Device Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_DEVID_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -232,7 +232,7 @@ typedef union {
/* -------- MTB_DEVTYPE : (MTB Offset: 0xFCC) (R/ 32) MTB Device Type -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_DEVTYPE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -242,7 +242,7 @@ typedef union {
/* -------- MTB_PID4 : (MTB Offset: 0xFD0) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_PID4_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -252,7 +252,7 @@ typedef union {
/* -------- MTB_PID5 : (MTB Offset: 0xFD4) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_PID5_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -262,7 +262,7 @@ typedef union {
/* -------- MTB_PID6 : (MTB Offset: 0xFD8) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_PID6_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -272,7 +272,7 @@ typedef union {
/* -------- MTB_PID7 : (MTB Offset: 0xFDC) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_PID7_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -282,7 +282,7 @@ typedef union {
/* -------- MTB_PID0 : (MTB Offset: 0xFE0) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_PID0_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -292,7 +292,7 @@ typedef union {
/* -------- MTB_PID1 : (MTB Offset: 0xFE4) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_PID1_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -302,7 +302,7 @@ typedef union {
/* -------- MTB_PID2 : (MTB Offset: 0xFE8) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_PID2_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -312,7 +312,7 @@ typedef union {
/* -------- MTB_PID3 : (MTB Offset: 0xFEC) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_PID3_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -322,7 +322,7 @@ typedef union {
/* -------- MTB_CID0 : (MTB Offset: 0xFF0) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_CID0_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -332,7 +332,7 @@ typedef union {
/* -------- MTB_CID1 : (MTB Offset: 0xFF4) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_CID1_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -342,7 +342,7 @@ typedef union {
/* -------- MTB_CID2 : (MTB Offset: 0xFF8) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_CID2_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -352,7 +352,7 @@ typedef union {
/* -------- MTB_CID3 : (MTB Offset: 0xFFC) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_CID3_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -362,35 +362,35 @@ typedef union {
/** \brief MTB hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO MTB_POSITION_Type POSITION; /**< \brief Offset: 0x000 (R/W 32) MTB Position */
- __IO MTB_MASTER_Type MASTER; /**< \brief Offset: 0x004 (R/W 32) MTB Master */
- __IO MTB_FLOW_Type FLOW; /**< \brief Offset: 0x008 (R/W 32) MTB Flow */
- __I MTB_BASE_Type BASE; /**< \brief Offset: 0x00C (R/ 32) MTB Base */
- RoReg8 Reserved1[0xEF0];
- __IO MTB_ITCTRL_Type ITCTRL; /**< \brief Offset: 0xF00 (R/W 32) MTB Integration Mode Control */
- RoReg8 Reserved2[0x9C];
- __IO MTB_CLAIMSET_Type CLAIMSET; /**< \brief Offset: 0xFA0 (R/W 32) MTB Claim Set */
- __IO MTB_CLAIMCLR_Type CLAIMCLR; /**< \brief Offset: 0xFA4 (R/W 32) MTB Claim Clear */
- RoReg8 Reserved3[0x8];
- __IO MTB_LOCKACCESS_Type LOCKACCESS; /**< \brief Offset: 0xFB0 (R/W 32) MTB Lock Access */
- __I MTB_LOCKSTATUS_Type LOCKSTATUS; /**< \brief Offset: 0xFB4 (R/ 32) MTB Lock Status */
- __I MTB_AUTHSTATUS_Type AUTHSTATUS; /**< \brief Offset: 0xFB8 (R/ 32) MTB Authentication Status */
- __I MTB_DEVARCH_Type DEVARCH; /**< \brief Offset: 0xFBC (R/ 32) MTB Device Architecture */
- RoReg8 Reserved4[0x8];
- __I MTB_DEVID_Type DEVID; /**< \brief Offset: 0xFC8 (R/ 32) MTB Device Configuration */
- __I MTB_DEVTYPE_Type DEVTYPE; /**< \brief Offset: 0xFCC (R/ 32) MTB Device Type */
- __I MTB_PID4_Type PID4; /**< \brief Offset: 0xFD0 (R/ 32) CoreSight */
- __I MTB_PID5_Type PID5; /**< \brief Offset: 0xFD4 (R/ 32) CoreSight */
- __I MTB_PID6_Type PID6; /**< \brief Offset: 0xFD8 (R/ 32) CoreSight */
- __I MTB_PID7_Type PID7; /**< \brief Offset: 0xFDC (R/ 32) CoreSight */
- __I MTB_PID0_Type PID0; /**< \brief Offset: 0xFE0 (R/ 32) CoreSight */
- __I MTB_PID1_Type PID1; /**< \brief Offset: 0xFE4 (R/ 32) CoreSight */
- __I MTB_PID2_Type PID2; /**< \brief Offset: 0xFE8 (R/ 32) CoreSight */
- __I MTB_PID3_Type PID3; /**< \brief Offset: 0xFEC (R/ 32) CoreSight */
- __I MTB_CID0_Type CID0; /**< \brief Offset: 0xFF0 (R/ 32) CoreSight */
- __I MTB_CID1_Type CID1; /**< \brief Offset: 0xFF4 (R/ 32) CoreSight */
- __I MTB_CID2_Type CID2; /**< \brief Offset: 0xFF8 (R/ 32) CoreSight */
- __I MTB_CID3_Type CID3; /**< \brief Offset: 0xFFC (R/ 32) CoreSight */
+ __IO MTB_POSITION_Type POSITION; /**< \brief Offset: 0x000 (R/W 32) MTB Position */
+ __IO MTB_MASTER_Type MASTER; /**< \brief Offset: 0x004 (R/W 32) MTB Master */
+ __IO MTB_FLOW_Type FLOW; /**< \brief Offset: 0x008 (R/W 32) MTB Flow */
+ __I MTB_BASE_Type BASE; /**< \brief Offset: 0x00C (R/ 32) MTB Base */
+ RoReg8 Reserved1[0xEF0];
+ __IO MTB_ITCTRL_Type ITCTRL; /**< \brief Offset: 0xF00 (R/W 32) MTB Integration Mode Control */
+ RoReg8 Reserved2[0x9C];
+ __IO MTB_CLAIMSET_Type CLAIMSET; /**< \brief Offset: 0xFA0 (R/W 32) MTB Claim Set */
+ __IO MTB_CLAIMCLR_Type CLAIMCLR; /**< \brief Offset: 0xFA4 (R/W 32) MTB Claim Clear */
+ RoReg8 Reserved3[0x8];
+ __IO MTB_LOCKACCESS_Type LOCKACCESS; /**< \brief Offset: 0xFB0 (R/W 32) MTB Lock Access */
+ __I MTB_LOCKSTATUS_Type LOCKSTATUS; /**< \brief Offset: 0xFB4 (R/ 32) MTB Lock Status */
+ __I MTB_AUTHSTATUS_Type AUTHSTATUS; /**< \brief Offset: 0xFB8 (R/ 32) MTB Authentication Status */
+ __I MTB_DEVARCH_Type DEVARCH; /**< \brief Offset: 0xFBC (R/ 32) MTB Device Architecture */
+ RoReg8 Reserved4[0x8];
+ __I MTB_DEVID_Type DEVID; /**< \brief Offset: 0xFC8 (R/ 32) MTB Device Configuration */
+ __I MTB_DEVTYPE_Type DEVTYPE; /**< \brief Offset: 0xFCC (R/ 32) MTB Device Type */
+ __I MTB_PID4_Type PID4; /**< \brief Offset: 0xFD0 (R/ 32) CoreSight */
+ __I MTB_PID5_Type PID5; /**< \brief Offset: 0xFD4 (R/ 32) CoreSight */
+ __I MTB_PID6_Type PID6; /**< \brief Offset: 0xFD8 (R/ 32) CoreSight */
+ __I MTB_PID7_Type PID7; /**< \brief Offset: 0xFDC (R/ 32) CoreSight */
+ __I MTB_PID0_Type PID0; /**< \brief Offset: 0xFE0 (R/ 32) CoreSight */
+ __I MTB_PID1_Type PID1; /**< \brief Offset: 0xFE4 (R/ 32) CoreSight */
+ __I MTB_PID2_Type PID2; /**< \brief Offset: 0xFE8 (R/ 32) CoreSight */
+ __I MTB_PID3_Type PID3; /**< \brief Offset: 0xFEC (R/ 32) CoreSight */
+ __I MTB_CID0_Type CID0; /**< \brief Offset: 0xFF0 (R/ 32) CoreSight */
+ __I MTB_CID1_Type CID1; /**< \brief Offset: 0xFF4 (R/ 32) CoreSight */
+ __I MTB_CID2_Type CID2; /**< \brief Offset: 0xFF8 (R/ 32) CoreSight */
+ __I MTB_CID3_Type CID3; /**< \brief Offset: 0xFFC (R/ 32) CoreSight */
} Mtb;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_nvmctrl.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_nvmctrl.h
index a9bfd4fd778..143af0a0ecc 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_nvmctrl.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_nvmctrl.h
@@ -59,12 +59,12 @@
/* -------- NVMCTRL_CTRLA : (NVMCTRL Offset: 0x00) (R/W 16) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t CMD:7; /*!< bit: 0.. 6 Command */
- uint16_t :1; /*!< bit: 7 Reserved */
- uint16_t CMDEX:8; /*!< bit: 8..15 Command Execution */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t CMD:7; /*!< bit: 0.. 6 Command */
+ uint16_t :1; /*!< bit: 7 Reserved */
+ uint16_t CMDEX:8; /*!< bit: 8..15 Command Execution */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} NVMCTRL_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -114,18 +114,18 @@ typedef union {
/* -------- NVMCTRL_CTRLB : (NVMCTRL Offset: 0x04) (R/W 32) Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t :1; /*!< bit: 0 Reserved */
- uint32_t RWS:4; /*!< bit: 1.. 4 NVM Read Wait States */
- uint32_t :2; /*!< bit: 5.. 6 Reserved */
- uint32_t MANW:1; /*!< bit: 7 Manual Write */
- uint32_t SLEEPPRM:2; /*!< bit: 8.. 9 Power Reduction Mode during Sleep */
- uint32_t :6; /*!< bit: 10..15 Reserved */
- uint32_t READMODE:2; /*!< bit: 16..17 NVMCTRL Read Mode */
- uint32_t CACHEDIS:1; /*!< bit: 18 Cache Disable */
- uint32_t :13; /*!< bit: 19..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t RWS:4; /*!< bit: 1.. 4 NVM Read Wait States */
+ uint32_t :2; /*!< bit: 5.. 6 Reserved */
+ uint32_t MANW:1; /*!< bit: 7 Manual Write */
+ uint32_t SLEEPPRM:2; /*!< bit: 8.. 9 Power Reduction Mode during Sleep */
+ uint32_t :6; /*!< bit: 10..15 Reserved */
+ uint32_t READMODE:2; /*!< bit: 16..17 NVMCTRL Read Mode */
+ uint32_t CACHEDIS:1; /*!< bit: 18 Cache Disable */
+ uint32_t :13; /*!< bit: 19..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} NVMCTRL_CTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -168,13 +168,13 @@ typedef union {
/* -------- NVMCTRL_PARAM : (NVMCTRL Offset: 0x08) (R/W 32) NVM Parameter -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t NVMP:16; /*!< bit: 0..15 NVM Pages */
- uint32_t PSZ:3; /*!< bit: 16..18 Page Size */
- uint32_t :1; /*!< bit: 19 Reserved */
- uint32_t RWWEEP:12; /*!< bit: 20..31 RWW EEPROM Pages */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t NVMP:16; /*!< bit: 0..15 NVM Pages */
+ uint32_t PSZ:3; /*!< bit: 16..18 Page Size */
+ uint32_t :1; /*!< bit: 19 Reserved */
+ uint32_t RWWEEP:12; /*!< bit: 20..31 RWW EEPROM Pages */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} NVMCTRL_PARAM_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -211,12 +211,12 @@ typedef union {
/* -------- NVMCTRL_INTENCLR : (NVMCTRL Offset: 0x0C) (R/W 8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Enable */
- uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Enable */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Enable */
+ uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Enable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} NVMCTRL_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -232,12 +232,12 @@ typedef union {
/* -------- NVMCTRL_INTENSET : (NVMCTRL Offset: 0x10) (R/W 8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Enable */
- uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Enable */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Enable */
+ uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Enable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} NVMCTRL_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -253,12 +253,12 @@ typedef union {
/* -------- NVMCTRL_INTFLAG : (NVMCTRL Offset: 0x14) (R/W 8) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t READY:1; /*!< bit: 0 NVM Ready */
- uint8_t ERROR:1; /*!< bit: 1 Error */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t READY:1; /*!< bit: 0 NVM Ready */
+ uint8_t ERROR:1; /*!< bit: 1 Error */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} NVMCTRL_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -274,17 +274,17 @@ typedef union {
/* -------- NVMCTRL_STATUS : (NVMCTRL Offset: 0x18) (R/W 16) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t PRM:1; /*!< bit: 0 Power Reduction Mode */
- uint16_t LOAD:1; /*!< bit: 1 NVM Page Buffer Active Loading */
- uint16_t PROGE:1; /*!< bit: 2 Programming Error Status */
- uint16_t LOCKE:1; /*!< bit: 3 Lock Error Status */
- uint16_t NVME:1; /*!< bit: 4 NVM Error */
- uint16_t :3; /*!< bit: 5.. 7 Reserved */
- uint16_t SB:1; /*!< bit: 8 Security Bit Status */
- uint16_t :7; /*!< bit: 9..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t PRM:1; /*!< bit: 0 Power Reduction Mode */
+ uint16_t LOAD:1; /*!< bit: 1 NVM Page Buffer Active Loading */
+ uint16_t PROGE:1; /*!< bit: 2 Programming Error Status */
+ uint16_t LOCKE:1; /*!< bit: 3 Lock Error Status */
+ uint16_t NVME:1; /*!< bit: 4 NVM Error */
+ uint16_t :3; /*!< bit: 5.. 7 Reserved */
+ uint16_t SB:1; /*!< bit: 8 Security Bit Status */
+ uint16_t :7; /*!< bit: 9..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} NVMCTRL_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -308,11 +308,11 @@ typedef union {
/* -------- NVMCTRL_ADDR : (NVMCTRL Offset: 0x1C) (R/W 32) Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t ADDR:22; /*!< bit: 0..21 NVM Address */
- uint32_t :10; /*!< bit: 22..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t ADDR:22; /*!< bit: 0..21 NVM Address */
+ uint32_t :10; /*!< bit: 22..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} NVMCTRL_ADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -327,10 +327,10 @@ typedef union {
/* -------- NVMCTRL_LOCK : (NVMCTRL Offset: 0x20) (R/W 16) Lock Section -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t LOCK:16; /*!< bit: 0..15 Region Lock Bits */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t LOCK:16; /*!< bit: 0..15 Region Lock Bits */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} NVMCTRL_LOCK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -344,20 +344,20 @@ typedef union {
/** \brief NVMCTRL APB hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO NVMCTRL_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
- RoReg8 Reserved1[0x2];
- __IO NVMCTRL_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) Control B */
- __IO NVMCTRL_PARAM_Type PARAM; /**< \brief Offset: 0x08 (R/W 32) NVM Parameter */
- __IO NVMCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
- RoReg8 Reserved2[0x3];
- __IO NVMCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 8) Interrupt Enable Set */
- RoReg8 Reserved3[0x3];
- __IO NVMCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 8) Interrupt Flag Status and Clear */
- RoReg8 Reserved4[0x3];
- __IO NVMCTRL_STATUS_Type STATUS; /**< \brief Offset: 0x18 (R/W 16) Status */
- RoReg8 Reserved5[0x2];
- __IO NVMCTRL_ADDR_Type ADDR; /**< \brief Offset: 0x1C (R/W 32) Address */
- __IO NVMCTRL_LOCK_Type LOCK; /**< \brief Offset: 0x20 (R/W 16) Lock Section */
+ __IO NVMCTRL_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
+ RoReg8 Reserved1[0x2];
+ __IO NVMCTRL_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) Control B */
+ __IO NVMCTRL_PARAM_Type PARAM; /**< \brief Offset: 0x08 (R/W 32) NVM Parameter */
+ __IO NVMCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
+ RoReg8 Reserved2[0x3];
+ __IO NVMCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 8) Interrupt Enable Set */
+ RoReg8 Reserved3[0x3];
+ __IO NVMCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 8) Interrupt Flag Status and Clear */
+ RoReg8 Reserved4[0x3];
+ __IO NVMCTRL_STATUS_Type STATUS; /**< \brief Offset: 0x18 (R/W 16) Status */
+ RoReg8 Reserved5[0x2];
+ __IO NVMCTRL_ADDR_Type ADDR; /**< \brief Offset: 0x1C (R/W 32) Address */
+ __IO NVMCTRL_LOCK_Type LOCK; /**< \brief Offset: 0x20 (R/W 16) Lock Section */
} Nvmctrl;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SECTION_NVMCTRL_CAL
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_pac.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_pac.h
index 049fb2a3f24..43b8a4f792d 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_pac.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_pac.h
@@ -59,11 +59,11 @@
/* -------- PAC_WPCLR : (PAC Offset: 0x0) (R/W 32) Write Protection Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t :1; /*!< bit: 0 Reserved */
- uint32_t WP:31; /*!< bit: 1..31 Write Protection Clear */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t WP:31; /*!< bit: 1..31 Write Protection Clear */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} PAC_WPCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -78,11 +78,11 @@ typedef union {
/* -------- PAC_WPSET : (PAC Offset: 0x4) (R/W 32) Write Protection Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t :1; /*!< bit: 0 Reserved */
- uint32_t WP:31; /*!< bit: 1..31 Write Protection Set */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t WP:31; /*!< bit: 1..31 Write Protection Set */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} PAC_WPSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -97,8 +97,8 @@ typedef union {
/** \brief PAC hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO PAC_WPCLR_Type WPCLR; /**< \brief Offset: 0x0 (R/W 32) Write Protection Clear */
- __IO PAC_WPSET_Type WPSET; /**< \brief Offset: 0x4 (R/W 32) Write Protection Set */
+ __IO PAC_WPCLR_Type WPCLR; /**< \brief Offset: 0x0 (R/W 32) Write Protection Clear */
+ __IO PAC_WPSET_Type WPSET; /**< \brief Offset: 0x4 (R/W 32) Write Protection Set */
} Pac;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_pm.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_pm.h
index 7e522dbe717..1dde1771ba7 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_pm.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_pm.h
@@ -59,7 +59,7 @@
/* -------- PM_CTRL : (PM Offset: 0x00) (R/W 8) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint8_t reg; /*!< Type used for register access */
+ uint8_t reg; /*!< Type used for register access */
} PM_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -71,11 +71,11 @@ typedef union {
/* -------- PM_SLEEP : (PM Offset: 0x01) (R/W 8) Sleep Mode -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t IDLE:2; /*!< bit: 0.. 1 Idle Mode Configuration */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t IDLE:2; /*!< bit: 0.. 1 Idle Mode Configuration */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} PM_SLEEP_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -96,11 +96,11 @@ typedef union {
/* -------- PM_EXTCTRL : (PM Offset: 0x02) (R/W 8) External Reset Controller -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t SETDIS:1; /*!< bit: 0 External Reset Disable */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t SETDIS:1; /*!< bit: 0 External Reset Disable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} PM_EXTCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -114,11 +114,11 @@ typedef union {
/* -------- PM_CPUSEL : (PM Offset: 0x08) (R/W 8) CPU Clock Select -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t CPUDIV:3; /*!< bit: 0.. 2 CPU Prescaler Selection */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t CPUDIV:3; /*!< bit: 0.. 2 CPU Prescaler Selection */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} PM_CPUSEL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -149,11 +149,11 @@ typedef union {
/* -------- PM_APBASEL : (PM Offset: 0x09) (R/W 8) APBA Clock Select -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t APBADIV:3; /*!< bit: 0.. 2 APBA Prescaler Selection */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t APBADIV:3; /*!< bit: 0.. 2 APBA Prescaler Selection */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} PM_APBASEL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -184,11 +184,11 @@ typedef union {
/* -------- PM_APBBSEL : (PM Offset: 0x0A) (R/W 8) APBB Clock Select -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t APBBDIV:3; /*!< bit: 0.. 2 APBB Prescaler Selection */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t APBBDIV:3; /*!< bit: 0.. 2 APBB Prescaler Selection */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} PM_APBBSEL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -219,11 +219,11 @@ typedef union {
/* -------- PM_APBCSEL : (PM Offset: 0x0B) (R/W 8) APBC Clock Select -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t APBCDIV:3; /*!< bit: 0.. 2 APBC Prescaler Selection */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t APBCDIV:3; /*!< bit: 0.. 2 APBC Prescaler Selection */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} PM_APBCSEL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -254,17 +254,17 @@ typedef union {
/* -------- PM_AHBMASK : (PM Offset: 0x14) (R/W 32) AHB Mask -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t HPB0_:1; /*!< bit: 0 HPB0 AHB Clock Mask */
- uint32_t HPB1_:1; /*!< bit: 1 HPB1 AHB Clock Mask */
- uint32_t HPB2_:1; /*!< bit: 2 HPB2 AHB Clock Mask */
- uint32_t DSU_:1; /*!< bit: 3 DSU AHB Clock Mask */
- uint32_t NVMCTRL_:1; /*!< bit: 4 NVMCTRL AHB Clock Mask */
- uint32_t DMAC_:1; /*!< bit: 5 DMAC AHB Clock Mask */
- uint32_t USB_:1; /*!< bit: 6 USB AHB Clock Mask */
- uint32_t :25; /*!< bit: 7..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t HPB0_:1; /*!< bit: 0 HPB0 AHB Clock Mask */
+ uint32_t HPB1_:1; /*!< bit: 1 HPB1 AHB Clock Mask */
+ uint32_t HPB2_:1; /*!< bit: 2 HPB2 AHB Clock Mask */
+ uint32_t DSU_:1; /*!< bit: 3 DSU AHB Clock Mask */
+ uint32_t NVMCTRL_:1; /*!< bit: 4 NVMCTRL AHB Clock Mask */
+ uint32_t DMAC_:1; /*!< bit: 5 DMAC AHB Clock Mask */
+ uint32_t USB_:1; /*!< bit: 6 USB AHB Clock Mask */
+ uint32_t :25; /*!< bit: 7..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} PM_AHBMASK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -290,17 +290,17 @@ typedef union {
/* -------- PM_APBAMASK : (PM Offset: 0x18) (R/W 32) APBA Mask -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t PAC0_:1; /*!< bit: 0 PAC0 APB Clock Enable */
- uint32_t PM_:1; /*!< bit: 1 PM APB Clock Enable */
- uint32_t SYSCTRL_:1; /*!< bit: 2 SYSCTRL APB Clock Enable */
- uint32_t GCLK_:1; /*!< bit: 3 GCLK APB Clock Enable */
- uint32_t WDT_:1; /*!< bit: 4 WDT APB Clock Enable */
- uint32_t RTC_:1; /*!< bit: 5 RTC APB Clock Enable */
- uint32_t EIC_:1; /*!< bit: 6 EIC APB Clock Enable */
- uint32_t :25; /*!< bit: 7..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t PAC0_:1; /*!< bit: 0 PAC0 APB Clock Enable */
+ uint32_t PM_:1; /*!< bit: 1 PM APB Clock Enable */
+ uint32_t SYSCTRL_:1; /*!< bit: 2 SYSCTRL APB Clock Enable */
+ uint32_t GCLK_:1; /*!< bit: 3 GCLK APB Clock Enable */
+ uint32_t WDT_:1; /*!< bit: 4 WDT APB Clock Enable */
+ uint32_t RTC_:1; /*!< bit: 5 RTC APB Clock Enable */
+ uint32_t EIC_:1; /*!< bit: 6 EIC APB Clock Enable */
+ uint32_t :25; /*!< bit: 7..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} PM_APBAMASK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -326,17 +326,17 @@ typedef union {
/* -------- PM_APBBMASK : (PM Offset: 0x1C) (R/W 32) APBB Mask -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t PAC1_:1; /*!< bit: 0 PAC1 APB Clock Enable */
- uint32_t DSU_:1; /*!< bit: 1 DSU APB Clock Enable */
- uint32_t NVMCTRL_:1; /*!< bit: 2 NVMCTRL APB Clock Enable */
- uint32_t PORT_:1; /*!< bit: 3 PORT APB Clock Enable */
- uint32_t DMAC_:1; /*!< bit: 4 DMAC APB Clock Enable */
- uint32_t USB_:1; /*!< bit: 5 USB APB Clock Enable */
- uint32_t HMATRIX_:1; /*!< bit: 6 HMATRIX APB Clock Enable */
- uint32_t :25; /*!< bit: 7..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t PAC1_:1; /*!< bit: 0 PAC1 APB Clock Enable */
+ uint32_t DSU_:1; /*!< bit: 1 DSU APB Clock Enable */
+ uint32_t NVMCTRL_:1; /*!< bit: 2 NVMCTRL APB Clock Enable */
+ uint32_t PORT_:1; /*!< bit: 3 PORT APB Clock Enable */
+ uint32_t DMAC_:1; /*!< bit: 4 DMAC APB Clock Enable */
+ uint32_t USB_:1; /*!< bit: 5 USB APB Clock Enable */
+ uint32_t HMATRIX_:1; /*!< bit: 6 HMATRIX APB Clock Enable */
+ uint32_t :25; /*!< bit: 7..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} PM_APBBMASK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -362,33 +362,33 @@ typedef union {
/* -------- PM_APBCMASK : (PM Offset: 0x20) (R/W 32) APBC Mask -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t PAC2_:1; /*!< bit: 0 PAC2 APB Clock Enable */
- uint32_t EVSYS_:1; /*!< bit: 1 EVSYS APB Clock Enable */
- uint32_t SERCOM0_:1; /*!< bit: 2 SERCOM0 APB Clock Enable */
- uint32_t SERCOM1_:1; /*!< bit: 3 SERCOM1 APB Clock Enable */
- uint32_t SERCOM2_:1; /*!< bit: 4 SERCOM2 APB Clock Enable */
- uint32_t SERCOM3_:1; /*!< bit: 5 SERCOM3 APB Clock Enable */
- uint32_t SERCOM4_:1; /*!< bit: 6 SERCOM4 APB Clock Enable */
- uint32_t SERCOM5_:1; /*!< bit: 7 SERCOM5 APB Clock Enable */
- uint32_t TCC0_:1; /*!< bit: 8 TCC0 APB Clock Enable */
- uint32_t TCC1_:1; /*!< bit: 9 TCC1 APB Clock Enable */
- uint32_t TCC2_:1; /*!< bit: 10 TCC2 APB Clock Enable */
- uint32_t TC3_:1; /*!< bit: 11 TC3 APB Clock Enable */
- uint32_t TC4_:1; /*!< bit: 12 TC4 APB Clock Enable */
- uint32_t TC5_:1; /*!< bit: 13 TC5 APB Clock Enable */
- uint32_t TC6_:1; /*!< bit: 14 TC6 APB Clock Enable */
- uint32_t TC7_:1; /*!< bit: 15 TC7 APB Clock Enable */
- uint32_t ADC_:1; /*!< bit: 16 ADC APB Clock Enable */
- uint32_t AC_:1; /*!< bit: 17 AC APB Clock Enable */
- uint32_t DAC_:1; /*!< bit: 18 DAC APB Clock Enable */
- uint32_t PTC_:1; /*!< bit: 19 PTC APB Clock Enable */
- uint32_t I2S_:1; /*!< bit: 20 I2S APB Clock Enable */
- uint32_t AC1_:1; /*!< bit: 21 AC1 APB Clock Enable */
- uint32_t LINCTRL_:1; /*!< bit: 22 LINCTRL APB Clock Enable */
- uint32_t :9; /*!< bit: 23..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t PAC2_:1; /*!< bit: 0 PAC2 APB Clock Enable */
+ uint32_t EVSYS_:1; /*!< bit: 1 EVSYS APB Clock Enable */
+ uint32_t SERCOM0_:1; /*!< bit: 2 SERCOM0 APB Clock Enable */
+ uint32_t SERCOM1_:1; /*!< bit: 3 SERCOM1 APB Clock Enable */
+ uint32_t SERCOM2_:1; /*!< bit: 4 SERCOM2 APB Clock Enable */
+ uint32_t SERCOM3_:1; /*!< bit: 5 SERCOM3 APB Clock Enable */
+ uint32_t SERCOM4_:1; /*!< bit: 6 SERCOM4 APB Clock Enable */
+ uint32_t SERCOM5_:1; /*!< bit: 7 SERCOM5 APB Clock Enable */
+ uint32_t TCC0_:1; /*!< bit: 8 TCC0 APB Clock Enable */
+ uint32_t TCC1_:1; /*!< bit: 9 TCC1 APB Clock Enable */
+ uint32_t TCC2_:1; /*!< bit: 10 TCC2 APB Clock Enable */
+ uint32_t TC3_:1; /*!< bit: 11 TC3 APB Clock Enable */
+ uint32_t TC4_:1; /*!< bit: 12 TC4 APB Clock Enable */
+ uint32_t TC5_:1; /*!< bit: 13 TC5 APB Clock Enable */
+ uint32_t TC6_:1; /*!< bit: 14 TC6 APB Clock Enable */
+ uint32_t TC7_:1; /*!< bit: 15 TC7 APB Clock Enable */
+ uint32_t ADC_:1; /*!< bit: 16 ADC APB Clock Enable */
+ uint32_t AC_:1; /*!< bit: 17 AC APB Clock Enable */
+ uint32_t DAC_:1; /*!< bit: 18 DAC APB Clock Enable */
+ uint32_t PTC_:1; /*!< bit: 19 PTC APB Clock Enable */
+ uint32_t I2S_:1; /*!< bit: 20 I2S APB Clock Enable */
+ uint32_t AC1_:1; /*!< bit: 21 AC1 APB Clock Enable */
+ uint32_t LINCTRL_:1; /*!< bit: 22 LINCTRL APB Clock Enable */
+ uint32_t :9; /*!< bit: 23..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} PM_APBCMASK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -446,11 +446,11 @@ typedef union {
/* -------- PM_INTENCLR : (PM Offset: 0x34) (R/W 8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} PM_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -464,11 +464,11 @@ typedef union {
/* -------- PM_INTENSET : (PM Offset: 0x35) (R/W 8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} PM_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -482,11 +482,11 @@ typedef union {
/* -------- PM_INTFLAG : (PM Offset: 0x36) (R/W 8) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t CKRDY:1; /*!< bit: 0 Clock Ready */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t CKRDY:1; /*!< bit: 0 Clock Ready */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} PM_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -500,17 +500,17 @@ typedef union {
/* -------- PM_RCAUSE : (PM Offset: 0x38) (R/ 8) Reset Cause -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t POR:1; /*!< bit: 0 Power On Reset */
- uint8_t BOD12:1; /*!< bit: 1 Brown Out 12 Detector Reset */
- uint8_t BOD33:1; /*!< bit: 2 Brown Out 33 Detector Reset */
- uint8_t :1; /*!< bit: 3 Reserved */
- uint8_t EXT:1; /*!< bit: 4 External Reset */
- uint8_t WDT:1; /*!< bit: 5 Watchdog Reset */
- uint8_t SYST:1; /*!< bit: 6 System Reset Request */
- uint8_t :1; /*!< bit: 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t POR:1; /*!< bit: 0 Power On Reset */
+ uint8_t BOD12:1; /*!< bit: 1 Brown Out 12 Detector Reset */
+ uint8_t BOD33:1; /*!< bit: 2 Brown Out 33 Detector Reset */
+ uint8_t :1; /*!< bit: 3 Reserved */
+ uint8_t EXT:1; /*!< bit: 4 External Reset */
+ uint8_t WDT:1; /*!< bit: 5 Watchdog Reset */
+ uint8_t SYST:1; /*!< bit: 6 System Reset Request */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} PM_RCAUSE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -534,25 +534,25 @@ typedef union {
/** \brief PM hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO PM_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 8) Control */
- __IO PM_SLEEP_Type SLEEP; /**< \brief Offset: 0x01 (R/W 8) Sleep Mode */
- __IO PM_EXTCTRL_Type EXTCTRL; /**< \brief Offset: 0x02 (R/W 8) External Reset Controller */
- RoReg8 Reserved1[0x5];
- __IO PM_CPUSEL_Type CPUSEL; /**< \brief Offset: 0x08 (R/W 8) CPU Clock Select */
- __IO PM_APBASEL_Type APBASEL; /**< \brief Offset: 0x09 (R/W 8) APBA Clock Select */
- __IO PM_APBBSEL_Type APBBSEL; /**< \brief Offset: 0x0A (R/W 8) APBB Clock Select */
- __IO PM_APBCSEL_Type APBCSEL; /**< \brief Offset: 0x0B (R/W 8) APBC Clock Select */
- RoReg8 Reserved2[0x8];
- __IO PM_AHBMASK_Type AHBMASK; /**< \brief Offset: 0x14 (R/W 32) AHB Mask */
- __IO PM_APBAMASK_Type APBAMASK; /**< \brief Offset: 0x18 (R/W 32) APBA Mask */
- __IO PM_APBBMASK_Type APBBMASK; /**< \brief Offset: 0x1C (R/W 32) APBB Mask */
- __IO PM_APBCMASK_Type APBCMASK; /**< \brief Offset: 0x20 (R/W 32) APBC Mask */
- RoReg8 Reserved3[0x10];
- __IO PM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x34 (R/W 8) Interrupt Enable Clear */
- __IO PM_INTENSET_Type INTENSET; /**< \brief Offset: 0x35 (R/W 8) Interrupt Enable Set */
- __IO PM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x36 (R/W 8) Interrupt Flag Status and Clear */
- RoReg8 Reserved4[0x1];
- __I PM_RCAUSE_Type RCAUSE; /**< \brief Offset: 0x38 (R/ 8) Reset Cause */
+ __IO PM_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 8) Control */
+ __IO PM_SLEEP_Type SLEEP; /**< \brief Offset: 0x01 (R/W 8) Sleep Mode */
+ __IO PM_EXTCTRL_Type EXTCTRL; /**< \brief Offset: 0x02 (R/W 8) External Reset Controller */
+ RoReg8 Reserved1[0x5];
+ __IO PM_CPUSEL_Type CPUSEL; /**< \brief Offset: 0x08 (R/W 8) CPU Clock Select */
+ __IO PM_APBASEL_Type APBASEL; /**< \brief Offset: 0x09 (R/W 8) APBA Clock Select */
+ __IO PM_APBBSEL_Type APBBSEL; /**< \brief Offset: 0x0A (R/W 8) APBB Clock Select */
+ __IO PM_APBCSEL_Type APBCSEL; /**< \brief Offset: 0x0B (R/W 8) APBC Clock Select */
+ RoReg8 Reserved2[0x8];
+ __IO PM_AHBMASK_Type AHBMASK; /**< \brief Offset: 0x14 (R/W 32) AHB Mask */
+ __IO PM_APBAMASK_Type APBAMASK; /**< \brief Offset: 0x18 (R/W 32) APBA Mask */
+ __IO PM_APBBMASK_Type APBBMASK; /**< \brief Offset: 0x1C (R/W 32) APBB Mask */
+ __IO PM_APBCMASK_Type APBCMASK; /**< \brief Offset: 0x20 (R/W 32) APBC Mask */
+ RoReg8 Reserved3[0x10];
+ __IO PM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x34 (R/W 8) Interrupt Enable Clear */
+ __IO PM_INTENSET_Type INTENSET; /**< \brief Offset: 0x35 (R/W 8) Interrupt Enable Set */
+ __IO PM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x36 (R/W 8) Interrupt Flag Status and Clear */
+ RoReg8 Reserved4[0x1];
+ __I PM_RCAUSE_Type RCAUSE; /**< \brief Offset: 0x38 (R/ 8) Reset Cause */
} Pm;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_port.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_port.h
index a057f1824c4..5d357d6e278 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_port.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_port.h
@@ -59,10 +59,10 @@
/* -------- PORT_DIR : (PORT Offset: 0x00) (R/W 32) GROUP Data Direction -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t DIR:32; /*!< bit: 0..31 Port Data Direction */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t DIR:32; /*!< bit: 0..31 Port Data Direction */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} PORT_DIR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -77,10 +77,10 @@ typedef union {
/* -------- PORT_DIRCLR : (PORT Offset: 0x04) (R/W 32) GROUP Data Direction Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t DIRCLR:32; /*!< bit: 0..31 Port Data Direction Clear */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t DIRCLR:32; /*!< bit: 0..31 Port Data Direction Clear */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} PORT_DIRCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -95,10 +95,10 @@ typedef union {
/* -------- PORT_DIRSET : (PORT Offset: 0x08) (R/W 32) GROUP Data Direction Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t DIRSET:32; /*!< bit: 0..31 Port Data Direction Set */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t DIRSET:32; /*!< bit: 0..31 Port Data Direction Set */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} PORT_DIRSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -113,10 +113,10 @@ typedef union {
/* -------- PORT_DIRTGL : (PORT Offset: 0x0C) (R/W 32) GROUP Data Direction Toggle -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t DIRTGL:32; /*!< bit: 0..31 Port Data Direction Toggle */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t DIRTGL:32; /*!< bit: 0..31 Port Data Direction Toggle */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} PORT_DIRTGL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -131,10 +131,10 @@ typedef union {
/* -------- PORT_OUT : (PORT Offset: 0x10) (R/W 32) GROUP Data Output Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t OUT:32; /*!< bit: 0..31 Port Data Output Value */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t OUT:32; /*!< bit: 0..31 Port Data Output Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} PORT_OUT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -149,10 +149,10 @@ typedef union {
/* -------- PORT_OUTCLR : (PORT Offset: 0x14) (R/W 32) GROUP Data Output Value Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t OUTCLR:32; /*!< bit: 0..31 Port Data Output Value Clear */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t OUTCLR:32; /*!< bit: 0..31 Port Data Output Value Clear */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} PORT_OUTCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -167,10 +167,10 @@ typedef union {
/* -------- PORT_OUTSET : (PORT Offset: 0x18) (R/W 32) GROUP Data Output Value Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t OUTSET:32; /*!< bit: 0..31 Port Data Output Value Set */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t OUTSET:32; /*!< bit: 0..31 Port Data Output Value Set */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} PORT_OUTSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -185,10 +185,10 @@ typedef union {
/* -------- PORT_OUTTGL : (PORT Offset: 0x1C) (R/W 32) GROUP Data Output Value Toggle -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t OUTTGL:32; /*!< bit: 0..31 Port Data Output Value Toggle */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t OUTTGL:32; /*!< bit: 0..31 Port Data Output Value Toggle */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} PORT_OUTTGL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -203,10 +203,10 @@ typedef union {
/* -------- PORT_IN : (PORT Offset: 0x20) (R/ 32) GROUP Data Input Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t IN:32; /*!< bit: 0..31 Port Data Input Value */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t IN:32; /*!< bit: 0..31 Port Data Input Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} PORT_IN_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -221,10 +221,10 @@ typedef union {
/* -------- PORT_CTRL : (PORT Offset: 0x24) (R/W 32) GROUP Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SAMPLING:32; /*!< bit: 0..31 Input Sampling Mode */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SAMPLING:32; /*!< bit: 0..31 Input Sampling Mode */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} PORT_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -239,21 +239,21 @@ typedef union {
/* -------- PORT_WRCONFIG : (PORT Offset: 0x28) ( /W 32) GROUP Write Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t PINMASK:16; /*!< bit: 0..15 Pin Mask for Multiple Pin Configuration */
- uint32_t PMUXEN:1; /*!< bit: 16 Peripheral Multiplexer Enable */
- uint32_t INEN:1; /*!< bit: 17 Input Enable */
- uint32_t PULLEN:1; /*!< bit: 18 Pull Enable */
- uint32_t :3; /*!< bit: 19..21 Reserved */
- uint32_t DRVSTR:1; /*!< bit: 22 Output Driver Strength Selection */
- uint32_t :1; /*!< bit: 23 Reserved */
- uint32_t PMUX:4; /*!< bit: 24..27 Peripheral Multiplexing */
- uint32_t WRPMUX:1; /*!< bit: 28 Write PMUX */
- uint32_t :1; /*!< bit: 29 Reserved */
- uint32_t WRPINCFG:1; /*!< bit: 30 Write PINCFG */
- uint32_t HWSEL:1; /*!< bit: 31 Half-Word Select */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t PINMASK:16; /*!< bit: 0..15 Pin Mask for Multiple Pin Configuration */
+ uint32_t PMUXEN:1; /*!< bit: 16 Peripheral Multiplexer Enable */
+ uint32_t INEN:1; /*!< bit: 17 Input Enable */
+ uint32_t PULLEN:1; /*!< bit: 18 Pull Enable */
+ uint32_t :3; /*!< bit: 19..21 Reserved */
+ uint32_t DRVSTR:1; /*!< bit: 22 Output Driver Strength Selection */
+ uint32_t :1; /*!< bit: 23 Reserved */
+ uint32_t PMUX:4; /*!< bit: 24..27 Peripheral Multiplexing */
+ uint32_t WRPMUX:1; /*!< bit: 28 Write PMUX */
+ uint32_t :1; /*!< bit: 29 Reserved */
+ uint32_t WRPINCFG:1; /*!< bit: 30 Write PINCFG */
+ uint32_t HWSEL:1; /*!< bit: 31 Half-Word Select */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} PORT_WRCONFIG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -285,11 +285,11 @@ typedef union {
/* -------- PORT_PMUX : (PORT Offset: 0x30) (R/W 8) GROUP Peripheral Multiplexing n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t PMUXE:4; /*!< bit: 0.. 3 Peripheral Multiplexing Even */
- uint8_t PMUXO:4; /*!< bit: 4.. 7 Peripheral Multiplexing Odd */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t PMUXE:4; /*!< bit: 0.. 3 Peripheral Multiplexing Even */
+ uint8_t PMUXO:4; /*!< bit: 4.. 7 Peripheral Multiplexing Odd */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} PORT_PMUX_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -339,15 +339,15 @@ typedef union {
/* -------- PORT_PINCFG : (PORT Offset: 0x40) (R/W 8) GROUP Pin Configuration n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t PMUXEN:1; /*!< bit: 0 Peripheral Multiplexer Enable */
- uint8_t INEN:1; /*!< bit: 1 Input Enable */
- uint8_t PULLEN:1; /*!< bit: 2 Pull Enable */
- uint8_t :3; /*!< bit: 3.. 5 Reserved */
- uint8_t DRVSTR:1; /*!< bit: 6 Output Driver Strength Selection */
- uint8_t :1; /*!< bit: 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t PMUXEN:1; /*!< bit: 0 Peripheral Multiplexer Enable */
+ uint8_t INEN:1; /*!< bit: 1 Input Enable */
+ uint8_t PULLEN:1; /*!< bit: 2 Pull Enable */
+ uint8_t :3; /*!< bit: 3.. 5 Reserved */
+ uint8_t DRVSTR:1; /*!< bit: 6 Output Driver Strength Selection */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} PORT_PINCFG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -367,28 +367,28 @@ typedef union {
/** \brief PortGroup hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO PORT_DIR_Type DIR; /**< \brief Offset: 0x00 (R/W 32) Data Direction */
- __IO PORT_DIRCLR_Type DIRCLR; /**< \brief Offset: 0x04 (R/W 32) Data Direction Clear */
- __IO PORT_DIRSET_Type DIRSET; /**< \brief Offset: 0x08 (R/W 32) Data Direction Set */
- __IO PORT_DIRTGL_Type DIRTGL; /**< \brief Offset: 0x0C (R/W 32) Data Direction Toggle */
- __IO PORT_OUT_Type OUT; /**< \brief Offset: 0x10 (R/W 32) Data Output Value */
- __IO PORT_OUTCLR_Type OUTCLR; /**< \brief Offset: 0x14 (R/W 32) Data Output Value Clear */
- __IO PORT_OUTSET_Type OUTSET; /**< \brief Offset: 0x18 (R/W 32) Data Output Value Set */
- __IO PORT_OUTTGL_Type OUTTGL; /**< \brief Offset: 0x1C (R/W 32) Data Output Value Toggle */
- __I PORT_IN_Type IN; /**< \brief Offset: 0x20 (R/ 32) Data Input Value */
- __IO PORT_CTRL_Type CTRL; /**< \brief Offset: 0x24 (R/W 32) Control */
- __O PORT_WRCONFIG_Type WRCONFIG; /**< \brief Offset: 0x28 ( /W 32) Write Configuration */
- RoReg8 Reserved1[0x4];
- __IO PORT_PMUX_Type PMUX[16]; /**< \brief Offset: 0x30 (R/W 8) Peripheral Multiplexing n */
- __IO PORT_PINCFG_Type PINCFG[32]; /**< \brief Offset: 0x40 (R/W 8) Pin Configuration n */
- RoReg8 Reserved2[0x20];
+ __IO PORT_DIR_Type DIR; /**< \brief Offset: 0x00 (R/W 32) Data Direction */
+ __IO PORT_DIRCLR_Type DIRCLR; /**< \brief Offset: 0x04 (R/W 32) Data Direction Clear */
+ __IO PORT_DIRSET_Type DIRSET; /**< \brief Offset: 0x08 (R/W 32) Data Direction Set */
+ __IO PORT_DIRTGL_Type DIRTGL; /**< \brief Offset: 0x0C (R/W 32) Data Direction Toggle */
+ __IO PORT_OUT_Type OUT; /**< \brief Offset: 0x10 (R/W 32) Data Output Value */
+ __IO PORT_OUTCLR_Type OUTCLR; /**< \brief Offset: 0x14 (R/W 32) Data Output Value Clear */
+ __IO PORT_OUTSET_Type OUTSET; /**< \brief Offset: 0x18 (R/W 32) Data Output Value Set */
+ __IO PORT_OUTTGL_Type OUTTGL; /**< \brief Offset: 0x1C (R/W 32) Data Output Value Toggle */
+ __I PORT_IN_Type IN; /**< \brief Offset: 0x20 (R/ 32) Data Input Value */
+ __IO PORT_CTRL_Type CTRL; /**< \brief Offset: 0x24 (R/W 32) Control */
+ __O PORT_WRCONFIG_Type WRCONFIG; /**< \brief Offset: 0x28 ( /W 32) Write Configuration */
+ RoReg8 Reserved1[0x4];
+ __IO PORT_PMUX_Type PMUX[16]; /**< \brief Offset: 0x30 (R/W 8) Peripheral Multiplexing n */
+ __IO PORT_PINCFG_Type PINCFG[32]; /**< \brief Offset: 0x40 (R/W 8) Pin Configuration n */
+ RoReg8 Reserved2[0x20];
} PortGroup;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief PORT hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- PortGroup Group[2]; /**< \brief Offset: 0x00 PortGroup groups [GROUPS] */
+ PortGroup Group[2]; /**< \brief Offset: 0x00 PortGroup groups [GROUPS] */
} Port;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SECTION_PORT_IOBUS
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_rtc.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_rtc.h
index a006274238e..eff57382300 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_rtc.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_rtc.h
@@ -59,16 +59,16 @@
/* -------- RTC_MODE0_CTRL : (RTC Offset: 0x00) (R/W 16) MODE0 MODE0 Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t SWRST:1; /*!< bit: 0 Software Reset */
- uint16_t ENABLE:1; /*!< bit: 1 Enable */
- uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
- uint16_t :3; /*!< bit: 4.. 6 Reserved */
- uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */
- uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
- uint16_t :4; /*!< bit: 12..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint16_t ENABLE:1; /*!< bit: 1 Enable */
+ uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
+ uint16_t :3; /*!< bit: 4.. 6 Reserved */
+ uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */
+ uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} RTC_MODE0_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -120,15 +120,15 @@ typedef union {
/* -------- RTC_MODE1_CTRL : (RTC Offset: 0x00) (R/W 16) MODE1 MODE1 Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t SWRST:1; /*!< bit: 0 Software Reset */
- uint16_t ENABLE:1; /*!< bit: 1 Enable */
- uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
- uint16_t :4; /*!< bit: 4.. 7 Reserved */
- uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
- uint16_t :4; /*!< bit: 12..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint16_t ENABLE:1; /*!< bit: 1 Enable */
+ uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
+ uint16_t :4; /*!< bit: 4.. 7 Reserved */
+ uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} RTC_MODE1_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -178,17 +178,17 @@ typedef union {
/* -------- RTC_MODE2_CTRL : (RTC Offset: 0x00) (R/W 16) MODE2 MODE2 Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t SWRST:1; /*!< bit: 0 Software Reset */
- uint16_t ENABLE:1; /*!< bit: 1 Enable */
- uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
- uint16_t :2; /*!< bit: 4.. 5 Reserved */
- uint16_t CLKREP:1; /*!< bit: 6 Clock Representation */
- uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */
- uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
- uint16_t :4; /*!< bit: 12..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint16_t ENABLE:1; /*!< bit: 1 Enable */
+ uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
+ uint16_t :2; /*!< bit: 4.. 5 Reserved */
+ uint16_t CLKREP:1; /*!< bit: 6 Clock Representation */
+ uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */
+ uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} RTC_MODE2_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -242,13 +242,13 @@ typedef union {
/* -------- RTC_READREQ : (RTC Offset: 0x02) (R/W 16) Read Request -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t ADDR:6; /*!< bit: 0.. 5 Address */
- uint16_t :8; /*!< bit: 6..13 Reserved */
- uint16_t RCONT:1; /*!< bit: 14 Read Continuously */
- uint16_t RREQ:1; /*!< bit: 15 Read Request */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t ADDR:6; /*!< bit: 0.. 5 Address */
+ uint16_t :8; /*!< bit: 6..13 Reserved */
+ uint16_t RCONT:1; /*!< bit: 14 Read Continuously */
+ uint16_t RREQ:1; /*!< bit: 15 Read Request */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} RTC_READREQ_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -267,25 +267,25 @@ typedef union {
/* -------- RTC_MODE0_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE0 MODE0 Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
- uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
- uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
- uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
- uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
- uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
- uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
- uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
- uint16_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */
- uint16_t :6; /*!< bit: 9..14 Reserved */
- uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
- } bit; /*!< Structure used for bit access */
- struct {
- uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
- uint16_t CMPEO:1; /*!< bit: 8 Compare x Event Output Enable */
- uint16_t :7; /*!< bit: 9..15 Reserved */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
+ uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
+ uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
+ uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
+ uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
+ uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
+ uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
+ uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
+ uint16_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */
+ uint16_t :6; /*!< bit: 9..14 Reserved */
+ uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
+ uint16_t CMPEO:1; /*!< bit: 8 Compare x Event Output Enable */
+ uint16_t :7; /*!< bit: 9..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
} RTC_MODE0_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -323,26 +323,26 @@ typedef union {
/* -------- RTC_MODE1_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE1 MODE1 Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
- uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
- uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
- uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
- uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
- uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
- uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
- uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
- uint16_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */
- uint16_t CMPEO1:1; /*!< bit: 9 Compare 1 Event Output Enable */
- uint16_t :5; /*!< bit: 10..14 Reserved */
- uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
- } bit; /*!< Structure used for bit access */
- struct {
- uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
- uint16_t CMPEO:2; /*!< bit: 8.. 9 Compare x Event Output Enable */
- uint16_t :6; /*!< bit: 10..15 Reserved */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
+ uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
+ uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
+ uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
+ uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
+ uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
+ uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
+ uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
+ uint16_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */
+ uint16_t CMPEO1:1; /*!< bit: 9 Compare 1 Event Output Enable */
+ uint16_t :5; /*!< bit: 10..14 Reserved */
+ uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
+ uint16_t CMPEO:2; /*!< bit: 8.. 9 Compare x Event Output Enable */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
} RTC_MODE1_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -382,25 +382,25 @@ typedef union {
/* -------- RTC_MODE2_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE2 MODE2 Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
- uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
- uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
- uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
- uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
- uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
- uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
- uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
- uint16_t ALARMEO0:1; /*!< bit: 8 Alarm 0 Event Output Enable */
- uint16_t :6; /*!< bit: 9..14 Reserved */
- uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
- } bit; /*!< Structure used for bit access */
- struct {
- uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
- uint16_t ALARMEO:1; /*!< bit: 8 Alarm x Event Output Enable */
- uint16_t :7; /*!< bit: 9..15 Reserved */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
+ uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
+ uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
+ uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
+ uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
+ uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
+ uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
+ uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
+ uint16_t ALARMEO0:1; /*!< bit: 8 Alarm 0 Event Output Enable */
+ uint16_t :6; /*!< bit: 9..14 Reserved */
+ uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
+ uint16_t ALARMEO:1; /*!< bit: 8 Alarm x Event Output Enable */
+ uint16_t :7; /*!< bit: 9..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
} RTC_MODE2_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -438,17 +438,17 @@ typedef union {
/* -------- RTC_MODE0_INTENCLR : (RTC Offset: 0x06) (R/W 8) MODE0 MODE0 Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
- uint8_t :5; /*!< bit: 1.. 5 Reserved */
- uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
- uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t CMP:1; /*!< bit: 0 Compare x Interrupt Enable */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
+ uint8_t :5; /*!< bit: 1.. 5 Reserved */
+ uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
+ uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t CMP:1; /*!< bit: 0 Compare x Interrupt Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} RTC_MODE0_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -469,18 +469,18 @@ typedef union {
/* -------- RTC_MODE1_INTENCLR : (RTC Offset: 0x06) (R/W 8) MODE1 MODE1 Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
- uint8_t CMP1:1; /*!< bit: 1 Compare 1 Interrupt Enable */
- uint8_t :4; /*!< bit: 2.. 5 Reserved */
- uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
- uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t CMP:2; /*!< bit: 0.. 1 Compare x Interrupt Enable */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
+ uint8_t CMP1:1; /*!< bit: 1 Compare 1 Interrupt Enable */
+ uint8_t :4; /*!< bit: 2.. 5 Reserved */
+ uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
+ uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t CMP:2; /*!< bit: 0.. 1 Compare x Interrupt Enable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} RTC_MODE1_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -503,17 +503,17 @@ typedef union {
/* -------- RTC_MODE2_INTENCLR : (RTC Offset: 0x06) (R/W 8) MODE2 MODE2 Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 Interrupt Enable */
- uint8_t :5; /*!< bit: 1.. 5 Reserved */
- uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
- uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t ALARM:1; /*!< bit: 0 Alarm x Interrupt Enable */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 Interrupt Enable */
+ uint8_t :5; /*!< bit: 1.. 5 Reserved */
+ uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
+ uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t ALARM:1; /*!< bit: 0 Alarm x Interrupt Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} RTC_MODE2_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -534,17 +534,17 @@ typedef union {
/* -------- RTC_MODE0_INTENSET : (RTC Offset: 0x07) (R/W 8) MODE0 MODE0 Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
- uint8_t :5; /*!< bit: 1.. 5 Reserved */
- uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
- uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t CMP:1; /*!< bit: 0 Compare x Interrupt Enable */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
+ uint8_t :5; /*!< bit: 1.. 5 Reserved */
+ uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
+ uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t CMP:1; /*!< bit: 0 Compare x Interrupt Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} RTC_MODE0_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -565,18 +565,18 @@ typedef union {
/* -------- RTC_MODE1_INTENSET : (RTC Offset: 0x07) (R/W 8) MODE1 MODE1 Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
- uint8_t CMP1:1; /*!< bit: 1 Compare 1 Interrupt Enable */
- uint8_t :4; /*!< bit: 2.. 5 Reserved */
- uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
- uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t CMP:2; /*!< bit: 0.. 1 Compare x Interrupt Enable */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
+ uint8_t CMP1:1; /*!< bit: 1 Compare 1 Interrupt Enable */
+ uint8_t :4; /*!< bit: 2.. 5 Reserved */
+ uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
+ uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t CMP:2; /*!< bit: 0.. 1 Compare x Interrupt Enable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} RTC_MODE1_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -599,17 +599,17 @@ typedef union {
/* -------- RTC_MODE2_INTENSET : (RTC Offset: 0x07) (R/W 8) MODE2 MODE2 Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 Interrupt Enable */
- uint8_t :5; /*!< bit: 1.. 5 Reserved */
- uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
- uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t ALARM:1; /*!< bit: 0 Alarm x Interrupt Enable */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 Interrupt Enable */
+ uint8_t :5; /*!< bit: 1.. 5 Reserved */
+ uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
+ uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t ALARM:1; /*!< bit: 0 Alarm x Interrupt Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} RTC_MODE2_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -630,17 +630,17 @@ typedef union {
/* -------- RTC_MODE0_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE0 MODE0 Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t CMP0:1; /*!< bit: 0 Compare 0 */
- uint8_t :5; /*!< bit: 1.. 5 Reserved */
- uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
- uint8_t OVF:1; /*!< bit: 7 Overflow */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t CMP:1; /*!< bit: 0 Compare x */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t CMP0:1; /*!< bit: 0 Compare 0 */
+ uint8_t :5; /*!< bit: 1.. 5 Reserved */
+ uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
+ uint8_t OVF:1; /*!< bit: 7 Overflow */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t CMP:1; /*!< bit: 0 Compare x */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} RTC_MODE0_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -661,18 +661,18 @@ typedef union {
/* -------- RTC_MODE1_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE1 MODE1 Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t CMP0:1; /*!< bit: 0 Compare 0 */
- uint8_t CMP1:1; /*!< bit: 1 Compare 1 */
- uint8_t :4; /*!< bit: 2.. 5 Reserved */
- uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
- uint8_t OVF:1; /*!< bit: 7 Overflow */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t CMP:2; /*!< bit: 0.. 1 Compare x */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t CMP0:1; /*!< bit: 0 Compare 0 */
+ uint8_t CMP1:1; /*!< bit: 1 Compare 1 */
+ uint8_t :4; /*!< bit: 2.. 5 Reserved */
+ uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
+ uint8_t OVF:1; /*!< bit: 7 Overflow */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t CMP:2; /*!< bit: 0.. 1 Compare x */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} RTC_MODE1_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -695,17 +695,17 @@ typedef union {
/* -------- RTC_MODE2_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE2 MODE2 Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 */
- uint8_t :5; /*!< bit: 1.. 5 Reserved */
- uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
- uint8_t OVF:1; /*!< bit: 7 Overflow */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t ALARM:1; /*!< bit: 0 Alarm x */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 */
+ uint8_t :5; /*!< bit: 1.. 5 Reserved */
+ uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
+ uint8_t OVF:1; /*!< bit: 7 Overflow */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t ALARM:1; /*!< bit: 0 Alarm x */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} RTC_MODE2_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -726,11 +726,11 @@ typedef union {
/* -------- RTC_STATUS : (RTC Offset: 0x0A) (R/W 8) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t :7; /*!< bit: 0.. 6 Reserved */
- uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t :7; /*!< bit: 0.. 6 Reserved */
+ uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} RTC_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -744,11 +744,11 @@ typedef union {
/* -------- RTC_DBGCTRL : (RTC Offset: 0x0B) (R/W 8) Debug Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DBGRUN:1; /*!< bit: 0 Run During Debug */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DBGRUN:1; /*!< bit: 0 Run During Debug */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} RTC_DBGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -762,11 +762,11 @@ typedef union {
/* -------- RTC_FREQCORR : (RTC Offset: 0x0C) (R/W 8) Frequency Correction -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t VALUE:7; /*!< bit: 0.. 6 Correction Value */
- uint8_t SIGN:1; /*!< bit: 7 Correction Sign */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t VALUE:7; /*!< bit: 0.. 6 Correction Value */
+ uint8_t SIGN:1; /*!< bit: 7 Correction Sign */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} RTC_FREQCORR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -783,10 +783,10 @@ typedef union {
/* -------- RTC_MODE0_COUNT : (RTC Offset: 0x10) (R/W 32) MODE0 MODE0 Counter Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t COUNT:32; /*!< bit: 0..31 Counter Value */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t COUNT:32; /*!< bit: 0..31 Counter Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} RTC_MODE0_COUNT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -801,10 +801,10 @@ typedef union {
/* -------- RTC_MODE1_COUNT : (RTC Offset: 0x10) (R/W 16) MODE1 MODE1 Counter Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t COUNT:16; /*!< bit: 0..15 Counter Value */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t COUNT:16; /*!< bit: 0..15 Counter Value */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} RTC_MODE1_COUNT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -819,15 +819,15 @@ typedef union {
/* -------- RTC_MODE2_CLOCK : (RTC Offset: 0x10) (R/W 32) MODE2 MODE2 Clock Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SECOND:6; /*!< bit: 0.. 5 Second */
- uint32_t MINUTE:6; /*!< bit: 6..11 Minute */
- uint32_t HOUR:5; /*!< bit: 12..16 Hour */
- uint32_t DAY:5; /*!< bit: 17..21 Day */
- uint32_t MONTH:4; /*!< bit: 22..25 Month */
- uint32_t YEAR:6; /*!< bit: 26..31 Year */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SECOND:6; /*!< bit: 0.. 5 Second */
+ uint32_t MINUTE:6; /*!< bit: 6..11 Minute */
+ uint32_t HOUR:5; /*!< bit: 12..16 Hour */
+ uint32_t DAY:5; /*!< bit: 17..21 Day */
+ uint32_t MONTH:4; /*!< bit: 22..25 Month */
+ uint32_t YEAR:6; /*!< bit: 26..31 Year */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} RTC_MODE2_CLOCK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -859,10 +859,10 @@ typedef union {
/* -------- RTC_MODE1_PER : (RTC Offset: 0x14) (R/W 16) MODE1 MODE1 Counter Period -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t PER:16; /*!< bit: 0..15 Counter Period */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t PER:16; /*!< bit: 0..15 Counter Period */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} RTC_MODE1_PER_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -877,10 +877,10 @@ typedef union {
/* -------- RTC_MODE0_COMP : (RTC Offset: 0x18) (R/W 32) MODE0 MODE0 Compare n Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t COMP:32; /*!< bit: 0..31 Compare Value */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t COMP:32; /*!< bit: 0..31 Compare Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} RTC_MODE0_COMP_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -895,10 +895,10 @@ typedef union {
/* -------- RTC_MODE1_COMP : (RTC Offset: 0x18) (R/W 16) MODE1 MODE1 Compare n Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t COMP:16; /*!< bit: 0..15 Compare Value */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t COMP:16; /*!< bit: 0..15 Compare Value */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} RTC_MODE1_COMP_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -913,15 +913,15 @@ typedef union {
/* -------- RTC_MODE2_ALARM : (RTC Offset: 0x18) (R/W 32) MODE2 MODE2_ALARM Alarm n Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SECOND:6; /*!< bit: 0.. 5 Second */
- uint32_t MINUTE:6; /*!< bit: 6..11 Minute */
- uint32_t HOUR:5; /*!< bit: 12..16 Hour */
- uint32_t DAY:5; /*!< bit: 17..21 Day */
- uint32_t MONTH:4; /*!< bit: 22..25 Month */
- uint32_t YEAR:6; /*!< bit: 26..31 Year */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SECOND:6; /*!< bit: 0.. 5 Second */
+ uint32_t MINUTE:6; /*!< bit: 6..11 Minute */
+ uint32_t HOUR:5; /*!< bit: 12..16 Hour */
+ uint32_t DAY:5; /*!< bit: 17..21 Day */
+ uint32_t MONTH:4; /*!< bit: 22..25 Month */
+ uint32_t YEAR:6; /*!< bit: 26..31 Year */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} RTC_MODE2_ALARM_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -951,11 +951,11 @@ typedef union {
/* -------- RTC_MODE2_MASK : (RTC Offset: 0x1C) (R/W 8) MODE2 MODE2_ALARM Alarm n Mask -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t SEL:3; /*!< bit: 0.. 2 Alarm Mask Selection */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t SEL:3; /*!< bit: 0.. 2 Alarm Mask Selection */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} RTC_MODE2_MASK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -984,79 +984,79 @@ typedef union {
/** \brief RtcMode2Alarm hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO RTC_MODE2_ALARM_Type ALARM; /**< \brief Offset: 0x00 (R/W 32) MODE2_ALARM Alarm n Value */
- __IO RTC_MODE2_MASK_Type MASK; /**< \brief Offset: 0x04 (R/W 8) MODE2_ALARM Alarm n Mask */
- RoReg8 Reserved1[0x3];
+ __IO RTC_MODE2_ALARM_Type ALARM; /**< \brief Offset: 0x00 (R/W 32) MODE2_ALARM Alarm n Value */
+ __IO RTC_MODE2_MASK_Type MASK; /**< \brief Offset: 0x04 (R/W 8) MODE2_ALARM Alarm n Mask */
+ RoReg8 Reserved1[0x3];
} RtcMode2Alarm;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief RTC_MODE0 hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* 32-bit Counter with Single 32-bit Compare */
- __IO RTC_MODE0_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE0 Control */
- __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
- __IO RTC_MODE0_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE0 Event Control */
- __IO RTC_MODE0_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE0 Interrupt Enable Clear */
- __IO RTC_MODE0_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE0 Interrupt Enable Set */
- __IO RTC_MODE0_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE0 Interrupt Flag Status and Clear */
- RoReg8 Reserved1[0x1];
- __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */
- __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */
- __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */
- RoReg8 Reserved2[0x3];
- __IO RTC_MODE0_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 32) MODE0 Counter Value */
- RoReg8 Reserved3[0x4];
- __IO RTC_MODE0_COMP_Type COMP[1]; /**< \brief Offset: 0x18 (R/W 32) MODE0 Compare n Value */
+ __IO RTC_MODE0_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE0 Control */
+ __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
+ __IO RTC_MODE0_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE0 Event Control */
+ __IO RTC_MODE0_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE0 Interrupt Enable Clear */
+ __IO RTC_MODE0_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE0 Interrupt Enable Set */
+ __IO RTC_MODE0_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE0 Interrupt Flag Status and Clear */
+ RoReg8 Reserved1[0x1];
+ __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */
+ __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */
+ __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */
+ RoReg8 Reserved2[0x3];
+ __IO RTC_MODE0_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 32) MODE0 Counter Value */
+ RoReg8 Reserved3[0x4];
+ __IO RTC_MODE0_COMP_Type COMP[1]; /**< \brief Offset: 0x18 (R/W 32) MODE0 Compare n Value */
} RtcMode0;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief RTC_MODE1 hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* 16-bit Counter with Two 16-bit Compares */
- __IO RTC_MODE1_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE1 Control */
- __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
- __IO RTC_MODE1_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE1 Event Control */
- __IO RTC_MODE1_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE1 Interrupt Enable Clear */
- __IO RTC_MODE1_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE1 Interrupt Enable Set */
- __IO RTC_MODE1_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE1 Interrupt Flag Status and Clear */
- RoReg8 Reserved1[0x1];
- __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */
- __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */
- __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */
- RoReg8 Reserved2[0x3];
- __IO RTC_MODE1_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 16) MODE1 Counter Value */
- RoReg8 Reserved3[0x2];
- __IO RTC_MODE1_PER_Type PER; /**< \brief Offset: 0x14 (R/W 16) MODE1 Counter Period */
- RoReg8 Reserved4[0x2];
- __IO RTC_MODE1_COMP_Type COMP[2]; /**< \brief Offset: 0x18 (R/W 16) MODE1 Compare n Value */
+ __IO RTC_MODE1_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE1 Control */
+ __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
+ __IO RTC_MODE1_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE1 Event Control */
+ __IO RTC_MODE1_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE1 Interrupt Enable Clear */
+ __IO RTC_MODE1_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE1 Interrupt Enable Set */
+ __IO RTC_MODE1_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE1 Interrupt Flag Status and Clear */
+ RoReg8 Reserved1[0x1];
+ __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */
+ __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */
+ __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */
+ RoReg8 Reserved2[0x3];
+ __IO RTC_MODE1_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 16) MODE1 Counter Value */
+ RoReg8 Reserved3[0x2];
+ __IO RTC_MODE1_PER_Type PER; /**< \brief Offset: 0x14 (R/W 16) MODE1 Counter Period */
+ RoReg8 Reserved4[0x2];
+ __IO RTC_MODE1_COMP_Type COMP[2]; /**< \brief Offset: 0x18 (R/W 16) MODE1 Compare n Value */
} RtcMode1;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief RTC_MODE2 hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* Clock/Calendar with Alarm */
- __IO RTC_MODE2_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE2 Control */
- __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
- __IO RTC_MODE2_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE2 Event Control */
- __IO RTC_MODE2_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE2 Interrupt Enable Clear */
- __IO RTC_MODE2_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE2 Interrupt Enable Set */
- __IO RTC_MODE2_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE2 Interrupt Flag Status and Clear */
- RoReg8 Reserved1[0x1];
- __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */
- __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */
- __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */
- RoReg8 Reserved2[0x3];
- __IO RTC_MODE2_CLOCK_Type CLOCK; /**< \brief Offset: 0x10 (R/W 32) MODE2 Clock Value */
- RoReg8 Reserved3[0x4];
- RtcMode2Alarm Mode2Alarm[1]; /**< \brief Offset: 0x18 RtcMode2Alarm groups [ALARM_NUM] */
+ __IO RTC_MODE2_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE2 Control */
+ __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
+ __IO RTC_MODE2_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE2 Event Control */
+ __IO RTC_MODE2_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE2 Interrupt Enable Clear */
+ __IO RTC_MODE2_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE2 Interrupt Enable Set */
+ __IO RTC_MODE2_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE2 Interrupt Flag Status and Clear */
+ RoReg8 Reserved1[0x1];
+ __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */
+ __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */
+ __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */
+ RoReg8 Reserved2[0x3];
+ __IO RTC_MODE2_CLOCK_Type CLOCK; /**< \brief Offset: 0x10 (R/W 32) MODE2 Clock Value */
+ RoReg8 Reserved3[0x4];
+ RtcMode2Alarm Mode2Alarm[1]; /**< \brief Offset: 0x18 RtcMode2Alarm groups [ALARM_NUM] */
} RtcMode2;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- RtcMode0 MODE0; /**< \brief Offset: 0x00 32-bit Counter with Single 32-bit Compare */
- RtcMode1 MODE1; /**< \brief Offset: 0x00 16-bit Counter with Two 16-bit Compares */
- RtcMode2 MODE2; /**< \brief Offset: 0x00 Clock/Calendar with Alarm */
+ RtcMode0 MODE0; /**< \brief Offset: 0x00 32-bit Counter with Single 32-bit Compare */
+ RtcMode1 MODE1; /**< \brief Offset: 0x00 16-bit Counter with Two 16-bit Compares */
+ RtcMode2 MODE2; /**< \brief Offset: 0x00 Clock/Calendar with Alarm */
} Rtc;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_sercom.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_sercom.h
index d26df24fc3d..ee0733bea3d 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_sercom.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_sercom.h
@@ -59,26 +59,26 @@
/* -------- SERCOM_I2CM_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CM I2CM Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Software Reset */
- uint32_t ENABLE:1; /*!< bit: 1 Enable */
- uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
- uint32_t :2; /*!< bit: 5.. 6 Reserved */
- uint32_t RUNSTDBY:1; /*!< bit: 7 Run in Standby */
- uint32_t :8; /*!< bit: 8..15 Reserved */
- uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */
- uint32_t :3; /*!< bit: 17..19 Reserved */
- uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */
- uint32_t MEXTTOEN:1; /*!< bit: 22 Master SCL Low Extend Timeout */
- uint32_t SEXTTOEN:1; /*!< bit: 23 Slave SCL Low Extend Timeout */
- uint32_t SPEED:2; /*!< bit: 24..25 Transfer Speed */
- uint32_t :1; /*!< bit: 26 Reserved */
- uint32_t SCLSM:1; /*!< bit: 27 SCL Clock Stretch Mode */
- uint32_t INACTOUT:2; /*!< bit: 28..29 Inactive Time-Out */
- uint32_t LOWTOUTEN:1; /*!< bit: 30 SCL Low Timeout Enable */
- uint32_t :1; /*!< bit: 31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */
+ uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
+ uint32_t :2; /*!< bit: 5.. 6 Reserved */
+ uint32_t RUNSTDBY:1; /*!< bit: 7 Run in Standby */
+ uint32_t :8; /*!< bit: 8..15 Reserved */
+ uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */
+ uint32_t :3; /*!< bit: 17..19 Reserved */
+ uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */
+ uint32_t MEXTTOEN:1; /*!< bit: 22 Master SCL Low Extend Timeout */
+ uint32_t SEXTTOEN:1; /*!< bit: 23 Slave SCL Low Extend Timeout */
+ uint32_t SPEED:2; /*!< bit: 24..25 Transfer Speed */
+ uint32_t :1; /*!< bit: 26 Reserved */
+ uint32_t SCLSM:1; /*!< bit: 27 SCL Clock Stretch Mode */
+ uint32_t INACTOUT:2; /*!< bit: 28..29 Inactive Time-Out */
+ uint32_t LOWTOUTEN:1; /*!< bit: 30 SCL Low Timeout Enable */
+ uint32_t :1; /*!< bit: 31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SERCOM_I2CM_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -130,26 +130,26 @@ typedef union {
/* -------- SERCOM_I2CS_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CS I2CS Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Software Reset */
- uint32_t ENABLE:1; /*!< bit: 1 Enable */
- uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
- uint32_t :2; /*!< bit: 5.. 6 Reserved */
- uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */
- uint32_t :8; /*!< bit: 8..15 Reserved */
- uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */
- uint32_t :3; /*!< bit: 17..19 Reserved */
- uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */
- uint32_t :1; /*!< bit: 22 Reserved */
- uint32_t SEXTTOEN:1; /*!< bit: 23 Slave SCL Low Extend Timeout */
- uint32_t SPEED:2; /*!< bit: 24..25 Transfer Speed */
- uint32_t :1; /*!< bit: 26 Reserved */
- uint32_t SCLSM:1; /*!< bit: 27 SCL Clock Stretch Mode */
- uint32_t :2; /*!< bit: 28..29 Reserved */
- uint32_t LOWTOUTEN:1; /*!< bit: 30 SCL Low Timeout Enable */
- uint32_t :1; /*!< bit: 31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */
+ uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
+ uint32_t :2; /*!< bit: 5.. 6 Reserved */
+ uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */
+ uint32_t :8; /*!< bit: 8..15 Reserved */
+ uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */
+ uint32_t :3; /*!< bit: 17..19 Reserved */
+ uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */
+ uint32_t :1; /*!< bit: 22 Reserved */
+ uint32_t SEXTTOEN:1; /*!< bit: 23 Slave SCL Low Extend Timeout */
+ uint32_t SPEED:2; /*!< bit: 24..25 Transfer Speed */
+ uint32_t :1; /*!< bit: 26 Reserved */
+ uint32_t SCLSM:1; /*!< bit: 27 SCL Clock Stretch Mode */
+ uint32_t :2; /*!< bit: 28..29 Reserved */
+ uint32_t LOWTOUTEN:1; /*!< bit: 30 SCL Low Timeout Enable */
+ uint32_t :1; /*!< bit: 31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SERCOM_I2CS_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -196,25 +196,25 @@ typedef union {
/* -------- SERCOM_SPI_CTRLA : (SERCOM Offset: 0x00) (R/W 32) SPI SPI Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Software Reset */
- uint32_t ENABLE:1; /*!< bit: 1 Enable */
- uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
- uint32_t :2; /*!< bit: 5.. 6 Reserved */
- uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */
- uint32_t IBON:1; /*!< bit: 8 Immediate Buffer Overflow Notification */
- uint32_t :7; /*!< bit: 9..15 Reserved */
- uint32_t DOPO:2; /*!< bit: 16..17 Data Out Pinout */
- uint32_t :2; /*!< bit: 18..19 Reserved */
- uint32_t DIPO:2; /*!< bit: 20..21 Data In Pinout */
- uint32_t :2; /*!< bit: 22..23 Reserved */
- uint32_t FORM:4; /*!< bit: 24..27 Frame Format */
- uint32_t CPHA:1; /*!< bit: 28 Clock Phase */
- uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */
- uint32_t DORD:1; /*!< bit: 30 Data Order */
- uint32_t :1; /*!< bit: 31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */
+ uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
+ uint32_t :2; /*!< bit: 5.. 6 Reserved */
+ uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */
+ uint32_t IBON:1; /*!< bit: 8 Immediate Buffer Overflow Notification */
+ uint32_t :7; /*!< bit: 9..15 Reserved */
+ uint32_t DOPO:2; /*!< bit: 16..17 Data Out Pinout */
+ uint32_t :2; /*!< bit: 18..19 Reserved */
+ uint32_t DIPO:2; /*!< bit: 20..21 Data In Pinout */
+ uint32_t :2; /*!< bit: 22..23 Reserved */
+ uint32_t FORM:4; /*!< bit: 24..27 Frame Format */
+ uint32_t CPHA:1; /*!< bit: 28 Clock Phase */
+ uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */
+ uint32_t DORD:1; /*!< bit: 30 Data Order */
+ uint32_t :1; /*!< bit: 31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SERCOM_SPI_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -264,26 +264,26 @@ typedef union {
/* -------- SERCOM_USART_CTRLA : (SERCOM Offset: 0x00) (R/W 32) USART USART Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Software Reset */
- uint32_t ENABLE:1; /*!< bit: 1 Enable */
- uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
- uint32_t :2; /*!< bit: 5.. 6 Reserved */
- uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */
- uint32_t IBON:1; /*!< bit: 8 Immediate Buffer Overflow Notification */
- uint32_t :4; /*!< bit: 9..12 Reserved */
- uint32_t SAMPR:3; /*!< bit: 13..15 Sample */
- uint32_t TXPO:2; /*!< bit: 16..17 Transmit Data Pinout */
- uint32_t :2; /*!< bit: 18..19 Reserved */
- uint32_t RXPO:2; /*!< bit: 20..21 Receive Data Pinout */
- uint32_t SAMPA:2; /*!< bit: 22..23 Sample Adjustment */
- uint32_t FORM:4; /*!< bit: 24..27 Frame Format */
- uint32_t CMODE:1; /*!< bit: 28 Communication Mode */
- uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */
- uint32_t DORD:1; /*!< bit: 30 Data Order */
- uint32_t :1; /*!< bit: 31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */
+ uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
+ uint32_t :2; /*!< bit: 5.. 6 Reserved */
+ uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */
+ uint32_t IBON:1; /*!< bit: 8 Immediate Buffer Overflow Notification */
+ uint32_t :4; /*!< bit: 9..12 Reserved */
+ uint32_t SAMPR:3; /*!< bit: 13..15 Sample */
+ uint32_t TXPO:2; /*!< bit: 16..17 Transmit Data Pinout */
+ uint32_t :2; /*!< bit: 18..19 Reserved */
+ uint32_t RXPO:2; /*!< bit: 20..21 Receive Data Pinout */
+ uint32_t SAMPA:2; /*!< bit: 22..23 Sample Adjustment */
+ uint32_t FORM:4; /*!< bit: 24..27 Frame Format */
+ uint32_t CMODE:1; /*!< bit: 28 Communication Mode */
+ uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */
+ uint32_t DORD:1; /*!< bit: 30 Data Order */
+ uint32_t :1; /*!< bit: 31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SERCOM_USART_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -339,16 +339,16 @@ typedef union {
/* -------- SERCOM_I2CM_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CM I2CM Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t :8; /*!< bit: 0.. 7 Reserved */
- uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */
- uint32_t QCEN:1; /*!< bit: 9 Quick Command Enable */
- uint32_t :6; /*!< bit: 10..15 Reserved */
- uint32_t CMD:2; /*!< bit: 16..17 Command */
- uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */
- uint32_t :13; /*!< bit: 19..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t :8; /*!< bit: 0.. 7 Reserved */
+ uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */
+ uint32_t QCEN:1; /*!< bit: 9 Quick Command Enable */
+ uint32_t :6; /*!< bit: 10..15 Reserved */
+ uint32_t CMD:2; /*!< bit: 16..17 Command */
+ uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */
+ uint32_t :13; /*!< bit: 19..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SERCOM_I2CM_CTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -369,18 +369,18 @@ typedef union {
/* -------- SERCOM_I2CS_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CS I2CS Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t :8; /*!< bit: 0.. 7 Reserved */
- uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */
- uint32_t GCMD:1; /*!< bit: 9 PMBus Group Command */
- uint32_t AACKEN:1; /*!< bit: 10 Automatic Address Acknowledge */
- uint32_t :3; /*!< bit: 11..13 Reserved */
- uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */
- uint32_t CMD:2; /*!< bit: 16..17 Command */
- uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */
- uint32_t :13; /*!< bit: 19..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t :8; /*!< bit: 0.. 7 Reserved */
+ uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */
+ uint32_t GCMD:1; /*!< bit: 9 PMBus Group Command */
+ uint32_t AACKEN:1; /*!< bit: 10 Automatic Address Acknowledge */
+ uint32_t :3; /*!< bit: 11..13 Reserved */
+ uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */
+ uint32_t CMD:2; /*!< bit: 16..17 Command */
+ uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */
+ uint32_t :13; /*!< bit: 19..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SERCOM_I2CS_CTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -406,20 +406,20 @@ typedef union {
/* -------- SERCOM_SPI_CTRLB : (SERCOM Offset: 0x04) (R/W 32) SPI SPI Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */
- uint32_t :3; /*!< bit: 3.. 5 Reserved */
- uint32_t PLOADEN:1; /*!< bit: 6 Data Preload Enable */
- uint32_t :2; /*!< bit: 7.. 8 Reserved */
- uint32_t SSDE:1; /*!< bit: 9 Slave Select Low Detect Enable */
- uint32_t :3; /*!< bit: 10..12 Reserved */
- uint32_t MSSEN:1; /*!< bit: 13 Master Slave Select Enable */
- uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */
- uint32_t :1; /*!< bit: 16 Reserved */
- uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */
- uint32_t :14; /*!< bit: 18..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */
+ uint32_t :3; /*!< bit: 3.. 5 Reserved */
+ uint32_t PLOADEN:1; /*!< bit: 6 Data Preload Enable */
+ uint32_t :2; /*!< bit: 7.. 8 Reserved */
+ uint32_t SSDE:1; /*!< bit: 9 Slave Select Low Detect Enable */
+ uint32_t :3; /*!< bit: 10..12 Reserved */
+ uint32_t MSSEN:1; /*!< bit: 13 Master Slave Select Enable */
+ uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */
+ uint32_t :1; /*!< bit: 16 Reserved */
+ uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */
+ uint32_t :14; /*!< bit: 18..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SERCOM_SPI_CTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -445,22 +445,22 @@ typedef union {
/* -------- SERCOM_USART_CTRLB : (SERCOM Offset: 0x04) (R/W 32) USART USART Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */
- uint32_t :3; /*!< bit: 3.. 5 Reserved */
- uint32_t SBMODE:1; /*!< bit: 6 Stop Bit Mode */
- uint32_t :1; /*!< bit: 7 Reserved */
- uint32_t COLDEN:1; /*!< bit: 8 Collision Detection Enable */
- uint32_t SFDE:1; /*!< bit: 9 Start of Frame Detection Enable */
- uint32_t ENC:1; /*!< bit: 10 Encoding Format */
- uint32_t :2; /*!< bit: 11..12 Reserved */
- uint32_t PMODE:1; /*!< bit: 13 Parity Mode */
- uint32_t :2; /*!< bit: 14..15 Reserved */
- uint32_t TXEN:1; /*!< bit: 16 Transmitter Enable */
- uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */
- uint32_t :14; /*!< bit: 18..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */
+ uint32_t :3; /*!< bit: 3.. 5 Reserved */
+ uint32_t SBMODE:1; /*!< bit: 6 Stop Bit Mode */
+ uint32_t :1; /*!< bit: 7 Reserved */
+ uint32_t COLDEN:1; /*!< bit: 8 Collision Detection Enable */
+ uint32_t SFDE:1; /*!< bit: 9 Start of Frame Detection Enable */
+ uint32_t ENC:1; /*!< bit: 10 Encoding Format */
+ uint32_t :2; /*!< bit: 11..12 Reserved */
+ uint32_t PMODE:1; /*!< bit: 13 Parity Mode */
+ uint32_t :2; /*!< bit: 14..15 Reserved */
+ uint32_t TXEN:1; /*!< bit: 16 Transmitter Enable */
+ uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */
+ uint32_t :14; /*!< bit: 18..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SERCOM_USART_CTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -489,13 +489,13 @@ typedef union {
/* -------- SERCOM_I2CM_BAUD : (SERCOM Offset: 0x0C) (R/W 32) I2CM I2CM Baud Rate -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t BAUD:8; /*!< bit: 0.. 7 Baud Rate Value */
- uint32_t BAUDLOW:8; /*!< bit: 8..15 Baud Rate Value Low */
- uint32_t HSBAUD:8; /*!< bit: 16..23 High Speed Baud Rate Value */
- uint32_t HSBAUDLOW:8; /*!< bit: 24..31 High Speed Baud Rate Value Low */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t BAUD:8; /*!< bit: 0.. 7 Baud Rate Value */
+ uint32_t BAUDLOW:8; /*!< bit: 8..15 Baud Rate Value Low */
+ uint32_t HSBAUD:8; /*!< bit: 16..23 High Speed Baud Rate Value */
+ uint32_t HSBAUDLOW:8; /*!< bit: 24..31 High Speed Baud Rate Value Low */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SERCOM_I2CM_BAUD_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -519,10 +519,10 @@ typedef union {
/* -------- SERCOM_SPI_BAUD : (SERCOM Offset: 0x0C) (R/W 8) SPI SPI Baud Rate -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t BAUD:8; /*!< bit: 0.. 7 Baud Rate Value */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t BAUD:8; /*!< bit: 0.. 7 Baud Rate Value */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_SPI_BAUD_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -537,21 +537,21 @@ typedef union {
/* -------- SERCOM_USART_BAUD : (SERCOM Offset: 0x0C) (R/W 16) USART USART Baud Rate -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t BAUD:16; /*!< bit: 0..15 Baud Rate Value */
- } bit; /*!< Structure used for bit access */
- struct { // FRAC mode
- uint16_t BAUD:13; /*!< bit: 0..12 Baud Rate Value */
- uint16_t FP:3; /*!< bit: 13..15 Fractional Part */
- } FRAC; /*!< Structure used for FRAC */
- struct { // FRACFP mode
- uint16_t BAUD:13; /*!< bit: 0..12 Baud Rate Value */
- uint16_t FP:3; /*!< bit: 13..15 Fractional Part */
- } FRACFP; /*!< Structure used for FRACFP */
- struct { // USARTFP mode
- uint16_t BAUD:16; /*!< bit: 0..15 Baud Rate Value */
- } USARTFP; /*!< Structure used for USARTFP */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t BAUD:16; /*!< bit: 0..15 Baud Rate Value */
+ } bit; /*!< Structure used for bit access */
+ struct { // FRAC mode
+ uint16_t BAUD:13; /*!< bit: 0..12 Baud Rate Value */
+ uint16_t FP:3; /*!< bit: 13..15 Fractional Part */
+ } FRAC; /*!< Structure used for FRAC */
+ struct { // FRACFP mode
+ uint16_t BAUD:13; /*!< bit: 0..12 Baud Rate Value */
+ uint16_t FP:3; /*!< bit: 13..15 Fractional Part */
+ } FRACFP; /*!< Structure used for FRACFP */
+ struct { // USARTFP mode
+ uint16_t BAUD:16; /*!< bit: 0..15 Baud Rate Value */
+ } USARTFP; /*!< Structure used for USARTFP */
+ uint16_t reg; /*!< Type used for register access */
} SERCOM_USART_BAUD_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -590,10 +590,10 @@ typedef union {
/* -------- SERCOM_USART_RXPL : (SERCOM Offset: 0x0E) (R/W 8) USART USART Receive Pulse Length -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t RXPL:8; /*!< bit: 0.. 7 Receive Pulse Length */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t RXPL:8; /*!< bit: 0.. 7 Receive Pulse Length */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_USART_RXPL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -608,13 +608,13 @@ typedef union {
/* -------- SERCOM_I2CM_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) I2CM I2CM Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt Disable */
- uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt Disable */
- uint8_t :5; /*!< bit: 2.. 6 Reserved */
- uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt Disable */
+ uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt Disable */
+ uint8_t :5; /*!< bit: 2.. 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_I2CM_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -632,14 +632,14 @@ typedef union {
/* -------- SERCOM_I2CS_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) I2CS I2CS Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt Disable */
- uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt Disable */
- uint8_t DRDY:1; /*!< bit: 2 Data Interrupt Disable */
- uint8_t :4; /*!< bit: 3.. 6 Reserved */
- uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt Disable */
+ uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt Disable */
+ uint8_t DRDY:1; /*!< bit: 2 Data Interrupt Disable */
+ uint8_t :4; /*!< bit: 3.. 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_I2CS_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -659,15 +659,15 @@ typedef union {
/* -------- SERCOM_SPI_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) SPI SPI Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Disable */
- uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Disable */
- uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Disable */
- uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Disable */
- uint8_t :3; /*!< bit: 4.. 6 Reserved */
- uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Disable */
+ uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Disable */
+ uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Disable */
+ uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Disable */
+ uint8_t :3; /*!< bit: 4.. 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_SPI_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -689,17 +689,17 @@ typedef union {
/* -------- SERCOM_USART_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) USART USART Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Disable */
- uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Disable */
- uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Disable */
- uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Disable */
- uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt Disable */
- uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt Disable */
- uint8_t :1; /*!< bit: 6 Reserved */
- uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Disable */
+ uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Disable */
+ uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Disable */
+ uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Disable */
+ uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt Disable */
+ uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt Disable */
+ uint8_t :1; /*!< bit: 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_USART_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -725,13 +725,13 @@ typedef union {
/* -------- SERCOM_I2CM_INTENSET : (SERCOM Offset: 0x16) (R/W 8) I2CM I2CM Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt Enable */
- uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt Enable */
- uint8_t :5; /*!< bit: 2.. 6 Reserved */
- uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt Enable */
+ uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt Enable */
+ uint8_t :5; /*!< bit: 2.. 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_I2CM_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -749,14 +749,14 @@ typedef union {
/* -------- SERCOM_I2CS_INTENSET : (SERCOM Offset: 0x16) (R/W 8) I2CS I2CS Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt Enable */
- uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt Enable */
- uint8_t DRDY:1; /*!< bit: 2 Data Interrupt Enable */
- uint8_t :4; /*!< bit: 3.. 6 Reserved */
- uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt Enable */
+ uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt Enable */
+ uint8_t DRDY:1; /*!< bit: 2 Data Interrupt Enable */
+ uint8_t :4; /*!< bit: 3.. 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_I2CS_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -776,15 +776,15 @@ typedef union {
/* -------- SERCOM_SPI_INTENSET : (SERCOM Offset: 0x16) (R/W 8) SPI SPI Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */
- uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */
- uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */
- uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Enable */
- uint8_t :3; /*!< bit: 4.. 6 Reserved */
- uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */
+ uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */
+ uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */
+ uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Enable */
+ uint8_t :3; /*!< bit: 4.. 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_SPI_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -806,17 +806,17 @@ typedef union {
/* -------- SERCOM_USART_INTENSET : (SERCOM Offset: 0x16) (R/W 8) USART USART Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */
- uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */
- uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */
- uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Enable */
- uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt Enable */
- uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt Enable */
- uint8_t :1; /*!< bit: 6 Reserved */
- uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */
+ uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */
+ uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */
+ uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Enable */
+ uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt Enable */
+ uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt Enable */
+ uint8_t :1; /*!< bit: 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_USART_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -842,13 +842,13 @@ typedef union {
/* -------- SERCOM_I2CM_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) I2CM I2CM Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt */
- uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt */
- uint8_t :5; /*!< bit: 2.. 6 Reserved */
- uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt */
+ uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt */
+ uint8_t :5; /*!< bit: 2.. 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_I2CM_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -866,14 +866,14 @@ typedef union {
/* -------- SERCOM_I2CS_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) I2CS I2CS Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt */
- uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt */
- uint8_t DRDY:1; /*!< bit: 2 Data Interrupt */
- uint8_t :4; /*!< bit: 3.. 6 Reserved */
- uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt */
+ uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt */
+ uint8_t DRDY:1; /*!< bit: 2 Data Interrupt */
+ uint8_t :4; /*!< bit: 3.. 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_I2CS_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -893,15 +893,15 @@ typedef union {
/* -------- SERCOM_SPI_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) SPI SPI Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */
- uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */
- uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */
- uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Flag */
- uint8_t :3; /*!< bit: 4.. 6 Reserved */
- uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */
+ uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */
+ uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */
+ uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Flag */
+ uint8_t :3; /*!< bit: 4.. 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_SPI_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -923,17 +923,17 @@ typedef union {
/* -------- SERCOM_USART_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) USART USART Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */
- uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */
- uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */
- uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt */
- uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt */
- uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt */
- uint8_t :1; /*!< bit: 6 Reserved */
- uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */
+ uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */
+ uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */
+ uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt */
+ uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt */
+ uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt */
+ uint8_t :1; /*!< bit: 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_USART_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -959,20 +959,20 @@ typedef union {
/* -------- SERCOM_I2CM_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CM I2CM Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t BUSERR:1; /*!< bit: 0 Bus Error */
- uint16_t ARBLOST:1; /*!< bit: 1 Arbitration Lost */
- uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */
- uint16_t :1; /*!< bit: 3 Reserved */
- uint16_t BUSSTATE:2; /*!< bit: 4.. 5 Bus State */
- uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Timeout */
- uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */
- uint16_t MEXTTOUT:1; /*!< bit: 8 Master SCL Low Extend Timeout */
- uint16_t SEXTTOUT:1; /*!< bit: 9 Slave SCL Low Extend Timeout */
- uint16_t LENERR:1; /*!< bit: 10 Length Error */
- uint16_t :5; /*!< bit: 11..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t BUSERR:1; /*!< bit: 0 Bus Error */
+ uint16_t ARBLOST:1; /*!< bit: 1 Arbitration Lost */
+ uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */
+ uint16_t :1; /*!< bit: 3 Reserved */
+ uint16_t BUSSTATE:2; /*!< bit: 4.. 5 Bus State */
+ uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Timeout */
+ uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */
+ uint16_t MEXTTOUT:1; /*!< bit: 8 Master SCL Low Extend Timeout */
+ uint16_t SEXTTOUT:1; /*!< bit: 9 Slave SCL Low Extend Timeout */
+ uint16_t LENERR:1; /*!< bit: 10 Length Error */
+ uint16_t :5; /*!< bit: 11..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} SERCOM_I2CM_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1003,21 +1003,21 @@ typedef union {
/* -------- SERCOM_I2CS_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CS I2CS Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t BUSERR:1; /*!< bit: 0 Bus Error */
- uint16_t COLL:1; /*!< bit: 1 Transmit Collision */
- uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */
- uint16_t DIR:1; /*!< bit: 3 Read/Write Direction */
- uint16_t SR:1; /*!< bit: 4 Repeated Start */
- uint16_t :1; /*!< bit: 5 Reserved */
- uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Timeout */
- uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */
- uint16_t :1; /*!< bit: 8 Reserved */
- uint16_t SEXTTOUT:1; /*!< bit: 9 Slave SCL Low Extend Timeout */
- uint16_t HS:1; /*!< bit: 10 High Speed */
- uint16_t :5; /*!< bit: 11..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t BUSERR:1; /*!< bit: 0 Bus Error */
+ uint16_t COLL:1; /*!< bit: 1 Transmit Collision */
+ uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */
+ uint16_t DIR:1; /*!< bit: 3 Read/Write Direction */
+ uint16_t SR:1; /*!< bit: 4 Repeated Start */
+ uint16_t :1; /*!< bit: 5 Reserved */
+ uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Timeout */
+ uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */
+ uint16_t :1; /*!< bit: 8 Reserved */
+ uint16_t SEXTTOUT:1; /*!< bit: 9 Slave SCL Low Extend Timeout */
+ uint16_t HS:1; /*!< bit: 10 High Speed */
+ uint16_t :5; /*!< bit: 11..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} SERCOM_I2CS_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1047,12 +1047,12 @@ typedef union {
/* -------- SERCOM_SPI_STATUS : (SERCOM Offset: 0x1A) (R/W 16) SPI SPI Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t :2; /*!< bit: 0.. 1 Reserved */
- uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */
- uint16_t :13; /*!< bit: 3..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t :2; /*!< bit: 0.. 1 Reserved */
+ uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */
+ uint16_t :13; /*!< bit: 3..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} SERCOM_SPI_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1066,16 +1066,16 @@ typedef union {
/* -------- SERCOM_USART_STATUS : (SERCOM Offset: 0x1A) (R/W 16) USART USART Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t PERR:1; /*!< bit: 0 Parity Error */
- uint16_t FERR:1; /*!< bit: 1 Frame Error */
- uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */
- uint16_t CTS:1; /*!< bit: 3 Clear To Send */
- uint16_t ISF:1; /*!< bit: 4 Inconsistent Sync Field */
- uint16_t COLL:1; /*!< bit: 5 Collision Detected */
- uint16_t :10; /*!< bit: 6..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t PERR:1; /*!< bit: 0 Parity Error */
+ uint16_t FERR:1; /*!< bit: 1 Frame Error */
+ uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */
+ uint16_t CTS:1; /*!< bit: 3 Clear To Send */
+ uint16_t ISF:1; /*!< bit: 4 Inconsistent Sync Field */
+ uint16_t COLL:1; /*!< bit: 5 Collision Detected */
+ uint16_t :10; /*!< bit: 6..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} SERCOM_USART_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1099,13 +1099,13 @@ typedef union {
/* -------- SERCOM_I2CM_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) I2CM I2CM Syncbusy -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
- uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
- uint32_t SYSOP:1; /*!< bit: 2 System Operation Synchronization Busy */
- uint32_t :29; /*!< bit: 3..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
+ uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
+ uint32_t SYSOP:1; /*!< bit: 2 System Operation Synchronization Busy */
+ uint32_t :29; /*!< bit: 3..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SERCOM_I2CM_SYNCBUSY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1123,12 +1123,12 @@ typedef union {
/* -------- SERCOM_I2CS_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) I2CS I2CS Syncbusy -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
- uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
- uint32_t :30; /*!< bit: 2..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
+ uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
+ uint32_t :30; /*!< bit: 2..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SERCOM_I2CS_SYNCBUSY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1144,13 +1144,13 @@ typedef union {
/* -------- SERCOM_SPI_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) SPI SPI Syncbusy -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
- uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
- uint32_t CTRLB:1; /*!< bit: 2 CTRLB Synchronization Busy */
- uint32_t :29; /*!< bit: 3..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
+ uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
+ uint32_t CTRLB:1; /*!< bit: 2 CTRLB Synchronization Busy */
+ uint32_t :29; /*!< bit: 3..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SERCOM_SPI_SYNCBUSY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1168,13 +1168,13 @@ typedef union {
/* -------- SERCOM_USART_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) USART USART Syncbusy -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
- uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
- uint32_t CTRLB:1; /*!< bit: 2 CTRLB Synchronization Busy */
- uint32_t :29; /*!< bit: 3..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
+ uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
+ uint32_t CTRLB:1; /*!< bit: 2 CTRLB Synchronization Busy */
+ uint32_t :29; /*!< bit: 3..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SERCOM_USART_SYNCBUSY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1192,16 +1192,16 @@ typedef union {
/* -------- SERCOM_I2CM_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CM I2CM Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t ADDR:11; /*!< bit: 0..10 Address Value */
- uint32_t :2; /*!< bit: 11..12 Reserved */
- uint32_t LENEN:1; /*!< bit: 13 Length Enable */
- uint32_t HS:1; /*!< bit: 14 High Speed Mode */
- uint32_t TENBITEN:1; /*!< bit: 15 Ten Bit Addressing Enable */
- uint32_t LEN:8; /*!< bit: 16..23 Length */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t ADDR:11; /*!< bit: 0..10 Address Value */
+ uint32_t :2; /*!< bit: 11..12 Reserved */
+ uint32_t LENEN:1; /*!< bit: 13 Length Enable */
+ uint32_t HS:1; /*!< bit: 14 High Speed Mode */
+ uint32_t TENBITEN:1; /*!< bit: 15 Ten Bit Addressing Enable */
+ uint32_t LEN:8; /*!< bit: 16..23 Length */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SERCOM_I2CM_ADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1225,16 +1225,16 @@ typedef union {
/* -------- SERCOM_I2CS_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CS I2CS Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t GENCEN:1; /*!< bit: 0 General Call Address Enable */
- uint32_t ADDR:10; /*!< bit: 1..10 Address Value */
- uint32_t :4; /*!< bit: 11..14 Reserved */
- uint32_t TENBITEN:1; /*!< bit: 15 Ten Bit Addressing Enable */
- uint32_t :1; /*!< bit: 16 Reserved */
- uint32_t ADDRMASK:10; /*!< bit: 17..26 Address Mask */
- uint32_t :5; /*!< bit: 27..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t GENCEN:1; /*!< bit: 0 General Call Address Enable */
+ uint32_t ADDR:10; /*!< bit: 1..10 Address Value */
+ uint32_t :4; /*!< bit: 11..14 Reserved */
+ uint32_t TENBITEN:1; /*!< bit: 15 Ten Bit Addressing Enable */
+ uint32_t :1; /*!< bit: 16 Reserved */
+ uint32_t ADDRMASK:10; /*!< bit: 17..26 Address Mask */
+ uint32_t :5; /*!< bit: 27..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SERCOM_I2CS_ADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1256,13 +1256,13 @@ typedef union {
/* -------- SERCOM_SPI_ADDR : (SERCOM Offset: 0x24) (R/W 32) SPI SPI Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t ADDR:8; /*!< bit: 0.. 7 Address Value */
- uint32_t :8; /*!< bit: 8..15 Reserved */
- uint32_t ADDRMASK:8; /*!< bit: 16..23 Address Mask */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t ADDR:8; /*!< bit: 0.. 7 Address Value */
+ uint32_t :8; /*!< bit: 8..15 Reserved */
+ uint32_t ADDRMASK:8; /*!< bit: 16..23 Address Mask */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SERCOM_SPI_ADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1280,10 +1280,10 @@ typedef union {
/* -------- SERCOM_I2CM_DATA : (SERCOM Offset: 0x28) (R/W 8) I2CM I2CM Data -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DATA:8; /*!< bit: 0.. 7 Data Value */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DATA:8; /*!< bit: 0.. 7 Data Value */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_I2CM_DATA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1298,10 +1298,10 @@ typedef union {
/* -------- SERCOM_I2CS_DATA : (SERCOM Offset: 0x28) (R/W 8) I2CS I2CS Data -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DATA:8; /*!< bit: 0.. 7 Data Value */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DATA:8; /*!< bit: 0.. 7 Data Value */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_I2CS_DATA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1316,11 +1316,11 @@ typedef union {
/* -------- SERCOM_SPI_DATA : (SERCOM Offset: 0x28) (R/W 32) SPI SPI Data -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t DATA:9; /*!< bit: 0.. 8 Data Value */
- uint32_t :23; /*!< bit: 9..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t DATA:9; /*!< bit: 0.. 8 Data Value */
+ uint32_t :23; /*!< bit: 9..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SERCOM_SPI_DATA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1335,11 +1335,11 @@ typedef union {
/* -------- SERCOM_USART_DATA : (SERCOM Offset: 0x28) (R/W 16) USART USART Data -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t DATA:9; /*!< bit: 0.. 8 Data Value */
- uint16_t :7; /*!< bit: 9..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t DATA:9; /*!< bit: 0.. 8 Data Value */
+ uint16_t :7; /*!< bit: 9..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} SERCOM_USART_DATA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1354,11 +1354,11 @@ typedef union {
/* -------- SERCOM_I2CM_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) I2CM I2CM Debug Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_I2CM_DBGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1372,11 +1372,11 @@ typedef union {
/* -------- SERCOM_SPI_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) SPI SPI Debug Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_SPI_DBGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1390,11 +1390,11 @@ typedef union {
/* -------- SERCOM_USART_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) USART USART Debug Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_USART_DBGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1408,101 +1408,101 @@ typedef union {
/** \brief SERCOM_I2CM hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* I2C Master Mode */
- __IO SERCOM_I2CM_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CM Control A */
- __IO SERCOM_I2CM_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CM Control B */
- RoReg8 Reserved1[0x4];
- __IO SERCOM_I2CM_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 32) I2CM Baud Rate */
- RoReg8 Reserved2[0x4];
- __IO SERCOM_I2CM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) I2CM Interrupt Enable Clear */
- RoReg8 Reserved3[0x1];
- __IO SERCOM_I2CM_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) I2CM Interrupt Enable Set */
- RoReg8 Reserved4[0x1];
- __IO SERCOM_I2CM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) I2CM Interrupt Flag Status and Clear */
- RoReg8 Reserved5[0x1];
- __IO SERCOM_I2CM_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) I2CM Status */
- __I SERCOM_I2CM_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) I2CM Syncbusy */
- RoReg8 Reserved6[0x4];
- __IO SERCOM_I2CM_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) I2CM Address */
- __IO SERCOM_I2CM_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 8) I2CM Data */
- RoReg8 Reserved7[0x7];
- __IO SERCOM_I2CM_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) I2CM Debug Control */
+ __IO SERCOM_I2CM_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CM Control A */
+ __IO SERCOM_I2CM_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CM Control B */
+ RoReg8 Reserved1[0x4];
+ __IO SERCOM_I2CM_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 32) I2CM Baud Rate */
+ RoReg8 Reserved2[0x4];
+ __IO SERCOM_I2CM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) I2CM Interrupt Enable Clear */
+ RoReg8 Reserved3[0x1];
+ __IO SERCOM_I2CM_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) I2CM Interrupt Enable Set */
+ RoReg8 Reserved4[0x1];
+ __IO SERCOM_I2CM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) I2CM Interrupt Flag Status and Clear */
+ RoReg8 Reserved5[0x1];
+ __IO SERCOM_I2CM_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) I2CM Status */
+ __I SERCOM_I2CM_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) I2CM Syncbusy */
+ RoReg8 Reserved6[0x4];
+ __IO SERCOM_I2CM_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) I2CM Address */
+ __IO SERCOM_I2CM_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 8) I2CM Data */
+ RoReg8 Reserved7[0x7];
+ __IO SERCOM_I2CM_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) I2CM Debug Control */
} SercomI2cm;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief SERCOM_I2CS hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* I2C Slave Mode */
- __IO SERCOM_I2CS_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CS Control A */
- __IO SERCOM_I2CS_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CS Control B */
- RoReg8 Reserved1[0xC];
- __IO SERCOM_I2CS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) I2CS Interrupt Enable Clear */
- RoReg8 Reserved2[0x1];
- __IO SERCOM_I2CS_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) I2CS Interrupt Enable Set */
- RoReg8 Reserved3[0x1];
- __IO SERCOM_I2CS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) I2CS Interrupt Flag Status and Clear */
- RoReg8 Reserved4[0x1];
- __IO SERCOM_I2CS_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) I2CS Status */
- __I SERCOM_I2CS_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) I2CS Syncbusy */
- RoReg8 Reserved5[0x4];
- __IO SERCOM_I2CS_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) I2CS Address */
- __IO SERCOM_I2CS_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 8) I2CS Data */
+ __IO SERCOM_I2CS_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CS Control A */
+ __IO SERCOM_I2CS_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CS Control B */
+ RoReg8 Reserved1[0xC];
+ __IO SERCOM_I2CS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) I2CS Interrupt Enable Clear */
+ RoReg8 Reserved2[0x1];
+ __IO SERCOM_I2CS_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) I2CS Interrupt Enable Set */
+ RoReg8 Reserved3[0x1];
+ __IO SERCOM_I2CS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) I2CS Interrupt Flag Status and Clear */
+ RoReg8 Reserved4[0x1];
+ __IO SERCOM_I2CS_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) I2CS Status */
+ __I SERCOM_I2CS_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) I2CS Syncbusy */
+ RoReg8 Reserved5[0x4];
+ __IO SERCOM_I2CS_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) I2CS Address */
+ __IO SERCOM_I2CS_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 8) I2CS Data */
} SercomI2cs;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief SERCOM_SPI hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* SPI Mode */
- __IO SERCOM_SPI_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) SPI Control A */
- __IO SERCOM_SPI_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) SPI Control B */
- RoReg8 Reserved1[0x4];
- __IO SERCOM_SPI_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 8) SPI Baud Rate */
- RoReg8 Reserved2[0x7];
- __IO SERCOM_SPI_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) SPI Interrupt Enable Clear */
- RoReg8 Reserved3[0x1];
- __IO SERCOM_SPI_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) SPI Interrupt Enable Set */
- RoReg8 Reserved4[0x1];
- __IO SERCOM_SPI_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) SPI Interrupt Flag Status and Clear */
- RoReg8 Reserved5[0x1];
- __IO SERCOM_SPI_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) SPI Status */
- __I SERCOM_SPI_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) SPI Syncbusy */
- RoReg8 Reserved6[0x4];
- __IO SERCOM_SPI_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) SPI Address */
- __IO SERCOM_SPI_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 32) SPI Data */
- RoReg8 Reserved7[0x4];
- __IO SERCOM_SPI_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) SPI Debug Control */
+ __IO SERCOM_SPI_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) SPI Control A */
+ __IO SERCOM_SPI_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) SPI Control B */
+ RoReg8 Reserved1[0x4];
+ __IO SERCOM_SPI_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 8) SPI Baud Rate */
+ RoReg8 Reserved2[0x7];
+ __IO SERCOM_SPI_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) SPI Interrupt Enable Clear */
+ RoReg8 Reserved3[0x1];
+ __IO SERCOM_SPI_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) SPI Interrupt Enable Set */
+ RoReg8 Reserved4[0x1];
+ __IO SERCOM_SPI_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) SPI Interrupt Flag Status and Clear */
+ RoReg8 Reserved5[0x1];
+ __IO SERCOM_SPI_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) SPI Status */
+ __I SERCOM_SPI_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) SPI Syncbusy */
+ RoReg8 Reserved6[0x4];
+ __IO SERCOM_SPI_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) SPI Address */
+ __IO SERCOM_SPI_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 32) SPI Data */
+ RoReg8 Reserved7[0x4];
+ __IO SERCOM_SPI_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) SPI Debug Control */
} SercomSpi;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief SERCOM_USART hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* USART Mode */
- __IO SERCOM_USART_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) USART Control A */
- __IO SERCOM_USART_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) USART Control B */
- RoReg8 Reserved1[0x4];
- __IO SERCOM_USART_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 16) USART Baud Rate */
- __IO SERCOM_USART_RXPL_Type RXPL; /**< \brief Offset: 0x0E (R/W 8) USART Receive Pulse Length */
- RoReg8 Reserved2[0x5];
- __IO SERCOM_USART_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) USART Interrupt Enable Clear */
- RoReg8 Reserved3[0x1];
- __IO SERCOM_USART_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) USART Interrupt Enable Set */
- RoReg8 Reserved4[0x1];
- __IO SERCOM_USART_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) USART Interrupt Flag Status and Clear */
- RoReg8 Reserved5[0x1];
- __IO SERCOM_USART_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) USART Status */
- __I SERCOM_USART_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) USART Syncbusy */
- RoReg8 Reserved6[0x8];
- __IO SERCOM_USART_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 16) USART Data */
- RoReg8 Reserved7[0x6];
- __IO SERCOM_USART_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) USART Debug Control */
+ __IO SERCOM_USART_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) USART Control A */
+ __IO SERCOM_USART_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) USART Control B */
+ RoReg8 Reserved1[0x4];
+ __IO SERCOM_USART_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 16) USART Baud Rate */
+ __IO SERCOM_USART_RXPL_Type RXPL; /**< \brief Offset: 0x0E (R/W 8) USART Receive Pulse Length */
+ RoReg8 Reserved2[0x5];
+ __IO SERCOM_USART_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) USART Interrupt Enable Clear */
+ RoReg8 Reserved3[0x1];
+ __IO SERCOM_USART_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) USART Interrupt Enable Set */
+ RoReg8 Reserved4[0x1];
+ __IO SERCOM_USART_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) USART Interrupt Flag Status and Clear */
+ RoReg8 Reserved5[0x1];
+ __IO SERCOM_USART_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) USART Status */
+ __I SERCOM_USART_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) USART Syncbusy */
+ RoReg8 Reserved6[0x8];
+ __IO SERCOM_USART_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 16) USART Data */
+ RoReg8 Reserved7[0x6];
+ __IO SERCOM_USART_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) USART Debug Control */
} SercomUsart;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- SercomI2cm I2CM; /**< \brief Offset: 0x00 I2C Master Mode */
- SercomI2cs I2CS; /**< \brief Offset: 0x00 I2C Slave Mode */
- SercomSpi SPI; /**< \brief Offset: 0x00 SPI Mode */
- SercomUsart USART; /**< \brief Offset: 0x00 USART Mode */
+ SercomI2cm I2CM; /**< \brief Offset: 0x00 I2C Master Mode */
+ SercomI2cs I2CS; /**< \brief Offset: 0x00 I2C Slave Mode */
+ SercomSpi SPI; /**< \brief Offset: 0x00 SPI Mode */
+ SercomUsart USART; /**< \brief Offset: 0x00 USART Mode */
} Sercom;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_sysctrl.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_sysctrl.h
index 1583d8893a6..6cd64b6ea98 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_sysctrl.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_sysctrl.h
@@ -59,26 +59,26 @@
/* -------- SYSCTRL_INTENCLR : (SYSCTRL Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready Interrupt Enable */
- uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready Interrupt Enable */
- uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready Interrupt Enable */
- uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready Interrupt Enable */
- uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready Interrupt Enable */
- uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds Interrupt Enable */
- uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine Interrupt Enable */
- uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse Interrupt Enable */
- uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped Interrupt Enable */
- uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready Interrupt Enable */
- uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection Interrupt Enable */
- uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready Interrupt Enable */
- uint32_t :3; /*!< bit: 12..14 Reserved */
- uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise Interrupt Enable */
- uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall Interrupt Enable */
- uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout Interrupt Enable */
- uint32_t :14; /*!< bit: 18..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready Interrupt Enable */
+ uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready Interrupt Enable */
+ uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready Interrupt Enable */
+ uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready Interrupt Enable */
+ uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready Interrupt Enable */
+ uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds Interrupt Enable */
+ uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine Interrupt Enable */
+ uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse Interrupt Enable */
+ uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped Interrupt Enable */
+ uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready Interrupt Enable */
+ uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection Interrupt Enable */
+ uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready Interrupt Enable */
+ uint32_t :3; /*!< bit: 12..14 Reserved */
+ uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise Interrupt Enable */
+ uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall Interrupt Enable */
+ uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout Interrupt Enable */
+ uint32_t :14; /*!< bit: 18..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SYSCTRL_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -120,26 +120,26 @@ typedef union {
/* -------- SYSCTRL_INTENSET : (SYSCTRL Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready Interrupt Enable */
- uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready Interrupt Enable */
- uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready Interrupt Enable */
- uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready Interrupt Enable */
- uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready Interrupt Enable */
- uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds Interrupt Enable */
- uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine Interrupt Enable */
- uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse Interrupt Enable */
- uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped Interrupt Enable */
- uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready Interrupt Enable */
- uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection Interrupt Enable */
- uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready Interrupt Enable */
- uint32_t :3; /*!< bit: 12..14 Reserved */
- uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise Interrupt Enable */
- uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall Interrupt Enable */
- uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout Interrupt Enable */
- uint32_t :14; /*!< bit: 18..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready Interrupt Enable */
+ uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready Interrupt Enable */
+ uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready Interrupt Enable */
+ uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready Interrupt Enable */
+ uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready Interrupt Enable */
+ uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds Interrupt Enable */
+ uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine Interrupt Enable */
+ uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse Interrupt Enable */
+ uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped Interrupt Enable */
+ uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready Interrupt Enable */
+ uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection Interrupt Enable */
+ uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready Interrupt Enable */
+ uint32_t :3; /*!< bit: 12..14 Reserved */
+ uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise Interrupt Enable */
+ uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall Interrupt Enable */
+ uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout Interrupt Enable */
+ uint32_t :14; /*!< bit: 18..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SYSCTRL_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -181,26 +181,26 @@ typedef union {
/* -------- SYSCTRL_INTFLAG : (SYSCTRL Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */
- uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready */
- uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready */
- uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready */
- uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready */
- uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds */
- uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine */
- uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse */
- uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped */
- uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready */
- uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection */
- uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready */
- uint32_t :3; /*!< bit: 12..14 Reserved */
- uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise */
- uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall */
- uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout */
- uint32_t :14; /*!< bit: 18..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */
+ uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready */
+ uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready */
+ uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready */
+ uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready */
+ uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds */
+ uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine */
+ uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse */
+ uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped */
+ uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready */
+ uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection */
+ uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready */
+ uint32_t :3; /*!< bit: 12..14 Reserved */
+ uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise */
+ uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall */
+ uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout */
+ uint32_t :14; /*!< bit: 18..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SYSCTRL_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -242,26 +242,26 @@ typedef union {
/* -------- SYSCTRL_PCLKSR : (SYSCTRL Offset: 0x0C) (R/ 32) Power and Clocks Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */
- uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready */
- uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready */
- uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready */
- uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready */
- uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds */
- uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine */
- uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse */
- uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped */
- uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready */
- uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection */
- uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready */
- uint32_t :3; /*!< bit: 12..14 Reserved */
- uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise */
- uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall */
- uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout */
- uint32_t :14; /*!< bit: 18..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */
+ uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready */
+ uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready */
+ uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready */
+ uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready */
+ uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds */
+ uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine */
+ uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse */
+ uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped */
+ uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready */
+ uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection */
+ uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready */
+ uint32_t :3; /*!< bit: 12..14 Reserved */
+ uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise */
+ uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall */
+ uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout */
+ uint32_t :14; /*!< bit: 18..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SYSCTRL_PCLKSR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -303,18 +303,18 @@ typedef union {
/* -------- SYSCTRL_XOSC : (SYSCTRL Offset: 0x10) (R/W 16) External Multipurpose Crystal Oscillator (XOSC) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t :1; /*!< bit: 0 Reserved */
- uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
- uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */
- uint16_t :3; /*!< bit: 3.. 5 Reserved */
- uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
- uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
- uint16_t GAIN:3; /*!< bit: 8..10 Oscillator Gain */
- uint16_t AMPGC:1; /*!< bit: 11 Automatic Amplitude Gain Control */
- uint16_t STARTUP:4; /*!< bit: 12..15 Start-Up Time */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t :1; /*!< bit: 0 Reserved */
+ uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
+ uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */
+ uint16_t :3; /*!< bit: 3.. 5 Reserved */
+ uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
+ uint16_t GAIN:3; /*!< bit: 8..10 Oscillator Gain */
+ uint16_t AMPGC:1; /*!< bit: 11 Automatic Amplitude Gain Control */
+ uint16_t STARTUP:4; /*!< bit: 12..15 Start-Up Time */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} SYSCTRL_XOSC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -352,21 +352,21 @@ typedef union {
/* -------- SYSCTRL_XOSC32K : (SYSCTRL Offset: 0x14) (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t :1; /*!< bit: 0 Reserved */
- uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
- uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */
- uint16_t EN32K:1; /*!< bit: 3 32kHz Output Enable */
- uint16_t EN1K:1; /*!< bit: 4 1kHz Output Enable */
- uint16_t AAMPEN:1; /*!< bit: 5 Automatic Amplitude Control Enable */
- uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
- uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
- uint16_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */
- uint16_t :1; /*!< bit: 11 Reserved */
- uint16_t WRTLOCK:1; /*!< bit: 12 Write Lock */
- uint16_t :3; /*!< bit: 13..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t :1; /*!< bit: 0 Reserved */
+ uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
+ uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */
+ uint16_t EN32K:1; /*!< bit: 3 32kHz Output Enable */
+ uint16_t EN1K:1; /*!< bit: 4 1kHz Output Enable */
+ uint16_t AAMPEN:1; /*!< bit: 5 Automatic Amplitude Control Enable */
+ uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
+ uint16_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */
+ uint16_t :1; /*!< bit: 11 Reserved */
+ uint16_t WRTLOCK:1; /*!< bit: 12 Write Lock */
+ uint16_t :3; /*!< bit: 13..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} SYSCTRL_XOSC32K_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -397,22 +397,22 @@ typedef union {
/* -------- SYSCTRL_OSC32K : (SYSCTRL Offset: 0x18) (R/W 32) 32kHz Internal Oscillator (OSC32K) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t :1; /*!< bit: 0 Reserved */
- uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
- uint32_t EN32K:1; /*!< bit: 2 32kHz Output Enable */
- uint32_t EN1K:1; /*!< bit: 3 1kHz Output Enable */
- uint32_t :2; /*!< bit: 4.. 5 Reserved */
- uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
- uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
- uint32_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */
- uint32_t :1; /*!< bit: 11 Reserved */
- uint32_t WRTLOCK:1; /*!< bit: 12 Write Lock */
- uint32_t :3; /*!< bit: 13..15 Reserved */
- uint32_t CALIB:7; /*!< bit: 16..22 Oscillator Calibration */
- uint32_t :9; /*!< bit: 23..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
+ uint32_t EN32K:1; /*!< bit: 2 32kHz Output Enable */
+ uint32_t EN1K:1; /*!< bit: 3 1kHz Output Enable */
+ uint32_t :2; /*!< bit: 4.. 5 Reserved */
+ uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
+ uint32_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */
+ uint32_t :1; /*!< bit: 11 Reserved */
+ uint32_t WRTLOCK:1; /*!< bit: 12 Write Lock */
+ uint32_t :3; /*!< bit: 13..15 Reserved */
+ uint32_t CALIB:7; /*!< bit: 16..22 Oscillator Calibration */
+ uint32_t :9; /*!< bit: 23..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SYSCTRL_OSC32K_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -442,12 +442,12 @@ typedef union {
/* -------- SYSCTRL_OSCULP32K : (SYSCTRL Offset: 0x1C) (R/W 8) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t CALIB:5; /*!< bit: 0.. 4 Oscillator Calibration */
- uint8_t :2; /*!< bit: 5.. 6 Reserved */
- uint8_t WRTLOCK:1; /*!< bit: 7 Write Lock */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t CALIB:5; /*!< bit: 0.. 4 Oscillator Calibration */
+ uint8_t :2; /*!< bit: 5.. 6 Reserved */
+ uint8_t WRTLOCK:1; /*!< bit: 7 Write Lock */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SYSCTRL_OSCULP32K_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -464,19 +464,19 @@ typedef union {
/* -------- SYSCTRL_OSC8M : (SYSCTRL Offset: 0x20) (R/W 32) 8MHz Internal Oscillator (OSC8M) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t :1; /*!< bit: 0 Reserved */
- uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
- uint32_t :4; /*!< bit: 2.. 5 Reserved */
- uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
- uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
- uint32_t PRESC:2; /*!< bit: 8.. 9 Oscillator Prescaler */
- uint32_t :6; /*!< bit: 10..15 Reserved */
- uint32_t CALIB:12; /*!< bit: 16..27 Oscillator Calibration */
- uint32_t :2; /*!< bit: 28..29 Reserved */
- uint32_t FRANGE:2; /*!< bit: 30..31 Oscillator Frequency Range */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
+ uint32_t :4; /*!< bit: 2.. 5 Reserved */
+ uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
+ uint32_t PRESC:2; /*!< bit: 8.. 9 Oscillator Prescaler */
+ uint32_t :6; /*!< bit: 10..15 Reserved */
+ uint32_t CALIB:12; /*!< bit: 16..27 Oscillator Calibration */
+ uint32_t :2; /*!< bit: 28..29 Reserved */
+ uint32_t FRANGE:2; /*!< bit: 30..31 Oscillator Frequency Range */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SYSCTRL_OSC8M_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -519,22 +519,22 @@ typedef union {
/* -------- SYSCTRL_DFLLCTRL : (SYSCTRL Offset: 0x24) (R/W 16) DFLL48M Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t :1; /*!< bit: 0 Reserved */
- uint16_t ENABLE:1; /*!< bit: 1 DFLL Enable */
- uint16_t MODE:1; /*!< bit: 2 Operating Mode Selection */
- uint16_t STABLE:1; /*!< bit: 3 Stable DFLL Frequency */
- uint16_t LLAW:1; /*!< bit: 4 Lose Lock After Wake */
- uint16_t USBCRM:1; /*!< bit: 5 USB Clock Recovery Mode */
- uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
- uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
- uint16_t CCDIS:1; /*!< bit: 8 Chill Cycle Disable */
- uint16_t QLDIS:1; /*!< bit: 9 Quick Lock Disable */
- uint16_t BPLCKC:1; /*!< bit: 10 Bypass Coarse Lock */
- uint16_t WAITLOCK:1; /*!< bit: 11 Wait Lock */
- uint16_t :4; /*!< bit: 12..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t :1; /*!< bit: 0 Reserved */
+ uint16_t ENABLE:1; /*!< bit: 1 DFLL Enable */
+ uint16_t MODE:1; /*!< bit: 2 Operating Mode Selection */
+ uint16_t STABLE:1; /*!< bit: 3 Stable DFLL Frequency */
+ uint16_t LLAW:1; /*!< bit: 4 Lose Lock After Wake */
+ uint16_t USBCRM:1; /*!< bit: 5 USB Clock Recovery Mode */
+ uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
+ uint16_t CCDIS:1; /*!< bit: 8 Chill Cycle Disable */
+ uint16_t QLDIS:1; /*!< bit: 9 Quick Lock Disable */
+ uint16_t BPLCKC:1; /*!< bit: 10 Bypass Coarse Lock */
+ uint16_t WAITLOCK:1; /*!< bit: 11 Wait Lock */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} SYSCTRL_DFLLCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -568,12 +568,12 @@ typedef union {
/* -------- SYSCTRL_DFLLVAL : (SYSCTRL Offset: 0x28) (R/W 32) DFLL48M Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t FINE:10; /*!< bit: 0.. 9 Fine Value */
- uint32_t COARSE:6; /*!< bit: 10..15 Coarse Value */
- uint32_t DIFF:16; /*!< bit: 16..31 Multiplication Ratio Difference */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t FINE:10; /*!< bit: 0.. 9 Fine Value */
+ uint32_t COARSE:6; /*!< bit: 10..15 Coarse Value */
+ uint32_t DIFF:16; /*!< bit: 16..31 Multiplication Ratio Difference */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SYSCTRL_DFLLVAL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -594,12 +594,12 @@ typedef union {
/* -------- SYSCTRL_DFLLMUL : (SYSCTRL Offset: 0x2C) (R/W 32) DFLL48M Multiplier -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t MUL:16; /*!< bit: 0..15 DFLL Multiply Factor */
- uint32_t FSTEP:10; /*!< bit: 16..25 Fine Maximum Step */
- uint32_t CSTEP:6; /*!< bit: 26..31 Coarse Maximum Step */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t MUL:16; /*!< bit: 0..15 DFLL Multiply Factor */
+ uint32_t FSTEP:10; /*!< bit: 16..25 Fine Maximum Step */
+ uint32_t CSTEP:6; /*!< bit: 26..31 Coarse Maximum Step */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SYSCTRL_DFLLMUL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -620,11 +620,11 @@ typedef union {
/* -------- SYSCTRL_DFLLSYNC : (SYSCTRL Offset: 0x30) (R/W 8) DFLL48M Synchronization -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t :7; /*!< bit: 0.. 6 Reserved */
- uint8_t READREQ:1; /*!< bit: 7 Read Request */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t :7; /*!< bit: 0.. 6 Reserved */
+ uint8_t READREQ:1; /*!< bit: 7 Read Request */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SYSCTRL_DFLLSYNC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -638,22 +638,22 @@ typedef union {
/* -------- SYSCTRL_BOD33 : (SYSCTRL Offset: 0x34) (R/W 32) 3.3V Brown-Out Detector (BOD33) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t :1; /*!< bit: 0 Reserved */
- uint32_t ENABLE:1; /*!< bit: 1 Enable */
- uint32_t HYST:1; /*!< bit: 2 Hysteresis */
- uint32_t ACTION:2; /*!< bit: 3.. 4 BOD33 Action */
- uint32_t :1; /*!< bit: 5 Reserved */
- uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
- uint32_t :1; /*!< bit: 7 Reserved */
- uint32_t MODE:1; /*!< bit: 8 Operation Mode */
- uint32_t CEN:1; /*!< bit: 9 Clock Enable */
- uint32_t :2; /*!< bit: 10..11 Reserved */
- uint32_t PSEL:4; /*!< bit: 12..15 Prescaler Select */
- uint32_t LEVEL:6; /*!< bit: 16..21 BOD33 Threshold Level */
- uint32_t :10; /*!< bit: 22..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */
+ uint32_t HYST:1; /*!< bit: 2 Hysteresis */
+ uint32_t ACTION:2; /*!< bit: 3.. 4 BOD33 Action */
+ uint32_t :1; /*!< bit: 5 Reserved */
+ uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint32_t :1; /*!< bit: 7 Reserved */
+ uint32_t MODE:1; /*!< bit: 8 Operation Mode */
+ uint32_t CEN:1; /*!< bit: 9 Clock Enable */
+ uint32_t :2; /*!< bit: 10..11 Reserved */
+ uint32_t PSEL:4; /*!< bit: 12..15 Prescaler Select */
+ uint32_t LEVEL:6; /*!< bit: 16..21 BOD33 Threshold Level */
+ uint32_t :10; /*!< bit: 22..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SYSCTRL_BOD33_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -722,14 +722,14 @@ typedef union {
/* -------- SYSCTRL_VREG : (SYSCTRL Offset: 0x3C) (R/W 16) Voltage Regulator System (VREG) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t :6; /*!< bit: 0.. 5 Reserved */
- uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
- uint16_t :6; /*!< bit: 7..12 Reserved */
- uint16_t FORCELDO:1; /*!< bit: 13 Force LDO Voltage Regulator */
- uint16_t :2; /*!< bit: 14..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t :6; /*!< bit: 0.. 5 Reserved */
+ uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint16_t :6; /*!< bit: 7..12 Reserved */
+ uint16_t FORCELDO:1; /*!< bit: 13 Force LDO Voltage Regulator */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} SYSCTRL_VREG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -745,15 +745,15 @@ typedef union {
/* -------- SYSCTRL_VREF : (SYSCTRL Offset: 0x40) (R/W 32) Voltage References System (VREF) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t :1; /*!< bit: 0 Reserved */
- uint32_t TSEN:1; /*!< bit: 1 Temperature Sensor Enable */
- uint32_t BGOUTEN:1; /*!< bit: 2 Bandgap Output Enable */
- uint32_t :13; /*!< bit: 3..15 Reserved */
- uint32_t CALIB:11; /*!< bit: 16..26 Bandgap Voltage Generator Calibration */
- uint32_t :5; /*!< bit: 27..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t TSEN:1; /*!< bit: 1 Temperature Sensor Enable */
+ uint32_t BGOUTEN:1; /*!< bit: 2 Bandgap Output Enable */
+ uint32_t :13; /*!< bit: 3..15 Reserved */
+ uint32_t CALIB:11; /*!< bit: 16..26 Bandgap Voltage Generator Calibration */
+ uint32_t :5; /*!< bit: 27..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SYSCTRL_VREF_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -772,14 +772,14 @@ typedef union {
/* -------- SYSCTRL_DPLLCTRLA : (SYSCTRL Offset: 0x44) (R/W 8) DPLL Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t :1; /*!< bit: 0 Reserved */
- uint8_t ENABLE:1; /*!< bit: 1 DPLL Enable */
- uint8_t :4; /*!< bit: 2.. 5 Reserved */
- uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
- uint8_t ONDEMAND:1; /*!< bit: 7 On Demand Clock Activation */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t :1; /*!< bit: 0 Reserved */
+ uint8_t ENABLE:1; /*!< bit: 1 DPLL Enable */
+ uint8_t :4; /*!< bit: 2.. 5 Reserved */
+ uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint8_t ONDEMAND:1; /*!< bit: 7 On Demand Clock Activation */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SYSCTRL_DPLLCTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -797,13 +797,13 @@ typedef union {
/* -------- SYSCTRL_DPLLRATIO : (SYSCTRL Offset: 0x48) (R/W 32) DPLL Ratio Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t LDR:12; /*!< bit: 0..11 Loop Divider Ratio */
- uint32_t :4; /*!< bit: 12..15 Reserved */
- uint32_t LDRFRAC:4; /*!< bit: 16..19 Loop Divider Ratio Fractional Part */
- uint32_t :12; /*!< bit: 20..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t LDR:12; /*!< bit: 0..11 Loop Divider Ratio */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t LDRFRAC:4; /*!< bit: 16..19 Loop Divider Ratio Fractional Part */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SYSCTRL_DPLLRATIO_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -821,20 +821,20 @@ typedef union {
/* -------- SYSCTRL_DPLLCTRLB : (SYSCTRL Offset: 0x4C) (R/W 32) DPLL Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t FILTER:2; /*!< bit: 0.. 1 Proportional Integral Filter Selection */
- uint32_t LPEN:1; /*!< bit: 2 Low-Power Enable */
- uint32_t WUF:1; /*!< bit: 3 Wake Up Fast */
- uint32_t REFCLK:2; /*!< bit: 4.. 5 Reference Clock Selection */
- uint32_t :2; /*!< bit: 6.. 7 Reserved */
- uint32_t LTIME:3; /*!< bit: 8..10 Lock Time */
- uint32_t :1; /*!< bit: 11 Reserved */
- uint32_t LBYPASS:1; /*!< bit: 12 Lock Bypass */
- uint32_t :3; /*!< bit: 13..15 Reserved */
- uint32_t DIV:11; /*!< bit: 16..26 Clock Divider */
- uint32_t :5; /*!< bit: 27..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t FILTER:2; /*!< bit: 0.. 1 Proportional Integral Filter Selection */
+ uint32_t LPEN:1; /*!< bit: 2 Low-Power Enable */
+ uint32_t WUF:1; /*!< bit: 3 Wake Up Fast */
+ uint32_t REFCLK:2; /*!< bit: 4.. 5 Reference Clock Selection */
+ uint32_t :2; /*!< bit: 6.. 7 Reserved */
+ uint32_t LTIME:3; /*!< bit: 8..10 Lock Time */
+ uint32_t :1; /*!< bit: 11 Reserved */
+ uint32_t LBYPASS:1; /*!< bit: 12 Lock Bypass */
+ uint32_t :3; /*!< bit: 13..15 Reserved */
+ uint32_t DIV:11; /*!< bit: 16..26 Clock Divider */
+ uint32_t :5; /*!< bit: 27..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SYSCTRL_DPLLCTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -888,14 +888,14 @@ typedef union {
/* -------- SYSCTRL_DPLLSTATUS : (SYSCTRL Offset: 0x50) (R/ 8) DPLL Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t LOCK:1; /*!< bit: 0 DPLL Lock Status */
- uint8_t CLKRDY:1; /*!< bit: 1 Output Clock Ready */
- uint8_t ENABLE:1; /*!< bit: 2 DPLL Enable */
- uint8_t DIV:1; /*!< bit: 3 Divider Enable */
- uint8_t :4; /*!< bit: 4.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t LOCK:1; /*!< bit: 0 DPLL Lock Status */
+ uint8_t CLKRDY:1; /*!< bit: 1 Output Clock Ready */
+ uint8_t ENABLE:1; /*!< bit: 2 DPLL Enable */
+ uint8_t DIV:1; /*!< bit: 3 Divider Enable */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SYSCTRL_DPLLSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -915,34 +915,34 @@ typedef union {
/** \brief SYSCTRL hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO SYSCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Clear */
- __IO SYSCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set */
- __IO SYSCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */
- __I SYSCTRL_PCLKSR_Type PCLKSR; /**< \brief Offset: 0x0C (R/ 32) Power and Clocks Status */
- __IO SYSCTRL_XOSC_Type XOSC; /**< \brief Offset: 0x10 (R/W 16) External Multipurpose Crystal Oscillator (XOSC) Control */
- RoReg8 Reserved1[0x2];
- __IO SYSCTRL_XOSC32K_Type XOSC32K; /**< \brief Offset: 0x14 (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control */
- RoReg8 Reserved2[0x2];
- __IO SYSCTRL_OSC32K_Type OSC32K; /**< \brief Offset: 0x18 (R/W 32) 32kHz Internal Oscillator (OSC32K) Control */
- __IO SYSCTRL_OSCULP32K_Type OSCULP32K; /**< \brief Offset: 0x1C (R/W 8) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
- RoReg8 Reserved3[0x3];
- __IO SYSCTRL_OSC8M_Type OSC8M; /**< \brief Offset: 0x20 (R/W 32) 8MHz Internal Oscillator (OSC8M) Control */
- __IO SYSCTRL_DFLLCTRL_Type DFLLCTRL; /**< \brief Offset: 0x24 (R/W 16) DFLL48M Control */
- RoReg8 Reserved4[0x2];
- __IO SYSCTRL_DFLLVAL_Type DFLLVAL; /**< \brief Offset: 0x28 (R/W 32) DFLL48M Value */
- __IO SYSCTRL_DFLLMUL_Type DFLLMUL; /**< \brief Offset: 0x2C (R/W 32) DFLL48M Multiplier */
- __IO SYSCTRL_DFLLSYNC_Type DFLLSYNC; /**< \brief Offset: 0x30 (R/W 8) DFLL48M Synchronization */
- RoReg8 Reserved5[0x3];
- __IO SYSCTRL_BOD33_Type BOD33; /**< \brief Offset: 0x34 (R/W 32) 3.3V Brown-Out Detector (BOD33) Control */
- RoReg8 Reserved6[0x4];
- __IO SYSCTRL_VREG_Type VREG; /**< \brief Offset: 0x3C (R/W 16) Voltage Regulator System (VREG) Control */
- RoReg8 Reserved7[0x2];
- __IO SYSCTRL_VREF_Type VREF; /**< \brief Offset: 0x40 (R/W 32) Voltage References System (VREF) Control */
- __IO SYSCTRL_DPLLCTRLA_Type DPLLCTRLA; /**< \brief Offset: 0x44 (R/W 8) DPLL Control A */
- RoReg8 Reserved8[0x3];
- __IO SYSCTRL_DPLLRATIO_Type DPLLRATIO; /**< \brief Offset: 0x48 (R/W 32) DPLL Ratio Control */
- __IO SYSCTRL_DPLLCTRLB_Type DPLLCTRLB; /**< \brief Offset: 0x4C (R/W 32) DPLL Control B */
- __I SYSCTRL_DPLLSTATUS_Type DPLLSTATUS; /**< \brief Offset: 0x50 (R/ 8) DPLL Status */
+ __IO SYSCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Clear */
+ __IO SYSCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set */
+ __IO SYSCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */
+ __I SYSCTRL_PCLKSR_Type PCLKSR; /**< \brief Offset: 0x0C (R/ 32) Power and Clocks Status */
+ __IO SYSCTRL_XOSC_Type XOSC; /**< \brief Offset: 0x10 (R/W 16) External Multipurpose Crystal Oscillator (XOSC) Control */
+ RoReg8 Reserved1[0x2];
+ __IO SYSCTRL_XOSC32K_Type XOSC32K; /**< \brief Offset: 0x14 (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control */
+ RoReg8 Reserved2[0x2];
+ __IO SYSCTRL_OSC32K_Type OSC32K; /**< \brief Offset: 0x18 (R/W 32) 32kHz Internal Oscillator (OSC32K) Control */
+ __IO SYSCTRL_OSCULP32K_Type OSCULP32K; /**< \brief Offset: 0x1C (R/W 8) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
+ RoReg8 Reserved3[0x3];
+ __IO SYSCTRL_OSC8M_Type OSC8M; /**< \brief Offset: 0x20 (R/W 32) 8MHz Internal Oscillator (OSC8M) Control */
+ __IO SYSCTRL_DFLLCTRL_Type DFLLCTRL; /**< \brief Offset: 0x24 (R/W 16) DFLL48M Control */
+ RoReg8 Reserved4[0x2];
+ __IO SYSCTRL_DFLLVAL_Type DFLLVAL; /**< \brief Offset: 0x28 (R/W 32) DFLL48M Value */
+ __IO SYSCTRL_DFLLMUL_Type DFLLMUL; /**< \brief Offset: 0x2C (R/W 32) DFLL48M Multiplier */
+ __IO SYSCTRL_DFLLSYNC_Type DFLLSYNC; /**< \brief Offset: 0x30 (R/W 8) DFLL48M Synchronization */
+ RoReg8 Reserved5[0x3];
+ __IO SYSCTRL_BOD33_Type BOD33; /**< \brief Offset: 0x34 (R/W 32) 3.3V Brown-Out Detector (BOD33) Control */
+ RoReg8 Reserved6[0x4];
+ __IO SYSCTRL_VREG_Type VREG; /**< \brief Offset: 0x3C (R/W 16) Voltage Regulator System (VREG) Control */
+ RoReg8 Reserved7[0x2];
+ __IO SYSCTRL_VREF_Type VREF; /**< \brief Offset: 0x40 (R/W 32) Voltage References System (VREF) Control */
+ __IO SYSCTRL_DPLLCTRLA_Type DPLLCTRLA; /**< \brief Offset: 0x44 (R/W 8) DPLL Control A */
+ RoReg8 Reserved8[0x3];
+ __IO SYSCTRL_DPLLRATIO_Type DPLLRATIO; /**< \brief Offset: 0x48 (R/W 32) DPLL Ratio Control */
+ __IO SYSCTRL_DPLLCTRLB_Type DPLLCTRLB; /**< \brief Offset: 0x4C (R/W 32) DPLL Control B */
+ __I SYSCTRL_DPLLSTATUS_Type DPLLSTATUS; /**< \brief Offset: 0x50 (R/ 8) DPLL Status */
} Sysctrl;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_tc.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_tc.h
index f631f961ddf..5bf0b1f9f66 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_tc.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_tc.h
@@ -59,19 +59,19 @@
/* -------- TC_CTRLA : (TC Offset: 0x00) (R/W 16) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t SWRST:1; /*!< bit: 0 Software Reset */
- uint16_t ENABLE:1; /*!< bit: 1 Enable */
- uint16_t MODE:2; /*!< bit: 2.. 3 TC Mode */
- uint16_t :1; /*!< bit: 4 Reserved */
- uint16_t WAVEGEN:2; /*!< bit: 5.. 6 Waveform Generation Operation */
- uint16_t :1; /*!< bit: 7 Reserved */
- uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler */
- uint16_t RUNSTDBY:1; /*!< bit: 11 Run in Standby */
- uint16_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization */
- uint16_t :2; /*!< bit: 14..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint16_t ENABLE:1; /*!< bit: 1 Enable */
+ uint16_t MODE:2; /*!< bit: 2.. 3 TC Mode */
+ uint16_t :1; /*!< bit: 4 Reserved */
+ uint16_t WAVEGEN:2; /*!< bit: 5.. 6 Waveform Generation Operation */
+ uint16_t :1; /*!< bit: 7 Reserved */
+ uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler */
+ uint16_t RUNSTDBY:1; /*!< bit: 11 Run in Standby */
+ uint16_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} TC_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -137,13 +137,13 @@ typedef union {
/* -------- TC_READREQ : (TC Offset: 0x02) (R/W 16) Read Request -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t ADDR:5; /*!< bit: 0.. 4 Address */
- uint16_t :9; /*!< bit: 5..13 Reserved */
- uint16_t RCONT:1; /*!< bit: 14 Read Continuously */
- uint16_t RREQ:1; /*!< bit: 15 Read Request */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t ADDR:5; /*!< bit: 0.. 4 Address */
+ uint16_t :9; /*!< bit: 5..13 Reserved */
+ uint16_t RCONT:1; /*!< bit: 14 Read Continuously */
+ uint16_t RREQ:1; /*!< bit: 15 Read Request */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} TC_READREQ_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -162,14 +162,14 @@ typedef union {
/* -------- TC_CTRLBCLR : (TC Offset: 0x04) (R/W 8) Control B Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DIR:1; /*!< bit: 0 Counter Direction */
- uint8_t :1; /*!< bit: 1 Reserved */
- uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
- uint8_t :3; /*!< bit: 3.. 5 Reserved */
- uint8_t CMD:2; /*!< bit: 6.. 7 Command */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DIR:1; /*!< bit: 0 Counter Direction */
+ uint8_t :1; /*!< bit: 1 Reserved */
+ uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
+ uint8_t :3; /*!< bit: 3.. 5 Reserved */
+ uint8_t CMD:2; /*!< bit: 6.. 7 Command */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} TC_CTRLBCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -194,14 +194,14 @@ typedef union {
/* -------- TC_CTRLBSET : (TC Offset: 0x05) (R/W 8) Control B Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DIR:1; /*!< bit: 0 Counter Direction */
- uint8_t :1; /*!< bit: 1 Reserved */
- uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
- uint8_t :3; /*!< bit: 3.. 5 Reserved */
- uint8_t CMD:2; /*!< bit: 6.. 7 Command */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DIR:1; /*!< bit: 0 Counter Direction */
+ uint8_t :1; /*!< bit: 1 Reserved */
+ uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
+ uint8_t :3; /*!< bit: 3.. 5 Reserved */
+ uint8_t CMD:2; /*!< bit: 6.. 7 Command */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} TC_CTRLBSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -226,21 +226,21 @@ typedef union {
/* -------- TC_CTRLC : (TC Offset: 0x06) (R/W 8) Control C -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t INVEN0:1; /*!< bit: 0 Output Waveform 0 Invert Enable */
- uint8_t INVEN1:1; /*!< bit: 1 Output Waveform 1 Invert Enable */
- uint8_t :2; /*!< bit: 2.. 3 Reserved */
- uint8_t CPTEN0:1; /*!< bit: 4 Capture Channel 0 Enable */
- uint8_t CPTEN1:1; /*!< bit: 5 Capture Channel 1 Enable */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t INVEN:2; /*!< bit: 0.. 1 Output Waveform x Invert Enable */
- uint8_t :2; /*!< bit: 2.. 3 Reserved */
- uint8_t CPTEN:2; /*!< bit: 4.. 5 Capture Channel x Enable */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t INVEN0:1; /*!< bit: 0 Output Waveform 0 Invert Enable */
+ uint8_t INVEN1:1; /*!< bit: 1 Output Waveform 1 Invert Enable */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t CPTEN0:1; /*!< bit: 4 Capture Channel 0 Enable */
+ uint8_t CPTEN1:1; /*!< bit: 5 Capture Channel 1 Enable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t INVEN:2; /*!< bit: 0.. 1 Output Waveform x Invert Enable */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t CPTEN:2; /*!< bit: 4.. 5 Capture Channel x Enable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} TC_CTRLC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -266,11 +266,11 @@ typedef union {
/* -------- TC_DBGCTRL : (TC Offset: 0x08) (R/W 8) Debug Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DBGRUN:1; /*!< bit: 0 Debug Run Mode */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DBGRUN:1; /*!< bit: 0 Debug Run Mode */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} TC_DBGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -284,24 +284,24 @@ typedef union {
/* -------- TC_EVCTRL : (TC Offset: 0x0A) (R/W 16) Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t EVACT:3; /*!< bit: 0.. 2 Event Action */
- uint16_t :1; /*!< bit: 3 Reserved */
- uint16_t TCINV:1; /*!< bit: 4 TC Inverted Event Input */
- uint16_t TCEI:1; /*!< bit: 5 TC Event Input */
- uint16_t :2; /*!< bit: 6.. 7 Reserved */
- uint16_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Event Output Enable */
- uint16_t :3; /*!< bit: 9..11 Reserved */
- uint16_t MCEO0:1; /*!< bit: 12 Match or Capture Channel 0 Event Output Enable */
- uint16_t MCEO1:1; /*!< bit: 13 Match or Capture Channel 1 Event Output Enable */
- uint16_t :2; /*!< bit: 14..15 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint16_t :12; /*!< bit: 0..11 Reserved */
- uint16_t MCEO:2; /*!< bit: 12..13 Match or Capture Channel x Event Output Enable */
- uint16_t :2; /*!< bit: 14..15 Reserved */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t EVACT:3; /*!< bit: 0.. 2 Event Action */
+ uint16_t :1; /*!< bit: 3 Reserved */
+ uint16_t TCINV:1; /*!< bit: 4 TC Inverted Event Input */
+ uint16_t TCEI:1; /*!< bit: 5 TC Event Input */
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ uint16_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Event Output Enable */
+ uint16_t :3; /*!< bit: 9..11 Reserved */
+ uint16_t MCEO0:1; /*!< bit: 12 Match or Capture Channel 0 Event Output Enable */
+ uint16_t MCEO1:1; /*!< bit: 13 Match or Capture Channel 1 Event Output Enable */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t :12; /*!< bit: 0..11 Reserved */
+ uint16_t MCEO:2; /*!< bit: 12..13 Match or Capture Channel x Event Output Enable */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
} TC_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -341,21 +341,21 @@ typedef union {
/* -------- TC_INTENCLR : (TC Offset: 0x0C) (R/W 8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
- uint8_t ERR:1; /*!< bit: 1 Error Interrupt Enable */
- uint8_t :1; /*!< bit: 2 Reserved */
- uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
- uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 Interrupt Enable */
- uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 Interrupt Enable */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t :4; /*!< bit: 0.. 3 Reserved */
- uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x Interrupt Enable */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
+ uint8_t ERR:1; /*!< bit: 1 Error Interrupt Enable */
+ uint8_t :1; /*!< bit: 2 Reserved */
+ uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
+ uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 Interrupt Enable */
+ uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 Interrupt Enable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t :4; /*!< bit: 0.. 3 Reserved */
+ uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x Interrupt Enable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} TC_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -380,21 +380,21 @@ typedef union {
/* -------- TC_INTENSET : (TC Offset: 0x0D) (R/W 8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
- uint8_t ERR:1; /*!< bit: 1 Error Interrupt Enable */
- uint8_t :1; /*!< bit: 2 Reserved */
- uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
- uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 Interrupt Enable */
- uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 Interrupt Enable */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t :4; /*!< bit: 0.. 3 Reserved */
- uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x Interrupt Enable */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
+ uint8_t ERR:1; /*!< bit: 1 Error Interrupt Enable */
+ uint8_t :1; /*!< bit: 2 Reserved */
+ uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
+ uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 Interrupt Enable */
+ uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 Interrupt Enable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t :4; /*!< bit: 0.. 3 Reserved */
+ uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x Interrupt Enable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} TC_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -419,21 +419,21 @@ typedef union {
/* -------- TC_INTFLAG : (TC Offset: 0x0E) (R/W 8) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t OVF:1; /*!< bit: 0 Overflow */
- uint8_t ERR:1; /*!< bit: 1 Error */
- uint8_t :1; /*!< bit: 2 Reserved */
- uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */
- uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 */
- uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t :4; /*!< bit: 0.. 3 Reserved */
- uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t OVF:1; /*!< bit: 0 Overflow */
+ uint8_t ERR:1; /*!< bit: 1 Error */
+ uint8_t :1; /*!< bit: 2 Reserved */
+ uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */
+ uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 */
+ uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t :4; /*!< bit: 0.. 3 Reserved */
+ uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} TC_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -458,14 +458,14 @@ typedef union {
/* -------- TC_STATUS : (TC Offset: 0x0F) (R/ 8) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t :3; /*!< bit: 0.. 2 Reserved */
- uint8_t STOP:1; /*!< bit: 3 Stop */
- uint8_t SLAVE:1; /*!< bit: 4 Slave */
- uint8_t :2; /*!< bit: 5.. 6 Reserved */
- uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t :3; /*!< bit: 0.. 2 Reserved */
+ uint8_t STOP:1; /*!< bit: 3 Stop */
+ uint8_t SLAVE:1; /*!< bit: 4 Slave */
+ uint8_t :2; /*!< bit: 5.. 6 Reserved */
+ uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} TC_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -483,10 +483,10 @@ typedef union {
/* -------- TC_COUNT16_COUNT : (TC Offset: 0x10) (R/W 16) COUNT16 COUNT16 Counter Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t COUNT:16; /*!< bit: 0..15 Count Value */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t COUNT:16; /*!< bit: 0..15 Count Value */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} TC_COUNT16_COUNT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -501,10 +501,10 @@ typedef union {
/* -------- TC_COUNT32_COUNT : (TC Offset: 0x10) (R/W 32) COUNT32 COUNT32 Counter Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t COUNT:32; /*!< bit: 0..31 Count Value */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t COUNT:32; /*!< bit: 0..31 Count Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} TC_COUNT32_COUNT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -519,10 +519,10 @@ typedef union {
/* -------- TC_COUNT8_COUNT : (TC Offset: 0x10) (R/W 8) COUNT8 COUNT8 Counter Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t COUNT:8; /*!< bit: 0.. 7 Counter Value */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t COUNT:8; /*!< bit: 0.. 7 Counter Value */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} TC_COUNT8_COUNT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -537,10 +537,10 @@ typedef union {
/* -------- TC_COUNT8_PER : (TC Offset: 0x14) (R/W 8) COUNT8 COUNT8 Period Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t PER:8; /*!< bit: 0.. 7 Period Value */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t PER:8; /*!< bit: 0.. 7 Period Value */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} TC_COUNT8_PER_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -555,10 +555,10 @@ typedef union {
/* -------- TC_COUNT16_CC : (TC Offset: 0x18) (R/W 16) COUNT16 COUNT16 Compare/Capture -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t CC:16; /*!< bit: 0..15 Compare/Capture Value */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t CC:16; /*!< bit: 0..15 Compare/Capture Value */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} TC_COUNT16_CC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -573,10 +573,10 @@ typedef union {
/* -------- TC_COUNT32_CC : (TC Offset: 0x18) (R/W 32) COUNT32 COUNT32 Compare/Capture -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t CC:32; /*!< bit: 0..31 Compare/Capture Value */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t CC:32; /*!< bit: 0..31 Compare/Capture Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} TC_COUNT32_CC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -591,10 +591,10 @@ typedef union {
/* -------- TC_COUNT8_CC : (TC Offset: 0x18) (R/W 8) COUNT8 COUNT8 Compare/Capture -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t CC:8; /*!< bit: 0.. 7 Compare/Capture Value */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t CC:8; /*!< bit: 0.. 7 Compare/Capture Value */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} TC_COUNT8_CC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -609,76 +609,76 @@ typedef union {
/** \brief TC_COUNT8 hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* 8-bit Counter Mode */
- __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
- __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
- __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
- __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
- __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */
- RoReg8 Reserved1[0x1];
- __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */
- RoReg8 Reserved2[0x1];
- __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */
- __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
- __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */
- __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */
- __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */
- __IO TC_COUNT8_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 8) COUNT8 Counter Value */
- RoReg8 Reserved3[0x3];
- __IO TC_COUNT8_PER_Type PER; /**< \brief Offset: 0x14 (R/W 8) COUNT8 Period Value */
- RoReg8 Reserved4[0x3];
- __IO TC_COUNT8_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 8) COUNT8 Compare/Capture */
+ __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
+ __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
+ __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
+ __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
+ __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */
+ RoReg8 Reserved1[0x1];
+ __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */
+ RoReg8 Reserved2[0x1];
+ __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */
+ __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
+ __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */
+ __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */
+ __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */
+ __IO TC_COUNT8_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 8) COUNT8 Counter Value */
+ RoReg8 Reserved3[0x3];
+ __IO TC_COUNT8_PER_Type PER; /**< \brief Offset: 0x14 (R/W 8) COUNT8 Period Value */
+ RoReg8 Reserved4[0x3];
+ __IO TC_COUNT8_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 8) COUNT8 Compare/Capture */
} TcCount8;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief TC_COUNT16 hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* 16-bit Counter Mode */
- __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
- __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
- __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
- __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
- __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */
- RoReg8 Reserved1[0x1];
- __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */
- RoReg8 Reserved2[0x1];
- __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */
- __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
- __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */
- __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */
- __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */
- __IO TC_COUNT16_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 16) COUNT16 Counter Value */
- RoReg8 Reserved3[0x6];
- __IO TC_COUNT16_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 16) COUNT16 Compare/Capture */
+ __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
+ __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
+ __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
+ __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
+ __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */
+ RoReg8 Reserved1[0x1];
+ __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */
+ RoReg8 Reserved2[0x1];
+ __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */
+ __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
+ __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */
+ __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */
+ __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */
+ __IO TC_COUNT16_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 16) COUNT16 Counter Value */
+ RoReg8 Reserved3[0x6];
+ __IO TC_COUNT16_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 16) COUNT16 Compare/Capture */
} TcCount16;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief TC_COUNT32 hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* 32-bit Counter Mode */
- __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
- __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
- __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
- __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
- __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */
- RoReg8 Reserved1[0x1];
- __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */
- RoReg8 Reserved2[0x1];
- __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */
- __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
- __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */
- __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */
- __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */
- __IO TC_COUNT32_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 32) COUNT32 Counter Value */
- RoReg8 Reserved3[0x4];
- __IO TC_COUNT32_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 32) COUNT32 Compare/Capture */
+ __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
+ __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
+ __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
+ __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
+ __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */
+ RoReg8 Reserved1[0x1];
+ __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */
+ RoReg8 Reserved2[0x1];
+ __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */
+ __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
+ __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */
+ __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */
+ __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */
+ __IO TC_COUNT32_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 32) COUNT32 Counter Value */
+ RoReg8 Reserved3[0x4];
+ __IO TC_COUNT32_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 32) COUNT32 Compare/Capture */
} TcCount32;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- TcCount8 COUNT8; /**< \brief Offset: 0x00 8-bit Counter Mode */
- TcCount16 COUNT16; /**< \brief Offset: 0x00 16-bit Counter Mode */
- TcCount32 COUNT32; /**< \brief Offset: 0x00 32-bit Counter Mode */
+ TcCount8 COUNT8; /**< \brief Offset: 0x00 8-bit Counter Mode */
+ TcCount16 COUNT16; /**< \brief Offset: 0x00 16-bit Counter Mode */
+ TcCount32 COUNT32; /**< \brief Offset: 0x00 32-bit Counter Mode */
} Tc;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_tcc.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_tcc.h
index ddbf7bb6ae5..fc23a16d11f 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_tcc.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_tcc.h
@@ -59,29 +59,29 @@
/* -------- TCC_CTRLA : (TCC Offset: 0x00) (R/W 32) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Software Reset */
- uint32_t ENABLE:1; /*!< bit: 1 Enable */
- uint32_t :3; /*!< bit: 2.. 4 Reserved */
- uint32_t RESOLUTION:2; /*!< bit: 5.. 6 Enhanced Resolution */
- uint32_t :1; /*!< bit: 7 Reserved */
- uint32_t PRESCALER:3; /*!< bit: 8..10 Prescaler */
- uint32_t RUNSTDBY:1; /*!< bit: 11 Run in Standby */
- uint32_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization Selection */
- uint32_t ALOCK:1; /*!< bit: 14 Auto Lock */
- uint32_t :9; /*!< bit: 15..23 Reserved */
- uint32_t CPTEN0:1; /*!< bit: 24 Capture Channel 0 Enable */
- uint32_t CPTEN1:1; /*!< bit: 25 Capture Channel 1 Enable */
- uint32_t CPTEN2:1; /*!< bit: 26 Capture Channel 2 Enable */
- uint32_t CPTEN3:1; /*!< bit: 27 Capture Channel 3 Enable */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :24; /*!< bit: 0..23 Reserved */
- uint32_t CPTEN:4; /*!< bit: 24..27 Capture Channel x Enable */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */
+ uint32_t :3; /*!< bit: 2.. 4 Reserved */
+ uint32_t RESOLUTION:2; /*!< bit: 5.. 6 Enhanced Resolution */
+ uint32_t :1; /*!< bit: 7 Reserved */
+ uint32_t PRESCALER:3; /*!< bit: 8..10 Prescaler */
+ uint32_t RUNSTDBY:1; /*!< bit: 11 Run in Standby */
+ uint32_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization Selection */
+ uint32_t ALOCK:1; /*!< bit: 14 Auto Lock */
+ uint32_t :9; /*!< bit: 15..23 Reserved */
+ uint32_t CPTEN0:1; /*!< bit: 24 Capture Channel 0 Enable */
+ uint32_t CPTEN1:1; /*!< bit: 25 Capture Channel 1 Enable */
+ uint32_t CPTEN2:1; /*!< bit: 26 Capture Channel 2 Enable */
+ uint32_t CPTEN3:1; /*!< bit: 27 Capture Channel 3 Enable */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :24; /*!< bit: 0..23 Reserved */
+ uint32_t CPTEN:4; /*!< bit: 24..27 Capture Channel x Enable */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -151,14 +151,14 @@ typedef union {
/* -------- TCC_CTRLBCLR : (TCC Offset: 0x04) (R/W 8) Control B Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DIR:1; /*!< bit: 0 Counter Direction */
- uint8_t LUPD:1; /*!< bit: 1 Lock Update */
- uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
- uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */
- uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DIR:1; /*!< bit: 0 Counter Direction */
+ uint8_t LUPD:1; /*!< bit: 1 Lock Update */
+ uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
+ uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */
+ uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} TCC_CTRLBCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -200,14 +200,14 @@ typedef union {
/* -------- TCC_CTRLBSET : (TCC Offset: 0x05) (R/W 8) Control B Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DIR:1; /*!< bit: 0 Counter Direction */
- uint8_t LUPD:1; /*!< bit: 1 Lock Update */
- uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
- uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */
- uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DIR:1; /*!< bit: 0 Counter Direction */
+ uint8_t LUPD:1; /*!< bit: 1 Lock Update */
+ uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
+ uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */
+ uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} TCC_CTRLBSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -249,37 +249,37 @@ typedef union {
/* -------- TCC_SYNCBUSY : (TCC Offset: 0x08) (R/ 32) Synchronization Busy -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Swrst Busy */
- uint32_t ENABLE:1; /*!< bit: 1 Enable Busy */
- uint32_t CTRLB:1; /*!< bit: 2 Ctrlb Busy */
- uint32_t STATUS:1; /*!< bit: 3 Status Busy */
- uint32_t COUNT:1; /*!< bit: 4 Count Busy */
- uint32_t PATT:1; /*!< bit: 5 Pattern Busy */
- uint32_t WAVE:1; /*!< bit: 6 Wave Busy */
- uint32_t PER:1; /*!< bit: 7 Period busy */
- uint32_t CC0:1; /*!< bit: 8 Compare Channel 0 Busy */
- uint32_t CC1:1; /*!< bit: 9 Compare Channel 1 Busy */
- uint32_t CC2:1; /*!< bit: 10 Compare Channel 2 Busy */
- uint32_t CC3:1; /*!< bit: 11 Compare Channel 3 Busy */
- uint32_t :4; /*!< bit: 12..15 Reserved */
- uint32_t PATTB:1; /*!< bit: 16 Pattern Buffer Busy */
- uint32_t WAVEB:1; /*!< bit: 17 Wave Buffer Busy */
- uint32_t PERB:1; /*!< bit: 18 Period Buffer Busy */
- uint32_t CCB0:1; /*!< bit: 19 Compare Channel Buffer 0 Busy */
- uint32_t CCB1:1; /*!< bit: 20 Compare Channel Buffer 1 Busy */
- uint32_t CCB2:1; /*!< bit: 21 Compare Channel Buffer 2 Busy */
- uint32_t CCB3:1; /*!< bit: 22 Compare Channel Buffer 3 Busy */
- uint32_t :9; /*!< bit: 23..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :8; /*!< bit: 0.. 7 Reserved */
- uint32_t CC:4; /*!< bit: 8..11 Compare Channel x Busy */
- uint32_t :7; /*!< bit: 12..18 Reserved */
- uint32_t CCB:4; /*!< bit: 19..22 Compare Channel Buffer x Busy */
- uint32_t :9; /*!< bit: 23..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Swrst Busy */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable Busy */
+ uint32_t CTRLB:1; /*!< bit: 2 Ctrlb Busy */
+ uint32_t STATUS:1; /*!< bit: 3 Status Busy */
+ uint32_t COUNT:1; /*!< bit: 4 Count Busy */
+ uint32_t PATT:1; /*!< bit: 5 Pattern Busy */
+ uint32_t WAVE:1; /*!< bit: 6 Wave Busy */
+ uint32_t PER:1; /*!< bit: 7 Period busy */
+ uint32_t CC0:1; /*!< bit: 8 Compare Channel 0 Busy */
+ uint32_t CC1:1; /*!< bit: 9 Compare Channel 1 Busy */
+ uint32_t CC2:1; /*!< bit: 10 Compare Channel 2 Busy */
+ uint32_t CC3:1; /*!< bit: 11 Compare Channel 3 Busy */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t PATTB:1; /*!< bit: 16 Pattern Buffer Busy */
+ uint32_t WAVEB:1; /*!< bit: 17 Wave Buffer Busy */
+ uint32_t PERB:1; /*!< bit: 18 Period Buffer Busy */
+ uint32_t CCB0:1; /*!< bit: 19 Compare Channel Buffer 0 Busy */
+ uint32_t CCB1:1; /*!< bit: 20 Compare Channel Buffer 1 Busy */
+ uint32_t CCB2:1; /*!< bit: 21 Compare Channel Buffer 2 Busy */
+ uint32_t CCB3:1; /*!< bit: 22 Compare Channel Buffer 3 Busy */
+ uint32_t :9; /*!< bit: 23..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :8; /*!< bit: 0.. 7 Reserved */
+ uint32_t CC:4; /*!< bit: 8..11 Compare Channel x Busy */
+ uint32_t :7; /*!< bit: 12..18 Reserved */
+ uint32_t CCB:4; /*!< bit: 19..22 Compare Channel Buffer x Busy */
+ uint32_t :9; /*!< bit: 23..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_SYNCBUSY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -335,22 +335,22 @@ typedef union {
/* -------- TCC_FCTRLA : (TCC Offset: 0x0C) (R/W 32) Recoverable Fault A Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SRC:2; /*!< bit: 0.. 1 Fault A Source */
- uint32_t :1; /*!< bit: 2 Reserved */
- uint32_t KEEP:1; /*!< bit: 3 Fault A Keeper */
- uint32_t QUAL:1; /*!< bit: 4 Fault A Qualification */
- uint32_t BLANK:2; /*!< bit: 5.. 6 Fault A Blanking Mode */
- uint32_t RESTART:1; /*!< bit: 7 Fault A Restart */
- uint32_t HALT:2; /*!< bit: 8.. 9 Fault A Halt Mode */
- uint32_t CHSEL:2; /*!< bit: 10..11 Fault A Capture Channel */
- uint32_t CAPTURE:3; /*!< bit: 12..14 Fault A Capture Action */
- uint32_t :1; /*!< bit: 15 Reserved */
- uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault A Blanking Time */
- uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault A Filter Value */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SRC:2; /*!< bit: 0.. 1 Fault A Source */
+ uint32_t :1; /*!< bit: 2 Reserved */
+ uint32_t KEEP:1; /*!< bit: 3 Fault A Keeper */
+ uint32_t QUAL:1; /*!< bit: 4 Fault A Qualification */
+ uint32_t BLANK:2; /*!< bit: 5.. 6 Fault A Blanking Mode */
+ uint32_t RESTART:1; /*!< bit: 7 Fault A Restart */
+ uint32_t HALT:2; /*!< bit: 8.. 9 Fault A Halt Mode */
+ uint32_t CHSEL:2; /*!< bit: 10..11 Fault A Capture Channel */
+ uint32_t CAPTURE:3; /*!< bit: 12..14 Fault A Capture Action */
+ uint32_t :1; /*!< bit: 15 Reserved */
+ uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault A Blanking Time */
+ uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault A Filter Value */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_FCTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -435,22 +435,22 @@ typedef union {
/* -------- TCC_FCTRLB : (TCC Offset: 0x10) (R/W 32) Recoverable Fault B Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SRC:2; /*!< bit: 0.. 1 Fault B Source */
- uint32_t :1; /*!< bit: 2 Reserved */
- uint32_t KEEP:1; /*!< bit: 3 Fault B Keeper */
- uint32_t QUAL:1; /*!< bit: 4 Fault B Qualification */
- uint32_t BLANK:2; /*!< bit: 5.. 6 Fault B Blanking Mode */
- uint32_t RESTART:1; /*!< bit: 7 Fault B Restart */
- uint32_t HALT:2; /*!< bit: 8.. 9 Fault B Halt Mode */
- uint32_t CHSEL:2; /*!< bit: 10..11 Fault B Capture Channel */
- uint32_t CAPTURE:3; /*!< bit: 12..14 Fault B Capture Action */
- uint32_t :1; /*!< bit: 15 Reserved */
- uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault B Blanking Time */
- uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault B Filter Value */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SRC:2; /*!< bit: 0.. 1 Fault B Source */
+ uint32_t :1; /*!< bit: 2 Reserved */
+ uint32_t KEEP:1; /*!< bit: 3 Fault B Keeper */
+ uint32_t QUAL:1; /*!< bit: 4 Fault B Qualification */
+ uint32_t BLANK:2; /*!< bit: 5.. 6 Fault B Blanking Mode */
+ uint32_t RESTART:1; /*!< bit: 7 Fault B Restart */
+ uint32_t HALT:2; /*!< bit: 8.. 9 Fault B Halt Mode */
+ uint32_t CHSEL:2; /*!< bit: 10..11 Fault B Capture Channel */
+ uint32_t CAPTURE:3; /*!< bit: 12..14 Fault B Capture Action */
+ uint32_t :1; /*!< bit: 15 Reserved */
+ uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault B Blanking Time */
+ uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault B Filter Value */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_FCTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -535,23 +535,23 @@ typedef union {
/* -------- TCC_WEXCTRL : (TCC Offset: 0x14) (R/W 32) Waveform Extension Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t OTMX:2; /*!< bit: 0.. 1 Output Matrix */
- uint32_t :6; /*!< bit: 2.. 7 Reserved */
- uint32_t DTIEN0:1; /*!< bit: 8 Dead-time Insertion Generator 0 Enable */
- uint32_t DTIEN1:1; /*!< bit: 9 Dead-time Insertion Generator 1 Enable */
- uint32_t DTIEN2:1; /*!< bit: 10 Dead-time Insertion Generator 2 Enable */
- uint32_t DTIEN3:1; /*!< bit: 11 Dead-time Insertion Generator 3 Enable */
- uint32_t :4; /*!< bit: 12..15 Reserved */
- uint32_t DTLS:8; /*!< bit: 16..23 Dead-time Low Side Outputs Value */
- uint32_t DTHS:8; /*!< bit: 24..31 Dead-time High Side Outputs Value */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :8; /*!< bit: 0.. 7 Reserved */
- uint32_t DTIEN:4; /*!< bit: 8..11 Dead-time Insertion Generator x Enable */
- uint32_t :20; /*!< bit: 12..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t OTMX:2; /*!< bit: 0.. 1 Output Matrix */
+ uint32_t :6; /*!< bit: 2.. 7 Reserved */
+ uint32_t DTIEN0:1; /*!< bit: 8 Dead-time Insertion Generator 0 Enable */
+ uint32_t DTIEN1:1; /*!< bit: 9 Dead-time Insertion Generator 1 Enable */
+ uint32_t DTIEN2:1; /*!< bit: 10 Dead-time Insertion Generator 2 Enable */
+ uint32_t DTIEN3:1; /*!< bit: 11 Dead-time Insertion Generator 3 Enable */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t DTLS:8; /*!< bit: 16..23 Dead-time Low Side Outputs Value */
+ uint32_t DTHS:8; /*!< bit: 24..31 Dead-time High Side Outputs Value */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :8; /*!< bit: 0.. 7 Reserved */
+ uint32_t DTIEN:4; /*!< bit: 8..11 Dead-time Insertion Generator x Enable */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_WEXCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -583,41 +583,41 @@ typedef union {
/* -------- TCC_DRVCTRL : (TCC Offset: 0x18) (R/W 32) Driver Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t NRE0:1; /*!< bit: 0 Non-Recoverable State 0 Output Enable */
- uint32_t NRE1:1; /*!< bit: 1 Non-Recoverable State 1 Output Enable */
- uint32_t NRE2:1; /*!< bit: 2 Non-Recoverable State 2 Output Enable */
- uint32_t NRE3:1; /*!< bit: 3 Non-Recoverable State 3 Output Enable */
- uint32_t NRE4:1; /*!< bit: 4 Non-Recoverable State 4 Output Enable */
- uint32_t NRE5:1; /*!< bit: 5 Non-Recoverable State 5 Output Enable */
- uint32_t NRE6:1; /*!< bit: 6 Non-Recoverable State 6 Output Enable */
- uint32_t NRE7:1; /*!< bit: 7 Non-Recoverable State 7 Output Enable */
- uint32_t NRV0:1; /*!< bit: 8 Non-Recoverable State 0 Output Value */
- uint32_t NRV1:1; /*!< bit: 9 Non-Recoverable State 1 Output Value */
- uint32_t NRV2:1; /*!< bit: 10 Non-Recoverable State 2 Output Value */
- uint32_t NRV3:1; /*!< bit: 11 Non-Recoverable State 3 Output Value */
- uint32_t NRV4:1; /*!< bit: 12 Non-Recoverable State 4 Output Value */
- uint32_t NRV5:1; /*!< bit: 13 Non-Recoverable State 5 Output Value */
- uint32_t NRV6:1; /*!< bit: 14 Non-Recoverable State 6 Output Value */
- uint32_t NRV7:1; /*!< bit: 15 Non-Recoverable State 7 Output Value */
- uint32_t INVEN0:1; /*!< bit: 16 Output Waveform 0 Inversion */
- uint32_t INVEN1:1; /*!< bit: 17 Output Waveform 1 Inversion */
- uint32_t INVEN2:1; /*!< bit: 18 Output Waveform 2 Inversion */
- uint32_t INVEN3:1; /*!< bit: 19 Output Waveform 3 Inversion */
- uint32_t INVEN4:1; /*!< bit: 20 Output Waveform 4 Inversion */
- uint32_t INVEN5:1; /*!< bit: 21 Output Waveform 5 Inversion */
- uint32_t INVEN6:1; /*!< bit: 22 Output Waveform 6 Inversion */
- uint32_t INVEN7:1; /*!< bit: 23 Output Waveform 7 Inversion */
- uint32_t FILTERVAL0:4; /*!< bit: 24..27 Non-Recoverable Fault Input 0 Filter Value */
- uint32_t FILTERVAL1:4; /*!< bit: 28..31 Non-Recoverable Fault Input 1 Filter Value */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t NRE:8; /*!< bit: 0.. 7 Non-Recoverable State x Output Enable */
- uint32_t NRV:8; /*!< bit: 8..15 Non-Recoverable State x Output Value */
- uint32_t INVEN:8; /*!< bit: 16..23 Output Waveform x Inversion */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t NRE0:1; /*!< bit: 0 Non-Recoverable State 0 Output Enable */
+ uint32_t NRE1:1; /*!< bit: 1 Non-Recoverable State 1 Output Enable */
+ uint32_t NRE2:1; /*!< bit: 2 Non-Recoverable State 2 Output Enable */
+ uint32_t NRE3:1; /*!< bit: 3 Non-Recoverable State 3 Output Enable */
+ uint32_t NRE4:1; /*!< bit: 4 Non-Recoverable State 4 Output Enable */
+ uint32_t NRE5:1; /*!< bit: 5 Non-Recoverable State 5 Output Enable */
+ uint32_t NRE6:1; /*!< bit: 6 Non-Recoverable State 6 Output Enable */
+ uint32_t NRE7:1; /*!< bit: 7 Non-Recoverable State 7 Output Enable */
+ uint32_t NRV0:1; /*!< bit: 8 Non-Recoverable State 0 Output Value */
+ uint32_t NRV1:1; /*!< bit: 9 Non-Recoverable State 1 Output Value */
+ uint32_t NRV2:1; /*!< bit: 10 Non-Recoverable State 2 Output Value */
+ uint32_t NRV3:1; /*!< bit: 11 Non-Recoverable State 3 Output Value */
+ uint32_t NRV4:1; /*!< bit: 12 Non-Recoverable State 4 Output Value */
+ uint32_t NRV5:1; /*!< bit: 13 Non-Recoverable State 5 Output Value */
+ uint32_t NRV6:1; /*!< bit: 14 Non-Recoverable State 6 Output Value */
+ uint32_t NRV7:1; /*!< bit: 15 Non-Recoverable State 7 Output Value */
+ uint32_t INVEN0:1; /*!< bit: 16 Output Waveform 0 Inversion */
+ uint32_t INVEN1:1; /*!< bit: 17 Output Waveform 1 Inversion */
+ uint32_t INVEN2:1; /*!< bit: 18 Output Waveform 2 Inversion */
+ uint32_t INVEN3:1; /*!< bit: 19 Output Waveform 3 Inversion */
+ uint32_t INVEN4:1; /*!< bit: 20 Output Waveform 4 Inversion */
+ uint32_t INVEN5:1; /*!< bit: 21 Output Waveform 5 Inversion */
+ uint32_t INVEN6:1; /*!< bit: 22 Output Waveform 6 Inversion */
+ uint32_t INVEN7:1; /*!< bit: 23 Output Waveform 7 Inversion */
+ uint32_t FILTERVAL0:4; /*!< bit: 24..27 Non-Recoverable Fault Input 0 Filter Value */
+ uint32_t FILTERVAL1:4; /*!< bit: 28..31 Non-Recoverable Fault Input 1 Filter Value */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t NRE:8; /*!< bit: 0.. 7 Non-Recoverable State x Output Enable */
+ uint32_t NRV:8; /*!< bit: 8..15 Non-Recoverable State x Output Value */
+ uint32_t INVEN:8; /*!< bit: 16..23 Output Waveform x Inversion */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_DRVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -692,13 +692,13 @@ typedef union {
/* -------- TCC_DBGCTRL : (TCC Offset: 0x1E) (R/W 8) Debug Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DBGRUN:1; /*!< bit: 0 Debug Running Mode */
- uint8_t :1; /*!< bit: 1 Reserved */
- uint8_t FDDBD:1; /*!< bit: 2 Fault Detection on Debug Break Detection */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DBGRUN:1; /*!< bit: 0 Debug Running Mode */
+ uint8_t :1; /*!< bit: 1 Reserved */
+ uint8_t FDDBD:1; /*!< bit: 2 Fault Detection on Debug Break Detection */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} TCC_DBGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -714,39 +714,39 @@ typedef union {
/* -------- TCC_EVCTRL : (TCC Offset: 0x20) (R/W 32) Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t EVACT0:3; /*!< bit: 0.. 2 Timer/counter Input Event0 Action */
- uint32_t EVACT1:3; /*!< bit: 3.. 5 Timer/counter Input Event1 Action */
- uint32_t CNTSEL:2; /*!< bit: 6.. 7 Timer/counter Output Event Mode */
- uint32_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Output Event Enable */
- uint32_t TRGEO:1; /*!< bit: 9 Retrigger Output Event Enable */
- uint32_t CNTEO:1; /*!< bit: 10 Timer/counter Output Event Enable */
- uint32_t :1; /*!< bit: 11 Reserved */
- uint32_t TCINV0:1; /*!< bit: 12 Inverted Event 0 Input Enable */
- uint32_t TCINV1:1; /*!< bit: 13 Inverted Event 1 Input Enable */
- uint32_t TCEI0:1; /*!< bit: 14 Timer/counter Event 0 Input Enable */
- uint32_t TCEI1:1; /*!< bit: 15 Timer/counter Event 1 Input Enable */
- uint32_t MCEI0:1; /*!< bit: 16 Match or Capture Channel 0 Event Input Enable */
- uint32_t MCEI1:1; /*!< bit: 17 Match or Capture Channel 1 Event Input Enable */
- uint32_t MCEI2:1; /*!< bit: 18 Match or Capture Channel 2 Event Input Enable */
- uint32_t MCEI3:1; /*!< bit: 19 Match or Capture Channel 3 Event Input Enable */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t MCEO0:1; /*!< bit: 24 Match or Capture Channel 0 Event Output Enable */
- uint32_t MCEO1:1; /*!< bit: 25 Match or Capture Channel 1 Event Output Enable */
- uint32_t MCEO2:1; /*!< bit: 26 Match or Capture Channel 2 Event Output Enable */
- uint32_t MCEO3:1; /*!< bit: 27 Match or Capture Channel 3 Event Output Enable */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :12; /*!< bit: 0..11 Reserved */
- uint32_t TCINV:2; /*!< bit: 12..13 Inverted Event x Input Enable */
- uint32_t TCEI:2; /*!< bit: 14..15 Timer/counter Event x Input Enable */
- uint32_t MCEI:4; /*!< bit: 16..19 Match or Capture Channel x Event Input Enable */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t MCEO:4; /*!< bit: 24..27 Match or Capture Channel x Event Output Enable */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t EVACT0:3; /*!< bit: 0.. 2 Timer/counter Input Event0 Action */
+ uint32_t EVACT1:3; /*!< bit: 3.. 5 Timer/counter Input Event1 Action */
+ uint32_t CNTSEL:2; /*!< bit: 6.. 7 Timer/counter Output Event Mode */
+ uint32_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Output Event Enable */
+ uint32_t TRGEO:1; /*!< bit: 9 Retrigger Output Event Enable */
+ uint32_t CNTEO:1; /*!< bit: 10 Timer/counter Output Event Enable */
+ uint32_t :1; /*!< bit: 11 Reserved */
+ uint32_t TCINV0:1; /*!< bit: 12 Inverted Event 0 Input Enable */
+ uint32_t TCINV1:1; /*!< bit: 13 Inverted Event 1 Input Enable */
+ uint32_t TCEI0:1; /*!< bit: 14 Timer/counter Event 0 Input Enable */
+ uint32_t TCEI1:1; /*!< bit: 15 Timer/counter Event 1 Input Enable */
+ uint32_t MCEI0:1; /*!< bit: 16 Match or Capture Channel 0 Event Input Enable */
+ uint32_t MCEI1:1; /*!< bit: 17 Match or Capture Channel 1 Event Input Enable */
+ uint32_t MCEI2:1; /*!< bit: 18 Match or Capture Channel 2 Event Input Enable */
+ uint32_t MCEI3:1; /*!< bit: 19 Match or Capture Channel 3 Event Input Enable */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t MCEO0:1; /*!< bit: 24 Match or Capture Channel 0 Event Output Enable */
+ uint32_t MCEO1:1; /*!< bit: 25 Match or Capture Channel 1 Event Output Enable */
+ uint32_t MCEO2:1; /*!< bit: 26 Match or Capture Channel 2 Event Output Enable */
+ uint32_t MCEO3:1; /*!< bit: 27 Match or Capture Channel 3 Event Output Enable */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :12; /*!< bit: 0..11 Reserved */
+ uint32_t TCINV:2; /*!< bit: 12..13 Inverted Event x Input Enable */
+ uint32_t TCEI:2; /*!< bit: 14..15 Timer/counter Event x Input Enable */
+ uint32_t MCEI:4; /*!< bit: 16..19 Match or Capture Channel x Event Input Enable */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t MCEO:4; /*!< bit: 24..27 Match or Capture Channel x Event Output Enable */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -847,29 +847,29 @@ typedef union {
/* -------- TCC_INTENCLR : (TCC Offset: 0x24) (R/W 32) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
- uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */
- uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */
- uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */
- uint32_t :7; /*!< bit: 4..10 Reserved */
- uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */
- uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */
- uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */
- uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */
- uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */
- uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */
- uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */
- uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */
- uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */
- uint32_t :12; /*!< bit: 20..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :16; /*!< bit: 0..15 Reserved */
- uint32_t MC:4; /*!< bit: 16..19 Match or Capture Channel x Interrupt Enable */
- uint32_t :12; /*!< bit: 20..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
+ uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */
+ uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */
+ uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */
+ uint32_t :7; /*!< bit: 4..10 Reserved */
+ uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */
+ uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */
+ uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */
+ uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */
+ uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */
+ uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */
+ uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */
+ uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */
+ uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :16; /*!< bit: 0..15 Reserved */
+ uint32_t MC:4; /*!< bit: 16..19 Match or Capture Channel x Interrupt Enable */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -910,29 +910,29 @@ typedef union {
/* -------- TCC_INTENSET : (TCC Offset: 0x28) (R/W 32) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
- uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */
- uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */
- uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */
- uint32_t :7; /*!< bit: 4..10 Reserved */
- uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */
- uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */
- uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */
- uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */
- uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */
- uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */
- uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */
- uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */
- uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */
- uint32_t :12; /*!< bit: 20..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :16; /*!< bit: 0..15 Reserved */
- uint32_t MC:4; /*!< bit: 16..19 Match or Capture Channel x Interrupt Enable */
- uint32_t :12; /*!< bit: 20..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
+ uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */
+ uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */
+ uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */
+ uint32_t :7; /*!< bit: 4..10 Reserved */
+ uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */
+ uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */
+ uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */
+ uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */
+ uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */
+ uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */
+ uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */
+ uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */
+ uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :16; /*!< bit: 0..15 Reserved */
+ uint32_t MC:4; /*!< bit: 16..19 Match or Capture Channel x Interrupt Enable */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -973,29 +973,29 @@ typedef union {
/* -------- TCC_INTFLAG : (TCC Offset: 0x2C) (R/W 32) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t OVF:1; /*!< bit: 0 Overflow */
- uint32_t TRG:1; /*!< bit: 1 Retrigger */
- uint32_t CNT:1; /*!< bit: 2 Counter */
- uint32_t ERR:1; /*!< bit: 3 Error */
- uint32_t :7; /*!< bit: 4..10 Reserved */
- uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault */
- uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A */
- uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B */
- uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 */
- uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 */
- uint32_t MC0:1; /*!< bit: 16 Match or Capture 0 */
- uint32_t MC1:1; /*!< bit: 17 Match or Capture 1 */
- uint32_t MC2:1; /*!< bit: 18 Match or Capture 2 */
- uint32_t MC3:1; /*!< bit: 19 Match or Capture 3 */
- uint32_t :12; /*!< bit: 20..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :16; /*!< bit: 0..15 Reserved */
- uint32_t MC:4; /*!< bit: 16..19 Match or Capture x */
- uint32_t :12; /*!< bit: 20..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t OVF:1; /*!< bit: 0 Overflow */
+ uint32_t TRG:1; /*!< bit: 1 Retrigger */
+ uint32_t CNT:1; /*!< bit: 2 Counter */
+ uint32_t ERR:1; /*!< bit: 3 Error */
+ uint32_t :7; /*!< bit: 4..10 Reserved */
+ uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault */
+ uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A */
+ uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B */
+ uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 */
+ uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 */
+ uint32_t MC0:1; /*!< bit: 16 Match or Capture 0 */
+ uint32_t MC1:1; /*!< bit: 17 Match or Capture 1 */
+ uint32_t MC2:1; /*!< bit: 18 Match or Capture 2 */
+ uint32_t MC3:1; /*!< bit: 19 Match or Capture 3 */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :16; /*!< bit: 0..15 Reserved */
+ uint32_t MC:4; /*!< bit: 16..19 Match or Capture x */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1036,42 +1036,42 @@ typedef union {
/* -------- TCC_STATUS : (TCC Offset: 0x30) (R/W 32) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t STOP:1; /*!< bit: 0 Stop */
- uint32_t IDX:1; /*!< bit: 1 Ramp */
- uint32_t :1; /*!< bit: 2 Reserved */
- uint32_t DFS:1; /*!< bit: 3 Non-Recoverable Debug Fault State */
- uint32_t SLAVE:1; /*!< bit: 4 Slave */
- uint32_t PATTBV:1; /*!< bit: 5 Pattern Buffer Valid */
- uint32_t WAVEBV:1; /*!< bit: 6 Wave Buffer Valid */
- uint32_t PERBV:1; /*!< bit: 7 Period Buffer Valid */
- uint32_t FAULTAIN:1; /*!< bit: 8 Recoverable Fault A Input */
- uint32_t FAULTBIN:1; /*!< bit: 9 Recoverable Fault B Input */
- uint32_t FAULT0IN:1; /*!< bit: 10 Non-Recoverable Fault0 Input */
- uint32_t FAULT1IN:1; /*!< bit: 11 Non-Recoverable Fault1 Input */
- uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A State */
- uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B State */
- uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 State */
- uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 State */
- uint32_t CCBV0:1; /*!< bit: 16 Compare Channel 0 Buffer Valid */
- uint32_t CCBV1:1; /*!< bit: 17 Compare Channel 1 Buffer Valid */
- uint32_t CCBV2:1; /*!< bit: 18 Compare Channel 2 Buffer Valid */
- uint32_t CCBV3:1; /*!< bit: 19 Compare Channel 3 Buffer Valid */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t CMP0:1; /*!< bit: 24 Compare Channel 0 Value */
- uint32_t CMP1:1; /*!< bit: 25 Compare Channel 1 Value */
- uint32_t CMP2:1; /*!< bit: 26 Compare Channel 2 Value */
- uint32_t CMP3:1; /*!< bit: 27 Compare Channel 3 Value */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :16; /*!< bit: 0..15 Reserved */
- uint32_t CCBV:4; /*!< bit: 16..19 Compare Channel x Buffer Valid */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t CMP:4; /*!< bit: 24..27 Compare Channel x Value */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t STOP:1; /*!< bit: 0 Stop */
+ uint32_t IDX:1; /*!< bit: 1 Ramp */
+ uint32_t :1; /*!< bit: 2 Reserved */
+ uint32_t DFS:1; /*!< bit: 3 Non-Recoverable Debug Fault State */
+ uint32_t SLAVE:1; /*!< bit: 4 Slave */
+ uint32_t PATTBV:1; /*!< bit: 5 Pattern Buffer Valid */
+ uint32_t WAVEBV:1; /*!< bit: 6 Wave Buffer Valid */
+ uint32_t PERBV:1; /*!< bit: 7 Period Buffer Valid */
+ uint32_t FAULTAIN:1; /*!< bit: 8 Recoverable Fault A Input */
+ uint32_t FAULTBIN:1; /*!< bit: 9 Recoverable Fault B Input */
+ uint32_t FAULT0IN:1; /*!< bit: 10 Non-Recoverable Fault0 Input */
+ uint32_t FAULT1IN:1; /*!< bit: 11 Non-Recoverable Fault1 Input */
+ uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A State */
+ uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B State */
+ uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 State */
+ uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 State */
+ uint32_t CCBV0:1; /*!< bit: 16 Compare Channel 0 Buffer Valid */
+ uint32_t CCBV1:1; /*!< bit: 17 Compare Channel 1 Buffer Valid */
+ uint32_t CCBV2:1; /*!< bit: 18 Compare Channel 2 Buffer Valid */
+ uint32_t CCBV3:1; /*!< bit: 19 Compare Channel 3 Buffer Valid */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t CMP0:1; /*!< bit: 24 Compare Channel 0 Value */
+ uint32_t CMP1:1; /*!< bit: 25 Compare Channel 1 Value */
+ uint32_t CMP2:1; /*!< bit: 26 Compare Channel 2 Value */
+ uint32_t CMP3:1; /*!< bit: 27 Compare Channel 3 Value */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :16; /*!< bit: 0..15 Reserved */
+ uint32_t CCBV:4; /*!< bit: 16..19 Compare Channel x Buffer Valid */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t CMP:4; /*!< bit: 24..27 Compare Channel x Value */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1135,26 +1135,26 @@ typedef union {
/* -------- TCC_COUNT : (TCC Offset: 0x34) (R/W 32) Count -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct { // DITH4 mode
- uint32_t :4; /*!< bit: 0.. 3 Reserved */
- uint32_t COUNT:20; /*!< bit: 4..23 Counter Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH4; /*!< Structure used for DITH4 */
- struct { // DITH5 mode
- uint32_t :5; /*!< bit: 0.. 4 Reserved */
- uint32_t COUNT:19; /*!< bit: 5..23 Counter Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH5; /*!< Structure used for DITH5 */
- struct { // DITH6 mode
- uint32_t :6; /*!< bit: 0.. 5 Reserved */
- uint32_t COUNT:18; /*!< bit: 6..23 Counter Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH6; /*!< Structure used for DITH6 */
- struct {
- uint32_t COUNT:24; /*!< bit: 0..23 Counter Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct { // DITH4 mode
+ uint32_t :4; /*!< bit: 0.. 3 Reserved */
+ uint32_t COUNT:20; /*!< bit: 4..23 Counter Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH4; /*!< Structure used for DITH4 */
+ struct { // DITH5 mode
+ uint32_t :5; /*!< bit: 0.. 4 Reserved */
+ uint32_t COUNT:19; /*!< bit: 5..23 Counter Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH5; /*!< Structure used for DITH5 */
+ struct { // DITH6 mode
+ uint32_t :6; /*!< bit: 0.. 5 Reserved */
+ uint32_t COUNT:18; /*!< bit: 6..23 Counter Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH6; /*!< Structure used for DITH6 */
+ struct {
+ uint32_t COUNT:24; /*!< bit: 0..23 Counter Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_COUNT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1187,29 +1187,29 @@ typedef union {
/* -------- TCC_PATT : (TCC Offset: 0x38) (R/W 16) Pattern -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t PGE0:1; /*!< bit: 0 Pattern Generator 0 Output Enable */
- uint16_t PGE1:1; /*!< bit: 1 Pattern Generator 1 Output Enable */
- uint16_t PGE2:1; /*!< bit: 2 Pattern Generator 2 Output Enable */
- uint16_t PGE3:1; /*!< bit: 3 Pattern Generator 3 Output Enable */
- uint16_t PGE4:1; /*!< bit: 4 Pattern Generator 4 Output Enable */
- uint16_t PGE5:1; /*!< bit: 5 Pattern Generator 5 Output Enable */
- uint16_t PGE6:1; /*!< bit: 6 Pattern Generator 6 Output Enable */
- uint16_t PGE7:1; /*!< bit: 7 Pattern Generator 7 Output Enable */
- uint16_t PGV0:1; /*!< bit: 8 Pattern Generator 0 Output Value */
- uint16_t PGV1:1; /*!< bit: 9 Pattern Generator 1 Output Value */
- uint16_t PGV2:1; /*!< bit: 10 Pattern Generator 2 Output Value */
- uint16_t PGV3:1; /*!< bit: 11 Pattern Generator 3 Output Value */
- uint16_t PGV4:1; /*!< bit: 12 Pattern Generator 4 Output Value */
- uint16_t PGV5:1; /*!< bit: 13 Pattern Generator 5 Output Value */
- uint16_t PGV6:1; /*!< bit: 14 Pattern Generator 6 Output Value */
- uint16_t PGV7:1; /*!< bit: 15 Pattern Generator 7 Output Value */
- } bit; /*!< Structure used for bit access */
- struct {
- uint16_t PGE:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable */
- uint16_t PGV:8; /*!< bit: 8..15 Pattern Generator x Output Value */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t PGE0:1; /*!< bit: 0 Pattern Generator 0 Output Enable */
+ uint16_t PGE1:1; /*!< bit: 1 Pattern Generator 1 Output Enable */
+ uint16_t PGE2:1; /*!< bit: 2 Pattern Generator 2 Output Enable */
+ uint16_t PGE3:1; /*!< bit: 3 Pattern Generator 3 Output Enable */
+ uint16_t PGE4:1; /*!< bit: 4 Pattern Generator 4 Output Enable */
+ uint16_t PGE5:1; /*!< bit: 5 Pattern Generator 5 Output Enable */
+ uint16_t PGE6:1; /*!< bit: 6 Pattern Generator 6 Output Enable */
+ uint16_t PGE7:1; /*!< bit: 7 Pattern Generator 7 Output Enable */
+ uint16_t PGV0:1; /*!< bit: 8 Pattern Generator 0 Output Value */
+ uint16_t PGV1:1; /*!< bit: 9 Pattern Generator 1 Output Value */
+ uint16_t PGV2:1; /*!< bit: 10 Pattern Generator 2 Output Value */
+ uint16_t PGV3:1; /*!< bit: 11 Pattern Generator 3 Output Value */
+ uint16_t PGV4:1; /*!< bit: 12 Pattern Generator 4 Output Value */
+ uint16_t PGV5:1; /*!< bit: 13 Pattern Generator 5 Output Value */
+ uint16_t PGV6:1; /*!< bit: 14 Pattern Generator 6 Output Value */
+ uint16_t PGV7:1; /*!< bit: 15 Pattern Generator 7 Output Value */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t PGE:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable */
+ uint16_t PGV:8; /*!< bit: 8..15 Pattern Generator x Output Value */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
} TCC_PATT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1259,38 +1259,38 @@ typedef union {
/* -------- TCC_WAVE : (TCC Offset: 0x3C) (R/W 32) Waveform Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t WAVEGEN:3; /*!< bit: 0.. 2 Waveform Generation */
- uint32_t :1; /*!< bit: 3 Reserved */
- uint32_t RAMP:2; /*!< bit: 4.. 5 Ramp Mode */
- uint32_t :1; /*!< bit: 6 Reserved */
- uint32_t CIPEREN:1; /*!< bit: 7 Circular period Enable */
- uint32_t CICCEN0:1; /*!< bit: 8 Circular Channel 0 Enable */
- uint32_t CICCEN1:1; /*!< bit: 9 Circular Channel 1 Enable */
- uint32_t CICCEN2:1; /*!< bit: 10 Circular Channel 2 Enable */
- uint32_t CICCEN3:1; /*!< bit: 11 Circular Channel 3 Enable */
- uint32_t :4; /*!< bit: 12..15 Reserved */
- uint32_t POL0:1; /*!< bit: 16 Channel 0 Polarity */
- uint32_t POL1:1; /*!< bit: 17 Channel 1 Polarity */
- uint32_t POL2:1; /*!< bit: 18 Channel 2 Polarity */
- uint32_t POL3:1; /*!< bit: 19 Channel 3 Polarity */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t SWAP0:1; /*!< bit: 24 Swap DTI Output Pair 0 */
- uint32_t SWAP1:1; /*!< bit: 25 Swap DTI Output Pair 1 */
- uint32_t SWAP2:1; /*!< bit: 26 Swap DTI Output Pair 2 */
- uint32_t SWAP3:1; /*!< bit: 27 Swap DTI Output Pair 3 */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :8; /*!< bit: 0.. 7 Reserved */
- uint32_t CICCEN:4; /*!< bit: 8..11 Circular Channel x Enable */
- uint32_t :4; /*!< bit: 12..15 Reserved */
- uint32_t POL:4; /*!< bit: 16..19 Channel x Polarity */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t SWAP:4; /*!< bit: 24..27 Swap DTI Output Pair x */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t WAVEGEN:3; /*!< bit: 0.. 2 Waveform Generation */
+ uint32_t :1; /*!< bit: 3 Reserved */
+ uint32_t RAMP:2; /*!< bit: 4.. 5 Ramp Mode */
+ uint32_t :1; /*!< bit: 6 Reserved */
+ uint32_t CIPEREN:1; /*!< bit: 7 Circular period Enable */
+ uint32_t CICCEN0:1; /*!< bit: 8 Circular Channel 0 Enable */
+ uint32_t CICCEN1:1; /*!< bit: 9 Circular Channel 1 Enable */
+ uint32_t CICCEN2:1; /*!< bit: 10 Circular Channel 2 Enable */
+ uint32_t CICCEN3:1; /*!< bit: 11 Circular Channel 3 Enable */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t POL0:1; /*!< bit: 16 Channel 0 Polarity */
+ uint32_t POL1:1; /*!< bit: 17 Channel 1 Polarity */
+ uint32_t POL2:1; /*!< bit: 18 Channel 2 Polarity */
+ uint32_t POL3:1; /*!< bit: 19 Channel 3 Polarity */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t SWAP0:1; /*!< bit: 24 Swap DTI Output Pair 0 */
+ uint32_t SWAP1:1; /*!< bit: 25 Swap DTI Output Pair 1 */
+ uint32_t SWAP2:1; /*!< bit: 26 Swap DTI Output Pair 2 */
+ uint32_t SWAP3:1; /*!< bit: 27 Swap DTI Output Pair 3 */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :8; /*!< bit: 0.. 7 Reserved */
+ uint32_t CICCEN:4; /*!< bit: 8..11 Circular Channel x Enable */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t POL:4; /*!< bit: 16..19 Channel x Polarity */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t SWAP:4; /*!< bit: 24..27 Swap DTI Output Pair x */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_WAVE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1363,26 +1363,26 @@ typedef union {
/* -------- TCC_PER : (TCC Offset: 0x40) (R/W 32) Period -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct { // DITH4 mode
- uint32_t DITHERCY:4; /*!< bit: 0.. 3 Dithering Cycle Number */
- uint32_t PER:20; /*!< bit: 4..23 Period Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH4; /*!< Structure used for DITH4 */
- struct { // DITH5 mode
- uint32_t DITHERCY:5; /*!< bit: 0.. 4 Dithering Cycle Number */
- uint32_t PER:19; /*!< bit: 5..23 Period Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH5; /*!< Structure used for DITH5 */
- struct { // DITH6 mode
- uint32_t DITHERCY:6; /*!< bit: 0.. 5 Dithering Cycle Number */
- uint32_t PER:18; /*!< bit: 6..23 Period Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH6; /*!< Structure used for DITH6 */
- struct {
- uint32_t PER:24; /*!< bit: 0..23 Period Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct { // DITH4 mode
+ uint32_t DITHERCY:4; /*!< bit: 0.. 3 Dithering Cycle Number */
+ uint32_t PER:20; /*!< bit: 4..23 Period Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH4; /*!< Structure used for DITH4 */
+ struct { // DITH5 mode
+ uint32_t DITHERCY:5; /*!< bit: 0.. 4 Dithering Cycle Number */
+ uint32_t PER:19; /*!< bit: 5..23 Period Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH5; /*!< Structure used for DITH5 */
+ struct { // DITH6 mode
+ uint32_t DITHERCY:6; /*!< bit: 0.. 5 Dithering Cycle Number */
+ uint32_t PER:18; /*!< bit: 6..23 Period Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH6; /*!< Structure used for DITH6 */
+ struct {
+ uint32_t PER:24; /*!< bit: 0..23 Period Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_PER_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1424,26 +1424,26 @@ typedef union {
/* -------- TCC_CC : (TCC Offset: 0x44) (R/W 32) Compare and Capture -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct { // DITH4 mode
- uint32_t DITHERCY:4; /*!< bit: 0.. 3 Dithering Cycle Number */
- uint32_t CC:20; /*!< bit: 4..23 Channel Compare/Capture Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH4; /*!< Structure used for DITH4 */
- struct { // DITH5 mode
- uint32_t DITHERCY:5; /*!< bit: 0.. 4 Dithering Cycle Number */
- uint32_t CC:19; /*!< bit: 5..23 Channel Compare/Capture Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH5; /*!< Structure used for DITH5 */
- struct { // DITH6 mode
- uint32_t DITHERCY:6; /*!< bit: 0.. 5 Dithering Cycle Number */
- uint32_t CC:18; /*!< bit: 6..23 Channel Compare/Capture Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH6; /*!< Structure used for DITH6 */
- struct {
- uint32_t CC:24; /*!< bit: 0..23 Channel Compare/Capture Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct { // DITH4 mode
+ uint32_t DITHERCY:4; /*!< bit: 0.. 3 Dithering Cycle Number */
+ uint32_t CC:20; /*!< bit: 4..23 Channel Compare/Capture Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH4; /*!< Structure used for DITH4 */
+ struct { // DITH5 mode
+ uint32_t DITHERCY:5; /*!< bit: 0.. 4 Dithering Cycle Number */
+ uint32_t CC:19; /*!< bit: 5..23 Channel Compare/Capture Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH5; /*!< Structure used for DITH5 */
+ struct { // DITH6 mode
+ uint32_t DITHERCY:6; /*!< bit: 0.. 5 Dithering Cycle Number */
+ uint32_t CC:18; /*!< bit: 6..23 Channel Compare/Capture Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH6; /*!< Structure used for DITH6 */
+ struct {
+ uint32_t CC:24; /*!< bit: 0..23 Channel Compare/Capture Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_CC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1485,29 +1485,29 @@ typedef union {
/* -------- TCC_PATTB : (TCC Offset: 0x64) (R/W 16) Pattern Buffer -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t PGEB0:1; /*!< bit: 0 Pattern Generator 0 Output Enable Buffer */
- uint16_t PGEB1:1; /*!< bit: 1 Pattern Generator 1 Output Enable Buffer */
- uint16_t PGEB2:1; /*!< bit: 2 Pattern Generator 2 Output Enable Buffer */
- uint16_t PGEB3:1; /*!< bit: 3 Pattern Generator 3 Output Enable Buffer */
- uint16_t PGEB4:1; /*!< bit: 4 Pattern Generator 4 Output Enable Buffer */
- uint16_t PGEB5:1; /*!< bit: 5 Pattern Generator 5 Output Enable Buffer */
- uint16_t PGEB6:1; /*!< bit: 6 Pattern Generator 6 Output Enable Buffer */
- uint16_t PGEB7:1; /*!< bit: 7 Pattern Generator 7 Output Enable Buffer */
- uint16_t PGVB0:1; /*!< bit: 8 Pattern Generator 0 Output Enable */
- uint16_t PGVB1:1; /*!< bit: 9 Pattern Generator 1 Output Enable */
- uint16_t PGVB2:1; /*!< bit: 10 Pattern Generator 2 Output Enable */
- uint16_t PGVB3:1; /*!< bit: 11 Pattern Generator 3 Output Enable */
- uint16_t PGVB4:1; /*!< bit: 12 Pattern Generator 4 Output Enable */
- uint16_t PGVB5:1; /*!< bit: 13 Pattern Generator 5 Output Enable */
- uint16_t PGVB6:1; /*!< bit: 14 Pattern Generator 6 Output Enable */
- uint16_t PGVB7:1; /*!< bit: 15 Pattern Generator 7 Output Enable */
- } bit; /*!< Structure used for bit access */
- struct {
- uint16_t PGEB:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable Buffer */
- uint16_t PGVB:8; /*!< bit: 8..15 Pattern Generator x Output Enable */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t PGEB0:1; /*!< bit: 0 Pattern Generator 0 Output Enable Buffer */
+ uint16_t PGEB1:1; /*!< bit: 1 Pattern Generator 1 Output Enable Buffer */
+ uint16_t PGEB2:1; /*!< bit: 2 Pattern Generator 2 Output Enable Buffer */
+ uint16_t PGEB3:1; /*!< bit: 3 Pattern Generator 3 Output Enable Buffer */
+ uint16_t PGEB4:1; /*!< bit: 4 Pattern Generator 4 Output Enable Buffer */
+ uint16_t PGEB5:1; /*!< bit: 5 Pattern Generator 5 Output Enable Buffer */
+ uint16_t PGEB6:1; /*!< bit: 6 Pattern Generator 6 Output Enable Buffer */
+ uint16_t PGEB7:1; /*!< bit: 7 Pattern Generator 7 Output Enable Buffer */
+ uint16_t PGVB0:1; /*!< bit: 8 Pattern Generator 0 Output Enable */
+ uint16_t PGVB1:1; /*!< bit: 9 Pattern Generator 1 Output Enable */
+ uint16_t PGVB2:1; /*!< bit: 10 Pattern Generator 2 Output Enable */
+ uint16_t PGVB3:1; /*!< bit: 11 Pattern Generator 3 Output Enable */
+ uint16_t PGVB4:1; /*!< bit: 12 Pattern Generator 4 Output Enable */
+ uint16_t PGVB5:1; /*!< bit: 13 Pattern Generator 5 Output Enable */
+ uint16_t PGVB6:1; /*!< bit: 14 Pattern Generator 6 Output Enable */
+ uint16_t PGVB7:1; /*!< bit: 15 Pattern Generator 7 Output Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t PGEB:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable Buffer */
+ uint16_t PGVB:8; /*!< bit: 8..15 Pattern Generator x Output Enable */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
} TCC_PATTB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1557,38 +1557,38 @@ typedef union {
/* -------- TCC_WAVEB : (TCC Offset: 0x68) (R/W 32) Waveform Control Buffer -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t WAVEGENB:3; /*!< bit: 0.. 2 Waveform Generation Buffer */
- uint32_t :1; /*!< bit: 3 Reserved */
- uint32_t RAMPB:2; /*!< bit: 4.. 5 Ramp Mode Buffer */
- uint32_t :1; /*!< bit: 6 Reserved */
- uint32_t CIPERENB:1; /*!< bit: 7 Circular Period Enable Buffer */
- uint32_t CICCENB0:1; /*!< bit: 8 Circular Channel 0 Enable Buffer */
- uint32_t CICCENB1:1; /*!< bit: 9 Circular Channel 1 Enable Buffer */
- uint32_t CICCENB2:1; /*!< bit: 10 Circular Channel 2 Enable Buffer */
- uint32_t CICCENB3:1; /*!< bit: 11 Circular Channel 3 Enable Buffer */
- uint32_t :4; /*!< bit: 12..15 Reserved */
- uint32_t POLB0:1; /*!< bit: 16 Channel 0 Polarity Buffer */
- uint32_t POLB1:1; /*!< bit: 17 Channel 1 Polarity Buffer */
- uint32_t POLB2:1; /*!< bit: 18 Channel 2 Polarity Buffer */
- uint32_t POLB3:1; /*!< bit: 19 Channel 3 Polarity Buffer */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t SWAPB0:1; /*!< bit: 24 Swap DTI Output Pair 0 Buffer */
- uint32_t SWAPB1:1; /*!< bit: 25 Swap DTI Output Pair 1 Buffer */
- uint32_t SWAPB2:1; /*!< bit: 26 Swap DTI Output Pair 2 Buffer */
- uint32_t SWAPB3:1; /*!< bit: 27 Swap DTI Output Pair 3 Buffer */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :8; /*!< bit: 0.. 7 Reserved */
- uint32_t CICCENB:4; /*!< bit: 8..11 Circular Channel x Enable Buffer */
- uint32_t :4; /*!< bit: 12..15 Reserved */
- uint32_t POLB:4; /*!< bit: 16..19 Channel x Polarity Buffer */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t SWAPB:4; /*!< bit: 24..27 Swap DTI Output Pair x Buffer */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t WAVEGENB:3; /*!< bit: 0.. 2 Waveform Generation Buffer */
+ uint32_t :1; /*!< bit: 3 Reserved */
+ uint32_t RAMPB:2; /*!< bit: 4.. 5 Ramp Mode Buffer */
+ uint32_t :1; /*!< bit: 6 Reserved */
+ uint32_t CIPERENB:1; /*!< bit: 7 Circular Period Enable Buffer */
+ uint32_t CICCENB0:1; /*!< bit: 8 Circular Channel 0 Enable Buffer */
+ uint32_t CICCENB1:1; /*!< bit: 9 Circular Channel 1 Enable Buffer */
+ uint32_t CICCENB2:1; /*!< bit: 10 Circular Channel 2 Enable Buffer */
+ uint32_t CICCENB3:1; /*!< bit: 11 Circular Channel 3 Enable Buffer */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t POLB0:1; /*!< bit: 16 Channel 0 Polarity Buffer */
+ uint32_t POLB1:1; /*!< bit: 17 Channel 1 Polarity Buffer */
+ uint32_t POLB2:1; /*!< bit: 18 Channel 2 Polarity Buffer */
+ uint32_t POLB3:1; /*!< bit: 19 Channel 3 Polarity Buffer */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t SWAPB0:1; /*!< bit: 24 Swap DTI Output Pair 0 Buffer */
+ uint32_t SWAPB1:1; /*!< bit: 25 Swap DTI Output Pair 1 Buffer */
+ uint32_t SWAPB2:1; /*!< bit: 26 Swap DTI Output Pair 2 Buffer */
+ uint32_t SWAPB3:1; /*!< bit: 27 Swap DTI Output Pair 3 Buffer */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :8; /*!< bit: 0.. 7 Reserved */
+ uint32_t CICCENB:4; /*!< bit: 8..11 Circular Channel x Enable Buffer */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t POLB:4; /*!< bit: 16..19 Channel x Polarity Buffer */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t SWAPB:4; /*!< bit: 24..27 Swap DTI Output Pair x Buffer */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_WAVEB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1661,26 +1661,26 @@ typedef union {
/* -------- TCC_PERB : (TCC Offset: 0x6C) (R/W 32) Period Buffer -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct { // DITH4 mode
- uint32_t DITHERCYB:4; /*!< bit: 0.. 3 Dithering Buffer Cycle Number */
- uint32_t PERB:20; /*!< bit: 4..23 Period Buffer Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH4; /*!< Structure used for DITH4 */
- struct { // DITH5 mode
- uint32_t DITHERCYB:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */
- uint32_t PERB:19; /*!< bit: 5..23 Period Buffer Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH5; /*!< Structure used for DITH5 */
- struct { // DITH6 mode
- uint32_t DITHERCYB:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */
- uint32_t PERB:18; /*!< bit: 6..23 Period Buffer Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH6; /*!< Structure used for DITH6 */
- struct {
- uint32_t PERB:24; /*!< bit: 0..23 Period Buffer Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct { // DITH4 mode
+ uint32_t DITHERCYB:4; /*!< bit: 0.. 3 Dithering Buffer Cycle Number */
+ uint32_t PERB:20; /*!< bit: 4..23 Period Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH4; /*!< Structure used for DITH4 */
+ struct { // DITH5 mode
+ uint32_t DITHERCYB:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */
+ uint32_t PERB:19; /*!< bit: 5..23 Period Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH5; /*!< Structure used for DITH5 */
+ struct { // DITH6 mode
+ uint32_t DITHERCYB:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */
+ uint32_t PERB:18; /*!< bit: 6..23 Period Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH6; /*!< Structure used for DITH6 */
+ struct {
+ uint32_t PERB:24; /*!< bit: 0..23 Period Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_PERB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1722,26 +1722,26 @@ typedef union {
/* -------- TCC_CCB : (TCC Offset: 0x70) (R/W 32) Compare and Capture Buffer -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct { // DITH4 mode
- uint32_t DITHERCYB:4; /*!< bit: 0.. 3 Dithering Buffer Cycle Number */
- uint32_t CCB:20; /*!< bit: 4..23 Channel Compare/Capture Buffer Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH4; /*!< Structure used for DITH4 */
- struct { // DITH5 mode
- uint32_t DITHERCYB:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */
- uint32_t CCB:19; /*!< bit: 5..23 Channel Compare/Capture Buffer Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH5; /*!< Structure used for DITH5 */
- struct { // DITH6 mode
- uint32_t DITHERCYB:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */
- uint32_t CCB:18; /*!< bit: 6..23 Channel Compare/Capture Buffer Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH6; /*!< Structure used for DITH6 */
- struct {
- uint32_t CCB:24; /*!< bit: 0..23 Channel Compare/Capture Buffer Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct { // DITH4 mode
+ uint32_t DITHERCYB:4; /*!< bit: 0.. 3 Dithering Buffer Cycle Number */
+ uint32_t CCB:20; /*!< bit: 4..23 Channel Compare/Capture Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH4; /*!< Structure used for DITH4 */
+ struct { // DITH5 mode
+ uint32_t DITHERCYB:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */
+ uint32_t CCB:19; /*!< bit: 5..23 Channel Compare/Capture Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH5; /*!< Structure used for DITH5 */
+ struct { // DITH6 mode
+ uint32_t DITHERCYB:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */
+ uint32_t CCB:18; /*!< bit: 6..23 Channel Compare/Capture Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH6; /*!< Structure used for DITH6 */
+ struct {
+ uint32_t CCB:24; /*!< bit: 0..23 Channel Compare/Capture Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_CCB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1783,35 +1783,35 @@ typedef union {
/** \brief TCC hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO TCC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */
- __IO TCC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
- __IO TCC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
- RoReg8 Reserved1[0x2];
- __I TCC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x08 (R/ 32) Synchronization Busy */
- __IO TCC_FCTRLA_Type FCTRLA; /**< \brief Offset: 0x0C (R/W 32) Recoverable Fault A Configuration */
- __IO TCC_FCTRLB_Type FCTRLB; /**< \brief Offset: 0x10 (R/W 32) Recoverable Fault B Configuration */
- __IO TCC_WEXCTRL_Type WEXCTRL; /**< \brief Offset: 0x14 (R/W 32) Waveform Extension Configuration */
- __IO TCC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x18 (R/W 32) Driver Control */
- RoReg8 Reserved2[0x2];
- __IO TCC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x1E (R/W 8) Debug Control */
- RoReg8 Reserved3[0x1];
- __IO TCC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x20 (R/W 32) Event Control */
- __IO TCC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x24 (R/W 32) Interrupt Enable Clear */
- __IO TCC_INTENSET_Type INTENSET; /**< \brief Offset: 0x28 (R/W 32) Interrupt Enable Set */
- __IO TCC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x2C (R/W 32) Interrupt Flag Status and Clear */
- __IO TCC_STATUS_Type STATUS; /**< \brief Offset: 0x30 (R/W 32) Status */
- __IO TCC_COUNT_Type COUNT; /**< \brief Offset: 0x34 (R/W 32) Count */
- __IO TCC_PATT_Type PATT; /**< \brief Offset: 0x38 (R/W 16) Pattern */
- RoReg8 Reserved4[0x2];
- __IO TCC_WAVE_Type WAVE; /**< \brief Offset: 0x3C (R/W 32) Waveform Control */
- __IO TCC_PER_Type PER; /**< \brief Offset: 0x40 (R/W 32) Period */
- __IO TCC_CC_Type CC[4]; /**< \brief Offset: 0x44 (R/W 32) Compare and Capture */
- RoReg8 Reserved5[0x10];
- __IO TCC_PATTB_Type PATTB; /**< \brief Offset: 0x64 (R/W 16) Pattern Buffer */
- RoReg8 Reserved6[0x2];
- __IO TCC_WAVEB_Type WAVEB; /**< \brief Offset: 0x68 (R/W 32) Waveform Control Buffer */
- __IO TCC_PERB_Type PERB; /**< \brief Offset: 0x6C (R/W 32) Period Buffer */
- __IO TCC_CCB_Type CCB[4]; /**< \brief Offset: 0x70 (R/W 32) Compare and Capture Buffer */
+ __IO TCC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */
+ __IO TCC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
+ __IO TCC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
+ RoReg8 Reserved1[0x2];
+ __I TCC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x08 (R/ 32) Synchronization Busy */
+ __IO TCC_FCTRLA_Type FCTRLA; /**< \brief Offset: 0x0C (R/W 32) Recoverable Fault A Configuration */
+ __IO TCC_FCTRLB_Type FCTRLB; /**< \brief Offset: 0x10 (R/W 32) Recoverable Fault B Configuration */
+ __IO TCC_WEXCTRL_Type WEXCTRL; /**< \brief Offset: 0x14 (R/W 32) Waveform Extension Configuration */
+ __IO TCC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x18 (R/W 32) Driver Control */
+ RoReg8 Reserved2[0x2];
+ __IO TCC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x1E (R/W 8) Debug Control */
+ RoReg8 Reserved3[0x1];
+ __IO TCC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x20 (R/W 32) Event Control */
+ __IO TCC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x24 (R/W 32) Interrupt Enable Clear */
+ __IO TCC_INTENSET_Type INTENSET; /**< \brief Offset: 0x28 (R/W 32) Interrupt Enable Set */
+ __IO TCC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x2C (R/W 32) Interrupt Flag Status and Clear */
+ __IO TCC_STATUS_Type STATUS; /**< \brief Offset: 0x30 (R/W 32) Status */
+ __IO TCC_COUNT_Type COUNT; /**< \brief Offset: 0x34 (R/W 32) Count */
+ __IO TCC_PATT_Type PATT; /**< \brief Offset: 0x38 (R/W 16) Pattern */
+ RoReg8 Reserved4[0x2];
+ __IO TCC_WAVE_Type WAVE; /**< \brief Offset: 0x3C (R/W 32) Waveform Control */
+ __IO TCC_PER_Type PER; /**< \brief Offset: 0x40 (R/W 32) Period */
+ __IO TCC_CC_Type CC[4]; /**< \brief Offset: 0x44 (R/W 32) Compare and Capture */
+ RoReg8 Reserved5[0x10];
+ __IO TCC_PATTB_Type PATTB; /**< \brief Offset: 0x64 (R/W 16) Pattern Buffer */
+ RoReg8 Reserved6[0x2];
+ __IO TCC_WAVEB_Type WAVEB; /**< \brief Offset: 0x68 (R/W 32) Waveform Control Buffer */
+ __IO TCC_PERB_Type PERB; /**< \brief Offset: 0x6C (R/W 32) Period Buffer */
+ __IO TCC_CCB_Type CCB[4]; /**< \brief Offset: 0x70 (R/W 32) Compare and Capture Buffer */
} Tcc;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_tcc_lighting.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_tcc_lighting.h
index 41ae22acf44..9c1f64a7bd9 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_tcc_lighting.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_tcc_lighting.h
@@ -56,29 +56,29 @@
/* -------- TCC_CTRLA : (TCC Offset: 0x00) (R/W 32) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Software Reset */
- uint32_t ENABLE:1; /*!< bit: 1 Enable */
- uint32_t :3; /*!< bit: 2.. 4 Reserved */
- uint32_t RESOLUTION:2; /*!< bit: 5.. 6 Enhanced Resolution */
- uint32_t :1; /*!< bit: 7 Reserved */
- uint32_t PRESCALER:3; /*!< bit: 8..10 Prescaler */
- uint32_t RUNSTDBY:1; /*!< bit: 11 Run in Standby */
- uint32_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization Selection */
- uint32_t ALOCK:1; /*!< bit: 14 Auto Lock */
- uint32_t :9; /*!< bit: 15..23 Reserved */
- uint32_t CPTEN0:1; /*!< bit: 24 Capture Channel 0 Enable */
- uint32_t CPTEN1:1; /*!< bit: 25 Capture Channel 1 Enable */
- uint32_t CPTEN2:1; /*!< bit: 26 Capture Channel 2 Enable */
- uint32_t CPTEN3:1; /*!< bit: 27 Capture Channel 3 Enable */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :24; /*!< bit: 0..23 Reserved */
- uint32_t CPTEN:4; /*!< bit: 24..27 Capture Channel x Enable */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */
+ uint32_t :3; /*!< bit: 2.. 4 Reserved */
+ uint32_t RESOLUTION:2; /*!< bit: 5.. 6 Enhanced Resolution */
+ uint32_t :1; /*!< bit: 7 Reserved */
+ uint32_t PRESCALER:3; /*!< bit: 8..10 Prescaler */
+ uint32_t RUNSTDBY:1; /*!< bit: 11 Run in Standby */
+ uint32_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization Selection */
+ uint32_t ALOCK:1; /*!< bit: 14 Auto Lock */
+ uint32_t :9; /*!< bit: 15..23 Reserved */
+ uint32_t CPTEN0:1; /*!< bit: 24 Capture Channel 0 Enable */
+ uint32_t CPTEN1:1; /*!< bit: 25 Capture Channel 1 Enable */
+ uint32_t CPTEN2:1; /*!< bit: 26 Capture Channel 2 Enable */
+ uint32_t CPTEN3:1; /*!< bit: 27 Capture Channel 3 Enable */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :24; /*!< bit: 0..23 Reserved */
+ uint32_t CPTEN:4; /*!< bit: 24..27 Capture Channel x Enable */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -148,14 +148,14 @@ typedef union {
/* -------- TCC_CTRLBCLR : (TCC Offset: 0x04) (R/W 8) Control B Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DIR:1; /*!< bit: 0 Counter Direction */
- uint8_t LUPD:1; /*!< bit: 1 Lock Update */
- uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
- uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */
- uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DIR:1; /*!< bit: 0 Counter Direction */
+ uint8_t LUPD:1; /*!< bit: 1 Lock Update */
+ uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
+ uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */
+ uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} TCC_CTRLBCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -197,14 +197,14 @@ typedef union {
/* -------- TCC_CTRLBSET : (TCC Offset: 0x05) (R/W 8) Control B Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DIR:1; /*!< bit: 0 Counter Direction */
- uint8_t LUPD:1; /*!< bit: 1 Lock Update */
- uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
- uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */
- uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DIR:1; /*!< bit: 0 Counter Direction */
+ uint8_t LUPD:1; /*!< bit: 1 Lock Update */
+ uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
+ uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */
+ uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} TCC_CTRLBSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -246,37 +246,37 @@ typedef union {
/* -------- TCC_SYNCBUSY : (TCC Offset: 0x08) (R/ 32) Synchronization Busy -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Swrst Busy */
- uint32_t ENABLE:1; /*!< bit: 1 Enable Busy */
- uint32_t CTRLB:1; /*!< bit: 2 Ctrlb Busy */
- uint32_t STATUS:1; /*!< bit: 3 Status Busy */
- uint32_t COUNT:1; /*!< bit: 4 Count Busy */
- uint32_t PATT:1; /*!< bit: 5 Pattern Busy */
- uint32_t WAVE:1; /*!< bit: 6 Wave Busy */
- uint32_t PER:1; /*!< bit: 7 Period busy */
- uint32_t CC0:1; /*!< bit: 8 Compare Channel 0 Busy */
- uint32_t CC1:1; /*!< bit: 9 Compare Channel 1 Busy */
- uint32_t CC2:1; /*!< bit: 10 Compare Channel 2 Busy */
- uint32_t CC3:1; /*!< bit: 11 Compare Channel 3 Busy */
- uint32_t :4; /*!< bit: 12..15 Reserved */
- uint32_t PATTB:1; /*!< bit: 16 Pattern Buffer Busy */
- uint32_t WAVEB:1; /*!< bit: 17 Wave Buffer Busy */
- uint32_t PERB:1; /*!< bit: 18 Period Buffer Busy */
- uint32_t CCB0:1; /*!< bit: 19 Compare Channel Buffer 0 Busy */
- uint32_t CCB1:1; /*!< bit: 20 Compare Channel Buffer 1 Busy */
- uint32_t CCB2:1; /*!< bit: 21 Compare Channel Buffer 2 Busy */
- uint32_t CCB3:1; /*!< bit: 22 Compare Channel Buffer 3 Busy */
- uint32_t :9; /*!< bit: 23..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :8; /*!< bit: 0.. 7 Reserved */
- uint32_t CC:4; /*!< bit: 8..11 Compare Channel x Busy */
- uint32_t :7; /*!< bit: 12..18 Reserved */
- uint32_t CCB:4; /*!< bit: 19..22 Compare Channel Buffer x Busy */
- uint32_t :9; /*!< bit: 23..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Swrst Busy */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable Busy */
+ uint32_t CTRLB:1; /*!< bit: 2 Ctrlb Busy */
+ uint32_t STATUS:1; /*!< bit: 3 Status Busy */
+ uint32_t COUNT:1; /*!< bit: 4 Count Busy */
+ uint32_t PATT:1; /*!< bit: 5 Pattern Busy */
+ uint32_t WAVE:1; /*!< bit: 6 Wave Busy */
+ uint32_t PER:1; /*!< bit: 7 Period busy */
+ uint32_t CC0:1; /*!< bit: 8 Compare Channel 0 Busy */
+ uint32_t CC1:1; /*!< bit: 9 Compare Channel 1 Busy */
+ uint32_t CC2:1; /*!< bit: 10 Compare Channel 2 Busy */
+ uint32_t CC3:1; /*!< bit: 11 Compare Channel 3 Busy */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t PATTB:1; /*!< bit: 16 Pattern Buffer Busy */
+ uint32_t WAVEB:1; /*!< bit: 17 Wave Buffer Busy */
+ uint32_t PERB:1; /*!< bit: 18 Period Buffer Busy */
+ uint32_t CCB0:1; /*!< bit: 19 Compare Channel Buffer 0 Busy */
+ uint32_t CCB1:1; /*!< bit: 20 Compare Channel Buffer 1 Busy */
+ uint32_t CCB2:1; /*!< bit: 21 Compare Channel Buffer 2 Busy */
+ uint32_t CCB3:1; /*!< bit: 22 Compare Channel Buffer 3 Busy */
+ uint32_t :9; /*!< bit: 23..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :8; /*!< bit: 0.. 7 Reserved */
+ uint32_t CC:4; /*!< bit: 8..11 Compare Channel x Busy */
+ uint32_t :7; /*!< bit: 12..18 Reserved */
+ uint32_t CCB:4; /*!< bit: 19..22 Compare Channel Buffer x Busy */
+ uint32_t :9; /*!< bit: 23..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_SYNCBUSY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -332,22 +332,22 @@ typedef union {
/* -------- TCC_FCTRLA : (TCC Offset: 0x0C) (R/W 32) Recoverable Fault A Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SRC:2; /*!< bit: 0.. 1 Fault A Source */
- uint32_t :1; /*!< bit: 2 Reserved */
- uint32_t KEEP:1; /*!< bit: 3 Fault A Keeper */
- uint32_t QUAL:1; /*!< bit: 4 Fault A Qualification */
- uint32_t BLANK:2; /*!< bit: 5.. 6 Fault A Blanking Mode */
- uint32_t RESTART:1; /*!< bit: 7 Fault A Restart */
- uint32_t HALT:2; /*!< bit: 8.. 9 Fault A Halt Mode */
- uint32_t CHSEL:2; /*!< bit: 10..11 Fault A Capture Channel */
- uint32_t CAPTURE:3; /*!< bit: 12..14 Fault A Capture Action */
- uint32_t :1; /*!< bit: 15 Reserved */
- uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault A Blanking Time */
- uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault A Filter Value */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SRC:2; /*!< bit: 0.. 1 Fault A Source */
+ uint32_t :1; /*!< bit: 2 Reserved */
+ uint32_t KEEP:1; /*!< bit: 3 Fault A Keeper */
+ uint32_t QUAL:1; /*!< bit: 4 Fault A Qualification */
+ uint32_t BLANK:2; /*!< bit: 5.. 6 Fault A Blanking Mode */
+ uint32_t RESTART:1; /*!< bit: 7 Fault A Restart */
+ uint32_t HALT:2; /*!< bit: 8.. 9 Fault A Halt Mode */
+ uint32_t CHSEL:2; /*!< bit: 10..11 Fault A Capture Channel */
+ uint32_t CAPTURE:3; /*!< bit: 12..14 Fault A Capture Action */
+ uint32_t :1; /*!< bit: 15 Reserved */
+ uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault A Blanking Time */
+ uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault A Filter Value */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_FCTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -434,22 +434,22 @@ typedef union {
/* -------- TCC_FCTRLB : (TCC Offset: 0x10) (R/W 32) Recoverable Fault B Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SRC:2; /*!< bit: 0.. 1 Fault B Source */
- uint32_t :1; /*!< bit: 2 Reserved */
- uint32_t KEEP:1; /*!< bit: 3 Fault B Keeper */
- uint32_t QUAL:1; /*!< bit: 4 Fault B Qualification */
- uint32_t BLANK:2; /*!< bit: 5.. 6 Fault B Blanking Mode */
- uint32_t RESTART:1; /*!< bit: 7 Fault B Restart */
- uint32_t HALT:2; /*!< bit: 8.. 9 Fault B Halt Mode */
- uint32_t CHSEL:2; /*!< bit: 10..11 Fault B Capture Channel */
- uint32_t CAPTURE:3; /*!< bit: 12..14 Fault B Capture Action */
- uint32_t :1; /*!< bit: 15 Reserved */
- uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault B Blanking Time */
- uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault B Filter Value */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SRC:2; /*!< bit: 0.. 1 Fault B Source */
+ uint32_t :1; /*!< bit: 2 Reserved */
+ uint32_t KEEP:1; /*!< bit: 3 Fault B Keeper */
+ uint32_t QUAL:1; /*!< bit: 4 Fault B Qualification */
+ uint32_t BLANK:2; /*!< bit: 5.. 6 Fault B Blanking Mode */
+ uint32_t RESTART:1; /*!< bit: 7 Fault B Restart */
+ uint32_t HALT:2; /*!< bit: 8.. 9 Fault B Halt Mode */
+ uint32_t CHSEL:2; /*!< bit: 10..11 Fault B Capture Channel */
+ uint32_t CAPTURE:3; /*!< bit: 12..14 Fault B Capture Action */
+ uint32_t :1; /*!< bit: 15 Reserved */
+ uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault B Blanking Time */
+ uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault B Filter Value */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_FCTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -536,23 +536,23 @@ typedef union {
/* -------- TCC_WEXCTRL : (TCC Offset: 0x14) (R/W 32) Waveform Extension Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t OTMX:2; /*!< bit: 0.. 1 Output Matrix */
- uint32_t :6; /*!< bit: 2.. 7 Reserved */
- uint32_t DTIEN0:1; /*!< bit: 8 Dead-time Insertion Generator 0 Enable */
- uint32_t DTIEN1:1; /*!< bit: 9 Dead-time Insertion Generator 1 Enable */
- uint32_t DTIEN2:1; /*!< bit: 10 Dead-time Insertion Generator 2 Enable */
- uint32_t DTIEN3:1; /*!< bit: 11 Dead-time Insertion Generator 3 Enable */
- uint32_t :4; /*!< bit: 12..15 Reserved */
- uint32_t DTLS:8; /*!< bit: 16..23 Dead-time Low Side Outputs Value */
- uint32_t DTHS:8; /*!< bit: 24..31 Dead-time High Side Outputs Value */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :8; /*!< bit: 0.. 7 Reserved */
- uint32_t DTIEN:4; /*!< bit: 8..11 Dead-time Insertion Generator x Enable */
- uint32_t :20; /*!< bit: 12..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t OTMX:2; /*!< bit: 0.. 1 Output Matrix */
+ uint32_t :6; /*!< bit: 2.. 7 Reserved */
+ uint32_t DTIEN0:1; /*!< bit: 8 Dead-time Insertion Generator 0 Enable */
+ uint32_t DTIEN1:1; /*!< bit: 9 Dead-time Insertion Generator 1 Enable */
+ uint32_t DTIEN2:1; /*!< bit: 10 Dead-time Insertion Generator 2 Enable */
+ uint32_t DTIEN3:1; /*!< bit: 11 Dead-time Insertion Generator 3 Enable */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t DTLS:8; /*!< bit: 16..23 Dead-time Low Side Outputs Value */
+ uint32_t DTHS:8; /*!< bit: 24..31 Dead-time High Side Outputs Value */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :8; /*!< bit: 0.. 7 Reserved */
+ uint32_t DTIEN:4; /*!< bit: 8..11 Dead-time Insertion Generator x Enable */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_WEXCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -584,41 +584,41 @@ typedef union {
/* -------- TCC_DRVCTRL : (TCC Offset: 0x18) (R/W 32) Driver Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t NRE0:1; /*!< bit: 0 Non-Recoverable State 0 Output Enable */
- uint32_t NRE1:1; /*!< bit: 1 Non-Recoverable State 1 Output Enable */
- uint32_t NRE2:1; /*!< bit: 2 Non-Recoverable State 2 Output Enable */
- uint32_t NRE3:1; /*!< bit: 3 Non-Recoverable State 3 Output Enable */
- uint32_t NRE4:1; /*!< bit: 4 Non-Recoverable State 4 Output Enable */
- uint32_t NRE5:1; /*!< bit: 5 Non-Recoverable State 5 Output Enable */
- uint32_t NRE6:1; /*!< bit: 6 Non-Recoverable State 6 Output Enable */
- uint32_t NRE7:1; /*!< bit: 7 Non-Recoverable State 7 Output Enable */
- uint32_t NRV0:1; /*!< bit: 8 Non-Recoverable State 0 Output Value */
- uint32_t NRV1:1; /*!< bit: 9 Non-Recoverable State 1 Output Value */
- uint32_t NRV2:1; /*!< bit: 10 Non-Recoverable State 2 Output Value */
- uint32_t NRV3:1; /*!< bit: 11 Non-Recoverable State 3 Output Value */
- uint32_t NRV4:1; /*!< bit: 12 Non-Recoverable State 4 Output Value */
- uint32_t NRV5:1; /*!< bit: 13 Non-Recoverable State 5 Output Value */
- uint32_t NRV6:1; /*!< bit: 14 Non-Recoverable State 6 Output Value */
- uint32_t NRV7:1; /*!< bit: 15 Non-Recoverable State 7 Output Value */
- uint32_t INVEN0:1; /*!< bit: 16 Output Waveform 0 Inversion */
- uint32_t INVEN1:1; /*!< bit: 17 Output Waveform 1 Inversion */
- uint32_t INVEN2:1; /*!< bit: 18 Output Waveform 2 Inversion */
- uint32_t INVEN3:1; /*!< bit: 19 Output Waveform 3 Inversion */
- uint32_t INVEN4:1; /*!< bit: 20 Output Waveform 4 Inversion */
- uint32_t INVEN5:1; /*!< bit: 21 Output Waveform 5 Inversion */
- uint32_t INVEN6:1; /*!< bit: 22 Output Waveform 6 Inversion */
- uint32_t INVEN7:1; /*!< bit: 23 Output Waveform 7 Inversion */
- uint32_t FILTERVAL0:4; /*!< bit: 24..27 Non-Recoverable Fault Input 0 Filter Value */
- uint32_t FILTERVAL1:4; /*!< bit: 28..31 Non-Recoverable Fault Input 1 Filter Value */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t NRE:8; /*!< bit: 0.. 7 Non-Recoverable State x Output Enable */
- uint32_t NRV:8; /*!< bit: 8..15 Non-Recoverable State x Output Value */
- uint32_t INVEN:8; /*!< bit: 16..23 Output Waveform x Inversion */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t NRE0:1; /*!< bit: 0 Non-Recoverable State 0 Output Enable */
+ uint32_t NRE1:1; /*!< bit: 1 Non-Recoverable State 1 Output Enable */
+ uint32_t NRE2:1; /*!< bit: 2 Non-Recoverable State 2 Output Enable */
+ uint32_t NRE3:1; /*!< bit: 3 Non-Recoverable State 3 Output Enable */
+ uint32_t NRE4:1; /*!< bit: 4 Non-Recoverable State 4 Output Enable */
+ uint32_t NRE5:1; /*!< bit: 5 Non-Recoverable State 5 Output Enable */
+ uint32_t NRE6:1; /*!< bit: 6 Non-Recoverable State 6 Output Enable */
+ uint32_t NRE7:1; /*!< bit: 7 Non-Recoverable State 7 Output Enable */
+ uint32_t NRV0:1; /*!< bit: 8 Non-Recoverable State 0 Output Value */
+ uint32_t NRV1:1; /*!< bit: 9 Non-Recoverable State 1 Output Value */
+ uint32_t NRV2:1; /*!< bit: 10 Non-Recoverable State 2 Output Value */
+ uint32_t NRV3:1; /*!< bit: 11 Non-Recoverable State 3 Output Value */
+ uint32_t NRV4:1; /*!< bit: 12 Non-Recoverable State 4 Output Value */
+ uint32_t NRV5:1; /*!< bit: 13 Non-Recoverable State 5 Output Value */
+ uint32_t NRV6:1; /*!< bit: 14 Non-Recoverable State 6 Output Value */
+ uint32_t NRV7:1; /*!< bit: 15 Non-Recoverable State 7 Output Value */
+ uint32_t INVEN0:1; /*!< bit: 16 Output Waveform 0 Inversion */
+ uint32_t INVEN1:1; /*!< bit: 17 Output Waveform 1 Inversion */
+ uint32_t INVEN2:1; /*!< bit: 18 Output Waveform 2 Inversion */
+ uint32_t INVEN3:1; /*!< bit: 19 Output Waveform 3 Inversion */
+ uint32_t INVEN4:1; /*!< bit: 20 Output Waveform 4 Inversion */
+ uint32_t INVEN5:1; /*!< bit: 21 Output Waveform 5 Inversion */
+ uint32_t INVEN6:1; /*!< bit: 22 Output Waveform 6 Inversion */
+ uint32_t INVEN7:1; /*!< bit: 23 Output Waveform 7 Inversion */
+ uint32_t FILTERVAL0:4; /*!< bit: 24..27 Non-Recoverable Fault Input 0 Filter Value */
+ uint32_t FILTERVAL1:4; /*!< bit: 28..31 Non-Recoverable Fault Input 1 Filter Value */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t NRE:8; /*!< bit: 0.. 7 Non-Recoverable State x Output Enable */
+ uint32_t NRV:8; /*!< bit: 8..15 Non-Recoverable State x Output Value */
+ uint32_t INVEN:8; /*!< bit: 16..23 Output Waveform x Inversion */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_DRVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -693,13 +693,13 @@ typedef union {
/* -------- TCC_DBGCTRL : (TCC Offset: 0x1E) (R/W 8) Debug Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DBGRUN:1; /*!< bit: 0 Debug Running Mode */
- uint8_t :1; /*!< bit: 1 Reserved */
- uint8_t FDDBD:1; /*!< bit: 2 Fault Detection on Debug Break Detection */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DBGRUN:1; /*!< bit: 0 Debug Running Mode */
+ uint8_t :1; /*!< bit: 1 Reserved */
+ uint8_t FDDBD:1; /*!< bit: 2 Fault Detection on Debug Break Detection */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} TCC_DBGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -715,39 +715,39 @@ typedef union {
/* -------- TCC_EVCTRL : (TCC Offset: 0x20) (R/W 32) Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t EVACT0:3; /*!< bit: 0.. 2 Timer/counter Input Event0 Action */
- uint32_t EVACT1:3; /*!< bit: 3.. 5 Timer/counter Input Event1 Action */
- uint32_t CNTSEL:2; /*!< bit: 6.. 7 Timer/counter Output Event Mode */
- uint32_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Output Event Enable */
- uint32_t TRGEO:1; /*!< bit: 9 Retrigger Output Event Enable */
- uint32_t CNTEO:1; /*!< bit: 10 Timer/counter Output Event Enable */
- uint32_t :1; /*!< bit: 11 Reserved */
- uint32_t TCINV0:1; /*!< bit: 12 Inverted Event 0 Input Enable */
- uint32_t TCINV1:1; /*!< bit: 13 Inverted Event 1 Input Enable */
- uint32_t TCEI0:1; /*!< bit: 14 Timer/counter Event 0 Input Enable */
- uint32_t TCEI1:1; /*!< bit: 15 Timer/counter Event 1 Input Enable */
- uint32_t MCEI0:1; /*!< bit: 16 Match or Capture Channel 0 Event Input Enable */
- uint32_t MCEI1:1; /*!< bit: 17 Match or Capture Channel 1 Event Input Enable */
- uint32_t MCEI2:1; /*!< bit: 18 Match or Capture Channel 2 Event Input Enable */
- uint32_t MCEI3:1; /*!< bit: 19 Match or Capture Channel 3 Event Input Enable */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t MCEO0:1; /*!< bit: 24 Match or Capture Channel 0 Event Output Enable */
- uint32_t MCEO1:1; /*!< bit: 25 Match or Capture Channel 1 Event Output Enable */
- uint32_t MCEO2:1; /*!< bit: 26 Match or Capture Channel 2 Event Output Enable */
- uint32_t MCEO3:1; /*!< bit: 27 Match or Capture Channel 3 Event Output Enable */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :12; /*!< bit: 0..11 Reserved */
- uint32_t TCINV:2; /*!< bit: 12..13 Inverted Event x Input Enable */
- uint32_t TCEI:2; /*!< bit: 14..15 Timer/counter Event x Input Enable */
- uint32_t MCEI:4; /*!< bit: 16..19 Match or Capture Channel x Event Input Enable */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t MCEO:4; /*!< bit: 24..27 Match or Capture Channel x Event Output Enable */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t EVACT0:3; /*!< bit: 0.. 2 Timer/counter Input Event0 Action */
+ uint32_t EVACT1:3; /*!< bit: 3.. 5 Timer/counter Input Event1 Action */
+ uint32_t CNTSEL:2; /*!< bit: 6.. 7 Timer/counter Output Event Mode */
+ uint32_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Output Event Enable */
+ uint32_t TRGEO:1; /*!< bit: 9 Retrigger Output Event Enable */
+ uint32_t CNTEO:1; /*!< bit: 10 Timer/counter Output Event Enable */
+ uint32_t :1; /*!< bit: 11 Reserved */
+ uint32_t TCINV0:1; /*!< bit: 12 Inverted Event 0 Input Enable */
+ uint32_t TCINV1:1; /*!< bit: 13 Inverted Event 1 Input Enable */
+ uint32_t TCEI0:1; /*!< bit: 14 Timer/counter Event 0 Input Enable */
+ uint32_t TCEI1:1; /*!< bit: 15 Timer/counter Event 1 Input Enable */
+ uint32_t MCEI0:1; /*!< bit: 16 Match or Capture Channel 0 Event Input Enable */
+ uint32_t MCEI1:1; /*!< bit: 17 Match or Capture Channel 1 Event Input Enable */
+ uint32_t MCEI2:1; /*!< bit: 18 Match or Capture Channel 2 Event Input Enable */
+ uint32_t MCEI3:1; /*!< bit: 19 Match or Capture Channel 3 Event Input Enable */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t MCEO0:1; /*!< bit: 24 Match or Capture Channel 0 Event Output Enable */
+ uint32_t MCEO1:1; /*!< bit: 25 Match or Capture Channel 1 Event Output Enable */
+ uint32_t MCEO2:1; /*!< bit: 26 Match or Capture Channel 2 Event Output Enable */
+ uint32_t MCEO3:1; /*!< bit: 27 Match or Capture Channel 3 Event Output Enable */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :12; /*!< bit: 0..11 Reserved */
+ uint32_t TCINV:2; /*!< bit: 12..13 Inverted Event x Input Enable */
+ uint32_t TCEI:2; /*!< bit: 14..15 Timer/counter Event x Input Enable */
+ uint32_t MCEI:4; /*!< bit: 16..19 Match or Capture Channel x Event Input Enable */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t MCEO:4; /*!< bit: 24..27 Match or Capture Channel x Event Output Enable */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -850,30 +850,30 @@ typedef union {
/* -------- TCC_INTENCLR : (TCC Offset: 0x24) (R/W 32) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
- uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */
- uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */
- uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */
- uint32_t :6; /*!< bit: 4.. 9 Reserved */
- uint32_t UFS:1; /*!< bit: 10 Non-Recoverable Update Fault Interrupt Enable */
- uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */
- uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */
- uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */
- uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */
- uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */
- uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */
- uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */
- uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */
- uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */
- uint32_t :12; /*!< bit: 20..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :16; /*!< bit: 0..15 Reserved */
- uint32_t MC:4; /*!< bit: 16..19 Match or Capture Channel x Interrupt Enable */
- uint32_t :12; /*!< bit: 20..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
+ uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */
+ uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */
+ uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */
+ uint32_t :6; /*!< bit: 4.. 9 Reserved */
+ uint32_t UFS:1; /*!< bit: 10 Non-Recoverable Update Fault Interrupt Enable */
+ uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */
+ uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */
+ uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */
+ uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */
+ uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */
+ uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */
+ uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */
+ uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */
+ uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :16; /*!< bit: 0..15 Reserved */
+ uint32_t MC:4; /*!< bit: 16..19 Match or Capture Channel x Interrupt Enable */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -916,30 +916,30 @@ typedef union {
/* -------- TCC_INTENSET : (TCC Offset: 0x28) (R/W 32) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
- uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */
- uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */
- uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */
- uint32_t :6; /*!< bit: 4.. 9 Reserved */
- uint32_t UFS:1; /*!< bit: 10 Non-Recoverable Update Fault Interrupt Enable */
- uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */
- uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */
- uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */
- uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */
- uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */
- uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */
- uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */
- uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */
- uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */
- uint32_t :12; /*!< bit: 20..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :16; /*!< bit: 0..15 Reserved */
- uint32_t MC:4; /*!< bit: 16..19 Match or Capture Channel x Interrupt Enable */
- uint32_t :12; /*!< bit: 20..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
+ uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */
+ uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */
+ uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */
+ uint32_t :6; /*!< bit: 4.. 9 Reserved */
+ uint32_t UFS:1; /*!< bit: 10 Non-Recoverable Update Fault Interrupt Enable */
+ uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */
+ uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */
+ uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */
+ uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */
+ uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */
+ uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */
+ uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */
+ uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */
+ uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :16; /*!< bit: 0..15 Reserved */
+ uint32_t MC:4; /*!< bit: 16..19 Match or Capture Channel x Interrupt Enable */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -982,30 +982,30 @@ typedef union {
/* -------- TCC_INTFLAG : (TCC Offset: 0x2C) (R/W 32) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t OVF:1; /*!< bit: 0 Overflow */
- uint32_t TRG:1; /*!< bit: 1 Retrigger */
- uint32_t CNT:1; /*!< bit: 2 Counter */
- uint32_t ERR:1; /*!< bit: 3 Error */
- uint32_t :6; /*!< bit: 4.. 9 Reserved */
- uint32_t UFS:1; /*!< bit: 10 Non-Recoverable Update Fault */
- uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault */
- uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A */
- uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B */
- uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 */
- uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 */
- uint32_t MC0:1; /*!< bit: 16 Match or Capture 0 */
- uint32_t MC1:1; /*!< bit: 17 Match or Capture 1 */
- uint32_t MC2:1; /*!< bit: 18 Match or Capture 2 */
- uint32_t MC3:1; /*!< bit: 19 Match or Capture 3 */
- uint32_t :12; /*!< bit: 20..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :16; /*!< bit: 0..15 Reserved */
- uint32_t MC:4; /*!< bit: 16..19 Match or Capture x */
- uint32_t :12; /*!< bit: 20..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t OVF:1; /*!< bit: 0 Overflow */
+ uint32_t TRG:1; /*!< bit: 1 Retrigger */
+ uint32_t CNT:1; /*!< bit: 2 Counter */
+ uint32_t ERR:1; /*!< bit: 3 Error */
+ uint32_t :6; /*!< bit: 4.. 9 Reserved */
+ uint32_t UFS:1; /*!< bit: 10 Non-Recoverable Update Fault */
+ uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault */
+ uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A */
+ uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B */
+ uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 */
+ uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 */
+ uint32_t MC0:1; /*!< bit: 16 Match or Capture 0 */
+ uint32_t MC1:1; /*!< bit: 17 Match or Capture 1 */
+ uint32_t MC2:1; /*!< bit: 18 Match or Capture 2 */
+ uint32_t MC3:1; /*!< bit: 19 Match or Capture 3 */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :16; /*!< bit: 0..15 Reserved */
+ uint32_t MC:4; /*!< bit: 16..19 Match or Capture x */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1048,42 +1048,42 @@ typedef union {
/* -------- TCC_STATUS : (TCC Offset: 0x30) (R/W 32) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t STOP:1; /*!< bit: 0 Stop */
- uint32_t IDX:1; /*!< bit: 1 Ramp */
- uint32_t UFS:1; /*!< bit: 2 Non-Recoverable Update Fault State */
- uint32_t DFS:1; /*!< bit: 3 Non-Recoverable Debug Fault State */
- uint32_t SLAVE:1; /*!< bit: 4 Slave */
- uint32_t PATTBV:1; /*!< bit: 5 Pattern Buffer Valid */
- uint32_t WAVEBV:1; /*!< bit: 6 Wave Buffer Valid */
- uint32_t PERBV:1; /*!< bit: 7 Period Buffer Valid */
- uint32_t FAULTAIN:1; /*!< bit: 8 Recoverable Fault A Input */
- uint32_t FAULTBIN:1; /*!< bit: 9 Recoverable Fault B Input */
- uint32_t FAULT0IN:1; /*!< bit: 10 Non-Recoverable Fault0 Input */
- uint32_t FAULT1IN:1; /*!< bit: 11 Non-Recoverable Fault1 Input */
- uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A State */
- uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B State */
- uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 State */
- uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 State */
- uint32_t CCBV0:1; /*!< bit: 16 Compare Channel 0 Buffer Valid */
- uint32_t CCBV1:1; /*!< bit: 17 Compare Channel 1 Buffer Valid */
- uint32_t CCBV2:1; /*!< bit: 18 Compare Channel 2 Buffer Valid */
- uint32_t CCBV3:1; /*!< bit: 19 Compare Channel 3 Buffer Valid */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t CMP0:1; /*!< bit: 24 Compare Channel 0 Value */
- uint32_t CMP1:1; /*!< bit: 25 Compare Channel 1 Value */
- uint32_t CMP2:1; /*!< bit: 26 Compare Channel 2 Value */
- uint32_t CMP3:1; /*!< bit: 27 Compare Channel 3 Value */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :16; /*!< bit: 0..15 Reserved */
- uint32_t CCBV:4; /*!< bit: 16..19 Compare Channel x Buffer Valid */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t CMP:4; /*!< bit: 24..27 Compare Channel x Value */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t STOP:1; /*!< bit: 0 Stop */
+ uint32_t IDX:1; /*!< bit: 1 Ramp */
+ uint32_t UFS:1; /*!< bit: 2 Non-Recoverable Update Fault State */
+ uint32_t DFS:1; /*!< bit: 3 Non-Recoverable Debug Fault State */
+ uint32_t SLAVE:1; /*!< bit: 4 Slave */
+ uint32_t PATTBV:1; /*!< bit: 5 Pattern Buffer Valid */
+ uint32_t WAVEBV:1; /*!< bit: 6 Wave Buffer Valid */
+ uint32_t PERBV:1; /*!< bit: 7 Period Buffer Valid */
+ uint32_t FAULTAIN:1; /*!< bit: 8 Recoverable Fault A Input */
+ uint32_t FAULTBIN:1; /*!< bit: 9 Recoverable Fault B Input */
+ uint32_t FAULT0IN:1; /*!< bit: 10 Non-Recoverable Fault0 Input */
+ uint32_t FAULT1IN:1; /*!< bit: 11 Non-Recoverable Fault1 Input */
+ uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A State */
+ uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B State */
+ uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 State */
+ uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 State */
+ uint32_t CCBV0:1; /*!< bit: 16 Compare Channel 0 Buffer Valid */
+ uint32_t CCBV1:1; /*!< bit: 17 Compare Channel 1 Buffer Valid */
+ uint32_t CCBV2:1; /*!< bit: 18 Compare Channel 2 Buffer Valid */
+ uint32_t CCBV3:1; /*!< bit: 19 Compare Channel 3 Buffer Valid */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t CMP0:1; /*!< bit: 24 Compare Channel 0 Value */
+ uint32_t CMP1:1; /*!< bit: 25 Compare Channel 1 Value */
+ uint32_t CMP2:1; /*!< bit: 26 Compare Channel 2 Value */
+ uint32_t CMP3:1; /*!< bit: 27 Compare Channel 3 Value */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :16; /*!< bit: 0..15 Reserved */
+ uint32_t CCBV:4; /*!< bit: 16..19 Compare Channel x Buffer Valid */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t CMP:4; /*!< bit: 24..27 Compare Channel x Value */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1149,26 +1149,26 @@ typedef union {
/* -------- TCC_COUNT : (TCC Offset: 0x34) (R/W 32) Count -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct { // DITH4 mode
- uint32_t :4; /*!< bit: 0.. 3 Reserved */
- uint32_t COUNT:20; /*!< bit: 4..23 Counter Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH4; /*!< Structure used for DITH4 */
- struct { // DITH5 mode
- uint32_t :5; /*!< bit: 0.. 4 Reserved */
- uint32_t COUNT:19; /*!< bit: 5..23 Counter Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH5; /*!< Structure used for DITH5 */
- struct { // DITH6 mode
- uint32_t :6; /*!< bit: 0.. 5 Reserved */
- uint32_t COUNT:18; /*!< bit: 6..23 Counter Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH6; /*!< Structure used for DITH6 */
- struct {
- uint32_t COUNT:24; /*!< bit: 0..23 Counter Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct { // DITH4 mode
+ uint32_t :4; /*!< bit: 0.. 3 Reserved */
+ uint32_t COUNT:20; /*!< bit: 4..23 Counter Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH4; /*!< Structure used for DITH4 */
+ struct { // DITH5 mode
+ uint32_t :5; /*!< bit: 0.. 4 Reserved */
+ uint32_t COUNT:19; /*!< bit: 5..23 Counter Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH5; /*!< Structure used for DITH5 */
+ struct { // DITH6 mode
+ uint32_t :6; /*!< bit: 0.. 5 Reserved */
+ uint32_t COUNT:18; /*!< bit: 6..23 Counter Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH6; /*!< Structure used for DITH6 */
+ struct {
+ uint32_t COUNT:24; /*!< bit: 0..23 Counter Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_COUNT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1201,29 +1201,29 @@ typedef union {
/* -------- TCC_PATT : (TCC Offset: 0x38) (R/W 16) Pattern -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t PGE0:1; /*!< bit: 0 Pattern Generator 0 Output Enable */
- uint16_t PGE1:1; /*!< bit: 1 Pattern Generator 1 Output Enable */
- uint16_t PGE2:1; /*!< bit: 2 Pattern Generator 2 Output Enable */
- uint16_t PGE3:1; /*!< bit: 3 Pattern Generator 3 Output Enable */
- uint16_t PGE4:1; /*!< bit: 4 Pattern Generator 4 Output Enable */
- uint16_t PGE5:1; /*!< bit: 5 Pattern Generator 5 Output Enable */
- uint16_t PGE6:1; /*!< bit: 6 Pattern Generator 6 Output Enable */
- uint16_t PGE7:1; /*!< bit: 7 Pattern Generator 7 Output Enable */
- uint16_t PGV0:1; /*!< bit: 8 Pattern Generator 0 Output Value */
- uint16_t PGV1:1; /*!< bit: 9 Pattern Generator 1 Output Value */
- uint16_t PGV2:1; /*!< bit: 10 Pattern Generator 2 Output Value */
- uint16_t PGV3:1; /*!< bit: 11 Pattern Generator 3 Output Value */
- uint16_t PGV4:1; /*!< bit: 12 Pattern Generator 4 Output Value */
- uint16_t PGV5:1; /*!< bit: 13 Pattern Generator 5 Output Value */
- uint16_t PGV6:1; /*!< bit: 14 Pattern Generator 6 Output Value */
- uint16_t PGV7:1; /*!< bit: 15 Pattern Generator 7 Output Value */
- } bit; /*!< Structure used for bit access */
- struct {
- uint16_t PGE:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable */
- uint16_t PGV:8; /*!< bit: 8..15 Pattern Generator x Output Value */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t PGE0:1; /*!< bit: 0 Pattern Generator 0 Output Enable */
+ uint16_t PGE1:1; /*!< bit: 1 Pattern Generator 1 Output Enable */
+ uint16_t PGE2:1; /*!< bit: 2 Pattern Generator 2 Output Enable */
+ uint16_t PGE3:1; /*!< bit: 3 Pattern Generator 3 Output Enable */
+ uint16_t PGE4:1; /*!< bit: 4 Pattern Generator 4 Output Enable */
+ uint16_t PGE5:1; /*!< bit: 5 Pattern Generator 5 Output Enable */
+ uint16_t PGE6:1; /*!< bit: 6 Pattern Generator 6 Output Enable */
+ uint16_t PGE7:1; /*!< bit: 7 Pattern Generator 7 Output Enable */
+ uint16_t PGV0:1; /*!< bit: 8 Pattern Generator 0 Output Value */
+ uint16_t PGV1:1; /*!< bit: 9 Pattern Generator 1 Output Value */
+ uint16_t PGV2:1; /*!< bit: 10 Pattern Generator 2 Output Value */
+ uint16_t PGV3:1; /*!< bit: 11 Pattern Generator 3 Output Value */
+ uint16_t PGV4:1; /*!< bit: 12 Pattern Generator 4 Output Value */
+ uint16_t PGV5:1; /*!< bit: 13 Pattern Generator 5 Output Value */
+ uint16_t PGV6:1; /*!< bit: 14 Pattern Generator 6 Output Value */
+ uint16_t PGV7:1; /*!< bit: 15 Pattern Generator 7 Output Value */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t PGE:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable */
+ uint16_t PGV:8; /*!< bit: 8..15 Pattern Generator x Output Value */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
} TCC_PATT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1273,38 +1273,38 @@ typedef union {
/* -------- TCC_WAVE : (TCC Offset: 0x3C) (R/W 32) Waveform Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t WAVEGEN:3; /*!< bit: 0.. 2 Waveform Generation */
- uint32_t :1; /*!< bit: 3 Reserved */
- uint32_t RAMP:2; /*!< bit: 4.. 5 Ramp Mode */
- uint32_t :1; /*!< bit: 6 Reserved */
- uint32_t CIPEREN:1; /*!< bit: 7 Circular period Enable */
- uint32_t CICCEN0:1; /*!< bit: 8 Circular Channel 0 Enable */
- uint32_t CICCEN1:1; /*!< bit: 9 Circular Channel 1 Enable */
- uint32_t CICCEN2:1; /*!< bit: 10 Circular Channel 2 Enable */
- uint32_t CICCEN3:1; /*!< bit: 11 Circular Channel 3 Enable */
- uint32_t :4; /*!< bit: 12..15 Reserved */
- uint32_t POL0:1; /*!< bit: 16 Channel 0 Polarity */
- uint32_t POL1:1; /*!< bit: 17 Channel 1 Polarity */
- uint32_t POL2:1; /*!< bit: 18 Channel 2 Polarity */
- uint32_t POL3:1; /*!< bit: 19 Channel 3 Polarity */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t SWAP0:1; /*!< bit: 24 Swap DTI Output Pair 0 */
- uint32_t SWAP1:1; /*!< bit: 25 Swap DTI Output Pair 1 */
- uint32_t SWAP2:1; /*!< bit: 26 Swap DTI Output Pair 2 */
- uint32_t SWAP3:1; /*!< bit: 27 Swap DTI Output Pair 3 */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :8; /*!< bit: 0.. 7 Reserved */
- uint32_t CICCEN:4; /*!< bit: 8..11 Circular Channel x Enable */
- uint32_t :4; /*!< bit: 12..15 Reserved */
- uint32_t POL:4; /*!< bit: 16..19 Channel x Polarity */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t SWAP:4; /*!< bit: 24..27 Swap DTI Output Pair x */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t WAVEGEN:3; /*!< bit: 0.. 2 Waveform Generation */
+ uint32_t :1; /*!< bit: 3 Reserved */
+ uint32_t RAMP:2; /*!< bit: 4.. 5 Ramp Mode */
+ uint32_t :1; /*!< bit: 6 Reserved */
+ uint32_t CIPEREN:1; /*!< bit: 7 Circular period Enable */
+ uint32_t CICCEN0:1; /*!< bit: 8 Circular Channel 0 Enable */
+ uint32_t CICCEN1:1; /*!< bit: 9 Circular Channel 1 Enable */
+ uint32_t CICCEN2:1; /*!< bit: 10 Circular Channel 2 Enable */
+ uint32_t CICCEN3:1; /*!< bit: 11 Circular Channel 3 Enable */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t POL0:1; /*!< bit: 16 Channel 0 Polarity */
+ uint32_t POL1:1; /*!< bit: 17 Channel 1 Polarity */
+ uint32_t POL2:1; /*!< bit: 18 Channel 2 Polarity */
+ uint32_t POL3:1; /*!< bit: 19 Channel 3 Polarity */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t SWAP0:1; /*!< bit: 24 Swap DTI Output Pair 0 */
+ uint32_t SWAP1:1; /*!< bit: 25 Swap DTI Output Pair 1 */
+ uint32_t SWAP2:1; /*!< bit: 26 Swap DTI Output Pair 2 */
+ uint32_t SWAP3:1; /*!< bit: 27 Swap DTI Output Pair 3 */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :8; /*!< bit: 0.. 7 Reserved */
+ uint32_t CICCEN:4; /*!< bit: 8..11 Circular Channel x Enable */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t POL:4; /*!< bit: 16..19 Channel x Polarity */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t SWAP:4; /*!< bit: 24..27 Swap DTI Output Pair x */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_WAVE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1379,26 +1379,26 @@ typedef union {
/* -------- TCC_PER : (TCC Offset: 0x40) (R/W 32) Period -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct { // DITH4 mode
- uint32_t DITHERCY:4; /*!< bit: 0.. 3 Dithering Cycle Number */
- uint32_t PER:20; /*!< bit: 4..23 Period Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH4; /*!< Structure used for DITH4 */
- struct { // DITH5 mode
- uint32_t DITHERCY:5; /*!< bit: 0.. 4 Dithering Cycle Number */
- uint32_t PER:19; /*!< bit: 5..23 Period Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH5; /*!< Structure used for DITH5 */
- struct { // DITH6 mode
- uint32_t DITHERCY:6; /*!< bit: 0.. 5 Dithering Cycle Number */
- uint32_t PER:18; /*!< bit: 6..23 Period Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH6; /*!< Structure used for DITH6 */
- struct {
- uint32_t PER:24; /*!< bit: 0..23 Period Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct { // DITH4 mode
+ uint32_t DITHERCY:4; /*!< bit: 0.. 3 Dithering Cycle Number */
+ uint32_t PER:20; /*!< bit: 4..23 Period Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH4; /*!< Structure used for DITH4 */
+ struct { // DITH5 mode
+ uint32_t DITHERCY:5; /*!< bit: 0.. 4 Dithering Cycle Number */
+ uint32_t PER:19; /*!< bit: 5..23 Period Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH5; /*!< Structure used for DITH5 */
+ struct { // DITH6 mode
+ uint32_t DITHERCY:6; /*!< bit: 0.. 5 Dithering Cycle Number */
+ uint32_t PER:18; /*!< bit: 6..23 Period Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH6; /*!< Structure used for DITH6 */
+ struct {
+ uint32_t PER:24; /*!< bit: 0..23 Period Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_PER_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1440,26 +1440,26 @@ typedef union {
/* -------- TCC_CC : (TCC Offset: 0x44) (R/W 32) Compare and Capture -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct { // DITH4 mode
- uint32_t DITHERCY:4; /*!< bit: 0.. 3 Dithering Cycle Number */
- uint32_t CC:20; /*!< bit: 4..23 Channel Compare/Capture Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH4; /*!< Structure used for DITH4 */
- struct { // DITH5 mode
- uint32_t DITHERCY:5; /*!< bit: 0.. 4 Dithering Cycle Number */
- uint32_t CC:19; /*!< bit: 5..23 Channel Compare/Capture Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH5; /*!< Structure used for DITH5 */
- struct { // DITH6 mode
- uint32_t DITHERCY:6; /*!< bit: 0.. 5 Dithering Cycle Number */
- uint32_t CC:18; /*!< bit: 6..23 Channel Compare/Capture Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH6; /*!< Structure used for DITH6 */
- struct {
- uint32_t CC:24; /*!< bit: 0..23 Channel Compare/Capture Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct { // DITH4 mode
+ uint32_t DITHERCY:4; /*!< bit: 0.. 3 Dithering Cycle Number */
+ uint32_t CC:20; /*!< bit: 4..23 Channel Compare/Capture Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH4; /*!< Structure used for DITH4 */
+ struct { // DITH5 mode
+ uint32_t DITHERCY:5; /*!< bit: 0.. 4 Dithering Cycle Number */
+ uint32_t CC:19; /*!< bit: 5..23 Channel Compare/Capture Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH5; /*!< Structure used for DITH5 */
+ struct { // DITH6 mode
+ uint32_t DITHERCY:6; /*!< bit: 0.. 5 Dithering Cycle Number */
+ uint32_t CC:18; /*!< bit: 6..23 Channel Compare/Capture Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH6; /*!< Structure used for DITH6 */
+ struct {
+ uint32_t CC:24; /*!< bit: 0..23 Channel Compare/Capture Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_CC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1501,29 +1501,29 @@ typedef union {
/* -------- TCC_PATTB : (TCC Offset: 0x64) (R/W 16) Pattern Buffer -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t PGEB0:1; /*!< bit: 0 Pattern Generator 0 Output Enable Buffer */
- uint16_t PGEB1:1; /*!< bit: 1 Pattern Generator 1 Output Enable Buffer */
- uint16_t PGEB2:1; /*!< bit: 2 Pattern Generator 2 Output Enable Buffer */
- uint16_t PGEB3:1; /*!< bit: 3 Pattern Generator 3 Output Enable Buffer */
- uint16_t PGEB4:1; /*!< bit: 4 Pattern Generator 4 Output Enable Buffer */
- uint16_t PGEB5:1; /*!< bit: 5 Pattern Generator 5 Output Enable Buffer */
- uint16_t PGEB6:1; /*!< bit: 6 Pattern Generator 6 Output Enable Buffer */
- uint16_t PGEB7:1; /*!< bit: 7 Pattern Generator 7 Output Enable Buffer */
- uint16_t PGVB0:1; /*!< bit: 8 Pattern Generator 0 Output Enable */
- uint16_t PGVB1:1; /*!< bit: 9 Pattern Generator 1 Output Enable */
- uint16_t PGVB2:1; /*!< bit: 10 Pattern Generator 2 Output Enable */
- uint16_t PGVB3:1; /*!< bit: 11 Pattern Generator 3 Output Enable */
- uint16_t PGVB4:1; /*!< bit: 12 Pattern Generator 4 Output Enable */
- uint16_t PGVB5:1; /*!< bit: 13 Pattern Generator 5 Output Enable */
- uint16_t PGVB6:1; /*!< bit: 14 Pattern Generator 6 Output Enable */
- uint16_t PGVB7:1; /*!< bit: 15 Pattern Generator 7 Output Enable */
- } bit; /*!< Structure used for bit access */
- struct {
- uint16_t PGEB:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable Buffer */
- uint16_t PGVB:8; /*!< bit: 8..15 Pattern Generator x Output Enable */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t PGEB0:1; /*!< bit: 0 Pattern Generator 0 Output Enable Buffer */
+ uint16_t PGEB1:1; /*!< bit: 1 Pattern Generator 1 Output Enable Buffer */
+ uint16_t PGEB2:1; /*!< bit: 2 Pattern Generator 2 Output Enable Buffer */
+ uint16_t PGEB3:1; /*!< bit: 3 Pattern Generator 3 Output Enable Buffer */
+ uint16_t PGEB4:1; /*!< bit: 4 Pattern Generator 4 Output Enable Buffer */
+ uint16_t PGEB5:1; /*!< bit: 5 Pattern Generator 5 Output Enable Buffer */
+ uint16_t PGEB6:1; /*!< bit: 6 Pattern Generator 6 Output Enable Buffer */
+ uint16_t PGEB7:1; /*!< bit: 7 Pattern Generator 7 Output Enable Buffer */
+ uint16_t PGVB0:1; /*!< bit: 8 Pattern Generator 0 Output Enable */
+ uint16_t PGVB1:1; /*!< bit: 9 Pattern Generator 1 Output Enable */
+ uint16_t PGVB2:1; /*!< bit: 10 Pattern Generator 2 Output Enable */
+ uint16_t PGVB3:1; /*!< bit: 11 Pattern Generator 3 Output Enable */
+ uint16_t PGVB4:1; /*!< bit: 12 Pattern Generator 4 Output Enable */
+ uint16_t PGVB5:1; /*!< bit: 13 Pattern Generator 5 Output Enable */
+ uint16_t PGVB6:1; /*!< bit: 14 Pattern Generator 6 Output Enable */
+ uint16_t PGVB7:1; /*!< bit: 15 Pattern Generator 7 Output Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t PGEB:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable Buffer */
+ uint16_t PGVB:8; /*!< bit: 8..15 Pattern Generator x Output Enable */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
} TCC_PATTB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1573,38 +1573,38 @@ typedef union {
/* -------- TCC_WAVEB : (TCC Offset: 0x68) (R/W 32) Waveform Control Buffer -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t WAVEGENB:3; /*!< bit: 0.. 2 Waveform Generation Buffer */
- uint32_t :1; /*!< bit: 3 Reserved */
- uint32_t RAMPB:2; /*!< bit: 4.. 5 Ramp Mode Buffer */
- uint32_t :1; /*!< bit: 6 Reserved */
- uint32_t CIPERENB:1; /*!< bit: 7 Circular Period Enable Buffer */
- uint32_t CICCENB0:1; /*!< bit: 8 Circular Channel 0 Enable Buffer */
- uint32_t CICCENB1:1; /*!< bit: 9 Circular Channel 1 Enable Buffer */
- uint32_t CICCENB2:1; /*!< bit: 10 Circular Channel 2 Enable Buffer */
- uint32_t CICCENB3:1; /*!< bit: 11 Circular Channel 3 Enable Buffer */
- uint32_t :4; /*!< bit: 12..15 Reserved */
- uint32_t POLB0:1; /*!< bit: 16 Channel 0 Polarity Buffer */
- uint32_t POLB1:1; /*!< bit: 17 Channel 1 Polarity Buffer */
- uint32_t POLB2:1; /*!< bit: 18 Channel 2 Polarity Buffer */
- uint32_t POLB3:1; /*!< bit: 19 Channel 3 Polarity Buffer */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t SWAPB0:1; /*!< bit: 24 Swap DTI Output Pair 0 Buffer */
- uint32_t SWAPB1:1; /*!< bit: 25 Swap DTI Output Pair 1 Buffer */
- uint32_t SWAPB2:1; /*!< bit: 26 Swap DTI Output Pair 2 Buffer */
- uint32_t SWAPB3:1; /*!< bit: 27 Swap DTI Output Pair 3 Buffer */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :8; /*!< bit: 0.. 7 Reserved */
- uint32_t CICCENB:4; /*!< bit: 8..11 Circular Channel x Enable Buffer */
- uint32_t :4; /*!< bit: 12..15 Reserved */
- uint32_t POLB:4; /*!< bit: 16..19 Channel x Polarity Buffer */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t SWAPB:4; /*!< bit: 24..27 Swap DTI Output Pair x Buffer */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t WAVEGENB:3; /*!< bit: 0.. 2 Waveform Generation Buffer */
+ uint32_t :1; /*!< bit: 3 Reserved */
+ uint32_t RAMPB:2; /*!< bit: 4.. 5 Ramp Mode Buffer */
+ uint32_t :1; /*!< bit: 6 Reserved */
+ uint32_t CIPERENB:1; /*!< bit: 7 Circular Period Enable Buffer */
+ uint32_t CICCENB0:1; /*!< bit: 8 Circular Channel 0 Enable Buffer */
+ uint32_t CICCENB1:1; /*!< bit: 9 Circular Channel 1 Enable Buffer */
+ uint32_t CICCENB2:1; /*!< bit: 10 Circular Channel 2 Enable Buffer */
+ uint32_t CICCENB3:1; /*!< bit: 11 Circular Channel 3 Enable Buffer */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t POLB0:1; /*!< bit: 16 Channel 0 Polarity Buffer */
+ uint32_t POLB1:1; /*!< bit: 17 Channel 1 Polarity Buffer */
+ uint32_t POLB2:1; /*!< bit: 18 Channel 2 Polarity Buffer */
+ uint32_t POLB3:1; /*!< bit: 19 Channel 3 Polarity Buffer */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t SWAPB0:1; /*!< bit: 24 Swap DTI Output Pair 0 Buffer */
+ uint32_t SWAPB1:1; /*!< bit: 25 Swap DTI Output Pair 1 Buffer */
+ uint32_t SWAPB2:1; /*!< bit: 26 Swap DTI Output Pair 2 Buffer */
+ uint32_t SWAPB3:1; /*!< bit: 27 Swap DTI Output Pair 3 Buffer */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :8; /*!< bit: 0.. 7 Reserved */
+ uint32_t CICCENB:4; /*!< bit: 8..11 Circular Channel x Enable Buffer */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t POLB:4; /*!< bit: 16..19 Channel x Polarity Buffer */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t SWAPB:4; /*!< bit: 24..27 Swap DTI Output Pair x Buffer */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_WAVEB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1679,26 +1679,26 @@ typedef union {
/* -------- TCC_PERB : (TCC Offset: 0x6C) (R/W 32) Period Buffer -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct { // DITH4 mode
- uint32_t DITHERCYB:4; /*!< bit: 0.. 3 Dithering Buffer Cycle Number */
- uint32_t PERB:20; /*!< bit: 4..23 Period Buffer Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH4; /*!< Structure used for DITH4 */
- struct { // DITH5 mode
- uint32_t DITHERCYB:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */
- uint32_t PERB:19; /*!< bit: 5..23 Period Buffer Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH5; /*!< Structure used for DITH5 */
- struct { // DITH6 mode
- uint32_t DITHERCYB:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */
- uint32_t PERB:18; /*!< bit: 6..23 Period Buffer Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH6; /*!< Structure used for DITH6 */
- struct {
- uint32_t PERB:24; /*!< bit: 0..23 Period Buffer Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct { // DITH4 mode
+ uint32_t DITHERCYB:4; /*!< bit: 0.. 3 Dithering Buffer Cycle Number */
+ uint32_t PERB:20; /*!< bit: 4..23 Period Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH4; /*!< Structure used for DITH4 */
+ struct { // DITH5 mode
+ uint32_t DITHERCYB:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */
+ uint32_t PERB:19; /*!< bit: 5..23 Period Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH5; /*!< Structure used for DITH5 */
+ struct { // DITH6 mode
+ uint32_t DITHERCYB:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */
+ uint32_t PERB:18; /*!< bit: 6..23 Period Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH6; /*!< Structure used for DITH6 */
+ struct {
+ uint32_t PERB:24; /*!< bit: 0..23 Period Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_PERB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1740,26 +1740,26 @@ typedef union {
/* -------- TCC_CCB : (TCC Offset: 0x70) (R/W 32) Compare and Capture Buffer -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct { // DITH4 mode
- uint32_t DITHERCYB:4; /*!< bit: 0.. 3 Dithering Buffer Cycle Number */
- uint32_t CCB:20; /*!< bit: 4..23 Channel Compare/Capture Buffer Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH4; /*!< Structure used for DITH4 */
- struct { // DITH5 mode
- uint32_t DITHERCYB:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */
- uint32_t CCB:19; /*!< bit: 5..23 Channel Compare/Capture Buffer Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH5; /*!< Structure used for DITH5 */
- struct { // DITH6 mode
- uint32_t DITHERCYB:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */
- uint32_t CCB:18; /*!< bit: 6..23 Channel Compare/Capture Buffer Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH6; /*!< Structure used for DITH6 */
- struct {
- uint32_t CCB:24; /*!< bit: 0..23 Channel Compare/Capture Buffer Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct { // DITH4 mode
+ uint32_t DITHERCYB:4; /*!< bit: 0.. 3 Dithering Buffer Cycle Number */
+ uint32_t CCB:20; /*!< bit: 4..23 Channel Compare/Capture Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH4; /*!< Structure used for DITH4 */
+ struct { // DITH5 mode
+ uint32_t DITHERCYB:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */
+ uint32_t CCB:19; /*!< bit: 5..23 Channel Compare/Capture Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH5; /*!< Structure used for DITH5 */
+ struct { // DITH6 mode
+ uint32_t DITHERCYB:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */
+ uint32_t CCB:18; /*!< bit: 6..23 Channel Compare/Capture Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH6; /*!< Structure used for DITH6 */
+ struct {
+ uint32_t CCB:24; /*!< bit: 0..23 Channel Compare/Capture Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_CCB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1801,35 +1801,35 @@ typedef union {
/** \brief TCC hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO TCC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */
- __IO TCC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
- __IO TCC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
- RoReg8 Reserved1[0x2];
- __I TCC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x08 (R/ 32) Synchronization Busy */
- __IO TCC_FCTRLA_Type FCTRLA; /**< \brief Offset: 0x0C (R/W 32) Recoverable Fault A Configuration */
- __IO TCC_FCTRLB_Type FCTRLB; /**< \brief Offset: 0x10 (R/W 32) Recoverable Fault B Configuration */
- __IO TCC_WEXCTRL_Type WEXCTRL; /**< \brief Offset: 0x14 (R/W 32) Waveform Extension Configuration */
- __IO TCC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x18 (R/W 32) Driver Control */
- RoReg8 Reserved2[0x2];
- __IO TCC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x1E (R/W 8) Debug Control */
- RoReg8 Reserved3[0x1];
- __IO TCC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x20 (R/W 32) Event Control */
- __IO TCC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x24 (R/W 32) Interrupt Enable Clear */
- __IO TCC_INTENSET_Type INTENSET; /**< \brief Offset: 0x28 (R/W 32) Interrupt Enable Set */
- __IO TCC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x2C (R/W 32) Interrupt Flag Status and Clear */
- __IO TCC_STATUS_Type STATUS; /**< \brief Offset: 0x30 (R/W 32) Status */
- __IO TCC_COUNT_Type COUNT; /**< \brief Offset: 0x34 (R/W 32) Count */
- __IO TCC_PATT_Type PATT; /**< \brief Offset: 0x38 (R/W 16) Pattern */
- RoReg8 Reserved4[0x2];
- __IO TCC_WAVE_Type WAVE; /**< \brief Offset: 0x3C (R/W 32) Waveform Control */
- __IO TCC_PER_Type PER; /**< \brief Offset: 0x40 (R/W 32) Period */
- __IO TCC_CC_Type CC[4]; /**< \brief Offset: 0x44 (R/W 32) Compare and Capture */
- RoReg8 Reserved5[0x10];
- __IO TCC_PATTB_Type PATTB; /**< \brief Offset: 0x64 (R/W 16) Pattern Buffer */
- RoReg8 Reserved6[0x2];
- __IO TCC_WAVEB_Type WAVEB; /**< \brief Offset: 0x68 (R/W 32) Waveform Control Buffer */
- __IO TCC_PERB_Type PERB; /**< \brief Offset: 0x6C (R/W 32) Period Buffer */
- __IO TCC_CCB_Type CCB[4]; /**< \brief Offset: 0x70 (R/W 32) Compare and Capture Buffer */
+ __IO TCC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */
+ __IO TCC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
+ __IO TCC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
+ RoReg8 Reserved1[0x2];
+ __I TCC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x08 (R/ 32) Synchronization Busy */
+ __IO TCC_FCTRLA_Type FCTRLA; /**< \brief Offset: 0x0C (R/W 32) Recoverable Fault A Configuration */
+ __IO TCC_FCTRLB_Type FCTRLB; /**< \brief Offset: 0x10 (R/W 32) Recoverable Fault B Configuration */
+ __IO TCC_WEXCTRL_Type WEXCTRL; /**< \brief Offset: 0x14 (R/W 32) Waveform Extension Configuration */
+ __IO TCC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x18 (R/W 32) Driver Control */
+ RoReg8 Reserved2[0x2];
+ __IO TCC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x1E (R/W 8) Debug Control */
+ RoReg8 Reserved3[0x1];
+ __IO TCC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x20 (R/W 32) Event Control */
+ __IO TCC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x24 (R/W 32) Interrupt Enable Clear */
+ __IO TCC_INTENSET_Type INTENSET; /**< \brief Offset: 0x28 (R/W 32) Interrupt Enable Set */
+ __IO TCC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x2C (R/W 32) Interrupt Flag Status and Clear */
+ __IO TCC_STATUS_Type STATUS; /**< \brief Offset: 0x30 (R/W 32) Status */
+ __IO TCC_COUNT_Type COUNT; /**< \brief Offset: 0x34 (R/W 32) Count */
+ __IO TCC_PATT_Type PATT; /**< \brief Offset: 0x38 (R/W 16) Pattern */
+ RoReg8 Reserved4[0x2];
+ __IO TCC_WAVE_Type WAVE; /**< \brief Offset: 0x3C (R/W 32) Waveform Control */
+ __IO TCC_PER_Type PER; /**< \brief Offset: 0x40 (R/W 32) Period */
+ __IO TCC_CC_Type CC[4]; /**< \brief Offset: 0x44 (R/W 32) Compare and Capture */
+ RoReg8 Reserved5[0x10];
+ __IO TCC_PATTB_Type PATTB; /**< \brief Offset: 0x64 (R/W 16) Pattern Buffer */
+ RoReg8 Reserved6[0x2];
+ __IO TCC_WAVEB_Type WAVEB; /**< \brief Offset: 0x68 (R/W 32) Waveform Control Buffer */
+ __IO TCC_PERB_Type PERB; /**< \brief Offset: 0x6C (R/W 32) Period Buffer */
+ __IO TCC_CCB_Type CCB[4]; /**< \brief Offset: 0x70 (R/W 32) Compare and Capture Buffer */
} Tcc;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_usb.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_usb.h
index 7586ee5d9a9..8a74359425f 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_usb.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_usb.h
@@ -59,14 +59,14 @@
/* -------- USB_CTRLA : (USB Offset: 0x000) (R/W 8) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t SWRST:1; /*!< bit: 0 Software Reset */
- uint8_t ENABLE:1; /*!< bit: 1 Enable */
- uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby Mode */
- uint8_t :4; /*!< bit: 3.. 6 Reserved */
- uint8_t MODE:1; /*!< bit: 7 Operating Mode */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable */
+ uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby Mode */
+ uint8_t :4; /*!< bit: 3.. 6 Reserved */
+ uint8_t MODE:1; /*!< bit: 7 Operating Mode */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} USB_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -90,12 +90,12 @@ typedef union {
/* -------- USB_SYNCBUSY : (USB Offset: 0x002) (R/ 8) Synchronization Busy -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
- uint8_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} USB_SYNCBUSY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -111,12 +111,12 @@ typedef union {
/* -------- USB_QOSCTRL : (USB Offset: 0x003) (R/W 8) USB Quality Of Service -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t CQOS:2; /*!< bit: 0.. 1 Configuration Quality of Service */
- uint8_t DQOS:2; /*!< bit: 2.. 3 Data Quality of Service */
- uint8_t :4; /*!< bit: 4.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t CQOS:2; /*!< bit: 0.. 1 Configuration Quality of Service */
+ uint8_t DQOS:2; /*!< bit: 2.. 3 Data Quality of Service */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} USB_QOSCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -150,20 +150,20 @@ typedef union {
/* -------- USB_DEVICE_CTRLB : (USB Offset: 0x008) (R/W 16) DEVICE DEVICE Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t DETACH:1; /*!< bit: 0 Detach */
- uint16_t UPRSM:1; /*!< bit: 1 Upstream Resume */
- uint16_t SPDCONF:2; /*!< bit: 2.. 3 Speed Configuration */
- uint16_t NREPLY:1; /*!< bit: 4 No Reply */
- uint16_t TSTJ:1; /*!< bit: 5 Test mode J */
- uint16_t TSTK:1; /*!< bit: 6 Test mode K */
- uint16_t TSTPCKT:1; /*!< bit: 7 Test packet mode */
- uint16_t OPMODE2:1; /*!< bit: 8 Specific Operational Mode */
- uint16_t GNAK:1; /*!< bit: 9 Global NAK */
- uint16_t LPMHDSK:2; /*!< bit: 10..11 Link Power Management Handshake */
- uint16_t :4; /*!< bit: 12..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t DETACH:1; /*!< bit: 0 Detach */
+ uint16_t UPRSM:1; /*!< bit: 1 Upstream Resume */
+ uint16_t SPDCONF:2; /*!< bit: 2.. 3 Speed Configuration */
+ uint16_t NREPLY:1; /*!< bit: 4 No Reply */
+ uint16_t TSTJ:1; /*!< bit: 5 Test mode J */
+ uint16_t TSTK:1; /*!< bit: 6 Test mode K */
+ uint16_t TSTPCKT:1; /*!< bit: 7 Test packet mode */
+ uint16_t OPMODE2:1; /*!< bit: 8 Specific Operational Mode */
+ uint16_t GNAK:1; /*!< bit: 9 Global NAK */
+ uint16_t LPMHDSK:2; /*!< bit: 10..11 Link Power Management Handshake */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} USB_DEVICE_CTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -213,21 +213,21 @@ typedef union {
/* -------- USB_HOST_CTRLB : (USB Offset: 0x008) (R/W 16) HOST HOST Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t :1; /*!< bit: 0 Reserved */
- uint16_t RESUME:1; /*!< bit: 1 Send USB Resume */
- uint16_t SPDCONF:2; /*!< bit: 2.. 3 Speed Configuration for Host */
- uint16_t :1; /*!< bit: 4 Reserved */
- uint16_t TSTJ:1; /*!< bit: 5 Test mode J */
- uint16_t TSTK:1; /*!< bit: 6 Test mode K */
- uint16_t :1; /*!< bit: 7 Reserved */
- uint16_t SOFE:1; /*!< bit: 8 Start of Frame Generation Enable */
- uint16_t BUSRESET:1; /*!< bit: 9 Send USB Reset */
- uint16_t VBUSOK:1; /*!< bit: 10 VBUS is OK */
- uint16_t L1RESUME:1; /*!< bit: 11 Send L1 Resume */
- uint16_t :4; /*!< bit: 12..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t :1; /*!< bit: 0 Reserved */
+ uint16_t RESUME:1; /*!< bit: 1 Send USB Resume */
+ uint16_t SPDCONF:2; /*!< bit: 2.. 3 Speed Configuration for Host */
+ uint16_t :1; /*!< bit: 4 Reserved */
+ uint16_t TSTJ:1; /*!< bit: 5 Test mode J */
+ uint16_t TSTK:1; /*!< bit: 6 Test mode K */
+ uint16_t :1; /*!< bit: 7 Reserved */
+ uint16_t SOFE:1; /*!< bit: 8 Start of Frame Generation Enable */
+ uint16_t BUSRESET:1; /*!< bit: 9 Send USB Reset */
+ uint16_t VBUSOK:1; /*!< bit: 10 VBUS is OK */
+ uint16_t L1RESUME:1; /*!< bit: 11 Send L1 Resume */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} USB_HOST_CTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -260,11 +260,11 @@ typedef union {
/* -------- USB_DEVICE_DADD : (USB Offset: 0x00A) (R/W 8) DEVICE DEVICE Device Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DADD:7; /*!< bit: 0.. 6 Device Address */
- uint8_t ADDEN:1; /*!< bit: 7 Device Address Enable */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DADD:7; /*!< bit: 0.. 6 Device Address */
+ uint8_t ADDEN:1; /*!< bit: 7 Device Address Enable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} USB_DEVICE_DADD_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -281,12 +281,12 @@ typedef union {
/* -------- USB_HOST_HSOFC : (USB Offset: 0x00A) (R/W 8) HOST HOST Host Start Of Frame Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t FLENC:4; /*!< bit: 0.. 3 Frame Length Control */
- uint8_t :3; /*!< bit: 4.. 6 Reserved */
- uint8_t FLENCE:1; /*!< bit: 7 Frame Length Control Enable */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t FLENC:4; /*!< bit: 0.. 3 Frame Length Control */
+ uint8_t :3; /*!< bit: 4.. 6 Reserved */
+ uint8_t FLENCE:1; /*!< bit: 7 Frame Length Control Enable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} USB_HOST_HSOFC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -303,13 +303,13 @@ typedef union {
/* -------- USB_DEVICE_STATUS : (USB Offset: 0x00C) (R/ 8) DEVICE DEVICE Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t :2; /*!< bit: 0.. 1 Reserved */
- uint8_t SPEED:2; /*!< bit: 2.. 3 Speed Status */
- uint8_t :2; /*!< bit: 4.. 5 Reserved */
- uint8_t LINESTATE:2; /*!< bit: 6.. 7 USB Line State Status */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t :2; /*!< bit: 0.. 1 Reserved */
+ uint8_t SPEED:2; /*!< bit: 2.. 3 Speed Status */
+ uint8_t :2; /*!< bit: 4.. 5 Reserved */
+ uint8_t LINESTATE:2; /*!< bit: 6.. 7 USB Line State Status */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} USB_DEVICE_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -339,13 +339,13 @@ typedef union {
/* -------- USB_HOST_STATUS : (USB Offset: 0x00C) (R/W 8) HOST HOST Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t :2; /*!< bit: 0.. 1 Reserved */
- uint8_t SPEED:2; /*!< bit: 2.. 3 Speed Status */
- uint8_t :2; /*!< bit: 4.. 5 Reserved */
- uint8_t LINESTATE:2; /*!< bit: 6.. 7 USB Line State Status */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t :2; /*!< bit: 0.. 1 Reserved */
+ uint8_t SPEED:2; /*!< bit: 2.. 3 Speed Status */
+ uint8_t :2; /*!< bit: 4.. 5 Reserved */
+ uint8_t LINESTATE:2; /*!< bit: 6.. 7 USB Line State Status */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} USB_HOST_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -363,11 +363,11 @@ typedef union {
/* -------- USB_FSMSTATUS : (USB Offset: 0x00D) (R/ 8) Finite State Machine Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t FSMSTATE:6; /*!< bit: 0.. 5 Fine State Machine Status */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t FSMSTATE:6; /*!< bit: 0.. 5 Fine State Machine Status */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} USB_FSMSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -396,13 +396,13 @@ typedef union {
/* -------- USB_DEVICE_FNUM : (USB Offset: 0x010) (R/ 16) DEVICE DEVICE Device Frame Number -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t MFNUM:3; /*!< bit: 0.. 2 Micro Frame Number */
- uint16_t FNUM:11; /*!< bit: 3..13 Frame Number */
- uint16_t :1; /*!< bit: 14 Reserved */
- uint16_t FNCERR:1; /*!< bit: 15 Frame Number CRC Error */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t MFNUM:3; /*!< bit: 0.. 2 Micro Frame Number */
+ uint16_t FNUM:11; /*!< bit: 3..13 Frame Number */
+ uint16_t :1; /*!< bit: 14 Reserved */
+ uint16_t FNCERR:1; /*!< bit: 15 Frame Number CRC Error */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} USB_DEVICE_FNUM_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -422,12 +422,12 @@ typedef union {
/* -------- USB_HOST_FNUM : (USB Offset: 0x010) (R/W 16) HOST HOST Host Frame Number -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t MFNUM:3; /*!< bit: 0.. 2 Micro Frame Number */
- uint16_t FNUM:11; /*!< bit: 3..13 Frame Number */
- uint16_t :2; /*!< bit: 14..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t MFNUM:3; /*!< bit: 0.. 2 Micro Frame Number */
+ uint16_t FNUM:11; /*!< bit: 3..13 Frame Number */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} USB_HOST_FNUM_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -445,10 +445,10 @@ typedef union {
/* -------- USB_HOST_FLENHIGH : (USB Offset: 0x012) (R/ 8) HOST HOST Host Frame Length -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t FLENHIGH:8; /*!< bit: 0.. 7 Frame Length */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t FLENHIGH:8; /*!< bit: 0.. 7 Frame Length */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} USB_HOST_FLENHIGH_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -463,20 +463,20 @@ typedef union {
/* -------- USB_DEVICE_INTENCLR : (USB Offset: 0x014) (R/W 16) DEVICE DEVICE Device Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t SUSPEND:1; /*!< bit: 0 Suspend Interrupt Enable */
- uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame Interrupt Enable in High Speed Mode */
- uint16_t SOF:1; /*!< bit: 2 Start Of Frame Interrupt Enable */
- uint16_t EORST:1; /*!< bit: 3 End of Reset Interrupt Enable */
- uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */
- uint16_t EORSM:1; /*!< bit: 5 End Of Resume Interrupt Enable */
- uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume Interrupt Enable */
- uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */
- uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet Interrupt Enable */
- uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend Interrupt Enable */
- uint16_t :6; /*!< bit: 10..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t SUSPEND:1; /*!< bit: 0 Suspend Interrupt Enable */
+ uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame Interrupt Enable in High Speed Mode */
+ uint16_t SOF:1; /*!< bit: 2 Start Of Frame Interrupt Enable */
+ uint16_t EORST:1; /*!< bit: 3 End of Reset Interrupt Enable */
+ uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */
+ uint16_t EORSM:1; /*!< bit: 5 End Of Resume Interrupt Enable */
+ uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume Interrupt Enable */
+ uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */
+ uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet Interrupt Enable */
+ uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend Interrupt Enable */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} USB_DEVICE_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -508,19 +508,19 @@ typedef union {
/* -------- USB_HOST_INTENCLR : (USB Offset: 0x014) (R/W 16) HOST HOST Host Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t :2; /*!< bit: 0.. 1 Reserved */
- uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame Interrupt Disable */
- uint16_t RST:1; /*!< bit: 3 BUS Reset Interrupt Disable */
- uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Disable */
- uint16_t DNRSM:1; /*!< bit: 5 DownStream to Device Interrupt Disable */
- uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume from Device Interrupt Disable */
- uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Disable */
- uint16_t DCONN:1; /*!< bit: 8 Device Connection Interrupt Disable */
- uint16_t DDISC:1; /*!< bit: 9 Device Disconnection Interrupt Disable */
- uint16_t :6; /*!< bit: 10..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t :2; /*!< bit: 0.. 1 Reserved */
+ uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame Interrupt Disable */
+ uint16_t RST:1; /*!< bit: 3 BUS Reset Interrupt Disable */
+ uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Disable */
+ uint16_t DNRSM:1; /*!< bit: 5 DownStream to Device Interrupt Disable */
+ uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume from Device Interrupt Disable */
+ uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Disable */
+ uint16_t DCONN:1; /*!< bit: 8 Device Connection Interrupt Disable */
+ uint16_t DDISC:1; /*!< bit: 9 Device Disconnection Interrupt Disable */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} USB_HOST_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -548,20 +548,20 @@ typedef union {
/* -------- USB_DEVICE_INTENSET : (USB Offset: 0x018) (R/W 16) DEVICE DEVICE Device Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t SUSPEND:1; /*!< bit: 0 Suspend Interrupt Enable */
- uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame Interrupt Enable in High Speed Mode */
- uint16_t SOF:1; /*!< bit: 2 Start Of Frame Interrupt Enable */
- uint16_t EORST:1; /*!< bit: 3 End of Reset Interrupt Enable */
- uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */
- uint16_t EORSM:1; /*!< bit: 5 End Of Resume Interrupt Enable */
- uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume Interrupt Enable */
- uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */
- uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet Interrupt Enable */
- uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend Interrupt Enable */
- uint16_t :6; /*!< bit: 10..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t SUSPEND:1; /*!< bit: 0 Suspend Interrupt Enable */
+ uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame Interrupt Enable in High Speed Mode */
+ uint16_t SOF:1; /*!< bit: 2 Start Of Frame Interrupt Enable */
+ uint16_t EORST:1; /*!< bit: 3 End of Reset Interrupt Enable */
+ uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */
+ uint16_t EORSM:1; /*!< bit: 5 End Of Resume Interrupt Enable */
+ uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume Interrupt Enable */
+ uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */
+ uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet Interrupt Enable */
+ uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend Interrupt Enable */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} USB_DEVICE_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -593,19 +593,19 @@ typedef union {
/* -------- USB_HOST_INTENSET : (USB Offset: 0x018) (R/W 16) HOST HOST Host Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t :2; /*!< bit: 0.. 1 Reserved */
- uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame Interrupt Enable */
- uint16_t RST:1; /*!< bit: 3 Bus Reset Interrupt Enable */
- uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */
- uint16_t DNRSM:1; /*!< bit: 5 DownStream to the Device Interrupt Enable */
- uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume fromthe device Interrupt Enable */
- uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */
- uint16_t DCONN:1; /*!< bit: 8 Link Power Management Interrupt Enable */
- uint16_t DDISC:1; /*!< bit: 9 Device Disconnection Interrupt Enable */
- uint16_t :6; /*!< bit: 10..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t :2; /*!< bit: 0.. 1 Reserved */
+ uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame Interrupt Enable */
+ uint16_t RST:1; /*!< bit: 3 Bus Reset Interrupt Enable */
+ uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */
+ uint16_t DNRSM:1; /*!< bit: 5 DownStream to the Device Interrupt Enable */
+ uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume fromthe device Interrupt Enable */
+ uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */
+ uint16_t DCONN:1; /*!< bit: 8 Link Power Management Interrupt Enable */
+ uint16_t DDISC:1; /*!< bit: 9 Device Disconnection Interrupt Enable */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} USB_HOST_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -633,20 +633,20 @@ typedef union {
/* -------- USB_DEVICE_INTFLAG : (USB Offset: 0x01C) (R/W 16) DEVICE DEVICE Device Interrupt Flag -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t SUSPEND:1; /*!< bit: 0 Suspend */
- uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame in High Speed Mode */
- uint16_t SOF:1; /*!< bit: 2 Start Of Frame */
- uint16_t EORST:1; /*!< bit: 3 End of Reset */
- uint16_t WAKEUP:1; /*!< bit: 4 Wake Up */
- uint16_t EORSM:1; /*!< bit: 5 End Of Resume */
- uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume */
- uint16_t RAMACER:1; /*!< bit: 7 Ram Access */
- uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet */
- uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend */
- uint16_t :6; /*!< bit: 10..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t SUSPEND:1; /*!< bit: 0 Suspend */
+ uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame in High Speed Mode */
+ uint16_t SOF:1; /*!< bit: 2 Start Of Frame */
+ uint16_t EORST:1; /*!< bit: 3 End of Reset */
+ uint16_t WAKEUP:1; /*!< bit: 4 Wake Up */
+ uint16_t EORSM:1; /*!< bit: 5 End Of Resume */
+ uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume */
+ uint16_t RAMACER:1; /*!< bit: 7 Ram Access */
+ uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet */
+ uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} USB_DEVICE_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -678,19 +678,19 @@ typedef union {
/* -------- USB_HOST_INTFLAG : (USB Offset: 0x01C) (R/W 16) HOST HOST Host Interrupt Flag -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t :2; /*!< bit: 0.. 1 Reserved */
- uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame */
- uint16_t RST:1; /*!< bit: 3 Bus Reset */
- uint16_t WAKEUP:1; /*!< bit: 4 Wake Up */
- uint16_t DNRSM:1; /*!< bit: 5 Downstream */
- uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume from the Device */
- uint16_t RAMACER:1; /*!< bit: 7 Ram Access */
- uint16_t DCONN:1; /*!< bit: 8 Device Connection */
- uint16_t DDISC:1; /*!< bit: 9 Device Disconnection */
- uint16_t :6; /*!< bit: 10..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t :2; /*!< bit: 0.. 1 Reserved */
+ uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame */
+ uint16_t RST:1; /*!< bit: 3 Bus Reset */
+ uint16_t WAKEUP:1; /*!< bit: 4 Wake Up */
+ uint16_t DNRSM:1; /*!< bit: 5 Downstream */
+ uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume from the Device */
+ uint16_t RAMACER:1; /*!< bit: 7 Ram Access */
+ uint16_t DCONN:1; /*!< bit: 8 Device Connection */
+ uint16_t DDISC:1; /*!< bit: 9 Device Disconnection */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} USB_HOST_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -718,22 +718,22 @@ typedef union {
/* -------- USB_DEVICE_EPINTSMRY : (USB Offset: 0x020) (R/ 16) DEVICE DEVICE End Point Interrupt Summary -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t EPINT0:1; /*!< bit: 0 End Point 0 Interrupt */
- uint16_t EPINT1:1; /*!< bit: 1 End Point 1 Interrupt */
- uint16_t EPINT2:1; /*!< bit: 2 End Point 2 Interrupt */
- uint16_t EPINT3:1; /*!< bit: 3 End Point 3 Interrupt */
- uint16_t EPINT4:1; /*!< bit: 4 End Point 4 Interrupt */
- uint16_t EPINT5:1; /*!< bit: 5 End Point 5 Interrupt */
- uint16_t EPINT6:1; /*!< bit: 6 End Point 6 Interrupt */
- uint16_t EPINT7:1; /*!< bit: 7 End Point 7 Interrupt */
- uint16_t :8; /*!< bit: 8..15 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint16_t EPINT:8; /*!< bit: 0.. 7 End Point x Interrupt */
- uint16_t :8; /*!< bit: 8..15 Reserved */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t EPINT0:1; /*!< bit: 0 End Point 0 Interrupt */
+ uint16_t EPINT1:1; /*!< bit: 1 End Point 1 Interrupt */
+ uint16_t EPINT2:1; /*!< bit: 2 End Point 2 Interrupt */
+ uint16_t EPINT3:1; /*!< bit: 3 End Point 3 Interrupt */
+ uint16_t EPINT4:1; /*!< bit: 4 End Point 4 Interrupt */
+ uint16_t EPINT5:1; /*!< bit: 5 End Point 5 Interrupt */
+ uint16_t EPINT6:1; /*!< bit: 6 End Point 6 Interrupt */
+ uint16_t EPINT7:1; /*!< bit: 7 End Point 7 Interrupt */
+ uint16_t :8; /*!< bit: 8..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t EPINT:8; /*!< bit: 0.. 7 End Point x Interrupt */
+ uint16_t :8; /*!< bit: 8..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
} USB_DEVICE_EPINTSMRY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -764,22 +764,22 @@ typedef union {
/* -------- USB_HOST_PINTSMRY : (USB Offset: 0x020) (R/ 16) HOST HOST Pipe Interrupt Summary -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t EPINT0:1; /*!< bit: 0 Pipe 0 Interrupt */
- uint16_t EPINT1:1; /*!< bit: 1 Pipe 1 Interrupt */
- uint16_t EPINT2:1; /*!< bit: 2 Pipe 2 Interrupt */
- uint16_t EPINT3:1; /*!< bit: 3 Pipe 3 Interrupt */
- uint16_t EPINT4:1; /*!< bit: 4 Pipe 4 Interrupt */
- uint16_t EPINT5:1; /*!< bit: 5 Pipe 5 Interrupt */
- uint16_t EPINT6:1; /*!< bit: 6 Pipe 6 Interrupt */
- uint16_t EPINT7:1; /*!< bit: 7 Pipe 7 Interrupt */
- uint16_t :8; /*!< bit: 8..15 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint16_t EPINT:8; /*!< bit: 0.. 7 Pipe x Interrupt */
- uint16_t :8; /*!< bit: 8..15 Reserved */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t EPINT0:1; /*!< bit: 0 Pipe 0 Interrupt */
+ uint16_t EPINT1:1; /*!< bit: 1 Pipe 1 Interrupt */
+ uint16_t EPINT2:1; /*!< bit: 2 Pipe 2 Interrupt */
+ uint16_t EPINT3:1; /*!< bit: 3 Pipe 3 Interrupt */
+ uint16_t EPINT4:1; /*!< bit: 4 Pipe 4 Interrupt */
+ uint16_t EPINT5:1; /*!< bit: 5 Pipe 5 Interrupt */
+ uint16_t EPINT6:1; /*!< bit: 6 Pipe 6 Interrupt */
+ uint16_t EPINT7:1; /*!< bit: 7 Pipe 7 Interrupt */
+ uint16_t :8; /*!< bit: 8..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t EPINT:8; /*!< bit: 0.. 7 Pipe x Interrupt */
+ uint16_t :8; /*!< bit: 8..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
} USB_HOST_PINTSMRY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -810,10 +810,10 @@ typedef union {
/* -------- USB_DESCADD : (USB Offset: 0x024) (R/W 32) Descriptor Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t DESCADD:32; /*!< bit: 0..31 Descriptor Address Value */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t DESCADD:32; /*!< bit: 0..31 Descriptor Address Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} USB_DESCADD_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -828,15 +828,15 @@ typedef union {
/* -------- USB_PADCAL : (USB Offset: 0x028) (R/W 16) USB PAD Calibration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t TRANSP:5; /*!< bit: 0.. 4 USB Pad Transp calibration */
- uint16_t :1; /*!< bit: 5 Reserved */
- uint16_t TRANSN:5; /*!< bit: 6..10 USB Pad Transn calibration */
- uint16_t :1; /*!< bit: 11 Reserved */
- uint16_t TRIM:3; /*!< bit: 12..14 USB Pad Trim calibration */
- uint16_t :1; /*!< bit: 15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t TRANSP:5; /*!< bit: 0.. 4 USB Pad Transp calibration */
+ uint16_t :1; /*!< bit: 5 Reserved */
+ uint16_t TRANSN:5; /*!< bit: 6..10 USB Pad Transn calibration */
+ uint16_t :1; /*!< bit: 11 Reserved */
+ uint16_t TRIM:3; /*!< bit: 12..14 USB Pad Trim calibration */
+ uint16_t :1; /*!< bit: 15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} USB_PADCAL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -857,13 +857,13 @@ typedef union {
/* -------- USB_DEVICE_EPCFG : (USB Offset: 0x100) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t EPTYPE0:3; /*!< bit: 0.. 2 End Point Type0 */
- uint8_t :1; /*!< bit: 3 Reserved */
- uint8_t EPTYPE1:3; /*!< bit: 4.. 6 End Point Type1 */
- uint8_t NYETDIS:1; /*!< bit: 7 NYET Token Disable */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t EPTYPE0:3; /*!< bit: 0.. 2 End Point Type0 */
+ uint8_t :1; /*!< bit: 3 Reserved */
+ uint8_t EPTYPE1:3; /*!< bit: 4.. 6 End Point Type1 */
+ uint8_t NYETDIS:1; /*!< bit: 7 NYET Token Disable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} USB_DEVICE_EPCFG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -883,13 +883,13 @@ typedef union {
/* -------- USB_HOST_PCFG : (USB Offset: 0x100) (R/W 8) HOST HOST_PIPE End Point Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t PTOKEN:2; /*!< bit: 0.. 1 Pipe Token */
- uint8_t BK:1; /*!< bit: 2 Pipe Bank */
- uint8_t PTYPE:3; /*!< bit: 3.. 5 Pipe Type */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t PTOKEN:2; /*!< bit: 0.. 1 Pipe Token */
+ uint8_t BK:1; /*!< bit: 2 Pipe Bank */
+ uint8_t PTYPE:3; /*!< bit: 3.. 5 Pipe Type */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} USB_HOST_PCFG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -909,10 +909,10 @@ typedef union {
/* -------- USB_HOST_BINTERVAL : (USB Offset: 0x103) (R/W 8) HOST HOST_PIPE Bus Access Period of Pipe -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t BITINTERVAL:8; /*!< bit: 0.. 7 Bit Interval */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t BITINTERVAL:8; /*!< bit: 0.. 7 Bit Interval */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} USB_HOST_BINTERVAL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -927,22 +927,22 @@ typedef union {
/* -------- USB_DEVICE_EPSTATUSCLR : (USB Offset: 0x104) ( /W 8) DEVICE DEVICE_ENDPOINT End Point Pipe Status Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle OUT Clear */
- uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle IN Clear */
- uint8_t CURBK:1; /*!< bit: 2 Curren Bank Clear */
- uint8_t :1; /*!< bit: 3 Reserved */
- uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request Clear */
- uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request Clear */
- uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Clear */
- uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Clear */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t :4; /*!< bit: 0.. 3 Reserved */
- uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request Clear */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle OUT Clear */
+ uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle IN Clear */
+ uint8_t CURBK:1; /*!< bit: 2 Curren Bank Clear */
+ uint8_t :1; /*!< bit: 3 Reserved */
+ uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request Clear */
+ uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request Clear */
+ uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Clear */
+ uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Clear */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t :4; /*!< bit: 0.. 3 Reserved */
+ uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request Clear */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} USB_DEVICE_EPSTATUSCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -971,17 +971,17 @@ typedef union {
/* -------- USB_HOST_PSTATUSCLR : (USB Offset: 0x104) ( /W 8) HOST HOST_PIPE End Point Pipe Status Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DTGL:1; /*!< bit: 0 Data Toggle clear */
- uint8_t :1; /*!< bit: 1 Reserved */
- uint8_t CURBK:1; /*!< bit: 2 Curren Bank clear */
- uint8_t :1; /*!< bit: 3 Reserved */
- uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze Clear */
- uint8_t :1; /*!< bit: 5 Reserved */
- uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Clear */
- uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Clear */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DTGL:1; /*!< bit: 0 Data Toggle clear */
+ uint8_t :1; /*!< bit: 1 Reserved */
+ uint8_t CURBK:1; /*!< bit: 2 Curren Bank clear */
+ uint8_t :1; /*!< bit: 3 Reserved */
+ uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze Clear */
+ uint8_t :1; /*!< bit: 5 Reserved */
+ uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Clear */
+ uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Clear */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} USB_HOST_PSTATUSCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1003,22 +1003,22 @@ typedef union {
/* -------- USB_DEVICE_EPSTATUSSET : (USB Offset: 0x105) ( /W 8) DEVICE DEVICE_ENDPOINT End Point Pipe Status Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle OUT Set */
- uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle IN Set */
- uint8_t CURBK:1; /*!< bit: 2 Current Bank Set */
- uint8_t :1; /*!< bit: 3 Reserved */
- uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request Set */
- uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request Set */
- uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Set */
- uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Set */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t :4; /*!< bit: 0.. 3 Reserved */
- uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request Set */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle OUT Set */
+ uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle IN Set */
+ uint8_t CURBK:1; /*!< bit: 2 Current Bank Set */
+ uint8_t :1; /*!< bit: 3 Reserved */
+ uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request Set */
+ uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request Set */
+ uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Set */
+ uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Set */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t :4; /*!< bit: 0.. 3 Reserved */
+ uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request Set */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} USB_DEVICE_EPSTATUSSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1047,17 +1047,17 @@ typedef union {
/* -------- USB_HOST_PSTATUSSET : (USB Offset: 0x105) ( /W 8) HOST HOST_PIPE End Point Pipe Status Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DTGL:1; /*!< bit: 0 Data Toggle Set */
- uint8_t :1; /*!< bit: 1 Reserved */
- uint8_t CURBK:1; /*!< bit: 2 Current Bank Set */
- uint8_t :1; /*!< bit: 3 Reserved */
- uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze Set */
- uint8_t :1; /*!< bit: 5 Reserved */
- uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Set */
- uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Set */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DTGL:1; /*!< bit: 0 Data Toggle Set */
+ uint8_t :1; /*!< bit: 1 Reserved */
+ uint8_t CURBK:1; /*!< bit: 2 Current Bank Set */
+ uint8_t :1; /*!< bit: 3 Reserved */
+ uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze Set */
+ uint8_t :1; /*!< bit: 5 Reserved */
+ uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Set */
+ uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Set */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} USB_HOST_PSTATUSSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1079,22 +1079,22 @@ typedef union {
/* -------- USB_DEVICE_EPSTATUS : (USB Offset: 0x106) (R/ 8) DEVICE DEVICE_ENDPOINT End Point Pipe Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle Out */
- uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle In */
- uint8_t CURBK:1; /*!< bit: 2 Current Bank */
- uint8_t :1; /*!< bit: 3 Reserved */
- uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request */
- uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request */
- uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 ready */
- uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 ready */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t :4; /*!< bit: 0.. 3 Reserved */
- uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle Out */
+ uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle In */
+ uint8_t CURBK:1; /*!< bit: 2 Current Bank */
+ uint8_t :1; /*!< bit: 3 Reserved */
+ uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request */
+ uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request */
+ uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 ready */
+ uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 ready */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t :4; /*!< bit: 0.. 3 Reserved */
+ uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} USB_DEVICE_EPSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1123,17 +1123,17 @@ typedef union {
/* -------- USB_HOST_PSTATUS : (USB Offset: 0x106) (R/ 8) HOST HOST_PIPE End Point Pipe Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DTGL:1; /*!< bit: 0 Data Toggle */
- uint8_t :1; /*!< bit: 1 Reserved */
- uint8_t CURBK:1; /*!< bit: 2 Current Bank */
- uint8_t :1; /*!< bit: 3 Reserved */
- uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze */
- uint8_t :1; /*!< bit: 5 Reserved */
- uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 ready */
- uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 ready */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DTGL:1; /*!< bit: 0 Data Toggle */
+ uint8_t :1; /*!< bit: 1 Reserved */
+ uint8_t CURBK:1; /*!< bit: 2 Current Bank */
+ uint8_t :1; /*!< bit: 3 Reserved */
+ uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze */
+ uint8_t :1; /*!< bit: 5 Reserved */
+ uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 ready */
+ uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 ready */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} USB_HOST_PSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1155,24 +1155,24 @@ typedef union {
/* -------- USB_DEVICE_EPINTFLAG : (USB Offset: 0x107) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Interrupt Flag -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 */
- uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 */
- uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 */
- uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 */
- uint8_t RXSTP:1; /*!< bit: 4 Received Setup */
- uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/out */
- uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/out */
- uint8_t :1; /*!< bit: 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x */
- uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x */
- uint8_t :1; /*!< bit: 4 Reserved */
- uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/out */
- uint8_t :1; /*!< bit: 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 */
+ uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 */
+ uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 */
+ uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 */
+ uint8_t RXSTP:1; /*!< bit: 4 Received Setup */
+ uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/out */
+ uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/out */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x */
+ uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x */
+ uint8_t :1; /*!< bit: 4 Reserved */
+ uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/out */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} USB_DEVICE_EPINTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1207,20 +1207,20 @@ typedef union {
/* -------- USB_HOST_PINTFLAG : (USB Offset: 0x107) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Flag */
- uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Flag */
- uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Flag */
- uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Flag */
- uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Flag */
- uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Flag */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Flag */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Flag */
+ uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Flag */
+ uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Flag */
+ uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Flag */
+ uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Flag */
+ uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Flag */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Flag */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} USB_HOST_PINTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1247,24 +1247,24 @@ typedef union {
/* -------- USB_DEVICE_EPINTENCLR : (USB Offset: 0x108) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Interrupt Clear Flag -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Disable */
- uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Disable */
- uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 Interrupt Disable */
- uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 Interrupt Disable */
- uint8_t RXSTP:1; /*!< bit: 4 Received Setup Interrupt Disable */
- uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/Out Interrupt Disable */
- uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/Out Interrupt Disable */
- uint8_t :1; /*!< bit: 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Disable */
- uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x Interrupt Disable */
- uint8_t :1; /*!< bit: 4 Reserved */
- uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/Out Interrupt Disable */
- uint8_t :1; /*!< bit: 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Disable */
+ uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Disable */
+ uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 Interrupt Disable */
+ uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 Interrupt Disable */
+ uint8_t RXSTP:1; /*!< bit: 4 Received Setup Interrupt Disable */
+ uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/Out Interrupt Disable */
+ uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/Out Interrupt Disable */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Disable */
+ uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x Interrupt Disable */
+ uint8_t :1; /*!< bit: 4 Reserved */
+ uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/Out Interrupt Disable */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} USB_DEVICE_EPINTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1299,20 +1299,20 @@ typedef union {
/* -------- USB_HOST_PINTENCLR : (USB Offset: 0x108) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Disable */
- uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Disable */
- uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Disable */
- uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Disable */
- uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Disable */
- uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Disable */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Disable */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Disable */
+ uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Disable */
+ uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Disable */
+ uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Disable */
+ uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Disable */
+ uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Disable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Disable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} USB_HOST_PINTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1339,24 +1339,24 @@ typedef union {
/* -------- USB_DEVICE_EPINTENSET : (USB Offset: 0x109) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Interrupt Set Flag -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Enable */
- uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Enable */
- uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 Interrupt Enable */
- uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 Interrupt Enable */
- uint8_t RXSTP:1; /*!< bit: 4 Received Setup Interrupt Enable */
- uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/out Interrupt enable */
- uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/out Interrupt enable */
- uint8_t :1; /*!< bit: 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Enable */
- uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x Interrupt Enable */
- uint8_t :1; /*!< bit: 4 Reserved */
- uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/out Interrupt enable */
- uint8_t :1; /*!< bit: 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Enable */
+ uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Enable */
+ uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 Interrupt Enable */
+ uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 Interrupt Enable */
+ uint8_t RXSTP:1; /*!< bit: 4 Received Setup Interrupt Enable */
+ uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/out Interrupt enable */
+ uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/out Interrupt enable */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Enable */
+ uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x Interrupt Enable */
+ uint8_t :1; /*!< bit: 4 Reserved */
+ uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/out Interrupt enable */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} USB_DEVICE_EPINTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1391,20 +1391,20 @@ typedef union {
/* -------- USB_HOST_PINTENSET : (USB Offset: 0x109) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Enable */
- uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Enable */
- uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Enable */
- uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Enable */
- uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Enable */
- uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Enable */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Enable */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Enable */
+ uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Enable */
+ uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Enable */
+ uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Enable */
+ uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Enable */
+ uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Enable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Enable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} USB_HOST_PINTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1431,10 +1431,10 @@ typedef union {
/* -------- USB_DEVICE_ADDR : (USB Offset: 0x000) (R/W 32) DEVICE DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t ADDR:32; /*!< bit: 0..31 Adress of data buffer */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t ADDR:32; /*!< bit: 0..31 Adress of data buffer */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} USB_DEVICE_ADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1448,10 +1448,10 @@ typedef union {
/* -------- USB_HOST_ADDR : (USB Offset: 0x000) (R/W 32) HOST HOST_DESC_BANK Host Bank, Adress of Data Buffer -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t ADDR:32; /*!< bit: 0..31 Adress of data buffer */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t ADDR:32; /*!< bit: 0..31 Adress of data buffer */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} USB_HOST_ADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1465,13 +1465,13 @@ typedef union {
/* -------- USB_DEVICE_PCKSIZE : (USB Offset: 0x004) (R/W 32) DEVICE DEVICE_DESC_BANK Endpoint Bank, Packet Size -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t BYTE_COUNT:14; /*!< bit: 0..13 Byte Count */
- uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27 Multi Packet In or Out size */
- uint32_t SIZE:3; /*!< bit: 28..30 Enpoint size */
- uint32_t AUTO_ZLP:1; /*!< bit: 31 Automatic Zero Length Packet */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t BYTE_COUNT:14; /*!< bit: 0..13 Byte Count */
+ uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27 Multi Packet In or Out size */
+ uint32_t SIZE:3; /*!< bit: 28..30 Enpoint size */
+ uint32_t AUTO_ZLP:1; /*!< bit: 31 Automatic Zero Length Packet */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} USB_DEVICE_PCKSIZE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1493,13 +1493,13 @@ typedef union {
/* -------- USB_HOST_PCKSIZE : (USB Offset: 0x004) (R/W 32) HOST HOST_DESC_BANK Host Bank, Packet Size -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t BYTE_COUNT:14; /*!< bit: 0..13 Byte Count */
- uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27 Multi Packet In or Out size */
- uint32_t SIZE:3; /*!< bit: 28..30 Pipe size */
- uint32_t AUTO_ZLP:1; /*!< bit: 31 Automatic Zero Length Packet */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t BYTE_COUNT:14; /*!< bit: 0..13 Byte Count */
+ uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27 Multi Packet In or Out size */
+ uint32_t SIZE:3; /*!< bit: 28..30 Pipe size */
+ uint32_t AUTO_ZLP:1; /*!< bit: 31 Automatic Zero Length Packet */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} USB_HOST_PCKSIZE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1521,12 +1521,12 @@ typedef union {
/* -------- USB_DEVICE_EXTREG : (USB Offset: 0x008) (R/W 16) DEVICE DEVICE_DESC_BANK Endpoint Bank, Extended -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t SUBPID:4; /*!< bit: 0.. 3 SUBPID field send with extended token */
- uint16_t VARIABLE:11; /*!< bit: 4..14 Variable field send with extended token */
- uint16_t :1; /*!< bit: 15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t SUBPID:4; /*!< bit: 0.. 3 SUBPID field send with extended token */
+ uint16_t VARIABLE:11; /*!< bit: 4..14 Variable field send with extended token */
+ uint16_t :1; /*!< bit: 15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} USB_DEVICE_EXTREG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1543,12 +1543,12 @@ typedef union {
/* -------- USB_HOST_EXTREG : (USB Offset: 0x008) (R/W 16) HOST HOST_DESC_BANK Host Bank, Extended -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t SUBPID:4; /*!< bit: 0.. 3 SUBPID field send with extended token */
- uint16_t VARIABLE:11; /*!< bit: 4..14 Variable field send with extended token */
- uint16_t :1; /*!< bit: 15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t SUBPID:4; /*!< bit: 0.. 3 SUBPID field send with extended token */
+ uint16_t VARIABLE:11; /*!< bit: 4..14 Variable field send with extended token */
+ uint16_t :1; /*!< bit: 15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} USB_HOST_EXTREG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1565,12 +1565,12 @@ typedef union {
/* -------- USB_DEVICE_STATUS_BK : (USB Offset: 0x00A) (R/W 8) DEVICE DEVICE_DESC_BANK Enpoint Bank, Status of Bank -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t CRCERR:1; /*!< bit: 0 CRC Error Status */
- uint8_t ERRORFLOW:1; /*!< bit: 1 Error Flow Status */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t CRCERR:1; /*!< bit: 0 CRC Error Status */
+ uint8_t ERRORFLOW:1; /*!< bit: 1 Error Flow Status */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} USB_DEVICE_STATUS_BK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1585,12 +1585,12 @@ typedef union {
/* -------- USB_HOST_STATUS_BK : (USB Offset: 0x00A) (R/W 8) HOST HOST_DESC_BANK Host Bank, Status of Bank -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t CRCERR:1; /*!< bit: 0 CRC Error Status */
- uint8_t ERRORFLOW:1; /*!< bit: 1 Error Flow Status */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t CRCERR:1; /*!< bit: 0 CRC Error Status */
+ uint8_t ERRORFLOW:1; /*!< bit: 1 Error Flow Status */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} USB_HOST_STATUS_BK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1605,13 +1605,13 @@ typedef union {
/* -------- USB_HOST_CTRL_PIPE : (USB Offset: 0x00C) (R/W 16) HOST HOST_DESC_BANK Host Bank, Host Control Pipe -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t PDADDR:7; /*!< bit: 0.. 6 Pipe Device Adress */
- uint16_t :1; /*!< bit: 7 Reserved */
- uint16_t PEPNUM:4; /*!< bit: 8..11 Pipe Endpoint Number */
- uint16_t PERMAX:4; /*!< bit: 12..15 Pipe Error Max Number */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t PDADDR:7; /*!< bit: 0.. 6 Pipe Device Adress */
+ uint16_t :1; /*!< bit: 7 Reserved */
+ uint16_t PEPNUM:4; /*!< bit: 8..11 Pipe Endpoint Number */
+ uint16_t PERMAX:4; /*!< bit: 12..15 Pipe Error Max Number */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} USB_HOST_CTRL_PIPE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1632,16 +1632,16 @@ typedef union {
/* -------- USB_HOST_STATUS_PIPE : (USB Offset: 0x00E) (R/W 16) HOST HOST_DESC_BANK Host Bank, Host Status Pipe -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t DTGLER:1; /*!< bit: 0 Data Toggle Error */
- uint16_t DAPIDER:1; /*!< bit: 1 Data PID Error */
- uint16_t PIDER:1; /*!< bit: 2 PID Error */
- uint16_t TOUTER:1; /*!< bit: 3 Time Out Error */
- uint16_t CRC16ER:1; /*!< bit: 4 CRC16 Error */
- uint16_t ERCNT:3; /*!< bit: 5.. 7 Pipe Error Count */
- uint16_t :8; /*!< bit: 8..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t DTGLER:1; /*!< bit: 0 Data Toggle Error */
+ uint16_t DAPIDER:1; /*!< bit: 1 Data PID Error */
+ uint16_t PIDER:1; /*!< bit: 2 PID Error */
+ uint16_t TOUTER:1; /*!< bit: 3 Time Out Error */
+ uint16_t CRC16ER:1; /*!< bit: 4 CRC16 Error */
+ uint16_t ERCNT:3; /*!< bit: 5.. 7 Pipe Error Count */
+ uint16_t :8; /*!< bit: 8..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} USB_HOST_STATUS_PIPE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1665,140 +1665,140 @@ typedef union {
/** \brief UsbDeviceDescBank SRAM registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO USB_DEVICE_ADDR_Type ADDR; /**< \brief Offset: 0x000 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer */
- __IO USB_DEVICE_PCKSIZE_Type PCKSIZE; /**< \brief Offset: 0x004 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Packet Size */
- __IO USB_DEVICE_EXTREG_Type EXTREG; /**< \brief Offset: 0x008 (R/W 16) DEVICE_DESC_BANK Endpoint Bank, Extended */
- __IO USB_DEVICE_STATUS_BK_Type STATUS_BK; /**< \brief Offset: 0x00A (R/W 8) DEVICE_DESC_BANK Enpoint Bank, Status of Bank */
- RoReg8 Reserved1[0x5];
+ __IO USB_DEVICE_ADDR_Type ADDR; /**< \brief Offset: 0x000 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer */
+ __IO USB_DEVICE_PCKSIZE_Type PCKSIZE; /**< \brief Offset: 0x004 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Packet Size */
+ __IO USB_DEVICE_EXTREG_Type EXTREG; /**< \brief Offset: 0x008 (R/W 16) DEVICE_DESC_BANK Endpoint Bank, Extended */
+ __IO USB_DEVICE_STATUS_BK_Type STATUS_BK; /**< \brief Offset: 0x00A (R/W 8) DEVICE_DESC_BANK Enpoint Bank, Status of Bank */
+ RoReg8 Reserved1[0x5];
} UsbDeviceDescBank;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief UsbHostDescBank SRAM registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO USB_HOST_ADDR_Type ADDR; /**< \brief Offset: 0x000 (R/W 32) HOST_DESC_BANK Host Bank, Adress of Data Buffer */
- __IO USB_HOST_PCKSIZE_Type PCKSIZE; /**< \brief Offset: 0x004 (R/W 32) HOST_DESC_BANK Host Bank, Packet Size */
- __IO USB_HOST_EXTREG_Type EXTREG; /**< \brief Offset: 0x008 (R/W 16) HOST_DESC_BANK Host Bank, Extended */
- __IO USB_HOST_STATUS_BK_Type STATUS_BK; /**< \brief Offset: 0x00A (R/W 8) HOST_DESC_BANK Host Bank, Status of Bank */
- RoReg8 Reserved1[0x1];
- __IO USB_HOST_CTRL_PIPE_Type CTRL_PIPE; /**< \brief Offset: 0x00C (R/W 16) HOST_DESC_BANK Host Bank, Host Control Pipe */
- __IO USB_HOST_STATUS_PIPE_Type STATUS_PIPE; /**< \brief Offset: 0x00E (R/W 16) HOST_DESC_BANK Host Bank, Host Status Pipe */
+ __IO USB_HOST_ADDR_Type ADDR; /**< \brief Offset: 0x000 (R/W 32) HOST_DESC_BANK Host Bank, Adress of Data Buffer */
+ __IO USB_HOST_PCKSIZE_Type PCKSIZE; /**< \brief Offset: 0x004 (R/W 32) HOST_DESC_BANK Host Bank, Packet Size */
+ __IO USB_HOST_EXTREG_Type EXTREG; /**< \brief Offset: 0x008 (R/W 16) HOST_DESC_BANK Host Bank, Extended */
+ __IO USB_HOST_STATUS_BK_Type STATUS_BK; /**< \brief Offset: 0x00A (R/W 8) HOST_DESC_BANK Host Bank, Status of Bank */
+ RoReg8 Reserved1[0x1];
+ __IO USB_HOST_CTRL_PIPE_Type CTRL_PIPE; /**< \brief Offset: 0x00C (R/W 16) HOST_DESC_BANK Host Bank, Host Control Pipe */
+ __IO USB_HOST_STATUS_PIPE_Type STATUS_PIPE; /**< \brief Offset: 0x00E (R/W 16) HOST_DESC_BANK Host Bank, Host Status Pipe */
} UsbHostDescBank;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief UsbDeviceEndpoint hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO USB_DEVICE_EPCFG_Type EPCFG; /**< \brief Offset: 0x000 (R/W 8) DEVICE_ENDPOINT End Point Configuration */
- RoReg8 Reserved1[0x3];
- __O USB_DEVICE_EPSTATUSCLR_Type EPSTATUSCLR; /**< \brief Offset: 0x004 ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Clear */
- __O USB_DEVICE_EPSTATUSSET_Type EPSTATUSSET; /**< \brief Offset: 0x005 ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Set */
- __I USB_DEVICE_EPSTATUS_Type EPSTATUS; /**< \brief Offset: 0x006 (R/ 8) DEVICE_ENDPOINT End Point Pipe Status */
- __IO USB_DEVICE_EPINTFLAG_Type EPINTFLAG; /**< \brief Offset: 0x007 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Flag */
- __IO USB_DEVICE_EPINTENCLR_Type EPINTENCLR; /**< \brief Offset: 0x008 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Clear Flag */
- __IO USB_DEVICE_EPINTENSET_Type EPINTENSET; /**< \brief Offset: 0x009 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Set Flag */
- RoReg8 Reserved2[0x16];
+ __IO USB_DEVICE_EPCFG_Type EPCFG; /**< \brief Offset: 0x000 (R/W 8) DEVICE_ENDPOINT End Point Configuration */
+ RoReg8 Reserved1[0x3];
+ __O USB_DEVICE_EPSTATUSCLR_Type EPSTATUSCLR; /**< \brief Offset: 0x004 ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Clear */
+ __O USB_DEVICE_EPSTATUSSET_Type EPSTATUSSET; /**< \brief Offset: 0x005 ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Set */
+ __I USB_DEVICE_EPSTATUS_Type EPSTATUS; /**< \brief Offset: 0x006 (R/ 8) DEVICE_ENDPOINT End Point Pipe Status */
+ __IO USB_DEVICE_EPINTFLAG_Type EPINTFLAG; /**< \brief Offset: 0x007 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Flag */
+ __IO USB_DEVICE_EPINTENCLR_Type EPINTENCLR; /**< \brief Offset: 0x008 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Clear Flag */
+ __IO USB_DEVICE_EPINTENSET_Type EPINTENSET; /**< \brief Offset: 0x009 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Set Flag */
+ RoReg8 Reserved2[0x16];
} UsbDeviceEndpoint;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief UsbHostPipe hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO USB_HOST_PCFG_Type PCFG; /**< \brief Offset: 0x000 (R/W 8) HOST_PIPE End Point Configuration */
- RoReg8 Reserved1[0x2];
- __IO USB_HOST_BINTERVAL_Type BINTERVAL; /**< \brief Offset: 0x003 (R/W 8) HOST_PIPE Bus Access Period of Pipe */
- __O USB_HOST_PSTATUSCLR_Type PSTATUSCLR; /**< \brief Offset: 0x004 ( /W 8) HOST_PIPE End Point Pipe Status Clear */
- __O USB_HOST_PSTATUSSET_Type PSTATUSSET; /**< \brief Offset: 0x005 ( /W 8) HOST_PIPE End Point Pipe Status Set */
- __I USB_HOST_PSTATUS_Type PSTATUS; /**< \brief Offset: 0x006 (R/ 8) HOST_PIPE End Point Pipe Status */
- __IO USB_HOST_PINTFLAG_Type PINTFLAG; /**< \brief Offset: 0x007 (R/W 8) HOST_PIPE Pipe Interrupt Flag */
- __IO USB_HOST_PINTENCLR_Type PINTENCLR; /**< \brief Offset: 0x008 (R/W 8) HOST_PIPE Pipe Interrupt Flag Clear */
- __IO USB_HOST_PINTENSET_Type PINTENSET; /**< \brief Offset: 0x009 (R/W 8) HOST_PIPE Pipe Interrupt Flag Set */
- RoReg8 Reserved2[0x16];
+ __IO USB_HOST_PCFG_Type PCFG; /**< \brief Offset: 0x000 (R/W 8) HOST_PIPE End Point Configuration */
+ RoReg8 Reserved1[0x2];
+ __IO USB_HOST_BINTERVAL_Type BINTERVAL; /**< \brief Offset: 0x003 (R/W 8) HOST_PIPE Bus Access Period of Pipe */
+ __O USB_HOST_PSTATUSCLR_Type PSTATUSCLR; /**< \brief Offset: 0x004 ( /W 8) HOST_PIPE End Point Pipe Status Clear */
+ __O USB_HOST_PSTATUSSET_Type PSTATUSSET; /**< \brief Offset: 0x005 ( /W 8) HOST_PIPE End Point Pipe Status Set */
+ __I USB_HOST_PSTATUS_Type PSTATUS; /**< \brief Offset: 0x006 (R/ 8) HOST_PIPE End Point Pipe Status */
+ __IO USB_HOST_PINTFLAG_Type PINTFLAG; /**< \brief Offset: 0x007 (R/W 8) HOST_PIPE Pipe Interrupt Flag */
+ __IO USB_HOST_PINTENCLR_Type PINTENCLR; /**< \brief Offset: 0x008 (R/W 8) HOST_PIPE Pipe Interrupt Flag Clear */
+ __IO USB_HOST_PINTENSET_Type PINTENSET; /**< \brief Offset: 0x009 (R/W 8) HOST_PIPE Pipe Interrupt Flag Set */
+ RoReg8 Reserved2[0x16];
} UsbHostPipe;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief USB_DEVICE APB hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* USB is Device */
- __IO USB_CTRLA_Type CTRLA; /**< \brief Offset: 0x000 (R/W 8) Control A */
- RoReg8 Reserved1[0x1];
- __I USB_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x002 (R/ 8) Synchronization Busy */
- __IO USB_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x003 (R/W 8) USB Quality Of Service */
- RoReg8 Reserved2[0x4];
- __IO USB_DEVICE_CTRLB_Type CTRLB; /**< \brief Offset: 0x008 (R/W 16) DEVICE Control B */
- __IO USB_DEVICE_DADD_Type DADD; /**< \brief Offset: 0x00A (R/W 8) DEVICE Device Address */
- RoReg8 Reserved3[0x1];
- __I USB_DEVICE_STATUS_Type STATUS; /**< \brief Offset: 0x00C (R/ 8) DEVICE Status */
- __I USB_FSMSTATUS_Type FSMSTATUS; /**< \brief Offset: 0x00D (R/ 8) Finite State Machine Status */
- RoReg8 Reserved4[0x2];
- __I USB_DEVICE_FNUM_Type FNUM; /**< \brief Offset: 0x010 (R/ 16) DEVICE Device Frame Number */
- RoReg8 Reserved5[0x2];
- __IO USB_DEVICE_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x014 (R/W 16) DEVICE Device Interrupt Enable Clear */
- RoReg8 Reserved6[0x2];
- __IO USB_DEVICE_INTENSET_Type INTENSET; /**< \brief Offset: 0x018 (R/W 16) DEVICE Device Interrupt Enable Set */
- RoReg8 Reserved7[0x2];
- __IO USB_DEVICE_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x01C (R/W 16) DEVICE Device Interrupt Flag */
- RoReg8 Reserved8[0x2];
- __I USB_DEVICE_EPINTSMRY_Type EPINTSMRY; /**< \brief Offset: 0x020 (R/ 16) DEVICE End Point Interrupt Summary */
- RoReg8 Reserved9[0x2];
- __IO USB_DESCADD_Type DESCADD; /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */
- __IO USB_PADCAL_Type PADCAL; /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */
- RoReg8 Reserved10[0xD6];
- UsbDeviceEndpoint DeviceEndpoint[8]; /**< \brief Offset: 0x100 UsbDeviceEndpoint groups [EPT_NUM] */
+ __IO USB_CTRLA_Type CTRLA; /**< \brief Offset: 0x000 (R/W 8) Control A */
+ RoReg8 Reserved1[0x1];
+ __I USB_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x002 (R/ 8) Synchronization Busy */
+ __IO USB_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x003 (R/W 8) USB Quality Of Service */
+ RoReg8 Reserved2[0x4];
+ __IO USB_DEVICE_CTRLB_Type CTRLB; /**< \brief Offset: 0x008 (R/W 16) DEVICE Control B */
+ __IO USB_DEVICE_DADD_Type DADD; /**< \brief Offset: 0x00A (R/W 8) DEVICE Device Address */
+ RoReg8 Reserved3[0x1];
+ __I USB_DEVICE_STATUS_Type STATUS; /**< \brief Offset: 0x00C (R/ 8) DEVICE Status */
+ __I USB_FSMSTATUS_Type FSMSTATUS; /**< \brief Offset: 0x00D (R/ 8) Finite State Machine Status */
+ RoReg8 Reserved4[0x2];
+ __I USB_DEVICE_FNUM_Type FNUM; /**< \brief Offset: 0x010 (R/ 16) DEVICE Device Frame Number */
+ RoReg8 Reserved5[0x2];
+ __IO USB_DEVICE_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x014 (R/W 16) DEVICE Device Interrupt Enable Clear */
+ RoReg8 Reserved6[0x2];
+ __IO USB_DEVICE_INTENSET_Type INTENSET; /**< \brief Offset: 0x018 (R/W 16) DEVICE Device Interrupt Enable Set */
+ RoReg8 Reserved7[0x2];
+ __IO USB_DEVICE_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x01C (R/W 16) DEVICE Device Interrupt Flag */
+ RoReg8 Reserved8[0x2];
+ __I USB_DEVICE_EPINTSMRY_Type EPINTSMRY; /**< \brief Offset: 0x020 (R/ 16) DEVICE End Point Interrupt Summary */
+ RoReg8 Reserved9[0x2];
+ __IO USB_DESCADD_Type DESCADD; /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */
+ __IO USB_PADCAL_Type PADCAL; /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */
+ RoReg8 Reserved10[0xD6];
+ UsbDeviceEndpoint DeviceEndpoint[8]; /**< \brief Offset: 0x100 UsbDeviceEndpoint groups [EPT_NUM] */
} UsbDevice;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief USB_HOST hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* USB is Host */
- __IO USB_CTRLA_Type CTRLA; /**< \brief Offset: 0x000 (R/W 8) Control A */
- RoReg8 Reserved1[0x1];
- __I USB_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x002 (R/ 8) Synchronization Busy */
- __IO USB_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x003 (R/W 8) USB Quality Of Service */
- RoReg8 Reserved2[0x4];
- __IO USB_HOST_CTRLB_Type CTRLB; /**< \brief Offset: 0x008 (R/W 16) HOST Control B */
- __IO USB_HOST_HSOFC_Type HSOFC; /**< \brief Offset: 0x00A (R/W 8) HOST Host Start Of Frame Control */
- RoReg8 Reserved3[0x1];
- __IO USB_HOST_STATUS_Type STATUS; /**< \brief Offset: 0x00C (R/W 8) HOST Status */
- __I USB_FSMSTATUS_Type FSMSTATUS; /**< \brief Offset: 0x00D (R/ 8) Finite State Machine Status */
- RoReg8 Reserved4[0x2];
- __IO USB_HOST_FNUM_Type FNUM; /**< \brief Offset: 0x010 (R/W 16) HOST Host Frame Number */
- __I USB_HOST_FLENHIGH_Type FLENHIGH; /**< \brief Offset: 0x012 (R/ 8) HOST Host Frame Length */
- RoReg8 Reserved5[0x1];
- __IO USB_HOST_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x014 (R/W 16) HOST Host Interrupt Enable Clear */
- RoReg8 Reserved6[0x2];
- __IO USB_HOST_INTENSET_Type INTENSET; /**< \brief Offset: 0x018 (R/W 16) HOST Host Interrupt Enable Set */
- RoReg8 Reserved7[0x2];
- __IO USB_HOST_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x01C (R/W 16) HOST Host Interrupt Flag */
- RoReg8 Reserved8[0x2];
- __I USB_HOST_PINTSMRY_Type PINTSMRY; /**< \brief Offset: 0x020 (R/ 16) HOST Pipe Interrupt Summary */
- RoReg8 Reserved9[0x2];
- __IO USB_DESCADD_Type DESCADD; /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */
- __IO USB_PADCAL_Type PADCAL; /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */
- RoReg8 Reserved10[0xD6];
- UsbHostPipe HostPipe[8]; /**< \brief Offset: 0x100 UsbHostPipe groups [EPT_NUM*HOST_IMPLEMENTED] */
+ __IO USB_CTRLA_Type CTRLA; /**< \brief Offset: 0x000 (R/W 8) Control A */
+ RoReg8 Reserved1[0x1];
+ __I USB_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x002 (R/ 8) Synchronization Busy */
+ __IO USB_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x003 (R/W 8) USB Quality Of Service */
+ RoReg8 Reserved2[0x4];
+ __IO USB_HOST_CTRLB_Type CTRLB; /**< \brief Offset: 0x008 (R/W 16) HOST Control B */
+ __IO USB_HOST_HSOFC_Type HSOFC; /**< \brief Offset: 0x00A (R/W 8) HOST Host Start Of Frame Control */
+ RoReg8 Reserved3[0x1];
+ __IO USB_HOST_STATUS_Type STATUS; /**< \brief Offset: 0x00C (R/W 8) HOST Status */
+ __I USB_FSMSTATUS_Type FSMSTATUS; /**< \brief Offset: 0x00D (R/ 8) Finite State Machine Status */
+ RoReg8 Reserved4[0x2];
+ __IO USB_HOST_FNUM_Type FNUM; /**< \brief Offset: 0x010 (R/W 16) HOST Host Frame Number */
+ __I USB_HOST_FLENHIGH_Type FLENHIGH; /**< \brief Offset: 0x012 (R/ 8) HOST Host Frame Length */
+ RoReg8 Reserved5[0x1];
+ __IO USB_HOST_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x014 (R/W 16) HOST Host Interrupt Enable Clear */
+ RoReg8 Reserved6[0x2];
+ __IO USB_HOST_INTENSET_Type INTENSET; /**< \brief Offset: 0x018 (R/W 16) HOST Host Interrupt Enable Set */
+ RoReg8 Reserved7[0x2];
+ __IO USB_HOST_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x01C (R/W 16) HOST Host Interrupt Flag */
+ RoReg8 Reserved8[0x2];
+ __I USB_HOST_PINTSMRY_Type PINTSMRY; /**< \brief Offset: 0x020 (R/ 16) HOST Pipe Interrupt Summary */
+ RoReg8 Reserved9[0x2];
+ __IO USB_DESCADD_Type DESCADD; /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */
+ __IO USB_PADCAL_Type PADCAL; /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */
+ RoReg8 Reserved10[0xD6];
+ UsbHostPipe HostPipe[8]; /**< \brief Offset: 0x100 UsbHostPipe groups [EPT_NUM*HOST_IMPLEMENTED] */
} UsbHost;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief USB_DEVICE Descriptor SRAM registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* USB is Device */
- UsbDeviceDescBank DeviceDescBank[2]; /**< \brief Offset: 0x000 UsbDeviceDescBank groups */
+ UsbDeviceDescBank DeviceDescBank[2]; /**< \brief Offset: 0x000 UsbDeviceDescBank groups */
} UsbDeviceDescriptor;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief USB_HOST Descriptor SRAM registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* USB is Host */
- UsbHostDescBank HostDescBank[2]; /**< \brief Offset: 0x000 UsbHostDescBank groups [2*HOST_IMPLEMENTED] */
+ UsbHostDescBank HostDescBank[2]; /**< \brief Offset: 0x000 UsbHostDescBank groups [2*HOST_IMPLEMENTED] */
} UsbHostDescriptor;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SECTION_USB_DESCRIPTOR
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- UsbDevice DEVICE; /**< \brief Offset: 0x000 USB is Device */
- UsbHost HOST; /**< \brief Offset: 0x000 USB is Host */
+ UsbDevice DEVICE; /**< \brief Offset: 0x000 USB is Device */
+ UsbHost HOST; /**< \brief Offset: 0x000 USB is Host */
} Usb;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_wdt.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_wdt.h
index 708398a7125..05d0aaec6bf 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_wdt.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_wdt.h
@@ -59,14 +59,14 @@
/* -------- WDT_CTRL : (WDT Offset: 0x0) (R/W 8) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t :1; /*!< bit: 0 Reserved */
- uint8_t ENABLE:1; /*!< bit: 1 Enable */
- uint8_t WEN:1; /*!< bit: 2 Watchdog Timer Window Mode Enable */
- uint8_t :4; /*!< bit: 3.. 6 Reserved */
- uint8_t ALWAYSON:1; /*!< bit: 7 Always-On */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t :1; /*!< bit: 0 Reserved */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable */
+ uint8_t WEN:1; /*!< bit: 2 Watchdog Timer Window Mode Enable */
+ uint8_t :4; /*!< bit: 3.. 6 Reserved */
+ uint8_t ALWAYSON:1; /*!< bit: 7 Always-On */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} WDT_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -84,11 +84,11 @@ typedef union {
/* -------- WDT_CONFIG : (WDT Offset: 0x1) (R/W 8) Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t PER:4; /*!< bit: 0.. 3 Time-Out Period */
- uint8_t WINDOW:4; /*!< bit: 4.. 7 Window Mode Time-Out Period */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t PER:4; /*!< bit: 0.. 3 Time-Out Period */
+ uint8_t WINDOW:4; /*!< bit: 4.. 7 Window Mode Time-Out Period */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} WDT_CONFIG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -154,11 +154,11 @@ typedef union {
/* -------- WDT_EWCTRL : (WDT Offset: 0x2) (R/W 8) Early Warning Interrupt Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t EWOFFSET:4; /*!< bit: 0.. 3 Early Warning Interrupt Time Offset */
- uint8_t :4; /*!< bit: 4.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t EWOFFSET:4; /*!< bit: 0.. 3 Early Warning Interrupt Time Offset */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} WDT_EWCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -197,11 +197,11 @@ typedef union {
/* -------- WDT_INTENCLR : (WDT Offset: 0x4) (R/W 8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} WDT_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -215,11 +215,11 @@ typedef union {
/* -------- WDT_INTENSET : (WDT Offset: 0x5) (R/W 8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} WDT_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -233,11 +233,11 @@ typedef union {
/* -------- WDT_INTFLAG : (WDT Offset: 0x6) (R/W 8) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t EW:1; /*!< bit: 0 Early Warning */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t EW:1; /*!< bit: 0 Early Warning */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} WDT_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -251,11 +251,11 @@ typedef union {
/* -------- WDT_STATUS : (WDT Offset: 0x7) (R/ 8) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t :7; /*!< bit: 0.. 6 Reserved */
- uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t :7; /*!< bit: 0.. 6 Reserved */
+ uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} WDT_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -269,10 +269,10 @@ typedef union {
/* -------- WDT_CLEAR : (WDT Offset: 0x8) ( /W 8) Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t CLEAR:8; /*!< bit: 0.. 7 Watchdog Clear */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t CLEAR:8; /*!< bit: 0.. 7 Watchdog Clear */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} WDT_CLEAR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -289,15 +289,15 @@ typedef union {
/** \brief WDT hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO WDT_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */
- __IO WDT_CONFIG_Type CONFIG; /**< \brief Offset: 0x1 (R/W 8) Configuration */
- __IO WDT_EWCTRL_Type EWCTRL; /**< \brief Offset: 0x2 (R/W 8) Early Warning Interrupt Control */
- RoReg8 Reserved1[0x1];
- __IO WDT_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */
- __IO WDT_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */
- __IO WDT_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */
- __I WDT_STATUS_Type STATUS; /**< \brief Offset: 0x7 (R/ 8) Status */
- __O WDT_CLEAR_Type CLEAR; /**< \brief Offset: 0x8 ( /W 8) Clear */
+ __IO WDT_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */
+ __IO WDT_CONFIG_Type CONFIG; /**< \brief Offset: 0x1 (R/W 8) Configuration */
+ __IO WDT_EWCTRL_Type EWCTRL; /**< \brief Offset: 0x2 (R/W 8) Early Warning Interrupt Control */
+ RoReg8 Reserved1[0x1];
+ __IO WDT_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */
+ __IO WDT_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */
+ __IO WDT_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */
+ __I WDT_STATUS_Type STATUS; /**< \brief Offset: 0x7 (R/ 8) Status */
+ __O WDT_CLEAR_Type CLEAR; /**< \brief Offset: 0x8 ( /W 8) Clear */
} Wdt;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_ac.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_ac.h
index b2a6f5feb56..95556474750 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_ac.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_ac.h
@@ -84,7 +84,7 @@
#define AC_CMP_NUM 2 // Number of comparators
#define AC_GCLK_ID_ANA 32 // Index of Generic Clock for analog
#define AC_GCLK_ID_DIG 31 // Index of Generic Clock for digital
-#define AC_NUM_CMP 2
+#define AC_NUM_CMP 2
#define AC_PAIRS 1 // Number of pairs of comparators
#endif /* _SAMD21_AC_INSTANCE_ */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_ac1.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_ac1.h
index 409ea408577..1cf4789d554 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_ac1.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_ac1.h
@@ -81,7 +81,7 @@
#define AC1_CMP_NUM 2 // Number of comparators
#define AC1_GCLK_ID_ANA 32 // Index of Generic Clock for analog
#define AC1_GCLK_ID_DIG 31 // Index of Generic Clock for digital
-#define AC1_NUM_CMP 2
+#define AC1_NUM_CMP 2
#define AC1_PAIRS 1 // Number of pairs of comparators
#endif /* _SAMD21_AC1_INSTANCE_ */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_gclk.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_gclk.h
index 318a89516fa..6868a46fe08 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_gclk.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_gclk.h
@@ -63,7 +63,7 @@
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for GCLK peripheral ========== */
-#define GCLK_GENDIV_BITS 16
+#define GCLK_GENDIV_BITS 16
#define GCLK_GEN_NUM 9 // Number of Generic Clock Generators
#define GCLK_GEN_NUM_MSB 8 // Number of Generic Clock Generators - 1
#define GCLK_GEN_SOURCE_NUM_MSB 8 // Number of Generic Clock Sources - 1
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_nvmctrl.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_nvmctrl.h
index 70811521f5d..fc6350ac7f7 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_nvmctrl.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_nvmctrl.h
@@ -77,16 +77,16 @@
#define NVMCTRL_AUX3_ADDRESS 0x0080A000
#define NVMCTRL_CLK_AHB_ID 4 // Index of AHB Clock in PM.AHBMASK register
#define NVMCTRL_FACTORY_WORD_IMPLEMENTED_MASK 0xC0000007FFFFFFFF
-#define NVMCTRL_FLASH_SIZE 65536
+#define NVMCTRL_FLASH_SIZE 65536
#define NVMCTRL_LOCKBIT_ADDRESS 0x00802000
-#define NVMCTRL_PAGES 1024
-#define NVMCTRL_PAGE_HW 32
-#define NVMCTRL_PAGE_SIZE 64
-#define NVMCTRL_PAGE_W 16
-#define NVMCTRL_PMSB 3
-#define NVMCTRL_PSZ_BITS 6
-#define NVMCTRL_ROW_PAGES 4
-#define NVMCTRL_ROW_SIZE 256
+#define NVMCTRL_PAGES 1024
+#define NVMCTRL_PAGE_HW 32
+#define NVMCTRL_PAGE_SIZE 64
+#define NVMCTRL_PAGE_W 16
+#define NVMCTRL_PMSB 3
+#define NVMCTRL_PSZ_BITS 6
+#define NVMCTRL_ROW_PAGES 4
+#define NVMCTRL_ROW_SIZE 256
#define NVMCTRL_USER_PAGE_ADDRESS 0x00800000
#define NVMCTRL_USER_PAGE_OFFSET 0x00800000
#define NVMCTRL_USER_WORD_IMPLEMENTED_MASK 0xC01FFFFFFFFFFFFF
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_pm.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_pm.h
index ca35bf9422b..5bd92cb87c0 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_pm.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_pm.h
@@ -83,10 +83,10 @@
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for PM peripheral ========== */
-#define PM_CTRL_MCSEL_DFLL48M 3
-#define PM_CTRL_MCSEL_GCLK 0
-#define PM_CTRL_MCSEL_OSC8M 1
-#define PM_CTRL_MCSEL_XOSC 2
-#define PM_PM_CLK_APB_NUM 2
+#define PM_CTRL_MCSEL_DFLL48M 3
+#define PM_CTRL_MCSEL_GCLK 0
+#define PM_CTRL_MCSEL_OSC8M 1
+#define PM_CTRL_MCSEL_XOSC 2
+#define PM_PM_CLK_APB_NUM 2
#endif /* _SAMD21_PM_INSTANCE_ */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sbmatrix.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sbmatrix.h
index 870e14da5f1..d3523080916 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sbmatrix.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sbmatrix.h
@@ -149,7 +149,7 @@
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for SBMATRIX peripheral ========== */
-#define SBMATRIX_DEFINED
+#define SBMATRIX_DEFINED
/* ========== Instance parameters for SBMATRIX ========== */
#define SBMATRIX_SLAVE_FLASH 0
#define SBMATRIX_SLAVE_HPB0 1
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom0.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom0.h
index 9f9c5f61083..cb294f27f8f 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom0.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom0.h
@@ -141,6 +141,6 @@
#define SERCOM0_DMAC_ID_TX 2 // Index of DMA TX trigger
#define SERCOM0_GCLK_ID_CORE 20 // Index of Generic Clock for Core
#define SERCOM0_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout
-#define SERCOM0_INT_MSB 6
+#define SERCOM0_INT_MSB 6
#endif /* _SAMD21_SERCOM0_INSTANCE_ */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom1.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom1.h
index d0536328d58..aeeafcd1390 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom1.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom1.h
@@ -141,6 +141,6 @@
#define SERCOM1_DMAC_ID_TX 4 // Index of DMA TX trigger
#define SERCOM1_GCLK_ID_CORE 21 // Index of Generic Clock for Core
#define SERCOM1_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout
-#define SERCOM1_INT_MSB 6
+#define SERCOM1_INT_MSB 6
#endif /* _SAMD21_SERCOM1_INSTANCE_ */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom2.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom2.h
index 57cf5ad44c9..d662b5d83dd 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom2.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom2.h
@@ -141,6 +141,6 @@
#define SERCOM2_DMAC_ID_TX 6 // Index of DMA TX trigger
#define SERCOM2_GCLK_ID_CORE 22 // Index of Generic Clock for Core
#define SERCOM2_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout
-#define SERCOM2_INT_MSB 6
+#define SERCOM2_INT_MSB 6
#endif /* _SAMD21_SERCOM2_INSTANCE_ */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom3.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom3.h
index a6f2831ef25..1da53d6be0b 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom3.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom3.h
@@ -141,6 +141,6 @@
#define SERCOM3_DMAC_ID_TX 8 // Index of DMA TX trigger
#define SERCOM3_GCLK_ID_CORE 23 // Index of Generic Clock for Core
#define SERCOM3_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout
-#define SERCOM3_INT_MSB 6
+#define SERCOM3_INT_MSB 6
#endif /* _SAMD21_SERCOM3_INSTANCE_ */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom4.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom4.h
index 36e9939eb0b..b4d74044a0d 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom4.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom4.h
@@ -141,6 +141,6 @@
#define SERCOM4_DMAC_ID_TX 10 // Index of DMA TX trigger
#define SERCOM4_GCLK_ID_CORE 24 // Index of Generic Clock for Core
#define SERCOM4_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout
-#define SERCOM4_INT_MSB 6
+#define SERCOM4_INT_MSB 6
#endif /* _SAMD21_SERCOM4_INSTANCE_ */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom5.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom5.h
index ea117a4b612..a468d17e85b 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom5.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom5.h
@@ -141,6 +141,6 @@
#define SERCOM5_DMAC_ID_TX 12 // Index of DMA TX trigger
#define SERCOM5_GCLK_ID_CORE 25 // Index of Generic Clock for Core
#define SERCOM5_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout
-#define SERCOM5_INT_MSB 6
+#define SERCOM5_INT_MSB 6
#endif /* _SAMD21_SERCOM5_INSTANCE_ */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sysctrl.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sysctrl.h
index e2b181b78c7..5b696479da6 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sysctrl.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sysctrl.h
@@ -93,31 +93,31 @@
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for SYSCTRL peripheral ========== */
-#define SYSCTRL_BGAP_CALIB_MSB 11
-#define SYSCTRL_BOD33_CALIB_MSB 5
-#define SYSCTRL_DFLL48M_COARSE_MSB 5
-#define SYSCTRL_DFLL48M_FINE_MSB 9
+#define SYSCTRL_BGAP_CALIB_MSB 11
+#define SYSCTRL_BOD33_CALIB_MSB 5
+#define SYSCTRL_DFLL48M_COARSE_MSB 5
+#define SYSCTRL_DFLL48M_FINE_MSB 9
#define SYSCTRL_GCLK_ID_DFLL48 0 // Index of Generic Clock for DFLL48
#define SYSCTRL_GCLK_ID_FDPLL 1 // Index of Generic Clock for DPLL
#define SYSCTRL_GCLK_ID_FDPLL32K 2 // Index of Generic Clock for DPLL 32K
-#define SYSCTRL_OSC32K_COARSE_CALIB_MSB 6
-#define SYSCTRL_POR33_ENTEST_MSB 1
-#define SYSCTRL_ULPVREF_DIVLEV_MSB 3
-#define SYSCTRL_ULPVREG_FORCEGAIN_MSB 1
-#define SYSCTRL_ULPVREG_RAMREFSEL_MSB 2
-#define SYSCTRL_VREF_CONTROL_MSB 48
-#define SYSCTRL_VREF_STATUS_MSB 7
-#define SYSCTRL_VREG_LEVEL_MSB 2
-#define SYSCTRL_BOD12_VERSION 0x111
-#define SYSCTRL_BOD33_VERSION 0x111
-#define SYSCTRL_DFLL48M_VERSION 0x301
-#define SYSCTRL_FDPLL_VERSION 0x111
-#define SYSCTRL_OSCULP32K_VERSION 0x111
-#define SYSCTRL_OSC8M_VERSION 0x120
-#define SYSCTRL_OSC32K_VERSION 0x112
-#define SYSCTRL_VREF_VERSION 0x201
-#define SYSCTRL_VREG_VERSION 0x201
-#define SYSCTRL_XOSC_VERSION 0x114
-#define SYSCTRL_XOSC32K_VERSION 0x113
+#define SYSCTRL_OSC32K_COARSE_CALIB_MSB 6
+#define SYSCTRL_POR33_ENTEST_MSB 1
+#define SYSCTRL_ULPVREF_DIVLEV_MSB 3
+#define SYSCTRL_ULPVREG_FORCEGAIN_MSB 1
+#define SYSCTRL_ULPVREG_RAMREFSEL_MSB 2
+#define SYSCTRL_VREF_CONTROL_MSB 48
+#define SYSCTRL_VREF_STATUS_MSB 7
+#define SYSCTRL_VREG_LEVEL_MSB 2
+#define SYSCTRL_BOD12_VERSION 0x111
+#define SYSCTRL_BOD33_VERSION 0x111
+#define SYSCTRL_DFLL48M_VERSION 0x301
+#define SYSCTRL_FDPLL_VERSION 0x111
+#define SYSCTRL_OSCULP32K_VERSION 0x111
+#define SYSCTRL_OSC8M_VERSION 0x120
+#define SYSCTRL_OSC32K_VERSION 0x112
+#define SYSCTRL_VREF_VERSION 0x201
+#define SYSCTRL_VREG_VERSION 0x201
+#define SYSCTRL_XOSC_VERSION 0x114
+#define SYSCTRL_XOSC32K_VERSION 0x113
#endif /* _SAMD21_SYSCTRL_INSTANCE_ */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc3.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc3.h
index 8eedead3bc9..07ad9025d50 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc3.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc3.h
@@ -106,7 +106,7 @@
#define TC3_DMAC_ID_MC_SIZE 2
#define TC3_DMAC_ID_OVF 24 // Indexes of DMA Overflow trigger
#define TC3_GCLK_ID 27 // Index of Generic Clock
-#define TC3_MASTER 0
+#define TC3_MASTER 0
#define TC3_OW_NUM 2 // Number of Output Waveforms
#define TC3_PERIOD_EXT 0 // Period feature implemented
#define TC3_SHADOW_EXT 0 // Shadow feature implemented
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc4.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc4.h
index 68e20637401..8539bca755c 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc4.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc4.h
@@ -106,7 +106,7 @@
#define TC4_DMAC_ID_MC_SIZE 2
#define TC4_DMAC_ID_OVF 27 // Indexes of DMA Overflow trigger
#define TC4_GCLK_ID 28 // Index of Generic Clock
-#define TC4_MASTER 1
+#define TC4_MASTER 1
#define TC4_OW_NUM 2 // Number of Output Waveforms
#define TC4_PERIOD_EXT 0 // Period feature implemented
#define TC4_SHADOW_EXT 0 // Shadow feature implemented
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc5.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc5.h
index fd483f0f492..0dfecceeb5e 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc5.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc5.h
@@ -106,7 +106,7 @@
#define TC5_DMAC_ID_MC_SIZE 2
#define TC5_DMAC_ID_OVF 30 // Indexes of DMA Overflow trigger
#define TC5_GCLK_ID 28 // Index of Generic Clock
-#define TC5_MASTER 0
+#define TC5_MASTER 0
#define TC5_OW_NUM 2 // Number of Output Waveforms
#define TC5_PERIOD_EXT 0 // Period feature implemented
#define TC5_SHADOW_EXT 0 // Shadow feature implemented
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc6.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc6.h
index 550bb404603..11cd7d2c10e 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc6.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc6.h
@@ -106,7 +106,7 @@
#define TC6_DMAC_ID_MC_SIZE 2
#define TC6_DMAC_ID_OVF 33 // Indexes of DMA Overflow trigger
#define TC6_GCLK_ID 29 // Index of Generic Clock
-#define TC6_MASTER 1
+#define TC6_MASTER 1
#define TC6_OW_NUM 2 // Number of Output Waveforms
#define TC6_PERIOD_EXT 0 // Period feature implemented
#define TC6_SHADOW_EXT 0 // Shadow feature implemented
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc7.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc7.h
index ebb32ce140b..190990f773f 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc7.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc7.h
@@ -106,7 +106,7 @@
#define TC7_DMAC_ID_MC_SIZE 2
#define TC7_DMAC_ID_OVF 36 // Indexes of DMA Overflow trigger
#define TC7_GCLK_ID 29 // Index of Generic Clock
-#define TC7_MASTER 0
+#define TC7_MASTER 0
#define TC7_OW_NUM 2 // Number of Output Waveforms
#define TC7_PERIOD_EXT 0 // Period feature implemented
#define TC7_SHADOW_EXT 0 // Shadow feature implemented
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tcc0.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tcc0.h
index 711ef16ce08..dcc737a45db 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tcc0.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tcc0.h
@@ -124,11 +124,11 @@
#define TCC0_DTI 1 // Dead-Time-Insertion feature implemented
#define TCC0_EXT 31 // (@_DITHERING*16+@_PG*8+@_SWAP*4+@_DTI*2+@_OTMX*1)
#define TCC0_GCLK_ID 26 // Index of Generic Clock
-#define TCC0_MASTER 0
+#define TCC0_MASTER 0
#define TCC0_OTMX 1 // Output Matrix feature implemented
#define TCC0_OW_NUM 8 // Number of Output Waveforms
#define TCC0_PG 1 // Pattern Generation feature implemented
-#define TCC0_SIZE 24
+#define TCC0_SIZE 24
#define TCC0_SWAP 1 // DTI outputs swap feature implemented
#define TCC0_TYPE 1 // TCC type 0 : NA, 1 : Master, 2 : Slave
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tcc1.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tcc1.h
index b4cc3bf2cf4..bc4c1710e58 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tcc1.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tcc1.h
@@ -112,11 +112,11 @@
#define TCC1_DTI 0 // Dead-Time-Insertion feature implemented
#define TCC1_EXT 24 // Coding of implemented extended features
#define TCC1_GCLK_ID 26 // Index of Generic Clock
-#define TCC1_MASTER 1
+#define TCC1_MASTER 1
#define TCC1_OTMX 0 // Output Matrix feature implemented
#define TCC1_OW_NUM 4 // Number of Output Waveforms
#define TCC1_PG 1 // Pattern Generation feature implemented
-#define TCC1_SIZE 24
+#define TCC1_SIZE 24
#define TCC1_SWAP 0 // DTI outputs swap feature implemented
#define TCC1_TYPE 2 // TCC type 0 : NA, 1 : Master, 2 : Slave
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tcc2.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tcc2.h
index 3f295c097f3..7b96139ca71 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tcc2.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tcc2.h
@@ -108,11 +108,11 @@
#define TCC2_DTI 0 // Dead-Time-Insertion feature implemented
#define TCC2_EXT 0 // Coding of implemented extended features
#define TCC2_GCLK_ID 27 // Index of Generic Clock
-#define TCC2_MASTER 0
+#define TCC2_MASTER 0
#define TCC2_OTMX 0 // Output Matrix feature implemented
#define TCC2_OW_NUM 2 // Number of Output Waveforms
#define TCC2_PG 0 // Pattern Generation feature implemented
-#define TCC2_SIZE 16
+#define TCC2_SIZE 16
#define TCC2_SWAP 0 // DTI outputs swap feature implemented
#define TCC2_TYPE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g17au.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g17au.h
index 4515df06254..37dc08b552c 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g17au.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g17au.h
@@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
- /*
- * Support and FAQ: visit Atmel Support
- */
+/*
+* Support and FAQ: visit Atmel Support
+*/
#ifndef _SAMD21G17AU_PIO_
#define _SAMD21G17AU_PIO_
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g18au.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g18au.h
index f4ff76b1d98..e4c3f08e8e8 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g18au.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g18au.h
@@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
- /*
- * Support and FAQ: visit Atmel Support
- */
+/*
+* Support and FAQ: visit Atmel Support
+*/
#ifndef _SAMD21G18AU_PIO_
#define _SAMD21G18AU_PIO_
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21.h
index 6c7b370e99a..56cb09907dc 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21.h
@@ -53,55 +53,55 @@
*/
#if defined(__SAMD21E15A__) || defined(__ATSAMD21E15A__)
- #include "samd21e15a.h"
+#include "samd21e15a.h"
#elif defined(__SAMD21E16A__) || defined(__ATSAMD21E16A__)
- #include "samd21e16a.h"
+#include "samd21e16a.h"
#elif defined(__SAMD21E17A__) || defined(__ATSAMD21E17A__)
- #include "samd21e17a.h"
+#include "samd21e17a.h"
#elif defined(__SAMD21E18A__) || defined(__ATSAMD21E18A__)
- #include "samd21e18a.h"
+#include "samd21e18a.h"
#elif defined(__SAMD21G15A__) || defined(__ATSAMD21G15A__)
- #include "samd21g15a.h"
+#include "samd21g15a.h"
#elif defined(__SAMD21G16A__) || defined(__ATSAMD21G16A__)
- #include "samd21g16a.h"
+#include "samd21g16a.h"
#elif defined(__SAMD21G17A__) || defined(__ATSAMD21G17A__)
- #include "samd21g17a.h"
+#include "samd21g17a.h"
#elif defined(__SAMD21G17AU__) || defined(__ATSAMD21G17AU__)
- #include "samd21g17au.h"
+#include "samd21g17au.h"
#elif defined(__SAMD21G18A__) || defined(__ATSAMD21G18A__)
- #include "samd21g18a.h"
+#include "samd21g18a.h"
#elif defined (__SAMD21G18AU__) || defined(__ATSAMD21G18AU__)
- #include "samd21g18au.h"
+#include "samd21g18au.h"
#elif defined(__SAMD21J15A__) || defined(__ATSAMD21J15A__)
- #include "samd21j15a.h"
+#include "samd21j15a.h"
#elif defined(__SAMD21J16A__) || defined(__ATSAMD21J16A__)
- #include "samd21j16a.h"
+#include "samd21j16a.h"
#elif defined(__SAMD21J17A__) || defined(__ATSAMD21J17A__)
- #include "samd21j17a.h"
+#include "samd21j17a.h"
#elif defined(__SAMD21J18A__) || defined(__ATSAMD21J18A__)
- #include "samd21j18a.h"
+#include "samd21j18a.h"
#elif defined(__SAMD21E15B__) || defined(__ATSAMD21E15B__)
- #include "samd21e15b.h"
+#include "samd21e15b.h"
#elif defined(__SAMD21E15BU__) || defined(__ATSAMD21E15BU__)
- #include "samd21e15bu.h"
+#include "samd21e15bu.h"
#elif defined(__SAMD21E15L__) || defined(__ATSAMD21E15L__)
- #include "samd21e15l.h"
+#include "samd21e15l.h"
#elif defined(__SAMD21E16B__) || defined(__ATSAMD21E16B__)
- #include "samd21e16b.h"
+#include "samd21e16b.h"
#elif defined(__SAMD21E16BU__) || defined(__ATSAMD21E16BU__)
- #include "samd21e16bu.h"
+#include "samd21e16bu.h"
#elif defined(__SAMD21E16L__) || defined(__ATSAMD21E16L__)
- #include "samd21e16l.h"
+#include "samd21e16l.h"
#elif defined(__SAMD21G15B__) || defined(__ATSAMD21G15B__)
- #include "samd21g15b.h"
+#include "samd21g15b.h"
#elif defined(__SAMD21G16B__) || defined(__ATSAMD21G16B__)
- #include "samd21g16b.h"
+#include "samd21g16b.h"
#elif defined(__SAMD21J15B__) || defined(__ATSAMD21J15B__)
- #include "samd21j15b.h"
+#include "samd21j15b.h"
#elif defined(__SAMD21J16B__) || defined(__ATSAMD21J16B__)
- #include "samd21j16b.h"
+#include "samd21j16b.h"
#else
- #error Library does not support the specified device.
+#error Library does not support the specified device.
#endif
#endif /* _SAMD21_ */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e15a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e15a.h
index 04bf30021da..ce18ac2b5c9 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e15a.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e15a.h
@@ -59,7 +59,7 @@
/*@{*/
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -93,94 +93,92 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
-typedef enum IRQn
-{
- /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
- /****** SAMD21E15A-specific Interrupt Numbers ***********************/
- PM_IRQn = 0, /**< 0 SAMD21E15A Power Manager (PM) */
- SYSCTRL_IRQn = 1, /**< 1 SAMD21E15A System Control (SYSCTRL) */
- WDT_IRQn = 2, /**< 2 SAMD21E15A Watchdog Timer (WDT) */
- RTC_IRQn = 3, /**< 3 SAMD21E15A Real-Time Counter (RTC) */
- EIC_IRQn = 4, /**< 4 SAMD21E15A External Interrupt Controller (EIC) */
- NVMCTRL_IRQn = 5, /**< 5 SAMD21E15A Non-Volatile Memory Controller (NVMCTRL) */
- DMAC_IRQn = 6, /**< 6 SAMD21E15A Direct Memory Access Controller (DMAC) */
- USB_IRQn = 7, /**< 7 SAMD21E15A Universal Serial Bus (USB) */
- EVSYS_IRQn = 8, /**< 8 SAMD21E15A Event System Interface (EVSYS) */
- SERCOM0_IRQn = 9, /**< 9 SAMD21E15A Serial Communication Interface 0 (SERCOM0) */
- SERCOM1_IRQn = 10, /**< 10 SAMD21E15A Serial Communication Interface 1 (SERCOM1) */
- SERCOM2_IRQn = 11, /**< 11 SAMD21E15A Serial Communication Interface 2 (SERCOM2) */
- SERCOM3_IRQn = 12, /**< 12 SAMD21E15A Serial Communication Interface 3 (SERCOM3) */
- TCC0_IRQn = 15, /**< 15 SAMD21E15A Timer Counter Control 0 (TCC0) */
- TCC1_IRQn = 16, /**< 16 SAMD21E15A Timer Counter Control 1 (TCC1) */
- TCC2_IRQn = 17, /**< 17 SAMD21E15A Timer Counter Control 2 (TCC2) */
- TC3_IRQn = 18, /**< 18 SAMD21E15A Basic Timer Counter 3 (TC3) */
- TC4_IRQn = 19, /**< 19 SAMD21E15A Basic Timer Counter 4 (TC4) */
- TC5_IRQn = 20, /**< 20 SAMD21E15A Basic Timer Counter 5 (TC5) */
- ADC_IRQn = 23, /**< 23 SAMD21E15A Analog Digital Converter (ADC) */
- AC_IRQn = 24, /**< 24 SAMD21E15A Analog Comparators (AC) */
- DAC_IRQn = 25, /**< 25 SAMD21E15A Digital Analog Converter (DAC) */
- PTC_IRQn = 26, /**< 26 SAMD21E15A Peripheral Touch Controller (PTC) */
- I2S_IRQn = 27, /**< 27 SAMD21E15A Inter-IC Sound Interface (I2S) */
-
- PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+typedef enum IRQn {
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21E15A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21E15A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21E15A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21E15A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21E15A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21E15A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21E15A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21E15A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21E15A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21E15A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21E15A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21E15A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21E15A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21E15A Serial Communication Interface 3 (SERCOM3) */
+ TCC0_IRQn = 15, /**< 15 SAMD21E15A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21E15A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21E15A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21E15A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21E15A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21E15A Basic Timer Counter 5 (TC5) */
+ ADC_IRQn = 23, /**< 23 SAMD21E15A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21E15A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21E15A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21E15A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21E15A Inter-IC Sound Interface (I2S) */
+
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
-
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnReservedM12;
- void* pfnReservedM11;
- void* pfnReservedM10;
- void* pfnReservedM9;
- void* pfnReservedM8;
- void* pfnReservedM7;
- void* pfnReservedM6;
- void* pfnSVC_Handler;
- void* pfnReservedM4;
- void* pfnReservedM3;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
-
- /* Peripheral handlers */
- void* pfnPM_Handler; /* 0 Power Manager */
- void* pfnSYSCTRL_Handler; /* 1 System Control */
- void* pfnWDT_Handler; /* 2 Watchdog Timer */
- void* pfnRTC_Handler; /* 3 Real-Time Counter */
- void* pfnEIC_Handler; /* 4 External Interrupt Controller */
- void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
- void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
- void* pfnUSB_Handler; /* 7 Universal Serial Bus */
- void* pfnEVSYS_Handler; /* 8 Event System Interface */
- void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
- void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
- void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
- void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
- void* pfnReserved13;
- void* pfnReserved14;
- void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
- void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
- void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
- void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
- void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
- void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
- void* pfnReserved21;
- void* pfnReserved22;
- void* pfnADC_Handler; /* 23 Analog Digital Converter */
- void* pfnAC_Handler; /* 24 Analog Comparators */
- void* pfnDAC_Handler; /* 25 Digital Analog Converter */
- void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
- void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+typedef struct _DeviceVectors {
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnReserved13;
+ void* pfnReserved14;
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnReserved21;
+ void* pfnReserved22;
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@@ -221,7 +219,7 @@ void I2S_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e15b.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e15b.h
index 1abc3e33ded..383ebbc320c 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e15b.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e15b.h
@@ -56,7 +56,7 @@
/*@{*/
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -90,95 +90,93 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
-typedef enum IRQn
-{
- /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
- /****** SAMD21E15B-specific Interrupt Numbers ***********************/
- PM_IRQn = 0, /**< 0 SAMD21E15B Power Manager (PM) */
- SYSCTRL_IRQn = 1, /**< 1 SAMD21E15B System Control (SYSCTRL) */
- WDT_IRQn = 2, /**< 2 SAMD21E15B Watchdog Timer (WDT) */
- RTC_IRQn = 3, /**< 3 SAMD21E15B Real-Time Counter (RTC) */
- EIC_IRQn = 4, /**< 4 SAMD21E15B External Interrupt Controller (EIC) */
- NVMCTRL_IRQn = 5, /**< 5 SAMD21E15B Non-Volatile Memory Controller (NVMCTRL) */
- DMAC_IRQn = 6, /**< 6 SAMD21E15B Direct Memory Access Controller (DMAC) */
- USB_IRQn = 7, /**< 7 SAMD21E15B Universal Serial Bus (USB) */
- EVSYS_IRQn = 8, /**< 8 SAMD21E15B Event System Interface (EVSYS) */
- SERCOM0_IRQn = 9, /**< 9 SAMD21E15B Serial Communication Interface 0 (SERCOM0) */
- SERCOM1_IRQn = 10, /**< 10 SAMD21E15B Serial Communication Interface 1 (SERCOM1) */
- SERCOM2_IRQn = 11, /**< 11 SAMD21E15B Serial Communication Interface 2 (SERCOM2) */
- SERCOM3_IRQn = 12, /**< 12 SAMD21E15B Serial Communication Interface 3 (SERCOM3) */
- TCC0_IRQn = 15, /**< 15 SAMD21E15B Timer Counter Control 0 (TCC0) */
- TCC1_IRQn = 16, /**< 16 SAMD21E15B Timer Counter Control 1 (TCC1) */
- TCC2_IRQn = 17, /**< 17 SAMD21E15B Timer Counter Control 2 (TCC2) */
- TC3_IRQn = 18, /**< 18 SAMD21E15B Basic Timer Counter 3 (TC3) */
- TC4_IRQn = 19, /**< 19 SAMD21E15B Basic Timer Counter 4 (TC4) */
- TC5_IRQn = 20, /**< 20 SAMD21E15B Basic Timer Counter 5 (TC5) */
- ADC_IRQn = 23, /**< 23 SAMD21E15B Analog Digital Converter (ADC) */
- AC_IRQn = 24, /**< 24 SAMD21E15B Analog Comparators (AC) */
- DAC_IRQn = 25, /**< 25 SAMD21E15B Digital Analog Converter (DAC) */
- PTC_IRQn = 26, /**< 26 SAMD21E15B Peripheral Touch Controller (PTC) */
- I2S_IRQn = 27, /**< 27 SAMD21E15B Inter-IC Sound Interface (I2S) */
-
- PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+typedef enum IRQn {
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21E15B-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21E15B Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21E15B System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21E15B Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21E15B Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21E15B External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21E15B Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21E15B Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21E15B Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21E15B Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21E15B Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21E15B Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21E15B Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21E15B Serial Communication Interface 3 (SERCOM3) */
+ TCC0_IRQn = 15, /**< 15 SAMD21E15B Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21E15B Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21E15B Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21E15B Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21E15B Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21E15B Basic Timer Counter 5 (TC5) */
+ ADC_IRQn = 23, /**< 23 SAMD21E15B Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21E15B Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21E15B Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21E15B Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21E15B Inter-IC Sound Interface (I2S) */
+
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
-
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnReservedM12;
- void* pfnReservedM11;
- void* pfnReservedM10;
- void* pfnReservedM9;
- void* pfnReservedM8;
- void* pfnReservedM7;
- void* pfnReservedM6;
- void* pfnSVC_Handler;
- void* pfnReservedM4;
- void* pfnReservedM3;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
-
- /* Peripheral handlers */
- void* pfnPM_Handler; /* 0 Power Manager */
- void* pfnSYSCTRL_Handler; /* 1 System Control */
- void* pfnWDT_Handler; /* 2 Watchdog Timer */
- void* pfnRTC_Handler; /* 3 Real-Time Counter */
- void* pfnEIC_Handler; /* 4 External Interrupt Controller */
- void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
- void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
- void* pfnUSB_Handler; /* 7 Universal Serial Bus */
- void* pfnEVSYS_Handler; /* 8 Event System Interface */
- void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
- void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
- void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
- void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
- void* pfnReserved13;
- void* pfnReserved14;
- void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
- void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
- void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
- void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
- void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
- void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
- void* pfnReserved21;
- void* pfnReserved22;
- void* pfnADC_Handler; /* 23 Analog Digital Converter */
- void* pfnAC_Handler; /* 24 Analog Comparators */
- void* pfnDAC_Handler; /* 25 Digital Analog Converter */
- void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
- void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
- void* pfnReserved28;
+typedef struct _DeviceVectors {
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnReserved13;
+ void* pfnReserved14;
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnReserved21;
+ void* pfnReserved22;
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+ void* pfnReserved28;
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@@ -219,7 +217,7 @@ void I2S_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e15bu.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e15bu.h
index 0cd86bbc872..4381001c3d7 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e15bu.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e15bu.h
@@ -56,7 +56,7 @@
/*@{*/
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -90,95 +90,93 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
-typedef enum IRQn
-{
- /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
- /****** SAMD21E15BU-specific Interrupt Numbers ***********************/
- PM_IRQn = 0, /**< 0 SAMD21E15BU Power Manager (PM) */
- SYSCTRL_IRQn = 1, /**< 1 SAMD21E15BU System Control (SYSCTRL) */
- WDT_IRQn = 2, /**< 2 SAMD21E15BU Watchdog Timer (WDT) */
- RTC_IRQn = 3, /**< 3 SAMD21E15BU Real-Time Counter (RTC) */
- EIC_IRQn = 4, /**< 4 SAMD21E15BU External Interrupt Controller (EIC) */
- NVMCTRL_IRQn = 5, /**< 5 SAMD21E15BU Non-Volatile Memory Controller (NVMCTRL) */
- DMAC_IRQn = 6, /**< 6 SAMD21E15BU Direct Memory Access Controller (DMAC) */
- USB_IRQn = 7, /**< 7 SAMD21E15BU Universal Serial Bus (USB) */
- EVSYS_IRQn = 8, /**< 8 SAMD21E15BU Event System Interface (EVSYS) */
- SERCOM0_IRQn = 9, /**< 9 SAMD21E15BU Serial Communication Interface 0 (SERCOM0) */
- SERCOM1_IRQn = 10, /**< 10 SAMD21E15BU Serial Communication Interface 1 (SERCOM1) */
- SERCOM2_IRQn = 11, /**< 11 SAMD21E15BU Serial Communication Interface 2 (SERCOM2) */
- SERCOM3_IRQn = 12, /**< 12 SAMD21E15BU Serial Communication Interface 3 (SERCOM3) */
- TCC0_IRQn = 15, /**< 15 SAMD21E15BU Timer Counter Control 0 (TCC0) */
- TCC1_IRQn = 16, /**< 16 SAMD21E15BU Timer Counter Control 1 (TCC1) */
- TCC2_IRQn = 17, /**< 17 SAMD21E15BU Timer Counter Control 2 (TCC2) */
- TC3_IRQn = 18, /**< 18 SAMD21E15BU Basic Timer Counter 3 (TC3) */
- TC4_IRQn = 19, /**< 19 SAMD21E15BU Basic Timer Counter 4 (TC4) */
- TC5_IRQn = 20, /**< 20 SAMD21E15BU Basic Timer Counter 5 (TC5) */
- ADC_IRQn = 23, /**< 23 SAMD21E15BU Analog Digital Converter (ADC) */
- AC_IRQn = 24, /**< 24 SAMD21E15BU Analog Comparators (AC) */
- DAC_IRQn = 25, /**< 25 SAMD21E15BU Digital Analog Converter (DAC) */
- PTC_IRQn = 26, /**< 26 SAMD21E15BU Peripheral Touch Controller (PTC) */
- I2S_IRQn = 27, /**< 27 SAMD21E15BU Inter-IC Sound Interface (I2S) */
-
- PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+typedef enum IRQn {
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21E15BU-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21E15BU Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21E15BU System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21E15BU Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21E15BU Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21E15BU External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21E15BU Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21E15BU Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21E15BU Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21E15BU Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21E15BU Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21E15BU Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21E15BU Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21E15BU Serial Communication Interface 3 (SERCOM3) */
+ TCC0_IRQn = 15, /**< 15 SAMD21E15BU Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21E15BU Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21E15BU Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21E15BU Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21E15BU Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21E15BU Basic Timer Counter 5 (TC5) */
+ ADC_IRQn = 23, /**< 23 SAMD21E15BU Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21E15BU Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21E15BU Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21E15BU Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21E15BU Inter-IC Sound Interface (I2S) */
+
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
-
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnReservedM12;
- void* pfnReservedM11;
- void* pfnReservedM10;
- void* pfnReservedM9;
- void* pfnReservedM8;
- void* pfnReservedM7;
- void* pfnReservedM6;
- void* pfnSVC_Handler;
- void* pfnReservedM4;
- void* pfnReservedM3;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
-
- /* Peripheral handlers */
- void* pfnPM_Handler; /* 0 Power Manager */
- void* pfnSYSCTRL_Handler; /* 1 System Control */
- void* pfnWDT_Handler; /* 2 Watchdog Timer */
- void* pfnRTC_Handler; /* 3 Real-Time Counter */
- void* pfnEIC_Handler; /* 4 External Interrupt Controller */
- void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
- void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
- void* pfnUSB_Handler; /* 7 Universal Serial Bus */
- void* pfnEVSYS_Handler; /* 8 Event System Interface */
- void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
- void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
- void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
- void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
- void* pfnReserved13;
- void* pfnReserved14;
- void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
- void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
- void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
- void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
- void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
- void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
- void* pfnReserved21;
- void* pfnReserved22;
- void* pfnADC_Handler; /* 23 Analog Digital Converter */
- void* pfnAC_Handler; /* 24 Analog Comparators */
- void* pfnDAC_Handler; /* 25 Digital Analog Converter */
- void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
- void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
- void* pfnReserved28;
+typedef struct _DeviceVectors {
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnReserved13;
+ void* pfnReserved14;
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnReserved21;
+ void* pfnReserved22;
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+ void* pfnReserved28;
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@@ -219,7 +217,7 @@ void I2S_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e15l.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e15l.h
index ab7c70b6cf0..fc4893f00ee 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e15l.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e15l.h
@@ -56,7 +56,7 @@
/*@{*/
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -90,93 +90,91 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
-typedef enum IRQn
-{
- /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
- /****** SAMD21E15L-specific Interrupt Numbers ***********************/
- PM_IRQn = 0, /**< 0 SAMD21E15L Power Manager (PM) */
- SYSCTRL_IRQn = 1, /**< 1 SAMD21E15L System Control (SYSCTRL) */
- WDT_IRQn = 2, /**< 2 SAMD21E15L Watchdog Timer (WDT) */
- RTC_IRQn = 3, /**< 3 SAMD21E15L Real-Time Counter (RTC) */
- EIC_IRQn = 4, /**< 4 SAMD21E15L External Interrupt Controller (EIC) */
- NVMCTRL_IRQn = 5, /**< 5 SAMD21E15L Non-Volatile Memory Controller (NVMCTRL) */
- DMAC_IRQn = 6, /**< 6 SAMD21E15L Direct Memory Access Controller (DMAC) */
- EVSYS_IRQn = 8, /**< 8 SAMD21E15L Event System Interface (EVSYS) */
- SERCOM0_IRQn = 9, /**< 9 SAMD21E15L Serial Communication Interface 0 (SERCOM0) */
- SERCOM1_IRQn = 10, /**< 10 SAMD21E15L Serial Communication Interface 1 (SERCOM1) */
- SERCOM2_IRQn = 11, /**< 11 SAMD21E15L Serial Communication Interface 2 (SERCOM2) */
- SERCOM3_IRQn = 12, /**< 12 SAMD21E15L Serial Communication Interface 3 (SERCOM3) */
- TCC0_IRQn = 15, /**< 15 SAMD21E15L Timer Counter Control 0 (TCC0) */
- TCC1_IRQn = 16, /**< 16 SAMD21E15L Timer Counter Control 1 (TCC1) */
- TCC2_IRQn = 17, /**< 17 SAMD21E15L Timer Counter Control 2 (TCC2) */
- TC3_IRQn = 18, /**< 18 SAMD21E15L Basic Timer Counter 3 (TC3) */
- TC4_IRQn = 19, /**< 19 SAMD21E15L Basic Timer Counter 4 (TC4) */
- TC5_IRQn = 20, /**< 20 SAMD21E15L Basic Timer Counter 5 (TC5) */
- ADC_IRQn = 23, /**< 23 SAMD21E15L Analog Digital Converter (ADC) */
- AC_IRQn = 24, /**< 24 SAMD21E15L Analog Comparators (AC) */
- DAC_IRQn = 25, /**< 25 SAMD21E15L Digital Analog Converter (DAC) */
- AC1_IRQn = 28, /**< 28 SAMD21E15L Analog Comparators 1 (AC1) */
-
- PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */
+typedef enum IRQn {
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21E15L-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21E15L Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21E15L System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21E15L Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21E15L Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21E15L External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21E15L Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21E15L Direct Memory Access Controller (DMAC) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21E15L Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21E15L Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21E15L Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21E15L Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21E15L Serial Communication Interface 3 (SERCOM3) */
+ TCC0_IRQn = 15, /**< 15 SAMD21E15L Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21E15L Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21E15L Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21E15L Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21E15L Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21E15L Basic Timer Counter 5 (TC5) */
+ ADC_IRQn = 23, /**< 23 SAMD21E15L Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21E15L Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21E15L Digital Analog Converter (DAC) */
+ AC1_IRQn = 28, /**< 28 SAMD21E15L Analog Comparators 1 (AC1) */
+
+ PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */
} IRQn_Type;
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
-
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnReservedM12;
- void* pfnReservedM11;
- void* pfnReservedM10;
- void* pfnReservedM9;
- void* pfnReservedM8;
- void* pfnReservedM7;
- void* pfnReservedM6;
- void* pfnSVC_Handler;
- void* pfnReservedM4;
- void* pfnReservedM3;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
-
- /* Peripheral handlers */
- void* pfnPM_Handler; /* 0 Power Manager */
- void* pfnSYSCTRL_Handler; /* 1 System Control */
- void* pfnWDT_Handler; /* 2 Watchdog Timer */
- void* pfnRTC_Handler; /* 3 Real-Time Counter */
- void* pfnEIC_Handler; /* 4 External Interrupt Controller */
- void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
- void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
- void* pfnReserved7;
- void* pfnEVSYS_Handler; /* 8 Event System Interface */
- void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
- void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
- void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
- void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
- void* pfnReserved13;
- void* pfnReserved14;
- void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
- void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
- void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
- void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
- void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
- void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
- void* pfnReserved21;
- void* pfnReserved22;
- void* pfnADC_Handler; /* 23 Analog Digital Converter */
- void* pfnAC_Handler; /* 24 Analog Comparators */
- void* pfnDAC_Handler; /* 25 Digital Analog Converter */
- void* pfnReserved26;
- void* pfnReserved27;
- void* pfnAC1_Handler; /* 28 Analog Comparators 1 */
+typedef struct _DeviceVectors {
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnReserved7;
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnReserved13;
+ void* pfnReserved14;
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnReserved21;
+ void* pfnReserved22;
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnReserved26;
+ void* pfnReserved27;
+ void* pfnAC1_Handler; /* 28 Analog Comparators 1 */
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@@ -215,7 +213,7 @@ void AC1_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e16a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e16a.h
index f708d078ec1..e84da564030 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e16a.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e16a.h
@@ -59,7 +59,7 @@
/*@{*/
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -93,94 +93,92 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
-typedef enum IRQn
-{
- /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
- /****** SAMD21E16A-specific Interrupt Numbers ***********************/
- PM_IRQn = 0, /**< 0 SAMD21E16A Power Manager (PM) */
- SYSCTRL_IRQn = 1, /**< 1 SAMD21E16A System Control (SYSCTRL) */
- WDT_IRQn = 2, /**< 2 SAMD21E16A Watchdog Timer (WDT) */
- RTC_IRQn = 3, /**< 3 SAMD21E16A Real-Time Counter (RTC) */
- EIC_IRQn = 4, /**< 4 SAMD21E16A External Interrupt Controller (EIC) */
- NVMCTRL_IRQn = 5, /**< 5 SAMD21E16A Non-Volatile Memory Controller (NVMCTRL) */
- DMAC_IRQn = 6, /**< 6 SAMD21E16A Direct Memory Access Controller (DMAC) */
- USB_IRQn = 7, /**< 7 SAMD21E16A Universal Serial Bus (USB) */
- EVSYS_IRQn = 8, /**< 8 SAMD21E16A Event System Interface (EVSYS) */
- SERCOM0_IRQn = 9, /**< 9 SAMD21E16A Serial Communication Interface 0 (SERCOM0) */
- SERCOM1_IRQn = 10, /**< 10 SAMD21E16A Serial Communication Interface 1 (SERCOM1) */
- SERCOM2_IRQn = 11, /**< 11 SAMD21E16A Serial Communication Interface 2 (SERCOM2) */
- SERCOM3_IRQn = 12, /**< 12 SAMD21E16A Serial Communication Interface 3 (SERCOM3) */
- TCC0_IRQn = 15, /**< 15 SAMD21E16A Timer Counter Control 0 (TCC0) */
- TCC1_IRQn = 16, /**< 16 SAMD21E16A Timer Counter Control 1 (TCC1) */
- TCC2_IRQn = 17, /**< 17 SAMD21E16A Timer Counter Control 2 (TCC2) */
- TC3_IRQn = 18, /**< 18 SAMD21E16A Basic Timer Counter 3 (TC3) */
- TC4_IRQn = 19, /**< 19 SAMD21E16A Basic Timer Counter 4 (TC4) */
- TC5_IRQn = 20, /**< 20 SAMD21E16A Basic Timer Counter 5 (TC5) */
- ADC_IRQn = 23, /**< 23 SAMD21E16A Analog Digital Converter (ADC) */
- AC_IRQn = 24, /**< 24 SAMD21E16A Analog Comparators (AC) */
- DAC_IRQn = 25, /**< 25 SAMD21E16A Digital Analog Converter (DAC) */
- PTC_IRQn = 26, /**< 26 SAMD21E16A Peripheral Touch Controller (PTC) */
- I2S_IRQn = 27, /**< 27 SAMD21E16A Inter-IC Sound Interface (I2S) */
-
- PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+typedef enum IRQn {
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21E16A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21E16A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21E16A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21E16A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21E16A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21E16A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21E16A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21E16A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21E16A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21E16A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21E16A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21E16A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21E16A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21E16A Serial Communication Interface 3 (SERCOM3) */
+ TCC0_IRQn = 15, /**< 15 SAMD21E16A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21E16A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21E16A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21E16A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21E16A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21E16A Basic Timer Counter 5 (TC5) */
+ ADC_IRQn = 23, /**< 23 SAMD21E16A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21E16A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21E16A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21E16A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21E16A Inter-IC Sound Interface (I2S) */
+
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
-
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnReservedM12;
- void* pfnReservedM11;
- void* pfnReservedM10;
- void* pfnReservedM9;
- void* pfnReservedM8;
- void* pfnReservedM7;
- void* pfnReservedM6;
- void* pfnSVC_Handler;
- void* pfnReservedM4;
- void* pfnReservedM3;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
-
- /* Peripheral handlers */
- void* pfnPM_Handler; /* 0 Power Manager */
- void* pfnSYSCTRL_Handler; /* 1 System Control */
- void* pfnWDT_Handler; /* 2 Watchdog Timer */
- void* pfnRTC_Handler; /* 3 Real-Time Counter */
- void* pfnEIC_Handler; /* 4 External Interrupt Controller */
- void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
- void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
- void* pfnUSB_Handler; /* 7 Universal Serial Bus */
- void* pfnEVSYS_Handler; /* 8 Event System Interface */
- void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
- void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
- void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
- void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
- void* pfnReserved13;
- void* pfnReserved14;
- void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
- void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
- void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
- void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
- void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
- void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
- void* pfnReserved21;
- void* pfnReserved22;
- void* pfnADC_Handler; /* 23 Analog Digital Converter */
- void* pfnAC_Handler; /* 24 Analog Comparators */
- void* pfnDAC_Handler; /* 25 Digital Analog Converter */
- void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
- void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+typedef struct _DeviceVectors {
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnReserved13;
+ void* pfnReserved14;
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnReserved21;
+ void* pfnReserved22;
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@@ -221,7 +219,7 @@ void I2S_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e16b.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e16b.h
index 01a22eb86c1..951d1f4889b 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e16b.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e16b.h
@@ -56,7 +56,7 @@
/*@{*/
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -90,95 +90,93 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
-typedef enum IRQn
-{
- /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
- /****** SAMD21E16B-specific Interrupt Numbers ***********************/
- PM_IRQn = 0, /**< 0 SAMD21E16B Power Manager (PM) */
- SYSCTRL_IRQn = 1, /**< 1 SAMD21E16B System Control (SYSCTRL) */
- WDT_IRQn = 2, /**< 2 SAMD21E16B Watchdog Timer (WDT) */
- RTC_IRQn = 3, /**< 3 SAMD21E16B Real-Time Counter (RTC) */
- EIC_IRQn = 4, /**< 4 SAMD21E16B External Interrupt Controller (EIC) */
- NVMCTRL_IRQn = 5, /**< 5 SAMD21E16B Non-Volatile Memory Controller (NVMCTRL) */
- DMAC_IRQn = 6, /**< 6 SAMD21E16B Direct Memory Access Controller (DMAC) */
- USB_IRQn = 7, /**< 7 SAMD21E16B Universal Serial Bus (USB) */
- EVSYS_IRQn = 8, /**< 8 SAMD21E16B Event System Interface (EVSYS) */
- SERCOM0_IRQn = 9, /**< 9 SAMD21E16B Serial Communication Interface 0 (SERCOM0) */
- SERCOM1_IRQn = 10, /**< 10 SAMD21E16B Serial Communication Interface 1 (SERCOM1) */
- SERCOM2_IRQn = 11, /**< 11 SAMD21E16B Serial Communication Interface 2 (SERCOM2) */
- SERCOM3_IRQn = 12, /**< 12 SAMD21E16B Serial Communication Interface 3 (SERCOM3) */
- TCC0_IRQn = 15, /**< 15 SAMD21E16B Timer Counter Control 0 (TCC0) */
- TCC1_IRQn = 16, /**< 16 SAMD21E16B Timer Counter Control 1 (TCC1) */
- TCC2_IRQn = 17, /**< 17 SAMD21E16B Timer Counter Control 2 (TCC2) */
- TC3_IRQn = 18, /**< 18 SAMD21E16B Basic Timer Counter 3 (TC3) */
- TC4_IRQn = 19, /**< 19 SAMD21E16B Basic Timer Counter 4 (TC4) */
- TC5_IRQn = 20, /**< 20 SAMD21E16B Basic Timer Counter 5 (TC5) */
- ADC_IRQn = 23, /**< 23 SAMD21E16B Analog Digital Converter (ADC) */
- AC_IRQn = 24, /**< 24 SAMD21E16B Analog Comparators (AC) */
- DAC_IRQn = 25, /**< 25 SAMD21E16B Digital Analog Converter (DAC) */
- PTC_IRQn = 26, /**< 26 SAMD21E16B Peripheral Touch Controller (PTC) */
- I2S_IRQn = 27, /**< 27 SAMD21E16B Inter-IC Sound Interface (I2S) */
-
- PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+typedef enum IRQn {
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21E16B-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21E16B Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21E16B System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21E16B Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21E16B Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21E16B External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21E16B Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21E16B Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21E16B Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21E16B Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21E16B Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21E16B Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21E16B Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21E16B Serial Communication Interface 3 (SERCOM3) */
+ TCC0_IRQn = 15, /**< 15 SAMD21E16B Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21E16B Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21E16B Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21E16B Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21E16B Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21E16B Basic Timer Counter 5 (TC5) */
+ ADC_IRQn = 23, /**< 23 SAMD21E16B Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21E16B Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21E16B Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21E16B Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21E16B Inter-IC Sound Interface (I2S) */
+
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
-
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnReservedM12;
- void* pfnReservedM11;
- void* pfnReservedM10;
- void* pfnReservedM9;
- void* pfnReservedM8;
- void* pfnReservedM7;
- void* pfnReservedM6;
- void* pfnSVC_Handler;
- void* pfnReservedM4;
- void* pfnReservedM3;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
-
- /* Peripheral handlers */
- void* pfnPM_Handler; /* 0 Power Manager */
- void* pfnSYSCTRL_Handler; /* 1 System Control */
- void* pfnWDT_Handler; /* 2 Watchdog Timer */
- void* pfnRTC_Handler; /* 3 Real-Time Counter */
- void* pfnEIC_Handler; /* 4 External Interrupt Controller */
- void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
- void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
- void* pfnUSB_Handler; /* 7 Universal Serial Bus */
- void* pfnEVSYS_Handler; /* 8 Event System Interface */
- void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
- void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
- void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
- void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
- void* pfnReserved13;
- void* pfnReserved14;
- void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
- void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
- void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
- void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
- void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
- void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
- void* pfnReserved21;
- void* pfnReserved22;
- void* pfnADC_Handler; /* 23 Analog Digital Converter */
- void* pfnAC_Handler; /* 24 Analog Comparators */
- void* pfnDAC_Handler; /* 25 Digital Analog Converter */
- void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
- void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
- void* pfnReserved28;
+typedef struct _DeviceVectors {
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnReserved13;
+ void* pfnReserved14;
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnReserved21;
+ void* pfnReserved22;
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+ void* pfnReserved28;
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@@ -219,7 +217,7 @@ void I2S_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e16bu.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e16bu.h
index 5b40278a71f..497b0d4fca9 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e16bu.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e16bu.h
@@ -56,7 +56,7 @@
/*@{*/
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -90,95 +90,93 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
-typedef enum IRQn
-{
- /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
- /****** SAMD21E16BU-specific Interrupt Numbers ***********************/
- PM_IRQn = 0, /**< 0 SAMD21E16BU Power Manager (PM) */
- SYSCTRL_IRQn = 1, /**< 1 SAMD21E16BU System Control (SYSCTRL) */
- WDT_IRQn = 2, /**< 2 SAMD21E16BU Watchdog Timer (WDT) */
- RTC_IRQn = 3, /**< 3 SAMD21E16BU Real-Time Counter (RTC) */
- EIC_IRQn = 4, /**< 4 SAMD21E16BU External Interrupt Controller (EIC) */
- NVMCTRL_IRQn = 5, /**< 5 SAMD21E16BU Non-Volatile Memory Controller (NVMCTRL) */
- DMAC_IRQn = 6, /**< 6 SAMD21E16BU Direct Memory Access Controller (DMAC) */
- USB_IRQn = 7, /**< 7 SAMD21E16BU Universal Serial Bus (USB) */
- EVSYS_IRQn = 8, /**< 8 SAMD21E16BU Event System Interface (EVSYS) */
- SERCOM0_IRQn = 9, /**< 9 SAMD21E16BU Serial Communication Interface 0 (SERCOM0) */
- SERCOM1_IRQn = 10, /**< 10 SAMD21E16BU Serial Communication Interface 1 (SERCOM1) */
- SERCOM2_IRQn = 11, /**< 11 SAMD21E16BU Serial Communication Interface 2 (SERCOM2) */
- SERCOM3_IRQn = 12, /**< 12 SAMD21E16BU Serial Communication Interface 3 (SERCOM3) */
- TCC0_IRQn = 15, /**< 15 SAMD21E16BU Timer Counter Control 0 (TCC0) */
- TCC1_IRQn = 16, /**< 16 SAMD21E16BU Timer Counter Control 1 (TCC1) */
- TCC2_IRQn = 17, /**< 17 SAMD21E16BU Timer Counter Control 2 (TCC2) */
- TC3_IRQn = 18, /**< 18 SAMD21E16BU Basic Timer Counter 3 (TC3) */
- TC4_IRQn = 19, /**< 19 SAMD21E16BU Basic Timer Counter 4 (TC4) */
- TC5_IRQn = 20, /**< 20 SAMD21E16BU Basic Timer Counter 5 (TC5) */
- ADC_IRQn = 23, /**< 23 SAMD21E16BU Analog Digital Converter (ADC) */
- AC_IRQn = 24, /**< 24 SAMD21E16BU Analog Comparators (AC) */
- DAC_IRQn = 25, /**< 25 SAMD21E16BU Digital Analog Converter (DAC) */
- PTC_IRQn = 26, /**< 26 SAMD21E16BU Peripheral Touch Controller (PTC) */
- I2S_IRQn = 27, /**< 27 SAMD21E16BU Inter-IC Sound Interface (I2S) */
-
- PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+typedef enum IRQn {
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21E16BU-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21E16BU Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21E16BU System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21E16BU Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21E16BU Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21E16BU External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21E16BU Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21E16BU Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21E16BU Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21E16BU Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21E16BU Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21E16BU Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21E16BU Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21E16BU Serial Communication Interface 3 (SERCOM3) */
+ TCC0_IRQn = 15, /**< 15 SAMD21E16BU Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21E16BU Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21E16BU Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21E16BU Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21E16BU Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21E16BU Basic Timer Counter 5 (TC5) */
+ ADC_IRQn = 23, /**< 23 SAMD21E16BU Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21E16BU Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21E16BU Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21E16BU Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21E16BU Inter-IC Sound Interface (I2S) */
+
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
-
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnReservedM12;
- void* pfnReservedM11;
- void* pfnReservedM10;
- void* pfnReservedM9;
- void* pfnReservedM8;
- void* pfnReservedM7;
- void* pfnReservedM6;
- void* pfnSVC_Handler;
- void* pfnReservedM4;
- void* pfnReservedM3;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
-
- /* Peripheral handlers */
- void* pfnPM_Handler; /* 0 Power Manager */
- void* pfnSYSCTRL_Handler; /* 1 System Control */
- void* pfnWDT_Handler; /* 2 Watchdog Timer */
- void* pfnRTC_Handler; /* 3 Real-Time Counter */
- void* pfnEIC_Handler; /* 4 External Interrupt Controller */
- void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
- void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
- void* pfnUSB_Handler; /* 7 Universal Serial Bus */
- void* pfnEVSYS_Handler; /* 8 Event System Interface */
- void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
- void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
- void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
- void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
- void* pfnReserved13;
- void* pfnReserved14;
- void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
- void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
- void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
- void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
- void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
- void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
- void* pfnReserved21;
- void* pfnReserved22;
- void* pfnADC_Handler; /* 23 Analog Digital Converter */
- void* pfnAC_Handler; /* 24 Analog Comparators */
- void* pfnDAC_Handler; /* 25 Digital Analog Converter */
- void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
- void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
- void* pfnReserved28;
+typedef struct _DeviceVectors {
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnReserved13;
+ void* pfnReserved14;
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnReserved21;
+ void* pfnReserved22;
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+ void* pfnReserved28;
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@@ -219,7 +217,7 @@ void I2S_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e16l.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e16l.h
index aa6cacb3b73..9ca3de0e884 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e16l.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e16l.h
@@ -56,7 +56,7 @@
/*@{*/
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -90,93 +90,91 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
-typedef enum IRQn
-{
- /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
- /****** SAMD21E16L-specific Interrupt Numbers ***********************/
- PM_IRQn = 0, /**< 0 SAMD21E16L Power Manager (PM) */
- SYSCTRL_IRQn = 1, /**< 1 SAMD21E16L System Control (SYSCTRL) */
- WDT_IRQn = 2, /**< 2 SAMD21E16L Watchdog Timer (WDT) */
- RTC_IRQn = 3, /**< 3 SAMD21E16L Real-Time Counter (RTC) */
- EIC_IRQn = 4, /**< 4 SAMD21E16L External Interrupt Controller (EIC) */
- NVMCTRL_IRQn = 5, /**< 5 SAMD21E16L Non-Volatile Memory Controller (NVMCTRL) */
- DMAC_IRQn = 6, /**< 6 SAMD21E16L Direct Memory Access Controller (DMAC) */
- EVSYS_IRQn = 8, /**< 8 SAMD21E16L Event System Interface (EVSYS) */
- SERCOM0_IRQn = 9, /**< 9 SAMD21E16L Serial Communication Interface 0 (SERCOM0) */
- SERCOM1_IRQn = 10, /**< 10 SAMD21E16L Serial Communication Interface 1 (SERCOM1) */
- SERCOM2_IRQn = 11, /**< 11 SAMD21E16L Serial Communication Interface 2 (SERCOM2) */
- SERCOM3_IRQn = 12, /**< 12 SAMD21E16L Serial Communication Interface 3 (SERCOM3) */
- TCC0_IRQn = 15, /**< 15 SAMD21E16L Timer Counter Control 0 (TCC0) */
- TCC1_IRQn = 16, /**< 16 SAMD21E16L Timer Counter Control 1 (TCC1) */
- TCC2_IRQn = 17, /**< 17 SAMD21E16L Timer Counter Control 2 (TCC2) */
- TC3_IRQn = 18, /**< 18 SAMD21E16L Basic Timer Counter 3 (TC3) */
- TC4_IRQn = 19, /**< 19 SAMD21E16L Basic Timer Counter 4 (TC4) */
- TC5_IRQn = 20, /**< 20 SAMD21E16L Basic Timer Counter 5 (TC5) */
- ADC_IRQn = 23, /**< 23 SAMD21E16L Analog Digital Converter (ADC) */
- AC_IRQn = 24, /**< 24 SAMD21E16L Analog Comparators (AC) */
- DAC_IRQn = 25, /**< 25 SAMD21E16L Digital Analog Converter (DAC) */
- AC1_IRQn = 28, /**< 28 SAMD21E16L Analog Comparators 1 (AC1) */
-
- PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */
+typedef enum IRQn {
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21E16L-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21E16L Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21E16L System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21E16L Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21E16L Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21E16L External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21E16L Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21E16L Direct Memory Access Controller (DMAC) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21E16L Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21E16L Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21E16L Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21E16L Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21E16L Serial Communication Interface 3 (SERCOM3) */
+ TCC0_IRQn = 15, /**< 15 SAMD21E16L Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21E16L Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21E16L Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21E16L Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21E16L Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21E16L Basic Timer Counter 5 (TC5) */
+ ADC_IRQn = 23, /**< 23 SAMD21E16L Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21E16L Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21E16L Digital Analog Converter (DAC) */
+ AC1_IRQn = 28, /**< 28 SAMD21E16L Analog Comparators 1 (AC1) */
+
+ PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */
} IRQn_Type;
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
-
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnReservedM12;
- void* pfnReservedM11;
- void* pfnReservedM10;
- void* pfnReservedM9;
- void* pfnReservedM8;
- void* pfnReservedM7;
- void* pfnReservedM6;
- void* pfnSVC_Handler;
- void* pfnReservedM4;
- void* pfnReservedM3;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
-
- /* Peripheral handlers */
- void* pfnPM_Handler; /* 0 Power Manager */
- void* pfnSYSCTRL_Handler; /* 1 System Control */
- void* pfnWDT_Handler; /* 2 Watchdog Timer */
- void* pfnRTC_Handler; /* 3 Real-Time Counter */
- void* pfnEIC_Handler; /* 4 External Interrupt Controller */
- void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
- void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
- void* pfnReserved7;
- void* pfnEVSYS_Handler; /* 8 Event System Interface */
- void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
- void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
- void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
- void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
- void* pfnReserved13;
- void* pfnReserved14;
- void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
- void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
- void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
- void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
- void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
- void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
- void* pfnReserved21;
- void* pfnReserved22;
- void* pfnADC_Handler; /* 23 Analog Digital Converter */
- void* pfnAC_Handler; /* 24 Analog Comparators */
- void* pfnDAC_Handler; /* 25 Digital Analog Converter */
- void* pfnReserved26;
- void* pfnReserved27;
- void* pfnAC1_Handler; /* 28 Analog Comparators 1 */
+typedef struct _DeviceVectors {
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnReserved7;
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnReserved13;
+ void* pfnReserved14;
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnReserved21;
+ void* pfnReserved22;
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnReserved26;
+ void* pfnReserved27;
+ void* pfnAC1_Handler; /* 28 Analog Comparators 1 */
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@@ -215,7 +213,7 @@ void AC1_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e17a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e17a.h
index 00912246bca..9e433c26e6f 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e17a.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e17a.h
@@ -59,7 +59,7 @@
/*@{*/
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -93,94 +93,92 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
-typedef enum IRQn
-{
- /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
- /****** SAMD21E17A-specific Interrupt Numbers ***********************/
- PM_IRQn = 0, /**< 0 SAMD21E17A Power Manager (PM) */
- SYSCTRL_IRQn = 1, /**< 1 SAMD21E17A System Control (SYSCTRL) */
- WDT_IRQn = 2, /**< 2 SAMD21E17A Watchdog Timer (WDT) */
- RTC_IRQn = 3, /**< 3 SAMD21E17A Real-Time Counter (RTC) */
- EIC_IRQn = 4, /**< 4 SAMD21E17A External Interrupt Controller (EIC) */
- NVMCTRL_IRQn = 5, /**< 5 SAMD21E17A Non-Volatile Memory Controller (NVMCTRL) */
- DMAC_IRQn = 6, /**< 6 SAMD21E17A Direct Memory Access Controller (DMAC) */
- USB_IRQn = 7, /**< 7 SAMD21E17A Universal Serial Bus (USB) */
- EVSYS_IRQn = 8, /**< 8 SAMD21E17A Event System Interface (EVSYS) */
- SERCOM0_IRQn = 9, /**< 9 SAMD21E17A Serial Communication Interface 0 (SERCOM0) */
- SERCOM1_IRQn = 10, /**< 10 SAMD21E17A Serial Communication Interface 1 (SERCOM1) */
- SERCOM2_IRQn = 11, /**< 11 SAMD21E17A Serial Communication Interface 2 (SERCOM2) */
- SERCOM3_IRQn = 12, /**< 12 SAMD21E17A Serial Communication Interface 3 (SERCOM3) */
- TCC0_IRQn = 15, /**< 15 SAMD21E17A Timer Counter Control 0 (TCC0) */
- TCC1_IRQn = 16, /**< 16 SAMD21E17A Timer Counter Control 1 (TCC1) */
- TCC2_IRQn = 17, /**< 17 SAMD21E17A Timer Counter Control 2 (TCC2) */
- TC3_IRQn = 18, /**< 18 SAMD21E17A Basic Timer Counter 3 (TC3) */
- TC4_IRQn = 19, /**< 19 SAMD21E17A Basic Timer Counter 4 (TC4) */
- TC5_IRQn = 20, /**< 20 SAMD21E17A Basic Timer Counter 5 (TC5) */
- ADC_IRQn = 23, /**< 23 SAMD21E17A Analog Digital Converter (ADC) */
- AC_IRQn = 24, /**< 24 SAMD21E17A Analog Comparators (AC) */
- DAC_IRQn = 25, /**< 25 SAMD21E17A Digital Analog Converter (DAC) */
- PTC_IRQn = 26, /**< 26 SAMD21E17A Peripheral Touch Controller (PTC) */
- I2S_IRQn = 27, /**< 27 SAMD21E17A Inter-IC Sound Interface (I2S) */
-
- PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+typedef enum IRQn {
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21E17A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21E17A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21E17A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21E17A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21E17A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21E17A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21E17A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21E17A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21E17A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21E17A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21E17A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21E17A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21E17A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21E17A Serial Communication Interface 3 (SERCOM3) */
+ TCC0_IRQn = 15, /**< 15 SAMD21E17A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21E17A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21E17A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21E17A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21E17A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21E17A Basic Timer Counter 5 (TC5) */
+ ADC_IRQn = 23, /**< 23 SAMD21E17A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21E17A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21E17A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21E17A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21E17A Inter-IC Sound Interface (I2S) */
+
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
-
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnReservedM12;
- void* pfnReservedM11;
- void* pfnReservedM10;
- void* pfnReservedM9;
- void* pfnReservedM8;
- void* pfnReservedM7;
- void* pfnReservedM6;
- void* pfnSVC_Handler;
- void* pfnReservedM4;
- void* pfnReservedM3;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
-
- /* Peripheral handlers */
- void* pfnPM_Handler; /* 0 Power Manager */
- void* pfnSYSCTRL_Handler; /* 1 System Control */
- void* pfnWDT_Handler; /* 2 Watchdog Timer */
- void* pfnRTC_Handler; /* 3 Real-Time Counter */
- void* pfnEIC_Handler; /* 4 External Interrupt Controller */
- void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
- void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
- void* pfnUSB_Handler; /* 7 Universal Serial Bus */
- void* pfnEVSYS_Handler; /* 8 Event System Interface */
- void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
- void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
- void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
- void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
- void* pfnReserved13;
- void* pfnReserved14;
- void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
- void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
- void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
- void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
- void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
- void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
- void* pfnReserved21;
- void* pfnReserved22;
- void* pfnADC_Handler; /* 23 Analog Digital Converter */
- void* pfnAC_Handler; /* 24 Analog Comparators */
- void* pfnDAC_Handler; /* 25 Digital Analog Converter */
- void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
- void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+typedef struct _DeviceVectors {
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnReserved13;
+ void* pfnReserved14;
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnReserved21;
+ void* pfnReserved22;
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@@ -221,7 +219,7 @@ void I2S_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e18a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e18a.h
index 8e09efc5e90..6d51d950977 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e18a.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e18a.h
@@ -59,7 +59,7 @@
/*@{*/
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -93,94 +93,92 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
-typedef enum IRQn
-{
- /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
- /****** SAMD21E18A-specific Interrupt Numbers ***********************/
- PM_IRQn = 0, /**< 0 SAMD21E18A Power Manager (PM) */
- SYSCTRL_IRQn = 1, /**< 1 SAMD21E18A System Control (SYSCTRL) */
- WDT_IRQn = 2, /**< 2 SAMD21E18A Watchdog Timer (WDT) */
- RTC_IRQn = 3, /**< 3 SAMD21E18A Real-Time Counter (RTC) */
- EIC_IRQn = 4, /**< 4 SAMD21E18A External Interrupt Controller (EIC) */
- NVMCTRL_IRQn = 5, /**< 5 SAMD21E18A Non-Volatile Memory Controller (NVMCTRL) */
- DMAC_IRQn = 6, /**< 6 SAMD21E18A Direct Memory Access Controller (DMAC) */
- USB_IRQn = 7, /**< 7 SAMD21E18A Universal Serial Bus (USB) */
- EVSYS_IRQn = 8, /**< 8 SAMD21E18A Event System Interface (EVSYS) */
- SERCOM0_IRQn = 9, /**< 9 SAMD21E18A Serial Communication Interface 0 (SERCOM0) */
- SERCOM1_IRQn = 10, /**< 10 SAMD21E18A Serial Communication Interface 1 (SERCOM1) */
- SERCOM2_IRQn = 11, /**< 11 SAMD21E18A Serial Communication Interface 2 (SERCOM2) */
- SERCOM3_IRQn = 12, /**< 12 SAMD21E18A Serial Communication Interface 3 (SERCOM3) */
- TCC0_IRQn = 15, /**< 15 SAMD21E18A Timer Counter Control 0 (TCC0) */
- TCC1_IRQn = 16, /**< 16 SAMD21E18A Timer Counter Control 1 (TCC1) */
- TCC2_IRQn = 17, /**< 17 SAMD21E18A Timer Counter Control 2 (TCC2) */
- TC3_IRQn = 18, /**< 18 SAMD21E18A Basic Timer Counter 3 (TC3) */
- TC4_IRQn = 19, /**< 19 SAMD21E18A Basic Timer Counter 4 (TC4) */
- TC5_IRQn = 20, /**< 20 SAMD21E18A Basic Timer Counter 5 (TC5) */
- ADC_IRQn = 23, /**< 23 SAMD21E18A Analog Digital Converter (ADC) */
- AC_IRQn = 24, /**< 24 SAMD21E18A Analog Comparators (AC) */
- DAC_IRQn = 25, /**< 25 SAMD21E18A Digital Analog Converter (DAC) */
- PTC_IRQn = 26, /**< 26 SAMD21E18A Peripheral Touch Controller (PTC) */
- I2S_IRQn = 27, /**< 27 SAMD21E18A Inter-IC Sound Interface (I2S) */
-
- PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+typedef enum IRQn {
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21E18A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21E18A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21E18A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21E18A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21E18A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21E18A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21E18A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21E18A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21E18A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21E18A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21E18A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21E18A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21E18A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21E18A Serial Communication Interface 3 (SERCOM3) */
+ TCC0_IRQn = 15, /**< 15 SAMD21E18A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21E18A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21E18A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21E18A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21E18A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21E18A Basic Timer Counter 5 (TC5) */
+ ADC_IRQn = 23, /**< 23 SAMD21E18A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21E18A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21E18A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21E18A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21E18A Inter-IC Sound Interface (I2S) */
+
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
-
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnReservedM12;
- void* pfnReservedM11;
- void* pfnReservedM10;
- void* pfnReservedM9;
- void* pfnReservedM8;
- void* pfnReservedM7;
- void* pfnReservedM6;
- void* pfnSVC_Handler;
- void* pfnReservedM4;
- void* pfnReservedM3;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
-
- /* Peripheral handlers */
- void* pfnPM_Handler; /* 0 Power Manager */
- void* pfnSYSCTRL_Handler; /* 1 System Control */
- void* pfnWDT_Handler; /* 2 Watchdog Timer */
- void* pfnRTC_Handler; /* 3 Real-Time Counter */
- void* pfnEIC_Handler; /* 4 External Interrupt Controller */
- void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
- void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
- void* pfnUSB_Handler; /* 7 Universal Serial Bus */
- void* pfnEVSYS_Handler; /* 8 Event System Interface */
- void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
- void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
- void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
- void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
- void* pfnReserved13;
- void* pfnReserved14;
- void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
- void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
- void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
- void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
- void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
- void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
- void* pfnReserved21;
- void* pfnReserved22;
- void* pfnADC_Handler; /* 23 Analog Digital Converter */
- void* pfnAC_Handler; /* 24 Analog Comparators */
- void* pfnDAC_Handler; /* 25 Digital Analog Converter */
- void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
- void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+typedef struct _DeviceVectors {
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnReserved13;
+ void* pfnReserved14;
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnReserved21;
+ void* pfnReserved22;
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@@ -221,7 +219,7 @@ void I2S_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g15a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g15a.h
index 880500e57d5..65129029c05 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g15a.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g15a.h
@@ -59,7 +59,7 @@
/*@{*/
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -93,96 +93,94 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
-typedef enum IRQn
-{
- /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
- /****** SAMD21G15A-specific Interrupt Numbers ***********************/
- PM_IRQn = 0, /**< 0 SAMD21G15A Power Manager (PM) */
- SYSCTRL_IRQn = 1, /**< 1 SAMD21G15A System Control (SYSCTRL) */
- WDT_IRQn = 2, /**< 2 SAMD21G15A Watchdog Timer (WDT) */
- RTC_IRQn = 3, /**< 3 SAMD21G15A Real-Time Counter (RTC) */
- EIC_IRQn = 4, /**< 4 SAMD21G15A External Interrupt Controller (EIC) */
- NVMCTRL_IRQn = 5, /**< 5 SAMD21G15A Non-Volatile Memory Controller (NVMCTRL) */
- DMAC_IRQn = 6, /**< 6 SAMD21G15A Direct Memory Access Controller (DMAC) */
- USB_IRQn = 7, /**< 7 SAMD21G15A Universal Serial Bus (USB) */
- EVSYS_IRQn = 8, /**< 8 SAMD21G15A Event System Interface (EVSYS) */
- SERCOM0_IRQn = 9, /**< 9 SAMD21G15A Serial Communication Interface 0 (SERCOM0) */
- SERCOM1_IRQn = 10, /**< 10 SAMD21G15A Serial Communication Interface 1 (SERCOM1) */
- SERCOM2_IRQn = 11, /**< 11 SAMD21G15A Serial Communication Interface 2 (SERCOM2) */
- SERCOM3_IRQn = 12, /**< 12 SAMD21G15A Serial Communication Interface 3 (SERCOM3) */
- SERCOM4_IRQn = 13, /**< 13 SAMD21G15A Serial Communication Interface 4 (SERCOM4) */
- SERCOM5_IRQn = 14, /**< 14 SAMD21G15A Serial Communication Interface 5 (SERCOM5) */
- TCC0_IRQn = 15, /**< 15 SAMD21G15A Timer Counter Control 0 (TCC0) */
- TCC1_IRQn = 16, /**< 16 SAMD21G15A Timer Counter Control 1 (TCC1) */
- TCC2_IRQn = 17, /**< 17 SAMD21G15A Timer Counter Control 2 (TCC2) */
- TC3_IRQn = 18, /**< 18 SAMD21G15A Basic Timer Counter 3 (TC3) */
- TC4_IRQn = 19, /**< 19 SAMD21G15A Basic Timer Counter 4 (TC4) */
- TC5_IRQn = 20, /**< 20 SAMD21G15A Basic Timer Counter 5 (TC5) */
- ADC_IRQn = 23, /**< 23 SAMD21G15A Analog Digital Converter (ADC) */
- AC_IRQn = 24, /**< 24 SAMD21G15A Analog Comparators (AC) */
- DAC_IRQn = 25, /**< 25 SAMD21G15A Digital Analog Converter (DAC) */
- PTC_IRQn = 26, /**< 26 SAMD21G15A Peripheral Touch Controller (PTC) */
- I2S_IRQn = 27, /**< 27 SAMD21G15A Inter-IC Sound Interface (I2S) */
-
- PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+typedef enum IRQn {
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21G15A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21G15A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21G15A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21G15A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21G15A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21G15A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21G15A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21G15A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21G15A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21G15A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21G15A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21G15A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21G15A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21G15A Serial Communication Interface 3 (SERCOM3) */
+ SERCOM4_IRQn = 13, /**< 13 SAMD21G15A Serial Communication Interface 4 (SERCOM4) */
+ SERCOM5_IRQn = 14, /**< 14 SAMD21G15A Serial Communication Interface 5 (SERCOM5) */
+ TCC0_IRQn = 15, /**< 15 SAMD21G15A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21G15A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21G15A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21G15A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21G15A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21G15A Basic Timer Counter 5 (TC5) */
+ ADC_IRQn = 23, /**< 23 SAMD21G15A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21G15A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21G15A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21G15A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21G15A Inter-IC Sound Interface (I2S) */
+
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
-
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnReservedM12;
- void* pfnReservedM11;
- void* pfnReservedM10;
- void* pfnReservedM9;
- void* pfnReservedM8;
- void* pfnReservedM7;
- void* pfnReservedM6;
- void* pfnSVC_Handler;
- void* pfnReservedM4;
- void* pfnReservedM3;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
-
- /* Peripheral handlers */
- void* pfnPM_Handler; /* 0 Power Manager */
- void* pfnSYSCTRL_Handler; /* 1 System Control */
- void* pfnWDT_Handler; /* 2 Watchdog Timer */
- void* pfnRTC_Handler; /* 3 Real-Time Counter */
- void* pfnEIC_Handler; /* 4 External Interrupt Controller */
- void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
- void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
- void* pfnUSB_Handler; /* 7 Universal Serial Bus */
- void* pfnEVSYS_Handler; /* 8 Event System Interface */
- void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
- void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
- void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
- void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
- void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
- void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
- void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
- void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
- void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
- void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
- void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
- void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
- void* pfnReserved21;
- void* pfnReserved22;
- void* pfnADC_Handler; /* 23 Analog Digital Converter */
- void* pfnAC_Handler; /* 24 Analog Comparators */
- void* pfnDAC_Handler; /* 25 Digital Analog Converter */
- void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
- void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+typedef struct _DeviceVectors {
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
+ void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnReserved21;
+ void* pfnReserved22;
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@@ -225,7 +223,7 @@ void I2S_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g15b.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g15b.h
index 0c883a40ebc..005b09076cf 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g15b.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g15b.h
@@ -56,7 +56,7 @@
/*@{*/
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -90,97 +90,95 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
-typedef enum IRQn
-{
- /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
- /****** SAMD21G15B-specific Interrupt Numbers ***********************/
- PM_IRQn = 0, /**< 0 SAMD21G15B Power Manager (PM) */
- SYSCTRL_IRQn = 1, /**< 1 SAMD21G15B System Control (SYSCTRL) */
- WDT_IRQn = 2, /**< 2 SAMD21G15B Watchdog Timer (WDT) */
- RTC_IRQn = 3, /**< 3 SAMD21G15B Real-Time Counter (RTC) */
- EIC_IRQn = 4, /**< 4 SAMD21G15B External Interrupt Controller (EIC) */
- NVMCTRL_IRQn = 5, /**< 5 SAMD21G15B Non-Volatile Memory Controller (NVMCTRL) */
- DMAC_IRQn = 6, /**< 6 SAMD21G15B Direct Memory Access Controller (DMAC) */
- USB_IRQn = 7, /**< 7 SAMD21G15B Universal Serial Bus (USB) */
- EVSYS_IRQn = 8, /**< 8 SAMD21G15B Event System Interface (EVSYS) */
- SERCOM0_IRQn = 9, /**< 9 SAMD21G15B Serial Communication Interface 0 (SERCOM0) */
- SERCOM1_IRQn = 10, /**< 10 SAMD21G15B Serial Communication Interface 1 (SERCOM1) */
- SERCOM2_IRQn = 11, /**< 11 SAMD21G15B Serial Communication Interface 2 (SERCOM2) */
- SERCOM3_IRQn = 12, /**< 12 SAMD21G15B Serial Communication Interface 3 (SERCOM3) */
- SERCOM4_IRQn = 13, /**< 13 SAMD21G15B Serial Communication Interface 4 (SERCOM4) */
- SERCOM5_IRQn = 14, /**< 14 SAMD21G15B Serial Communication Interface 5 (SERCOM5) */
- TCC0_IRQn = 15, /**< 15 SAMD21G15B Timer Counter Control 0 (TCC0) */
- TCC1_IRQn = 16, /**< 16 SAMD21G15B Timer Counter Control 1 (TCC1) */
- TCC2_IRQn = 17, /**< 17 SAMD21G15B Timer Counter Control 2 (TCC2) */
- TC3_IRQn = 18, /**< 18 SAMD21G15B Basic Timer Counter 3 (TC3) */
- TC4_IRQn = 19, /**< 19 SAMD21G15B Basic Timer Counter 4 (TC4) */
- TC5_IRQn = 20, /**< 20 SAMD21G15B Basic Timer Counter 5 (TC5) */
- ADC_IRQn = 23, /**< 23 SAMD21G15B Analog Digital Converter (ADC) */
- AC_IRQn = 24, /**< 24 SAMD21G15B Analog Comparators (AC) */
- DAC_IRQn = 25, /**< 25 SAMD21G15B Digital Analog Converter (DAC) */
- PTC_IRQn = 26, /**< 26 SAMD21G15B Peripheral Touch Controller (PTC) */
- I2S_IRQn = 27, /**< 27 SAMD21G15B Inter-IC Sound Interface (I2S) */
-
- PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+typedef enum IRQn {
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21G15B-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21G15B Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21G15B System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21G15B Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21G15B Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21G15B External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21G15B Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21G15B Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21G15B Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21G15B Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21G15B Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21G15B Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21G15B Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21G15B Serial Communication Interface 3 (SERCOM3) */
+ SERCOM4_IRQn = 13, /**< 13 SAMD21G15B Serial Communication Interface 4 (SERCOM4) */
+ SERCOM5_IRQn = 14, /**< 14 SAMD21G15B Serial Communication Interface 5 (SERCOM5) */
+ TCC0_IRQn = 15, /**< 15 SAMD21G15B Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21G15B Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21G15B Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21G15B Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21G15B Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21G15B Basic Timer Counter 5 (TC5) */
+ ADC_IRQn = 23, /**< 23 SAMD21G15B Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21G15B Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21G15B Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21G15B Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21G15B Inter-IC Sound Interface (I2S) */
+
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
-
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnReservedM12;
- void* pfnReservedM11;
- void* pfnReservedM10;
- void* pfnReservedM9;
- void* pfnReservedM8;
- void* pfnReservedM7;
- void* pfnReservedM6;
- void* pfnSVC_Handler;
- void* pfnReservedM4;
- void* pfnReservedM3;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
-
- /* Peripheral handlers */
- void* pfnPM_Handler; /* 0 Power Manager */
- void* pfnSYSCTRL_Handler; /* 1 System Control */
- void* pfnWDT_Handler; /* 2 Watchdog Timer */
- void* pfnRTC_Handler; /* 3 Real-Time Counter */
- void* pfnEIC_Handler; /* 4 External Interrupt Controller */
- void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
- void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
- void* pfnUSB_Handler; /* 7 Universal Serial Bus */
- void* pfnEVSYS_Handler; /* 8 Event System Interface */
- void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
- void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
- void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
- void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
- void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
- void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
- void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
- void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
- void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
- void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
- void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
- void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
- void* pfnReserved21;
- void* pfnReserved22;
- void* pfnADC_Handler; /* 23 Analog Digital Converter */
- void* pfnAC_Handler; /* 24 Analog Comparators */
- void* pfnDAC_Handler; /* 25 Digital Analog Converter */
- void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
- void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
- void* pfnReserved28;
+typedef struct _DeviceVectors {
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
+ void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnReserved21;
+ void* pfnReserved22;
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+ void* pfnReserved28;
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@@ -223,7 +221,7 @@ void I2S_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g16a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g16a.h
index b30c493c292..707fbd3e89c 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g16a.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g16a.h
@@ -59,7 +59,7 @@
/*@{*/
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -93,96 +93,94 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
-typedef enum IRQn
-{
- /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
- /****** SAMD21G16A-specific Interrupt Numbers ***********************/
- PM_IRQn = 0, /**< 0 SAMD21G16A Power Manager (PM) */
- SYSCTRL_IRQn = 1, /**< 1 SAMD21G16A System Control (SYSCTRL) */
- WDT_IRQn = 2, /**< 2 SAMD21G16A Watchdog Timer (WDT) */
- RTC_IRQn = 3, /**< 3 SAMD21G16A Real-Time Counter (RTC) */
- EIC_IRQn = 4, /**< 4 SAMD21G16A External Interrupt Controller (EIC) */
- NVMCTRL_IRQn = 5, /**< 5 SAMD21G16A Non-Volatile Memory Controller (NVMCTRL) */
- DMAC_IRQn = 6, /**< 6 SAMD21G16A Direct Memory Access Controller (DMAC) */
- USB_IRQn = 7, /**< 7 SAMD21G16A Universal Serial Bus (USB) */
- EVSYS_IRQn = 8, /**< 8 SAMD21G16A Event System Interface (EVSYS) */
- SERCOM0_IRQn = 9, /**< 9 SAMD21G16A Serial Communication Interface 0 (SERCOM0) */
- SERCOM1_IRQn = 10, /**< 10 SAMD21G16A Serial Communication Interface 1 (SERCOM1) */
- SERCOM2_IRQn = 11, /**< 11 SAMD21G16A Serial Communication Interface 2 (SERCOM2) */
- SERCOM3_IRQn = 12, /**< 12 SAMD21G16A Serial Communication Interface 3 (SERCOM3) */
- SERCOM4_IRQn = 13, /**< 13 SAMD21G16A Serial Communication Interface 4 (SERCOM4) */
- SERCOM5_IRQn = 14, /**< 14 SAMD21G16A Serial Communication Interface 5 (SERCOM5) */
- TCC0_IRQn = 15, /**< 15 SAMD21G16A Timer Counter Control 0 (TCC0) */
- TCC1_IRQn = 16, /**< 16 SAMD21G16A Timer Counter Control 1 (TCC1) */
- TCC2_IRQn = 17, /**< 17 SAMD21G16A Timer Counter Control 2 (TCC2) */
- TC3_IRQn = 18, /**< 18 SAMD21G16A Basic Timer Counter 3 (TC3) */
- TC4_IRQn = 19, /**< 19 SAMD21G16A Basic Timer Counter 4 (TC4) */
- TC5_IRQn = 20, /**< 20 SAMD21G16A Basic Timer Counter 5 (TC5) */
- ADC_IRQn = 23, /**< 23 SAMD21G16A Analog Digital Converter (ADC) */
- AC_IRQn = 24, /**< 24 SAMD21G16A Analog Comparators (AC) */
- DAC_IRQn = 25, /**< 25 SAMD21G16A Digital Analog Converter (DAC) */
- PTC_IRQn = 26, /**< 26 SAMD21G16A Peripheral Touch Controller (PTC) */
- I2S_IRQn = 27, /**< 27 SAMD21G16A Inter-IC Sound Interface (I2S) */
-
- PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+typedef enum IRQn {
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21G16A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21G16A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21G16A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21G16A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21G16A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21G16A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21G16A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21G16A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21G16A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21G16A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21G16A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21G16A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21G16A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21G16A Serial Communication Interface 3 (SERCOM3) */
+ SERCOM4_IRQn = 13, /**< 13 SAMD21G16A Serial Communication Interface 4 (SERCOM4) */
+ SERCOM5_IRQn = 14, /**< 14 SAMD21G16A Serial Communication Interface 5 (SERCOM5) */
+ TCC0_IRQn = 15, /**< 15 SAMD21G16A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21G16A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21G16A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21G16A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21G16A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21G16A Basic Timer Counter 5 (TC5) */
+ ADC_IRQn = 23, /**< 23 SAMD21G16A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21G16A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21G16A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21G16A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21G16A Inter-IC Sound Interface (I2S) */
+
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
-
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnReservedM12;
- void* pfnReservedM11;
- void* pfnReservedM10;
- void* pfnReservedM9;
- void* pfnReservedM8;
- void* pfnReservedM7;
- void* pfnReservedM6;
- void* pfnSVC_Handler;
- void* pfnReservedM4;
- void* pfnReservedM3;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
-
- /* Peripheral handlers */
- void* pfnPM_Handler; /* 0 Power Manager */
- void* pfnSYSCTRL_Handler; /* 1 System Control */
- void* pfnWDT_Handler; /* 2 Watchdog Timer */
- void* pfnRTC_Handler; /* 3 Real-Time Counter */
- void* pfnEIC_Handler; /* 4 External Interrupt Controller */
- void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
- void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
- void* pfnUSB_Handler; /* 7 Universal Serial Bus */
- void* pfnEVSYS_Handler; /* 8 Event System Interface */
- void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
- void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
- void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
- void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
- void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
- void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
- void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
- void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
- void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
- void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
- void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
- void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
- void* pfnReserved21;
- void* pfnReserved22;
- void* pfnADC_Handler; /* 23 Analog Digital Converter */
- void* pfnAC_Handler; /* 24 Analog Comparators */
- void* pfnDAC_Handler; /* 25 Digital Analog Converter */
- void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
- void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+typedef struct _DeviceVectors {
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
+ void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnReserved21;
+ void* pfnReserved22;
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@@ -225,7 +223,7 @@ void I2S_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g16b.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g16b.h
index 8e6e90aa403..1703045c4e4 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g16b.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g16b.h
@@ -56,7 +56,7 @@
/*@{*/
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -90,97 +90,95 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
-typedef enum IRQn
-{
- /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
- /****** SAMD21G16B-specific Interrupt Numbers ***********************/
- PM_IRQn = 0, /**< 0 SAMD21G16B Power Manager (PM) */
- SYSCTRL_IRQn = 1, /**< 1 SAMD21G16B System Control (SYSCTRL) */
- WDT_IRQn = 2, /**< 2 SAMD21G16B Watchdog Timer (WDT) */
- RTC_IRQn = 3, /**< 3 SAMD21G16B Real-Time Counter (RTC) */
- EIC_IRQn = 4, /**< 4 SAMD21G16B External Interrupt Controller (EIC) */
- NVMCTRL_IRQn = 5, /**< 5 SAMD21G16B Non-Volatile Memory Controller (NVMCTRL) */
- DMAC_IRQn = 6, /**< 6 SAMD21G16B Direct Memory Access Controller (DMAC) */
- USB_IRQn = 7, /**< 7 SAMD21G16B Universal Serial Bus (USB) */
- EVSYS_IRQn = 8, /**< 8 SAMD21G16B Event System Interface (EVSYS) */
- SERCOM0_IRQn = 9, /**< 9 SAMD21G16B Serial Communication Interface 0 (SERCOM0) */
- SERCOM1_IRQn = 10, /**< 10 SAMD21G16B Serial Communication Interface 1 (SERCOM1) */
- SERCOM2_IRQn = 11, /**< 11 SAMD21G16B Serial Communication Interface 2 (SERCOM2) */
- SERCOM3_IRQn = 12, /**< 12 SAMD21G16B Serial Communication Interface 3 (SERCOM3) */
- SERCOM4_IRQn = 13, /**< 13 SAMD21G16B Serial Communication Interface 4 (SERCOM4) */
- SERCOM5_IRQn = 14, /**< 14 SAMD21G16B Serial Communication Interface 5 (SERCOM5) */
- TCC0_IRQn = 15, /**< 15 SAMD21G16B Timer Counter Control 0 (TCC0) */
- TCC1_IRQn = 16, /**< 16 SAMD21G16B Timer Counter Control 1 (TCC1) */
- TCC2_IRQn = 17, /**< 17 SAMD21G16B Timer Counter Control 2 (TCC2) */
- TC3_IRQn = 18, /**< 18 SAMD21G16B Basic Timer Counter 3 (TC3) */
- TC4_IRQn = 19, /**< 19 SAMD21G16B Basic Timer Counter 4 (TC4) */
- TC5_IRQn = 20, /**< 20 SAMD21G16B Basic Timer Counter 5 (TC5) */
- ADC_IRQn = 23, /**< 23 SAMD21G16B Analog Digital Converter (ADC) */
- AC_IRQn = 24, /**< 24 SAMD21G16B Analog Comparators (AC) */
- DAC_IRQn = 25, /**< 25 SAMD21G16B Digital Analog Converter (DAC) */
- PTC_IRQn = 26, /**< 26 SAMD21G16B Peripheral Touch Controller (PTC) */
- I2S_IRQn = 27, /**< 27 SAMD21G16B Inter-IC Sound Interface (I2S) */
-
- PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+typedef enum IRQn {
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21G16B-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21G16B Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21G16B System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21G16B Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21G16B Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21G16B External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21G16B Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21G16B Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21G16B Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21G16B Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21G16B Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21G16B Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21G16B Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21G16B Serial Communication Interface 3 (SERCOM3) */
+ SERCOM4_IRQn = 13, /**< 13 SAMD21G16B Serial Communication Interface 4 (SERCOM4) */
+ SERCOM5_IRQn = 14, /**< 14 SAMD21G16B Serial Communication Interface 5 (SERCOM5) */
+ TCC0_IRQn = 15, /**< 15 SAMD21G16B Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21G16B Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21G16B Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21G16B Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21G16B Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21G16B Basic Timer Counter 5 (TC5) */
+ ADC_IRQn = 23, /**< 23 SAMD21G16B Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21G16B Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21G16B Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21G16B Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21G16B Inter-IC Sound Interface (I2S) */
+
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
-
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnReservedM12;
- void* pfnReservedM11;
- void* pfnReservedM10;
- void* pfnReservedM9;
- void* pfnReservedM8;
- void* pfnReservedM7;
- void* pfnReservedM6;
- void* pfnSVC_Handler;
- void* pfnReservedM4;
- void* pfnReservedM3;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
-
- /* Peripheral handlers */
- void* pfnPM_Handler; /* 0 Power Manager */
- void* pfnSYSCTRL_Handler; /* 1 System Control */
- void* pfnWDT_Handler; /* 2 Watchdog Timer */
- void* pfnRTC_Handler; /* 3 Real-Time Counter */
- void* pfnEIC_Handler; /* 4 External Interrupt Controller */
- void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
- void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
- void* pfnUSB_Handler; /* 7 Universal Serial Bus */
- void* pfnEVSYS_Handler; /* 8 Event System Interface */
- void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
- void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
- void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
- void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
- void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
- void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
- void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
- void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
- void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
- void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
- void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
- void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
- void* pfnReserved21;
- void* pfnReserved22;
- void* pfnADC_Handler; /* 23 Analog Digital Converter */
- void* pfnAC_Handler; /* 24 Analog Comparators */
- void* pfnDAC_Handler; /* 25 Digital Analog Converter */
- void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
- void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
- void* pfnReserved28;
+typedef struct _DeviceVectors {
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
+ void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnReserved21;
+ void* pfnReserved22;
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+ void* pfnReserved28;
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@@ -223,7 +221,7 @@ void I2S_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g17a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g17a.h
index 732d977e8f0..ccf9f074f4a 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g17a.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g17a.h
@@ -59,7 +59,7 @@
/*@{*/
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -93,96 +93,94 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
-typedef enum IRQn
-{
- /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
- /****** SAMD21G17A-specific Interrupt Numbers ***********************/
- PM_IRQn = 0, /**< 0 SAMD21G17A Power Manager (PM) */
- SYSCTRL_IRQn = 1, /**< 1 SAMD21G17A System Control (SYSCTRL) */
- WDT_IRQn = 2, /**< 2 SAMD21G17A Watchdog Timer (WDT) */
- RTC_IRQn = 3, /**< 3 SAMD21G17A Real-Time Counter (RTC) */
- EIC_IRQn = 4, /**< 4 SAMD21G17A External Interrupt Controller (EIC) */
- NVMCTRL_IRQn = 5, /**< 5 SAMD21G17A Non-Volatile Memory Controller (NVMCTRL) */
- DMAC_IRQn = 6, /**< 6 SAMD21G17A Direct Memory Access Controller (DMAC) */
- USB_IRQn = 7, /**< 7 SAMD21G17A Universal Serial Bus (USB) */
- EVSYS_IRQn = 8, /**< 8 SAMD21G17A Event System Interface (EVSYS) */
- SERCOM0_IRQn = 9, /**< 9 SAMD21G17A Serial Communication Interface 0 (SERCOM0) */
- SERCOM1_IRQn = 10, /**< 10 SAMD21G17A Serial Communication Interface 1 (SERCOM1) */
- SERCOM2_IRQn = 11, /**< 11 SAMD21G17A Serial Communication Interface 2 (SERCOM2) */
- SERCOM3_IRQn = 12, /**< 12 SAMD21G17A Serial Communication Interface 3 (SERCOM3) */
- SERCOM4_IRQn = 13, /**< 13 SAMD21G17A Serial Communication Interface 4 (SERCOM4) */
- SERCOM5_IRQn = 14, /**< 14 SAMD21G17A Serial Communication Interface 5 (SERCOM5) */
- TCC0_IRQn = 15, /**< 15 SAMD21G17A Timer Counter Control 0 (TCC0) */
- TCC1_IRQn = 16, /**< 16 SAMD21G17A Timer Counter Control 1 (TCC1) */
- TCC2_IRQn = 17, /**< 17 SAMD21G17A Timer Counter Control 2 (TCC2) */
- TC3_IRQn = 18, /**< 18 SAMD21G17A Basic Timer Counter 3 (TC3) */
- TC4_IRQn = 19, /**< 19 SAMD21G17A Basic Timer Counter 4 (TC4) */
- TC5_IRQn = 20, /**< 20 SAMD21G17A Basic Timer Counter 5 (TC5) */
- ADC_IRQn = 23, /**< 23 SAMD21G17A Analog Digital Converter (ADC) */
- AC_IRQn = 24, /**< 24 SAMD21G17A Analog Comparators (AC) */
- DAC_IRQn = 25, /**< 25 SAMD21G17A Digital Analog Converter (DAC) */
- PTC_IRQn = 26, /**< 26 SAMD21G17A Peripheral Touch Controller (PTC) */
- I2S_IRQn = 27, /**< 27 SAMD21G17A Inter-IC Sound Interface (I2S) */
-
- PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+typedef enum IRQn {
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21G17A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21G17A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21G17A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21G17A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21G17A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21G17A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21G17A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21G17A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21G17A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21G17A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21G17A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21G17A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21G17A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21G17A Serial Communication Interface 3 (SERCOM3) */
+ SERCOM4_IRQn = 13, /**< 13 SAMD21G17A Serial Communication Interface 4 (SERCOM4) */
+ SERCOM5_IRQn = 14, /**< 14 SAMD21G17A Serial Communication Interface 5 (SERCOM5) */
+ TCC0_IRQn = 15, /**< 15 SAMD21G17A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21G17A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21G17A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21G17A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21G17A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21G17A Basic Timer Counter 5 (TC5) */
+ ADC_IRQn = 23, /**< 23 SAMD21G17A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21G17A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21G17A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21G17A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21G17A Inter-IC Sound Interface (I2S) */
+
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
-
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnReservedM12;
- void* pfnReservedM11;
- void* pfnReservedM10;
- void* pfnReservedM9;
- void* pfnReservedM8;
- void* pfnReservedM7;
- void* pfnReservedM6;
- void* pfnSVC_Handler;
- void* pfnReservedM4;
- void* pfnReservedM3;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
-
- /* Peripheral handlers */
- void* pfnPM_Handler; /* 0 Power Manager */
- void* pfnSYSCTRL_Handler; /* 1 System Control */
- void* pfnWDT_Handler; /* 2 Watchdog Timer */
- void* pfnRTC_Handler; /* 3 Real-Time Counter */
- void* pfnEIC_Handler; /* 4 External Interrupt Controller */
- void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
- void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
- void* pfnUSB_Handler; /* 7 Universal Serial Bus */
- void* pfnEVSYS_Handler; /* 8 Event System Interface */
- void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
- void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
- void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
- void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
- void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
- void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
- void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
- void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
- void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
- void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
- void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
- void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
- void* pfnReserved21;
- void* pfnReserved22;
- void* pfnADC_Handler; /* 23 Analog Digital Converter */
- void* pfnAC_Handler; /* 24 Analog Comparators */
- void* pfnDAC_Handler; /* 25 Digital Analog Converter */
- void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
- void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+typedef struct _DeviceVectors {
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
+ void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnReserved21;
+ void* pfnReserved22;
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@@ -225,7 +223,7 @@ void I2S_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g17au.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g17au.h
index 2ca29801a0e..01502c92ee4 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g17au.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g17au.h
@@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
- /*
- * Support and FAQ: visit Atmel Support
- */
+/*
+* Support and FAQ: visit Atmel Support
+*/
#ifndef _SAMD21G17AU_
#define _SAMD21G17AU_
@@ -59,7 +59,7 @@
/*@{*/
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -93,99 +93,97 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
-typedef enum IRQn
-{
- /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
- /****** SAMD21G17AU-specific Interrupt Numbers ***********************/
- PM_IRQn = 0, /**< 0 SAMD21G17AU Power Manager (PM) */
- SYSCTRL_IRQn = 1, /**< 1 SAMD21G17AU System Control (SYSCTRL) */
- WDT_IRQn = 2, /**< 2 SAMD21G17AU Watchdog Timer (WDT) */
- RTC_IRQn = 3, /**< 3 SAMD21G17AU Real-Time Counter (RTC) */
- EIC_IRQn = 4, /**< 4 SAMD21G17AU External Interrupt Controller (EIC) */
- NVMCTRL_IRQn = 5, /**< 5 SAMD21G17AU Non-Volatile Memory Controller (NVMCTRL) */
- DMAC_IRQn = 6, /**< 6 SAMD21G17AU Direct Memory Access Controller (DMAC) */
- USB_IRQn = 7, /**< 7 SAMD21G17AU Universal Serial Bus (USB) */
- EVSYS_IRQn = 8, /**< 8 SAMD21G17AU Event System Interface (EVSYS) */
- SERCOM0_IRQn = 9, /**< 9 SAMD21G17AU Serial Communication Interface 0 (SERCOM0) */
- SERCOM1_IRQn = 10, /**< 10 SAMD21G17AU Serial Communication Interface 1 (SERCOM1) */
- SERCOM2_IRQn = 11, /**< 11 SAMD21G17AU Serial Communication Interface 2 (SERCOM2) */
- SERCOM3_IRQn = 12, /**< 12 SAMD21G17AU Serial Communication Interface 3 (SERCOM3) */
- SERCOM4_IRQn = 13, /**< 13 SAMD21G17AU Serial Communication Interface 4 (SERCOM4) */
- SERCOM5_IRQn = 14, /**< 14 SAMD21G17AU Serial Communication Interface 5 (SERCOM5) */
- TCC0_IRQn = 15, /**< 15 SAMD21G17AU Timer Counter Control 0 (TCC0) */
- TCC1_IRQn = 16, /**< 16 SAMD21G17AU Timer Counter Control 1 (TCC1) */
- TCC2_IRQn = 17, /**< 17 SAMD21G17AU Timer Counter Control 2 (TCC2) */
- TC3_IRQn = 18, /**< 18 SAMD21G17AU Basic Timer Counter 3 (TC3) */
- TC4_IRQn = 19, /**< 19 SAMD21G17AU Basic Timer Counter 4 (TC4) */
- TC5_IRQn = 20, /**< 20 SAMD21G17AU Basic Timer Counter 5 (TC5) */
- TC6_IRQn = 21, /**< 21 SAMD21G17AU Basic Timer Counter 6 (TC6) */
- TC7_IRQn = 22, /**< 22 SAMD21G17AU Basic Timer Counter 7 (TC7) */
- ADC_IRQn = 23, /**< 23 SAMD21G17AU Analog Digital Converter (ADC) */
- AC_IRQn = 24, /**< 24 SAMD21G17AU Analog Comparators (AC) */
- DAC_IRQn = 25, /**< 25 SAMD21G17AU Digital Analog Converter (DAC) */
- PTC_IRQn = 26, /**< 26 SAMD21G17AU Peripheral Touch Controller (PTC) */
- I2S_IRQn = 27, /**< 27 SAMD21G17AU Inter-IC Sound Interface (I2S) */
-
- PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+typedef enum IRQn {
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21G17AU-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21G17AU Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21G17AU System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21G17AU Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21G17AU Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21G17AU External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21G17AU Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21G17AU Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21G17AU Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21G17AU Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21G17AU Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21G17AU Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21G17AU Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21G17AU Serial Communication Interface 3 (SERCOM3) */
+ SERCOM4_IRQn = 13, /**< 13 SAMD21G17AU Serial Communication Interface 4 (SERCOM4) */
+ SERCOM5_IRQn = 14, /**< 14 SAMD21G17AU Serial Communication Interface 5 (SERCOM5) */
+ TCC0_IRQn = 15, /**< 15 SAMD21G17AU Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21G17AU Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21G17AU Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21G17AU Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21G17AU Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21G17AU Basic Timer Counter 5 (TC5) */
+ TC6_IRQn = 21, /**< 21 SAMD21G17AU Basic Timer Counter 6 (TC6) */
+ TC7_IRQn = 22, /**< 22 SAMD21G17AU Basic Timer Counter 7 (TC7) */
+ ADC_IRQn = 23, /**< 23 SAMD21G17AU Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21G17AU Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21G17AU Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21G17AU Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21G17AU Inter-IC Sound Interface (I2S) */
+
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
-
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnReservedM12;
- void* pfnReservedM11;
- void* pfnReservedM10;
- void* pfnReservedM9;
- void* pfnReservedM8;
- void* pfnReservedM7;
- void* pfnReservedM6;
- void* pfnSVC_Handler;
- void* pfnReservedM4;
- void* pfnReservedM3;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
-
- /* Peripheral handlers */
- void* pfnPM_Handler; /* 0 Power Manager */
- void* pfnSYSCTRL_Handler; /* 1 System Control */
- void* pfnWDT_Handler; /* 2 Watchdog Timer */
- void* pfnRTC_Handler; /* 3 Real-Time Counter */
- void* pfnEIC_Handler; /* 4 External Interrupt Controller */
- void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
- void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
- void* pfnUSB_Handler; /* 7 Universal Serial Bus */
- void* pfnEVSYS_Handler; /* 8 Event System Interface */
- void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
- void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
- void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
- void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
- void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
- void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
- void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
- void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
- void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
- void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
- void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
- void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
- void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
- void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
- void* pfnADC_Handler; /* 23 Analog Digital Converter */
- void* pfnAC_Handler; /* 24 Analog Comparators */
- void* pfnDAC_Handler; /* 25 Digital Analog Converter */
- void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
- void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
- void* pfnReserved28;
+typedef struct _DeviceVectors {
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
+ void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
+ void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+ void* pfnReserved28;
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@@ -230,7 +228,7 @@ void I2S_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g18a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g18a.h
index 68d362c0e50..83e232a224f 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g18a.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g18a.h
@@ -59,7 +59,7 @@
/*@{*/
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -93,96 +93,94 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
-typedef enum IRQn
-{
- /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
- /****** SAMD21G18A-specific Interrupt Numbers ***********************/
- PM_IRQn = 0, /**< 0 SAMD21G18A Power Manager (PM) */
- SYSCTRL_IRQn = 1, /**< 1 SAMD21G18A System Control (SYSCTRL) */
- WDT_IRQn = 2, /**< 2 SAMD21G18A Watchdog Timer (WDT) */
- RTC_IRQn = 3, /**< 3 SAMD21G18A Real-Time Counter (RTC) */
- EIC_IRQn = 4, /**< 4 SAMD21G18A External Interrupt Controller (EIC) */
- NVMCTRL_IRQn = 5, /**< 5 SAMD21G18A Non-Volatile Memory Controller (NVMCTRL) */
- DMAC_IRQn = 6, /**< 6 SAMD21G18A Direct Memory Access Controller (DMAC) */
- USB_IRQn = 7, /**< 7 SAMD21G18A Universal Serial Bus (USB) */
- EVSYS_IRQn = 8, /**< 8 SAMD21G18A Event System Interface (EVSYS) */
- SERCOM0_IRQn = 9, /**< 9 SAMD21G18A Serial Communication Interface 0 (SERCOM0) */
- SERCOM1_IRQn = 10, /**< 10 SAMD21G18A Serial Communication Interface 1 (SERCOM1) */
- SERCOM2_IRQn = 11, /**< 11 SAMD21G18A Serial Communication Interface 2 (SERCOM2) */
- SERCOM3_IRQn = 12, /**< 12 SAMD21G18A Serial Communication Interface 3 (SERCOM3) */
- SERCOM4_IRQn = 13, /**< 13 SAMD21G18A Serial Communication Interface 4 (SERCOM4) */
- SERCOM5_IRQn = 14, /**< 14 SAMD21G18A Serial Communication Interface 5 (SERCOM5) */
- TCC0_IRQn = 15, /**< 15 SAMD21G18A Timer Counter Control 0 (TCC0) */
- TCC1_IRQn = 16, /**< 16 SAMD21G18A Timer Counter Control 1 (TCC1) */
- TCC2_IRQn = 17, /**< 17 SAMD21G18A Timer Counter Control 2 (TCC2) */
- TC3_IRQn = 18, /**< 18 SAMD21G18A Basic Timer Counter 3 (TC3) */
- TC4_IRQn = 19, /**< 19 SAMD21G18A Basic Timer Counter 4 (TC4) */
- TC5_IRQn = 20, /**< 20 SAMD21G18A Basic Timer Counter 5 (TC5) */
- ADC_IRQn = 23, /**< 23 SAMD21G18A Analog Digital Converter (ADC) */
- AC_IRQn = 24, /**< 24 SAMD21G18A Analog Comparators (AC) */
- DAC_IRQn = 25, /**< 25 SAMD21G18A Digital Analog Converter (DAC) */
- PTC_IRQn = 26, /**< 26 SAMD21G18A Peripheral Touch Controller (PTC) */
- I2S_IRQn = 27, /**< 27 SAMD21G18A Inter-IC Sound Interface (I2S) */
-
- PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+typedef enum IRQn {
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21G18A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21G18A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21G18A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21G18A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21G18A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21G18A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21G18A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21G18A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21G18A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21G18A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21G18A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21G18A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21G18A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21G18A Serial Communication Interface 3 (SERCOM3) */
+ SERCOM4_IRQn = 13, /**< 13 SAMD21G18A Serial Communication Interface 4 (SERCOM4) */
+ SERCOM5_IRQn = 14, /**< 14 SAMD21G18A Serial Communication Interface 5 (SERCOM5) */
+ TCC0_IRQn = 15, /**< 15 SAMD21G18A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21G18A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21G18A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21G18A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21G18A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21G18A Basic Timer Counter 5 (TC5) */
+ ADC_IRQn = 23, /**< 23 SAMD21G18A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21G18A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21G18A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21G18A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21G18A Inter-IC Sound Interface (I2S) */
+
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
-
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnReservedM12;
- void* pfnReservedM11;
- void* pfnReservedM10;
- void* pfnReservedM9;
- void* pfnReservedM8;
- void* pfnReservedM7;
- void* pfnReservedM6;
- void* pfnSVC_Handler;
- void* pfnReservedM4;
- void* pfnReservedM3;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
-
- /* Peripheral handlers */
- void* pfnPM_Handler; /* 0 Power Manager */
- void* pfnSYSCTRL_Handler; /* 1 System Control */
- void* pfnWDT_Handler; /* 2 Watchdog Timer */
- void* pfnRTC_Handler; /* 3 Real-Time Counter */
- void* pfnEIC_Handler; /* 4 External Interrupt Controller */
- void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
- void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
- void* pfnUSB_Handler; /* 7 Universal Serial Bus */
- void* pfnEVSYS_Handler; /* 8 Event System Interface */
- void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
- void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
- void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
- void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
- void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
- void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
- void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
- void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
- void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
- void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
- void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
- void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
- void* pfnReserved21;
- void* pfnReserved22;
- void* pfnADC_Handler; /* 23 Analog Digital Converter */
- void* pfnAC_Handler; /* 24 Analog Comparators */
- void* pfnDAC_Handler; /* 25 Digital Analog Converter */
- void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
- void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+typedef struct _DeviceVectors {
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
+ void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnReserved21;
+ void* pfnReserved22;
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@@ -225,7 +223,7 @@ void I2S_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g18au.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g18au.h
index 3e4bff3dcdd..dda17586c6f 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g18au.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g18au.h
@@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
- /*
- * Support and FAQ: visit Atmel Support
- */
+/*
+* Support and FAQ: visit Atmel Support
+*/
#ifndef _SAMD21G18AU_
#define _SAMD21G18AU_
@@ -59,7 +59,7 @@
/*@{*/
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -93,98 +93,96 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
-typedef enum IRQn
-{
- /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
- /****** SAMD21G18AU-specific Interrupt Numbers ***********************/
- PM_IRQn = 0, /**< 0 SAMD21G18AU Power Manager (PM) */
- SYSCTRL_IRQn = 1, /**< 1 SAMD21G18AU System Control (SYSCTRL) */
- WDT_IRQn = 2, /**< 2 SAMD21G18AU Watchdog Timer (WDT) */
- RTC_IRQn = 3, /**< 3 SAMD21G18AU Real-Time Counter (RTC) */
- EIC_IRQn = 4, /**< 4 SAMD21G18AU External Interrupt Controller (EIC) */
- NVMCTRL_IRQn = 5, /**< 5 SAMD21G18AU Non-Volatile Memory Controller (NVMCTRL) */
- DMAC_IRQn = 6, /**< 6 SAMD21G18AU Direct Memory Access Controller (DMAC) */
- USB_IRQn = 7, /**< 7 SAMD21G18AU Universal Serial Bus (USB) */
- EVSYS_IRQn = 8, /**< 8 SAMD21G18AU Event System Interface (EVSYS) */
- SERCOM0_IRQn = 9, /**< 9 SAMD21G18AU Serial Communication Interface 0 (SERCOM0) */
- SERCOM1_IRQn = 10, /**< 10 SAMD21G18AU Serial Communication Interface 1 (SERCOM1) */
- SERCOM2_IRQn = 11, /**< 11 SAMD21G18AU Serial Communication Interface 2 (SERCOM2) */
- SERCOM3_IRQn = 12, /**< 12 SAMD21G18AU Serial Communication Interface 3 (SERCOM3) */
- SERCOM4_IRQn = 13, /**< 13 SAMD21G18AU Serial Communication Interface 4 (SERCOM4) */
- SERCOM5_IRQn = 14, /**< 14 SAMD21G18AU Serial Communication Interface 5 (SERCOM5) */
- TCC0_IRQn = 15, /**< 15 SAMD21G18AU Timer Counter Control 0 (TCC0) */
- TCC1_IRQn = 16, /**< 16 SAMD21G18AU Timer Counter Control 1 (TCC1) */
- TCC2_IRQn = 17, /**< 17 SAMD21G18AU Timer Counter Control 2 (TCC2) */
- TC3_IRQn = 18, /**< 18 SAMD21G18AU Basic Timer Counter 3 (TC3) */
- TC4_IRQn = 19, /**< 19 SAMD21G18AU Basic Timer Counter 4 (TC4) */
- TC5_IRQn = 20, /**< 20 SAMD21G18AU Basic Timer Counter 5 (TC5) */
- TC6_IRQn = 21, /**< 21 SAMD21G18AU Basic Timer Counter 6 (TC6) */
- TC7_IRQn = 22, /**< 22 SAMD21G18AU Basic Timer Counter 7 (TC7) */
- ADC_IRQn = 23, /**< 23 SAMD21G18AU Analog Digital Converter (ADC) */
- AC_IRQn = 24, /**< 24 SAMD21G18AU Analog Comparators (AC) */
- DAC_IRQn = 25, /**< 25 SAMD21G18AU Digital Analog Converter (DAC) */
- PTC_IRQn = 26, /**< 26 SAMD21G18AU Peripheral Touch Controller (PTC) */
- I2S_IRQn = 27, /**< 27 SAMD21G18AU Inter-IC Sound Interface (I2S) */
-
- PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+typedef enum IRQn {
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21G18AU-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21G18AU Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21G18AU System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21G18AU Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21G18AU Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21G18AU External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21G18AU Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21G18AU Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21G18AU Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21G18AU Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21G18AU Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21G18AU Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21G18AU Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21G18AU Serial Communication Interface 3 (SERCOM3) */
+ SERCOM4_IRQn = 13, /**< 13 SAMD21G18AU Serial Communication Interface 4 (SERCOM4) */
+ SERCOM5_IRQn = 14, /**< 14 SAMD21G18AU Serial Communication Interface 5 (SERCOM5) */
+ TCC0_IRQn = 15, /**< 15 SAMD21G18AU Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21G18AU Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21G18AU Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21G18AU Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21G18AU Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21G18AU Basic Timer Counter 5 (TC5) */
+ TC6_IRQn = 21, /**< 21 SAMD21G18AU Basic Timer Counter 6 (TC6) */
+ TC7_IRQn = 22, /**< 22 SAMD21G18AU Basic Timer Counter 7 (TC7) */
+ ADC_IRQn = 23, /**< 23 SAMD21G18AU Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21G18AU Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21G18AU Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21G18AU Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21G18AU Inter-IC Sound Interface (I2S) */
+
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
-
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnReservedM12;
- void* pfnReservedM11;
- void* pfnReservedM10;
- void* pfnReservedM9;
- void* pfnReservedM8;
- void* pfnReservedM7;
- void* pfnReservedM6;
- void* pfnSVC_Handler;
- void* pfnReservedM4;
- void* pfnReservedM3;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
-
- /* Peripheral handlers */
- void* pfnPM_Handler; /* 0 Power Manager */
- void* pfnSYSCTRL_Handler; /* 1 System Control */
- void* pfnWDT_Handler; /* 2 Watchdog Timer */
- void* pfnRTC_Handler; /* 3 Real-Time Counter */
- void* pfnEIC_Handler; /* 4 External Interrupt Controller */
- void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
- void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
- void* pfnUSB_Handler; /* 7 Universal Serial Bus */
- void* pfnEVSYS_Handler; /* 8 Event System Interface */
- void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
- void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
- void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
- void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
- void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
- void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
- void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
- void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
- void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
- void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
- void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
- void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
- void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
- void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
- void* pfnADC_Handler; /* 23 Analog Digital Converter */
- void* pfnAC_Handler; /* 24 Analog Comparators */
- void* pfnDAC_Handler; /* 25 Digital Analog Converter */
- void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
- void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+typedef struct _DeviceVectors {
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
+ void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
+ void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@@ -229,7 +227,7 @@ void I2S_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21j15a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21j15a.h
index cb63e76a36c..932efa39149 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21j15a.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21j15a.h
@@ -59,7 +59,7 @@
/*@{*/
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -93,98 +93,96 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
-typedef enum IRQn
-{
- /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
- /****** SAMD21J15A-specific Interrupt Numbers ***********************/
- PM_IRQn = 0, /**< 0 SAMD21J15A Power Manager (PM) */
- SYSCTRL_IRQn = 1, /**< 1 SAMD21J15A System Control (SYSCTRL) */
- WDT_IRQn = 2, /**< 2 SAMD21J15A Watchdog Timer (WDT) */
- RTC_IRQn = 3, /**< 3 SAMD21J15A Real-Time Counter (RTC) */
- EIC_IRQn = 4, /**< 4 SAMD21J15A External Interrupt Controller (EIC) */
- NVMCTRL_IRQn = 5, /**< 5 SAMD21J15A Non-Volatile Memory Controller (NVMCTRL) */
- DMAC_IRQn = 6, /**< 6 SAMD21J15A Direct Memory Access Controller (DMAC) */
- USB_IRQn = 7, /**< 7 SAMD21J15A Universal Serial Bus (USB) */
- EVSYS_IRQn = 8, /**< 8 SAMD21J15A Event System Interface (EVSYS) */
- SERCOM0_IRQn = 9, /**< 9 SAMD21J15A Serial Communication Interface 0 (SERCOM0) */
- SERCOM1_IRQn = 10, /**< 10 SAMD21J15A Serial Communication Interface 1 (SERCOM1) */
- SERCOM2_IRQn = 11, /**< 11 SAMD21J15A Serial Communication Interface 2 (SERCOM2) */
- SERCOM3_IRQn = 12, /**< 12 SAMD21J15A Serial Communication Interface 3 (SERCOM3) */
- SERCOM4_IRQn = 13, /**< 13 SAMD21J15A Serial Communication Interface 4 (SERCOM4) */
- SERCOM5_IRQn = 14, /**< 14 SAMD21J15A Serial Communication Interface 5 (SERCOM5) */
- TCC0_IRQn = 15, /**< 15 SAMD21J15A Timer Counter Control 0 (TCC0) */
- TCC1_IRQn = 16, /**< 16 SAMD21J15A Timer Counter Control 1 (TCC1) */
- TCC2_IRQn = 17, /**< 17 SAMD21J15A Timer Counter Control 2 (TCC2) */
- TC3_IRQn = 18, /**< 18 SAMD21J15A Basic Timer Counter 3 (TC3) */
- TC4_IRQn = 19, /**< 19 SAMD21J15A Basic Timer Counter 4 (TC4) */
- TC5_IRQn = 20, /**< 20 SAMD21J15A Basic Timer Counter 5 (TC5) */
- TC6_IRQn = 21, /**< 21 SAMD21J15A Basic Timer Counter 6 (TC6) */
- TC7_IRQn = 22, /**< 22 SAMD21J15A Basic Timer Counter 7 (TC7) */
- ADC_IRQn = 23, /**< 23 SAMD21J15A Analog Digital Converter (ADC) */
- AC_IRQn = 24, /**< 24 SAMD21J15A Analog Comparators (AC) */
- DAC_IRQn = 25, /**< 25 SAMD21J15A Digital Analog Converter (DAC) */
- PTC_IRQn = 26, /**< 26 SAMD21J15A Peripheral Touch Controller (PTC) */
- I2S_IRQn = 27, /**< 27 SAMD21J15A Inter-IC Sound Interface (I2S) */
-
- PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+typedef enum IRQn {
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21J15A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21J15A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21J15A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21J15A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21J15A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21J15A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21J15A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21J15A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21J15A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21J15A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21J15A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21J15A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21J15A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21J15A Serial Communication Interface 3 (SERCOM3) */
+ SERCOM4_IRQn = 13, /**< 13 SAMD21J15A Serial Communication Interface 4 (SERCOM4) */
+ SERCOM5_IRQn = 14, /**< 14 SAMD21J15A Serial Communication Interface 5 (SERCOM5) */
+ TCC0_IRQn = 15, /**< 15 SAMD21J15A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21J15A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21J15A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21J15A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21J15A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21J15A Basic Timer Counter 5 (TC5) */
+ TC6_IRQn = 21, /**< 21 SAMD21J15A Basic Timer Counter 6 (TC6) */
+ TC7_IRQn = 22, /**< 22 SAMD21J15A Basic Timer Counter 7 (TC7) */
+ ADC_IRQn = 23, /**< 23 SAMD21J15A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21J15A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21J15A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21J15A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21J15A Inter-IC Sound Interface (I2S) */
+
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
-
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnReservedM12;
- void* pfnReservedM11;
- void* pfnReservedM10;
- void* pfnReservedM9;
- void* pfnReservedM8;
- void* pfnReservedM7;
- void* pfnReservedM6;
- void* pfnSVC_Handler;
- void* pfnReservedM4;
- void* pfnReservedM3;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
-
- /* Peripheral handlers */
- void* pfnPM_Handler; /* 0 Power Manager */
- void* pfnSYSCTRL_Handler; /* 1 System Control */
- void* pfnWDT_Handler; /* 2 Watchdog Timer */
- void* pfnRTC_Handler; /* 3 Real-Time Counter */
- void* pfnEIC_Handler; /* 4 External Interrupt Controller */
- void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
- void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
- void* pfnUSB_Handler; /* 7 Universal Serial Bus */
- void* pfnEVSYS_Handler; /* 8 Event System Interface */
- void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
- void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
- void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
- void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
- void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
- void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
- void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
- void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
- void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
- void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
- void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
- void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
- void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
- void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
- void* pfnADC_Handler; /* 23 Analog Digital Converter */
- void* pfnAC_Handler; /* 24 Analog Comparators */
- void* pfnDAC_Handler; /* 25 Digital Analog Converter */
- void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
- void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+typedef struct _DeviceVectors {
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
+ void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
+ void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@@ -229,7 +227,7 @@ void I2S_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21j15b.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21j15b.h
index ab2e99b9403..daaabc0794e 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21j15b.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21j15b.h
@@ -56,7 +56,7 @@
/*@{*/
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -90,99 +90,97 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
-typedef enum IRQn
-{
- /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
- /****** SAMD21J15B-specific Interrupt Numbers ***********************/
- PM_IRQn = 0, /**< 0 SAMD21J15B Power Manager (PM) */
- SYSCTRL_IRQn = 1, /**< 1 SAMD21J15B System Control (SYSCTRL) */
- WDT_IRQn = 2, /**< 2 SAMD21J15B Watchdog Timer (WDT) */
- RTC_IRQn = 3, /**< 3 SAMD21J15B Real-Time Counter (RTC) */
- EIC_IRQn = 4, /**< 4 SAMD21J15B External Interrupt Controller (EIC) */
- NVMCTRL_IRQn = 5, /**< 5 SAMD21J15B Non-Volatile Memory Controller (NVMCTRL) */
- DMAC_IRQn = 6, /**< 6 SAMD21J15B Direct Memory Access Controller (DMAC) */
- USB_IRQn = 7, /**< 7 SAMD21J15B Universal Serial Bus (USB) */
- EVSYS_IRQn = 8, /**< 8 SAMD21J15B Event System Interface (EVSYS) */
- SERCOM0_IRQn = 9, /**< 9 SAMD21J15B Serial Communication Interface 0 (SERCOM0) */
- SERCOM1_IRQn = 10, /**< 10 SAMD21J15B Serial Communication Interface 1 (SERCOM1) */
- SERCOM2_IRQn = 11, /**< 11 SAMD21J15B Serial Communication Interface 2 (SERCOM2) */
- SERCOM3_IRQn = 12, /**< 12 SAMD21J15B Serial Communication Interface 3 (SERCOM3) */
- SERCOM4_IRQn = 13, /**< 13 SAMD21J15B Serial Communication Interface 4 (SERCOM4) */
- SERCOM5_IRQn = 14, /**< 14 SAMD21J15B Serial Communication Interface 5 (SERCOM5) */
- TCC0_IRQn = 15, /**< 15 SAMD21J15B Timer Counter Control 0 (TCC0) */
- TCC1_IRQn = 16, /**< 16 SAMD21J15B Timer Counter Control 1 (TCC1) */
- TCC2_IRQn = 17, /**< 17 SAMD21J15B Timer Counter Control 2 (TCC2) */
- TC3_IRQn = 18, /**< 18 SAMD21J15B Basic Timer Counter 3 (TC3) */
- TC4_IRQn = 19, /**< 19 SAMD21J15B Basic Timer Counter 4 (TC4) */
- TC5_IRQn = 20, /**< 20 SAMD21J15B Basic Timer Counter 5 (TC5) */
- TC6_IRQn = 21, /**< 21 SAMD21J15B Basic Timer Counter 6 (TC6) */
- TC7_IRQn = 22, /**< 22 SAMD21J15B Basic Timer Counter 7 (TC7) */
- ADC_IRQn = 23, /**< 23 SAMD21J15B Analog Digital Converter (ADC) */
- AC_IRQn = 24, /**< 24 SAMD21J15B Analog Comparators (AC) */
- DAC_IRQn = 25, /**< 25 SAMD21J15B Digital Analog Converter (DAC) */
- PTC_IRQn = 26, /**< 26 SAMD21J15B Peripheral Touch Controller (PTC) */
- I2S_IRQn = 27, /**< 27 SAMD21J15B Inter-IC Sound Interface (I2S) */
-
- PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+typedef enum IRQn {
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21J15B-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21J15B Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21J15B System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21J15B Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21J15B Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21J15B External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21J15B Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21J15B Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21J15B Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21J15B Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21J15B Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21J15B Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21J15B Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21J15B Serial Communication Interface 3 (SERCOM3) */
+ SERCOM4_IRQn = 13, /**< 13 SAMD21J15B Serial Communication Interface 4 (SERCOM4) */
+ SERCOM5_IRQn = 14, /**< 14 SAMD21J15B Serial Communication Interface 5 (SERCOM5) */
+ TCC0_IRQn = 15, /**< 15 SAMD21J15B Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21J15B Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21J15B Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21J15B Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21J15B Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21J15B Basic Timer Counter 5 (TC5) */
+ TC6_IRQn = 21, /**< 21 SAMD21J15B Basic Timer Counter 6 (TC6) */
+ TC7_IRQn = 22, /**< 22 SAMD21J15B Basic Timer Counter 7 (TC7) */
+ ADC_IRQn = 23, /**< 23 SAMD21J15B Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21J15B Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21J15B Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21J15B Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21J15B Inter-IC Sound Interface (I2S) */
+
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
-
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnReservedM12;
- void* pfnReservedM11;
- void* pfnReservedM10;
- void* pfnReservedM9;
- void* pfnReservedM8;
- void* pfnReservedM7;
- void* pfnReservedM6;
- void* pfnSVC_Handler;
- void* pfnReservedM4;
- void* pfnReservedM3;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
-
- /* Peripheral handlers */
- void* pfnPM_Handler; /* 0 Power Manager */
- void* pfnSYSCTRL_Handler; /* 1 System Control */
- void* pfnWDT_Handler; /* 2 Watchdog Timer */
- void* pfnRTC_Handler; /* 3 Real-Time Counter */
- void* pfnEIC_Handler; /* 4 External Interrupt Controller */
- void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
- void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
- void* pfnUSB_Handler; /* 7 Universal Serial Bus */
- void* pfnEVSYS_Handler; /* 8 Event System Interface */
- void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
- void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
- void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
- void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
- void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
- void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
- void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
- void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
- void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
- void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
- void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
- void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
- void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
- void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
- void* pfnADC_Handler; /* 23 Analog Digital Converter */
- void* pfnAC_Handler; /* 24 Analog Comparators */
- void* pfnDAC_Handler; /* 25 Digital Analog Converter */
- void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
- void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
- void* pfnReserved28;
+typedef struct _DeviceVectors {
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
+ void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
+ void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+ void* pfnReserved28;
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@@ -227,7 +225,7 @@ void I2S_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21j16a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21j16a.h
index bdb84982fbe..78628939871 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21j16a.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21j16a.h
@@ -59,7 +59,7 @@
/*@{*/
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -93,98 +93,96 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
-typedef enum IRQn
-{
- /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
- /****** SAMD21J16A-specific Interrupt Numbers ***********************/
- PM_IRQn = 0, /**< 0 SAMD21J16A Power Manager (PM) */
- SYSCTRL_IRQn = 1, /**< 1 SAMD21J16A System Control (SYSCTRL) */
- WDT_IRQn = 2, /**< 2 SAMD21J16A Watchdog Timer (WDT) */
- RTC_IRQn = 3, /**< 3 SAMD21J16A Real-Time Counter (RTC) */
- EIC_IRQn = 4, /**< 4 SAMD21J16A External Interrupt Controller (EIC) */
- NVMCTRL_IRQn = 5, /**< 5 SAMD21J16A Non-Volatile Memory Controller (NVMCTRL) */
- DMAC_IRQn = 6, /**< 6 SAMD21J16A Direct Memory Access Controller (DMAC) */
- USB_IRQn = 7, /**< 7 SAMD21J16A Universal Serial Bus (USB) */
- EVSYS_IRQn = 8, /**< 8 SAMD21J16A Event System Interface (EVSYS) */
- SERCOM0_IRQn = 9, /**< 9 SAMD21J16A Serial Communication Interface 0 (SERCOM0) */
- SERCOM1_IRQn = 10, /**< 10 SAMD21J16A Serial Communication Interface 1 (SERCOM1) */
- SERCOM2_IRQn = 11, /**< 11 SAMD21J16A Serial Communication Interface 2 (SERCOM2) */
- SERCOM3_IRQn = 12, /**< 12 SAMD21J16A Serial Communication Interface 3 (SERCOM3) */
- SERCOM4_IRQn = 13, /**< 13 SAMD21J16A Serial Communication Interface 4 (SERCOM4) */
- SERCOM5_IRQn = 14, /**< 14 SAMD21J16A Serial Communication Interface 5 (SERCOM5) */
- TCC0_IRQn = 15, /**< 15 SAMD21J16A Timer Counter Control 0 (TCC0) */
- TCC1_IRQn = 16, /**< 16 SAMD21J16A Timer Counter Control 1 (TCC1) */
- TCC2_IRQn = 17, /**< 17 SAMD21J16A Timer Counter Control 2 (TCC2) */
- TC3_IRQn = 18, /**< 18 SAMD21J16A Basic Timer Counter 3 (TC3) */
- TC4_IRQn = 19, /**< 19 SAMD21J16A Basic Timer Counter 4 (TC4) */
- TC5_IRQn = 20, /**< 20 SAMD21J16A Basic Timer Counter 5 (TC5) */
- TC6_IRQn = 21, /**< 21 SAMD21J16A Basic Timer Counter 6 (TC6) */
- TC7_IRQn = 22, /**< 22 SAMD21J16A Basic Timer Counter 7 (TC7) */
- ADC_IRQn = 23, /**< 23 SAMD21J16A Analog Digital Converter (ADC) */
- AC_IRQn = 24, /**< 24 SAMD21J16A Analog Comparators (AC) */
- DAC_IRQn = 25, /**< 25 SAMD21J16A Digital Analog Converter (DAC) */
- PTC_IRQn = 26, /**< 26 SAMD21J16A Peripheral Touch Controller (PTC) */
- I2S_IRQn = 27, /**< 27 SAMD21J16A Inter-IC Sound Interface (I2S) */
-
- PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+typedef enum IRQn {
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21J16A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21J16A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21J16A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21J16A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21J16A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21J16A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21J16A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21J16A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21J16A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21J16A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21J16A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21J16A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21J16A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21J16A Serial Communication Interface 3 (SERCOM3) */
+ SERCOM4_IRQn = 13, /**< 13 SAMD21J16A Serial Communication Interface 4 (SERCOM4) */
+ SERCOM5_IRQn = 14, /**< 14 SAMD21J16A Serial Communication Interface 5 (SERCOM5) */
+ TCC0_IRQn = 15, /**< 15 SAMD21J16A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21J16A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21J16A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21J16A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21J16A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21J16A Basic Timer Counter 5 (TC5) */
+ TC6_IRQn = 21, /**< 21 SAMD21J16A Basic Timer Counter 6 (TC6) */
+ TC7_IRQn = 22, /**< 22 SAMD21J16A Basic Timer Counter 7 (TC7) */
+ ADC_IRQn = 23, /**< 23 SAMD21J16A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21J16A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21J16A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21J16A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21J16A Inter-IC Sound Interface (I2S) */
+
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
-
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnReservedM12;
- void* pfnReservedM11;
- void* pfnReservedM10;
- void* pfnReservedM9;
- void* pfnReservedM8;
- void* pfnReservedM7;
- void* pfnReservedM6;
- void* pfnSVC_Handler;
- void* pfnReservedM4;
- void* pfnReservedM3;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
-
- /* Peripheral handlers */
- void* pfnPM_Handler; /* 0 Power Manager */
- void* pfnSYSCTRL_Handler; /* 1 System Control */
- void* pfnWDT_Handler; /* 2 Watchdog Timer */
- void* pfnRTC_Handler; /* 3 Real-Time Counter */
- void* pfnEIC_Handler; /* 4 External Interrupt Controller */
- void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
- void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
- void* pfnUSB_Handler; /* 7 Universal Serial Bus */
- void* pfnEVSYS_Handler; /* 8 Event System Interface */
- void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
- void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
- void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
- void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
- void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
- void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
- void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
- void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
- void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
- void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
- void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
- void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
- void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
- void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
- void* pfnADC_Handler; /* 23 Analog Digital Converter */
- void* pfnAC_Handler; /* 24 Analog Comparators */
- void* pfnDAC_Handler; /* 25 Digital Analog Converter */
- void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
- void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+typedef struct _DeviceVectors {
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
+ void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
+ void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@@ -229,7 +227,7 @@ void I2S_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21j16b.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21j16b.h
index 1d5f3c9590b..471dc95ce26 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21j16b.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21j16b.h
@@ -56,7 +56,7 @@
/*@{*/
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -90,99 +90,97 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
-typedef enum IRQn
-{
- /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
- /****** SAMD21J16B-specific Interrupt Numbers ***********************/
- PM_IRQn = 0, /**< 0 SAMD21J16B Power Manager (PM) */
- SYSCTRL_IRQn = 1, /**< 1 SAMD21J16B System Control (SYSCTRL) */
- WDT_IRQn = 2, /**< 2 SAMD21J16B Watchdog Timer (WDT) */
- RTC_IRQn = 3, /**< 3 SAMD21J16B Real-Time Counter (RTC) */
- EIC_IRQn = 4, /**< 4 SAMD21J16B External Interrupt Controller (EIC) */
- NVMCTRL_IRQn = 5, /**< 5 SAMD21J16B Non-Volatile Memory Controller (NVMCTRL) */
- DMAC_IRQn = 6, /**< 6 SAMD21J16B Direct Memory Access Controller (DMAC) */
- USB_IRQn = 7, /**< 7 SAMD21J16B Universal Serial Bus (USB) */
- EVSYS_IRQn = 8, /**< 8 SAMD21J16B Event System Interface (EVSYS) */
- SERCOM0_IRQn = 9, /**< 9 SAMD21J16B Serial Communication Interface 0 (SERCOM0) */
- SERCOM1_IRQn = 10, /**< 10 SAMD21J16B Serial Communication Interface 1 (SERCOM1) */
- SERCOM2_IRQn = 11, /**< 11 SAMD21J16B Serial Communication Interface 2 (SERCOM2) */
- SERCOM3_IRQn = 12, /**< 12 SAMD21J16B Serial Communication Interface 3 (SERCOM3) */
- SERCOM4_IRQn = 13, /**< 13 SAMD21J16B Serial Communication Interface 4 (SERCOM4) */
- SERCOM5_IRQn = 14, /**< 14 SAMD21J16B Serial Communication Interface 5 (SERCOM5) */
- TCC0_IRQn = 15, /**< 15 SAMD21J16B Timer Counter Control 0 (TCC0) */
- TCC1_IRQn = 16, /**< 16 SAMD21J16B Timer Counter Control 1 (TCC1) */
- TCC2_IRQn = 17, /**< 17 SAMD21J16B Timer Counter Control 2 (TCC2) */
- TC3_IRQn = 18, /**< 18 SAMD21J16B Basic Timer Counter 3 (TC3) */
- TC4_IRQn = 19, /**< 19 SAMD21J16B Basic Timer Counter 4 (TC4) */
- TC5_IRQn = 20, /**< 20 SAMD21J16B Basic Timer Counter 5 (TC5) */
- TC6_IRQn = 21, /**< 21 SAMD21J16B Basic Timer Counter 6 (TC6) */
- TC7_IRQn = 22, /**< 22 SAMD21J16B Basic Timer Counter 7 (TC7) */
- ADC_IRQn = 23, /**< 23 SAMD21J16B Analog Digital Converter (ADC) */
- AC_IRQn = 24, /**< 24 SAMD21J16B Analog Comparators (AC) */
- DAC_IRQn = 25, /**< 25 SAMD21J16B Digital Analog Converter (DAC) */
- PTC_IRQn = 26, /**< 26 SAMD21J16B Peripheral Touch Controller (PTC) */
- I2S_IRQn = 27, /**< 27 SAMD21J16B Inter-IC Sound Interface (I2S) */
-
- PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+typedef enum IRQn {
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21J16B-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21J16B Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21J16B System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21J16B Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21J16B Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21J16B External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21J16B Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21J16B Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21J16B Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21J16B Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21J16B Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21J16B Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21J16B Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21J16B Serial Communication Interface 3 (SERCOM3) */
+ SERCOM4_IRQn = 13, /**< 13 SAMD21J16B Serial Communication Interface 4 (SERCOM4) */
+ SERCOM5_IRQn = 14, /**< 14 SAMD21J16B Serial Communication Interface 5 (SERCOM5) */
+ TCC0_IRQn = 15, /**< 15 SAMD21J16B Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21J16B Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21J16B Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21J16B Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21J16B Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21J16B Basic Timer Counter 5 (TC5) */
+ TC6_IRQn = 21, /**< 21 SAMD21J16B Basic Timer Counter 6 (TC6) */
+ TC7_IRQn = 22, /**< 22 SAMD21J16B Basic Timer Counter 7 (TC7) */
+ ADC_IRQn = 23, /**< 23 SAMD21J16B Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21J16B Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21J16B Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21J16B Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21J16B Inter-IC Sound Interface (I2S) */
+
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
-
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnReservedM12;
- void* pfnReservedM11;
- void* pfnReservedM10;
- void* pfnReservedM9;
- void* pfnReservedM8;
- void* pfnReservedM7;
- void* pfnReservedM6;
- void* pfnSVC_Handler;
- void* pfnReservedM4;
- void* pfnReservedM3;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
-
- /* Peripheral handlers */
- void* pfnPM_Handler; /* 0 Power Manager */
- void* pfnSYSCTRL_Handler; /* 1 System Control */
- void* pfnWDT_Handler; /* 2 Watchdog Timer */
- void* pfnRTC_Handler; /* 3 Real-Time Counter */
- void* pfnEIC_Handler; /* 4 External Interrupt Controller */
- void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
- void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
- void* pfnUSB_Handler; /* 7 Universal Serial Bus */
- void* pfnEVSYS_Handler; /* 8 Event System Interface */
- void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
- void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
- void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
- void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
- void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
- void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
- void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
- void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
- void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
- void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
- void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
- void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
- void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
- void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
- void* pfnADC_Handler; /* 23 Analog Digital Converter */
- void* pfnAC_Handler; /* 24 Analog Comparators */
- void* pfnDAC_Handler; /* 25 Digital Analog Converter */
- void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
- void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
- void* pfnReserved28;
+typedef struct _DeviceVectors {
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
+ void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
+ void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+ void* pfnReserved28;
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@@ -227,7 +225,7 @@ void I2S_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21j17a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21j17a.h
index 0f9c74ef49d..c61c596149d 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21j17a.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21j17a.h
@@ -59,7 +59,7 @@
/*@{*/
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -93,98 +93,96 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
-typedef enum IRQn
-{
- /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
- /****** SAMD21J17A-specific Interrupt Numbers ***********************/
- PM_IRQn = 0, /**< 0 SAMD21J17A Power Manager (PM) */
- SYSCTRL_IRQn = 1, /**< 1 SAMD21J17A System Control (SYSCTRL) */
- WDT_IRQn = 2, /**< 2 SAMD21J17A Watchdog Timer (WDT) */
- RTC_IRQn = 3, /**< 3 SAMD21J17A Real-Time Counter (RTC) */
- EIC_IRQn = 4, /**< 4 SAMD21J17A External Interrupt Controller (EIC) */
- NVMCTRL_IRQn = 5, /**< 5 SAMD21J17A Non-Volatile Memory Controller (NVMCTRL) */
- DMAC_IRQn = 6, /**< 6 SAMD21J17A Direct Memory Access Controller (DMAC) */
- USB_IRQn = 7, /**< 7 SAMD21J17A Universal Serial Bus (USB) */
- EVSYS_IRQn = 8, /**< 8 SAMD21J17A Event System Interface (EVSYS) */
- SERCOM0_IRQn = 9, /**< 9 SAMD21J17A Serial Communication Interface 0 (SERCOM0) */
- SERCOM1_IRQn = 10, /**< 10 SAMD21J17A Serial Communication Interface 1 (SERCOM1) */
- SERCOM2_IRQn = 11, /**< 11 SAMD21J17A Serial Communication Interface 2 (SERCOM2) */
- SERCOM3_IRQn = 12, /**< 12 SAMD21J17A Serial Communication Interface 3 (SERCOM3) */
- SERCOM4_IRQn = 13, /**< 13 SAMD21J17A Serial Communication Interface 4 (SERCOM4) */
- SERCOM5_IRQn = 14, /**< 14 SAMD21J17A Serial Communication Interface 5 (SERCOM5) */
- TCC0_IRQn = 15, /**< 15 SAMD21J17A Timer Counter Control 0 (TCC0) */
- TCC1_IRQn = 16, /**< 16 SAMD21J17A Timer Counter Control 1 (TCC1) */
- TCC2_IRQn = 17, /**< 17 SAMD21J17A Timer Counter Control 2 (TCC2) */
- TC3_IRQn = 18, /**< 18 SAMD21J17A Basic Timer Counter 3 (TC3) */
- TC4_IRQn = 19, /**< 19 SAMD21J17A Basic Timer Counter 4 (TC4) */
- TC5_IRQn = 20, /**< 20 SAMD21J17A Basic Timer Counter 5 (TC5) */
- TC6_IRQn = 21, /**< 21 SAMD21J17A Basic Timer Counter 6 (TC6) */
- TC7_IRQn = 22, /**< 22 SAMD21J17A Basic Timer Counter 7 (TC7) */
- ADC_IRQn = 23, /**< 23 SAMD21J17A Analog Digital Converter (ADC) */
- AC_IRQn = 24, /**< 24 SAMD21J17A Analog Comparators (AC) */
- DAC_IRQn = 25, /**< 25 SAMD21J17A Digital Analog Converter (DAC) */
- PTC_IRQn = 26, /**< 26 SAMD21J17A Peripheral Touch Controller (PTC) */
- I2S_IRQn = 27, /**< 27 SAMD21J17A Inter-IC Sound Interface (I2S) */
-
- PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+typedef enum IRQn {
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21J17A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21J17A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21J17A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21J17A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21J17A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21J17A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21J17A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21J17A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21J17A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21J17A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21J17A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21J17A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21J17A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21J17A Serial Communication Interface 3 (SERCOM3) */
+ SERCOM4_IRQn = 13, /**< 13 SAMD21J17A Serial Communication Interface 4 (SERCOM4) */
+ SERCOM5_IRQn = 14, /**< 14 SAMD21J17A Serial Communication Interface 5 (SERCOM5) */
+ TCC0_IRQn = 15, /**< 15 SAMD21J17A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21J17A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21J17A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21J17A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21J17A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21J17A Basic Timer Counter 5 (TC5) */
+ TC6_IRQn = 21, /**< 21 SAMD21J17A Basic Timer Counter 6 (TC6) */
+ TC7_IRQn = 22, /**< 22 SAMD21J17A Basic Timer Counter 7 (TC7) */
+ ADC_IRQn = 23, /**< 23 SAMD21J17A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21J17A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21J17A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21J17A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21J17A Inter-IC Sound Interface (I2S) */
+
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
-
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnReservedM12;
- void* pfnReservedM11;
- void* pfnReservedM10;
- void* pfnReservedM9;
- void* pfnReservedM8;
- void* pfnReservedM7;
- void* pfnReservedM6;
- void* pfnSVC_Handler;
- void* pfnReservedM4;
- void* pfnReservedM3;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
-
- /* Peripheral handlers */
- void* pfnPM_Handler; /* 0 Power Manager */
- void* pfnSYSCTRL_Handler; /* 1 System Control */
- void* pfnWDT_Handler; /* 2 Watchdog Timer */
- void* pfnRTC_Handler; /* 3 Real-Time Counter */
- void* pfnEIC_Handler; /* 4 External Interrupt Controller */
- void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
- void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
- void* pfnUSB_Handler; /* 7 Universal Serial Bus */
- void* pfnEVSYS_Handler; /* 8 Event System Interface */
- void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
- void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
- void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
- void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
- void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
- void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
- void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
- void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
- void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
- void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
- void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
- void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
- void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
- void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
- void* pfnADC_Handler; /* 23 Analog Digital Converter */
- void* pfnAC_Handler; /* 24 Analog Comparators */
- void* pfnDAC_Handler; /* 25 Digital Analog Converter */
- void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
- void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+typedef struct _DeviceVectors {
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
+ void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
+ void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@@ -229,7 +227,7 @@ void I2S_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21j18a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21j18a.h
index c6835110f71..c00fccdfca8 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21j18a.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21j18a.h
@@ -59,7 +59,7 @@
/*@{*/
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -93,98 +93,96 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
-typedef enum IRQn
-{
- /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
- /****** SAMD21J18A-specific Interrupt Numbers ***********************/
- PM_IRQn = 0, /**< 0 SAMD21J18A Power Manager (PM) */
- SYSCTRL_IRQn = 1, /**< 1 SAMD21J18A System Control (SYSCTRL) */
- WDT_IRQn = 2, /**< 2 SAMD21J18A Watchdog Timer (WDT) */
- RTC_IRQn = 3, /**< 3 SAMD21J18A Real-Time Counter (RTC) */
- EIC_IRQn = 4, /**< 4 SAMD21J18A External Interrupt Controller (EIC) */
- NVMCTRL_IRQn = 5, /**< 5 SAMD21J18A Non-Volatile Memory Controller (NVMCTRL) */
- DMAC_IRQn = 6, /**< 6 SAMD21J18A Direct Memory Access Controller (DMAC) */
- USB_IRQn = 7, /**< 7 SAMD21J18A Universal Serial Bus (USB) */
- EVSYS_IRQn = 8, /**< 8 SAMD21J18A Event System Interface (EVSYS) */
- SERCOM0_IRQn = 9, /**< 9 SAMD21J18A Serial Communication Interface 0 (SERCOM0) */
- SERCOM1_IRQn = 10, /**< 10 SAMD21J18A Serial Communication Interface 1 (SERCOM1) */
- SERCOM2_IRQn = 11, /**< 11 SAMD21J18A Serial Communication Interface 2 (SERCOM2) */
- SERCOM3_IRQn = 12, /**< 12 SAMD21J18A Serial Communication Interface 3 (SERCOM3) */
- SERCOM4_IRQn = 13, /**< 13 SAMD21J18A Serial Communication Interface 4 (SERCOM4) */
- SERCOM5_IRQn = 14, /**< 14 SAMD21J18A Serial Communication Interface 5 (SERCOM5) */
- TCC0_IRQn = 15, /**< 15 SAMD21J18A Timer Counter Control 0 (TCC0) */
- TCC1_IRQn = 16, /**< 16 SAMD21J18A Timer Counter Control 1 (TCC1) */
- TCC2_IRQn = 17, /**< 17 SAMD21J18A Timer Counter Control 2 (TCC2) */
- TC3_IRQn = 18, /**< 18 SAMD21J18A Basic Timer Counter 3 (TC3) */
- TC4_IRQn = 19, /**< 19 SAMD21J18A Basic Timer Counter 4 (TC4) */
- TC5_IRQn = 20, /**< 20 SAMD21J18A Basic Timer Counter 5 (TC5) */
- TC6_IRQn = 21, /**< 21 SAMD21J18A Basic Timer Counter 6 (TC6) */
- TC7_IRQn = 22, /**< 22 SAMD21J18A Basic Timer Counter 7 (TC7) */
- ADC_IRQn = 23, /**< 23 SAMD21J18A Analog Digital Converter (ADC) */
- AC_IRQn = 24, /**< 24 SAMD21J18A Analog Comparators (AC) */
- DAC_IRQn = 25, /**< 25 SAMD21J18A Digital Analog Converter (DAC) */
- PTC_IRQn = 26, /**< 26 SAMD21J18A Peripheral Touch Controller (PTC) */
- I2S_IRQn = 27, /**< 27 SAMD21J18A Inter-IC Sound Interface (I2S) */
-
- PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+typedef enum IRQn {
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21J18A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21J18A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21J18A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21J18A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21J18A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21J18A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21J18A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21J18A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21J18A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21J18A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21J18A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21J18A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21J18A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21J18A Serial Communication Interface 3 (SERCOM3) */
+ SERCOM4_IRQn = 13, /**< 13 SAMD21J18A Serial Communication Interface 4 (SERCOM4) */
+ SERCOM5_IRQn = 14, /**< 14 SAMD21J18A Serial Communication Interface 5 (SERCOM5) */
+ TCC0_IRQn = 15, /**< 15 SAMD21J18A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21J18A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21J18A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21J18A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21J18A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21J18A Basic Timer Counter 5 (TC5) */
+ TC6_IRQn = 21, /**< 21 SAMD21J18A Basic Timer Counter 6 (TC6) */
+ TC7_IRQn = 22, /**< 22 SAMD21J18A Basic Timer Counter 7 (TC7) */
+ ADC_IRQn = 23, /**< 23 SAMD21J18A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21J18A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21J18A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21J18A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21J18A Inter-IC Sound Interface (I2S) */
+
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
-
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnReservedM12;
- void* pfnReservedM11;
- void* pfnReservedM10;
- void* pfnReservedM9;
- void* pfnReservedM8;
- void* pfnReservedM7;
- void* pfnReservedM6;
- void* pfnSVC_Handler;
- void* pfnReservedM4;
- void* pfnReservedM3;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
-
- /* Peripheral handlers */
- void* pfnPM_Handler; /* 0 Power Manager */
- void* pfnSYSCTRL_Handler; /* 1 System Control */
- void* pfnWDT_Handler; /* 2 Watchdog Timer */
- void* pfnRTC_Handler; /* 3 Real-Time Counter */
- void* pfnEIC_Handler; /* 4 External Interrupt Controller */
- void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
- void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
- void* pfnUSB_Handler; /* 7 Universal Serial Bus */
- void* pfnEVSYS_Handler; /* 8 Event System Interface */
- void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
- void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
- void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
- void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
- void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
- void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
- void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
- void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
- void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
- void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
- void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
- void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
- void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
- void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
- void* pfnADC_Handler; /* 23 Analog Digital Converter */
- void* pfnAC_Handler; /* 24 Analog Comparators */
- void* pfnDAC_Handler; /* 25 Digital Analog Converter */
- void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
- void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+typedef struct _DeviceVectors {
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
+ void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
+ void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@@ -229,7 +227,7 @@ void I2S_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_ac.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_ac.h
index c375dd16b20..1973b025f65 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_ac.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_ac.h
@@ -56,14 +56,14 @@
/* -------- AC_CTRLA : (AC Offset: 0x00) (R/W 8) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t SWRST:1; /*!< bit: 0 Software Reset */
- uint8_t ENABLE:1; /*!< bit: 1 Enable */
- uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */
- uint8_t :4; /*!< bit: 3.. 6 Reserved */
- uint8_t LPMUX:1; /*!< bit: 7 Low-Power Mux */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable */
+ uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */
+ uint8_t :4; /*!< bit: 3.. 6 Reserved */
+ uint8_t LPMUX:1; /*!< bit: 7 Low-Power Mux */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} AC_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -84,16 +84,16 @@ typedef union {
/* -------- AC_CTRLB : (AC Offset: 0x01) ( /W 8) Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t START0:1; /*!< bit: 0 Comparator 0 Start Comparison */
- uint8_t START1:1; /*!< bit: 1 Comparator 1 Start Comparison */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t START:2; /*!< bit: 0.. 1 Comparator x Start Comparison */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t START0:1; /*!< bit: 0 Comparator 0 Start Comparison */
+ uint8_t START1:1; /*!< bit: 1 Comparator 1 Start Comparison */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t START:2; /*!< bit: 0.. 1 Comparator x Start Comparison */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} AC_CTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -112,25 +112,25 @@ typedef union {
/* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t COMPEO0:1; /*!< bit: 0 Comparator 0 Event Output Enable */
- uint16_t COMPEO1:1; /*!< bit: 1 Comparator 1 Event Output Enable */
- uint16_t :2; /*!< bit: 2.. 3 Reserved */
- uint16_t WINEO0:1; /*!< bit: 4 Window 0 Event Output Enable */
- uint16_t :3; /*!< bit: 5.. 7 Reserved */
- uint16_t COMPEI0:1; /*!< bit: 8 Comparator 0 Event Input */
- uint16_t COMPEI1:1; /*!< bit: 9 Comparator 1 Event Input */
- uint16_t :6; /*!< bit: 10..15 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint16_t COMPEO:2; /*!< bit: 0.. 1 Comparator x Event Output Enable */
- uint16_t :2; /*!< bit: 2.. 3 Reserved */
- uint16_t WINEO:1; /*!< bit: 4 Window x Event Output Enable */
- uint16_t :3; /*!< bit: 5.. 7 Reserved */
- uint16_t COMPEI:2; /*!< bit: 8.. 9 Comparator x Event Input */
- uint16_t :6; /*!< bit: 10..15 Reserved */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t COMPEO0:1; /*!< bit: 0 Comparator 0 Event Output Enable */
+ uint16_t COMPEO1:1; /*!< bit: 1 Comparator 1 Event Output Enable */
+ uint16_t :2; /*!< bit: 2.. 3 Reserved */
+ uint16_t WINEO0:1; /*!< bit: 4 Window 0 Event Output Enable */
+ uint16_t :3; /*!< bit: 5.. 7 Reserved */
+ uint16_t COMPEI0:1; /*!< bit: 8 Comparator 0 Event Input */
+ uint16_t COMPEI1:1; /*!< bit: 9 Comparator 1 Event Input */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t COMPEO:2; /*!< bit: 0.. 1 Comparator x Event Output Enable */
+ uint16_t :2; /*!< bit: 2.. 3 Reserved */
+ uint16_t WINEO:1; /*!< bit: 4 Window x Event Output Enable */
+ uint16_t :3; /*!< bit: 5.. 7 Reserved */
+ uint16_t COMPEI:2; /*!< bit: 8.. 9 Comparator x Event Input */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
} AC_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -161,20 +161,20 @@ typedef union {
/* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */
- uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */
- uint8_t :2; /*!< bit: 2.. 3 Reserved */
- uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */
- uint8_t :3; /*!< bit: 5.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */
- uint8_t :2; /*!< bit: 2.. 3 Reserved */
- uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */
- uint8_t :3; /*!< bit: 5.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */
+ uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} AC_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -198,20 +198,20 @@ typedef union {
/* -------- AC_INTENSET : (AC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */
- uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */
- uint8_t :2; /*!< bit: 2.. 3 Reserved */
- uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */
- uint8_t :3; /*!< bit: 5.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */
- uint8_t :2; /*!< bit: 2.. 3 Reserved */
- uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */
- uint8_t :3; /*!< bit: 5.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */
+ uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} AC_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -235,20 +235,20 @@ typedef union {
/* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */
- __I uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */
- __I uint8_t :2; /*!< bit: 2.. 3 Reserved */
- __I uint8_t WIN0:1; /*!< bit: 4 Window 0 */
- __I uint8_t :3; /*!< bit: 5.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- __I uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x */
- __I uint8_t :2; /*!< bit: 2.. 3 Reserved */
- __I uint8_t WIN:1; /*!< bit: 4 Window x */
- __I uint8_t :3; /*!< bit: 5.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ __I uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */
+ __I uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */
+ __I uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ __I uint8_t WIN0:1; /*!< bit: 4 Window 0 */
+ __I uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ __I uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x */
+ __I uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ __I uint8_t WIN:1; /*!< bit: 4 Window x */
+ __I uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} AC_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -272,18 +272,18 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register
/* -------- AC_STATUSA : (AC Offset: 0x08) (R/ 8) Status A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */
- uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */
- uint8_t :2; /*!< bit: 2.. 3 Reserved */
- uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */
+ uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} AC_STATUSA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -311,17 +311,17 @@ typedef union {
/* -------- AC_STATUSB : (AC Offset: 0x09) (R/ 8) Status B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t READY0:1; /*!< bit: 0 Comparator 0 Ready */
- uint8_t READY1:1; /*!< bit: 1 Comparator 1 Ready */
- uint8_t :5; /*!< bit: 2.. 6 Reserved */
- uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t READY:2; /*!< bit: 0.. 1 Comparator x Ready */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t READY0:1; /*!< bit: 0 Comparator 0 Ready */
+ uint8_t READY1:1; /*!< bit: 1 Comparator 1 Ready */
+ uint8_t :5; /*!< bit: 2.. 6 Reserved */
+ uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t READY:2; /*!< bit: 0.. 1 Comparator x Ready */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} AC_STATUSB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -342,18 +342,18 @@ typedef union {
/* -------- AC_STATUSC : (AC Offset: 0x0A) (R/ 8) Status C -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */
- uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */
- uint8_t :2; /*!< bit: 2.. 3 Reserved */
- uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */
+ uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} AC_STATUSC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -381,12 +381,12 @@ typedef union {
/* -------- AC_WINCTRL : (AC Offset: 0x0C) (R/W 8) Window Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t WEN0:1; /*!< bit: 0 Window 0 Mode Enable */
- uint8_t WINTSEL0:2; /*!< bit: 1.. 2 Window 0 Interrupt Selection */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t WEN0:1; /*!< bit: 0 Window 0 Mode Enable */
+ uint8_t WINTSEL0:2; /*!< bit: 1.. 2 Window 0 Interrupt Selection */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} AC_WINCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -411,26 +411,26 @@ typedef union {
/* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t ENABLE:1; /*!< bit: 0 Enable */
- uint32_t SINGLE:1; /*!< bit: 1 Single-Shot Mode */
- uint32_t SPEED:2; /*!< bit: 2.. 3 Speed Selection */
- uint32_t :1; /*!< bit: 4 Reserved */
- uint32_t INTSEL:2; /*!< bit: 5.. 6 Interrupt Selection */
- uint32_t :1; /*!< bit: 7 Reserved */
- uint32_t MUXNEG:3; /*!< bit: 8..10 Negative Input Mux Selection */
- uint32_t :1; /*!< bit: 11 Reserved */
- uint32_t MUXPOS:2; /*!< bit: 12..13 Positive Input Mux Selection */
- uint32_t :1; /*!< bit: 14 Reserved */
- uint32_t SWAP:1; /*!< bit: 15 Swap Inputs and Invert */
- uint32_t OUT:2; /*!< bit: 16..17 Output */
- uint32_t :1; /*!< bit: 18 Reserved */
- uint32_t HYST:1; /*!< bit: 19 Hysteresis Enable */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t FLEN:3; /*!< bit: 24..26 Filter Length */
- uint32_t :5; /*!< bit: 27..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t ENABLE:1; /*!< bit: 0 Enable */
+ uint32_t SINGLE:1; /*!< bit: 1 Single-Shot Mode */
+ uint32_t SPEED:2; /*!< bit: 2.. 3 Speed Selection */
+ uint32_t :1; /*!< bit: 4 Reserved */
+ uint32_t INTSEL:2; /*!< bit: 5.. 6 Interrupt Selection */
+ uint32_t :1; /*!< bit: 7 Reserved */
+ uint32_t MUXNEG:3; /*!< bit: 8..10 Negative Input Mux Selection */
+ uint32_t :1; /*!< bit: 11 Reserved */
+ uint32_t MUXPOS:2; /*!< bit: 12..13 Positive Input Mux Selection */
+ uint32_t :1; /*!< bit: 14 Reserved */
+ uint32_t SWAP:1; /*!< bit: 15 Swap Inputs and Invert */
+ uint32_t OUT:2; /*!< bit: 16..17 Output */
+ uint32_t :1; /*!< bit: 18 Reserved */
+ uint32_t HYST:1; /*!< bit: 19 Hysteresis Enable */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t FLEN:3; /*!< bit: 24..26 Filter Length */
+ uint32_t :5; /*!< bit: 27..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} AC_COMPCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -516,11 +516,11 @@ typedef union {
/* -------- AC_SCALER : (AC Offset: 0x20) (R/W 8) Scaler n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t VALUE:6; /*!< bit: 0.. 5 Scaler Value */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t VALUE:6; /*!< bit: 0.. 5 Scaler Value */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} AC_SCALER_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -535,22 +535,22 @@ typedef union {
/** \brief AC hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO AC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
- __O AC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B */
- __IO AC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 16) Event Control */
- __IO AC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */
- __IO AC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */
- __IO AC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */
- RoReg8 Reserved1[0x1];
- __I AC_STATUSA_Type STATUSA; /**< \brief Offset: 0x08 (R/ 8) Status A */
- __I AC_STATUSB_Type STATUSB; /**< \brief Offset: 0x09 (R/ 8) Status B */
- __I AC_STATUSC_Type STATUSC; /**< \brief Offset: 0x0A (R/ 8) Status C */
- RoReg8 Reserved2[0x1];
- __IO AC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x0C (R/W 8) Window Control */
- RoReg8 Reserved3[0x3];
- __IO AC_COMPCTRL_Type COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */
- RoReg8 Reserved4[0x8];
- __IO AC_SCALER_Type SCALER[2]; /**< \brief Offset: 0x20 (R/W 8) Scaler n */
+ __IO AC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
+ __O AC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B */
+ __IO AC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 16) Event Control */
+ __IO AC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */
+ __IO AC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */
+ __IO AC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */
+ RoReg8 Reserved1[0x1];
+ __I AC_STATUSA_Type STATUSA; /**< \brief Offset: 0x08 (R/ 8) Status A */
+ __I AC_STATUSB_Type STATUSB; /**< \brief Offset: 0x09 (R/ 8) Status B */
+ __I AC_STATUSC_Type STATUSC; /**< \brief Offset: 0x0A (R/ 8) Status C */
+ RoReg8 Reserved2[0x1];
+ __IO AC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x0C (R/W 8) Window Control */
+ RoReg8 Reserved3[0x3];
+ __IO AC_COMPCTRL_Type COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */
+ RoReg8 Reserved4[0x8];
+ __IO AC_SCALER_Type SCALER[2]; /**< \brief Offset: 0x20 (R/W 8) Scaler n */
} Ac;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_adc.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_adc.h
index 256d4f2b4db..871f0bff690 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_adc.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_adc.h
@@ -56,13 +56,13 @@
/* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 8) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t SWRST:1; /*!< bit: 0 Software Reset */
- uint8_t ENABLE:1; /*!< bit: 1 Enable */
- uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable */
+ uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} ADC_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -80,12 +80,12 @@ typedef union {
/* -------- ADC_REFCTRL : (ADC Offset: 0x01) (R/W 8) Reference Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t REFSEL:4; /*!< bit: 0.. 3 Reference Selection */
- uint8_t :3; /*!< bit: 4.. 6 Reserved */
- uint8_t REFCOMP:1; /*!< bit: 7 Reference Buffer Offset Compensation Enable */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t REFSEL:4; /*!< bit: 0.. 3 Reference Selection */
+ uint8_t :3; /*!< bit: 4.. 6 Reserved */
+ uint8_t REFCOMP:1; /*!< bit: 7 Reference Buffer Offset Compensation Enable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} ADC_REFCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -112,12 +112,12 @@ typedef union {
/* -------- ADC_AVGCTRL : (ADC Offset: 0x02) (R/W 8) Average Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t SAMPLENUM:4; /*!< bit: 0.. 3 Number of Samples to be Collected */
- uint8_t ADJRES:3; /*!< bit: 4.. 6 Adjusting Result / Division Coefficient */
- uint8_t :1; /*!< bit: 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t SAMPLENUM:4; /*!< bit: 0.. 3 Number of Samples to be Collected */
+ uint8_t ADJRES:3; /*!< bit: 4.. 6 Adjusting Result / Division Coefficient */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} ADC_AVGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -157,11 +157,11 @@ typedef union {
/* -------- ADC_SAMPCTRL : (ADC Offset: 0x03) (R/W 8) Sampling Time Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t SAMPLEN:6; /*!< bit: 0.. 5 Sampling Time Length */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t SAMPLEN:6; /*!< bit: 0.. 5 Sampling Time Length */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} ADC_SAMPCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -176,17 +176,17 @@ typedef union {
/* -------- ADC_CTRLB : (ADC Offset: 0x04) (R/W 16) Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t DIFFMODE:1; /*!< bit: 0 Differential Mode */
- uint16_t LEFTADJ:1; /*!< bit: 1 Left-Adjusted Result */
- uint16_t FREERUN:1; /*!< bit: 2 Free Running Mode */
- uint16_t CORREN:1; /*!< bit: 3 Digital Correction Logic Enabled */
- uint16_t RESSEL:2; /*!< bit: 4.. 5 Conversion Result Resolution */
- uint16_t :2; /*!< bit: 6.. 7 Reserved */
- uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler Configuration */
- uint16_t :5; /*!< bit: 11..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t DIFFMODE:1; /*!< bit: 0 Differential Mode */
+ uint16_t LEFTADJ:1; /*!< bit: 1 Left-Adjusted Result */
+ uint16_t FREERUN:1; /*!< bit: 2 Free Running Mode */
+ uint16_t CORREN:1; /*!< bit: 3 Digital Correction Logic Enabled */
+ uint16_t RESSEL:2; /*!< bit: 4.. 5 Conversion Result Resolution */
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler Configuration */
+ uint16_t :5; /*!< bit: 11..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} ADC_CTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -236,11 +236,11 @@ typedef union {
/* -------- ADC_WINCTRL : (ADC Offset: 0x08) (R/W 8) Window Monitor Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t WINMODE:3; /*!< bit: 0.. 2 Window Monitor Mode */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t WINMODE:3; /*!< bit: 0.. 2 Window Monitor Mode */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} ADC_WINCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -265,12 +265,12 @@ typedef union {
/* -------- ADC_SWTRIG : (ADC Offset: 0x0C) (R/W 8) Software Trigger -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t FLUSH:1; /*!< bit: 0 ADC Conversion Flush */
- uint8_t START:1; /*!< bit: 1 ADC Start Conversion */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t FLUSH:1; /*!< bit: 0 ADC Conversion Flush */
+ uint8_t START:1; /*!< bit: 1 ADC Start Conversion */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} ADC_SWTRIG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -286,17 +286,17 @@ typedef union {
/* -------- ADC_INPUTCTRL : (ADC Offset: 0x10) (R/W 32) Input Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t MUXPOS:5; /*!< bit: 0.. 4 Positive Mux Input Selection */
- uint32_t :3; /*!< bit: 5.. 7 Reserved */
- uint32_t MUXNEG:5; /*!< bit: 8..12 Negative Mux Input Selection */
- uint32_t :3; /*!< bit: 13..15 Reserved */
- uint32_t INPUTSCAN:4; /*!< bit: 16..19 Number of Input Channels Included in Scan */
- uint32_t INPUTOFFSET:4; /*!< bit: 20..23 Positive Mux Setting Offset */
- uint32_t GAIN:4; /*!< bit: 24..27 Gain Factor Selection */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t MUXPOS:5; /*!< bit: 0.. 4 Positive Mux Input Selection */
+ uint32_t :3; /*!< bit: 5.. 7 Reserved */
+ uint32_t MUXNEG:5; /*!< bit: 8..12 Negative Mux Input Selection */
+ uint32_t :3; /*!< bit: 13..15 Reserved */
+ uint32_t INPUTSCAN:4; /*!< bit: 16..19 Number of Input Channels Included in Scan */
+ uint32_t INPUTOFFSET:4; /*!< bit: 20..23 Positive Mux Setting Offset */
+ uint32_t GAIN:4; /*!< bit: 24..27 Gain Factor Selection */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} ADC_INPUTCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -405,15 +405,15 @@ typedef union {
/* -------- ADC_EVCTRL : (ADC Offset: 0x14) (R/W 8) Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event In */
- uint8_t SYNCEI:1; /*!< bit: 1 Synchronization Event In */
- uint8_t :2; /*!< bit: 2.. 3 Reserved */
- uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */
- uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event In */
+ uint8_t SYNCEI:1; /*!< bit: 1 Synchronization Event In */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */
+ uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} ADC_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -433,14 +433,14 @@ typedef union {
/* -------- ADC_INTENCLR : (ADC Offset: 0x16) (R/W 8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */
- uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */
- uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */
- uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
- uint8_t :4; /*!< bit: 4.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */
+ uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */
+ uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */
+ uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} ADC_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -460,14 +460,14 @@ typedef union {
/* -------- ADC_INTENSET : (ADC Offset: 0x17) (R/W 8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */
- uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */
- uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */
- uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
- uint8_t :4; /*!< bit: 4.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */
+ uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */
+ uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */
+ uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} ADC_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -487,14 +487,14 @@ typedef union {
/* -------- ADC_INTFLAG : (ADC Offset: 0x18) (R/W 8) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint8_t RESRDY:1; /*!< bit: 0 Result Ready */
- __I uint8_t OVERRUN:1; /*!< bit: 1 Overrun */
- __I uint8_t WINMON:1; /*!< bit: 2 Window Monitor */
- __I uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */
- __I uint8_t :4; /*!< bit: 4.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ __I uint8_t RESRDY:1; /*!< bit: 0 Result Ready */
+ __I uint8_t OVERRUN:1; /*!< bit: 1 Overrun */
+ __I uint8_t WINMON:1; /*!< bit: 2 Window Monitor */
+ __I uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */
+ __I uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} ADC_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -514,11 +514,11 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register
/* -------- ADC_STATUS : (ADC Offset: 0x19) (R/ 8) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t :7; /*!< bit: 0.. 6 Reserved */
- uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t :7; /*!< bit: 0.. 6 Reserved */
+ uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} ADC_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -532,10 +532,10 @@ typedef union {
/* -------- ADC_RESULT : (ADC Offset: 0x1A) (R/ 16) Result -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t RESULT:16; /*!< bit: 0..15 Result Conversion Value */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t RESULT:16; /*!< bit: 0..15 Result Conversion Value */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} ADC_RESULT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -550,10 +550,10 @@ typedef union {
/* -------- ADC_WINLT : (ADC Offset: 0x1C) (R/W 16) Window Monitor Lower Threshold -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t WINLT:16; /*!< bit: 0..15 Window Lower Threshold */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t WINLT:16; /*!< bit: 0..15 Window Lower Threshold */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} ADC_WINLT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -568,10 +568,10 @@ typedef union {
/* -------- ADC_WINUT : (ADC Offset: 0x20) (R/W 16) Window Monitor Upper Threshold -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t WINUT:16; /*!< bit: 0..15 Window Upper Threshold */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t WINUT:16; /*!< bit: 0..15 Window Upper Threshold */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} ADC_WINUT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -586,11 +586,11 @@ typedef union {
/* -------- ADC_GAINCORR : (ADC Offset: 0x24) (R/W 16) Gain Correction -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t GAINCORR:12; /*!< bit: 0..11 Gain Correction Value */
- uint16_t :4; /*!< bit: 12..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t GAINCORR:12; /*!< bit: 0..11 Gain Correction Value */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} ADC_GAINCORR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -605,11 +605,11 @@ typedef union {
/* -------- ADC_OFFSETCORR : (ADC Offset: 0x26) (R/W 16) Offset Correction -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t OFFSETCORR:12; /*!< bit: 0..11 Offset Correction Value */
- uint16_t :4; /*!< bit: 12..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t OFFSETCORR:12; /*!< bit: 0..11 Offset Correction Value */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} ADC_OFFSETCORR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -624,12 +624,12 @@ typedef union {
/* -------- ADC_CALIB : (ADC Offset: 0x28) (R/W 16) Calibration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t LINEARITY_CAL:8; /*!< bit: 0.. 7 Linearity Calibration Value */
- uint16_t BIAS_CAL:3; /*!< bit: 8..10 Bias Calibration Value */
- uint16_t :5; /*!< bit: 11..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t LINEARITY_CAL:8; /*!< bit: 0.. 7 Linearity Calibration Value */
+ uint16_t BIAS_CAL:3; /*!< bit: 8..10 Bias Calibration Value */
+ uint16_t :5; /*!< bit: 11..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} ADC_CALIB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -647,11 +647,11 @@ typedef union {
/* -------- ADC_DBGCTRL : (ADC Offset: 0x2A) (R/W 8) Debug Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} ADC_DBGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -665,32 +665,32 @@ typedef union {
/** \brief ADC hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO ADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
- __IO ADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x01 (R/W 8) Reference Control */
- __IO ADC_AVGCTRL_Type AVGCTRL; /**< \brief Offset: 0x02 (R/W 8) Average Control */
- __IO ADC_SAMPCTRL_Type SAMPCTRL; /**< \brief Offset: 0x03 (R/W 8) Sampling Time Control */
- __IO ADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 16) Control B */
- RoReg8 Reserved1[0x2];
- __IO ADC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x08 (R/W 8) Window Monitor Control */
- RoReg8 Reserved2[0x3];
- __IO ADC_SWTRIG_Type SWTRIG; /**< \brief Offset: 0x0C (R/W 8) Software Trigger */
- RoReg8 Reserved3[0x3];
- __IO ADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x10 (R/W 32) Input Control */
- __IO ADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x14 (R/W 8) Event Control */
- RoReg8 Reserved4[0x1];
- __IO ADC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x16 (R/W 8) Interrupt Enable Clear */
- __IO ADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x17 (R/W 8) Interrupt Enable Set */
- __IO ADC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) Interrupt Flag Status and Clear */
- __I ADC_STATUS_Type STATUS; /**< \brief Offset: 0x19 (R/ 8) Status */
- __I ADC_RESULT_Type RESULT; /**< \brief Offset: 0x1A (R/ 16) Result */
- __IO ADC_WINLT_Type WINLT; /**< \brief Offset: 0x1C (R/W 16) Window Monitor Lower Threshold */
- RoReg8 Reserved5[0x2];
- __IO ADC_WINUT_Type WINUT; /**< \brief Offset: 0x20 (R/W 16) Window Monitor Upper Threshold */
- RoReg8 Reserved6[0x2];
- __IO ADC_GAINCORR_Type GAINCORR; /**< \brief Offset: 0x24 (R/W 16) Gain Correction */
- __IO ADC_OFFSETCORR_Type OFFSETCORR; /**< \brief Offset: 0x26 (R/W 16) Offset Correction */
- __IO ADC_CALIB_Type CALIB; /**< \brief Offset: 0x28 (R/W 16) Calibration */
- __IO ADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x2A (R/W 8) Debug Control */
+ __IO ADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
+ __IO ADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x01 (R/W 8) Reference Control */
+ __IO ADC_AVGCTRL_Type AVGCTRL; /**< \brief Offset: 0x02 (R/W 8) Average Control */
+ __IO ADC_SAMPCTRL_Type SAMPCTRL; /**< \brief Offset: 0x03 (R/W 8) Sampling Time Control */
+ __IO ADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 16) Control B */
+ RoReg8 Reserved1[0x2];
+ __IO ADC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x08 (R/W 8) Window Monitor Control */
+ RoReg8 Reserved2[0x3];
+ __IO ADC_SWTRIG_Type SWTRIG; /**< \brief Offset: 0x0C (R/W 8) Software Trigger */
+ RoReg8 Reserved3[0x3];
+ __IO ADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x10 (R/W 32) Input Control */
+ __IO ADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x14 (R/W 8) Event Control */
+ RoReg8 Reserved4[0x1];
+ __IO ADC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x16 (R/W 8) Interrupt Enable Clear */
+ __IO ADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x17 (R/W 8) Interrupt Enable Set */
+ __IO ADC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) Interrupt Flag Status and Clear */
+ __I ADC_STATUS_Type STATUS; /**< \brief Offset: 0x19 (R/ 8) Status */
+ __I ADC_RESULT_Type RESULT; /**< \brief Offset: 0x1A (R/ 16) Result */
+ __IO ADC_WINLT_Type WINLT; /**< \brief Offset: 0x1C (R/W 16) Window Monitor Lower Threshold */
+ RoReg8 Reserved5[0x2];
+ __IO ADC_WINUT_Type WINUT; /**< \brief Offset: 0x20 (R/W 16) Window Monitor Upper Threshold */
+ RoReg8 Reserved6[0x2];
+ __IO ADC_GAINCORR_Type GAINCORR; /**< \brief Offset: 0x24 (R/W 16) Gain Correction */
+ __IO ADC_OFFSETCORR_Type OFFSETCORR; /**< \brief Offset: 0x26 (R/W 16) Offset Correction */
+ __IO ADC_CALIB_Type CALIB; /**< \brief Offset: 0x28 (R/W 16) Calibration */
+ __IO ADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x2A (R/W 8) Debug Control */
} Adc;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_dmac.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_dmac.h
index 18d086f946b..8ddc41bb5d6 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_dmac.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_dmac.h
@@ -56,23 +56,23 @@
/* -------- DMAC_CTRL : (DMAC Offset: 0x00) (R/W 16) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t SWRST:1; /*!< bit: 0 Software Reset */
- uint16_t DMAENABLE:1; /*!< bit: 1 DMA Enable */
- uint16_t CRCENABLE:1; /*!< bit: 2 CRC Enable */
- uint16_t :5; /*!< bit: 3.. 7 Reserved */
- uint16_t LVLEN0:1; /*!< bit: 8 Priority Level 0 Enable */
- uint16_t LVLEN1:1; /*!< bit: 9 Priority Level 1 Enable */
- uint16_t LVLEN2:1; /*!< bit: 10 Priority Level 2 Enable */
- uint16_t LVLEN3:1; /*!< bit: 11 Priority Level 3 Enable */
- uint16_t :4; /*!< bit: 12..15 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint16_t :8; /*!< bit: 0.. 7 Reserved */
- uint16_t LVLEN:4; /*!< bit: 8..11 Priority Level x Enable */
- uint16_t :4; /*!< bit: 12..15 Reserved */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint16_t DMAENABLE:1; /*!< bit: 1 DMA Enable */
+ uint16_t CRCENABLE:1; /*!< bit: 2 CRC Enable */
+ uint16_t :5; /*!< bit: 3.. 7 Reserved */
+ uint16_t LVLEN0:1; /*!< bit: 8 Priority Level 0 Enable */
+ uint16_t LVLEN1:1; /*!< bit: 9 Priority Level 1 Enable */
+ uint16_t LVLEN2:1; /*!< bit: 10 Priority Level 2 Enable */
+ uint16_t LVLEN3:1; /*!< bit: 11 Priority Level 3 Enable */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t :8; /*!< bit: 0.. 7 Reserved */
+ uint16_t LVLEN:4; /*!< bit: 8..11 Priority Level x Enable */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
} DMAC_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -101,14 +101,14 @@ typedef union {
/* -------- DMAC_CRCCTRL : (DMAC Offset: 0x02) (R/W 16) CRC Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t CRCBEATSIZE:2; /*!< bit: 0.. 1 CRC Beat Size */
- uint16_t CRCPOLY:2; /*!< bit: 2.. 3 CRC Polynomial Type */
- uint16_t :4; /*!< bit: 4.. 7 Reserved */
- uint16_t CRCSRC:6; /*!< bit: 8..13 CRC Input Source */
- uint16_t :2; /*!< bit: 14..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t CRCBEATSIZE:2; /*!< bit: 0.. 1 CRC Beat Size */
+ uint16_t CRCPOLY:2; /*!< bit: 2.. 3 CRC Polynomial Type */
+ uint16_t :4; /*!< bit: 4.. 7 Reserved */
+ uint16_t CRCSRC:6; /*!< bit: 8..13 CRC Input Source */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} DMAC_CRCCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -143,10 +143,10 @@ typedef union {
/* -------- DMAC_CRCDATAIN : (DMAC Offset: 0x04) (R/W 32) CRC Data Input -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t CRCDATAIN:32; /*!< bit: 0..31 CRC Data Input */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t CRCDATAIN:32; /*!< bit: 0..31 CRC Data Input */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DMAC_CRCDATAIN_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -161,10 +161,10 @@ typedef union {
/* -------- DMAC_CRCCHKSUM : (DMAC Offset: 0x08) (R/W 32) CRC Checksum -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t CRCCHKSUM:32; /*!< bit: 0..31 CRC Checksum */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t CRCCHKSUM:32; /*!< bit: 0..31 CRC Checksum */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DMAC_CRCCHKSUM_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -179,12 +179,12 @@ typedef union {
/* -------- DMAC_CRCSTATUS : (DMAC Offset: 0x0C) (R/W 8) CRC Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t CRCBUSY:1; /*!< bit: 0 CRC Module Busy */
- uint8_t CRCZERO:1; /*!< bit: 1 CRC Zero */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t CRCBUSY:1; /*!< bit: 0 CRC Module Busy */
+ uint8_t CRCZERO:1; /*!< bit: 1 CRC Zero */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} DMAC_CRCSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -200,11 +200,11 @@ typedef union {
/* -------- DMAC_DBGCTRL : (DMAC Offset: 0x0D) (R/W 8) Debug Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} DMAC_DBGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -218,13 +218,13 @@ typedef union {
/* -------- DMAC_QOSCTRL : (DMAC Offset: 0x0E) (R/W 8) QOS Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t WRBQOS:2; /*!< bit: 0.. 1 Write-Back Quality of Service */
- uint8_t FQOS:2; /*!< bit: 2.. 3 Fetch Quality of Service */
- uint8_t DQOS:2; /*!< bit: 4.. 5 Data Transfer Quality of Service */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t WRBQOS:2; /*!< bit: 0.. 1 Write-Back Quality of Service */
+ uint8_t FQOS:2; /*!< bit: 2.. 3 Fetch Quality of Service */
+ uint8_t DQOS:2; /*!< bit: 4.. 5 Data Transfer Quality of Service */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} DMAC_QOSCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -269,26 +269,26 @@ typedef union {
/* -------- DMAC_SWTRIGCTRL : (DMAC Offset: 0x10) (R/W 32) Software Trigger Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SWTRIG0:1; /*!< bit: 0 Channel 0 Software Trigger */
- uint32_t SWTRIG1:1; /*!< bit: 1 Channel 1 Software Trigger */
- uint32_t SWTRIG2:1; /*!< bit: 2 Channel 2 Software Trigger */
- uint32_t SWTRIG3:1; /*!< bit: 3 Channel 3 Software Trigger */
- uint32_t SWTRIG4:1; /*!< bit: 4 Channel 4 Software Trigger */
- uint32_t SWTRIG5:1; /*!< bit: 5 Channel 5 Software Trigger */
- uint32_t SWTRIG6:1; /*!< bit: 6 Channel 6 Software Trigger */
- uint32_t SWTRIG7:1; /*!< bit: 7 Channel 7 Software Trigger */
- uint32_t SWTRIG8:1; /*!< bit: 8 Channel 8 Software Trigger */
- uint32_t SWTRIG9:1; /*!< bit: 9 Channel 9 Software Trigger */
- uint32_t SWTRIG10:1; /*!< bit: 10 Channel 10 Software Trigger */
- uint32_t SWTRIG11:1; /*!< bit: 11 Channel 11 Software Trigger */
- uint32_t :20; /*!< bit: 12..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t SWTRIG:12; /*!< bit: 0..11 Channel x Software Trigger */
- uint32_t :20; /*!< bit: 12..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SWTRIG0:1; /*!< bit: 0 Channel 0 Software Trigger */
+ uint32_t SWTRIG1:1; /*!< bit: 1 Channel 1 Software Trigger */
+ uint32_t SWTRIG2:1; /*!< bit: 2 Channel 2 Software Trigger */
+ uint32_t SWTRIG3:1; /*!< bit: 3 Channel 3 Software Trigger */
+ uint32_t SWTRIG4:1; /*!< bit: 4 Channel 4 Software Trigger */
+ uint32_t SWTRIG5:1; /*!< bit: 5 Channel 5 Software Trigger */
+ uint32_t SWTRIG6:1; /*!< bit: 6 Channel 6 Software Trigger */
+ uint32_t SWTRIG7:1; /*!< bit: 7 Channel 7 Software Trigger */
+ uint32_t SWTRIG8:1; /*!< bit: 8 Channel 8 Software Trigger */
+ uint32_t SWTRIG9:1; /*!< bit: 9 Channel 9 Software Trigger */
+ uint32_t SWTRIG10:1; /*!< bit: 10 Channel 10 Software Trigger */
+ uint32_t SWTRIG11:1; /*!< bit: 11 Channel 11 Software Trigger */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t SWTRIG:12; /*!< bit: 0..11 Channel x Software Trigger */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} DMAC_SWTRIGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -327,21 +327,21 @@ typedef union {
/* -------- DMAC_PRICTRL0 : (DMAC Offset: 0x14) (R/W 32) Priority Control 0 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t LVLPRI0:4; /*!< bit: 0.. 3 Level 0 Channel Priority Number */
- uint32_t :3; /*!< bit: 4.. 6 Reserved */
- uint32_t RRLVLEN0:1; /*!< bit: 7 Level 0 Round-Robin Scheduling Enable */
- uint32_t LVLPRI1:4; /*!< bit: 8..11 Level 1 Channel Priority Number */
- uint32_t :3; /*!< bit: 12..14 Reserved */
- uint32_t RRLVLEN1:1; /*!< bit: 15 Level 1 Round-Robin Scheduling Enable */
- uint32_t LVLPRI2:4; /*!< bit: 16..19 Level 2 Channel Priority Number */
- uint32_t :3; /*!< bit: 20..22 Reserved */
- uint32_t RRLVLEN2:1; /*!< bit: 23 Level 2 Round-Robin Scheduling Enable */
- uint32_t LVLPRI3:4; /*!< bit: 24..27 Level 3 Channel Priority Number */
- uint32_t :3; /*!< bit: 28..30 Reserved */
- uint32_t RRLVLEN3:1; /*!< bit: 31 Level 3 Round-Robin Scheduling Enable */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t LVLPRI0:4; /*!< bit: 0.. 3 Level 0 Channel Priority Number */
+ uint32_t :3; /*!< bit: 4.. 6 Reserved */
+ uint32_t RRLVLEN0:1; /*!< bit: 7 Level 0 Round-Robin Scheduling Enable */
+ uint32_t LVLPRI1:4; /*!< bit: 8..11 Level 1 Channel Priority Number */
+ uint32_t :3; /*!< bit: 12..14 Reserved */
+ uint32_t RRLVLEN1:1; /*!< bit: 15 Level 1 Round-Robin Scheduling Enable */
+ uint32_t LVLPRI2:4; /*!< bit: 16..19 Level 2 Channel Priority Number */
+ uint32_t :3; /*!< bit: 20..22 Reserved */
+ uint32_t RRLVLEN2:1; /*!< bit: 23 Level 2 Round-Robin Scheduling Enable */
+ uint32_t LVLPRI3:4; /*!< bit: 24..27 Level 3 Channel Priority Number */
+ uint32_t :3; /*!< bit: 28..30 Reserved */
+ uint32_t RRLVLEN3:1; /*!< bit: 31 Level 3 Round-Robin Scheduling Enable */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DMAC_PRICTRL0_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -373,18 +373,18 @@ typedef union {
/* -------- DMAC_INTPEND : (DMAC Offset: 0x20) (R/W 16) Interrupt Pending -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t ID:4; /*!< bit: 0.. 3 Channel ID */
- uint16_t :4; /*!< bit: 4.. 7 Reserved */
- uint16_t TERR:1; /*!< bit: 8 Transfer Error */
- uint16_t TCMPL:1; /*!< bit: 9 Transfer Complete */
- uint16_t SUSP:1; /*!< bit: 10 Channel Suspend */
- uint16_t :2; /*!< bit: 11..12 Reserved */
- uint16_t FERR:1; /*!< bit: 13 Fetch Error */
- uint16_t BUSY:1; /*!< bit: 14 Busy */
- uint16_t PEND:1; /*!< bit: 15 Pending */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t ID:4; /*!< bit: 0.. 3 Channel ID */
+ uint16_t :4; /*!< bit: 4.. 7 Reserved */
+ uint16_t TERR:1; /*!< bit: 8 Transfer Error */
+ uint16_t TCMPL:1; /*!< bit: 9 Transfer Complete */
+ uint16_t SUSP:1; /*!< bit: 10 Channel Suspend */
+ uint16_t :2; /*!< bit: 11..12 Reserved */
+ uint16_t FERR:1; /*!< bit: 13 Fetch Error */
+ uint16_t BUSY:1; /*!< bit: 14 Busy */
+ uint16_t PEND:1; /*!< bit: 15 Pending */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} DMAC_INTPEND_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -411,26 +411,26 @@ typedef union {
/* -------- DMAC_INTSTATUS : (DMAC Offset: 0x24) (R/ 32) Interrupt Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t CHINT0:1; /*!< bit: 0 Channel 0 Pending Interrupt */
- uint32_t CHINT1:1; /*!< bit: 1 Channel 1 Pending Interrupt */
- uint32_t CHINT2:1; /*!< bit: 2 Channel 2 Pending Interrupt */
- uint32_t CHINT3:1; /*!< bit: 3 Channel 3 Pending Interrupt */
- uint32_t CHINT4:1; /*!< bit: 4 Channel 4 Pending Interrupt */
- uint32_t CHINT5:1; /*!< bit: 5 Channel 5 Pending Interrupt */
- uint32_t CHINT6:1; /*!< bit: 6 Channel 6 Pending Interrupt */
- uint32_t CHINT7:1; /*!< bit: 7 Channel 7 Pending Interrupt */
- uint32_t CHINT8:1; /*!< bit: 8 Channel 8 Pending Interrupt */
- uint32_t CHINT9:1; /*!< bit: 9 Channel 9 Pending Interrupt */
- uint32_t CHINT10:1; /*!< bit: 10 Channel 10 Pending Interrupt */
- uint32_t CHINT11:1; /*!< bit: 11 Channel 11 Pending Interrupt */
- uint32_t :20; /*!< bit: 12..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t CHINT:12; /*!< bit: 0..11 Channel x Pending Interrupt */
- uint32_t :20; /*!< bit: 12..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t CHINT0:1; /*!< bit: 0 Channel 0 Pending Interrupt */
+ uint32_t CHINT1:1; /*!< bit: 1 Channel 1 Pending Interrupt */
+ uint32_t CHINT2:1; /*!< bit: 2 Channel 2 Pending Interrupt */
+ uint32_t CHINT3:1; /*!< bit: 3 Channel 3 Pending Interrupt */
+ uint32_t CHINT4:1; /*!< bit: 4 Channel 4 Pending Interrupt */
+ uint32_t CHINT5:1; /*!< bit: 5 Channel 5 Pending Interrupt */
+ uint32_t CHINT6:1; /*!< bit: 6 Channel 6 Pending Interrupt */
+ uint32_t CHINT7:1; /*!< bit: 7 Channel 7 Pending Interrupt */
+ uint32_t CHINT8:1; /*!< bit: 8 Channel 8 Pending Interrupt */
+ uint32_t CHINT9:1; /*!< bit: 9 Channel 9 Pending Interrupt */
+ uint32_t CHINT10:1; /*!< bit: 10 Channel 10 Pending Interrupt */
+ uint32_t CHINT11:1; /*!< bit: 11 Channel 11 Pending Interrupt */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t CHINT:12; /*!< bit: 0..11 Channel x Pending Interrupt */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} DMAC_INTSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -469,26 +469,26 @@ typedef union {
/* -------- DMAC_BUSYCH : (DMAC Offset: 0x28) (R/ 32) Busy Channels -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t BUSYCH0:1; /*!< bit: 0 Busy Channel 0 */
- uint32_t BUSYCH1:1; /*!< bit: 1 Busy Channel 1 */
- uint32_t BUSYCH2:1; /*!< bit: 2 Busy Channel 2 */
- uint32_t BUSYCH3:1; /*!< bit: 3 Busy Channel 3 */
- uint32_t BUSYCH4:1; /*!< bit: 4 Busy Channel 4 */
- uint32_t BUSYCH5:1; /*!< bit: 5 Busy Channel 5 */
- uint32_t BUSYCH6:1; /*!< bit: 6 Busy Channel 6 */
- uint32_t BUSYCH7:1; /*!< bit: 7 Busy Channel 7 */
- uint32_t BUSYCH8:1; /*!< bit: 8 Busy Channel 8 */
- uint32_t BUSYCH9:1; /*!< bit: 9 Busy Channel 9 */
- uint32_t BUSYCH10:1; /*!< bit: 10 Busy Channel 10 */
- uint32_t BUSYCH11:1; /*!< bit: 11 Busy Channel 11 */
- uint32_t :20; /*!< bit: 12..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t BUSYCH:12; /*!< bit: 0..11 Busy Channel x */
- uint32_t :20; /*!< bit: 12..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t BUSYCH0:1; /*!< bit: 0 Busy Channel 0 */
+ uint32_t BUSYCH1:1; /*!< bit: 1 Busy Channel 1 */
+ uint32_t BUSYCH2:1; /*!< bit: 2 Busy Channel 2 */
+ uint32_t BUSYCH3:1; /*!< bit: 3 Busy Channel 3 */
+ uint32_t BUSYCH4:1; /*!< bit: 4 Busy Channel 4 */
+ uint32_t BUSYCH5:1; /*!< bit: 5 Busy Channel 5 */
+ uint32_t BUSYCH6:1; /*!< bit: 6 Busy Channel 6 */
+ uint32_t BUSYCH7:1; /*!< bit: 7 Busy Channel 7 */
+ uint32_t BUSYCH8:1; /*!< bit: 8 Busy Channel 8 */
+ uint32_t BUSYCH9:1; /*!< bit: 9 Busy Channel 9 */
+ uint32_t BUSYCH10:1; /*!< bit: 10 Busy Channel 10 */
+ uint32_t BUSYCH11:1; /*!< bit: 11 Busy Channel 11 */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t BUSYCH:12; /*!< bit: 0..11 Busy Channel x */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} DMAC_BUSYCH_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -527,26 +527,26 @@ typedef union {
/* -------- DMAC_PENDCH : (DMAC Offset: 0x2C) (R/ 32) Pending Channels -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t PENDCH0:1; /*!< bit: 0 Pending Channel 0 */
- uint32_t PENDCH1:1; /*!< bit: 1 Pending Channel 1 */
- uint32_t PENDCH2:1; /*!< bit: 2 Pending Channel 2 */
- uint32_t PENDCH3:1; /*!< bit: 3 Pending Channel 3 */
- uint32_t PENDCH4:1; /*!< bit: 4 Pending Channel 4 */
- uint32_t PENDCH5:1; /*!< bit: 5 Pending Channel 5 */
- uint32_t PENDCH6:1; /*!< bit: 6 Pending Channel 6 */
- uint32_t PENDCH7:1; /*!< bit: 7 Pending Channel 7 */
- uint32_t PENDCH8:1; /*!< bit: 8 Pending Channel 8 */
- uint32_t PENDCH9:1; /*!< bit: 9 Pending Channel 9 */
- uint32_t PENDCH10:1; /*!< bit: 10 Pending Channel 10 */
- uint32_t PENDCH11:1; /*!< bit: 11 Pending Channel 11 */
- uint32_t :20; /*!< bit: 12..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t PENDCH:12; /*!< bit: 0..11 Pending Channel x */
- uint32_t :20; /*!< bit: 12..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t PENDCH0:1; /*!< bit: 0 Pending Channel 0 */
+ uint32_t PENDCH1:1; /*!< bit: 1 Pending Channel 1 */
+ uint32_t PENDCH2:1; /*!< bit: 2 Pending Channel 2 */
+ uint32_t PENDCH3:1; /*!< bit: 3 Pending Channel 3 */
+ uint32_t PENDCH4:1; /*!< bit: 4 Pending Channel 4 */
+ uint32_t PENDCH5:1; /*!< bit: 5 Pending Channel 5 */
+ uint32_t PENDCH6:1; /*!< bit: 6 Pending Channel 6 */
+ uint32_t PENDCH7:1; /*!< bit: 7 Pending Channel 7 */
+ uint32_t PENDCH8:1; /*!< bit: 8 Pending Channel 8 */
+ uint32_t PENDCH9:1; /*!< bit: 9 Pending Channel 9 */
+ uint32_t PENDCH10:1; /*!< bit: 10 Pending Channel 10 */
+ uint32_t PENDCH11:1; /*!< bit: 11 Pending Channel 11 */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t PENDCH:12; /*!< bit: 0..11 Pending Channel x */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} DMAC_PENDCH_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -585,22 +585,22 @@ typedef union {
/* -------- DMAC_ACTIVE : (DMAC Offset: 0x30) (R/ 32) Active Channel and Levels -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t LVLEX0:1; /*!< bit: 0 Level 0 Channel Trigger Request Executing */
- uint32_t LVLEX1:1; /*!< bit: 1 Level 1 Channel Trigger Request Executing */
- uint32_t LVLEX2:1; /*!< bit: 2 Level 2 Channel Trigger Request Executing */
- uint32_t LVLEX3:1; /*!< bit: 3 Level 3 Channel Trigger Request Executing */
- uint32_t :4; /*!< bit: 4.. 7 Reserved */
- uint32_t ID:5; /*!< bit: 8..12 Active Channel ID */
- uint32_t :2; /*!< bit: 13..14 Reserved */
- uint32_t ABUSY:1; /*!< bit: 15 Active Channel Busy */
- uint32_t BTCNT:16; /*!< bit: 16..31 Active Channel Block Transfer Count */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t LVLEX:4; /*!< bit: 0.. 3 Level x Channel Trigger Request Executing */
- uint32_t :28; /*!< bit: 4..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t LVLEX0:1; /*!< bit: 0 Level 0 Channel Trigger Request Executing */
+ uint32_t LVLEX1:1; /*!< bit: 1 Level 1 Channel Trigger Request Executing */
+ uint32_t LVLEX2:1; /*!< bit: 2 Level 2 Channel Trigger Request Executing */
+ uint32_t LVLEX3:1; /*!< bit: 3 Level 3 Channel Trigger Request Executing */
+ uint32_t :4; /*!< bit: 4.. 7 Reserved */
+ uint32_t ID:5; /*!< bit: 8..12 Active Channel ID */
+ uint32_t :2; /*!< bit: 13..14 Reserved */
+ uint32_t ABUSY:1; /*!< bit: 15 Active Channel Busy */
+ uint32_t BTCNT:16; /*!< bit: 16..31 Active Channel Block Transfer Count */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t LVLEX:4; /*!< bit: 0.. 3 Level x Channel Trigger Request Executing */
+ uint32_t :28; /*!< bit: 4..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} DMAC_ACTIVE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -631,10 +631,10 @@ typedef union {
/* -------- DMAC_BASEADDR : (DMAC Offset: 0x34) (R/W 32) Descriptor Memory Section Base Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t BASEADDR:32; /*!< bit: 0..31 Descriptor Memory Base Address */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t BASEADDR:32; /*!< bit: 0..31 Descriptor Memory Base Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DMAC_BASEADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -649,10 +649,10 @@ typedef union {
/* -------- DMAC_WRBADDR : (DMAC Offset: 0x38) (R/W 32) Write-Back Memory Section Base Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t WRBADDR:32; /*!< bit: 0..31 Write-Back Memory Base Address */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t WRBADDR:32; /*!< bit: 0..31 Write-Back Memory Base Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DMAC_WRBADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -667,11 +667,11 @@ typedef union {
/* -------- DMAC_CHID : (DMAC Offset: 0x3F) (R/W 8) Channel ID -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t ID:4; /*!< bit: 0.. 3 Channel ID */
- uint8_t :4; /*!< bit: 4.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t ID:4; /*!< bit: 0.. 3 Channel ID */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} DMAC_CHID_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -686,12 +686,12 @@ typedef union {
/* -------- DMAC_CHCTRLA : (DMAC Offset: 0x40) (R/W 8) Channel Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t SWRST:1; /*!< bit: 0 Channel Software Reset */
- uint8_t ENABLE:1; /*!< bit: 1 Channel Enable */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Channel Software Reset */
+ uint8_t ENABLE:1; /*!< bit: 1 Channel Enable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} DMAC_CHCTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -707,19 +707,19 @@ typedef union {
/* -------- DMAC_CHCTRLB : (DMAC Offset: 0x44) (R/W 32) Channel Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t EVACT:3; /*!< bit: 0.. 2 Event Input Action */
- uint32_t EVIE:1; /*!< bit: 3 Channel Event Input Enable */
- uint32_t EVOE:1; /*!< bit: 4 Channel Event Output Enable */
- uint32_t LVL:2; /*!< bit: 5.. 6 Channel Arbitration Level */
- uint32_t :1; /*!< bit: 7 Reserved */
- uint32_t TRIGSRC:6; /*!< bit: 8..13 Trigger Source */
- uint32_t :8; /*!< bit: 14..21 Reserved */
- uint32_t TRIGACT:2; /*!< bit: 22..23 Trigger Action */
- uint32_t CMD:2; /*!< bit: 24..25 Software Command */
- uint32_t :6; /*!< bit: 26..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t EVACT:3; /*!< bit: 0.. 2 Event Input Action */
+ uint32_t EVIE:1; /*!< bit: 3 Channel Event Input Enable */
+ uint32_t EVOE:1; /*!< bit: 4 Channel Event Output Enable */
+ uint32_t LVL:2; /*!< bit: 5.. 6 Channel Arbitration Level */
+ uint32_t :1; /*!< bit: 7 Reserved */
+ uint32_t TRIGSRC:6; /*!< bit: 8..13 Trigger Source */
+ uint32_t :8; /*!< bit: 14..21 Reserved */
+ uint32_t TRIGACT:2; /*!< bit: 22..23 Trigger Action */
+ uint32_t CMD:2; /*!< bit: 24..25 Software Command */
+ uint32_t :6; /*!< bit: 26..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DMAC_CHCTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -786,13 +786,13 @@ typedef union {
/* -------- DMAC_CHINTENCLR : (DMAC Offset: 0x4C) (R/W 8) Channel Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */
- uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */
- uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */
+ uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */
+ uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} DMAC_CHINTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -810,13 +810,13 @@ typedef union {
/* -------- DMAC_CHINTENSET : (DMAC Offset: 0x4D) (R/W 8) Channel Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */
- uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */
- uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */
+ uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */
+ uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} DMAC_CHINTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -834,13 +834,13 @@ typedef union {
/* -------- DMAC_CHINTFLAG : (DMAC Offset: 0x4E) (R/W 8) Channel Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error */
- __I uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete */
- __I uint8_t SUSP:1; /*!< bit: 2 Channel Suspend */
- __I uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ __I uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error */
+ __I uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete */
+ __I uint8_t SUSP:1; /*!< bit: 2 Channel Suspend */
+ __I uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} DMAC_CHINTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -858,13 +858,13 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register
/* -------- DMAC_CHSTATUS : (DMAC Offset: 0x4F) (R/ 8) Channel Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t PEND:1; /*!< bit: 0 Channel Pending */
- uint8_t BUSY:1; /*!< bit: 1 Channel Busy */
- uint8_t FERR:1; /*!< bit: 2 Channel Fetch Error */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t PEND:1; /*!< bit: 0 Channel Pending */
+ uint8_t BUSY:1; /*!< bit: 1 Channel Busy */
+ uint8_t FERR:1; /*!< bit: 2 Channel Fetch Error */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} DMAC_CHSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -882,18 +882,18 @@ typedef union {
/* -------- DMAC_BTCTRL : (DMAC Offset: 0x00) (R/W 16) Block Transfer Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t VALID:1; /*!< bit: 0 Descriptor Valid */
- uint16_t EVOSEL:2; /*!< bit: 1.. 2 Event Output Selection */
- uint16_t BLOCKACT:2; /*!< bit: 3.. 4 Block Action */
- uint16_t :3; /*!< bit: 5.. 7 Reserved */
- uint16_t BEATSIZE:2; /*!< bit: 8.. 9 Beat Size */
- uint16_t SRCINC:1; /*!< bit: 10 Source Address Increment Enable */
- uint16_t DSTINC:1; /*!< bit: 11 Destination Address Increment Enable */
- uint16_t STEPSEL:1; /*!< bit: 12 Step Selection */
- uint16_t STEPSIZE:3; /*!< bit: 13..15 Address Increment Step Size */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t VALID:1; /*!< bit: 0 Descriptor Valid */
+ uint16_t EVOSEL:2; /*!< bit: 1.. 2 Event Output Selection */
+ uint16_t BLOCKACT:2; /*!< bit: 3.. 4 Block Action */
+ uint16_t :3; /*!< bit: 5.. 7 Reserved */
+ uint16_t BEATSIZE:2; /*!< bit: 8.. 9 Beat Size */
+ uint16_t SRCINC:1; /*!< bit: 10 Source Address Increment Enable */
+ uint16_t DSTINC:1; /*!< bit: 11 Destination Address Increment Enable */
+ uint16_t STEPSEL:1; /*!< bit: 12 Step Selection */
+ uint16_t STEPSIZE:3; /*!< bit: 13..15 Address Increment Step Size */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} DMAC_BTCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -965,10 +965,10 @@ typedef union {
/* -------- DMAC_BTCNT : (DMAC Offset: 0x02) (R/W 16) Block Transfer Count -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t BTCNT:16; /*!< bit: 0..15 Block Transfer Count */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t BTCNT:16; /*!< bit: 0..15 Block Transfer Count */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} DMAC_BTCNT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -982,10 +982,10 @@ typedef union {
/* -------- DMAC_SRCADDR : (DMAC Offset: 0x04) (R/W 32) Block Transfer Source Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SRCADDR:32; /*!< bit: 0..31 Transfer Source Address */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SRCADDR:32; /*!< bit: 0..31 Transfer Source Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DMAC_SRCADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -999,10 +999,10 @@ typedef union {
/* -------- DMAC_DSTADDR : (DMAC Offset: 0x08) (R/W 32) Block Transfer Destination Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t DSTADDR:32; /*!< bit: 0..31 Transfer Destination Address */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t DSTADDR:32; /*!< bit: 0..31 Transfer Destination Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DMAC_DSTADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1016,10 +1016,10 @@ typedef union {
/* -------- DMAC_DESCADDR : (DMAC Offset: 0x0C) (R/W 32) Next Descriptor Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t DESCADDR:32; /*!< bit: 0..31 Next Descriptor Address */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t DESCADDR:32; /*!< bit: 0..31 Next Descriptor Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DMAC_DESCADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1033,49 +1033,49 @@ typedef union {
/** \brief DMAC APB hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO DMAC_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) Control */
- __IO DMAC_CRCCTRL_Type CRCCTRL; /**< \brief Offset: 0x02 (R/W 16) CRC Control */
- __IO DMAC_CRCDATAIN_Type CRCDATAIN; /**< \brief Offset: 0x04 (R/W 32) CRC Data Input */
- __IO DMAC_CRCCHKSUM_Type CRCCHKSUM; /**< \brief Offset: 0x08 (R/W 32) CRC Checksum */
- __IO DMAC_CRCSTATUS_Type CRCSTATUS; /**< \brief Offset: 0x0C (R/W 8) CRC Status */
- __IO DMAC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0D (R/W 8) Debug Control */
- __IO DMAC_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x0E (R/W 8) QOS Control */
- RoReg8 Reserved1[0x1];
- __IO DMAC_SWTRIGCTRL_Type SWTRIGCTRL; /**< \brief Offset: 0x10 (R/W 32) Software Trigger Control */
- __IO DMAC_PRICTRL0_Type PRICTRL0; /**< \brief Offset: 0x14 (R/W 32) Priority Control 0 */
- RoReg8 Reserved2[0x8];
- __IO DMAC_INTPEND_Type INTPEND; /**< \brief Offset: 0x20 (R/W 16) Interrupt Pending */
- RoReg8 Reserved3[0x2];
- __I DMAC_INTSTATUS_Type INTSTATUS; /**< \brief Offset: 0x24 (R/ 32) Interrupt Status */
- __I DMAC_BUSYCH_Type BUSYCH; /**< \brief Offset: 0x28 (R/ 32) Busy Channels */
- __I DMAC_PENDCH_Type PENDCH; /**< \brief Offset: 0x2C (R/ 32) Pending Channels */
- __I DMAC_ACTIVE_Type ACTIVE; /**< \brief Offset: 0x30 (R/ 32) Active Channel and Levels */
- __IO DMAC_BASEADDR_Type BASEADDR; /**< \brief Offset: 0x34 (R/W 32) Descriptor Memory Section Base Address */
- __IO DMAC_WRBADDR_Type WRBADDR; /**< \brief Offset: 0x38 (R/W 32) Write-Back Memory Section Base Address */
- RoReg8 Reserved4[0x3];
- __IO DMAC_CHID_Type CHID; /**< \brief Offset: 0x3F (R/W 8) Channel ID */
- __IO DMAC_CHCTRLA_Type CHCTRLA; /**< \brief Offset: 0x40 (R/W 8) Channel Control A */
- RoReg8 Reserved5[0x3];
- __IO DMAC_CHCTRLB_Type CHCTRLB; /**< \brief Offset: 0x44 (R/W 32) Channel Control B */
- RoReg8 Reserved6[0x4];
- __IO DMAC_CHINTENCLR_Type CHINTENCLR; /**< \brief Offset: 0x4C (R/W 8) Channel Interrupt Enable Clear */
- __IO DMAC_CHINTENSET_Type CHINTENSET; /**< \brief Offset: 0x4D (R/W 8) Channel Interrupt Enable Set */
- __IO DMAC_CHINTFLAG_Type CHINTFLAG; /**< \brief Offset: 0x4E (R/W 8) Channel Interrupt Flag Status and Clear */
- __I DMAC_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x4F (R/ 8) Channel Status */
+ __IO DMAC_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) Control */
+ __IO DMAC_CRCCTRL_Type CRCCTRL; /**< \brief Offset: 0x02 (R/W 16) CRC Control */
+ __IO DMAC_CRCDATAIN_Type CRCDATAIN; /**< \brief Offset: 0x04 (R/W 32) CRC Data Input */
+ __IO DMAC_CRCCHKSUM_Type CRCCHKSUM; /**< \brief Offset: 0x08 (R/W 32) CRC Checksum */
+ __IO DMAC_CRCSTATUS_Type CRCSTATUS; /**< \brief Offset: 0x0C (R/W 8) CRC Status */
+ __IO DMAC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0D (R/W 8) Debug Control */
+ __IO DMAC_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x0E (R/W 8) QOS Control */
+ RoReg8 Reserved1[0x1];
+ __IO DMAC_SWTRIGCTRL_Type SWTRIGCTRL; /**< \brief Offset: 0x10 (R/W 32) Software Trigger Control */
+ __IO DMAC_PRICTRL0_Type PRICTRL0; /**< \brief Offset: 0x14 (R/W 32) Priority Control 0 */
+ RoReg8 Reserved2[0x8];
+ __IO DMAC_INTPEND_Type INTPEND; /**< \brief Offset: 0x20 (R/W 16) Interrupt Pending */
+ RoReg8 Reserved3[0x2];
+ __I DMAC_INTSTATUS_Type INTSTATUS; /**< \brief Offset: 0x24 (R/ 32) Interrupt Status */
+ __I DMAC_BUSYCH_Type BUSYCH; /**< \brief Offset: 0x28 (R/ 32) Busy Channels */
+ __I DMAC_PENDCH_Type PENDCH; /**< \brief Offset: 0x2C (R/ 32) Pending Channels */
+ __I DMAC_ACTIVE_Type ACTIVE; /**< \brief Offset: 0x30 (R/ 32) Active Channel and Levels */
+ __IO DMAC_BASEADDR_Type BASEADDR; /**< \brief Offset: 0x34 (R/W 32) Descriptor Memory Section Base Address */
+ __IO DMAC_WRBADDR_Type WRBADDR; /**< \brief Offset: 0x38 (R/W 32) Write-Back Memory Section Base Address */
+ RoReg8 Reserved4[0x3];
+ __IO DMAC_CHID_Type CHID; /**< \brief Offset: 0x3F (R/W 8) Channel ID */
+ __IO DMAC_CHCTRLA_Type CHCTRLA; /**< \brief Offset: 0x40 (R/W 8) Channel Control A */
+ RoReg8 Reserved5[0x3];
+ __IO DMAC_CHCTRLB_Type CHCTRLB; /**< \brief Offset: 0x44 (R/W 32) Channel Control B */
+ RoReg8 Reserved6[0x4];
+ __IO DMAC_CHINTENCLR_Type CHINTENCLR; /**< \brief Offset: 0x4C (R/W 8) Channel Interrupt Enable Clear */
+ __IO DMAC_CHINTENSET_Type CHINTENSET; /**< \brief Offset: 0x4D (R/W 8) Channel Interrupt Enable Set */
+ __IO DMAC_CHINTFLAG_Type CHINTFLAG; /**< \brief Offset: 0x4E (R/W 8) Channel Interrupt Flag Status and Clear */
+ __I DMAC_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x4F (R/ 8) Channel Status */
} Dmac;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief DMAC Descriptor SRAM registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO DMAC_BTCTRL_Type BTCTRL; /**< \brief Offset: 0x00 (R/W 16) Block Transfer Control */
- __IO DMAC_BTCNT_Type BTCNT; /**< \brief Offset: 0x02 (R/W 16) Block Transfer Count */
- __IO DMAC_SRCADDR_Type SRCADDR; /**< \brief Offset: 0x04 (R/W 32) Block Transfer Source Address */
- __IO DMAC_DSTADDR_Type DSTADDR; /**< \brief Offset: 0x08 (R/W 32) Block Transfer Destination Address */
- __IO DMAC_DESCADDR_Type DESCADDR; /**< \brief Offset: 0x0C (R/W 32) Next Descriptor Address */
+ __IO DMAC_BTCTRL_Type BTCTRL; /**< \brief Offset: 0x00 (R/W 16) Block Transfer Control */
+ __IO DMAC_BTCNT_Type BTCNT; /**< \brief Offset: 0x02 (R/W 16) Block Transfer Count */
+ __IO DMAC_SRCADDR_Type SRCADDR; /**< \brief Offset: 0x04 (R/W 32) Block Transfer Source Address */
+ __IO DMAC_DSTADDR_Type DSTADDR; /**< \brief Offset: 0x08 (R/W 32) Block Transfer Destination Address */
+ __IO DMAC_DESCADDR_Type DESCADDR; /**< \brief Offset: 0x0C (R/W 32) Next Descriptor Address */
} DmacDescriptor
#ifdef __GNUC__
- __attribute__ ((aligned (8)))
+__attribute__ ((aligned (8)))
#endif
;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_dsu.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_dsu.h
index 8a9ab9840e5..6fc3b837148 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_dsu.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_dsu.h
@@ -56,15 +56,15 @@
/* -------- DSU_CTRL : (DSU Offset: 0x0000) ( /W 8) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t SWRST:1; /*!< bit: 0 Software Reset */
- uint8_t :1; /*!< bit: 1 Reserved */
- uint8_t CRC:1; /*!< bit: 2 32-bit Cyclic Redundancy Check */
- uint8_t MBIST:1; /*!< bit: 3 Memory Built-In Self-Test */
- uint8_t CE:1; /*!< bit: 4 Chip Erase */
- uint8_t :3; /*!< bit: 5.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t :1; /*!< bit: 1 Reserved */
+ uint8_t CRC:1; /*!< bit: 2 32-bit Cyclic Redundancy Check */
+ uint8_t MBIST:1; /*!< bit: 3 Memory Built-In Self-Test */
+ uint8_t CE:1; /*!< bit: 4 Chip Erase */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} DSU_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -84,15 +84,15 @@ typedef union {
/* -------- DSU_STATUSA : (DSU Offset: 0x0001) (R/W 8) Status A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DONE:1; /*!< bit: 0 Done */
- uint8_t CRSTEXT:1; /*!< bit: 1 CPU Reset Phase Extension */
- uint8_t BERR:1; /*!< bit: 2 Bus Error */
- uint8_t FAIL:1; /*!< bit: 3 Failure */
- uint8_t PERR:1; /*!< bit: 4 Protection Error */
- uint8_t :3; /*!< bit: 5.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DONE:1; /*!< bit: 0 Done */
+ uint8_t CRSTEXT:1; /*!< bit: 1 CPU Reset Phase Extension */
+ uint8_t BERR:1; /*!< bit: 2 Bus Error */
+ uint8_t FAIL:1; /*!< bit: 3 Failure */
+ uint8_t PERR:1; /*!< bit: 4 Protection Error */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} DSU_STATUSA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -114,20 +114,20 @@ typedef union {
/* -------- DSU_STATUSB : (DSU Offset: 0x0002) (R/ 8) Status B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t PROT:1; /*!< bit: 0 Protected */
- uint8_t DBGPRES:1; /*!< bit: 1 Debugger Present */
- uint8_t DCCD0:1; /*!< bit: 2 Debug Communication Channel 0 Dirty */
- uint8_t DCCD1:1; /*!< bit: 3 Debug Communication Channel 1 Dirty */
- uint8_t HPE:1; /*!< bit: 4 Hot-Plugging Enable */
- uint8_t :3; /*!< bit: 5.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t :2; /*!< bit: 0.. 1 Reserved */
- uint8_t DCCD:2; /*!< bit: 2.. 3 Debug Communication Channel x Dirty */
- uint8_t :4; /*!< bit: 4.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t PROT:1; /*!< bit: 0 Protected */
+ uint8_t DBGPRES:1; /*!< bit: 1 Debugger Present */
+ uint8_t DCCD0:1; /*!< bit: 2 Debug Communication Channel 0 Dirty */
+ uint8_t DCCD1:1; /*!< bit: 3 Debug Communication Channel 1 Dirty */
+ uint8_t HPE:1; /*!< bit: 4 Hot-Plugging Enable */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t :2; /*!< bit: 0.. 1 Reserved */
+ uint8_t DCCD:2; /*!< bit: 2.. 3 Debug Communication Channel x Dirty */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} DSU_STATUSB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -152,11 +152,11 @@ typedef union {
/* -------- DSU_ADDR : (DSU Offset: 0x0004) (R/W 32) Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t :2; /*!< bit: 0.. 1 Reserved */
- uint32_t ADDR:30; /*!< bit: 2..31 Address */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t :2; /*!< bit: 0.. 1 Reserved */
+ uint32_t ADDR:30; /*!< bit: 2..31 Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DSU_ADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -171,11 +171,11 @@ typedef union {
/* -------- DSU_LENGTH : (DSU Offset: 0x0008) (R/W 32) Length -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t :2; /*!< bit: 0.. 1 Reserved */
- uint32_t LENGTH:30; /*!< bit: 2..31 Length */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t :2; /*!< bit: 0.. 1 Reserved */
+ uint32_t LENGTH:30; /*!< bit: 2..31 Length */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DSU_LENGTH_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -190,10 +190,10 @@ typedef union {
/* -------- DSU_DATA : (DSU Offset: 0x000C) (R/W 32) Data -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t DATA:32; /*!< bit: 0..31 Data */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t DATA:32; /*!< bit: 0..31 Data */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DSU_DATA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -208,10 +208,10 @@ typedef union {
/* -------- DSU_DCC : (DSU Offset: 0x0010) (R/W 32) Debug Communication Channel n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t DATA:32; /*!< bit: 0..31 Data */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t DATA:32; /*!< bit: 0..31 Data */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DSU_DCC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -226,16 +226,16 @@ typedef union {
/* -------- DSU_DID : (DSU Offset: 0x0018) (R/ 32) Device Identification -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t DEVSEL:8; /*!< bit: 0.. 7 Device Select */
- uint32_t REVISION:4; /*!< bit: 8..11 Revision */
- uint32_t DIE:4; /*!< bit: 12..15 Die Identification */
- uint32_t SERIES:6; /*!< bit: 16..21 Product Series */
- uint32_t :1; /*!< bit: 22 Reserved */
- uint32_t FAMILY:5; /*!< bit: 23..27 Product Family */
- uint32_t PROCESSOR:4; /*!< bit: 28..31 Processor */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t DEVSEL:8; /*!< bit: 0.. 7 Device Select */
+ uint32_t REVISION:4; /*!< bit: 8..11 Revision */
+ uint32_t DIE:4; /*!< bit: 12..15 Die Identification */
+ uint32_t SERIES:6; /*!< bit: 16..21 Product Series */
+ uint32_t :1; /*!< bit: 22 Reserved */
+ uint32_t FAMILY:5; /*!< bit: 23..27 Product Family */
+ uint32_t PROCESSOR:4; /*!< bit: 28..31 Processor */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DSU_DID_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -264,13 +264,13 @@ typedef union {
/* -------- DSU_ENTRY : (DSU Offset: 0x1000) (R/ 32) Coresight ROM Table Entry n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t EPRES:1; /*!< bit: 0 Entry Present */
- uint32_t FMT:1; /*!< bit: 1 Format */
- uint32_t :10; /*!< bit: 2..11 Reserved */
- uint32_t ADDOFF:20; /*!< bit: 12..31 Address Offset */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t EPRES:1; /*!< bit: 0 Entry Present */
+ uint32_t FMT:1; /*!< bit: 1 Format */
+ uint32_t :10; /*!< bit: 2..11 Reserved */
+ uint32_t ADDOFF:20; /*!< bit: 12..31 Address Offset */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DSU_ENTRY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -289,10 +289,10 @@ typedef union {
/* -------- DSU_END : (DSU Offset: 0x1008) (R/ 32) Coresight ROM Table End -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t END:32; /*!< bit: 0..31 End Marker */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t END:32; /*!< bit: 0..31 End Marker */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DSU_END_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -307,11 +307,11 @@ typedef union {
/* -------- DSU_MEMTYPE : (DSU Offset: 0x1FCC) (R/ 32) Coresight ROM Table Memory Type -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SMEMP:1; /*!< bit: 0 System Memory Present */
- uint32_t :31; /*!< bit: 1..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SMEMP:1; /*!< bit: 0 System Memory Present */
+ uint32_t :31; /*!< bit: 1..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DSU_MEMTYPE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -325,12 +325,12 @@ typedef union {
/* -------- DSU_PID4 : (DSU Offset: 0x1FD0) (R/ 32) Peripheral Identification 4 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t JEPCC:4; /*!< bit: 0.. 3 JEP-106 Continuation Code */
- uint32_t FKBC:4; /*!< bit: 4.. 7 4KB Count */
- uint32_t :24; /*!< bit: 8..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t JEPCC:4; /*!< bit: 0.. 3 JEP-106 Continuation Code */
+ uint32_t FKBC:4; /*!< bit: 4.. 7 4KB Count */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DSU_PID4_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -348,11 +348,11 @@ typedef union {
/* -------- DSU_PID0 : (DSU Offset: 0x1FE0) (R/ 32) Peripheral Identification 0 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t PARTNBL:8; /*!< bit: 0.. 7 Part Number Low */
- uint32_t :24; /*!< bit: 8..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t PARTNBL:8; /*!< bit: 0.. 7 Part Number Low */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DSU_PID0_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -367,12 +367,12 @@ typedef union {
/* -------- DSU_PID1 : (DSU Offset: 0x1FE4) (R/ 32) Peripheral Identification 1 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t PARTNBH:4; /*!< bit: 0.. 3 Part Number High */
- uint32_t JEPIDCL:4; /*!< bit: 4.. 7 Low part of the JEP-106 Identity Code */
- uint32_t :24; /*!< bit: 8..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t PARTNBH:4; /*!< bit: 0.. 3 Part Number High */
+ uint32_t JEPIDCL:4; /*!< bit: 4.. 7 Low part of the JEP-106 Identity Code */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DSU_PID1_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -390,13 +390,13 @@ typedef union {
/* -------- DSU_PID2 : (DSU Offset: 0x1FE8) (R/ 32) Peripheral Identification 2 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t JEPIDCH:3; /*!< bit: 0.. 2 JEP-106 Identity Code High */
- uint32_t JEPU:1; /*!< bit: 3 JEP-106 Identity Code is used */
- uint32_t REVISION:4; /*!< bit: 4.. 7 Revision Number */
- uint32_t :24; /*!< bit: 8..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t JEPIDCH:3; /*!< bit: 0.. 2 JEP-106 Identity Code High */
+ uint32_t JEPU:1; /*!< bit: 3 JEP-106 Identity Code is used */
+ uint32_t REVISION:4; /*!< bit: 4.. 7 Revision Number */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DSU_PID2_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -416,12 +416,12 @@ typedef union {
/* -------- DSU_PID3 : (DSU Offset: 0x1FEC) (R/ 32) Peripheral Identification 3 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t CUSMOD:4; /*!< bit: 0.. 3 ARM CUSMOD */
- uint32_t REVAND:4; /*!< bit: 4.. 7 Revision Number */
- uint32_t :24; /*!< bit: 8..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t CUSMOD:4; /*!< bit: 0.. 3 ARM CUSMOD */
+ uint32_t REVAND:4; /*!< bit: 4.. 7 Revision Number */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DSU_PID3_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -439,11 +439,11 @@ typedef union {
/* -------- DSU_CID0 : (DSU Offset: 0x1FF0) (R/ 32) Component Identification 0 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t PREAMBLEB0:8; /*!< bit: 0.. 7 Preamble Byte 0 */
- uint32_t :24; /*!< bit: 8..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t PREAMBLEB0:8; /*!< bit: 0.. 7 Preamble Byte 0 */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DSU_CID0_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -458,12 +458,12 @@ typedef union {
/* -------- DSU_CID1 : (DSU Offset: 0x1FF4) (R/ 32) Component Identification 1 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t PREAMBLE:4; /*!< bit: 0.. 3 Preamble */
- uint32_t CCLASS:4; /*!< bit: 4.. 7 Component Class */
- uint32_t :24; /*!< bit: 8..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t PREAMBLE:4; /*!< bit: 0.. 3 Preamble */
+ uint32_t CCLASS:4; /*!< bit: 4.. 7 Component Class */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DSU_CID1_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -481,11 +481,11 @@ typedef union {
/* -------- DSU_CID2 : (DSU Offset: 0x1FF8) (R/ 32) Component Identification 2 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t PREAMBLEB2:8; /*!< bit: 0.. 7 Preamble Byte 2 */
- uint32_t :24; /*!< bit: 8..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t PREAMBLEB2:8; /*!< bit: 0.. 7 Preamble Byte 2 */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DSU_CID2_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -500,11 +500,11 @@ typedef union {
/* -------- DSU_CID3 : (DSU Offset: 0x1FFC) (R/ 32) Component Identification 3 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t PREAMBLEB3:8; /*!< bit: 0.. 7 Preamble Byte 3 */
- uint32_t :24; /*!< bit: 8..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t PREAMBLEB3:8; /*!< bit: 0.. 7 Preamble Byte 3 */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} DSU_CID3_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -519,30 +519,30 @@ typedef union {
/** \brief DSU hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __O DSU_CTRL_Type CTRL; /**< \brief Offset: 0x0000 ( /W 8) Control */
- __IO DSU_STATUSA_Type STATUSA; /**< \brief Offset: 0x0001 (R/W 8) Status A */
- __I DSU_STATUSB_Type STATUSB; /**< \brief Offset: 0x0002 (R/ 8) Status B */
- RoReg8 Reserved1[0x1];
- __IO DSU_ADDR_Type ADDR; /**< \brief Offset: 0x0004 (R/W 32) Address */
- __IO DSU_LENGTH_Type LENGTH; /**< \brief Offset: 0x0008 (R/W 32) Length */
- __IO DSU_DATA_Type DATA; /**< \brief Offset: 0x000C (R/W 32) Data */
- __IO DSU_DCC_Type DCC[2]; /**< \brief Offset: 0x0010 (R/W 32) Debug Communication Channel n */
- __I DSU_DID_Type DID; /**< \brief Offset: 0x0018 (R/ 32) Device Identification */
- RoReg8 Reserved2[0xFE4];
- __I DSU_ENTRY_Type ENTRY[2]; /**< \brief Offset: 0x1000 (R/ 32) Coresight ROM Table Entry n */
- __I DSU_END_Type END; /**< \brief Offset: 0x1008 (R/ 32) Coresight ROM Table End */
- RoReg8 Reserved3[0xFC0];
- __I DSU_MEMTYPE_Type MEMTYPE; /**< \brief Offset: 0x1FCC (R/ 32) Coresight ROM Table Memory Type */
- __I DSU_PID4_Type PID4; /**< \brief Offset: 0x1FD0 (R/ 32) Peripheral Identification 4 */
- RoReg8 Reserved4[0xC];
- __I DSU_PID0_Type PID0; /**< \brief Offset: 0x1FE0 (R/ 32) Peripheral Identification 0 */
- __I DSU_PID1_Type PID1; /**< \brief Offset: 0x1FE4 (R/ 32) Peripheral Identification 1 */
- __I DSU_PID2_Type PID2; /**< \brief Offset: 0x1FE8 (R/ 32) Peripheral Identification 2 */
- __I DSU_PID3_Type PID3; /**< \brief Offset: 0x1FEC (R/ 32) Peripheral Identification 3 */
- __I DSU_CID0_Type CID0; /**< \brief Offset: 0x1FF0 (R/ 32) Component Identification 0 */
- __I DSU_CID1_Type CID1; /**< \brief Offset: 0x1FF4 (R/ 32) Component Identification 1 */
- __I DSU_CID2_Type CID2; /**< \brief Offset: 0x1FF8 (R/ 32) Component Identification 2 */
- __I DSU_CID3_Type CID3; /**< \brief Offset: 0x1FFC (R/ 32) Component Identification 3 */
+ __O DSU_CTRL_Type CTRL; /**< \brief Offset: 0x0000 ( /W 8) Control */
+ __IO DSU_STATUSA_Type STATUSA; /**< \brief Offset: 0x0001 (R/W 8) Status A */
+ __I DSU_STATUSB_Type STATUSB; /**< \brief Offset: 0x0002 (R/ 8) Status B */
+ RoReg8 Reserved1[0x1];
+ __IO DSU_ADDR_Type ADDR; /**< \brief Offset: 0x0004 (R/W 32) Address */
+ __IO DSU_LENGTH_Type LENGTH; /**< \brief Offset: 0x0008 (R/W 32) Length */
+ __IO DSU_DATA_Type DATA; /**< \brief Offset: 0x000C (R/W 32) Data */
+ __IO DSU_DCC_Type DCC[2]; /**< \brief Offset: 0x0010 (R/W 32) Debug Communication Channel n */
+ __I DSU_DID_Type DID; /**< \brief Offset: 0x0018 (R/ 32) Device Identification */
+ RoReg8 Reserved2[0xFE4];
+ __I DSU_ENTRY_Type ENTRY[2]; /**< \brief Offset: 0x1000 (R/ 32) Coresight ROM Table Entry n */
+ __I DSU_END_Type END; /**< \brief Offset: 0x1008 (R/ 32) Coresight ROM Table End */
+ RoReg8 Reserved3[0xFC0];
+ __I DSU_MEMTYPE_Type MEMTYPE; /**< \brief Offset: 0x1FCC (R/ 32) Coresight ROM Table Memory Type */
+ __I DSU_PID4_Type PID4; /**< \brief Offset: 0x1FD0 (R/ 32) Peripheral Identification 4 */
+ RoReg8 Reserved4[0xC];
+ __I DSU_PID0_Type PID0; /**< \brief Offset: 0x1FE0 (R/ 32) Peripheral Identification 0 */
+ __I DSU_PID1_Type PID1; /**< \brief Offset: 0x1FE4 (R/ 32) Peripheral Identification 1 */
+ __I DSU_PID2_Type PID2; /**< \brief Offset: 0x1FE8 (R/ 32) Peripheral Identification 2 */
+ __I DSU_PID3_Type PID3; /**< \brief Offset: 0x1FEC (R/ 32) Peripheral Identification 3 */
+ __I DSU_CID0_Type CID0; /**< \brief Offset: 0x1FF0 (R/ 32) Component Identification 0 */
+ __I DSU_CID1_Type CID1; /**< \brief Offset: 0x1FF4 (R/ 32) Component Identification 1 */
+ __I DSU_CID2_Type CID2; /**< \brief Offset: 0x1FF8 (R/ 32) Component Identification 2 */
+ __I DSU_CID3_Type CID3; /**< \brief Offset: 0x1FFC (R/ 32) Component Identification 3 */
} Dsu;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_eic.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_eic.h
index bd6444328b9..1f7322d85a8 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_eic.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_eic.h
@@ -56,12 +56,12 @@
/* -------- EIC_CTRL : (EIC Offset: 0x00) (R/W 8) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t SWRST:1; /*!< bit: 0 Software Reset */
- uint8_t ENABLE:1; /*!< bit: 1 Enable */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} EIC_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -77,11 +77,11 @@ typedef union {
/* -------- EIC_STATUS : (EIC Offset: 0x01) (R/ 8) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t :7; /*!< bit: 0.. 6 Reserved */
- uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t :7; /*!< bit: 0.. 6 Reserved */
+ uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} EIC_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -95,12 +95,12 @@ typedef union {
/* -------- EIC_NMICTRL : (EIC Offset: 0x02) (R/W 8) Non-Maskable Interrupt Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t NMISENSE:3; /*!< bit: 0.. 2 Non-Maskable Interrupt Sense */
- uint8_t NMIFILTEN:1; /*!< bit: 3 Non-Maskable Interrupt Filter Enable */
- uint8_t :4; /*!< bit: 4.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t NMISENSE:3; /*!< bit: 0.. 2 Non-Maskable Interrupt Sense */
+ uint8_t NMIFILTEN:1; /*!< bit: 3 Non-Maskable Interrupt Filter Enable */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} EIC_NMICTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -129,11 +129,11 @@ typedef union {
/* -------- EIC_NMIFLAG : (EIC Offset: 0x03) (R/W 8) Non-Maskable Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t NMI:1; /*!< bit: 0 Non-Maskable Interrupt */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t NMI:1; /*!< bit: 0 Non-Maskable Interrupt */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} EIC_NMIFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -147,30 +147,30 @@ typedef union {
/* -------- EIC_EVCTRL : (EIC Offset: 0x04) (R/W 32) Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t EXTINTEO0:1; /*!< bit: 0 External Interrupt 0 Event Output Enable */
- uint32_t EXTINTEO1:1; /*!< bit: 1 External Interrupt 1 Event Output Enable */
- uint32_t EXTINTEO2:1; /*!< bit: 2 External Interrupt 2 Event Output Enable */
- uint32_t EXTINTEO3:1; /*!< bit: 3 External Interrupt 3 Event Output Enable */
- uint32_t EXTINTEO4:1; /*!< bit: 4 External Interrupt 4 Event Output Enable */
- uint32_t EXTINTEO5:1; /*!< bit: 5 External Interrupt 5 Event Output Enable */
- uint32_t EXTINTEO6:1; /*!< bit: 6 External Interrupt 6 Event Output Enable */
- uint32_t EXTINTEO7:1; /*!< bit: 7 External Interrupt 7 Event Output Enable */
- uint32_t EXTINTEO8:1; /*!< bit: 8 External Interrupt 8 Event Output Enable */
- uint32_t EXTINTEO9:1; /*!< bit: 9 External Interrupt 9 Event Output Enable */
- uint32_t EXTINTEO10:1; /*!< bit: 10 External Interrupt 10 Event Output Enable */
- uint32_t EXTINTEO11:1; /*!< bit: 11 External Interrupt 11 Event Output Enable */
- uint32_t EXTINTEO12:1; /*!< bit: 12 External Interrupt 12 Event Output Enable */
- uint32_t EXTINTEO13:1; /*!< bit: 13 External Interrupt 13 Event Output Enable */
- uint32_t EXTINTEO14:1; /*!< bit: 14 External Interrupt 14 Event Output Enable */
- uint32_t EXTINTEO15:1; /*!< bit: 15 External Interrupt 15 Event Output Enable */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t EXTINTEO:16; /*!< bit: 0..15 External Interrupt x Event Output Enable */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t EXTINTEO0:1; /*!< bit: 0 External Interrupt 0 Event Output Enable */
+ uint32_t EXTINTEO1:1; /*!< bit: 1 External Interrupt 1 Event Output Enable */
+ uint32_t EXTINTEO2:1; /*!< bit: 2 External Interrupt 2 Event Output Enable */
+ uint32_t EXTINTEO3:1; /*!< bit: 3 External Interrupt 3 Event Output Enable */
+ uint32_t EXTINTEO4:1; /*!< bit: 4 External Interrupt 4 Event Output Enable */
+ uint32_t EXTINTEO5:1; /*!< bit: 5 External Interrupt 5 Event Output Enable */
+ uint32_t EXTINTEO6:1; /*!< bit: 6 External Interrupt 6 Event Output Enable */
+ uint32_t EXTINTEO7:1; /*!< bit: 7 External Interrupt 7 Event Output Enable */
+ uint32_t EXTINTEO8:1; /*!< bit: 8 External Interrupt 8 Event Output Enable */
+ uint32_t EXTINTEO9:1; /*!< bit: 9 External Interrupt 9 Event Output Enable */
+ uint32_t EXTINTEO10:1; /*!< bit: 10 External Interrupt 10 Event Output Enable */
+ uint32_t EXTINTEO11:1; /*!< bit: 11 External Interrupt 11 Event Output Enable */
+ uint32_t EXTINTEO12:1; /*!< bit: 12 External Interrupt 12 Event Output Enable */
+ uint32_t EXTINTEO13:1; /*!< bit: 13 External Interrupt 13 Event Output Enable */
+ uint32_t EXTINTEO14:1; /*!< bit: 14 External Interrupt 14 Event Output Enable */
+ uint32_t EXTINTEO15:1; /*!< bit: 15 External Interrupt 15 Event Output Enable */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t EXTINTEO:16; /*!< bit: 0..15 External Interrupt x Event Output Enable */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} EIC_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -217,30 +217,30 @@ typedef union {
/* -------- EIC_INTENCLR : (EIC Offset: 0x08) (R/W 32) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 Enable */
- uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 Enable */
- uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 Enable */
- uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 Enable */
- uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 Enable */
- uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 Enable */
- uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 Enable */
- uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 Enable */
- uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 Enable */
- uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 Enable */
- uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 Enable */
- uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 Enable */
- uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 Enable */
- uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 Enable */
- uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 Enable */
- uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 Enable */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x Enable */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 Enable */
+ uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 Enable */
+ uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 Enable */
+ uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 Enable */
+ uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 Enable */
+ uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 Enable */
+ uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 Enable */
+ uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 Enable */
+ uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 Enable */
+ uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 Enable */
+ uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 Enable */
+ uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 Enable */
+ uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 Enable */
+ uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 Enable */
+ uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 Enable */
+ uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 Enable */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x Enable */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} EIC_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -287,30 +287,30 @@ typedef union {
/* -------- EIC_INTENSET : (EIC Offset: 0x0C) (R/W 32) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 Enable */
- uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 Enable */
- uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 Enable */
- uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 Enable */
- uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 Enable */
- uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 Enable */
- uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 Enable */
- uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 Enable */
- uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 Enable */
- uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 Enable */
- uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 Enable */
- uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 Enable */
- uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 Enable */
- uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 Enable */
- uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 Enable */
- uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 Enable */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x Enable */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 Enable */
+ uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 Enable */
+ uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 Enable */
+ uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 Enable */
+ uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 Enable */
+ uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 Enable */
+ uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 Enable */
+ uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 Enable */
+ uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 Enable */
+ uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 Enable */
+ uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 Enable */
+ uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 Enable */
+ uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 Enable */
+ uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 Enable */
+ uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 Enable */
+ uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 Enable */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x Enable */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} EIC_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -357,30 +357,30 @@ typedef union {
/* -------- EIC_INTFLAG : (EIC Offset: 0x10) (R/W 32) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 */
- __I uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 */
- __I uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 */
- __I uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 */
- __I uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 */
- __I uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 */
- __I uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 */
- __I uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 */
- __I uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 */
- __I uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 */
- __I uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 */
- __I uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 */
- __I uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 */
- __I uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 */
- __I uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 */
- __I uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 */
- __I uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- __I uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x */
- __I uint32_t :16; /*!< bit: 16..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ __I uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 */
+ __I uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 */
+ __I uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 */
+ __I uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 */
+ __I uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 */
+ __I uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 */
+ __I uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 */
+ __I uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 */
+ __I uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 */
+ __I uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 */
+ __I uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 */
+ __I uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 */
+ __I uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 */
+ __I uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 */
+ __I uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 */
+ __I uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 */
+ __I uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ __I uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x */
+ __I uint32_t :16; /*!< bit: 16..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} EIC_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -427,30 +427,30 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register
/* -------- EIC_WAKEUP : (EIC Offset: 0x14) (R/W 32) Wake-Up Enable -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t WAKEUPEN0:1; /*!< bit: 0 External Interrupt 0 Wake-up Enable */
- uint32_t WAKEUPEN1:1; /*!< bit: 1 External Interrupt 1 Wake-up Enable */
- uint32_t WAKEUPEN2:1; /*!< bit: 2 External Interrupt 2 Wake-up Enable */
- uint32_t WAKEUPEN3:1; /*!< bit: 3 External Interrupt 3 Wake-up Enable */
- uint32_t WAKEUPEN4:1; /*!< bit: 4 External Interrupt 4 Wake-up Enable */
- uint32_t WAKEUPEN5:1; /*!< bit: 5 External Interrupt 5 Wake-up Enable */
- uint32_t WAKEUPEN6:1; /*!< bit: 6 External Interrupt 6 Wake-up Enable */
- uint32_t WAKEUPEN7:1; /*!< bit: 7 External Interrupt 7 Wake-up Enable */
- uint32_t WAKEUPEN8:1; /*!< bit: 8 External Interrupt 8 Wake-up Enable */
- uint32_t WAKEUPEN9:1; /*!< bit: 9 External Interrupt 9 Wake-up Enable */
- uint32_t WAKEUPEN10:1; /*!< bit: 10 External Interrupt 10 Wake-up Enable */
- uint32_t WAKEUPEN11:1; /*!< bit: 11 External Interrupt 11 Wake-up Enable */
- uint32_t WAKEUPEN12:1; /*!< bit: 12 External Interrupt 12 Wake-up Enable */
- uint32_t WAKEUPEN13:1; /*!< bit: 13 External Interrupt 13 Wake-up Enable */
- uint32_t WAKEUPEN14:1; /*!< bit: 14 External Interrupt 14 Wake-up Enable */
- uint32_t WAKEUPEN15:1; /*!< bit: 15 External Interrupt 15 Wake-up Enable */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t WAKEUPEN:16; /*!< bit: 0..15 External Interrupt x Wake-up Enable */
- uint32_t :16; /*!< bit: 16..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t WAKEUPEN0:1; /*!< bit: 0 External Interrupt 0 Wake-up Enable */
+ uint32_t WAKEUPEN1:1; /*!< bit: 1 External Interrupt 1 Wake-up Enable */
+ uint32_t WAKEUPEN2:1; /*!< bit: 2 External Interrupt 2 Wake-up Enable */
+ uint32_t WAKEUPEN3:1; /*!< bit: 3 External Interrupt 3 Wake-up Enable */
+ uint32_t WAKEUPEN4:1; /*!< bit: 4 External Interrupt 4 Wake-up Enable */
+ uint32_t WAKEUPEN5:1; /*!< bit: 5 External Interrupt 5 Wake-up Enable */
+ uint32_t WAKEUPEN6:1; /*!< bit: 6 External Interrupt 6 Wake-up Enable */
+ uint32_t WAKEUPEN7:1; /*!< bit: 7 External Interrupt 7 Wake-up Enable */
+ uint32_t WAKEUPEN8:1; /*!< bit: 8 External Interrupt 8 Wake-up Enable */
+ uint32_t WAKEUPEN9:1; /*!< bit: 9 External Interrupt 9 Wake-up Enable */
+ uint32_t WAKEUPEN10:1; /*!< bit: 10 External Interrupt 10 Wake-up Enable */
+ uint32_t WAKEUPEN11:1; /*!< bit: 11 External Interrupt 11 Wake-up Enable */
+ uint32_t WAKEUPEN12:1; /*!< bit: 12 External Interrupt 12 Wake-up Enable */
+ uint32_t WAKEUPEN13:1; /*!< bit: 13 External Interrupt 13 Wake-up Enable */
+ uint32_t WAKEUPEN14:1; /*!< bit: 14 External Interrupt 14 Wake-up Enable */
+ uint32_t WAKEUPEN15:1; /*!< bit: 15 External Interrupt 15 Wake-up Enable */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t WAKEUPEN:16; /*!< bit: 0..15 External Interrupt x Wake-up Enable */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} EIC_WAKEUP_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -497,25 +497,25 @@ typedef union {
/* -------- EIC_CONFIG : (EIC Offset: 0x18) (R/W 32) Configuration n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SENSE0:3; /*!< bit: 0.. 2 Input Sense 0 Configuration */
- uint32_t FILTEN0:1; /*!< bit: 3 Filter 0 Enable */
- uint32_t SENSE1:3; /*!< bit: 4.. 6 Input Sense 1 Configuration */
- uint32_t FILTEN1:1; /*!< bit: 7 Filter 1 Enable */
- uint32_t SENSE2:3; /*!< bit: 8..10 Input Sense 2 Configuration */
- uint32_t FILTEN2:1; /*!< bit: 11 Filter 2 Enable */
- uint32_t SENSE3:3; /*!< bit: 12..14 Input Sense 3 Configuration */
- uint32_t FILTEN3:1; /*!< bit: 15 Filter 3 Enable */
- uint32_t SENSE4:3; /*!< bit: 16..18 Input Sense 4 Configuration */
- uint32_t FILTEN4:1; /*!< bit: 19 Filter 4 Enable */
- uint32_t SENSE5:3; /*!< bit: 20..22 Input Sense 5 Configuration */
- uint32_t FILTEN5:1; /*!< bit: 23 Filter 5 Enable */
- uint32_t SENSE6:3; /*!< bit: 24..26 Input Sense 6 Configuration */
- uint32_t FILTEN6:1; /*!< bit: 27 Filter 6 Enable */
- uint32_t SENSE7:3; /*!< bit: 28..30 Input Sense 7 Configuration */
- uint32_t FILTEN7:1; /*!< bit: 31 Filter 7 Enable */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SENSE0:3; /*!< bit: 0.. 2 Input Sense 0 Configuration */
+ uint32_t FILTEN0:1; /*!< bit: 3 Filter 0 Enable */
+ uint32_t SENSE1:3; /*!< bit: 4.. 6 Input Sense 1 Configuration */
+ uint32_t FILTEN1:1; /*!< bit: 7 Filter 1 Enable */
+ uint32_t SENSE2:3; /*!< bit: 8..10 Input Sense 2 Configuration */
+ uint32_t FILTEN2:1; /*!< bit: 11 Filter 2 Enable */
+ uint32_t SENSE3:3; /*!< bit: 12..14 Input Sense 3 Configuration */
+ uint32_t FILTEN3:1; /*!< bit: 15 Filter 3 Enable */
+ uint32_t SENSE4:3; /*!< bit: 16..18 Input Sense 4 Configuration */
+ uint32_t FILTEN4:1; /*!< bit: 19 Filter 4 Enable */
+ uint32_t SENSE5:3; /*!< bit: 20..22 Input Sense 5 Configuration */
+ uint32_t FILTEN5:1; /*!< bit: 23 Filter 5 Enable */
+ uint32_t SENSE6:3; /*!< bit: 24..26 Input Sense 6 Configuration */
+ uint32_t FILTEN6:1; /*!< bit: 27 Filter 6 Enable */
+ uint32_t SENSE7:3; /*!< bit: 28..30 Input Sense 7 Configuration */
+ uint32_t FILTEN7:1; /*!< bit: 31 Filter 7 Enable */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} EIC_CONFIG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -663,16 +663,16 @@ typedef union {
/** \brief EIC hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO EIC_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 8) Control */
- __I EIC_STATUS_Type STATUS; /**< \brief Offset: 0x01 (R/ 8) Status */
- __IO EIC_NMICTRL_Type NMICTRL; /**< \brief Offset: 0x02 (R/W 8) Non-Maskable Interrupt Control */
- __IO EIC_NMIFLAG_Type NMIFLAG; /**< \brief Offset: 0x03 (R/W 8) Non-Maskable Interrupt Flag Status and Clear */
- __IO EIC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 32) Event Control */
- __IO EIC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 32) Interrupt Enable Clear */
- __IO EIC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0C (R/W 32) Interrupt Enable Set */
- __IO EIC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x10 (R/W 32) Interrupt Flag Status and Clear */
- __IO EIC_WAKEUP_Type WAKEUP; /**< \brief Offset: 0x14 (R/W 32) Wake-Up Enable */
- __IO EIC_CONFIG_Type CONFIG[2]; /**< \brief Offset: 0x18 (R/W 32) Configuration n */
+ __IO EIC_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 8) Control */
+ __I EIC_STATUS_Type STATUS; /**< \brief Offset: 0x01 (R/ 8) Status */
+ __IO EIC_NMICTRL_Type NMICTRL; /**< \brief Offset: 0x02 (R/W 8) Non-Maskable Interrupt Control */
+ __IO EIC_NMIFLAG_Type NMIFLAG; /**< \brief Offset: 0x03 (R/W 8) Non-Maskable Interrupt Flag Status and Clear */
+ __IO EIC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 32) Event Control */
+ __IO EIC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 32) Interrupt Enable Clear */
+ __IO EIC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0C (R/W 32) Interrupt Enable Set */
+ __IO EIC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x10 (R/W 32) Interrupt Flag Status and Clear */
+ __IO EIC_WAKEUP_Type WAKEUP; /**< \brief Offset: 0x14 (R/W 32) Wake-Up Enable */
+ __IO EIC_CONFIG_Type CONFIG[2]; /**< \brief Offset: 0x18 (R/W 32) Configuration n */
} Eic;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_evsys.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_evsys.h
index b665bc29b43..32d12f23168 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_evsys.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_evsys.h
@@ -56,13 +56,13 @@
/* -------- EVSYS_CTRL : (EVSYS Offset: 0x00) ( /W 8) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t SWRST:1; /*!< bit: 0 Software Reset */
- uint8_t :3; /*!< bit: 1.. 3 Reserved */
- uint8_t GCLKREQ:1; /*!< bit: 4 Generic Clock Requests */
- uint8_t :3; /*!< bit: 5.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t :3; /*!< bit: 1.. 3 Reserved */
+ uint8_t GCLKREQ:1; /*!< bit: 4 Generic Clock Requests */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} EVSYS_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -78,18 +78,18 @@ typedef union {
/* -------- EVSYS_CHANNEL : (EVSYS Offset: 0x04) (R/W 32) Channel -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t CHANNEL:4; /*!< bit: 0.. 3 Channel Selection */
- uint32_t :4; /*!< bit: 4.. 7 Reserved */
- uint32_t SWEVT:1; /*!< bit: 8 Software Event */
- uint32_t :7; /*!< bit: 9..15 Reserved */
- uint32_t EVGEN:7; /*!< bit: 16..22 Event Generator Selection */
- uint32_t :1; /*!< bit: 23 Reserved */
- uint32_t PATH:2; /*!< bit: 24..25 Path Selection */
- uint32_t EDGSEL:2; /*!< bit: 26..27 Edge Detection Selection */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t CHANNEL:4; /*!< bit: 0.. 3 Channel Selection */
+ uint32_t :4; /*!< bit: 4.. 7 Reserved */
+ uint32_t SWEVT:1; /*!< bit: 8 Software Event */
+ uint32_t :7; /*!< bit: 9..15 Reserved */
+ uint32_t EVGEN:7; /*!< bit: 16..22 Event Generator Selection */
+ uint32_t :1; /*!< bit: 23 Reserved */
+ uint32_t PATH:2; /*!< bit: 24..25 Path Selection */
+ uint32_t EDGSEL:2; /*!< bit: 26..27 Edge Detection Selection */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} EVSYS_CHANNEL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -129,13 +129,13 @@ typedef union {
/* -------- EVSYS_USER : (EVSYS Offset: 0x08) (R/W 16) User Multiplexer -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t USER:5; /*!< bit: 0.. 4 User Multiplexer Selection */
- uint16_t :3; /*!< bit: 5.. 7 Reserved */
- uint16_t CHANNEL:5; /*!< bit: 8..12 Channel Event Selection */
- uint16_t :3; /*!< bit: 13..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t USER:5; /*!< bit: 0.. 4 User Multiplexer Selection */
+ uint16_t :3; /*!< bit: 5.. 7 Reserved */
+ uint16_t CHANNEL:5; /*!< bit: 8..12 Channel Event Selection */
+ uint16_t :3; /*!< bit: 13..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} EVSYS_USER_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -155,43 +155,43 @@ typedef union {
/* -------- EVSYS_CHSTATUS : (EVSYS Offset: 0x0C) (R/ 32) Channel Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t USRRDY0:1; /*!< bit: 0 Channel 0 User Ready */
- uint32_t USRRDY1:1; /*!< bit: 1 Channel 1 User Ready */
- uint32_t USRRDY2:1; /*!< bit: 2 Channel 2 User Ready */
- uint32_t USRRDY3:1; /*!< bit: 3 Channel 3 User Ready */
- uint32_t USRRDY4:1; /*!< bit: 4 Channel 4 User Ready */
- uint32_t USRRDY5:1; /*!< bit: 5 Channel 5 User Ready */
- uint32_t USRRDY6:1; /*!< bit: 6 Channel 6 User Ready */
- uint32_t USRRDY7:1; /*!< bit: 7 Channel 7 User Ready */
- uint32_t CHBUSY0:1; /*!< bit: 8 Channel 0 Busy */
- uint32_t CHBUSY1:1; /*!< bit: 9 Channel 1 Busy */
- uint32_t CHBUSY2:1; /*!< bit: 10 Channel 2 Busy */
- uint32_t CHBUSY3:1; /*!< bit: 11 Channel 3 Busy */
- uint32_t CHBUSY4:1; /*!< bit: 12 Channel 4 Busy */
- uint32_t CHBUSY5:1; /*!< bit: 13 Channel 5 Busy */
- uint32_t CHBUSY6:1; /*!< bit: 14 Channel 6 Busy */
- uint32_t CHBUSY7:1; /*!< bit: 15 Channel 7 Busy */
- uint32_t USRRDY8:1; /*!< bit: 16 Channel 8 User Ready */
- uint32_t USRRDY9:1; /*!< bit: 17 Channel 9 User Ready */
- uint32_t USRRDY10:1; /*!< bit: 18 Channel 10 User Ready */
- uint32_t USRRDY11:1; /*!< bit: 19 Channel 11 User Ready */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t CHBUSY8:1; /*!< bit: 24 Channel 8 Busy */
- uint32_t CHBUSY9:1; /*!< bit: 25 Channel 9 Busy */
- uint32_t CHBUSY10:1; /*!< bit: 26 Channel 10 Busy */
- uint32_t CHBUSY11:1; /*!< bit: 27 Channel 11 Busy */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t USRRDY:8; /*!< bit: 0.. 7 Channel x User Ready */
- uint32_t CHBUSY:8; /*!< bit: 8..15 Channel x Busy */
- uint32_t USRRDYp8:4; /*!< bit: 16..19 Channel x+8 User Ready */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t CHBUSYp8:4; /*!< bit: 24..27 Channel x+8 Busy */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t USRRDY0:1; /*!< bit: 0 Channel 0 User Ready */
+ uint32_t USRRDY1:1; /*!< bit: 1 Channel 1 User Ready */
+ uint32_t USRRDY2:1; /*!< bit: 2 Channel 2 User Ready */
+ uint32_t USRRDY3:1; /*!< bit: 3 Channel 3 User Ready */
+ uint32_t USRRDY4:1; /*!< bit: 4 Channel 4 User Ready */
+ uint32_t USRRDY5:1; /*!< bit: 5 Channel 5 User Ready */
+ uint32_t USRRDY6:1; /*!< bit: 6 Channel 6 User Ready */
+ uint32_t USRRDY7:1; /*!< bit: 7 Channel 7 User Ready */
+ uint32_t CHBUSY0:1; /*!< bit: 8 Channel 0 Busy */
+ uint32_t CHBUSY1:1; /*!< bit: 9 Channel 1 Busy */
+ uint32_t CHBUSY2:1; /*!< bit: 10 Channel 2 Busy */
+ uint32_t CHBUSY3:1; /*!< bit: 11 Channel 3 Busy */
+ uint32_t CHBUSY4:1; /*!< bit: 12 Channel 4 Busy */
+ uint32_t CHBUSY5:1; /*!< bit: 13 Channel 5 Busy */
+ uint32_t CHBUSY6:1; /*!< bit: 14 Channel 6 Busy */
+ uint32_t CHBUSY7:1; /*!< bit: 15 Channel 7 Busy */
+ uint32_t USRRDY8:1; /*!< bit: 16 Channel 8 User Ready */
+ uint32_t USRRDY9:1; /*!< bit: 17 Channel 9 User Ready */
+ uint32_t USRRDY10:1; /*!< bit: 18 Channel 10 User Ready */
+ uint32_t USRRDY11:1; /*!< bit: 19 Channel 11 User Ready */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t CHBUSY8:1; /*!< bit: 24 Channel 8 Busy */
+ uint32_t CHBUSY9:1; /*!< bit: 25 Channel 9 Busy */
+ uint32_t CHBUSY10:1; /*!< bit: 26 Channel 10 Busy */
+ uint32_t CHBUSY11:1; /*!< bit: 27 Channel 11 Busy */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t USRRDY:8; /*!< bit: 0.. 7 Channel x User Ready */
+ uint32_t CHBUSY:8; /*!< bit: 8..15 Channel x Busy */
+ uint32_t USRRDYp8:4; /*!< bit: 16..19 Channel x+8 User Ready */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t CHBUSYp8:4; /*!< bit: 24..27 Channel x+8 Busy */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} EVSYS_CHSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -263,43 +263,43 @@ typedef union {
/* -------- EVSYS_INTENCLR : (EVSYS Offset: 0x10) (R/W 32) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */
- uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */
- uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */
- uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */
- uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */
- uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */
- uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */
- uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */
- uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection Interrupt Enable */
- uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection Interrupt Enable */
- uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection Interrupt Enable */
- uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection Interrupt Enable */
- uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection Interrupt Enable */
- uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection Interrupt Enable */
- uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection Interrupt Enable */
- uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection Interrupt Enable */
- uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun Interrupt Enable */
- uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun Interrupt Enable */
- uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun Interrupt Enable */
- uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun Interrupt Enable */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */
- uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */
- uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */
- uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun Interrupt Enable */
- uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection Interrupt Enable */
- uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun Interrupt Enable */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection Interrupt Enable */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */
+ uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */
+ uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */
+ uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */
+ uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */
+ uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */
+ uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */
+ uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */
+ uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection Interrupt Enable */
+ uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection Interrupt Enable */
+ uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection Interrupt Enable */
+ uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection Interrupt Enable */
+ uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection Interrupt Enable */
+ uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection Interrupt Enable */
+ uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection Interrupt Enable */
+ uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection Interrupt Enable */
+ uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun Interrupt Enable */
+ uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun Interrupt Enable */
+ uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun Interrupt Enable */
+ uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun Interrupt Enable */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */
+ uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */
+ uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */
+ uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun Interrupt Enable */
+ uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection Interrupt Enable */
+ uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun Interrupt Enable */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection Interrupt Enable */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} EVSYS_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -371,43 +371,43 @@ typedef union {
/* -------- EVSYS_INTENSET : (EVSYS Offset: 0x14) (R/W 32) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */
- uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */
- uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */
- uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */
- uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */
- uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */
- uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */
- uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */
- uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection Interrupt Enable */
- uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection Interrupt Enable */
- uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection Interrupt Enable */
- uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection Interrupt Enable */
- uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection Interrupt Enable */
- uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection Interrupt Enable */
- uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection Interrupt Enable */
- uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection Interrupt Enable */
- uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun Interrupt Enable */
- uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun Interrupt Enable */
- uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun Interrupt Enable */
- uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun Interrupt Enable */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */
- uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */
- uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */
- uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun Interrupt Enable */
- uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection Interrupt Enable */
- uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun Interrupt Enable */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection Interrupt Enable */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */
+ uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */
+ uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */
+ uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */
+ uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */
+ uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */
+ uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */
+ uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */
+ uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection Interrupt Enable */
+ uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection Interrupt Enable */
+ uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection Interrupt Enable */
+ uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection Interrupt Enable */
+ uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection Interrupt Enable */
+ uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection Interrupt Enable */
+ uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection Interrupt Enable */
+ uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection Interrupt Enable */
+ uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun Interrupt Enable */
+ uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun Interrupt Enable */
+ uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun Interrupt Enable */
+ uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun Interrupt Enable */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */
+ uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */
+ uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */
+ uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun Interrupt Enable */
+ uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection Interrupt Enable */
+ uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun Interrupt Enable */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection Interrupt Enable */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} EVSYS_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -479,43 +479,43 @@ typedef union {
/* -------- EVSYS_INTFLAG : (EVSYS Offset: 0x18) (R/W 32) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun */
- __I uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun */
- __I uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun */
- __I uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun */
- __I uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun */
- __I uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun */
- __I uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun */
- __I uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun */
- __I uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection */
- __I uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection */
- __I uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection */
- __I uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection */
- __I uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection */
- __I uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection */
- __I uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection */
- __I uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection */
- __I uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun */
- __I uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun */
- __I uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun */
- __I uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun */
- __I uint32_t :4; /*!< bit: 20..23 Reserved */
- __I uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection */
- __I uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection */
- __I uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection */
- __I uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection */
- __I uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- __I uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun */
- __I uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection */
- __I uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun */
- __I uint32_t :4; /*!< bit: 20..23 Reserved */
- __I uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection */
- __I uint32_t :4; /*!< bit: 28..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ __I uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun */
+ __I uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun */
+ __I uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun */
+ __I uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun */
+ __I uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun */
+ __I uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun */
+ __I uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun */
+ __I uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun */
+ __I uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection */
+ __I uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection */
+ __I uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection */
+ __I uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection */
+ __I uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection */
+ __I uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection */
+ __I uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection */
+ __I uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection */
+ __I uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun */
+ __I uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun */
+ __I uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun */
+ __I uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun */
+ __I uint32_t :4; /*!< bit: 20..23 Reserved */
+ __I uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection */
+ __I uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection */
+ __I uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection */
+ __I uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection */
+ __I uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ __I uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun */
+ __I uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection */
+ __I uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun */
+ __I uint32_t :4; /*!< bit: 20..23 Reserved */
+ __I uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection */
+ __I uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} EVSYS_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -587,15 +587,15 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register
/** \brief EVSYS hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __O EVSYS_CTRL_Type CTRL; /**< \brief Offset: 0x00 ( /W 8) Control */
- RoReg8 Reserved1[0x3];
- __IO EVSYS_CHANNEL_Type CHANNEL; /**< \brief Offset: 0x04 (R/W 32) Channel */
- __IO EVSYS_USER_Type USER; /**< \brief Offset: 0x08 (R/W 16) User Multiplexer */
- RoReg8 Reserved2[0x2];
- __I EVSYS_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x0C (R/ 32) Channel Status */
- __IO EVSYS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x10 (R/W 32) Interrupt Enable Clear */
- __IO EVSYS_INTENSET_Type INTENSET; /**< \brief Offset: 0x14 (R/W 32) Interrupt Enable Set */
- __IO EVSYS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 32) Interrupt Flag Status and Clear */
+ __O EVSYS_CTRL_Type CTRL; /**< \brief Offset: 0x00 ( /W 8) Control */
+ RoReg8 Reserved1[0x3];
+ __IO EVSYS_CHANNEL_Type CHANNEL; /**< \brief Offset: 0x04 (R/W 32) Channel */
+ __IO EVSYS_USER_Type USER; /**< \brief Offset: 0x08 (R/W 16) User Multiplexer */
+ RoReg8 Reserved2[0x2];
+ __I EVSYS_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x0C (R/ 32) Channel Status */
+ __IO EVSYS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x10 (R/W 32) Interrupt Enable Clear */
+ __IO EVSYS_INTENSET_Type INTENSET; /**< \brief Offset: 0x14 (R/W 32) Interrupt Enable Set */
+ __IO EVSYS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 32) Interrupt Flag Status and Clear */
} Evsys;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_gclk.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_gclk.h
index f18ef047ac0..86e97913db9 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_gclk.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_gclk.h
@@ -56,11 +56,11 @@
/* -------- GCLK_CTRL : (GCLK Offset: 0x0) (R/W 8) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t SWRST:1; /*!< bit: 0 Software Reset */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} GCLK_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -74,11 +74,11 @@ typedef union {
/* -------- GCLK_STATUS : (GCLK Offset: 0x1) (R/ 8) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t :7; /*!< bit: 0.. 6 Reserved */
- uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy Status */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t :7; /*!< bit: 0.. 6 Reserved */
+ uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy Status */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} GCLK_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -92,15 +92,15 @@ typedef union {
/* -------- GCLK_CLKCTRL : (GCLK Offset: 0x2) (R/W 16) Generic Clock Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t ID:6; /*!< bit: 0.. 5 Generic Clock Selection ID */
- uint16_t :2; /*!< bit: 6.. 7 Reserved */
- uint16_t GEN:4; /*!< bit: 8..11 Generic Clock Generator */
- uint16_t :2; /*!< bit: 12..13 Reserved */
- uint16_t CLKEN:1; /*!< bit: 14 Clock Enable */
- uint16_t WRTLOCK:1; /*!< bit: 15 Write Lock */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t ID:6; /*!< bit: 0.. 5 Generic Clock Selection ID */
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ uint16_t GEN:4; /*!< bit: 8..11 Generic Clock Generator */
+ uint16_t :2; /*!< bit: 12..13 Reserved */
+ uint16_t CLKEN:1; /*!< bit: 14 Clock Enable */
+ uint16_t WRTLOCK:1; /*!< bit: 15 Write Lock */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} GCLK_CLKCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -212,20 +212,20 @@ typedef union {
/* -------- GCLK_GENCTRL : (GCLK Offset: 0x4) (R/W 32) Generic Clock Generator Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t ID:4; /*!< bit: 0.. 3 Generic Clock Generator Selection */
- uint32_t :4; /*!< bit: 4.. 7 Reserved */
- uint32_t SRC:5; /*!< bit: 8..12 Source Select */
- uint32_t :3; /*!< bit: 13..15 Reserved */
- uint32_t GENEN:1; /*!< bit: 16 Generic Clock Generator Enable */
- uint32_t IDC:1; /*!< bit: 17 Improve Duty Cycle */
- uint32_t OOV:1; /*!< bit: 18 Output Off Value */
- uint32_t OE:1; /*!< bit: 19 Output Enable */
- uint32_t DIVSEL:1; /*!< bit: 20 Divide Selection */
- uint32_t RUNSTDBY:1; /*!< bit: 21 Run in Standby */
- uint32_t :10; /*!< bit: 22..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t ID:4; /*!< bit: 0.. 3 Generic Clock Generator Selection */
+ uint32_t :4; /*!< bit: 4.. 7 Reserved */
+ uint32_t SRC:5; /*!< bit: 8..12 Source Select */
+ uint32_t :3; /*!< bit: 13..15 Reserved */
+ uint32_t GENEN:1; /*!< bit: 16 Generic Clock Generator Enable */
+ uint32_t IDC:1; /*!< bit: 17 Improve Duty Cycle */
+ uint32_t OOV:1; /*!< bit: 18 Output Off Value */
+ uint32_t OE:1; /*!< bit: 19 Output Enable */
+ uint32_t DIVSEL:1; /*!< bit: 20 Divide Selection */
+ uint32_t RUNSTDBY:1; /*!< bit: 21 Run in Standby */
+ uint32_t :10; /*!< bit: 22..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} GCLK_GENCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -273,13 +273,13 @@ typedef union {
/* -------- GCLK_GENDIV : (GCLK Offset: 0x8) (R/W 32) Generic Clock Generator Division -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t ID:4; /*!< bit: 0.. 3 Generic Clock Generator Selection */
- uint32_t :4; /*!< bit: 4.. 7 Reserved */
- uint32_t DIV:16; /*!< bit: 8..23 Division Factor */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t ID:4; /*!< bit: 0.. 3 Generic Clock Generator Selection */
+ uint32_t :4; /*!< bit: 4.. 7 Reserved */
+ uint32_t DIV:16; /*!< bit: 8..23 Division Factor */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} GCLK_GENDIV_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -297,11 +297,11 @@ typedef union {
/** \brief GCLK hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO GCLK_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */
- __I GCLK_STATUS_Type STATUS; /**< \brief Offset: 0x1 (R/ 8) Status */
- __IO GCLK_CLKCTRL_Type CLKCTRL; /**< \brief Offset: 0x2 (R/W 16) Generic Clock Control */
- __IO GCLK_GENCTRL_Type GENCTRL; /**< \brief Offset: 0x4 (R/W 32) Generic Clock Generator Control */
- __IO GCLK_GENDIV_Type GENDIV; /**< \brief Offset: 0x8 (R/W 32) Generic Clock Generator Division */
+ __IO GCLK_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */
+ __I GCLK_STATUS_Type STATUS; /**< \brief Offset: 0x1 (R/ 8) Status */
+ __IO GCLK_CLKCTRL_Type CLKCTRL; /**< \brief Offset: 0x2 (R/W 16) Generic Clock Control */
+ __IO GCLK_GENCTRL_Type GENCTRL; /**< \brief Offset: 0x4 (R/W 32) Generic Clock Generator Control */
+ __IO GCLK_GENDIV_Type GENDIV; /**< \brief Offset: 0x8 (R/W 32) Generic Clock Generator Division */
} Gclk;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_hmatrixb.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_hmatrixb.h
index 0102cabd6bf..465c605b7cf 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_hmatrixb.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_hmatrixb.h
@@ -56,7 +56,7 @@
/* -------- HMATRIXB_PRAS : (HMATRIXB Offset: 0x080) (R/W 32) PRS Priority A for Slave -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} HMATRIXB_PRAS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -68,7 +68,7 @@ typedef union {
/* -------- HMATRIXB_PRBS : (HMATRIXB Offset: 0x084) (R/W 32) PRS Priority B for Slave -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} HMATRIXB_PRBS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -80,10 +80,10 @@ typedef union {
/* -------- HMATRIXB_SFR : (HMATRIXB Offset: 0x110) (R/W 32) Special Function -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SFR:32; /*!< bit: 0..31 Special Function Register */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SFR:32; /*!< bit: 0..31 Special Function Register */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} HMATRIXB_SFR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -98,18 +98,18 @@ typedef union {
/** \brief HmatrixbPrs hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO HMATRIXB_PRAS_Type PRAS; /**< \brief Offset: 0x000 (R/W 32) Priority A for Slave */
- __IO HMATRIXB_PRBS_Type PRBS; /**< \brief Offset: 0x004 (R/W 32) Priority B for Slave */
+ __IO HMATRIXB_PRAS_Type PRAS; /**< \brief Offset: 0x000 (R/W 32) Priority A for Slave */
+ __IO HMATRIXB_PRBS_Type PRBS; /**< \brief Offset: 0x004 (R/W 32) Priority B for Slave */
} HmatrixbPrs;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief HMATRIXB hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- RoReg8 Reserved1[0x80];
- HmatrixbPrs Prs[16]; /**< \brief Offset: 0x080 HmatrixbPrs groups */
- RoReg8 Reserved2[0x10];
- __IO HMATRIXB_SFR_Type SFR[16]; /**< \brief Offset: 0x110 (R/W 32) Special Function */
+ RoReg8 Reserved1[0x80];
+ HmatrixbPrs Prs[16]; /**< \brief Offset: 0x080 HmatrixbPrs groups */
+ RoReg8 Reserved2[0x10];
+ __IO HMATRIXB_SFR_Type SFR[16]; /**< \brief Offset: 0x110 (R/W 32) Special Function */
} Hmatrixb;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_mtb.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_mtb.h
index 4da747bfe39..b180c85346e 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_mtb.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_mtb.h
@@ -56,12 +56,12 @@
/* -------- MTB_POSITION : (MTB Offset: 0x000) (R/W 32) MTB Position -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t :2; /*!< bit: 0.. 1 Reserved */
- uint32_t WRAP:1; /*!< bit: 2 Pointer Value Wraps */
- uint32_t POINTER:29; /*!< bit: 3..31 Trace Packet Location Pointer */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t :2; /*!< bit: 0.. 1 Reserved */
+ uint32_t WRAP:1; /*!< bit: 2 Pointer Value Wraps */
+ uint32_t POINTER:29; /*!< bit: 3..31 Trace Packet Location Pointer */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_POSITION_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -77,17 +77,17 @@ typedef union {
/* -------- MTB_MASTER : (MTB Offset: 0x004) (R/W 32) MTB Master -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t MASK:5; /*!< bit: 0.. 4 Maximum Value of the Trace Buffer in SRAM */
- uint32_t TSTARTEN:1; /*!< bit: 5 Trace Start Input Enable */
- uint32_t TSTOPEN:1; /*!< bit: 6 Trace Stop Input Enable */
- uint32_t SFRWPRIV:1; /*!< bit: 7 Special Function Register Write Privilege */
- uint32_t RAMPRIV:1; /*!< bit: 8 SRAM Privilege */
- uint32_t HALTREQ:1; /*!< bit: 9 Halt Request */
- uint32_t :21; /*!< bit: 10..30 Reserved */
- uint32_t EN:1; /*!< bit: 31 Main Trace Enable */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t MASK:5; /*!< bit: 0.. 4 Maximum Value of the Trace Buffer in SRAM */
+ uint32_t TSTARTEN:1; /*!< bit: 5 Trace Start Input Enable */
+ uint32_t TSTOPEN:1; /*!< bit: 6 Trace Stop Input Enable */
+ uint32_t SFRWPRIV:1; /*!< bit: 7 Special Function Register Write Privilege */
+ uint32_t RAMPRIV:1; /*!< bit: 8 SRAM Privilege */
+ uint32_t HALTREQ:1; /*!< bit: 9 Halt Request */
+ uint32_t :21; /*!< bit: 10..30 Reserved */
+ uint32_t EN:1; /*!< bit: 31 Main Trace Enable */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_MASTER_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -114,13 +114,13 @@ typedef union {
/* -------- MTB_FLOW : (MTB Offset: 0x008) (R/W 32) MTB Flow -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t AUTOSTOP:1; /*!< bit: 0 Auto Stop Tracing */
- uint32_t AUTOHALT:1; /*!< bit: 1 Auto Halt Request */
- uint32_t :1; /*!< bit: 2 Reserved */
- uint32_t WATERMARK:29; /*!< bit: 3..31 Watermark value */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t AUTOSTOP:1; /*!< bit: 0 Auto Stop Tracing */
+ uint32_t AUTOHALT:1; /*!< bit: 1 Auto Halt Request */
+ uint32_t :1; /*!< bit: 2 Reserved */
+ uint32_t WATERMARK:29; /*!< bit: 3..31 Watermark value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_FLOW_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -139,7 +139,7 @@ typedef union {
/* -------- MTB_BASE : (MTB Offset: 0x00C) (R/ 32) MTB Base -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_BASE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -149,7 +149,7 @@ typedef union {
/* -------- MTB_ITCTRL : (MTB Offset: 0xF00) (R/W 32) MTB Integration Mode Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_ITCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -159,7 +159,7 @@ typedef union {
/* -------- MTB_CLAIMSET : (MTB Offset: 0xFA0) (R/W 32) MTB Claim Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_CLAIMSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -169,7 +169,7 @@ typedef union {
/* -------- MTB_CLAIMCLR : (MTB Offset: 0xFA4) (R/W 32) MTB Claim Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_CLAIMCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -179,7 +179,7 @@ typedef union {
/* -------- MTB_LOCKACCESS : (MTB Offset: 0xFB0) (R/W 32) MTB Lock Access -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_LOCKACCESS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -189,7 +189,7 @@ typedef union {
/* -------- MTB_LOCKSTATUS : (MTB Offset: 0xFB4) (R/ 32) MTB Lock Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_LOCKSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -199,7 +199,7 @@ typedef union {
/* -------- MTB_AUTHSTATUS : (MTB Offset: 0xFB8) (R/ 32) MTB Authentication Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_AUTHSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -209,7 +209,7 @@ typedef union {
/* -------- MTB_DEVARCH : (MTB Offset: 0xFBC) (R/ 32) MTB Device Architecture -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_DEVARCH_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -219,7 +219,7 @@ typedef union {
/* -------- MTB_DEVID : (MTB Offset: 0xFC8) (R/ 32) MTB Device Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_DEVID_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -229,7 +229,7 @@ typedef union {
/* -------- MTB_DEVTYPE : (MTB Offset: 0xFCC) (R/ 32) MTB Device Type -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_DEVTYPE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -239,7 +239,7 @@ typedef union {
/* -------- MTB_PID4 : (MTB Offset: 0xFD0) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_PID4_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -249,7 +249,7 @@ typedef union {
/* -------- MTB_PID5 : (MTB Offset: 0xFD4) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_PID5_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -259,7 +259,7 @@ typedef union {
/* -------- MTB_PID6 : (MTB Offset: 0xFD8) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_PID6_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -269,7 +269,7 @@ typedef union {
/* -------- MTB_PID7 : (MTB Offset: 0xFDC) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_PID7_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -279,7 +279,7 @@ typedef union {
/* -------- MTB_PID0 : (MTB Offset: 0xFE0) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_PID0_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -289,7 +289,7 @@ typedef union {
/* -------- MTB_PID1 : (MTB Offset: 0xFE4) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_PID1_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -299,7 +299,7 @@ typedef union {
/* -------- MTB_PID2 : (MTB Offset: 0xFE8) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_PID2_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -309,7 +309,7 @@ typedef union {
/* -------- MTB_PID3 : (MTB Offset: 0xFEC) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_PID3_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -319,7 +319,7 @@ typedef union {
/* -------- MTB_CID0 : (MTB Offset: 0xFF0) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_CID0_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -329,7 +329,7 @@ typedef union {
/* -------- MTB_CID1 : (MTB Offset: 0xFF4) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_CID1_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -339,7 +339,7 @@ typedef union {
/* -------- MTB_CID2 : (MTB Offset: 0xFF8) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_CID2_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -349,7 +349,7 @@ typedef union {
/* -------- MTB_CID3 : (MTB Offset: 0xFFC) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint32_t reg; /*!< Type used for register access */
+ uint32_t reg; /*!< Type used for register access */
} MTB_CID3_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -359,35 +359,35 @@ typedef union {
/** \brief MTB hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO MTB_POSITION_Type POSITION; /**< \brief Offset: 0x000 (R/W 32) MTB Position */
- __IO MTB_MASTER_Type MASTER; /**< \brief Offset: 0x004 (R/W 32) MTB Master */
- __IO MTB_FLOW_Type FLOW; /**< \brief Offset: 0x008 (R/W 32) MTB Flow */
- __I MTB_BASE_Type BASE; /**< \brief Offset: 0x00C (R/ 32) MTB Base */
- RoReg8 Reserved1[0xEF0];
- __IO MTB_ITCTRL_Type ITCTRL; /**< \brief Offset: 0xF00 (R/W 32) MTB Integration Mode Control */
- RoReg8 Reserved2[0x9C];
- __IO MTB_CLAIMSET_Type CLAIMSET; /**< \brief Offset: 0xFA0 (R/W 32) MTB Claim Set */
- __IO MTB_CLAIMCLR_Type CLAIMCLR; /**< \brief Offset: 0xFA4 (R/W 32) MTB Claim Clear */
- RoReg8 Reserved3[0x8];
- __IO MTB_LOCKACCESS_Type LOCKACCESS; /**< \brief Offset: 0xFB0 (R/W 32) MTB Lock Access */
- __I MTB_LOCKSTATUS_Type LOCKSTATUS; /**< \brief Offset: 0xFB4 (R/ 32) MTB Lock Status */
- __I MTB_AUTHSTATUS_Type AUTHSTATUS; /**< \brief Offset: 0xFB8 (R/ 32) MTB Authentication Status */
- __I MTB_DEVARCH_Type DEVARCH; /**< \brief Offset: 0xFBC (R/ 32) MTB Device Architecture */
- RoReg8 Reserved4[0x8];
- __I MTB_DEVID_Type DEVID; /**< \brief Offset: 0xFC8 (R/ 32) MTB Device Configuration */
- __I MTB_DEVTYPE_Type DEVTYPE; /**< \brief Offset: 0xFCC (R/ 32) MTB Device Type */
- __I MTB_PID4_Type PID4; /**< \brief Offset: 0xFD0 (R/ 32) CoreSight */
- __I MTB_PID5_Type PID5; /**< \brief Offset: 0xFD4 (R/ 32) CoreSight */
- __I MTB_PID6_Type PID6; /**< \brief Offset: 0xFD8 (R/ 32) CoreSight */
- __I MTB_PID7_Type PID7; /**< \brief Offset: 0xFDC (R/ 32) CoreSight */
- __I MTB_PID0_Type PID0; /**< \brief Offset: 0xFE0 (R/ 32) CoreSight */
- __I MTB_PID1_Type PID1; /**< \brief Offset: 0xFE4 (R/ 32) CoreSight */
- __I MTB_PID2_Type PID2; /**< \brief Offset: 0xFE8 (R/ 32) CoreSight */
- __I MTB_PID3_Type PID3; /**< \brief Offset: 0xFEC (R/ 32) CoreSight */
- __I MTB_CID0_Type CID0; /**< \brief Offset: 0xFF0 (R/ 32) CoreSight */
- __I MTB_CID1_Type CID1; /**< \brief Offset: 0xFF4 (R/ 32) CoreSight */
- __I MTB_CID2_Type CID2; /**< \brief Offset: 0xFF8 (R/ 32) CoreSight */
- __I MTB_CID3_Type CID3; /**< \brief Offset: 0xFFC (R/ 32) CoreSight */
+ __IO MTB_POSITION_Type POSITION; /**< \brief Offset: 0x000 (R/W 32) MTB Position */
+ __IO MTB_MASTER_Type MASTER; /**< \brief Offset: 0x004 (R/W 32) MTB Master */
+ __IO MTB_FLOW_Type FLOW; /**< \brief Offset: 0x008 (R/W 32) MTB Flow */
+ __I MTB_BASE_Type BASE; /**< \brief Offset: 0x00C (R/ 32) MTB Base */
+ RoReg8 Reserved1[0xEF0];
+ __IO MTB_ITCTRL_Type ITCTRL; /**< \brief Offset: 0xF00 (R/W 32) MTB Integration Mode Control */
+ RoReg8 Reserved2[0x9C];
+ __IO MTB_CLAIMSET_Type CLAIMSET; /**< \brief Offset: 0xFA0 (R/W 32) MTB Claim Set */
+ __IO MTB_CLAIMCLR_Type CLAIMCLR; /**< \brief Offset: 0xFA4 (R/W 32) MTB Claim Clear */
+ RoReg8 Reserved3[0x8];
+ __IO MTB_LOCKACCESS_Type LOCKACCESS; /**< \brief Offset: 0xFB0 (R/W 32) MTB Lock Access */
+ __I MTB_LOCKSTATUS_Type LOCKSTATUS; /**< \brief Offset: 0xFB4 (R/ 32) MTB Lock Status */
+ __I MTB_AUTHSTATUS_Type AUTHSTATUS; /**< \brief Offset: 0xFB8 (R/ 32) MTB Authentication Status */
+ __I MTB_DEVARCH_Type DEVARCH; /**< \brief Offset: 0xFBC (R/ 32) MTB Device Architecture */
+ RoReg8 Reserved4[0x8];
+ __I MTB_DEVID_Type DEVID; /**< \brief Offset: 0xFC8 (R/ 32) MTB Device Configuration */
+ __I MTB_DEVTYPE_Type DEVTYPE; /**< \brief Offset: 0xFCC (R/ 32) MTB Device Type */
+ __I MTB_PID4_Type PID4; /**< \brief Offset: 0xFD0 (R/ 32) CoreSight */
+ __I MTB_PID5_Type PID5; /**< \brief Offset: 0xFD4 (R/ 32) CoreSight */
+ __I MTB_PID6_Type PID6; /**< \brief Offset: 0xFD8 (R/ 32) CoreSight */
+ __I MTB_PID7_Type PID7; /**< \brief Offset: 0xFDC (R/ 32) CoreSight */
+ __I MTB_PID0_Type PID0; /**< \brief Offset: 0xFE0 (R/ 32) CoreSight */
+ __I MTB_PID1_Type PID1; /**< \brief Offset: 0xFE4 (R/ 32) CoreSight */
+ __I MTB_PID2_Type PID2; /**< \brief Offset: 0xFE8 (R/ 32) CoreSight */
+ __I MTB_PID3_Type PID3; /**< \brief Offset: 0xFEC (R/ 32) CoreSight */
+ __I MTB_CID0_Type CID0; /**< \brief Offset: 0xFF0 (R/ 32) CoreSight */
+ __I MTB_CID1_Type CID1; /**< \brief Offset: 0xFF4 (R/ 32) CoreSight */
+ __I MTB_CID2_Type CID2; /**< \brief Offset: 0xFF8 (R/ 32) CoreSight */
+ __I MTB_CID3_Type CID3; /**< \brief Offset: 0xFFC (R/ 32) CoreSight */
} Mtb;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_nvmctrl.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_nvmctrl.h
index 3398fd9eef1..e014da1069d 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_nvmctrl.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_nvmctrl.h
@@ -56,12 +56,12 @@
/* -------- NVMCTRL_CTRLA : (NVMCTRL Offset: 0x00) (R/W 16) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t CMD:7; /*!< bit: 0.. 6 Command */
- uint16_t :1; /*!< bit: 7 Reserved */
- uint16_t CMDEX:8; /*!< bit: 8..15 Command Execution */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t CMD:7; /*!< bit: 0.. 6 Command */
+ uint16_t :1; /*!< bit: 7 Reserved */
+ uint16_t CMDEX:8; /*!< bit: 8..15 Command Execution */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} NVMCTRL_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -107,18 +107,18 @@ typedef union {
/* -------- NVMCTRL_CTRLB : (NVMCTRL Offset: 0x04) (R/W 32) Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t :1; /*!< bit: 0 Reserved */
- uint32_t RWS:4; /*!< bit: 1.. 4 NVM Read Wait States */
- uint32_t :2; /*!< bit: 5.. 6 Reserved */
- uint32_t MANW:1; /*!< bit: 7 Manual Write */
- uint32_t SLEEPPRM:2; /*!< bit: 8.. 9 Power Reduction Mode during Sleep */
- uint32_t :6; /*!< bit: 10..15 Reserved */
- uint32_t READMODE:2; /*!< bit: 16..17 NVMCTRL Read Mode */
- uint32_t CACHEDIS:1; /*!< bit: 18 Cache Disable */
- uint32_t :13; /*!< bit: 19..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t RWS:4; /*!< bit: 1.. 4 NVM Read Wait States */
+ uint32_t :2; /*!< bit: 5.. 6 Reserved */
+ uint32_t MANW:1; /*!< bit: 7 Manual Write */
+ uint32_t SLEEPPRM:2; /*!< bit: 8.. 9 Power Reduction Mode during Sleep */
+ uint32_t :6; /*!< bit: 10..15 Reserved */
+ uint32_t READMODE:2; /*!< bit: 16..17 NVMCTRL Read Mode */
+ uint32_t CACHEDIS:1; /*!< bit: 18 Cache Disable */
+ uint32_t :13; /*!< bit: 19..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} NVMCTRL_CTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -161,12 +161,12 @@ typedef union {
/* -------- NVMCTRL_PARAM : (NVMCTRL Offset: 0x08) (R/W 32) NVM Parameter -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t NVMP:16; /*!< bit: 0..15 NVM Pages */
- uint32_t PSZ:3; /*!< bit: 16..18 Page Size */
- uint32_t :13; /*!< bit: 19..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t NVMP:16; /*!< bit: 0..15 NVM Pages */
+ uint32_t PSZ:3; /*!< bit: 16..18 Page Size */
+ uint32_t :13; /*!< bit: 19..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} NVMCTRL_PARAM_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -200,12 +200,12 @@ typedef union {
/* -------- NVMCTRL_INTENCLR : (NVMCTRL Offset: 0x0C) (R/W 8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Enable */
- uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Enable */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Enable */
+ uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Enable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} NVMCTRL_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -221,12 +221,12 @@ typedef union {
/* -------- NVMCTRL_INTENSET : (NVMCTRL Offset: 0x10) (R/W 8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Enable */
- uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Enable */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Enable */
+ uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Enable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} NVMCTRL_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -242,12 +242,12 @@ typedef union {
/* -------- NVMCTRL_INTFLAG : (NVMCTRL Offset: 0x14) (R/W 8) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint8_t READY:1; /*!< bit: 0 NVM Ready */
- __I uint8_t ERROR:1; /*!< bit: 1 Error */
- __I uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ __I uint8_t READY:1; /*!< bit: 0 NVM Ready */
+ __I uint8_t ERROR:1; /*!< bit: 1 Error */
+ __I uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} NVMCTRL_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -263,17 +263,17 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register
/* -------- NVMCTRL_STATUS : (NVMCTRL Offset: 0x18) (R/W 16) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t PRM:1; /*!< bit: 0 Power Reduction Mode */
- uint16_t LOAD:1; /*!< bit: 1 NVM Page Buffer Active Loading */
- uint16_t PROGE:1; /*!< bit: 2 Programming Error Status */
- uint16_t LOCKE:1; /*!< bit: 3 Lock Error Status */
- uint16_t NVME:1; /*!< bit: 4 NVM Error */
- uint16_t :3; /*!< bit: 5.. 7 Reserved */
- uint16_t SB:1; /*!< bit: 8 Security Bit Status */
- uint16_t :7; /*!< bit: 9..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t PRM:1; /*!< bit: 0 Power Reduction Mode */
+ uint16_t LOAD:1; /*!< bit: 1 NVM Page Buffer Active Loading */
+ uint16_t PROGE:1; /*!< bit: 2 Programming Error Status */
+ uint16_t LOCKE:1; /*!< bit: 3 Lock Error Status */
+ uint16_t NVME:1; /*!< bit: 4 NVM Error */
+ uint16_t :3; /*!< bit: 5.. 7 Reserved */
+ uint16_t SB:1; /*!< bit: 8 Security Bit Status */
+ uint16_t :7; /*!< bit: 9..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} NVMCTRL_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -297,11 +297,11 @@ typedef union {
/* -------- NVMCTRL_ADDR : (NVMCTRL Offset: 0x1C) (R/W 32) Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t ADDR:22; /*!< bit: 0..21 NVM Address */
- uint32_t :10; /*!< bit: 22..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t ADDR:22; /*!< bit: 0..21 NVM Address */
+ uint32_t :10; /*!< bit: 22..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} NVMCTRL_ADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -316,10 +316,10 @@ typedef union {
/* -------- NVMCTRL_LOCK : (NVMCTRL Offset: 0x20) (R/W 16) Lock Section -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t LOCK:16; /*!< bit: 0..15 Region Lock Bits */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t LOCK:16; /*!< bit: 0..15 Region Lock Bits */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} NVMCTRL_LOCK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -333,20 +333,20 @@ typedef union {
/** \brief NVMCTRL APB hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO NVMCTRL_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
- RoReg8 Reserved1[0x2];
- __IO NVMCTRL_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) Control B */
- __IO NVMCTRL_PARAM_Type PARAM; /**< \brief Offset: 0x08 (R/W 32) NVM Parameter */
- __IO NVMCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
- RoReg8 Reserved2[0x3];
- __IO NVMCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 8) Interrupt Enable Set */
- RoReg8 Reserved3[0x3];
- __IO NVMCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 8) Interrupt Flag Status and Clear */
- RoReg8 Reserved4[0x3];
- __IO NVMCTRL_STATUS_Type STATUS; /**< \brief Offset: 0x18 (R/W 16) Status */
- RoReg8 Reserved5[0x2];
- __IO NVMCTRL_ADDR_Type ADDR; /**< \brief Offset: 0x1C (R/W 32) Address */
- __IO NVMCTRL_LOCK_Type LOCK; /**< \brief Offset: 0x20 (R/W 16) Lock Section */
+ __IO NVMCTRL_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
+ RoReg8 Reserved1[0x2];
+ __IO NVMCTRL_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) Control B */
+ __IO NVMCTRL_PARAM_Type PARAM; /**< \brief Offset: 0x08 (R/W 32) NVM Parameter */
+ __IO NVMCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
+ RoReg8 Reserved2[0x3];
+ __IO NVMCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 8) Interrupt Enable Set */
+ RoReg8 Reserved3[0x3];
+ __IO NVMCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 8) Interrupt Flag Status and Clear */
+ RoReg8 Reserved4[0x3];
+ __IO NVMCTRL_STATUS_Type STATUS; /**< \brief Offset: 0x18 (R/W 16) Status */
+ RoReg8 Reserved5[0x2];
+ __IO NVMCTRL_ADDR_Type ADDR; /**< \brief Offset: 0x1C (R/W 32) Address */
+ __IO NVMCTRL_LOCK_Type LOCK; /**< \brief Offset: 0x20 (R/W 16) Lock Section */
} Nvmctrl;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SECTION_NVMCTRL_CAL
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_pac.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_pac.h
index a8f52746853..9a4bc89e6d6 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_pac.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_pac.h
@@ -56,11 +56,11 @@
/* -------- PAC_WPCLR : (PAC Offset: 0x0) (R/W 32) Write Protection Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t :1; /*!< bit: 0 Reserved */
- uint32_t WP:31; /*!< bit: 1..31 Write Protection Clear */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t WP:31; /*!< bit: 1..31 Write Protection Clear */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} PAC_WPCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -75,11 +75,11 @@ typedef union {
/* -------- PAC_WPSET : (PAC Offset: 0x4) (R/W 32) Write Protection Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t :1; /*!< bit: 0 Reserved */
- uint32_t WP:31; /*!< bit: 1..31 Write Protection Set */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t WP:31; /*!< bit: 1..31 Write Protection Set */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} PAC_WPSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -94,8 +94,8 @@ typedef union {
/** \brief PAC hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO PAC_WPCLR_Type WPCLR; /**< \brief Offset: 0x0 (R/W 32) Write Protection Clear */
- __IO PAC_WPSET_Type WPSET; /**< \brief Offset: 0x4 (R/W 32) Write Protection Set */
+ __IO PAC_WPCLR_Type WPCLR; /**< \brief Offset: 0x0 (R/W 32) Write Protection Clear */
+ __IO PAC_WPSET_Type WPSET; /**< \brief Offset: 0x4 (R/W 32) Write Protection Set */
} Pac;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_pm.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_pm.h
index 4c837c5ba27..4832dc43a4d 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_pm.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_pm.h
@@ -56,7 +56,7 @@
/* -------- PM_CTRL : (PM Offset: 0x00) (R/W 8) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- uint8_t reg; /*!< Type used for register access */
+ uint8_t reg; /*!< Type used for register access */
} PM_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -68,11 +68,11 @@ typedef union {
/* -------- PM_SLEEP : (PM Offset: 0x01) (R/W 8) Sleep Mode -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t IDLE:2; /*!< bit: 0.. 1 Idle Mode Configuration */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t IDLE:2; /*!< bit: 0.. 1 Idle Mode Configuration */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} PM_SLEEP_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -93,11 +93,11 @@ typedef union {
/* -------- PM_CPUSEL : (PM Offset: 0x08) (R/W 8) CPU Clock Select -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t CPUDIV:3; /*!< bit: 0.. 2 CPU Prescaler Selection */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t CPUDIV:3; /*!< bit: 0.. 2 CPU Prescaler Selection */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} PM_CPUSEL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -128,11 +128,11 @@ typedef union {
/* -------- PM_APBASEL : (PM Offset: 0x09) (R/W 8) APBA Clock Select -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t APBADIV:3; /*!< bit: 0.. 2 APBA Prescaler Selection */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t APBADIV:3; /*!< bit: 0.. 2 APBA Prescaler Selection */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} PM_APBASEL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -163,11 +163,11 @@ typedef union {
/* -------- PM_APBBSEL : (PM Offset: 0x0A) (R/W 8) APBB Clock Select -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t APBBDIV:3; /*!< bit: 0.. 2 APBB Prescaler Selection */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t APBBDIV:3; /*!< bit: 0.. 2 APBB Prescaler Selection */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} PM_APBBSEL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -198,11 +198,11 @@ typedef union {
/* -------- PM_APBCSEL : (PM Offset: 0x0B) (R/W 8) APBC Clock Select -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t APBCDIV:3; /*!< bit: 0.. 2 APBC Prescaler Selection */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t APBCDIV:3; /*!< bit: 0.. 2 APBC Prescaler Selection */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} PM_APBCSEL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -233,17 +233,17 @@ typedef union {
/* -------- PM_AHBMASK : (PM Offset: 0x14) (R/W 32) AHB Mask -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t HPB0_:1; /*!< bit: 0 HPB0 AHB Clock Mask */
- uint32_t HPB1_:1; /*!< bit: 1 HPB1 AHB Clock Mask */
- uint32_t HPB2_:1; /*!< bit: 2 HPB2 AHB Clock Mask */
- uint32_t DSU_:1; /*!< bit: 3 DSU AHB Clock Mask */
- uint32_t NVMCTRL_:1; /*!< bit: 4 NVMCTRL AHB Clock Mask */
- uint32_t DMAC_:1; /*!< bit: 5 DMAC AHB Clock Mask */
- uint32_t USB_:1; /*!< bit: 6 USB AHB Clock Mask */
- uint32_t :25; /*!< bit: 7..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t HPB0_:1; /*!< bit: 0 HPB0 AHB Clock Mask */
+ uint32_t HPB1_:1; /*!< bit: 1 HPB1 AHB Clock Mask */
+ uint32_t HPB2_:1; /*!< bit: 2 HPB2 AHB Clock Mask */
+ uint32_t DSU_:1; /*!< bit: 3 DSU AHB Clock Mask */
+ uint32_t NVMCTRL_:1; /*!< bit: 4 NVMCTRL AHB Clock Mask */
+ uint32_t DMAC_:1; /*!< bit: 5 DMAC AHB Clock Mask */
+ uint32_t USB_:1; /*!< bit: 6 USB AHB Clock Mask */
+ uint32_t :25; /*!< bit: 7..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} PM_AHBMASK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -269,17 +269,17 @@ typedef union {
/* -------- PM_APBAMASK : (PM Offset: 0x18) (R/W 32) APBA Mask -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t PAC0_:1; /*!< bit: 0 PAC0 APB Clock Enable */
- uint32_t PM_:1; /*!< bit: 1 PM APB Clock Enable */
- uint32_t SYSCTRL_:1; /*!< bit: 2 SYSCTRL APB Clock Enable */
- uint32_t GCLK_:1; /*!< bit: 3 GCLK APB Clock Enable */
- uint32_t WDT_:1; /*!< bit: 4 WDT APB Clock Enable */
- uint32_t RTC_:1; /*!< bit: 5 RTC APB Clock Enable */
- uint32_t EIC_:1; /*!< bit: 6 EIC APB Clock Enable */
- uint32_t :25; /*!< bit: 7..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t PAC0_:1; /*!< bit: 0 PAC0 APB Clock Enable */
+ uint32_t PM_:1; /*!< bit: 1 PM APB Clock Enable */
+ uint32_t SYSCTRL_:1; /*!< bit: 2 SYSCTRL APB Clock Enable */
+ uint32_t GCLK_:1; /*!< bit: 3 GCLK APB Clock Enable */
+ uint32_t WDT_:1; /*!< bit: 4 WDT APB Clock Enable */
+ uint32_t RTC_:1; /*!< bit: 5 RTC APB Clock Enable */
+ uint32_t EIC_:1; /*!< bit: 6 EIC APB Clock Enable */
+ uint32_t :25; /*!< bit: 7..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} PM_APBAMASK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -305,17 +305,17 @@ typedef union {
/* -------- PM_APBBMASK : (PM Offset: 0x1C) (R/W 32) APBB Mask -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t PAC1_:1; /*!< bit: 0 PAC1 APB Clock Enable */
- uint32_t DSU_:1; /*!< bit: 1 DSU APB Clock Enable */
- uint32_t NVMCTRL_:1; /*!< bit: 2 NVMCTRL APB Clock Enable */
- uint32_t PORT_:1; /*!< bit: 3 PORT APB Clock Enable */
- uint32_t DMAC_:1; /*!< bit: 4 DMAC APB Clock Enable */
- uint32_t USB_:1; /*!< bit: 5 USB APB Clock Enable */
- uint32_t HMATRIX_:1; /*!< bit: 6 HMATRIX APB Clock Enable */
- uint32_t :25; /*!< bit: 7..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t PAC1_:1; /*!< bit: 0 PAC1 APB Clock Enable */
+ uint32_t DSU_:1; /*!< bit: 1 DSU APB Clock Enable */
+ uint32_t NVMCTRL_:1; /*!< bit: 2 NVMCTRL APB Clock Enable */
+ uint32_t PORT_:1; /*!< bit: 3 PORT APB Clock Enable */
+ uint32_t DMAC_:1; /*!< bit: 4 DMAC APB Clock Enable */
+ uint32_t USB_:1; /*!< bit: 5 USB APB Clock Enable */
+ uint32_t HMATRIX_:1; /*!< bit: 6 HMATRIX APB Clock Enable */
+ uint32_t :25; /*!< bit: 7..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} PM_APBBMASK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -341,31 +341,31 @@ typedef union {
/* -------- PM_APBCMASK : (PM Offset: 0x20) (R/W 32) APBC Mask -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t PAC2_:1; /*!< bit: 0 PAC2 APB Clock Enable */
- uint32_t EVSYS_:1; /*!< bit: 1 EVSYS APB Clock Enable */
- uint32_t SERCOM0_:1; /*!< bit: 2 SERCOM0 APB Clock Enable */
- uint32_t SERCOM1_:1; /*!< bit: 3 SERCOM1 APB Clock Enable */
- uint32_t SERCOM2_:1; /*!< bit: 4 SERCOM2 APB Clock Enable */
- uint32_t SERCOM3_:1; /*!< bit: 5 SERCOM3 APB Clock Enable */
- uint32_t SERCOM4_:1; /*!< bit: 6 SERCOM4 APB Clock Enable */
- uint32_t SERCOM5_:1; /*!< bit: 7 SERCOM5 APB Clock Enable */
- uint32_t TCC0_:1; /*!< bit: 8 TCC0 APB Clock Enable */
- uint32_t TCC1_:1; /*!< bit: 9 TCC1 APB Clock Enable */
- uint32_t TCC2_:1; /*!< bit: 10 TCC2 APB Clock Enable */
- uint32_t TC3_:1; /*!< bit: 11 TC3 APB Clock Enable */
- uint32_t TC4_:1; /*!< bit: 12 TC4 APB Clock Enable */
- uint32_t TC5_:1; /*!< bit: 13 TC5 APB Clock Enable */
- uint32_t :2; /*!< bit: 14..15 Reserved */
- uint32_t ADC_:1; /*!< bit: 16 ADC APB Clock Enable */
- uint32_t AC_:1; /*!< bit: 17 AC APB Clock Enable */
- uint32_t :1; /*!< bit: 18 Reserved */
- uint32_t PTC_:1; /*!< bit: 19 PTC APB Clock Enable */
- uint32_t :1; /*!< bit: 20 Reserved */
- uint32_t RFCTRL_:1; /*!< bit: 21 RFCTRL APB Clock Enable */
- uint32_t :10; /*!< bit: 22..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t PAC2_:1; /*!< bit: 0 PAC2 APB Clock Enable */
+ uint32_t EVSYS_:1; /*!< bit: 1 EVSYS APB Clock Enable */
+ uint32_t SERCOM0_:1; /*!< bit: 2 SERCOM0 APB Clock Enable */
+ uint32_t SERCOM1_:1; /*!< bit: 3 SERCOM1 APB Clock Enable */
+ uint32_t SERCOM2_:1; /*!< bit: 4 SERCOM2 APB Clock Enable */
+ uint32_t SERCOM3_:1; /*!< bit: 5 SERCOM3 APB Clock Enable */
+ uint32_t SERCOM4_:1; /*!< bit: 6 SERCOM4 APB Clock Enable */
+ uint32_t SERCOM5_:1; /*!< bit: 7 SERCOM5 APB Clock Enable */
+ uint32_t TCC0_:1; /*!< bit: 8 TCC0 APB Clock Enable */
+ uint32_t TCC1_:1; /*!< bit: 9 TCC1 APB Clock Enable */
+ uint32_t TCC2_:1; /*!< bit: 10 TCC2 APB Clock Enable */
+ uint32_t TC3_:1; /*!< bit: 11 TC3 APB Clock Enable */
+ uint32_t TC4_:1; /*!< bit: 12 TC4 APB Clock Enable */
+ uint32_t TC5_:1; /*!< bit: 13 TC5 APB Clock Enable */
+ uint32_t :2; /*!< bit: 14..15 Reserved */
+ uint32_t ADC_:1; /*!< bit: 16 ADC APB Clock Enable */
+ uint32_t AC_:1; /*!< bit: 17 AC APB Clock Enable */
+ uint32_t :1; /*!< bit: 18 Reserved */
+ uint32_t PTC_:1; /*!< bit: 19 PTC APB Clock Enable */
+ uint32_t :1; /*!< bit: 20 Reserved */
+ uint32_t RFCTRL_:1; /*!< bit: 21 RFCTRL APB Clock Enable */
+ uint32_t :10; /*!< bit: 22..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} PM_APBCMASK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -413,11 +413,11 @@ typedef union {
/* -------- PM_INTENCLR : (PM Offset: 0x34) (R/W 8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} PM_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -431,11 +431,11 @@ typedef union {
/* -------- PM_INTENSET : (PM Offset: 0x35) (R/W 8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} PM_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -449,11 +449,11 @@ typedef union {
/* -------- PM_INTFLAG : (PM Offset: 0x36) (R/W 8) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint8_t CKRDY:1; /*!< bit: 0 Clock Ready */
- __I uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ __I uint8_t CKRDY:1; /*!< bit: 0 Clock Ready */
+ __I uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} PM_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -467,17 +467,17 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register
/* -------- PM_RCAUSE : (PM Offset: 0x38) (R/ 8) Reset Cause -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t POR:1; /*!< bit: 0 Power On Reset */
- uint8_t BOD12:1; /*!< bit: 1 Brown Out 12 Detector Reset */
- uint8_t BOD33:1; /*!< bit: 2 Brown Out 33 Detector Reset */
- uint8_t :1; /*!< bit: 3 Reserved */
- uint8_t EXT:1; /*!< bit: 4 External Reset */
- uint8_t WDT:1; /*!< bit: 5 Watchdog Reset */
- uint8_t SYST:1; /*!< bit: 6 System Reset Request */
- uint8_t :1; /*!< bit: 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t POR:1; /*!< bit: 0 Power On Reset */
+ uint8_t BOD12:1; /*!< bit: 1 Brown Out 12 Detector Reset */
+ uint8_t BOD33:1; /*!< bit: 2 Brown Out 33 Detector Reset */
+ uint8_t :1; /*!< bit: 3 Reserved */
+ uint8_t EXT:1; /*!< bit: 4 External Reset */
+ uint8_t WDT:1; /*!< bit: 5 Watchdog Reset */
+ uint8_t SYST:1; /*!< bit: 6 System Reset Request */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} PM_RCAUSE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -501,24 +501,24 @@ typedef union {
/** \brief PM hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO PM_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 8) Control */
- __IO PM_SLEEP_Type SLEEP; /**< \brief Offset: 0x01 (R/W 8) Sleep Mode */
- RoReg8 Reserved1[0x6];
- __IO PM_CPUSEL_Type CPUSEL; /**< \brief Offset: 0x08 (R/W 8) CPU Clock Select */
- __IO PM_APBASEL_Type APBASEL; /**< \brief Offset: 0x09 (R/W 8) APBA Clock Select */
- __IO PM_APBBSEL_Type APBBSEL; /**< \brief Offset: 0x0A (R/W 8) APBB Clock Select */
- __IO PM_APBCSEL_Type APBCSEL; /**< \brief Offset: 0x0B (R/W 8) APBC Clock Select */
- RoReg8 Reserved2[0x8];
- __IO PM_AHBMASK_Type AHBMASK; /**< \brief Offset: 0x14 (R/W 32) AHB Mask */
- __IO PM_APBAMASK_Type APBAMASK; /**< \brief Offset: 0x18 (R/W 32) APBA Mask */
- __IO PM_APBBMASK_Type APBBMASK; /**< \brief Offset: 0x1C (R/W 32) APBB Mask */
- __IO PM_APBCMASK_Type APBCMASK; /**< \brief Offset: 0x20 (R/W 32) APBC Mask */
- RoReg8 Reserved3[0x10];
- __IO PM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x34 (R/W 8) Interrupt Enable Clear */
- __IO PM_INTENSET_Type INTENSET; /**< \brief Offset: 0x35 (R/W 8) Interrupt Enable Set */
- __IO PM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x36 (R/W 8) Interrupt Flag Status and Clear */
- RoReg8 Reserved4[0x1];
- __I PM_RCAUSE_Type RCAUSE; /**< \brief Offset: 0x38 (R/ 8) Reset Cause */
+ __IO PM_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 8) Control */
+ __IO PM_SLEEP_Type SLEEP; /**< \brief Offset: 0x01 (R/W 8) Sleep Mode */
+ RoReg8 Reserved1[0x6];
+ __IO PM_CPUSEL_Type CPUSEL; /**< \brief Offset: 0x08 (R/W 8) CPU Clock Select */
+ __IO PM_APBASEL_Type APBASEL; /**< \brief Offset: 0x09 (R/W 8) APBA Clock Select */
+ __IO PM_APBBSEL_Type APBBSEL; /**< \brief Offset: 0x0A (R/W 8) APBB Clock Select */
+ __IO PM_APBCSEL_Type APBCSEL; /**< \brief Offset: 0x0B (R/W 8) APBC Clock Select */
+ RoReg8 Reserved2[0x8];
+ __IO PM_AHBMASK_Type AHBMASK; /**< \brief Offset: 0x14 (R/W 32) AHB Mask */
+ __IO PM_APBAMASK_Type APBAMASK; /**< \brief Offset: 0x18 (R/W 32) APBA Mask */
+ __IO PM_APBBMASK_Type APBBMASK; /**< \brief Offset: 0x1C (R/W 32) APBB Mask */
+ __IO PM_APBCMASK_Type APBCMASK; /**< \brief Offset: 0x20 (R/W 32) APBC Mask */
+ RoReg8 Reserved3[0x10];
+ __IO PM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x34 (R/W 8) Interrupt Enable Clear */
+ __IO PM_INTENSET_Type INTENSET; /**< \brief Offset: 0x35 (R/W 8) Interrupt Enable Set */
+ __IO PM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x36 (R/W 8) Interrupt Flag Status and Clear */
+ RoReg8 Reserved4[0x1];
+ __I PM_RCAUSE_Type RCAUSE; /**< \brief Offset: 0x38 (R/ 8) Reset Cause */
} Pm;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_port.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_port.h
index 23187d92918..344e41bc75f 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_port.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_port.h
@@ -56,10 +56,10 @@
/* -------- PORT_DIR : (PORT Offset: 0x00) (R/W 32) GROUP Data Direction -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t DIR:32; /*!< bit: 0..31 Port Data Direction */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t DIR:32; /*!< bit: 0..31 Port Data Direction */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} PORT_DIR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -74,10 +74,10 @@ typedef union {
/* -------- PORT_DIRCLR : (PORT Offset: 0x04) (R/W 32) GROUP Data Direction Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t DIRCLR:32; /*!< bit: 0..31 Port Data Direction Clear */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t DIRCLR:32; /*!< bit: 0..31 Port Data Direction Clear */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} PORT_DIRCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -92,10 +92,10 @@ typedef union {
/* -------- PORT_DIRSET : (PORT Offset: 0x08) (R/W 32) GROUP Data Direction Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t DIRSET:32; /*!< bit: 0..31 Port Data Direction Set */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t DIRSET:32; /*!< bit: 0..31 Port Data Direction Set */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} PORT_DIRSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -110,10 +110,10 @@ typedef union {
/* -------- PORT_DIRTGL : (PORT Offset: 0x0C) (R/W 32) GROUP Data Direction Toggle -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t DIRTGL:32; /*!< bit: 0..31 Port Data Direction Toggle */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t DIRTGL:32; /*!< bit: 0..31 Port Data Direction Toggle */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} PORT_DIRTGL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -128,10 +128,10 @@ typedef union {
/* -------- PORT_OUT : (PORT Offset: 0x10) (R/W 32) GROUP Data Output Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t OUT:32; /*!< bit: 0..31 Port Data Output Value */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t OUT:32; /*!< bit: 0..31 Port Data Output Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} PORT_OUT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -146,10 +146,10 @@ typedef union {
/* -------- PORT_OUTCLR : (PORT Offset: 0x14) (R/W 32) GROUP Data Output Value Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t OUTCLR:32; /*!< bit: 0..31 Port Data Output Value Clear */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t OUTCLR:32; /*!< bit: 0..31 Port Data Output Value Clear */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} PORT_OUTCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -164,10 +164,10 @@ typedef union {
/* -------- PORT_OUTSET : (PORT Offset: 0x18) (R/W 32) GROUP Data Output Value Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t OUTSET:32; /*!< bit: 0..31 Port Data Output Value Set */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t OUTSET:32; /*!< bit: 0..31 Port Data Output Value Set */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} PORT_OUTSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -182,10 +182,10 @@ typedef union {
/* -------- PORT_OUTTGL : (PORT Offset: 0x1C) (R/W 32) GROUP Data Output Value Toggle -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t OUTTGL:32; /*!< bit: 0..31 Port Data Output Value Toggle */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t OUTTGL:32; /*!< bit: 0..31 Port Data Output Value Toggle */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} PORT_OUTTGL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -200,10 +200,10 @@ typedef union {
/* -------- PORT_IN : (PORT Offset: 0x20) (R/ 32) GROUP Data Input Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t IN:32; /*!< bit: 0..31 Port Data Input Value */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t IN:32; /*!< bit: 0..31 Port Data Input Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} PORT_IN_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -218,10 +218,10 @@ typedef union {
/* -------- PORT_CTRL : (PORT Offset: 0x24) (R/W 32) GROUP Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SAMPLING:32; /*!< bit: 0..31 Input Sampling Mode */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SAMPLING:32; /*!< bit: 0..31 Input Sampling Mode */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} PORT_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -236,21 +236,21 @@ typedef union {
/* -------- PORT_WRCONFIG : (PORT Offset: 0x28) ( /W 32) GROUP Write Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t PINMASK:16; /*!< bit: 0..15 Pin Mask for Multiple Pin Configuration */
- uint32_t PMUXEN:1; /*!< bit: 16 Peripheral Multiplexer Enable */
- uint32_t INEN:1; /*!< bit: 17 Input Enable */
- uint32_t PULLEN:1; /*!< bit: 18 Pull Enable */
- uint32_t :3; /*!< bit: 19..21 Reserved */
- uint32_t DRVSTR:1; /*!< bit: 22 Output Driver Strength Selection */
- uint32_t :1; /*!< bit: 23 Reserved */
- uint32_t PMUX:4; /*!< bit: 24..27 Peripheral Multiplexing */
- uint32_t WRPMUX:1; /*!< bit: 28 Write PMUX */
- uint32_t :1; /*!< bit: 29 Reserved */
- uint32_t WRPINCFG:1; /*!< bit: 30 Write PINCFG */
- uint32_t HWSEL:1; /*!< bit: 31 Half-Word Select */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t PINMASK:16; /*!< bit: 0..15 Pin Mask for Multiple Pin Configuration */
+ uint32_t PMUXEN:1; /*!< bit: 16 Peripheral Multiplexer Enable */
+ uint32_t INEN:1; /*!< bit: 17 Input Enable */
+ uint32_t PULLEN:1; /*!< bit: 18 Pull Enable */
+ uint32_t :3; /*!< bit: 19..21 Reserved */
+ uint32_t DRVSTR:1; /*!< bit: 22 Output Driver Strength Selection */
+ uint32_t :1; /*!< bit: 23 Reserved */
+ uint32_t PMUX:4; /*!< bit: 24..27 Peripheral Multiplexing */
+ uint32_t WRPMUX:1; /*!< bit: 28 Write PMUX */
+ uint32_t :1; /*!< bit: 29 Reserved */
+ uint32_t WRPINCFG:1; /*!< bit: 30 Write PINCFG */
+ uint32_t HWSEL:1; /*!< bit: 31 Half-Word Select */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} PORT_WRCONFIG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -282,11 +282,11 @@ typedef union {
/* -------- PORT_PMUX : (PORT Offset: 0x30) (R/W 8) GROUP Peripheral Multiplexing n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t PMUXE:4; /*!< bit: 0.. 3 Peripheral Multiplexing Even */
- uint8_t PMUXO:4; /*!< bit: 4.. 7 Peripheral Multiplexing Odd */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t PMUXE:4; /*!< bit: 0.. 3 Peripheral Multiplexing Even */
+ uint8_t PMUXO:4; /*!< bit: 4.. 7 Peripheral Multiplexing Odd */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} PORT_PMUX_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -336,15 +336,15 @@ typedef union {
/* -------- PORT_PINCFG : (PORT Offset: 0x40) (R/W 8) GROUP Pin Configuration n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t PMUXEN:1; /*!< bit: 0 Peripheral Multiplexer Enable */
- uint8_t INEN:1; /*!< bit: 1 Input Enable */
- uint8_t PULLEN:1; /*!< bit: 2 Pull Enable */
- uint8_t :3; /*!< bit: 3.. 5 Reserved */
- uint8_t DRVSTR:1; /*!< bit: 6 Output Driver Strength Selection */
- uint8_t :1; /*!< bit: 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t PMUXEN:1; /*!< bit: 0 Peripheral Multiplexer Enable */
+ uint8_t INEN:1; /*!< bit: 1 Input Enable */
+ uint8_t PULLEN:1; /*!< bit: 2 Pull Enable */
+ uint8_t :3; /*!< bit: 3.. 5 Reserved */
+ uint8_t DRVSTR:1; /*!< bit: 6 Output Driver Strength Selection */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} PORT_PINCFG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -364,28 +364,28 @@ typedef union {
/** \brief PortGroup hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO PORT_DIR_Type DIR; /**< \brief Offset: 0x00 (R/W 32) Data Direction */
- __IO PORT_DIRCLR_Type DIRCLR; /**< \brief Offset: 0x04 (R/W 32) Data Direction Clear */
- __IO PORT_DIRSET_Type DIRSET; /**< \brief Offset: 0x08 (R/W 32) Data Direction Set */
- __IO PORT_DIRTGL_Type DIRTGL; /**< \brief Offset: 0x0C (R/W 32) Data Direction Toggle */
- __IO PORT_OUT_Type OUT; /**< \brief Offset: 0x10 (R/W 32) Data Output Value */
- __IO PORT_OUTCLR_Type OUTCLR; /**< \brief Offset: 0x14 (R/W 32) Data Output Value Clear */
- __IO PORT_OUTSET_Type OUTSET; /**< \brief Offset: 0x18 (R/W 32) Data Output Value Set */
- __IO PORT_OUTTGL_Type OUTTGL; /**< \brief Offset: 0x1C (R/W 32) Data Output Value Toggle */
- __I PORT_IN_Type IN; /**< \brief Offset: 0x20 (R/ 32) Data Input Value */
- __IO PORT_CTRL_Type CTRL; /**< \brief Offset: 0x24 (R/W 32) Control */
- __O PORT_WRCONFIG_Type WRCONFIG; /**< \brief Offset: 0x28 ( /W 32) Write Configuration */
- RoReg8 Reserved1[0x4];
- __IO PORT_PMUX_Type PMUX[16]; /**< \brief Offset: 0x30 (R/W 8) Peripheral Multiplexing n */
- __IO PORT_PINCFG_Type PINCFG[32]; /**< \brief Offset: 0x40 (R/W 8) Pin Configuration n */
- RoReg8 Reserved2[0x20];
+ __IO PORT_DIR_Type DIR; /**< \brief Offset: 0x00 (R/W 32) Data Direction */
+ __IO PORT_DIRCLR_Type DIRCLR; /**< \brief Offset: 0x04 (R/W 32) Data Direction Clear */
+ __IO PORT_DIRSET_Type DIRSET; /**< \brief Offset: 0x08 (R/W 32) Data Direction Set */
+ __IO PORT_DIRTGL_Type DIRTGL; /**< \brief Offset: 0x0C (R/W 32) Data Direction Toggle */
+ __IO PORT_OUT_Type OUT; /**< \brief Offset: 0x10 (R/W 32) Data Output Value */
+ __IO PORT_OUTCLR_Type OUTCLR; /**< \brief Offset: 0x14 (R/W 32) Data Output Value Clear */
+ __IO PORT_OUTSET_Type OUTSET; /**< \brief Offset: 0x18 (R/W 32) Data Output Value Set */
+ __IO PORT_OUTTGL_Type OUTTGL; /**< \brief Offset: 0x1C (R/W 32) Data Output Value Toggle */
+ __I PORT_IN_Type IN; /**< \brief Offset: 0x20 (R/ 32) Data Input Value */
+ __IO PORT_CTRL_Type CTRL; /**< \brief Offset: 0x24 (R/W 32) Control */
+ __O PORT_WRCONFIG_Type WRCONFIG; /**< \brief Offset: 0x28 ( /W 32) Write Configuration */
+ RoReg8 Reserved1[0x4];
+ __IO PORT_PMUX_Type PMUX[16]; /**< \brief Offset: 0x30 (R/W 8) Peripheral Multiplexing n */
+ __IO PORT_PINCFG_Type PINCFG[32]; /**< \brief Offset: 0x40 (R/W 8) Pin Configuration n */
+ RoReg8 Reserved2[0x20];
} PortGroup;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief PORT hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- PortGroup Group[3]; /**< \brief Offset: 0x00 PortGroup groups [GROUPS] */
+ PortGroup Group[3]; /**< \brief Offset: 0x00 PortGroup groups [GROUPS] */
} Port;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SECTION_PORT_IOBUS
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_rfctrl.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_rfctrl.h
index c260bb52b6b..d18226b3891 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_rfctrl.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_rfctrl.h
@@ -56,16 +56,16 @@
/* -------- RFCTRL_FECFG : (RFCTRL Offset: 0x0) (R/W 16) Front-end control bus configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t F0CFG:2; /*!< bit: 0.. 1 Front-end control signal 0 configuration */
- uint16_t F1CFG:2; /*!< bit: 2.. 3 Front-end control signal 1 configuration */
- uint16_t F2CFG:2; /*!< bit: 4.. 5 Front-end control signal 2 configuration */
- uint16_t F3CFG:2; /*!< bit: 6.. 7 Front-end control signal 3 configuration */
- uint16_t F4CFG:2; /*!< bit: 8.. 9 Front-end control signal 4 configuration */
- uint16_t F5CFG:2; /*!< bit: 10..11 Front-end control signal 5 configuration */
- uint16_t :4; /*!< bit: 12..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t F0CFG:2; /*!< bit: 0.. 1 Front-end control signal 0 configuration */
+ uint16_t F1CFG:2; /*!< bit: 2.. 3 Front-end control signal 1 configuration */
+ uint16_t F2CFG:2; /*!< bit: 4.. 5 Front-end control signal 2 configuration */
+ uint16_t F3CFG:2; /*!< bit: 6.. 7 Front-end control signal 3 configuration */
+ uint16_t F4CFG:2; /*!< bit: 8.. 9 Front-end control signal 4 configuration */
+ uint16_t F5CFG:2; /*!< bit: 10..11 Front-end control signal 5 configuration */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} RFCTRL_FECFG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -95,7 +95,7 @@ typedef union {
/** \brief RFCTRL hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO RFCTRL_FECFG_Type FECFG; /**< \brief Offset: 0x0 (R/W 16) Front-end control bus configuration */
+ __IO RFCTRL_FECFG_Type FECFG; /**< \brief Offset: 0x0 (R/W 16) Front-end control bus configuration */
} Rfctrl;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_rtc.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_rtc.h
index 9e657ccd9b3..6c1e8c48c1e 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_rtc.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_rtc.h
@@ -56,16 +56,16 @@
/* -------- RTC_MODE0_CTRL : (RTC Offset: 0x00) (R/W 16) MODE0 MODE0 Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t SWRST:1; /*!< bit: 0 Software Reset */
- uint16_t ENABLE:1; /*!< bit: 1 Enable */
- uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
- uint16_t :3; /*!< bit: 4.. 6 Reserved */
- uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */
- uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
- uint16_t :4; /*!< bit: 12..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint16_t ENABLE:1; /*!< bit: 1 Enable */
+ uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
+ uint16_t :3; /*!< bit: 4.. 6 Reserved */
+ uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */
+ uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} RTC_MODE0_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -117,15 +117,15 @@ typedef union {
/* -------- RTC_MODE1_CTRL : (RTC Offset: 0x00) (R/W 16) MODE1 MODE1 Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t SWRST:1; /*!< bit: 0 Software Reset */
- uint16_t ENABLE:1; /*!< bit: 1 Enable */
- uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
- uint16_t :4; /*!< bit: 4.. 7 Reserved */
- uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
- uint16_t :4; /*!< bit: 12..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint16_t ENABLE:1; /*!< bit: 1 Enable */
+ uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
+ uint16_t :4; /*!< bit: 4.. 7 Reserved */
+ uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} RTC_MODE1_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -175,17 +175,17 @@ typedef union {
/* -------- RTC_MODE2_CTRL : (RTC Offset: 0x00) (R/W 16) MODE2 MODE2 Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t SWRST:1; /*!< bit: 0 Software Reset */
- uint16_t ENABLE:1; /*!< bit: 1 Enable */
- uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
- uint16_t :2; /*!< bit: 4.. 5 Reserved */
- uint16_t CLKREP:1; /*!< bit: 6 Clock Representation */
- uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */
- uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
- uint16_t :4; /*!< bit: 12..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint16_t ENABLE:1; /*!< bit: 1 Enable */
+ uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
+ uint16_t :2; /*!< bit: 4.. 5 Reserved */
+ uint16_t CLKREP:1; /*!< bit: 6 Clock Representation */
+ uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */
+ uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} RTC_MODE2_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -239,13 +239,13 @@ typedef union {
/* -------- RTC_READREQ : (RTC Offset: 0x02) (R/W 16) Read Request -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t ADDR:6; /*!< bit: 0.. 5 Address */
- uint16_t :8; /*!< bit: 6..13 Reserved */
- uint16_t RCONT:1; /*!< bit: 14 Read Continuously */
- uint16_t RREQ:1; /*!< bit: 15 Read Request */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t ADDR:6; /*!< bit: 0.. 5 Address */
+ uint16_t :8; /*!< bit: 6..13 Reserved */
+ uint16_t RCONT:1; /*!< bit: 14 Read Continuously */
+ uint16_t RREQ:1; /*!< bit: 15 Read Request */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} RTC_READREQ_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -264,25 +264,25 @@ typedef union {
/* -------- RTC_MODE0_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE0 MODE0 Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
- uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
- uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
- uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
- uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
- uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
- uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
- uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
- uint16_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */
- uint16_t :6; /*!< bit: 9..14 Reserved */
- uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
- } bit; /*!< Structure used for bit access */
- struct {
- uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
- uint16_t CMPEO:1; /*!< bit: 8 Compare x Event Output Enable */
- uint16_t :7; /*!< bit: 9..15 Reserved */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
+ uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
+ uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
+ uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
+ uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
+ uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
+ uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
+ uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
+ uint16_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */
+ uint16_t :6; /*!< bit: 9..14 Reserved */
+ uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
+ uint16_t CMPEO:1; /*!< bit: 8 Compare x Event Output Enable */
+ uint16_t :7; /*!< bit: 9..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
} RTC_MODE0_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -320,26 +320,26 @@ typedef union {
/* -------- RTC_MODE1_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE1 MODE1 Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
- uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
- uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
- uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
- uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
- uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
- uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
- uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
- uint16_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */
- uint16_t CMPEO1:1; /*!< bit: 9 Compare 1 Event Output Enable */
- uint16_t :5; /*!< bit: 10..14 Reserved */
- uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
- } bit; /*!< Structure used for bit access */
- struct {
- uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
- uint16_t CMPEO:2; /*!< bit: 8.. 9 Compare x Event Output Enable */
- uint16_t :6; /*!< bit: 10..15 Reserved */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
+ uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
+ uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
+ uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
+ uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
+ uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
+ uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
+ uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
+ uint16_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */
+ uint16_t CMPEO1:1; /*!< bit: 9 Compare 1 Event Output Enable */
+ uint16_t :5; /*!< bit: 10..14 Reserved */
+ uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
+ uint16_t CMPEO:2; /*!< bit: 8.. 9 Compare x Event Output Enable */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
} RTC_MODE1_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -379,25 +379,25 @@ typedef union {
/* -------- RTC_MODE2_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE2 MODE2 Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
- uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
- uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
- uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
- uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
- uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
- uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
- uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
- uint16_t ALARMEO0:1; /*!< bit: 8 Alarm 0 Event Output Enable */
- uint16_t :6; /*!< bit: 9..14 Reserved */
- uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
- } bit; /*!< Structure used for bit access */
- struct {
- uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
- uint16_t ALARMEO:1; /*!< bit: 8 Alarm x Event Output Enable */
- uint16_t :7; /*!< bit: 9..15 Reserved */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
+ uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
+ uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
+ uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
+ uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
+ uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
+ uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
+ uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
+ uint16_t ALARMEO0:1; /*!< bit: 8 Alarm 0 Event Output Enable */
+ uint16_t :6; /*!< bit: 9..14 Reserved */
+ uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
+ uint16_t ALARMEO:1; /*!< bit: 8 Alarm x Event Output Enable */
+ uint16_t :7; /*!< bit: 9..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
} RTC_MODE2_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -435,17 +435,17 @@ typedef union {
/* -------- RTC_MODE0_INTENCLR : (RTC Offset: 0x06) (R/W 8) MODE0 MODE0 Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
- uint8_t :5; /*!< bit: 1.. 5 Reserved */
- uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
- uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t CMP:1; /*!< bit: 0 Compare x Interrupt Enable */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
+ uint8_t :5; /*!< bit: 1.. 5 Reserved */
+ uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
+ uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t CMP:1; /*!< bit: 0 Compare x Interrupt Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} RTC_MODE0_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -466,18 +466,18 @@ typedef union {
/* -------- RTC_MODE1_INTENCLR : (RTC Offset: 0x06) (R/W 8) MODE1 MODE1 Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
- uint8_t CMP1:1; /*!< bit: 1 Compare 1 Interrupt Enable */
- uint8_t :4; /*!< bit: 2.. 5 Reserved */
- uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
- uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t CMP:2; /*!< bit: 0.. 1 Compare x Interrupt Enable */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
+ uint8_t CMP1:1; /*!< bit: 1 Compare 1 Interrupt Enable */
+ uint8_t :4; /*!< bit: 2.. 5 Reserved */
+ uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
+ uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t CMP:2; /*!< bit: 0.. 1 Compare x Interrupt Enable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} RTC_MODE1_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -500,17 +500,17 @@ typedef union {
/* -------- RTC_MODE2_INTENCLR : (RTC Offset: 0x06) (R/W 8) MODE2 MODE2 Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 Interrupt Enable */
- uint8_t :5; /*!< bit: 1.. 5 Reserved */
- uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
- uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t ALARM:1; /*!< bit: 0 Alarm x Interrupt Enable */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 Interrupt Enable */
+ uint8_t :5; /*!< bit: 1.. 5 Reserved */
+ uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
+ uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t ALARM:1; /*!< bit: 0 Alarm x Interrupt Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} RTC_MODE2_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -531,17 +531,17 @@ typedef union {
/* -------- RTC_MODE0_INTENSET : (RTC Offset: 0x07) (R/W 8) MODE0 MODE0 Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
- uint8_t :5; /*!< bit: 1.. 5 Reserved */
- uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
- uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t CMP:1; /*!< bit: 0 Compare x Interrupt Enable */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
+ uint8_t :5; /*!< bit: 1.. 5 Reserved */
+ uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
+ uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t CMP:1; /*!< bit: 0 Compare x Interrupt Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} RTC_MODE0_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -562,18 +562,18 @@ typedef union {
/* -------- RTC_MODE1_INTENSET : (RTC Offset: 0x07) (R/W 8) MODE1 MODE1 Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
- uint8_t CMP1:1; /*!< bit: 1 Compare 1 Interrupt Enable */
- uint8_t :4; /*!< bit: 2.. 5 Reserved */
- uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
- uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t CMP:2; /*!< bit: 0.. 1 Compare x Interrupt Enable */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
+ uint8_t CMP1:1; /*!< bit: 1 Compare 1 Interrupt Enable */
+ uint8_t :4; /*!< bit: 2.. 5 Reserved */
+ uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
+ uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t CMP:2; /*!< bit: 0.. 1 Compare x Interrupt Enable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} RTC_MODE1_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -596,17 +596,17 @@ typedef union {
/* -------- RTC_MODE2_INTENSET : (RTC Offset: 0x07) (R/W 8) MODE2 MODE2 Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 Interrupt Enable */
- uint8_t :5; /*!< bit: 1.. 5 Reserved */
- uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
- uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t ALARM:1; /*!< bit: 0 Alarm x Interrupt Enable */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 Interrupt Enable */
+ uint8_t :5; /*!< bit: 1.. 5 Reserved */
+ uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
+ uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t ALARM:1; /*!< bit: 0 Alarm x Interrupt Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} RTC_MODE2_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -627,17 +627,17 @@ typedef union {
/* -------- RTC_MODE0_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE0 MODE0 Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint8_t CMP0:1; /*!< bit: 0 Compare 0 */
- __I uint8_t :5; /*!< bit: 1.. 5 Reserved */
- __I uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
- __I uint8_t OVF:1; /*!< bit: 7 Overflow */
- } bit; /*!< Structure used for bit access */
- struct {
- __I uint8_t CMP:1; /*!< bit: 0 Compare x */
- __I uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ __I uint8_t CMP0:1; /*!< bit: 0 Compare 0 */
+ __I uint8_t :5; /*!< bit: 1.. 5 Reserved */
+ __I uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
+ __I uint8_t OVF:1; /*!< bit: 7 Overflow */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ __I uint8_t CMP:1; /*!< bit: 0 Compare x */
+ __I uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} RTC_MODE0_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -658,18 +658,18 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register
/* -------- RTC_MODE1_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE1 MODE1 Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint8_t CMP0:1; /*!< bit: 0 Compare 0 */
- __I uint8_t CMP1:1; /*!< bit: 1 Compare 1 */
- __I uint8_t :4; /*!< bit: 2.. 5 Reserved */
- __I uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
- __I uint8_t OVF:1; /*!< bit: 7 Overflow */
- } bit; /*!< Structure used for bit access */
- struct {
- __I uint8_t CMP:2; /*!< bit: 0.. 1 Compare x */
- __I uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ __I uint8_t CMP0:1; /*!< bit: 0 Compare 0 */
+ __I uint8_t CMP1:1; /*!< bit: 1 Compare 1 */
+ __I uint8_t :4; /*!< bit: 2.. 5 Reserved */
+ __I uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
+ __I uint8_t OVF:1; /*!< bit: 7 Overflow */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ __I uint8_t CMP:2; /*!< bit: 0.. 1 Compare x */
+ __I uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} RTC_MODE1_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -692,17 +692,17 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register
/* -------- RTC_MODE2_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE2 MODE2 Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 */
- __I uint8_t :5; /*!< bit: 1.. 5 Reserved */
- __I uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
- __I uint8_t OVF:1; /*!< bit: 7 Overflow */
- } bit; /*!< Structure used for bit access */
- struct {
- __I uint8_t ALARM:1; /*!< bit: 0 Alarm x */
- __I uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ __I uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 */
+ __I uint8_t :5; /*!< bit: 1.. 5 Reserved */
+ __I uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
+ __I uint8_t OVF:1; /*!< bit: 7 Overflow */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ __I uint8_t ALARM:1; /*!< bit: 0 Alarm x */
+ __I uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} RTC_MODE2_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -723,11 +723,11 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register
/* -------- RTC_STATUS : (RTC Offset: 0x0A) (R/W 8) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t :7; /*!< bit: 0.. 6 Reserved */
- uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t :7; /*!< bit: 0.. 6 Reserved */
+ uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} RTC_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -741,11 +741,11 @@ typedef union {
/* -------- RTC_DBGCTRL : (RTC Offset: 0x0B) (R/W 8) Debug Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DBGRUN:1; /*!< bit: 0 Run During Debug */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DBGRUN:1; /*!< bit: 0 Run During Debug */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} RTC_DBGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -759,11 +759,11 @@ typedef union {
/* -------- RTC_FREQCORR : (RTC Offset: 0x0C) (R/W 8) Frequency Correction -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t VALUE:7; /*!< bit: 0.. 6 Correction Value */
- uint8_t SIGN:1; /*!< bit: 7 Correction Sign */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t VALUE:7; /*!< bit: 0.. 6 Correction Value */
+ uint8_t SIGN:1; /*!< bit: 7 Correction Sign */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} RTC_FREQCORR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -780,10 +780,10 @@ typedef union {
/* -------- RTC_MODE0_COUNT : (RTC Offset: 0x10) (R/W 32) MODE0 MODE0 Counter Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t COUNT:32; /*!< bit: 0..31 Counter Value */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t COUNT:32; /*!< bit: 0..31 Counter Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} RTC_MODE0_COUNT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -798,10 +798,10 @@ typedef union {
/* -------- RTC_MODE1_COUNT : (RTC Offset: 0x10) (R/W 16) MODE1 MODE1 Counter Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t COUNT:16; /*!< bit: 0..15 Counter Value */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t COUNT:16; /*!< bit: 0..15 Counter Value */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} RTC_MODE1_COUNT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -816,15 +816,15 @@ typedef union {
/* -------- RTC_MODE2_CLOCK : (RTC Offset: 0x10) (R/W 32) MODE2 MODE2 Clock Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SECOND:6; /*!< bit: 0.. 5 Second */
- uint32_t MINUTE:6; /*!< bit: 6..11 Minute */
- uint32_t HOUR:5; /*!< bit: 12..16 Hour */
- uint32_t DAY:5; /*!< bit: 17..21 Day */
- uint32_t MONTH:4; /*!< bit: 22..25 Month */
- uint32_t YEAR:6; /*!< bit: 26..31 Year */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SECOND:6; /*!< bit: 0.. 5 Second */
+ uint32_t MINUTE:6; /*!< bit: 6..11 Minute */
+ uint32_t HOUR:5; /*!< bit: 12..16 Hour */
+ uint32_t DAY:5; /*!< bit: 17..21 Day */
+ uint32_t MONTH:4; /*!< bit: 22..25 Month */
+ uint32_t YEAR:6; /*!< bit: 26..31 Year */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} RTC_MODE2_CLOCK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -856,10 +856,10 @@ typedef union {
/* -------- RTC_MODE1_PER : (RTC Offset: 0x14) (R/W 16) MODE1 MODE1 Counter Period -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t PER:16; /*!< bit: 0..15 Counter Period */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t PER:16; /*!< bit: 0..15 Counter Period */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} RTC_MODE1_PER_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -874,10 +874,10 @@ typedef union {
/* -------- RTC_MODE0_COMP : (RTC Offset: 0x18) (R/W 32) MODE0 MODE0 Compare n Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t COMP:32; /*!< bit: 0..31 Compare Value */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t COMP:32; /*!< bit: 0..31 Compare Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} RTC_MODE0_COMP_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -892,10 +892,10 @@ typedef union {
/* -------- RTC_MODE1_COMP : (RTC Offset: 0x18) (R/W 16) MODE1 MODE1 Compare n Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t COMP:16; /*!< bit: 0..15 Compare Value */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t COMP:16; /*!< bit: 0..15 Compare Value */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} RTC_MODE1_COMP_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -910,15 +910,15 @@ typedef union {
/* -------- RTC_MODE2_ALARM : (RTC Offset: 0x18) (R/W 32) MODE2 MODE2_ALARM Alarm n Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SECOND:6; /*!< bit: 0.. 5 Second */
- uint32_t MINUTE:6; /*!< bit: 6..11 Minute */
- uint32_t HOUR:5; /*!< bit: 12..16 Hour */
- uint32_t DAY:5; /*!< bit: 17..21 Day */
- uint32_t MONTH:4; /*!< bit: 22..25 Month */
- uint32_t YEAR:6; /*!< bit: 26..31 Year */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SECOND:6; /*!< bit: 0.. 5 Second */
+ uint32_t MINUTE:6; /*!< bit: 6..11 Minute */
+ uint32_t HOUR:5; /*!< bit: 12..16 Hour */
+ uint32_t DAY:5; /*!< bit: 17..21 Day */
+ uint32_t MONTH:4; /*!< bit: 22..25 Month */
+ uint32_t YEAR:6; /*!< bit: 26..31 Year */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} RTC_MODE2_ALARM_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -948,11 +948,11 @@ typedef union {
/* -------- RTC_MODE2_MASK : (RTC Offset: 0x1C) (R/W 8) MODE2 MODE2_ALARM Alarm n Mask -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t SEL:3; /*!< bit: 0.. 2 Alarm Mask Selection */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t SEL:3; /*!< bit: 0.. 2 Alarm Mask Selection */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} RTC_MODE2_MASK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -981,79 +981,79 @@ typedef union {
/** \brief RtcMode2Alarm hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO RTC_MODE2_ALARM_Type ALARM; /**< \brief Offset: 0x00 (R/W 32) MODE2_ALARM Alarm n Value */
- __IO RTC_MODE2_MASK_Type MASK; /**< \brief Offset: 0x04 (R/W 8) MODE2_ALARM Alarm n Mask */
- RoReg8 Reserved1[0x3];
+ __IO RTC_MODE2_ALARM_Type ALARM; /**< \brief Offset: 0x00 (R/W 32) MODE2_ALARM Alarm n Value */
+ __IO RTC_MODE2_MASK_Type MASK; /**< \brief Offset: 0x04 (R/W 8) MODE2_ALARM Alarm n Mask */
+ RoReg8 Reserved1[0x3];
} RtcMode2Alarm;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief RTC_MODE0 hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* 32-bit Counter with Single 32-bit Compare */
- __IO RTC_MODE0_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE0 Control */
- __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
- __IO RTC_MODE0_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE0 Event Control */
- __IO RTC_MODE0_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE0 Interrupt Enable Clear */
- __IO RTC_MODE0_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE0 Interrupt Enable Set */
- __IO RTC_MODE0_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE0 Interrupt Flag Status and Clear */
- RoReg8 Reserved1[0x1];
- __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */
- __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */
- __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */
- RoReg8 Reserved2[0x3];
- __IO RTC_MODE0_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 32) MODE0 Counter Value */
- RoReg8 Reserved3[0x4];
- __IO RTC_MODE0_COMP_Type COMP[1]; /**< \brief Offset: 0x18 (R/W 32) MODE0 Compare n Value */
+ __IO RTC_MODE0_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE0 Control */
+ __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
+ __IO RTC_MODE0_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE0 Event Control */
+ __IO RTC_MODE0_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE0 Interrupt Enable Clear */
+ __IO RTC_MODE0_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE0 Interrupt Enable Set */
+ __IO RTC_MODE0_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE0 Interrupt Flag Status and Clear */
+ RoReg8 Reserved1[0x1];
+ __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */
+ __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */
+ __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */
+ RoReg8 Reserved2[0x3];
+ __IO RTC_MODE0_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 32) MODE0 Counter Value */
+ RoReg8 Reserved3[0x4];
+ __IO RTC_MODE0_COMP_Type COMP[1]; /**< \brief Offset: 0x18 (R/W 32) MODE0 Compare n Value */
} RtcMode0;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief RTC_MODE1 hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* 16-bit Counter with Two 16-bit Compares */
- __IO RTC_MODE1_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE1 Control */
- __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
- __IO RTC_MODE1_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE1 Event Control */
- __IO RTC_MODE1_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE1 Interrupt Enable Clear */
- __IO RTC_MODE1_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE1 Interrupt Enable Set */
- __IO RTC_MODE1_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE1 Interrupt Flag Status and Clear */
- RoReg8 Reserved1[0x1];
- __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */
- __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */
- __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */
- RoReg8 Reserved2[0x3];
- __IO RTC_MODE1_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 16) MODE1 Counter Value */
- RoReg8 Reserved3[0x2];
- __IO RTC_MODE1_PER_Type PER; /**< \brief Offset: 0x14 (R/W 16) MODE1 Counter Period */
- RoReg8 Reserved4[0x2];
- __IO RTC_MODE1_COMP_Type COMP[2]; /**< \brief Offset: 0x18 (R/W 16) MODE1 Compare n Value */
+ __IO RTC_MODE1_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE1 Control */
+ __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
+ __IO RTC_MODE1_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE1 Event Control */
+ __IO RTC_MODE1_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE1 Interrupt Enable Clear */
+ __IO RTC_MODE1_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE1 Interrupt Enable Set */
+ __IO RTC_MODE1_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE1 Interrupt Flag Status and Clear */
+ RoReg8 Reserved1[0x1];
+ __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */
+ __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */
+ __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */
+ RoReg8 Reserved2[0x3];
+ __IO RTC_MODE1_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 16) MODE1 Counter Value */
+ RoReg8 Reserved3[0x2];
+ __IO RTC_MODE1_PER_Type PER; /**< \brief Offset: 0x14 (R/W 16) MODE1 Counter Period */
+ RoReg8 Reserved4[0x2];
+ __IO RTC_MODE1_COMP_Type COMP[2]; /**< \brief Offset: 0x18 (R/W 16) MODE1 Compare n Value */
} RtcMode1;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief RTC_MODE2 hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* Clock/Calendar with Alarm */
- __IO RTC_MODE2_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE2 Control */
- __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
- __IO RTC_MODE2_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE2 Event Control */
- __IO RTC_MODE2_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE2 Interrupt Enable Clear */
- __IO RTC_MODE2_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE2 Interrupt Enable Set */
- __IO RTC_MODE2_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE2 Interrupt Flag Status and Clear */
- RoReg8 Reserved1[0x1];
- __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */
- __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */
- __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */
- RoReg8 Reserved2[0x3];
- __IO RTC_MODE2_CLOCK_Type CLOCK; /**< \brief Offset: 0x10 (R/W 32) MODE2 Clock Value */
- RoReg8 Reserved3[0x4];
- RtcMode2Alarm Mode2Alarm[1]; /**< \brief Offset: 0x18 RtcMode2Alarm groups [ALARM_NUM] */
+ __IO RTC_MODE2_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE2 Control */
+ __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
+ __IO RTC_MODE2_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE2 Event Control */
+ __IO RTC_MODE2_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE2 Interrupt Enable Clear */
+ __IO RTC_MODE2_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE2 Interrupt Enable Set */
+ __IO RTC_MODE2_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE2 Interrupt Flag Status and Clear */
+ RoReg8 Reserved1[0x1];
+ __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */
+ __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */
+ __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */
+ RoReg8 Reserved2[0x3];
+ __IO RTC_MODE2_CLOCK_Type CLOCK; /**< \brief Offset: 0x10 (R/W 32) MODE2 Clock Value */
+ RoReg8 Reserved3[0x4];
+ RtcMode2Alarm Mode2Alarm[1]; /**< \brief Offset: 0x18 RtcMode2Alarm groups [ALARM_NUM] */
} RtcMode2;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- RtcMode0 MODE0; /**< \brief Offset: 0x00 32-bit Counter with Single 32-bit Compare */
- RtcMode1 MODE1; /**< \brief Offset: 0x00 16-bit Counter with Two 16-bit Compares */
- RtcMode2 MODE2; /**< \brief Offset: 0x00 Clock/Calendar with Alarm */
+ RtcMode0 MODE0; /**< \brief Offset: 0x00 32-bit Counter with Single 32-bit Compare */
+ RtcMode1 MODE1; /**< \brief Offset: 0x00 16-bit Counter with Two 16-bit Compares */
+ RtcMode2 MODE2; /**< \brief Offset: 0x00 Clock/Calendar with Alarm */
} Rtc;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_sercom.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_sercom.h
index f1271ff1ace..055938af599 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_sercom.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_sercom.h
@@ -56,26 +56,26 @@
/* -------- SERCOM_I2CM_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CM I2CM Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Software Reset */
- uint32_t ENABLE:1; /*!< bit: 1 Enable */
- uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
- uint32_t :2; /*!< bit: 5.. 6 Reserved */
- uint32_t RUNSTDBY:1; /*!< bit: 7 Run in Standby */
- uint32_t :8; /*!< bit: 8..15 Reserved */
- uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */
- uint32_t :3; /*!< bit: 17..19 Reserved */
- uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */
- uint32_t MEXTTOEN:1; /*!< bit: 22 Master SCL Low Extend Timeout */
- uint32_t SEXTTOEN:1; /*!< bit: 23 Slave SCL Low Extend Timeout */
- uint32_t SPEED:2; /*!< bit: 24..25 Transfer Speed */
- uint32_t :1; /*!< bit: 26 Reserved */
- uint32_t SCLSM:1; /*!< bit: 27 SCL Clock Stretch Mode */
- uint32_t INACTOUT:2; /*!< bit: 28..29 Inactive Time-Out */
- uint32_t LOWTOUTEN:1; /*!< bit: 30 SCL Low Timeout Enable */
- uint32_t :1; /*!< bit: 31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */
+ uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
+ uint32_t :2; /*!< bit: 5.. 6 Reserved */
+ uint32_t RUNSTDBY:1; /*!< bit: 7 Run in Standby */
+ uint32_t :8; /*!< bit: 8..15 Reserved */
+ uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */
+ uint32_t :3; /*!< bit: 17..19 Reserved */
+ uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */
+ uint32_t MEXTTOEN:1; /*!< bit: 22 Master SCL Low Extend Timeout */
+ uint32_t SEXTTOEN:1; /*!< bit: 23 Slave SCL Low Extend Timeout */
+ uint32_t SPEED:2; /*!< bit: 24..25 Transfer Speed */
+ uint32_t :1; /*!< bit: 26 Reserved */
+ uint32_t SCLSM:1; /*!< bit: 27 SCL Clock Stretch Mode */
+ uint32_t INACTOUT:2; /*!< bit: 28..29 Inactive Time-Out */
+ uint32_t LOWTOUTEN:1; /*!< bit: 30 SCL Low Timeout Enable */
+ uint32_t :1; /*!< bit: 31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SERCOM_I2CM_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -127,26 +127,26 @@ typedef union {
/* -------- SERCOM_I2CS_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CS I2CS Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Software Reset */
- uint32_t ENABLE:1; /*!< bit: 1 Enable */
- uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
- uint32_t :2; /*!< bit: 5.. 6 Reserved */
- uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */
- uint32_t :8; /*!< bit: 8..15 Reserved */
- uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */
- uint32_t :3; /*!< bit: 17..19 Reserved */
- uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */
- uint32_t :1; /*!< bit: 22 Reserved */
- uint32_t SEXTTOEN:1; /*!< bit: 23 Slave SCL Low Extend Timeout */
- uint32_t SPEED:2; /*!< bit: 24..25 Transfer Speed */
- uint32_t :1; /*!< bit: 26 Reserved */
- uint32_t SCLSM:1; /*!< bit: 27 SCL Clock Stretch Mode */
- uint32_t :2; /*!< bit: 28..29 Reserved */
- uint32_t LOWTOUTEN:1; /*!< bit: 30 SCL Low Timeout Enable */
- uint32_t :1; /*!< bit: 31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */
+ uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
+ uint32_t :2; /*!< bit: 5.. 6 Reserved */
+ uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */
+ uint32_t :8; /*!< bit: 8..15 Reserved */
+ uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */
+ uint32_t :3; /*!< bit: 17..19 Reserved */
+ uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */
+ uint32_t :1; /*!< bit: 22 Reserved */
+ uint32_t SEXTTOEN:1; /*!< bit: 23 Slave SCL Low Extend Timeout */
+ uint32_t SPEED:2; /*!< bit: 24..25 Transfer Speed */
+ uint32_t :1; /*!< bit: 26 Reserved */
+ uint32_t SCLSM:1; /*!< bit: 27 SCL Clock Stretch Mode */
+ uint32_t :2; /*!< bit: 28..29 Reserved */
+ uint32_t LOWTOUTEN:1; /*!< bit: 30 SCL Low Timeout Enable */
+ uint32_t :1; /*!< bit: 31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SERCOM_I2CS_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -193,25 +193,25 @@ typedef union {
/* -------- SERCOM_SPI_CTRLA : (SERCOM Offset: 0x00) (R/W 32) SPI SPI Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Software Reset */
- uint32_t ENABLE:1; /*!< bit: 1 Enable */
- uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
- uint32_t :2; /*!< bit: 5.. 6 Reserved */
- uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */
- uint32_t IBON:1; /*!< bit: 8 Immediate Buffer Overflow Notification */
- uint32_t :7; /*!< bit: 9..15 Reserved */
- uint32_t DOPO:2; /*!< bit: 16..17 Data Out Pinout */
- uint32_t :2; /*!< bit: 18..19 Reserved */
- uint32_t DIPO:2; /*!< bit: 20..21 Data In Pinout */
- uint32_t :2; /*!< bit: 22..23 Reserved */
- uint32_t FORM:4; /*!< bit: 24..27 Frame Format */
- uint32_t CPHA:1; /*!< bit: 28 Clock Phase */
- uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */
- uint32_t DORD:1; /*!< bit: 30 Data Order */
- uint32_t :1; /*!< bit: 31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */
+ uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
+ uint32_t :2; /*!< bit: 5.. 6 Reserved */
+ uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */
+ uint32_t IBON:1; /*!< bit: 8 Immediate Buffer Overflow Notification */
+ uint32_t :7; /*!< bit: 9..15 Reserved */
+ uint32_t DOPO:2; /*!< bit: 16..17 Data Out Pinout */
+ uint32_t :2; /*!< bit: 18..19 Reserved */
+ uint32_t DIPO:2; /*!< bit: 20..21 Data In Pinout */
+ uint32_t :2; /*!< bit: 22..23 Reserved */
+ uint32_t FORM:4; /*!< bit: 24..27 Frame Format */
+ uint32_t CPHA:1; /*!< bit: 28 Clock Phase */
+ uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */
+ uint32_t DORD:1; /*!< bit: 30 Data Order */
+ uint32_t :1; /*!< bit: 31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SERCOM_SPI_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -261,26 +261,26 @@ typedef union {
/* -------- SERCOM_USART_CTRLA : (SERCOM Offset: 0x00) (R/W 32) USART USART Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Software Reset */
- uint32_t ENABLE:1; /*!< bit: 1 Enable */
- uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
- uint32_t :2; /*!< bit: 5.. 6 Reserved */
- uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */
- uint32_t IBON:1; /*!< bit: 8 Immediate Buffer Overflow Notification */
- uint32_t :4; /*!< bit: 9..12 Reserved */
- uint32_t SAMPR:3; /*!< bit: 13..15 Sample */
- uint32_t TXPO:2; /*!< bit: 16..17 Transmit Data Pinout */
- uint32_t :2; /*!< bit: 18..19 Reserved */
- uint32_t RXPO:2; /*!< bit: 20..21 Receive Data Pinout */
- uint32_t SAMPA:2; /*!< bit: 22..23 Sample Adjustment */
- uint32_t FORM:4; /*!< bit: 24..27 Frame Format */
- uint32_t CMODE:1; /*!< bit: 28 Communication Mode */
- uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */
- uint32_t DORD:1; /*!< bit: 30 Data Order */
- uint32_t :1; /*!< bit: 31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */
+ uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
+ uint32_t :2; /*!< bit: 5.. 6 Reserved */
+ uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */
+ uint32_t IBON:1; /*!< bit: 8 Immediate Buffer Overflow Notification */
+ uint32_t :4; /*!< bit: 9..12 Reserved */
+ uint32_t SAMPR:3; /*!< bit: 13..15 Sample */
+ uint32_t TXPO:2; /*!< bit: 16..17 Transmit Data Pinout */
+ uint32_t :2; /*!< bit: 18..19 Reserved */
+ uint32_t RXPO:2; /*!< bit: 20..21 Receive Data Pinout */
+ uint32_t SAMPA:2; /*!< bit: 22..23 Sample Adjustment */
+ uint32_t FORM:4; /*!< bit: 24..27 Frame Format */
+ uint32_t CMODE:1; /*!< bit: 28 Communication Mode */
+ uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */
+ uint32_t DORD:1; /*!< bit: 30 Data Order */
+ uint32_t :1; /*!< bit: 31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SERCOM_USART_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -336,16 +336,16 @@ typedef union {
/* -------- SERCOM_I2CM_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CM I2CM Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t :8; /*!< bit: 0.. 7 Reserved */
- uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */
- uint32_t QCEN:1; /*!< bit: 9 Quick Command Enable */
- uint32_t :6; /*!< bit: 10..15 Reserved */
- uint32_t CMD:2; /*!< bit: 16..17 Command */
- uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */
- uint32_t :13; /*!< bit: 19..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t :8; /*!< bit: 0.. 7 Reserved */
+ uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */
+ uint32_t QCEN:1; /*!< bit: 9 Quick Command Enable */
+ uint32_t :6; /*!< bit: 10..15 Reserved */
+ uint32_t CMD:2; /*!< bit: 16..17 Command */
+ uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */
+ uint32_t :13; /*!< bit: 19..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SERCOM_I2CM_CTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -366,18 +366,18 @@ typedef union {
/* -------- SERCOM_I2CS_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CS I2CS Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t :8; /*!< bit: 0.. 7 Reserved */
- uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */
- uint32_t GCMD:1; /*!< bit: 9 PMBus Group Command */
- uint32_t AACKEN:1; /*!< bit: 10 Automatic Address Acknowledge */
- uint32_t :3; /*!< bit: 11..13 Reserved */
- uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */
- uint32_t CMD:2; /*!< bit: 16..17 Command */
- uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */
- uint32_t :13; /*!< bit: 19..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t :8; /*!< bit: 0.. 7 Reserved */
+ uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */
+ uint32_t GCMD:1; /*!< bit: 9 PMBus Group Command */
+ uint32_t AACKEN:1; /*!< bit: 10 Automatic Address Acknowledge */
+ uint32_t :3; /*!< bit: 11..13 Reserved */
+ uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */
+ uint32_t CMD:2; /*!< bit: 16..17 Command */
+ uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */
+ uint32_t :13; /*!< bit: 19..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SERCOM_I2CS_CTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -403,20 +403,20 @@ typedef union {
/* -------- SERCOM_SPI_CTRLB : (SERCOM Offset: 0x04) (R/W 32) SPI SPI Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */
- uint32_t :3; /*!< bit: 3.. 5 Reserved */
- uint32_t PLOADEN:1; /*!< bit: 6 Data Preload Enable */
- uint32_t :2; /*!< bit: 7.. 8 Reserved */
- uint32_t SSDE:1; /*!< bit: 9 Slave Select Low Detect Enable */
- uint32_t :3; /*!< bit: 10..12 Reserved */
- uint32_t MSSEN:1; /*!< bit: 13 Master Slave Select Enable */
- uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */
- uint32_t :1; /*!< bit: 16 Reserved */
- uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */
- uint32_t :14; /*!< bit: 18..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */
+ uint32_t :3; /*!< bit: 3.. 5 Reserved */
+ uint32_t PLOADEN:1; /*!< bit: 6 Data Preload Enable */
+ uint32_t :2; /*!< bit: 7.. 8 Reserved */
+ uint32_t SSDE:1; /*!< bit: 9 Slave Select Low Detect Enable */
+ uint32_t :3; /*!< bit: 10..12 Reserved */
+ uint32_t MSSEN:1; /*!< bit: 13 Master Slave Select Enable */
+ uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */
+ uint32_t :1; /*!< bit: 16 Reserved */
+ uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */
+ uint32_t :14; /*!< bit: 18..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SERCOM_SPI_CTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -442,22 +442,22 @@ typedef union {
/* -------- SERCOM_USART_CTRLB : (SERCOM Offset: 0x04) (R/W 32) USART USART Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */
- uint32_t :3; /*!< bit: 3.. 5 Reserved */
- uint32_t SBMODE:1; /*!< bit: 6 Stop Bit Mode */
- uint32_t :1; /*!< bit: 7 Reserved */
- uint32_t COLDEN:1; /*!< bit: 8 Collision Detection Enable */
- uint32_t SFDE:1; /*!< bit: 9 Start of Frame Detection Enable */
- uint32_t ENC:1; /*!< bit: 10 Encoding Format */
- uint32_t :2; /*!< bit: 11..12 Reserved */
- uint32_t PMODE:1; /*!< bit: 13 Parity Mode */
- uint32_t :2; /*!< bit: 14..15 Reserved */
- uint32_t TXEN:1; /*!< bit: 16 Transmitter Enable */
- uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */
- uint32_t :14; /*!< bit: 18..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */
+ uint32_t :3; /*!< bit: 3.. 5 Reserved */
+ uint32_t SBMODE:1; /*!< bit: 6 Stop Bit Mode */
+ uint32_t :1; /*!< bit: 7 Reserved */
+ uint32_t COLDEN:1; /*!< bit: 8 Collision Detection Enable */
+ uint32_t SFDE:1; /*!< bit: 9 Start of Frame Detection Enable */
+ uint32_t ENC:1; /*!< bit: 10 Encoding Format */
+ uint32_t :2; /*!< bit: 11..12 Reserved */
+ uint32_t PMODE:1; /*!< bit: 13 Parity Mode */
+ uint32_t :2; /*!< bit: 14..15 Reserved */
+ uint32_t TXEN:1; /*!< bit: 16 Transmitter Enable */
+ uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */
+ uint32_t :14; /*!< bit: 18..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SERCOM_USART_CTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -486,13 +486,13 @@ typedef union {
/* -------- SERCOM_I2CM_BAUD : (SERCOM Offset: 0x0C) (R/W 32) I2CM I2CM Baud Rate -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t BAUD:8; /*!< bit: 0.. 7 Baud Rate Value */
- uint32_t BAUDLOW:8; /*!< bit: 8..15 Baud Rate Value Low */
- uint32_t HSBAUD:8; /*!< bit: 16..23 High Speed Baud Rate Value */
- uint32_t HSBAUDLOW:8; /*!< bit: 24..31 High Speed Baud Rate Value Low */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t BAUD:8; /*!< bit: 0.. 7 Baud Rate Value */
+ uint32_t BAUDLOW:8; /*!< bit: 8..15 Baud Rate Value Low */
+ uint32_t HSBAUD:8; /*!< bit: 16..23 High Speed Baud Rate Value */
+ uint32_t HSBAUDLOW:8; /*!< bit: 24..31 High Speed Baud Rate Value Low */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SERCOM_I2CM_BAUD_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -516,10 +516,10 @@ typedef union {
/* -------- SERCOM_SPI_BAUD : (SERCOM Offset: 0x0C) (R/W 8) SPI SPI Baud Rate -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t BAUD:8; /*!< bit: 0.. 7 Baud Rate Value */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t BAUD:8; /*!< bit: 0.. 7 Baud Rate Value */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_SPI_BAUD_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -534,21 +534,21 @@ typedef union {
/* -------- SERCOM_USART_BAUD : (SERCOM Offset: 0x0C) (R/W 16) USART USART Baud Rate -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t BAUD:16; /*!< bit: 0..15 Baud Rate Value */
- } bit; /*!< Structure used for bit access */
- struct { // FRAC mode
- uint16_t BAUD:13; /*!< bit: 0..12 Baud Rate Value */
- uint16_t FP:3; /*!< bit: 13..15 Fractional Part */
- } FRAC; /*!< Structure used for FRAC */
- struct { // FRACFP mode
- uint16_t BAUD:13; /*!< bit: 0..12 Baud Rate Value */
- uint16_t FP:3; /*!< bit: 13..15 Fractional Part */
- } FRACFP; /*!< Structure used for FRACFP */
- struct { // USARTFP mode
- uint16_t BAUD:16; /*!< bit: 0..15 Baud Rate Value */
- } USARTFP; /*!< Structure used for USARTFP */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t BAUD:16; /*!< bit: 0..15 Baud Rate Value */
+ } bit; /*!< Structure used for bit access */
+ struct { // FRAC mode
+ uint16_t BAUD:13; /*!< bit: 0..12 Baud Rate Value */
+ uint16_t FP:3; /*!< bit: 13..15 Fractional Part */
+ } FRAC; /*!< Structure used for FRAC */
+ struct { // FRACFP mode
+ uint16_t BAUD:13; /*!< bit: 0..12 Baud Rate Value */
+ uint16_t FP:3; /*!< bit: 13..15 Fractional Part */
+ } FRACFP; /*!< Structure used for FRACFP */
+ struct { // USARTFP mode
+ uint16_t BAUD:16; /*!< bit: 0..15 Baud Rate Value */
+ } USARTFP; /*!< Structure used for USARTFP */
+ uint16_t reg; /*!< Type used for register access */
} SERCOM_USART_BAUD_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -587,10 +587,10 @@ typedef union {
/* -------- SERCOM_USART_RXPL : (SERCOM Offset: 0x0E) (R/W 8) USART USART Receive Pulse Length -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t RXPL:8; /*!< bit: 0.. 7 Receive Pulse Length */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t RXPL:8; /*!< bit: 0.. 7 Receive Pulse Length */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_USART_RXPL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -605,13 +605,13 @@ typedef union {
/* -------- SERCOM_I2CM_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) I2CM I2CM Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt Disable */
- uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt Disable */
- uint8_t :5; /*!< bit: 2.. 6 Reserved */
- uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt Disable */
+ uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt Disable */
+ uint8_t :5; /*!< bit: 2.. 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_I2CM_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -629,14 +629,14 @@ typedef union {
/* -------- SERCOM_I2CS_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) I2CS I2CS Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt Disable */
- uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt Disable */
- uint8_t DRDY:1; /*!< bit: 2 Data Interrupt Disable */
- uint8_t :4; /*!< bit: 3.. 6 Reserved */
- uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt Disable */
+ uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt Disable */
+ uint8_t DRDY:1; /*!< bit: 2 Data Interrupt Disable */
+ uint8_t :4; /*!< bit: 3.. 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_I2CS_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -656,15 +656,15 @@ typedef union {
/* -------- SERCOM_SPI_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) SPI SPI Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Disable */
- uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Disable */
- uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Disable */
- uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Disable */
- uint8_t :3; /*!< bit: 4.. 6 Reserved */
- uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Disable */
+ uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Disable */
+ uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Disable */
+ uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Disable */
+ uint8_t :3; /*!< bit: 4.. 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_SPI_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -686,17 +686,17 @@ typedef union {
/* -------- SERCOM_USART_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) USART USART Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Disable */
- uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Disable */
- uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Disable */
- uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Disable */
- uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt Disable */
- uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt Disable */
- uint8_t :1; /*!< bit: 6 Reserved */
- uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Disable */
+ uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Disable */
+ uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Disable */
+ uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Disable */
+ uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt Disable */
+ uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt Disable */
+ uint8_t :1; /*!< bit: 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_USART_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -722,13 +722,13 @@ typedef union {
/* -------- SERCOM_I2CM_INTENSET : (SERCOM Offset: 0x16) (R/W 8) I2CM I2CM Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt Enable */
- uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt Enable */
- uint8_t :5; /*!< bit: 2.. 6 Reserved */
- uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt Enable */
+ uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt Enable */
+ uint8_t :5; /*!< bit: 2.. 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_I2CM_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -746,14 +746,14 @@ typedef union {
/* -------- SERCOM_I2CS_INTENSET : (SERCOM Offset: 0x16) (R/W 8) I2CS I2CS Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt Enable */
- uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt Enable */
- uint8_t DRDY:1; /*!< bit: 2 Data Interrupt Enable */
- uint8_t :4; /*!< bit: 3.. 6 Reserved */
- uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt Enable */
+ uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt Enable */
+ uint8_t DRDY:1; /*!< bit: 2 Data Interrupt Enable */
+ uint8_t :4; /*!< bit: 3.. 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_I2CS_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -773,15 +773,15 @@ typedef union {
/* -------- SERCOM_SPI_INTENSET : (SERCOM Offset: 0x16) (R/W 8) SPI SPI Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */
- uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */
- uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */
- uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Enable */
- uint8_t :3; /*!< bit: 4.. 6 Reserved */
- uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */
+ uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */
+ uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */
+ uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Enable */
+ uint8_t :3; /*!< bit: 4.. 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_SPI_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -803,17 +803,17 @@ typedef union {
/* -------- SERCOM_USART_INTENSET : (SERCOM Offset: 0x16) (R/W 8) USART USART Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */
- uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */
- uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */
- uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Enable */
- uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt Enable */
- uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt Enable */
- uint8_t :1; /*!< bit: 6 Reserved */
- uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */
+ uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */
+ uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */
+ uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Enable */
+ uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt Enable */
+ uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt Enable */
+ uint8_t :1; /*!< bit: 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_USART_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -839,13 +839,13 @@ typedef union {
/* -------- SERCOM_I2CM_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) I2CM I2CM Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt */
- __I uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt */
- __I uint8_t :5; /*!< bit: 2.. 6 Reserved */
- __I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ __I uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt */
+ __I uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt */
+ __I uint8_t :5; /*!< bit: 2.. 6 Reserved */
+ __I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_I2CM_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -863,14 +863,14 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register
/* -------- SERCOM_I2CS_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) I2CS I2CS Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt */
- __I uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt */
- __I uint8_t DRDY:1; /*!< bit: 2 Data Interrupt */
- __I uint8_t :4; /*!< bit: 3.. 6 Reserved */
- __I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ __I uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt */
+ __I uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt */
+ __I uint8_t DRDY:1; /*!< bit: 2 Data Interrupt */
+ __I uint8_t :4; /*!< bit: 3.. 6 Reserved */
+ __I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_I2CS_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -890,15 +890,15 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register
/* -------- SERCOM_SPI_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) SPI SPI Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */
- __I uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */
- __I uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */
- __I uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Flag */
- __I uint8_t :3; /*!< bit: 4.. 6 Reserved */
- __I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ __I uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */
+ __I uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */
+ __I uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */
+ __I uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Flag */
+ __I uint8_t :3; /*!< bit: 4.. 6 Reserved */
+ __I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_SPI_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -920,17 +920,17 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register
/* -------- SERCOM_USART_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) USART USART Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */
- __I uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */
- __I uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */
- __I uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt */
- __I uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt */
- __I uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt */
- __I uint8_t :1; /*!< bit: 6 Reserved */
- __I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ __I uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */
+ __I uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */
+ __I uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */
+ __I uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt */
+ __I uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt */
+ __I uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt */
+ __I uint8_t :1; /*!< bit: 6 Reserved */
+ __I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_USART_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -956,20 +956,20 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register
/* -------- SERCOM_I2CM_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CM I2CM Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t BUSERR:1; /*!< bit: 0 Bus Error */
- uint16_t ARBLOST:1; /*!< bit: 1 Arbitration Lost */
- uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */
- uint16_t :1; /*!< bit: 3 Reserved */
- uint16_t BUSSTATE:2; /*!< bit: 4.. 5 Bus State */
- uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Timeout */
- uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */
- uint16_t MEXTTOUT:1; /*!< bit: 8 Master SCL Low Extend Timeout */
- uint16_t SEXTTOUT:1; /*!< bit: 9 Slave SCL Low Extend Timeout */
- uint16_t LENERR:1; /*!< bit: 10 Length Error */
- uint16_t :5; /*!< bit: 11..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t BUSERR:1; /*!< bit: 0 Bus Error */
+ uint16_t ARBLOST:1; /*!< bit: 1 Arbitration Lost */
+ uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */
+ uint16_t :1; /*!< bit: 3 Reserved */
+ uint16_t BUSSTATE:2; /*!< bit: 4.. 5 Bus State */
+ uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Timeout */
+ uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */
+ uint16_t MEXTTOUT:1; /*!< bit: 8 Master SCL Low Extend Timeout */
+ uint16_t SEXTTOUT:1; /*!< bit: 9 Slave SCL Low Extend Timeout */
+ uint16_t LENERR:1; /*!< bit: 10 Length Error */
+ uint16_t :5; /*!< bit: 11..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} SERCOM_I2CM_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1000,21 +1000,21 @@ typedef union {
/* -------- SERCOM_I2CS_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CS I2CS Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t BUSERR:1; /*!< bit: 0 Bus Error */
- uint16_t COLL:1; /*!< bit: 1 Transmit Collision */
- uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */
- uint16_t DIR:1; /*!< bit: 3 Read/Write Direction */
- uint16_t SR:1; /*!< bit: 4 Repeated Start */
- uint16_t :1; /*!< bit: 5 Reserved */
- uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Timeout */
- uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */
- uint16_t :1; /*!< bit: 8 Reserved */
- uint16_t SEXTTOUT:1; /*!< bit: 9 Slave SCL Low Extend Timeout */
- uint16_t HS:1; /*!< bit: 10 High Speed */
- uint16_t :5; /*!< bit: 11..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t BUSERR:1; /*!< bit: 0 Bus Error */
+ uint16_t COLL:1; /*!< bit: 1 Transmit Collision */
+ uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */
+ uint16_t DIR:1; /*!< bit: 3 Read/Write Direction */
+ uint16_t SR:1; /*!< bit: 4 Repeated Start */
+ uint16_t :1; /*!< bit: 5 Reserved */
+ uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Timeout */
+ uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */
+ uint16_t :1; /*!< bit: 8 Reserved */
+ uint16_t SEXTTOUT:1; /*!< bit: 9 Slave SCL Low Extend Timeout */
+ uint16_t HS:1; /*!< bit: 10 High Speed */
+ uint16_t :5; /*!< bit: 11..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} SERCOM_I2CS_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1044,12 +1044,12 @@ typedef union {
/* -------- SERCOM_SPI_STATUS : (SERCOM Offset: 0x1A) (R/W 16) SPI SPI Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t :2; /*!< bit: 0.. 1 Reserved */
- uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */
- uint16_t :13; /*!< bit: 3..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t :2; /*!< bit: 0.. 1 Reserved */
+ uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */
+ uint16_t :13; /*!< bit: 3..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} SERCOM_SPI_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1063,16 +1063,16 @@ typedef union {
/* -------- SERCOM_USART_STATUS : (SERCOM Offset: 0x1A) (R/W 16) USART USART Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t PERR:1; /*!< bit: 0 Parity Error */
- uint16_t FERR:1; /*!< bit: 1 Frame Error */
- uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */
- uint16_t CTS:1; /*!< bit: 3 Clear To Send */
- uint16_t ISF:1; /*!< bit: 4 Inconsistent Sync Field */
- uint16_t COLL:1; /*!< bit: 5 Collision Detected */
- uint16_t :10; /*!< bit: 6..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t PERR:1; /*!< bit: 0 Parity Error */
+ uint16_t FERR:1; /*!< bit: 1 Frame Error */
+ uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */
+ uint16_t CTS:1; /*!< bit: 3 Clear To Send */
+ uint16_t ISF:1; /*!< bit: 4 Inconsistent Sync Field */
+ uint16_t COLL:1; /*!< bit: 5 Collision Detected */
+ uint16_t :10; /*!< bit: 6..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} SERCOM_USART_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1096,13 +1096,13 @@ typedef union {
/* -------- SERCOM_I2CM_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) I2CM I2CM Syncbusy -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
- uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
- uint32_t SYSOP:1; /*!< bit: 2 System Operation Synchronization Busy */
- uint32_t :29; /*!< bit: 3..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
+ uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
+ uint32_t SYSOP:1; /*!< bit: 2 System Operation Synchronization Busy */
+ uint32_t :29; /*!< bit: 3..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SERCOM_I2CM_SYNCBUSY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1120,12 +1120,12 @@ typedef union {
/* -------- SERCOM_I2CS_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) I2CS I2CS Syncbusy -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
- uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
- uint32_t :30; /*!< bit: 2..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
+ uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
+ uint32_t :30; /*!< bit: 2..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SERCOM_I2CS_SYNCBUSY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1141,13 +1141,13 @@ typedef union {
/* -------- SERCOM_SPI_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) SPI SPI Syncbusy -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
- uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
- uint32_t CTRLB:1; /*!< bit: 2 CTRLB Synchronization Busy */
- uint32_t :29; /*!< bit: 3..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
+ uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
+ uint32_t CTRLB:1; /*!< bit: 2 CTRLB Synchronization Busy */
+ uint32_t :29; /*!< bit: 3..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SERCOM_SPI_SYNCBUSY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1165,13 +1165,13 @@ typedef union {
/* -------- SERCOM_USART_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) USART USART Syncbusy -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
- uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
- uint32_t CTRLB:1; /*!< bit: 2 CTRLB Synchronization Busy */
- uint32_t :29; /*!< bit: 3..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
+ uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
+ uint32_t CTRLB:1; /*!< bit: 2 CTRLB Synchronization Busy */
+ uint32_t :29; /*!< bit: 3..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SERCOM_USART_SYNCBUSY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1189,16 +1189,16 @@ typedef union {
/* -------- SERCOM_I2CM_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CM I2CM Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t ADDR:11; /*!< bit: 0..10 Address Value */
- uint32_t :2; /*!< bit: 11..12 Reserved */
- uint32_t LENEN:1; /*!< bit: 13 Length Enable */
- uint32_t HS:1; /*!< bit: 14 High Speed Mode */
- uint32_t TENBITEN:1; /*!< bit: 15 Ten Bit Addressing Enable */
- uint32_t LEN:8; /*!< bit: 16..23 Length */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t ADDR:11; /*!< bit: 0..10 Address Value */
+ uint32_t :2; /*!< bit: 11..12 Reserved */
+ uint32_t LENEN:1; /*!< bit: 13 Length Enable */
+ uint32_t HS:1; /*!< bit: 14 High Speed Mode */
+ uint32_t TENBITEN:1; /*!< bit: 15 Ten Bit Addressing Enable */
+ uint32_t LEN:8; /*!< bit: 16..23 Length */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SERCOM_I2CM_ADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1222,16 +1222,16 @@ typedef union {
/* -------- SERCOM_I2CS_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CS I2CS Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t GENCEN:1; /*!< bit: 0 General Call Address Enable */
- uint32_t ADDR:10; /*!< bit: 1..10 Address Value */
- uint32_t :4; /*!< bit: 11..14 Reserved */
- uint32_t TENBITEN:1; /*!< bit: 15 Ten Bit Addressing Enable */
- uint32_t :1; /*!< bit: 16 Reserved */
- uint32_t ADDRMASK:10; /*!< bit: 17..26 Address Mask */
- uint32_t :5; /*!< bit: 27..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t GENCEN:1; /*!< bit: 0 General Call Address Enable */
+ uint32_t ADDR:10; /*!< bit: 1..10 Address Value */
+ uint32_t :4; /*!< bit: 11..14 Reserved */
+ uint32_t TENBITEN:1; /*!< bit: 15 Ten Bit Addressing Enable */
+ uint32_t :1; /*!< bit: 16 Reserved */
+ uint32_t ADDRMASK:10; /*!< bit: 17..26 Address Mask */
+ uint32_t :5; /*!< bit: 27..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SERCOM_I2CS_ADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1253,13 +1253,13 @@ typedef union {
/* -------- SERCOM_SPI_ADDR : (SERCOM Offset: 0x24) (R/W 32) SPI SPI Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t ADDR:8; /*!< bit: 0.. 7 Address Value */
- uint32_t :8; /*!< bit: 8..15 Reserved */
- uint32_t ADDRMASK:8; /*!< bit: 16..23 Address Mask */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t ADDR:8; /*!< bit: 0.. 7 Address Value */
+ uint32_t :8; /*!< bit: 8..15 Reserved */
+ uint32_t ADDRMASK:8; /*!< bit: 16..23 Address Mask */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SERCOM_SPI_ADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1277,10 +1277,10 @@ typedef union {
/* -------- SERCOM_I2CM_DATA : (SERCOM Offset: 0x28) (R/W 8) I2CM I2CM Data -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DATA:8; /*!< bit: 0.. 7 Data Value */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DATA:8; /*!< bit: 0.. 7 Data Value */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_I2CM_DATA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1295,10 +1295,10 @@ typedef union {
/* -------- SERCOM_I2CS_DATA : (SERCOM Offset: 0x28) (R/W 8) I2CS I2CS Data -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DATA:8; /*!< bit: 0.. 7 Data Value */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DATA:8; /*!< bit: 0.. 7 Data Value */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_I2CS_DATA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1313,11 +1313,11 @@ typedef union {
/* -------- SERCOM_SPI_DATA : (SERCOM Offset: 0x28) (R/W 32) SPI SPI Data -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t DATA:9; /*!< bit: 0.. 8 Data Value */
- uint32_t :23; /*!< bit: 9..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t DATA:9; /*!< bit: 0.. 8 Data Value */
+ uint32_t :23; /*!< bit: 9..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SERCOM_SPI_DATA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1332,11 +1332,11 @@ typedef union {
/* -------- SERCOM_USART_DATA : (SERCOM Offset: 0x28) (R/W 16) USART USART Data -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t DATA:9; /*!< bit: 0.. 8 Data Value */
- uint16_t :7; /*!< bit: 9..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t DATA:9; /*!< bit: 0.. 8 Data Value */
+ uint16_t :7; /*!< bit: 9..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} SERCOM_USART_DATA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1351,11 +1351,11 @@ typedef union {
/* -------- SERCOM_I2CM_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) I2CM I2CM Debug Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_I2CM_DBGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1369,11 +1369,11 @@ typedef union {
/* -------- SERCOM_SPI_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) SPI SPI Debug Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_SPI_DBGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1387,11 +1387,11 @@ typedef union {
/* -------- SERCOM_USART_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) USART USART Debug Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SERCOM_USART_DBGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1405,101 +1405,101 @@ typedef union {
/** \brief SERCOM_I2CM hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* I2C Master Mode */
- __IO SERCOM_I2CM_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CM Control A */
- __IO SERCOM_I2CM_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CM Control B */
- RoReg8 Reserved1[0x4];
- __IO SERCOM_I2CM_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 32) I2CM Baud Rate */
- RoReg8 Reserved2[0x4];
- __IO SERCOM_I2CM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) I2CM Interrupt Enable Clear */
- RoReg8 Reserved3[0x1];
- __IO SERCOM_I2CM_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) I2CM Interrupt Enable Set */
- RoReg8 Reserved4[0x1];
- __IO SERCOM_I2CM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) I2CM Interrupt Flag Status and Clear */
- RoReg8 Reserved5[0x1];
- __IO SERCOM_I2CM_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) I2CM Status */
- __I SERCOM_I2CM_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) I2CM Syncbusy */
- RoReg8 Reserved6[0x4];
- __IO SERCOM_I2CM_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) I2CM Address */
- __IO SERCOM_I2CM_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 8) I2CM Data */
- RoReg8 Reserved7[0x7];
- __IO SERCOM_I2CM_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) I2CM Debug Control */
+ __IO SERCOM_I2CM_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CM Control A */
+ __IO SERCOM_I2CM_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CM Control B */
+ RoReg8 Reserved1[0x4];
+ __IO SERCOM_I2CM_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 32) I2CM Baud Rate */
+ RoReg8 Reserved2[0x4];
+ __IO SERCOM_I2CM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) I2CM Interrupt Enable Clear */
+ RoReg8 Reserved3[0x1];
+ __IO SERCOM_I2CM_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) I2CM Interrupt Enable Set */
+ RoReg8 Reserved4[0x1];
+ __IO SERCOM_I2CM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) I2CM Interrupt Flag Status and Clear */
+ RoReg8 Reserved5[0x1];
+ __IO SERCOM_I2CM_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) I2CM Status */
+ __I SERCOM_I2CM_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) I2CM Syncbusy */
+ RoReg8 Reserved6[0x4];
+ __IO SERCOM_I2CM_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) I2CM Address */
+ __IO SERCOM_I2CM_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 8) I2CM Data */
+ RoReg8 Reserved7[0x7];
+ __IO SERCOM_I2CM_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) I2CM Debug Control */
} SercomI2cm;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief SERCOM_I2CS hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* I2C Slave Mode */
- __IO SERCOM_I2CS_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CS Control A */
- __IO SERCOM_I2CS_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CS Control B */
- RoReg8 Reserved1[0xC];
- __IO SERCOM_I2CS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) I2CS Interrupt Enable Clear */
- RoReg8 Reserved2[0x1];
- __IO SERCOM_I2CS_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) I2CS Interrupt Enable Set */
- RoReg8 Reserved3[0x1];
- __IO SERCOM_I2CS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) I2CS Interrupt Flag Status and Clear */
- RoReg8 Reserved4[0x1];
- __IO SERCOM_I2CS_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) I2CS Status */
- __I SERCOM_I2CS_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) I2CS Syncbusy */
- RoReg8 Reserved5[0x4];
- __IO SERCOM_I2CS_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) I2CS Address */
- __IO SERCOM_I2CS_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 8) I2CS Data */
+ __IO SERCOM_I2CS_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CS Control A */
+ __IO SERCOM_I2CS_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CS Control B */
+ RoReg8 Reserved1[0xC];
+ __IO SERCOM_I2CS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) I2CS Interrupt Enable Clear */
+ RoReg8 Reserved2[0x1];
+ __IO SERCOM_I2CS_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) I2CS Interrupt Enable Set */
+ RoReg8 Reserved3[0x1];
+ __IO SERCOM_I2CS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) I2CS Interrupt Flag Status and Clear */
+ RoReg8 Reserved4[0x1];
+ __IO SERCOM_I2CS_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) I2CS Status */
+ __I SERCOM_I2CS_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) I2CS Syncbusy */
+ RoReg8 Reserved5[0x4];
+ __IO SERCOM_I2CS_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) I2CS Address */
+ __IO SERCOM_I2CS_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 8) I2CS Data */
} SercomI2cs;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief SERCOM_SPI hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* SPI Mode */
- __IO SERCOM_SPI_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) SPI Control A */
- __IO SERCOM_SPI_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) SPI Control B */
- RoReg8 Reserved1[0x4];
- __IO SERCOM_SPI_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 8) SPI Baud Rate */
- RoReg8 Reserved2[0x7];
- __IO SERCOM_SPI_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) SPI Interrupt Enable Clear */
- RoReg8 Reserved3[0x1];
- __IO SERCOM_SPI_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) SPI Interrupt Enable Set */
- RoReg8 Reserved4[0x1];
- __IO SERCOM_SPI_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) SPI Interrupt Flag Status and Clear */
- RoReg8 Reserved5[0x1];
- __IO SERCOM_SPI_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) SPI Status */
- __I SERCOM_SPI_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) SPI Syncbusy */
- RoReg8 Reserved6[0x4];
- __IO SERCOM_SPI_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) SPI Address */
- __IO SERCOM_SPI_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 32) SPI Data */
- RoReg8 Reserved7[0x4];
- __IO SERCOM_SPI_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) SPI Debug Control */
+ __IO SERCOM_SPI_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) SPI Control A */
+ __IO SERCOM_SPI_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) SPI Control B */
+ RoReg8 Reserved1[0x4];
+ __IO SERCOM_SPI_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 8) SPI Baud Rate */
+ RoReg8 Reserved2[0x7];
+ __IO SERCOM_SPI_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) SPI Interrupt Enable Clear */
+ RoReg8 Reserved3[0x1];
+ __IO SERCOM_SPI_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) SPI Interrupt Enable Set */
+ RoReg8 Reserved4[0x1];
+ __IO SERCOM_SPI_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) SPI Interrupt Flag Status and Clear */
+ RoReg8 Reserved5[0x1];
+ __IO SERCOM_SPI_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) SPI Status */
+ __I SERCOM_SPI_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) SPI Syncbusy */
+ RoReg8 Reserved6[0x4];
+ __IO SERCOM_SPI_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) SPI Address */
+ __IO SERCOM_SPI_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 32) SPI Data */
+ RoReg8 Reserved7[0x4];
+ __IO SERCOM_SPI_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) SPI Debug Control */
} SercomSpi;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief SERCOM_USART hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* USART Mode */
- __IO SERCOM_USART_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) USART Control A */
- __IO SERCOM_USART_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) USART Control B */
- RoReg8 Reserved1[0x4];
- __IO SERCOM_USART_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 16) USART Baud Rate */
- __IO SERCOM_USART_RXPL_Type RXPL; /**< \brief Offset: 0x0E (R/W 8) USART Receive Pulse Length */
- RoReg8 Reserved2[0x5];
- __IO SERCOM_USART_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) USART Interrupt Enable Clear */
- RoReg8 Reserved3[0x1];
- __IO SERCOM_USART_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) USART Interrupt Enable Set */
- RoReg8 Reserved4[0x1];
- __IO SERCOM_USART_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) USART Interrupt Flag Status and Clear */
- RoReg8 Reserved5[0x1];
- __IO SERCOM_USART_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) USART Status */
- __I SERCOM_USART_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) USART Syncbusy */
- RoReg8 Reserved6[0x8];
- __IO SERCOM_USART_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 16) USART Data */
- RoReg8 Reserved7[0x6];
- __IO SERCOM_USART_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) USART Debug Control */
+ __IO SERCOM_USART_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) USART Control A */
+ __IO SERCOM_USART_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) USART Control B */
+ RoReg8 Reserved1[0x4];
+ __IO SERCOM_USART_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 16) USART Baud Rate */
+ __IO SERCOM_USART_RXPL_Type RXPL; /**< \brief Offset: 0x0E (R/W 8) USART Receive Pulse Length */
+ RoReg8 Reserved2[0x5];
+ __IO SERCOM_USART_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) USART Interrupt Enable Clear */
+ RoReg8 Reserved3[0x1];
+ __IO SERCOM_USART_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) USART Interrupt Enable Set */
+ RoReg8 Reserved4[0x1];
+ __IO SERCOM_USART_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) USART Interrupt Flag Status and Clear */
+ RoReg8 Reserved5[0x1];
+ __IO SERCOM_USART_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) USART Status */
+ __I SERCOM_USART_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) USART Syncbusy */
+ RoReg8 Reserved6[0x8];
+ __IO SERCOM_USART_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 16) USART Data */
+ RoReg8 Reserved7[0x6];
+ __IO SERCOM_USART_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) USART Debug Control */
} SercomUsart;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- SercomI2cm I2CM; /**< \brief Offset: 0x00 I2C Master Mode */
- SercomI2cs I2CS; /**< \brief Offset: 0x00 I2C Slave Mode */
- SercomSpi SPI; /**< \brief Offset: 0x00 SPI Mode */
- SercomUsart USART; /**< \brief Offset: 0x00 USART Mode */
+ SercomI2cm I2CM; /**< \brief Offset: 0x00 I2C Master Mode */
+ SercomI2cs I2CS; /**< \brief Offset: 0x00 I2C Slave Mode */
+ SercomSpi SPI; /**< \brief Offset: 0x00 SPI Mode */
+ SercomUsart USART; /**< \brief Offset: 0x00 USART Mode */
} Sercom;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_sysctrl.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_sysctrl.h
index 92791c64811..52eb8bddd1c 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_sysctrl.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_sysctrl.h
@@ -56,26 +56,26 @@
/* -------- SYSCTRL_INTENCLR : (SYSCTRL Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready Interrupt Enable */
- uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready Interrupt Enable */
- uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready Interrupt Enable */
- uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready Interrupt Enable */
- uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready Interrupt Enable */
- uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds Interrupt Enable */
- uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine Interrupt Enable */
- uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse Interrupt Enable */
- uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped Interrupt Enable */
- uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready Interrupt Enable */
- uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection Interrupt Enable */
- uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready Interrupt Enable */
- uint32_t :3; /*!< bit: 12..14 Reserved */
- uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise Interrupt Enable */
- uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall Interrupt Enable */
- uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout Interrupt Enable */
- uint32_t :14; /*!< bit: 18..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready Interrupt Enable */
+ uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready Interrupt Enable */
+ uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready Interrupt Enable */
+ uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready Interrupt Enable */
+ uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready Interrupt Enable */
+ uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds Interrupt Enable */
+ uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine Interrupt Enable */
+ uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse Interrupt Enable */
+ uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped Interrupt Enable */
+ uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready Interrupt Enable */
+ uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection Interrupt Enable */
+ uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready Interrupt Enable */
+ uint32_t :3; /*!< bit: 12..14 Reserved */
+ uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise Interrupt Enable */
+ uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall Interrupt Enable */
+ uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout Interrupt Enable */
+ uint32_t :14; /*!< bit: 18..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SYSCTRL_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -117,26 +117,26 @@ typedef union {
/* -------- SYSCTRL_INTENSET : (SYSCTRL Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready Interrupt Enable */
- uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready Interrupt Enable */
- uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready Interrupt Enable */
- uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready Interrupt Enable */
- uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready Interrupt Enable */
- uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds Interrupt Enable */
- uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine Interrupt Enable */
- uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse Interrupt Enable */
- uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped Interrupt Enable */
- uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready Interrupt Enable */
- uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection Interrupt Enable */
- uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready Interrupt Enable */
- uint32_t :3; /*!< bit: 12..14 Reserved */
- uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise Interrupt Enable */
- uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall Interrupt Enable */
- uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout Interrupt Enable */
- uint32_t :14; /*!< bit: 18..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready Interrupt Enable */
+ uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready Interrupt Enable */
+ uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready Interrupt Enable */
+ uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready Interrupt Enable */
+ uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready Interrupt Enable */
+ uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds Interrupt Enable */
+ uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine Interrupt Enable */
+ uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse Interrupt Enable */
+ uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped Interrupt Enable */
+ uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready Interrupt Enable */
+ uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection Interrupt Enable */
+ uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready Interrupt Enable */
+ uint32_t :3; /*!< bit: 12..14 Reserved */
+ uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise Interrupt Enable */
+ uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall Interrupt Enable */
+ uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout Interrupt Enable */
+ uint32_t :14; /*!< bit: 18..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SYSCTRL_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -178,26 +178,26 @@ typedef union {
/* -------- SYSCTRL_INTFLAG : (SYSCTRL Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */
- __I uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready */
- __I uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready */
- __I uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready */
- __I uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready */
- __I uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds */
- __I uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine */
- __I uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse */
- __I uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped */
- __I uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready */
- __I uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection */
- __I uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready */
- __I uint32_t :3; /*!< bit: 12..14 Reserved */
- __I uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise */
- __I uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall */
- __I uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout */
- __I uint32_t :14; /*!< bit: 18..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ __I uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */
+ __I uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready */
+ __I uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready */
+ __I uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready */
+ __I uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready */
+ __I uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds */
+ __I uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine */
+ __I uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse */
+ __I uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped */
+ __I uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready */
+ __I uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection */
+ __I uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready */
+ __I uint32_t :3; /*!< bit: 12..14 Reserved */
+ __I uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise */
+ __I uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall */
+ __I uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout */
+ __I uint32_t :14; /*!< bit: 18..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SYSCTRL_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -239,26 +239,26 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register
/* -------- SYSCTRL_PCLKSR : (SYSCTRL Offset: 0x0C) (R/ 32) Power and Clocks Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */
- uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready */
- uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready */
- uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready */
- uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready */
- uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds */
- uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine */
- uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse */
- uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped */
- uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready */
- uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection */
- uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready */
- uint32_t :3; /*!< bit: 12..14 Reserved */
- uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise */
- uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall */
- uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout */
- uint32_t :14; /*!< bit: 18..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */
+ uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready */
+ uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready */
+ uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready */
+ uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready */
+ uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds */
+ uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine */
+ uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse */
+ uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped */
+ uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready */
+ uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection */
+ uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready */
+ uint32_t :3; /*!< bit: 12..14 Reserved */
+ uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise */
+ uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall */
+ uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout */
+ uint32_t :14; /*!< bit: 18..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SYSCTRL_PCLKSR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -300,18 +300,18 @@ typedef union {
/* -------- SYSCTRL_XOSC : (SYSCTRL Offset: 0x10) (R/W 16) External Multipurpose Crystal Oscillator (XOSC) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t :1; /*!< bit: 0 Reserved */
- uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
- uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */
- uint16_t :3; /*!< bit: 3.. 5 Reserved */
- uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
- uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
- uint16_t GAIN:3; /*!< bit: 8..10 Oscillator Gain */
- uint16_t AMPGC:1; /*!< bit: 11 Automatic Amplitude Gain Control */
- uint16_t STARTUP:4; /*!< bit: 12..15 Start-Up Time */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t :1; /*!< bit: 0 Reserved */
+ uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
+ uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */
+ uint16_t :3; /*!< bit: 3.. 5 Reserved */
+ uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
+ uint16_t GAIN:3; /*!< bit: 8..10 Oscillator Gain */
+ uint16_t AMPGC:1; /*!< bit: 11 Automatic Amplitude Gain Control */
+ uint16_t STARTUP:4; /*!< bit: 12..15 Start-Up Time */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} SYSCTRL_XOSC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -349,21 +349,21 @@ typedef union {
/* -------- SYSCTRL_XOSC32K : (SYSCTRL Offset: 0x14) (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t :1; /*!< bit: 0 Reserved */
- uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
- uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */
- uint16_t EN32K:1; /*!< bit: 3 32kHz Output Enable */
- uint16_t EN1K:1; /*!< bit: 4 1kHz Output Enable */
- uint16_t AAMPEN:1; /*!< bit: 5 Automatic Amplitude Control Enable */
- uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
- uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
- uint16_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */
- uint16_t :1; /*!< bit: 11 Reserved */
- uint16_t WRTLOCK:1; /*!< bit: 12 Write Lock */
- uint16_t :3; /*!< bit: 13..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t :1; /*!< bit: 0 Reserved */
+ uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
+ uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */
+ uint16_t EN32K:1; /*!< bit: 3 32kHz Output Enable */
+ uint16_t EN1K:1; /*!< bit: 4 1kHz Output Enable */
+ uint16_t AAMPEN:1; /*!< bit: 5 Automatic Amplitude Control Enable */
+ uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
+ uint16_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */
+ uint16_t :1; /*!< bit: 11 Reserved */
+ uint16_t WRTLOCK:1; /*!< bit: 12 Write Lock */
+ uint16_t :3; /*!< bit: 13..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} SYSCTRL_XOSC32K_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -394,22 +394,22 @@ typedef union {
/* -------- SYSCTRL_OSC32K : (SYSCTRL Offset: 0x18) (R/W 32) 32kHz Internal Oscillator (OSC32K) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t :1; /*!< bit: 0 Reserved */
- uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
- uint32_t EN32K:1; /*!< bit: 2 32kHz Output Enable */
- uint32_t EN1K:1; /*!< bit: 3 1kHz Output Enable */
- uint32_t :2; /*!< bit: 4.. 5 Reserved */
- uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
- uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
- uint32_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */
- uint32_t :1; /*!< bit: 11 Reserved */
- uint32_t WRTLOCK:1; /*!< bit: 12 Write Lock */
- uint32_t :3; /*!< bit: 13..15 Reserved */
- uint32_t CALIB:7; /*!< bit: 16..22 Oscillator Calibration */
- uint32_t :9; /*!< bit: 23..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
+ uint32_t EN32K:1; /*!< bit: 2 32kHz Output Enable */
+ uint32_t EN1K:1; /*!< bit: 3 1kHz Output Enable */
+ uint32_t :2; /*!< bit: 4.. 5 Reserved */
+ uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
+ uint32_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */
+ uint32_t :1; /*!< bit: 11 Reserved */
+ uint32_t WRTLOCK:1; /*!< bit: 12 Write Lock */
+ uint32_t :3; /*!< bit: 13..15 Reserved */
+ uint32_t CALIB:7; /*!< bit: 16..22 Oscillator Calibration */
+ uint32_t :9; /*!< bit: 23..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SYSCTRL_OSC32K_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -439,12 +439,12 @@ typedef union {
/* -------- SYSCTRL_OSCULP32K : (SYSCTRL Offset: 0x1C) (R/W 8) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t CALIB:5; /*!< bit: 0.. 4 Oscillator Calibration */
- uint8_t :2; /*!< bit: 5.. 6 Reserved */
- uint8_t WRTLOCK:1; /*!< bit: 7 Write Lock */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t CALIB:5; /*!< bit: 0.. 4 Oscillator Calibration */
+ uint8_t :2; /*!< bit: 5.. 6 Reserved */
+ uint8_t WRTLOCK:1; /*!< bit: 7 Write Lock */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SYSCTRL_OSCULP32K_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -461,19 +461,19 @@ typedef union {
/* -------- SYSCTRL_OSC8M : (SYSCTRL Offset: 0x20) (R/W 32) 8MHz Internal Oscillator (OSC8M) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t :1; /*!< bit: 0 Reserved */
- uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
- uint32_t :4; /*!< bit: 2.. 5 Reserved */
- uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
- uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
- uint32_t PRESC:2; /*!< bit: 8.. 9 Oscillator Prescaler */
- uint32_t :6; /*!< bit: 10..15 Reserved */
- uint32_t CALIB:12; /*!< bit: 16..27 Oscillator Calibration */
- uint32_t :2; /*!< bit: 28..29 Reserved */
- uint32_t FRANGE:2; /*!< bit: 30..31 Oscillator Frequency Range */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
+ uint32_t :4; /*!< bit: 2.. 5 Reserved */
+ uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
+ uint32_t PRESC:2; /*!< bit: 8.. 9 Oscillator Prescaler */
+ uint32_t :6; /*!< bit: 10..15 Reserved */
+ uint32_t CALIB:12; /*!< bit: 16..27 Oscillator Calibration */
+ uint32_t :2; /*!< bit: 28..29 Reserved */
+ uint32_t FRANGE:2; /*!< bit: 30..31 Oscillator Frequency Range */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SYSCTRL_OSC8M_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -516,22 +516,22 @@ typedef union {
/* -------- SYSCTRL_DFLLCTRL : (SYSCTRL Offset: 0x24) (R/W 16) DFLL48M Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t :1; /*!< bit: 0 Reserved */
- uint16_t ENABLE:1; /*!< bit: 1 DFLL Enable */
- uint16_t MODE:1; /*!< bit: 2 Operating Mode Selection */
- uint16_t STABLE:1; /*!< bit: 3 Stable DFLL Frequency */
- uint16_t LLAW:1; /*!< bit: 4 Lose Lock After Wake */
- uint16_t USBCRM:1; /*!< bit: 5 USB Clock Recovery Mode */
- uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
- uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
- uint16_t CCDIS:1; /*!< bit: 8 Chill Cycle Disable */
- uint16_t QLDIS:1; /*!< bit: 9 Quick Lock Disable */
- uint16_t BPLCKC:1; /*!< bit: 10 Bypass Coarse Lock */
- uint16_t WAITLOCK:1; /*!< bit: 11 Wait Lock */
- uint16_t :4; /*!< bit: 12..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t :1; /*!< bit: 0 Reserved */
+ uint16_t ENABLE:1; /*!< bit: 1 DFLL Enable */
+ uint16_t MODE:1; /*!< bit: 2 Operating Mode Selection */
+ uint16_t STABLE:1; /*!< bit: 3 Stable DFLL Frequency */
+ uint16_t LLAW:1; /*!< bit: 4 Lose Lock After Wake */
+ uint16_t USBCRM:1; /*!< bit: 5 USB Clock Recovery Mode */
+ uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
+ uint16_t CCDIS:1; /*!< bit: 8 Chill Cycle Disable */
+ uint16_t QLDIS:1; /*!< bit: 9 Quick Lock Disable */
+ uint16_t BPLCKC:1; /*!< bit: 10 Bypass Coarse Lock */
+ uint16_t WAITLOCK:1; /*!< bit: 11 Wait Lock */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} SYSCTRL_DFLLCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -565,12 +565,12 @@ typedef union {
/* -------- SYSCTRL_DFLLVAL : (SYSCTRL Offset: 0x28) (R/W 32) DFLL48M Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t FINE:10; /*!< bit: 0.. 9 Fine Value */
- uint32_t COARSE:6; /*!< bit: 10..15 Coarse Value */
- uint32_t DIFF:16; /*!< bit: 16..31 Multiplication Ratio Difference */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t FINE:10; /*!< bit: 0.. 9 Fine Value */
+ uint32_t COARSE:6; /*!< bit: 10..15 Coarse Value */
+ uint32_t DIFF:16; /*!< bit: 16..31 Multiplication Ratio Difference */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SYSCTRL_DFLLVAL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -591,12 +591,12 @@ typedef union {
/* -------- SYSCTRL_DFLLMUL : (SYSCTRL Offset: 0x2C) (R/W 32) DFLL48M Multiplier -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t MUL:16; /*!< bit: 0..15 DFLL Multiply Factor */
- uint32_t FSTEP:10; /*!< bit: 16..25 Fine Maximum Step */
- uint32_t CSTEP:6; /*!< bit: 26..31 Coarse Maximum Step */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t MUL:16; /*!< bit: 0..15 DFLL Multiply Factor */
+ uint32_t FSTEP:10; /*!< bit: 16..25 Fine Maximum Step */
+ uint32_t CSTEP:6; /*!< bit: 26..31 Coarse Maximum Step */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SYSCTRL_DFLLMUL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -617,11 +617,11 @@ typedef union {
/* -------- SYSCTRL_DFLLSYNC : (SYSCTRL Offset: 0x30) (R/W 8) DFLL48M Synchronization -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t :7; /*!< bit: 0.. 6 Reserved */
- uint8_t READREQ:1; /*!< bit: 7 Read Request */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t :7; /*!< bit: 0.. 6 Reserved */
+ uint8_t READREQ:1; /*!< bit: 7 Read Request */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SYSCTRL_DFLLSYNC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -635,22 +635,22 @@ typedef union {
/* -------- SYSCTRL_BOD33 : (SYSCTRL Offset: 0x34) (R/W 32) 3.3V Brown-Out Detector (BOD33) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t :1; /*!< bit: 0 Reserved */
- uint32_t ENABLE:1; /*!< bit: 1 Enable */
- uint32_t HYST:1; /*!< bit: 2 Hysteresis */
- uint32_t ACTION:2; /*!< bit: 3.. 4 BOD33 Action */
- uint32_t :1; /*!< bit: 5 Reserved */
- uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
- uint32_t :1; /*!< bit: 7 Reserved */
- uint32_t MODE:1; /*!< bit: 8 Operation Mode */
- uint32_t CEN:1; /*!< bit: 9 Clock Enable */
- uint32_t :2; /*!< bit: 10..11 Reserved */
- uint32_t PSEL:4; /*!< bit: 12..15 Prescaler Select */
- uint32_t LEVEL:6; /*!< bit: 16..21 BOD33 Threshold Level */
- uint32_t :10; /*!< bit: 22..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */
+ uint32_t HYST:1; /*!< bit: 2 Hysteresis */
+ uint32_t ACTION:2; /*!< bit: 3.. 4 BOD33 Action */
+ uint32_t :1; /*!< bit: 5 Reserved */
+ uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint32_t :1; /*!< bit: 7 Reserved */
+ uint32_t MODE:1; /*!< bit: 8 Operation Mode */
+ uint32_t CEN:1; /*!< bit: 9 Clock Enable */
+ uint32_t :2; /*!< bit: 10..11 Reserved */
+ uint32_t PSEL:4; /*!< bit: 12..15 Prescaler Select */
+ uint32_t LEVEL:6; /*!< bit: 16..21 BOD33 Threshold Level */
+ uint32_t :10; /*!< bit: 22..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SYSCTRL_BOD33_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -719,14 +719,14 @@ typedef union {
/* -------- SYSCTRL_VREG : (SYSCTRL Offset: 0x3C) (R/W 16) Voltage Regulator System (VREG) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t :6; /*!< bit: 0.. 5 Reserved */
- uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
- uint16_t :6; /*!< bit: 7..12 Reserved */
- uint16_t FORCELDO:1; /*!< bit: 13 Force LDO Voltage Regulator */
- uint16_t :2; /*!< bit: 14..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t :6; /*!< bit: 0.. 5 Reserved */
+ uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint16_t :6; /*!< bit: 7..12 Reserved */
+ uint16_t FORCELDO:1; /*!< bit: 13 Force LDO Voltage Regulator */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} SYSCTRL_VREG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -742,15 +742,15 @@ typedef union {
/* -------- SYSCTRL_VREF : (SYSCTRL Offset: 0x40) (R/W 32) Voltage References System (VREF) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t :1; /*!< bit: 0 Reserved */
- uint32_t TSEN:1; /*!< bit: 1 Temperature Sensor Enable */
- uint32_t BGOUTEN:1; /*!< bit: 2 Bandgap Output Enable */
- uint32_t :13; /*!< bit: 3..15 Reserved */
- uint32_t CALIB:11; /*!< bit: 16..26 Bandgap Voltage Generator Calibration */
- uint32_t :5; /*!< bit: 27..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t TSEN:1; /*!< bit: 1 Temperature Sensor Enable */
+ uint32_t BGOUTEN:1; /*!< bit: 2 Bandgap Output Enable */
+ uint32_t :13; /*!< bit: 3..15 Reserved */
+ uint32_t CALIB:11; /*!< bit: 16..26 Bandgap Voltage Generator Calibration */
+ uint32_t :5; /*!< bit: 27..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SYSCTRL_VREF_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -769,14 +769,14 @@ typedef union {
/* -------- SYSCTRL_DPLLCTRLA : (SYSCTRL Offset: 0x44) (R/W 8) DPLL Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t :1; /*!< bit: 0 Reserved */
- uint8_t ENABLE:1; /*!< bit: 1 DPLL Enable */
- uint8_t :4; /*!< bit: 2.. 5 Reserved */
- uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
- uint8_t ONDEMAND:1; /*!< bit: 7 On Demand Clock Activation */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t :1; /*!< bit: 0 Reserved */
+ uint8_t ENABLE:1; /*!< bit: 1 DPLL Enable */
+ uint8_t :4; /*!< bit: 2.. 5 Reserved */
+ uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint8_t ONDEMAND:1; /*!< bit: 7 On Demand Clock Activation */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SYSCTRL_DPLLCTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -794,13 +794,13 @@ typedef union {
/* -------- SYSCTRL_DPLLRATIO : (SYSCTRL Offset: 0x48) (R/W 32) DPLL Ratio Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t LDR:12; /*!< bit: 0..11 Loop Divider Ratio */
- uint32_t :4; /*!< bit: 12..15 Reserved */
- uint32_t LDRFRAC:4; /*!< bit: 16..19 Loop Divider Ratio Fractional Part */
- uint32_t :12; /*!< bit: 20..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t LDR:12; /*!< bit: 0..11 Loop Divider Ratio */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t LDRFRAC:4; /*!< bit: 16..19 Loop Divider Ratio Fractional Part */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SYSCTRL_DPLLRATIO_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -818,20 +818,20 @@ typedef union {
/* -------- SYSCTRL_DPLLCTRLB : (SYSCTRL Offset: 0x4C) (R/W 32) DPLL Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t FILTER:2; /*!< bit: 0.. 1 Proportional Integral Filter Selection */
- uint32_t LPEN:1; /*!< bit: 2 Low-Power Enable */
- uint32_t WUF:1; /*!< bit: 3 Wake Up Fast */
- uint32_t REFCLK:2; /*!< bit: 4.. 5 Reference Clock Selection */
- uint32_t :2; /*!< bit: 6.. 7 Reserved */
- uint32_t LTIME:3; /*!< bit: 8..10 Lock Time */
- uint32_t :1; /*!< bit: 11 Reserved */
- uint32_t LBYPASS:1; /*!< bit: 12 Lock Bypass */
- uint32_t :3; /*!< bit: 13..15 Reserved */
- uint32_t DIV:11; /*!< bit: 16..26 Clock Divider */
- uint32_t :5; /*!< bit: 27..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t FILTER:2; /*!< bit: 0.. 1 Proportional Integral Filter Selection */
+ uint32_t LPEN:1; /*!< bit: 2 Low-Power Enable */
+ uint32_t WUF:1; /*!< bit: 3 Wake Up Fast */
+ uint32_t REFCLK:2; /*!< bit: 4.. 5 Reference Clock Selection */
+ uint32_t :2; /*!< bit: 6.. 7 Reserved */
+ uint32_t LTIME:3; /*!< bit: 8..10 Lock Time */
+ uint32_t :1; /*!< bit: 11 Reserved */
+ uint32_t LBYPASS:1; /*!< bit: 12 Lock Bypass */
+ uint32_t :3; /*!< bit: 13..15 Reserved */
+ uint32_t DIV:11; /*!< bit: 16..26 Clock Divider */
+ uint32_t :5; /*!< bit: 27..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} SYSCTRL_DPLLCTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -885,14 +885,14 @@ typedef union {
/* -------- SYSCTRL_DPLLSTATUS : (SYSCTRL Offset: 0x50) (R/ 8) DPLL Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t LOCK:1; /*!< bit: 0 DPLL Lock Status */
- uint8_t CLKRDY:1; /*!< bit: 1 Output Clock Ready */
- uint8_t ENABLE:1; /*!< bit: 2 DPLL Enable */
- uint8_t DIV:1; /*!< bit: 3 Divider Enable */
- uint8_t :4; /*!< bit: 4.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t LOCK:1; /*!< bit: 0 DPLL Lock Status */
+ uint8_t CLKRDY:1; /*!< bit: 1 Output Clock Ready */
+ uint8_t ENABLE:1; /*!< bit: 2 DPLL Enable */
+ uint8_t DIV:1; /*!< bit: 3 Divider Enable */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} SYSCTRL_DPLLSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -912,34 +912,34 @@ typedef union {
/** \brief SYSCTRL hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO SYSCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Clear */
- __IO SYSCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set */
- __IO SYSCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */
- __I SYSCTRL_PCLKSR_Type PCLKSR; /**< \brief Offset: 0x0C (R/ 32) Power and Clocks Status */
- __IO SYSCTRL_XOSC_Type XOSC; /**< \brief Offset: 0x10 (R/W 16) External Multipurpose Crystal Oscillator (XOSC) Control */
- RoReg8 Reserved1[0x2];
- __IO SYSCTRL_XOSC32K_Type XOSC32K; /**< \brief Offset: 0x14 (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control */
- RoReg8 Reserved2[0x2];
- __IO SYSCTRL_OSC32K_Type OSC32K; /**< \brief Offset: 0x18 (R/W 32) 32kHz Internal Oscillator (OSC32K) Control */
- __IO SYSCTRL_OSCULP32K_Type OSCULP32K; /**< \brief Offset: 0x1C (R/W 8) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
- RoReg8 Reserved3[0x3];
- __IO SYSCTRL_OSC8M_Type OSC8M; /**< \brief Offset: 0x20 (R/W 32) 8MHz Internal Oscillator (OSC8M) Control */
- __IO SYSCTRL_DFLLCTRL_Type DFLLCTRL; /**< \brief Offset: 0x24 (R/W 16) DFLL48M Control */
- RoReg8 Reserved4[0x2];
- __IO SYSCTRL_DFLLVAL_Type DFLLVAL; /**< \brief Offset: 0x28 (R/W 32) DFLL48M Value */
- __IO SYSCTRL_DFLLMUL_Type DFLLMUL; /**< \brief Offset: 0x2C (R/W 32) DFLL48M Multiplier */
- __IO SYSCTRL_DFLLSYNC_Type DFLLSYNC; /**< \brief Offset: 0x30 (R/W 8) DFLL48M Synchronization */
- RoReg8 Reserved5[0x3];
- __IO SYSCTRL_BOD33_Type BOD33; /**< \brief Offset: 0x34 (R/W 32) 3.3V Brown-Out Detector (BOD33) Control */
- RoReg8 Reserved6[0x4];
- __IO SYSCTRL_VREG_Type VREG; /**< \brief Offset: 0x3C (R/W 16) Voltage Regulator System (VREG) Control */
- RoReg8 Reserved7[0x2];
- __IO SYSCTRL_VREF_Type VREF; /**< \brief Offset: 0x40 (R/W 32) Voltage References System (VREF) Control */
- __IO SYSCTRL_DPLLCTRLA_Type DPLLCTRLA; /**< \brief Offset: 0x44 (R/W 8) DPLL Control A */
- RoReg8 Reserved8[0x3];
- __IO SYSCTRL_DPLLRATIO_Type DPLLRATIO; /**< \brief Offset: 0x48 (R/W 32) DPLL Ratio Control */
- __IO SYSCTRL_DPLLCTRLB_Type DPLLCTRLB; /**< \brief Offset: 0x4C (R/W 32) DPLL Control B */
- __I SYSCTRL_DPLLSTATUS_Type DPLLSTATUS; /**< \brief Offset: 0x50 (R/ 8) DPLL Status */
+ __IO SYSCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Clear */
+ __IO SYSCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set */
+ __IO SYSCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */
+ __I SYSCTRL_PCLKSR_Type PCLKSR; /**< \brief Offset: 0x0C (R/ 32) Power and Clocks Status */
+ __IO SYSCTRL_XOSC_Type XOSC; /**< \brief Offset: 0x10 (R/W 16) External Multipurpose Crystal Oscillator (XOSC) Control */
+ RoReg8 Reserved1[0x2];
+ __IO SYSCTRL_XOSC32K_Type XOSC32K; /**< \brief Offset: 0x14 (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control */
+ RoReg8 Reserved2[0x2];
+ __IO SYSCTRL_OSC32K_Type OSC32K; /**< \brief Offset: 0x18 (R/W 32) 32kHz Internal Oscillator (OSC32K) Control */
+ __IO SYSCTRL_OSCULP32K_Type OSCULP32K; /**< \brief Offset: 0x1C (R/W 8) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
+ RoReg8 Reserved3[0x3];
+ __IO SYSCTRL_OSC8M_Type OSC8M; /**< \brief Offset: 0x20 (R/W 32) 8MHz Internal Oscillator (OSC8M) Control */
+ __IO SYSCTRL_DFLLCTRL_Type DFLLCTRL; /**< \brief Offset: 0x24 (R/W 16) DFLL48M Control */
+ RoReg8 Reserved4[0x2];
+ __IO SYSCTRL_DFLLVAL_Type DFLLVAL; /**< \brief Offset: 0x28 (R/W 32) DFLL48M Value */
+ __IO SYSCTRL_DFLLMUL_Type DFLLMUL; /**< \brief Offset: 0x2C (R/W 32) DFLL48M Multiplier */
+ __IO SYSCTRL_DFLLSYNC_Type DFLLSYNC; /**< \brief Offset: 0x30 (R/W 8) DFLL48M Synchronization */
+ RoReg8 Reserved5[0x3];
+ __IO SYSCTRL_BOD33_Type BOD33; /**< \brief Offset: 0x34 (R/W 32) 3.3V Brown-Out Detector (BOD33) Control */
+ RoReg8 Reserved6[0x4];
+ __IO SYSCTRL_VREG_Type VREG; /**< \brief Offset: 0x3C (R/W 16) Voltage Regulator System (VREG) Control */
+ RoReg8 Reserved7[0x2];
+ __IO SYSCTRL_VREF_Type VREF; /**< \brief Offset: 0x40 (R/W 32) Voltage References System (VREF) Control */
+ __IO SYSCTRL_DPLLCTRLA_Type DPLLCTRLA; /**< \brief Offset: 0x44 (R/W 8) DPLL Control A */
+ RoReg8 Reserved8[0x3];
+ __IO SYSCTRL_DPLLRATIO_Type DPLLRATIO; /**< \brief Offset: 0x48 (R/W 32) DPLL Ratio Control */
+ __IO SYSCTRL_DPLLCTRLB_Type DPLLCTRLB; /**< \brief Offset: 0x4C (R/W 32) DPLL Control B */
+ __I SYSCTRL_DPLLSTATUS_Type DPLLSTATUS; /**< \brief Offset: 0x50 (R/ 8) DPLL Status */
} Sysctrl;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_tc.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_tc.h
index e2e3700f953..44f2f706e29 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_tc.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_tc.h
@@ -56,19 +56,19 @@
/* -------- TC_CTRLA : (TC Offset: 0x00) (R/W 16) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t SWRST:1; /*!< bit: 0 Software Reset */
- uint16_t ENABLE:1; /*!< bit: 1 Enable */
- uint16_t MODE:2; /*!< bit: 2.. 3 TC Mode */
- uint16_t :1; /*!< bit: 4 Reserved */
- uint16_t WAVEGEN:2; /*!< bit: 5.. 6 Waveform Generation Operation */
- uint16_t :1; /*!< bit: 7 Reserved */
- uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler */
- uint16_t RUNSTDBY:1; /*!< bit: 11 Run in Standby */
- uint16_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization */
- uint16_t :2; /*!< bit: 14..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint16_t ENABLE:1; /*!< bit: 1 Enable */
+ uint16_t MODE:2; /*!< bit: 2.. 3 TC Mode */
+ uint16_t :1; /*!< bit: 4 Reserved */
+ uint16_t WAVEGEN:2; /*!< bit: 5.. 6 Waveform Generation Operation */
+ uint16_t :1; /*!< bit: 7 Reserved */
+ uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler */
+ uint16_t RUNSTDBY:1; /*!< bit: 11 Run in Standby */
+ uint16_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} TC_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -134,13 +134,13 @@ typedef union {
/* -------- TC_READREQ : (TC Offset: 0x02) (R/W 16) Read Request -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t ADDR:5; /*!< bit: 0.. 4 Address */
- uint16_t :9; /*!< bit: 5..13 Reserved */
- uint16_t RCONT:1; /*!< bit: 14 Read Continuously */
- uint16_t RREQ:1; /*!< bit: 15 Read Request */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t ADDR:5; /*!< bit: 0.. 4 Address */
+ uint16_t :9; /*!< bit: 5..13 Reserved */
+ uint16_t RCONT:1; /*!< bit: 14 Read Continuously */
+ uint16_t RREQ:1; /*!< bit: 15 Read Request */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} TC_READREQ_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -159,14 +159,14 @@ typedef union {
/* -------- TC_CTRLBCLR : (TC Offset: 0x04) (R/W 8) Control B Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DIR:1; /*!< bit: 0 Counter Direction */
- uint8_t :1; /*!< bit: 1 Reserved */
- uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
- uint8_t :3; /*!< bit: 3.. 5 Reserved */
- uint8_t CMD:2; /*!< bit: 6.. 7 Command */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DIR:1; /*!< bit: 0 Counter Direction */
+ uint8_t :1; /*!< bit: 1 Reserved */
+ uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
+ uint8_t :3; /*!< bit: 3.. 5 Reserved */
+ uint8_t CMD:2; /*!< bit: 6.. 7 Command */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} TC_CTRLBCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -191,14 +191,14 @@ typedef union {
/* -------- TC_CTRLBSET : (TC Offset: 0x05) (R/W 8) Control B Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DIR:1; /*!< bit: 0 Counter Direction */
- uint8_t :1; /*!< bit: 1 Reserved */
- uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
- uint8_t :3; /*!< bit: 3.. 5 Reserved */
- uint8_t CMD:2; /*!< bit: 6.. 7 Command */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DIR:1; /*!< bit: 0 Counter Direction */
+ uint8_t :1; /*!< bit: 1 Reserved */
+ uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
+ uint8_t :3; /*!< bit: 3.. 5 Reserved */
+ uint8_t CMD:2; /*!< bit: 6.. 7 Command */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} TC_CTRLBSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -223,21 +223,21 @@ typedef union {
/* -------- TC_CTRLC : (TC Offset: 0x06) (R/W 8) Control C -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t INVEN0:1; /*!< bit: 0 Output Waveform 0 Invert Enable */
- uint8_t INVEN1:1; /*!< bit: 1 Output Waveform 1 Invert Enable */
- uint8_t :2; /*!< bit: 2.. 3 Reserved */
- uint8_t CPTEN0:1; /*!< bit: 4 Capture Channel 0 Enable */
- uint8_t CPTEN1:1; /*!< bit: 5 Capture Channel 1 Enable */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t INVEN:2; /*!< bit: 0.. 1 Output Waveform x Invert Enable */
- uint8_t :2; /*!< bit: 2.. 3 Reserved */
- uint8_t CPTEN:2; /*!< bit: 4.. 5 Capture Channel x Enable */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t INVEN0:1; /*!< bit: 0 Output Waveform 0 Invert Enable */
+ uint8_t INVEN1:1; /*!< bit: 1 Output Waveform 1 Invert Enable */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t CPTEN0:1; /*!< bit: 4 Capture Channel 0 Enable */
+ uint8_t CPTEN1:1; /*!< bit: 5 Capture Channel 1 Enable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t INVEN:2; /*!< bit: 0.. 1 Output Waveform x Invert Enable */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t CPTEN:2; /*!< bit: 4.. 5 Capture Channel x Enable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} TC_CTRLC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -263,11 +263,11 @@ typedef union {
/* -------- TC_DBGCTRL : (TC Offset: 0x08) (R/W 8) Debug Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DBGRUN:1; /*!< bit: 0 Debug Run Mode */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DBGRUN:1; /*!< bit: 0 Debug Run Mode */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} TC_DBGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -281,24 +281,24 @@ typedef union {
/* -------- TC_EVCTRL : (TC Offset: 0x0A) (R/W 16) Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t EVACT:3; /*!< bit: 0.. 2 Event Action */
- uint16_t :1; /*!< bit: 3 Reserved */
- uint16_t TCINV:1; /*!< bit: 4 TC Inverted Event Input */
- uint16_t TCEI:1; /*!< bit: 5 TC Event Input */
- uint16_t :2; /*!< bit: 6.. 7 Reserved */
- uint16_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Event Output Enable */
- uint16_t :3; /*!< bit: 9..11 Reserved */
- uint16_t MCEO0:1; /*!< bit: 12 Match or Capture Channel 0 Event Output Enable */
- uint16_t MCEO1:1; /*!< bit: 13 Match or Capture Channel 1 Event Output Enable */
- uint16_t :2; /*!< bit: 14..15 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint16_t :12; /*!< bit: 0..11 Reserved */
- uint16_t MCEO:2; /*!< bit: 12..13 Match or Capture Channel x Event Output Enable */
- uint16_t :2; /*!< bit: 14..15 Reserved */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t EVACT:3; /*!< bit: 0.. 2 Event Action */
+ uint16_t :1; /*!< bit: 3 Reserved */
+ uint16_t TCINV:1; /*!< bit: 4 TC Inverted Event Input */
+ uint16_t TCEI:1; /*!< bit: 5 TC Event Input */
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ uint16_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Event Output Enable */
+ uint16_t :3; /*!< bit: 9..11 Reserved */
+ uint16_t MCEO0:1; /*!< bit: 12 Match or Capture Channel 0 Event Output Enable */
+ uint16_t MCEO1:1; /*!< bit: 13 Match or Capture Channel 1 Event Output Enable */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t :12; /*!< bit: 0..11 Reserved */
+ uint16_t MCEO:2; /*!< bit: 12..13 Match or Capture Channel x Event Output Enable */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
} TC_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -338,21 +338,21 @@ typedef union {
/* -------- TC_INTENCLR : (TC Offset: 0x0C) (R/W 8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
- uint8_t ERR:1; /*!< bit: 1 Error Interrupt Enable */
- uint8_t :1; /*!< bit: 2 Reserved */
- uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
- uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 Interrupt Enable */
- uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 Interrupt Enable */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t :4; /*!< bit: 0.. 3 Reserved */
- uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x Interrupt Enable */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
+ uint8_t ERR:1; /*!< bit: 1 Error Interrupt Enable */
+ uint8_t :1; /*!< bit: 2 Reserved */
+ uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
+ uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 Interrupt Enable */
+ uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 Interrupt Enable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t :4; /*!< bit: 0.. 3 Reserved */
+ uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x Interrupt Enable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} TC_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -377,21 +377,21 @@ typedef union {
/* -------- TC_INTENSET : (TC Offset: 0x0D) (R/W 8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
- uint8_t ERR:1; /*!< bit: 1 Error Interrupt Enable */
- uint8_t :1; /*!< bit: 2 Reserved */
- uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
- uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 Interrupt Enable */
- uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 Interrupt Enable */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t :4; /*!< bit: 0.. 3 Reserved */
- uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x Interrupt Enable */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
+ uint8_t ERR:1; /*!< bit: 1 Error Interrupt Enable */
+ uint8_t :1; /*!< bit: 2 Reserved */
+ uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
+ uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 Interrupt Enable */
+ uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 Interrupt Enable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t :4; /*!< bit: 0.. 3 Reserved */
+ uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x Interrupt Enable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} TC_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -416,21 +416,21 @@ typedef union {
/* -------- TC_INTFLAG : (TC Offset: 0x0E) (R/W 8) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint8_t OVF:1; /*!< bit: 0 Overflow */
- __I uint8_t ERR:1; /*!< bit: 1 Error */
- __I uint8_t :1; /*!< bit: 2 Reserved */
- __I uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */
- __I uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 */
- __I uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 */
- __I uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- __I uint8_t :4; /*!< bit: 0.. 3 Reserved */
- __I uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x */
- __I uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ __I uint8_t OVF:1; /*!< bit: 0 Overflow */
+ __I uint8_t ERR:1; /*!< bit: 1 Error */
+ __I uint8_t :1; /*!< bit: 2 Reserved */
+ __I uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */
+ __I uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 */
+ __I uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 */
+ __I uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ __I uint8_t :4; /*!< bit: 0.. 3 Reserved */
+ __I uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x */
+ __I uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} TC_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -455,14 +455,14 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register
/* -------- TC_STATUS : (TC Offset: 0x0F) (R/ 8) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t :3; /*!< bit: 0.. 2 Reserved */
- uint8_t STOP:1; /*!< bit: 3 Stop */
- uint8_t SLAVE:1; /*!< bit: 4 Slave */
- uint8_t :2; /*!< bit: 5.. 6 Reserved */
- uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t :3; /*!< bit: 0.. 2 Reserved */
+ uint8_t STOP:1; /*!< bit: 3 Stop */
+ uint8_t SLAVE:1; /*!< bit: 4 Slave */
+ uint8_t :2; /*!< bit: 5.. 6 Reserved */
+ uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} TC_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -480,10 +480,10 @@ typedef union {
/* -------- TC_COUNT16_COUNT : (TC Offset: 0x10) (R/W 16) COUNT16 COUNT16 Counter Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t COUNT:16; /*!< bit: 0..15 Count Value */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t COUNT:16; /*!< bit: 0..15 Count Value */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} TC_COUNT16_COUNT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -498,10 +498,10 @@ typedef union {
/* -------- TC_COUNT32_COUNT : (TC Offset: 0x10) (R/W 32) COUNT32 COUNT32 Counter Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t COUNT:32; /*!< bit: 0..31 Count Value */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t COUNT:32; /*!< bit: 0..31 Count Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} TC_COUNT32_COUNT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -516,10 +516,10 @@ typedef union {
/* -------- TC_COUNT8_COUNT : (TC Offset: 0x10) (R/W 8) COUNT8 COUNT8 Counter Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t COUNT:8; /*!< bit: 0.. 7 Counter Value */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t COUNT:8; /*!< bit: 0.. 7 Counter Value */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} TC_COUNT8_COUNT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -534,10 +534,10 @@ typedef union {
/* -------- TC_COUNT8_PER : (TC Offset: 0x14) (R/W 8) COUNT8 COUNT8 Period Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t PER:8; /*!< bit: 0.. 7 Period Value */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t PER:8; /*!< bit: 0.. 7 Period Value */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} TC_COUNT8_PER_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -552,10 +552,10 @@ typedef union {
/* -------- TC_COUNT16_CC : (TC Offset: 0x18) (R/W 16) COUNT16 COUNT16 Compare/Capture -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t CC:16; /*!< bit: 0..15 Compare/Capture Value */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t CC:16; /*!< bit: 0..15 Compare/Capture Value */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} TC_COUNT16_CC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -570,10 +570,10 @@ typedef union {
/* -------- TC_COUNT32_CC : (TC Offset: 0x18) (R/W 32) COUNT32 COUNT32 Compare/Capture -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t CC:32; /*!< bit: 0..31 Compare/Capture Value */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t CC:32; /*!< bit: 0..31 Compare/Capture Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} TC_COUNT32_CC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -588,10 +588,10 @@ typedef union {
/* -------- TC_COUNT8_CC : (TC Offset: 0x18) (R/W 8) COUNT8 COUNT8 Compare/Capture -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t CC:8; /*!< bit: 0.. 7 Compare/Capture Value */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t CC:8; /*!< bit: 0.. 7 Compare/Capture Value */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} TC_COUNT8_CC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -606,76 +606,76 @@ typedef union {
/** \brief TC_COUNT8 hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* 8-bit Counter Mode */
- __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
- __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
- __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
- __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
- __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */
- RoReg8 Reserved1[0x1];
- __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */
- RoReg8 Reserved2[0x1];
- __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */
- __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
- __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */
- __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */
- __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */
- __IO TC_COUNT8_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 8) COUNT8 Counter Value */
- RoReg8 Reserved3[0x3];
- __IO TC_COUNT8_PER_Type PER; /**< \brief Offset: 0x14 (R/W 8) COUNT8 Period Value */
- RoReg8 Reserved4[0x3];
- __IO TC_COUNT8_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 8) COUNT8 Compare/Capture */
+ __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
+ __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
+ __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
+ __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
+ __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */
+ RoReg8 Reserved1[0x1];
+ __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */
+ RoReg8 Reserved2[0x1];
+ __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */
+ __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
+ __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */
+ __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */
+ __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */
+ __IO TC_COUNT8_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 8) COUNT8 Counter Value */
+ RoReg8 Reserved3[0x3];
+ __IO TC_COUNT8_PER_Type PER; /**< \brief Offset: 0x14 (R/W 8) COUNT8 Period Value */
+ RoReg8 Reserved4[0x3];
+ __IO TC_COUNT8_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 8) COUNT8 Compare/Capture */
} TcCount8;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief TC_COUNT16 hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* 16-bit Counter Mode */
- __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
- __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
- __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
- __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
- __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */
- RoReg8 Reserved1[0x1];
- __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */
- RoReg8 Reserved2[0x1];
- __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */
- __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
- __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */
- __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */
- __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */
- __IO TC_COUNT16_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 16) COUNT16 Counter Value */
- RoReg8 Reserved3[0x6];
- __IO TC_COUNT16_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 16) COUNT16 Compare/Capture */
+ __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
+ __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
+ __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
+ __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
+ __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */
+ RoReg8 Reserved1[0x1];
+ __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */
+ RoReg8 Reserved2[0x1];
+ __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */
+ __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
+ __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */
+ __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */
+ __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */
+ __IO TC_COUNT16_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 16) COUNT16 Counter Value */
+ RoReg8 Reserved3[0x6];
+ __IO TC_COUNT16_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 16) COUNT16 Compare/Capture */
} TcCount16;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief TC_COUNT32 hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* 32-bit Counter Mode */
- __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
- __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
- __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
- __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
- __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */
- RoReg8 Reserved1[0x1];
- __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */
- RoReg8 Reserved2[0x1];
- __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */
- __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
- __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */
- __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */
- __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */
- __IO TC_COUNT32_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 32) COUNT32 Counter Value */
- RoReg8 Reserved3[0x4];
- __IO TC_COUNT32_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 32) COUNT32 Compare/Capture */
+ __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
+ __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
+ __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
+ __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
+ __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */
+ RoReg8 Reserved1[0x1];
+ __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */
+ RoReg8 Reserved2[0x1];
+ __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */
+ __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
+ __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */
+ __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */
+ __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */
+ __IO TC_COUNT32_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 32) COUNT32 Counter Value */
+ RoReg8 Reserved3[0x4];
+ __IO TC_COUNT32_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 32) COUNT32 Compare/Capture */
} TcCount32;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- TcCount8 COUNT8; /**< \brief Offset: 0x00 8-bit Counter Mode */
- TcCount16 COUNT16; /**< \brief Offset: 0x00 16-bit Counter Mode */
- TcCount32 COUNT32; /**< \brief Offset: 0x00 32-bit Counter Mode */
+ TcCount8 COUNT8; /**< \brief Offset: 0x00 8-bit Counter Mode */
+ TcCount16 COUNT16; /**< \brief Offset: 0x00 16-bit Counter Mode */
+ TcCount32 COUNT32; /**< \brief Offset: 0x00 32-bit Counter Mode */
} Tc;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_tcc.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_tcc.h
index 2a8ecd3c575..82747024970 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_tcc.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_tcc.h
@@ -56,29 +56,29 @@
/* -------- TCC_CTRLA : (TCC Offset: 0x00) (R/W 32) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Software Reset */
- uint32_t ENABLE:1; /*!< bit: 1 Enable */
- uint32_t :3; /*!< bit: 2.. 4 Reserved */
- uint32_t RESOLUTION:2; /*!< bit: 5.. 6 Enhanced Resolution */
- uint32_t :1; /*!< bit: 7 Reserved */
- uint32_t PRESCALER:3; /*!< bit: 8..10 Prescaler */
- uint32_t RUNSTDBY:1; /*!< bit: 11 Run in Standby */
- uint32_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization Selection */
- uint32_t ALOCK:1; /*!< bit: 14 Auto Lock */
- uint32_t :9; /*!< bit: 15..23 Reserved */
- uint32_t CPTEN0:1; /*!< bit: 24 Capture Channel 0 Enable */
- uint32_t CPTEN1:1; /*!< bit: 25 Capture Channel 1 Enable */
- uint32_t CPTEN2:1; /*!< bit: 26 Capture Channel 2 Enable */
- uint32_t CPTEN3:1; /*!< bit: 27 Capture Channel 3 Enable */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :24; /*!< bit: 0..23 Reserved */
- uint32_t CPTEN:4; /*!< bit: 24..27 Capture Channel x Enable */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */
+ uint32_t :3; /*!< bit: 2.. 4 Reserved */
+ uint32_t RESOLUTION:2; /*!< bit: 5.. 6 Enhanced Resolution */
+ uint32_t :1; /*!< bit: 7 Reserved */
+ uint32_t PRESCALER:3; /*!< bit: 8..10 Prescaler */
+ uint32_t RUNSTDBY:1; /*!< bit: 11 Run in Standby */
+ uint32_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization Selection */
+ uint32_t ALOCK:1; /*!< bit: 14 Auto Lock */
+ uint32_t :9; /*!< bit: 15..23 Reserved */
+ uint32_t CPTEN0:1; /*!< bit: 24 Capture Channel 0 Enable */
+ uint32_t CPTEN1:1; /*!< bit: 25 Capture Channel 1 Enable */
+ uint32_t CPTEN2:1; /*!< bit: 26 Capture Channel 2 Enable */
+ uint32_t CPTEN3:1; /*!< bit: 27 Capture Channel 3 Enable */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :24; /*!< bit: 0..23 Reserved */
+ uint32_t CPTEN:4; /*!< bit: 24..27 Capture Channel x Enable */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -148,14 +148,14 @@ typedef union {
/* -------- TCC_CTRLBCLR : (TCC Offset: 0x04) (R/W 8) Control B Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DIR:1; /*!< bit: 0 Counter Direction */
- uint8_t LUPD:1; /*!< bit: 1 Lock Update */
- uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
- uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */
- uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DIR:1; /*!< bit: 0 Counter Direction */
+ uint8_t LUPD:1; /*!< bit: 1 Lock Update */
+ uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
+ uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */
+ uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} TCC_CTRLBCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -197,14 +197,14 @@ typedef union {
/* -------- TCC_CTRLBSET : (TCC Offset: 0x05) (R/W 8) Control B Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DIR:1; /*!< bit: 0 Counter Direction */
- uint8_t LUPD:1; /*!< bit: 1 Lock Update */
- uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
- uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */
- uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DIR:1; /*!< bit: 0 Counter Direction */
+ uint8_t LUPD:1; /*!< bit: 1 Lock Update */
+ uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
+ uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */
+ uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} TCC_CTRLBSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -246,37 +246,37 @@ typedef union {
/* -------- TCC_SYNCBUSY : (TCC Offset: 0x08) (R/ 32) Synchronization Busy -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SWRST:1; /*!< bit: 0 Swrst Busy */
- uint32_t ENABLE:1; /*!< bit: 1 Enable Busy */
- uint32_t CTRLB:1; /*!< bit: 2 Ctrlb Busy */
- uint32_t STATUS:1; /*!< bit: 3 Status Busy */
- uint32_t COUNT:1; /*!< bit: 4 Count Busy */
- uint32_t PATT:1; /*!< bit: 5 Pattern Busy */
- uint32_t WAVE:1; /*!< bit: 6 Wave Busy */
- uint32_t PER:1; /*!< bit: 7 Period busy */
- uint32_t CC0:1; /*!< bit: 8 Compare Channel 0 Busy */
- uint32_t CC1:1; /*!< bit: 9 Compare Channel 1 Busy */
- uint32_t CC2:1; /*!< bit: 10 Compare Channel 2 Busy */
- uint32_t CC3:1; /*!< bit: 11 Compare Channel 3 Busy */
- uint32_t :4; /*!< bit: 12..15 Reserved */
- uint32_t PATTB:1; /*!< bit: 16 Pattern Buffer Busy */
- uint32_t WAVEB:1; /*!< bit: 17 Wave Buffer Busy */
- uint32_t PERB:1; /*!< bit: 18 Period Buffer Busy */
- uint32_t CCB0:1; /*!< bit: 19 Compare Channel Buffer 0 Busy */
- uint32_t CCB1:1; /*!< bit: 20 Compare Channel Buffer 1 Busy */
- uint32_t CCB2:1; /*!< bit: 21 Compare Channel Buffer 2 Busy */
- uint32_t CCB3:1; /*!< bit: 22 Compare Channel Buffer 3 Busy */
- uint32_t :9; /*!< bit: 23..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :8; /*!< bit: 0.. 7 Reserved */
- uint32_t CC:4; /*!< bit: 8..11 Compare Channel x Busy */
- uint32_t :7; /*!< bit: 12..18 Reserved */
- uint32_t CCB:4; /*!< bit: 19..22 Compare Channel Buffer x Busy */
- uint32_t :9; /*!< bit: 23..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Swrst Busy */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable Busy */
+ uint32_t CTRLB:1; /*!< bit: 2 Ctrlb Busy */
+ uint32_t STATUS:1; /*!< bit: 3 Status Busy */
+ uint32_t COUNT:1; /*!< bit: 4 Count Busy */
+ uint32_t PATT:1; /*!< bit: 5 Pattern Busy */
+ uint32_t WAVE:1; /*!< bit: 6 Wave Busy */
+ uint32_t PER:1; /*!< bit: 7 Period busy */
+ uint32_t CC0:1; /*!< bit: 8 Compare Channel 0 Busy */
+ uint32_t CC1:1; /*!< bit: 9 Compare Channel 1 Busy */
+ uint32_t CC2:1; /*!< bit: 10 Compare Channel 2 Busy */
+ uint32_t CC3:1; /*!< bit: 11 Compare Channel 3 Busy */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t PATTB:1; /*!< bit: 16 Pattern Buffer Busy */
+ uint32_t WAVEB:1; /*!< bit: 17 Wave Buffer Busy */
+ uint32_t PERB:1; /*!< bit: 18 Period Buffer Busy */
+ uint32_t CCB0:1; /*!< bit: 19 Compare Channel Buffer 0 Busy */
+ uint32_t CCB1:1; /*!< bit: 20 Compare Channel Buffer 1 Busy */
+ uint32_t CCB2:1; /*!< bit: 21 Compare Channel Buffer 2 Busy */
+ uint32_t CCB3:1; /*!< bit: 22 Compare Channel Buffer 3 Busy */
+ uint32_t :9; /*!< bit: 23..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :8; /*!< bit: 0.. 7 Reserved */
+ uint32_t CC:4; /*!< bit: 8..11 Compare Channel x Busy */
+ uint32_t :7; /*!< bit: 12..18 Reserved */
+ uint32_t CCB:4; /*!< bit: 19..22 Compare Channel Buffer x Busy */
+ uint32_t :9; /*!< bit: 23..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_SYNCBUSY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -332,22 +332,22 @@ typedef union {
/* -------- TCC_FCTRLA : (TCC Offset: 0x0C) (R/W 32) Recoverable Fault A Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SRC:2; /*!< bit: 0.. 1 Fault A Source */
- uint32_t :1; /*!< bit: 2 Reserved */
- uint32_t KEEP:1; /*!< bit: 3 Fault A Keeper */
- uint32_t QUAL:1; /*!< bit: 4 Fault A Qualification */
- uint32_t BLANK:2; /*!< bit: 5.. 6 Fault A Blanking Mode */
- uint32_t RESTART:1; /*!< bit: 7 Fault A Restart */
- uint32_t HALT:2; /*!< bit: 8.. 9 Fault A Halt Mode */
- uint32_t CHSEL:2; /*!< bit: 10..11 Fault A Capture Channel */
- uint32_t CAPTURE:3; /*!< bit: 12..14 Fault A Capture Action */
- uint32_t :1; /*!< bit: 15 Reserved */
- uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault A Blanking Time */
- uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault A Filter Value */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SRC:2; /*!< bit: 0.. 1 Fault A Source */
+ uint32_t :1; /*!< bit: 2 Reserved */
+ uint32_t KEEP:1; /*!< bit: 3 Fault A Keeper */
+ uint32_t QUAL:1; /*!< bit: 4 Fault A Qualification */
+ uint32_t BLANK:2; /*!< bit: 5.. 6 Fault A Blanking Mode */
+ uint32_t RESTART:1; /*!< bit: 7 Fault A Restart */
+ uint32_t HALT:2; /*!< bit: 8.. 9 Fault A Halt Mode */
+ uint32_t CHSEL:2; /*!< bit: 10..11 Fault A Capture Channel */
+ uint32_t CAPTURE:3; /*!< bit: 12..14 Fault A Capture Action */
+ uint32_t :1; /*!< bit: 15 Reserved */
+ uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault A Blanking Time */
+ uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault A Filter Value */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_FCTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -432,22 +432,22 @@ typedef union {
/* -------- TCC_FCTRLB : (TCC Offset: 0x10) (R/W 32) Recoverable Fault B Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t SRC:2; /*!< bit: 0.. 1 Fault B Source */
- uint32_t :1; /*!< bit: 2 Reserved */
- uint32_t KEEP:1; /*!< bit: 3 Fault B Keeper */
- uint32_t QUAL:1; /*!< bit: 4 Fault B Qualification */
- uint32_t BLANK:2; /*!< bit: 5.. 6 Fault B Blanking Mode */
- uint32_t RESTART:1; /*!< bit: 7 Fault B Restart */
- uint32_t HALT:2; /*!< bit: 8.. 9 Fault B Halt Mode */
- uint32_t CHSEL:2; /*!< bit: 10..11 Fault B Capture Channel */
- uint32_t CAPTURE:3; /*!< bit: 12..14 Fault B Capture Action */
- uint32_t :1; /*!< bit: 15 Reserved */
- uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault B Blanking Time */
- uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault B Filter Value */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t SRC:2; /*!< bit: 0.. 1 Fault B Source */
+ uint32_t :1; /*!< bit: 2 Reserved */
+ uint32_t KEEP:1; /*!< bit: 3 Fault B Keeper */
+ uint32_t QUAL:1; /*!< bit: 4 Fault B Qualification */
+ uint32_t BLANK:2; /*!< bit: 5.. 6 Fault B Blanking Mode */
+ uint32_t RESTART:1; /*!< bit: 7 Fault B Restart */
+ uint32_t HALT:2; /*!< bit: 8.. 9 Fault B Halt Mode */
+ uint32_t CHSEL:2; /*!< bit: 10..11 Fault B Capture Channel */
+ uint32_t CAPTURE:3; /*!< bit: 12..14 Fault B Capture Action */
+ uint32_t :1; /*!< bit: 15 Reserved */
+ uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault B Blanking Time */
+ uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault B Filter Value */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_FCTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -532,23 +532,23 @@ typedef union {
/* -------- TCC_WEXCTRL : (TCC Offset: 0x14) (R/W 32) Waveform Extension Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t OTMX:2; /*!< bit: 0.. 1 Output Matrix */
- uint32_t :6; /*!< bit: 2.. 7 Reserved */
- uint32_t DTIEN0:1; /*!< bit: 8 Dead-time Insertion Generator 0 Enable */
- uint32_t DTIEN1:1; /*!< bit: 9 Dead-time Insertion Generator 1 Enable */
- uint32_t DTIEN2:1; /*!< bit: 10 Dead-time Insertion Generator 2 Enable */
- uint32_t DTIEN3:1; /*!< bit: 11 Dead-time Insertion Generator 3 Enable */
- uint32_t :4; /*!< bit: 12..15 Reserved */
- uint32_t DTLS:8; /*!< bit: 16..23 Dead-time Low Side Outputs Value */
- uint32_t DTHS:8; /*!< bit: 24..31 Dead-time High Side Outputs Value */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :8; /*!< bit: 0.. 7 Reserved */
- uint32_t DTIEN:4; /*!< bit: 8..11 Dead-time Insertion Generator x Enable */
- uint32_t :20; /*!< bit: 12..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t OTMX:2; /*!< bit: 0.. 1 Output Matrix */
+ uint32_t :6; /*!< bit: 2.. 7 Reserved */
+ uint32_t DTIEN0:1; /*!< bit: 8 Dead-time Insertion Generator 0 Enable */
+ uint32_t DTIEN1:1; /*!< bit: 9 Dead-time Insertion Generator 1 Enable */
+ uint32_t DTIEN2:1; /*!< bit: 10 Dead-time Insertion Generator 2 Enable */
+ uint32_t DTIEN3:1; /*!< bit: 11 Dead-time Insertion Generator 3 Enable */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t DTLS:8; /*!< bit: 16..23 Dead-time Low Side Outputs Value */
+ uint32_t DTHS:8; /*!< bit: 24..31 Dead-time High Side Outputs Value */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :8; /*!< bit: 0.. 7 Reserved */
+ uint32_t DTIEN:4; /*!< bit: 8..11 Dead-time Insertion Generator x Enable */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_WEXCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -580,41 +580,41 @@ typedef union {
/* -------- TCC_DRVCTRL : (TCC Offset: 0x18) (R/W 32) Driver Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t NRE0:1; /*!< bit: 0 Non-Recoverable State 0 Output Enable */
- uint32_t NRE1:1; /*!< bit: 1 Non-Recoverable State 1 Output Enable */
- uint32_t NRE2:1; /*!< bit: 2 Non-Recoverable State 2 Output Enable */
- uint32_t NRE3:1; /*!< bit: 3 Non-Recoverable State 3 Output Enable */
- uint32_t NRE4:1; /*!< bit: 4 Non-Recoverable State 4 Output Enable */
- uint32_t NRE5:1; /*!< bit: 5 Non-Recoverable State 5 Output Enable */
- uint32_t NRE6:1; /*!< bit: 6 Non-Recoverable State 6 Output Enable */
- uint32_t NRE7:1; /*!< bit: 7 Non-Recoverable State 7 Output Enable */
- uint32_t NRV0:1; /*!< bit: 8 Non-Recoverable State 0 Output Value */
- uint32_t NRV1:1; /*!< bit: 9 Non-Recoverable State 1 Output Value */
- uint32_t NRV2:1; /*!< bit: 10 Non-Recoverable State 2 Output Value */
- uint32_t NRV3:1; /*!< bit: 11 Non-Recoverable State 3 Output Value */
- uint32_t NRV4:1; /*!< bit: 12 Non-Recoverable State 4 Output Value */
- uint32_t NRV5:1; /*!< bit: 13 Non-Recoverable State 5 Output Value */
- uint32_t NRV6:1; /*!< bit: 14 Non-Recoverable State 6 Output Value */
- uint32_t NRV7:1; /*!< bit: 15 Non-Recoverable State 7 Output Value */
- uint32_t INVEN0:1; /*!< bit: 16 Output Waveform 0 Inversion */
- uint32_t INVEN1:1; /*!< bit: 17 Output Waveform 1 Inversion */
- uint32_t INVEN2:1; /*!< bit: 18 Output Waveform 2 Inversion */
- uint32_t INVEN3:1; /*!< bit: 19 Output Waveform 3 Inversion */
- uint32_t INVEN4:1; /*!< bit: 20 Output Waveform 4 Inversion */
- uint32_t INVEN5:1; /*!< bit: 21 Output Waveform 5 Inversion */
- uint32_t INVEN6:1; /*!< bit: 22 Output Waveform 6 Inversion */
- uint32_t INVEN7:1; /*!< bit: 23 Output Waveform 7 Inversion */
- uint32_t FILTERVAL0:4; /*!< bit: 24..27 Non-Recoverable Fault Input 0 Filter Value */
- uint32_t FILTERVAL1:4; /*!< bit: 28..31 Non-Recoverable Fault Input 1 Filter Value */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t NRE:8; /*!< bit: 0.. 7 Non-Recoverable State x Output Enable */
- uint32_t NRV:8; /*!< bit: 8..15 Non-Recoverable State x Output Value */
- uint32_t INVEN:8; /*!< bit: 16..23 Output Waveform x Inversion */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t NRE0:1; /*!< bit: 0 Non-Recoverable State 0 Output Enable */
+ uint32_t NRE1:1; /*!< bit: 1 Non-Recoverable State 1 Output Enable */
+ uint32_t NRE2:1; /*!< bit: 2 Non-Recoverable State 2 Output Enable */
+ uint32_t NRE3:1; /*!< bit: 3 Non-Recoverable State 3 Output Enable */
+ uint32_t NRE4:1; /*!< bit: 4 Non-Recoverable State 4 Output Enable */
+ uint32_t NRE5:1; /*!< bit: 5 Non-Recoverable State 5 Output Enable */
+ uint32_t NRE6:1; /*!< bit: 6 Non-Recoverable State 6 Output Enable */
+ uint32_t NRE7:1; /*!< bit: 7 Non-Recoverable State 7 Output Enable */
+ uint32_t NRV0:1; /*!< bit: 8 Non-Recoverable State 0 Output Value */
+ uint32_t NRV1:1; /*!< bit: 9 Non-Recoverable State 1 Output Value */
+ uint32_t NRV2:1; /*!< bit: 10 Non-Recoverable State 2 Output Value */
+ uint32_t NRV3:1; /*!< bit: 11 Non-Recoverable State 3 Output Value */
+ uint32_t NRV4:1; /*!< bit: 12 Non-Recoverable State 4 Output Value */
+ uint32_t NRV5:1; /*!< bit: 13 Non-Recoverable State 5 Output Value */
+ uint32_t NRV6:1; /*!< bit: 14 Non-Recoverable State 6 Output Value */
+ uint32_t NRV7:1; /*!< bit: 15 Non-Recoverable State 7 Output Value */
+ uint32_t INVEN0:1; /*!< bit: 16 Output Waveform 0 Inversion */
+ uint32_t INVEN1:1; /*!< bit: 17 Output Waveform 1 Inversion */
+ uint32_t INVEN2:1; /*!< bit: 18 Output Waveform 2 Inversion */
+ uint32_t INVEN3:1; /*!< bit: 19 Output Waveform 3 Inversion */
+ uint32_t INVEN4:1; /*!< bit: 20 Output Waveform 4 Inversion */
+ uint32_t INVEN5:1; /*!< bit: 21 Output Waveform 5 Inversion */
+ uint32_t INVEN6:1; /*!< bit: 22 Output Waveform 6 Inversion */
+ uint32_t INVEN7:1; /*!< bit: 23 Output Waveform 7 Inversion */
+ uint32_t FILTERVAL0:4; /*!< bit: 24..27 Non-Recoverable Fault Input 0 Filter Value */
+ uint32_t FILTERVAL1:4; /*!< bit: 28..31 Non-Recoverable Fault Input 1 Filter Value */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t NRE:8; /*!< bit: 0.. 7 Non-Recoverable State x Output Enable */
+ uint32_t NRV:8; /*!< bit: 8..15 Non-Recoverable State x Output Value */
+ uint32_t INVEN:8; /*!< bit: 16..23 Output Waveform x Inversion */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_DRVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -689,13 +689,13 @@ typedef union {
/* -------- TCC_DBGCTRL : (TCC Offset: 0x1E) (R/W 8) Debug Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DBGRUN:1; /*!< bit: 0 Debug Running Mode */
- uint8_t :1; /*!< bit: 1 Reserved */
- uint8_t FDDBD:1; /*!< bit: 2 Fault Detection on Debug Break Detection */
- uint8_t :5; /*!< bit: 3.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DBGRUN:1; /*!< bit: 0 Debug Running Mode */
+ uint8_t :1; /*!< bit: 1 Reserved */
+ uint8_t FDDBD:1; /*!< bit: 2 Fault Detection on Debug Break Detection */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} TCC_DBGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -711,39 +711,39 @@ typedef union {
/* -------- TCC_EVCTRL : (TCC Offset: 0x20) (R/W 32) Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t EVACT0:3; /*!< bit: 0.. 2 Timer/counter Input Event0 Action */
- uint32_t EVACT1:3; /*!< bit: 3.. 5 Timer/counter Input Event1 Action */
- uint32_t CNTSEL:2; /*!< bit: 6.. 7 Timer/counter Output Event Mode */
- uint32_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Output Event Enable */
- uint32_t TRGEO:1; /*!< bit: 9 Retrigger Output Event Enable */
- uint32_t CNTEO:1; /*!< bit: 10 Timer/counter Output Event Enable */
- uint32_t :1; /*!< bit: 11 Reserved */
- uint32_t TCINV0:1; /*!< bit: 12 Inverted Event 0 Input Enable */
- uint32_t TCINV1:1; /*!< bit: 13 Inverted Event 1 Input Enable */
- uint32_t TCEI0:1; /*!< bit: 14 Timer/counter Event 0 Input Enable */
- uint32_t TCEI1:1; /*!< bit: 15 Timer/counter Event 1 Input Enable */
- uint32_t MCEI0:1; /*!< bit: 16 Match or Capture Channel 0 Event Input Enable */
- uint32_t MCEI1:1; /*!< bit: 17 Match or Capture Channel 1 Event Input Enable */
- uint32_t MCEI2:1; /*!< bit: 18 Match or Capture Channel 2 Event Input Enable */
- uint32_t MCEI3:1; /*!< bit: 19 Match or Capture Channel 3 Event Input Enable */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t MCEO0:1; /*!< bit: 24 Match or Capture Channel 0 Event Output Enable */
- uint32_t MCEO1:1; /*!< bit: 25 Match or Capture Channel 1 Event Output Enable */
- uint32_t MCEO2:1; /*!< bit: 26 Match or Capture Channel 2 Event Output Enable */
- uint32_t MCEO3:1; /*!< bit: 27 Match or Capture Channel 3 Event Output Enable */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :12; /*!< bit: 0..11 Reserved */
- uint32_t TCINV:2; /*!< bit: 12..13 Inverted Event x Input Enable */
- uint32_t TCEI:2; /*!< bit: 14..15 Timer/counter Event x Input Enable */
- uint32_t MCEI:4; /*!< bit: 16..19 Match or Capture Channel x Event Input Enable */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t MCEO:4; /*!< bit: 24..27 Match or Capture Channel x Event Output Enable */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t EVACT0:3; /*!< bit: 0.. 2 Timer/counter Input Event0 Action */
+ uint32_t EVACT1:3; /*!< bit: 3.. 5 Timer/counter Input Event1 Action */
+ uint32_t CNTSEL:2; /*!< bit: 6.. 7 Timer/counter Output Event Mode */
+ uint32_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Output Event Enable */
+ uint32_t TRGEO:1; /*!< bit: 9 Retrigger Output Event Enable */
+ uint32_t CNTEO:1; /*!< bit: 10 Timer/counter Output Event Enable */
+ uint32_t :1; /*!< bit: 11 Reserved */
+ uint32_t TCINV0:1; /*!< bit: 12 Inverted Event 0 Input Enable */
+ uint32_t TCINV1:1; /*!< bit: 13 Inverted Event 1 Input Enable */
+ uint32_t TCEI0:1; /*!< bit: 14 Timer/counter Event 0 Input Enable */
+ uint32_t TCEI1:1; /*!< bit: 15 Timer/counter Event 1 Input Enable */
+ uint32_t MCEI0:1; /*!< bit: 16 Match or Capture Channel 0 Event Input Enable */
+ uint32_t MCEI1:1; /*!< bit: 17 Match or Capture Channel 1 Event Input Enable */
+ uint32_t MCEI2:1; /*!< bit: 18 Match or Capture Channel 2 Event Input Enable */
+ uint32_t MCEI3:1; /*!< bit: 19 Match or Capture Channel 3 Event Input Enable */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t MCEO0:1; /*!< bit: 24 Match or Capture Channel 0 Event Output Enable */
+ uint32_t MCEO1:1; /*!< bit: 25 Match or Capture Channel 1 Event Output Enable */
+ uint32_t MCEO2:1; /*!< bit: 26 Match or Capture Channel 2 Event Output Enable */
+ uint32_t MCEO3:1; /*!< bit: 27 Match or Capture Channel 3 Event Output Enable */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :12; /*!< bit: 0..11 Reserved */
+ uint32_t TCINV:2; /*!< bit: 12..13 Inverted Event x Input Enable */
+ uint32_t TCEI:2; /*!< bit: 14..15 Timer/counter Event x Input Enable */
+ uint32_t MCEI:4; /*!< bit: 16..19 Match or Capture Channel x Event Input Enable */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t MCEO:4; /*!< bit: 24..27 Match or Capture Channel x Event Output Enable */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -844,29 +844,29 @@ typedef union {
/* -------- TCC_INTENCLR : (TCC Offset: 0x24) (R/W 32) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
- uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */
- uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */
- uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */
- uint32_t :7; /*!< bit: 4..10 Reserved */
- uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */
- uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */
- uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */
- uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */
- uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */
- uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */
- uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */
- uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */
- uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */
- uint32_t :12; /*!< bit: 20..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :16; /*!< bit: 0..15 Reserved */
- uint32_t MC:4; /*!< bit: 16..19 Match or Capture Channel x Interrupt Enable */
- uint32_t :12; /*!< bit: 20..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
+ uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */
+ uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */
+ uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */
+ uint32_t :7; /*!< bit: 4..10 Reserved */
+ uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */
+ uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */
+ uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */
+ uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */
+ uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */
+ uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */
+ uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */
+ uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */
+ uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :16; /*!< bit: 0..15 Reserved */
+ uint32_t MC:4; /*!< bit: 16..19 Match or Capture Channel x Interrupt Enable */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -907,29 +907,29 @@ typedef union {
/* -------- TCC_INTENSET : (TCC Offset: 0x28) (R/W 32) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
- uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */
- uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */
- uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */
- uint32_t :7; /*!< bit: 4..10 Reserved */
- uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */
- uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */
- uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */
- uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */
- uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */
- uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */
- uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */
- uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */
- uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */
- uint32_t :12; /*!< bit: 20..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :16; /*!< bit: 0..15 Reserved */
- uint32_t MC:4; /*!< bit: 16..19 Match or Capture Channel x Interrupt Enable */
- uint32_t :12; /*!< bit: 20..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
+ uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */
+ uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */
+ uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */
+ uint32_t :7; /*!< bit: 4..10 Reserved */
+ uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */
+ uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */
+ uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */
+ uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */
+ uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */
+ uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */
+ uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */
+ uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */
+ uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :16; /*!< bit: 0..15 Reserved */
+ uint32_t MC:4; /*!< bit: 16..19 Match or Capture Channel x Interrupt Enable */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -970,29 +970,29 @@ typedef union {
/* -------- TCC_INTFLAG : (TCC Offset: 0x2C) (R/W 32) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint32_t OVF:1; /*!< bit: 0 Overflow */
- __I uint32_t TRG:1; /*!< bit: 1 Retrigger */
- __I uint32_t CNT:1; /*!< bit: 2 Counter */
- __I uint32_t ERR:1; /*!< bit: 3 Error */
- __I uint32_t :7; /*!< bit: 4..10 Reserved */
- __I uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault */
- __I uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A */
- __I uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B */
- __I uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 */
- __I uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 */
- __I uint32_t MC0:1; /*!< bit: 16 Match or Capture 0 */
- __I uint32_t MC1:1; /*!< bit: 17 Match or Capture 1 */
- __I uint32_t MC2:1; /*!< bit: 18 Match or Capture 2 */
- __I uint32_t MC3:1; /*!< bit: 19 Match or Capture 3 */
- __I uint32_t :12; /*!< bit: 20..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- __I uint32_t :16; /*!< bit: 0..15 Reserved */
- __I uint32_t MC:4; /*!< bit: 16..19 Match or Capture x */
- __I uint32_t :12; /*!< bit: 20..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ __I uint32_t OVF:1; /*!< bit: 0 Overflow */
+ __I uint32_t TRG:1; /*!< bit: 1 Retrigger */
+ __I uint32_t CNT:1; /*!< bit: 2 Counter */
+ __I uint32_t ERR:1; /*!< bit: 3 Error */
+ __I uint32_t :7; /*!< bit: 4..10 Reserved */
+ __I uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault */
+ __I uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A */
+ __I uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B */
+ __I uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 */
+ __I uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 */
+ __I uint32_t MC0:1; /*!< bit: 16 Match or Capture 0 */
+ __I uint32_t MC1:1; /*!< bit: 17 Match or Capture 1 */
+ __I uint32_t MC2:1; /*!< bit: 18 Match or Capture 2 */
+ __I uint32_t MC3:1; /*!< bit: 19 Match or Capture 3 */
+ __I uint32_t :12; /*!< bit: 20..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ __I uint32_t :16; /*!< bit: 0..15 Reserved */
+ __I uint32_t MC:4; /*!< bit: 16..19 Match or Capture x */
+ __I uint32_t :12; /*!< bit: 20..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1033,42 +1033,42 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register
/* -------- TCC_STATUS : (TCC Offset: 0x30) (R/W 32) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t STOP:1; /*!< bit: 0 Stop */
- uint32_t IDX:1; /*!< bit: 1 Ramp */
- uint32_t :1; /*!< bit: 2 Reserved */
- uint32_t DFS:1; /*!< bit: 3 Non-Recoverable Debug Fault State */
- uint32_t SLAVE:1; /*!< bit: 4 Slave */
- uint32_t PATTBV:1; /*!< bit: 5 Pattern Buffer Valid */
- uint32_t WAVEBV:1; /*!< bit: 6 Wave Buffer Valid */
- uint32_t PERBV:1; /*!< bit: 7 Period Buffer Valid */
- uint32_t FAULTAIN:1; /*!< bit: 8 Recoverable Fault A Input */
- uint32_t FAULTBIN:1; /*!< bit: 9 Recoverable Fault B Input */
- uint32_t FAULT0IN:1; /*!< bit: 10 Non-Recoverable Fault0 Input */
- uint32_t FAULT1IN:1; /*!< bit: 11 Non-Recoverable Fault1 Input */
- uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A State */
- uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B State */
- uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 State */
- uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 State */
- uint32_t CCBV0:1; /*!< bit: 16 Compare Channel 0 Buffer Valid */
- uint32_t CCBV1:1; /*!< bit: 17 Compare Channel 1 Buffer Valid */
- uint32_t CCBV2:1; /*!< bit: 18 Compare Channel 2 Buffer Valid */
- uint32_t CCBV3:1; /*!< bit: 19 Compare Channel 3 Buffer Valid */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t CMP0:1; /*!< bit: 24 Compare Channel 0 Value */
- uint32_t CMP1:1; /*!< bit: 25 Compare Channel 1 Value */
- uint32_t CMP2:1; /*!< bit: 26 Compare Channel 2 Value */
- uint32_t CMP3:1; /*!< bit: 27 Compare Channel 3 Value */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :16; /*!< bit: 0..15 Reserved */
- uint32_t CCBV:4; /*!< bit: 16..19 Compare Channel x Buffer Valid */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t CMP:4; /*!< bit: 24..27 Compare Channel x Value */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t STOP:1; /*!< bit: 0 Stop */
+ uint32_t IDX:1; /*!< bit: 1 Ramp */
+ uint32_t :1; /*!< bit: 2 Reserved */
+ uint32_t DFS:1; /*!< bit: 3 Non-Recoverable Debug Fault State */
+ uint32_t SLAVE:1; /*!< bit: 4 Slave */
+ uint32_t PATTBV:1; /*!< bit: 5 Pattern Buffer Valid */
+ uint32_t WAVEBV:1; /*!< bit: 6 Wave Buffer Valid */
+ uint32_t PERBV:1; /*!< bit: 7 Period Buffer Valid */
+ uint32_t FAULTAIN:1; /*!< bit: 8 Recoverable Fault A Input */
+ uint32_t FAULTBIN:1; /*!< bit: 9 Recoverable Fault B Input */
+ uint32_t FAULT0IN:1; /*!< bit: 10 Non-Recoverable Fault0 Input */
+ uint32_t FAULT1IN:1; /*!< bit: 11 Non-Recoverable Fault1 Input */
+ uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A State */
+ uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B State */
+ uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 State */
+ uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 State */
+ uint32_t CCBV0:1; /*!< bit: 16 Compare Channel 0 Buffer Valid */
+ uint32_t CCBV1:1; /*!< bit: 17 Compare Channel 1 Buffer Valid */
+ uint32_t CCBV2:1; /*!< bit: 18 Compare Channel 2 Buffer Valid */
+ uint32_t CCBV3:1; /*!< bit: 19 Compare Channel 3 Buffer Valid */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t CMP0:1; /*!< bit: 24 Compare Channel 0 Value */
+ uint32_t CMP1:1; /*!< bit: 25 Compare Channel 1 Value */
+ uint32_t CMP2:1; /*!< bit: 26 Compare Channel 2 Value */
+ uint32_t CMP3:1; /*!< bit: 27 Compare Channel 3 Value */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :16; /*!< bit: 0..15 Reserved */
+ uint32_t CCBV:4; /*!< bit: 16..19 Compare Channel x Buffer Valid */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t CMP:4; /*!< bit: 24..27 Compare Channel x Value */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1132,26 +1132,26 @@ typedef union {
/* -------- TCC_COUNT : (TCC Offset: 0x34) (R/W 32) Count -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct { // DITH4 mode
- uint32_t :4; /*!< bit: 0.. 3 Reserved */
- uint32_t COUNT:20; /*!< bit: 4..23 Counter Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH4; /*!< Structure used for DITH4 */
- struct { // DITH5 mode
- uint32_t :5; /*!< bit: 0.. 4 Reserved */
- uint32_t COUNT:19; /*!< bit: 5..23 Counter Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH5; /*!< Structure used for DITH5 */
- struct { // DITH6 mode
- uint32_t :6; /*!< bit: 0.. 5 Reserved */
- uint32_t COUNT:18; /*!< bit: 6..23 Counter Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH6; /*!< Structure used for DITH6 */
- struct {
- uint32_t COUNT:24; /*!< bit: 0..23 Counter Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct { // DITH4 mode
+ uint32_t :4; /*!< bit: 0.. 3 Reserved */
+ uint32_t COUNT:20; /*!< bit: 4..23 Counter Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH4; /*!< Structure used for DITH4 */
+ struct { // DITH5 mode
+ uint32_t :5; /*!< bit: 0.. 4 Reserved */
+ uint32_t COUNT:19; /*!< bit: 5..23 Counter Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH5; /*!< Structure used for DITH5 */
+ struct { // DITH6 mode
+ uint32_t :6; /*!< bit: 0.. 5 Reserved */
+ uint32_t COUNT:18; /*!< bit: 6..23 Counter Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH6; /*!< Structure used for DITH6 */
+ struct {
+ uint32_t COUNT:24; /*!< bit: 0..23 Counter Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_COUNT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1184,29 +1184,29 @@ typedef union {
/* -------- TCC_PATT : (TCC Offset: 0x38) (R/W 16) Pattern -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t PGE0:1; /*!< bit: 0 Pattern Generator 0 Output Enable */
- uint16_t PGE1:1; /*!< bit: 1 Pattern Generator 1 Output Enable */
- uint16_t PGE2:1; /*!< bit: 2 Pattern Generator 2 Output Enable */
- uint16_t PGE3:1; /*!< bit: 3 Pattern Generator 3 Output Enable */
- uint16_t PGE4:1; /*!< bit: 4 Pattern Generator 4 Output Enable */
- uint16_t PGE5:1; /*!< bit: 5 Pattern Generator 5 Output Enable */
- uint16_t PGE6:1; /*!< bit: 6 Pattern Generator 6 Output Enable */
- uint16_t PGE7:1; /*!< bit: 7 Pattern Generator 7 Output Enable */
- uint16_t PGV0:1; /*!< bit: 8 Pattern Generator 0 Output Value */
- uint16_t PGV1:1; /*!< bit: 9 Pattern Generator 1 Output Value */
- uint16_t PGV2:1; /*!< bit: 10 Pattern Generator 2 Output Value */
- uint16_t PGV3:1; /*!< bit: 11 Pattern Generator 3 Output Value */
- uint16_t PGV4:1; /*!< bit: 12 Pattern Generator 4 Output Value */
- uint16_t PGV5:1; /*!< bit: 13 Pattern Generator 5 Output Value */
- uint16_t PGV6:1; /*!< bit: 14 Pattern Generator 6 Output Value */
- uint16_t PGV7:1; /*!< bit: 15 Pattern Generator 7 Output Value */
- } bit; /*!< Structure used for bit access */
- struct {
- uint16_t PGE:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable */
- uint16_t PGV:8; /*!< bit: 8..15 Pattern Generator x Output Value */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t PGE0:1; /*!< bit: 0 Pattern Generator 0 Output Enable */
+ uint16_t PGE1:1; /*!< bit: 1 Pattern Generator 1 Output Enable */
+ uint16_t PGE2:1; /*!< bit: 2 Pattern Generator 2 Output Enable */
+ uint16_t PGE3:1; /*!< bit: 3 Pattern Generator 3 Output Enable */
+ uint16_t PGE4:1; /*!< bit: 4 Pattern Generator 4 Output Enable */
+ uint16_t PGE5:1; /*!< bit: 5 Pattern Generator 5 Output Enable */
+ uint16_t PGE6:1; /*!< bit: 6 Pattern Generator 6 Output Enable */
+ uint16_t PGE7:1; /*!< bit: 7 Pattern Generator 7 Output Enable */
+ uint16_t PGV0:1; /*!< bit: 8 Pattern Generator 0 Output Value */
+ uint16_t PGV1:1; /*!< bit: 9 Pattern Generator 1 Output Value */
+ uint16_t PGV2:1; /*!< bit: 10 Pattern Generator 2 Output Value */
+ uint16_t PGV3:1; /*!< bit: 11 Pattern Generator 3 Output Value */
+ uint16_t PGV4:1; /*!< bit: 12 Pattern Generator 4 Output Value */
+ uint16_t PGV5:1; /*!< bit: 13 Pattern Generator 5 Output Value */
+ uint16_t PGV6:1; /*!< bit: 14 Pattern Generator 6 Output Value */
+ uint16_t PGV7:1; /*!< bit: 15 Pattern Generator 7 Output Value */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t PGE:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable */
+ uint16_t PGV:8; /*!< bit: 8..15 Pattern Generator x Output Value */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
} TCC_PATT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1256,38 +1256,38 @@ typedef union {
/* -------- TCC_WAVE : (TCC Offset: 0x3C) (R/W 32) Waveform Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t WAVEGEN:3; /*!< bit: 0.. 2 Waveform Generation */
- uint32_t :1; /*!< bit: 3 Reserved */
- uint32_t RAMP:2; /*!< bit: 4.. 5 Ramp Mode */
- uint32_t :1; /*!< bit: 6 Reserved */
- uint32_t CIPEREN:1; /*!< bit: 7 Circular period Enable */
- uint32_t CICCEN0:1; /*!< bit: 8 Circular Channel 0 Enable */
- uint32_t CICCEN1:1; /*!< bit: 9 Circular Channel 1 Enable */
- uint32_t CICCEN2:1; /*!< bit: 10 Circular Channel 2 Enable */
- uint32_t CICCEN3:1; /*!< bit: 11 Circular Channel 3 Enable */
- uint32_t :4; /*!< bit: 12..15 Reserved */
- uint32_t POL0:1; /*!< bit: 16 Channel 0 Polarity */
- uint32_t POL1:1; /*!< bit: 17 Channel 1 Polarity */
- uint32_t POL2:1; /*!< bit: 18 Channel 2 Polarity */
- uint32_t POL3:1; /*!< bit: 19 Channel 3 Polarity */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t SWAP0:1; /*!< bit: 24 Swap DTI Output Pair 0 */
- uint32_t SWAP1:1; /*!< bit: 25 Swap DTI Output Pair 1 */
- uint32_t SWAP2:1; /*!< bit: 26 Swap DTI Output Pair 2 */
- uint32_t SWAP3:1; /*!< bit: 27 Swap DTI Output Pair 3 */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :8; /*!< bit: 0.. 7 Reserved */
- uint32_t CICCEN:4; /*!< bit: 8..11 Circular Channel x Enable */
- uint32_t :4; /*!< bit: 12..15 Reserved */
- uint32_t POL:4; /*!< bit: 16..19 Channel x Polarity */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t SWAP:4; /*!< bit: 24..27 Swap DTI Output Pair x */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t WAVEGEN:3; /*!< bit: 0.. 2 Waveform Generation */
+ uint32_t :1; /*!< bit: 3 Reserved */
+ uint32_t RAMP:2; /*!< bit: 4.. 5 Ramp Mode */
+ uint32_t :1; /*!< bit: 6 Reserved */
+ uint32_t CIPEREN:1; /*!< bit: 7 Circular period Enable */
+ uint32_t CICCEN0:1; /*!< bit: 8 Circular Channel 0 Enable */
+ uint32_t CICCEN1:1; /*!< bit: 9 Circular Channel 1 Enable */
+ uint32_t CICCEN2:1; /*!< bit: 10 Circular Channel 2 Enable */
+ uint32_t CICCEN3:1; /*!< bit: 11 Circular Channel 3 Enable */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t POL0:1; /*!< bit: 16 Channel 0 Polarity */
+ uint32_t POL1:1; /*!< bit: 17 Channel 1 Polarity */
+ uint32_t POL2:1; /*!< bit: 18 Channel 2 Polarity */
+ uint32_t POL3:1; /*!< bit: 19 Channel 3 Polarity */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t SWAP0:1; /*!< bit: 24 Swap DTI Output Pair 0 */
+ uint32_t SWAP1:1; /*!< bit: 25 Swap DTI Output Pair 1 */
+ uint32_t SWAP2:1; /*!< bit: 26 Swap DTI Output Pair 2 */
+ uint32_t SWAP3:1; /*!< bit: 27 Swap DTI Output Pair 3 */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :8; /*!< bit: 0.. 7 Reserved */
+ uint32_t CICCEN:4; /*!< bit: 8..11 Circular Channel x Enable */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t POL:4; /*!< bit: 16..19 Channel x Polarity */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t SWAP:4; /*!< bit: 24..27 Swap DTI Output Pair x */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_WAVE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1360,26 +1360,26 @@ typedef union {
/* -------- TCC_PER : (TCC Offset: 0x40) (R/W 32) Period -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct { // DITH4 mode
- uint32_t DITHERCY:4; /*!< bit: 0.. 3 Dithering Cycle Number */
- uint32_t PER:20; /*!< bit: 4..23 Period Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH4; /*!< Structure used for DITH4 */
- struct { // DITH5 mode
- uint32_t DITHERCY:5; /*!< bit: 0.. 4 Dithering Cycle Number */
- uint32_t PER:19; /*!< bit: 5..23 Period Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH5; /*!< Structure used for DITH5 */
- struct { // DITH6 mode
- uint32_t DITHERCY:6; /*!< bit: 0.. 5 Dithering Cycle Number */
- uint32_t PER:18; /*!< bit: 6..23 Period Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH6; /*!< Structure used for DITH6 */
- struct {
- uint32_t PER:24; /*!< bit: 0..23 Period Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct { // DITH4 mode
+ uint32_t DITHERCY:4; /*!< bit: 0.. 3 Dithering Cycle Number */
+ uint32_t PER:20; /*!< bit: 4..23 Period Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH4; /*!< Structure used for DITH4 */
+ struct { // DITH5 mode
+ uint32_t DITHERCY:5; /*!< bit: 0.. 4 Dithering Cycle Number */
+ uint32_t PER:19; /*!< bit: 5..23 Period Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH5; /*!< Structure used for DITH5 */
+ struct { // DITH6 mode
+ uint32_t DITHERCY:6; /*!< bit: 0.. 5 Dithering Cycle Number */
+ uint32_t PER:18; /*!< bit: 6..23 Period Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH6; /*!< Structure used for DITH6 */
+ struct {
+ uint32_t PER:24; /*!< bit: 0..23 Period Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_PER_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1421,26 +1421,26 @@ typedef union {
/* -------- TCC_CC : (TCC Offset: 0x44) (R/W 32) Compare and Capture -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct { // DITH4 mode
- uint32_t DITHERCY:4; /*!< bit: 0.. 3 Dithering Cycle Number */
- uint32_t CC:20; /*!< bit: 4..23 Channel Compare/Capture Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH4; /*!< Structure used for DITH4 */
- struct { // DITH5 mode
- uint32_t DITHERCY:5; /*!< bit: 0.. 4 Dithering Cycle Number */
- uint32_t CC:19; /*!< bit: 5..23 Channel Compare/Capture Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH5; /*!< Structure used for DITH5 */
- struct { // DITH6 mode
- uint32_t DITHERCY:6; /*!< bit: 0.. 5 Dithering Cycle Number */
- uint32_t CC:18; /*!< bit: 6..23 Channel Compare/Capture Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH6; /*!< Structure used for DITH6 */
- struct {
- uint32_t CC:24; /*!< bit: 0..23 Channel Compare/Capture Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct { // DITH4 mode
+ uint32_t DITHERCY:4; /*!< bit: 0.. 3 Dithering Cycle Number */
+ uint32_t CC:20; /*!< bit: 4..23 Channel Compare/Capture Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH4; /*!< Structure used for DITH4 */
+ struct { // DITH5 mode
+ uint32_t DITHERCY:5; /*!< bit: 0.. 4 Dithering Cycle Number */
+ uint32_t CC:19; /*!< bit: 5..23 Channel Compare/Capture Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH5; /*!< Structure used for DITH5 */
+ struct { // DITH6 mode
+ uint32_t DITHERCY:6; /*!< bit: 0.. 5 Dithering Cycle Number */
+ uint32_t CC:18; /*!< bit: 6..23 Channel Compare/Capture Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH6; /*!< Structure used for DITH6 */
+ struct {
+ uint32_t CC:24; /*!< bit: 0..23 Channel Compare/Capture Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_CC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1482,29 +1482,29 @@ typedef union {
/* -------- TCC_PATTB : (TCC Offset: 0x64) (R/W 16) Pattern Buffer -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t PGEB0:1; /*!< bit: 0 Pattern Generator 0 Output Enable Buffer */
- uint16_t PGEB1:1; /*!< bit: 1 Pattern Generator 1 Output Enable Buffer */
- uint16_t PGEB2:1; /*!< bit: 2 Pattern Generator 2 Output Enable Buffer */
- uint16_t PGEB3:1; /*!< bit: 3 Pattern Generator 3 Output Enable Buffer */
- uint16_t PGEB4:1; /*!< bit: 4 Pattern Generator 4 Output Enable Buffer */
- uint16_t PGEB5:1; /*!< bit: 5 Pattern Generator 5 Output Enable Buffer */
- uint16_t PGEB6:1; /*!< bit: 6 Pattern Generator 6 Output Enable Buffer */
- uint16_t PGEB7:1; /*!< bit: 7 Pattern Generator 7 Output Enable Buffer */
- uint16_t PGVB0:1; /*!< bit: 8 Pattern Generator 0 Output Enable */
- uint16_t PGVB1:1; /*!< bit: 9 Pattern Generator 1 Output Enable */
- uint16_t PGVB2:1; /*!< bit: 10 Pattern Generator 2 Output Enable */
- uint16_t PGVB3:1; /*!< bit: 11 Pattern Generator 3 Output Enable */
- uint16_t PGVB4:1; /*!< bit: 12 Pattern Generator 4 Output Enable */
- uint16_t PGVB5:1; /*!< bit: 13 Pattern Generator 5 Output Enable */
- uint16_t PGVB6:1; /*!< bit: 14 Pattern Generator 6 Output Enable */
- uint16_t PGVB7:1; /*!< bit: 15 Pattern Generator 7 Output Enable */
- } bit; /*!< Structure used for bit access */
- struct {
- uint16_t PGEB:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable Buffer */
- uint16_t PGVB:8; /*!< bit: 8..15 Pattern Generator x Output Enable */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t PGEB0:1; /*!< bit: 0 Pattern Generator 0 Output Enable Buffer */
+ uint16_t PGEB1:1; /*!< bit: 1 Pattern Generator 1 Output Enable Buffer */
+ uint16_t PGEB2:1; /*!< bit: 2 Pattern Generator 2 Output Enable Buffer */
+ uint16_t PGEB3:1; /*!< bit: 3 Pattern Generator 3 Output Enable Buffer */
+ uint16_t PGEB4:1; /*!< bit: 4 Pattern Generator 4 Output Enable Buffer */
+ uint16_t PGEB5:1; /*!< bit: 5 Pattern Generator 5 Output Enable Buffer */
+ uint16_t PGEB6:1; /*!< bit: 6 Pattern Generator 6 Output Enable Buffer */
+ uint16_t PGEB7:1; /*!< bit: 7 Pattern Generator 7 Output Enable Buffer */
+ uint16_t PGVB0:1; /*!< bit: 8 Pattern Generator 0 Output Enable */
+ uint16_t PGVB1:1; /*!< bit: 9 Pattern Generator 1 Output Enable */
+ uint16_t PGVB2:1; /*!< bit: 10 Pattern Generator 2 Output Enable */
+ uint16_t PGVB3:1; /*!< bit: 11 Pattern Generator 3 Output Enable */
+ uint16_t PGVB4:1; /*!< bit: 12 Pattern Generator 4 Output Enable */
+ uint16_t PGVB5:1; /*!< bit: 13 Pattern Generator 5 Output Enable */
+ uint16_t PGVB6:1; /*!< bit: 14 Pattern Generator 6 Output Enable */
+ uint16_t PGVB7:1; /*!< bit: 15 Pattern Generator 7 Output Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t PGEB:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable Buffer */
+ uint16_t PGVB:8; /*!< bit: 8..15 Pattern Generator x Output Enable */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
} TCC_PATTB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1554,38 +1554,38 @@ typedef union {
/* -------- TCC_WAVEB : (TCC Offset: 0x68) (R/W 32) Waveform Control Buffer -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t WAVEGENB:3; /*!< bit: 0.. 2 Waveform Generation Buffer */
- uint32_t :1; /*!< bit: 3 Reserved */
- uint32_t RAMPB:2; /*!< bit: 4.. 5 Ramp Mode Buffer */
- uint32_t :1; /*!< bit: 6 Reserved */
- uint32_t CIPERENB:1; /*!< bit: 7 Circular Period Enable Buffer */
- uint32_t CICCENB0:1; /*!< bit: 8 Circular Channel 0 Enable Buffer */
- uint32_t CICCENB1:1; /*!< bit: 9 Circular Channel 1 Enable Buffer */
- uint32_t CICCENB2:1; /*!< bit: 10 Circular Channel 2 Enable Buffer */
- uint32_t CICCENB3:1; /*!< bit: 11 Circular Channel 3 Enable Buffer */
- uint32_t :4; /*!< bit: 12..15 Reserved */
- uint32_t POLB0:1; /*!< bit: 16 Channel 0 Polarity Buffer */
- uint32_t POLB1:1; /*!< bit: 17 Channel 1 Polarity Buffer */
- uint32_t POLB2:1; /*!< bit: 18 Channel 2 Polarity Buffer */
- uint32_t POLB3:1; /*!< bit: 19 Channel 3 Polarity Buffer */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t SWAPB0:1; /*!< bit: 24 Swap DTI Output Pair 0 Buffer */
- uint32_t SWAPB1:1; /*!< bit: 25 Swap DTI Output Pair 1 Buffer */
- uint32_t SWAPB2:1; /*!< bit: 26 Swap DTI Output Pair 2 Buffer */
- uint32_t SWAPB3:1; /*!< bit: 27 Swap DTI Output Pair 3 Buffer */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint32_t :8; /*!< bit: 0.. 7 Reserved */
- uint32_t CICCENB:4; /*!< bit: 8..11 Circular Channel x Enable Buffer */
- uint32_t :4; /*!< bit: 12..15 Reserved */
- uint32_t POLB:4; /*!< bit: 16..19 Channel x Polarity Buffer */
- uint32_t :4; /*!< bit: 20..23 Reserved */
- uint32_t SWAPB:4; /*!< bit: 24..27 Swap DTI Output Pair x Buffer */
- uint32_t :4; /*!< bit: 28..31 Reserved */
- } vec; /*!< Structure used for vec access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t WAVEGENB:3; /*!< bit: 0.. 2 Waveform Generation Buffer */
+ uint32_t :1; /*!< bit: 3 Reserved */
+ uint32_t RAMPB:2; /*!< bit: 4.. 5 Ramp Mode Buffer */
+ uint32_t :1; /*!< bit: 6 Reserved */
+ uint32_t CIPERENB:1; /*!< bit: 7 Circular Period Enable Buffer */
+ uint32_t CICCENB0:1; /*!< bit: 8 Circular Channel 0 Enable Buffer */
+ uint32_t CICCENB1:1; /*!< bit: 9 Circular Channel 1 Enable Buffer */
+ uint32_t CICCENB2:1; /*!< bit: 10 Circular Channel 2 Enable Buffer */
+ uint32_t CICCENB3:1; /*!< bit: 11 Circular Channel 3 Enable Buffer */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t POLB0:1; /*!< bit: 16 Channel 0 Polarity Buffer */
+ uint32_t POLB1:1; /*!< bit: 17 Channel 1 Polarity Buffer */
+ uint32_t POLB2:1; /*!< bit: 18 Channel 2 Polarity Buffer */
+ uint32_t POLB3:1; /*!< bit: 19 Channel 3 Polarity Buffer */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t SWAPB0:1; /*!< bit: 24 Swap DTI Output Pair 0 Buffer */
+ uint32_t SWAPB1:1; /*!< bit: 25 Swap DTI Output Pair 1 Buffer */
+ uint32_t SWAPB2:1; /*!< bit: 26 Swap DTI Output Pair 2 Buffer */
+ uint32_t SWAPB3:1; /*!< bit: 27 Swap DTI Output Pair 3 Buffer */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :8; /*!< bit: 0.. 7 Reserved */
+ uint32_t CICCENB:4; /*!< bit: 8..11 Circular Channel x Enable Buffer */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t POLB:4; /*!< bit: 16..19 Channel x Polarity Buffer */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t SWAPB:4; /*!< bit: 24..27 Swap DTI Output Pair x Buffer */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_WAVEB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1658,26 +1658,26 @@ typedef union {
/* -------- TCC_PERB : (TCC Offset: 0x6C) (R/W 32) Period Buffer -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct { // DITH4 mode
- uint32_t DITHERCYB:4; /*!< bit: 0.. 3 Dithering Buffer Cycle Number */
- uint32_t PERB:20; /*!< bit: 4..23 Period Buffer Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH4; /*!< Structure used for DITH4 */
- struct { // DITH5 mode
- uint32_t DITHERCYB:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */
- uint32_t PERB:19; /*!< bit: 5..23 Period Buffer Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH5; /*!< Structure used for DITH5 */
- struct { // DITH6 mode
- uint32_t DITHERCYB:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */
- uint32_t PERB:18; /*!< bit: 6..23 Period Buffer Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH6; /*!< Structure used for DITH6 */
- struct {
- uint32_t PERB:24; /*!< bit: 0..23 Period Buffer Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct { // DITH4 mode
+ uint32_t DITHERCYB:4; /*!< bit: 0.. 3 Dithering Buffer Cycle Number */
+ uint32_t PERB:20; /*!< bit: 4..23 Period Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH4; /*!< Structure used for DITH4 */
+ struct { // DITH5 mode
+ uint32_t DITHERCYB:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */
+ uint32_t PERB:19; /*!< bit: 5..23 Period Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH5; /*!< Structure used for DITH5 */
+ struct { // DITH6 mode
+ uint32_t DITHERCYB:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */
+ uint32_t PERB:18; /*!< bit: 6..23 Period Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH6; /*!< Structure used for DITH6 */
+ struct {
+ uint32_t PERB:24; /*!< bit: 0..23 Period Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_PERB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1719,26 +1719,26 @@ typedef union {
/* -------- TCC_CCB : (TCC Offset: 0x70) (R/W 32) Compare and Capture Buffer -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct { // DITH4 mode
- uint32_t DITHERCYB:4; /*!< bit: 0.. 3 Dithering Buffer Cycle Number */
- uint32_t CCB:20; /*!< bit: 4..23 Channel Compare/Capture Buffer Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH4; /*!< Structure used for DITH4 */
- struct { // DITH5 mode
- uint32_t DITHERCYB:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */
- uint32_t CCB:19; /*!< bit: 5..23 Channel Compare/Capture Buffer Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH5; /*!< Structure used for DITH5 */
- struct { // DITH6 mode
- uint32_t DITHERCYB:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */
- uint32_t CCB:18; /*!< bit: 6..23 Channel Compare/Capture Buffer Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } DITH6; /*!< Structure used for DITH6 */
- struct {
- uint32_t CCB:24; /*!< bit: 0..23 Channel Compare/Capture Buffer Value */
- uint32_t :8; /*!< bit: 24..31 Reserved */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct { // DITH4 mode
+ uint32_t DITHERCYB:4; /*!< bit: 0.. 3 Dithering Buffer Cycle Number */
+ uint32_t CCB:20; /*!< bit: 4..23 Channel Compare/Capture Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH4; /*!< Structure used for DITH4 */
+ struct { // DITH5 mode
+ uint32_t DITHERCYB:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */
+ uint32_t CCB:19; /*!< bit: 5..23 Channel Compare/Capture Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH5; /*!< Structure used for DITH5 */
+ struct { // DITH6 mode
+ uint32_t DITHERCYB:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */
+ uint32_t CCB:18; /*!< bit: 6..23 Channel Compare/Capture Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH6; /*!< Structure used for DITH6 */
+ struct {
+ uint32_t CCB:24; /*!< bit: 0..23 Channel Compare/Capture Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} TCC_CCB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1780,35 +1780,35 @@ typedef union {
/** \brief TCC hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO TCC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */
- __IO TCC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
- __IO TCC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
- RoReg8 Reserved1[0x2];
- __I TCC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x08 (R/ 32) Synchronization Busy */
- __IO TCC_FCTRLA_Type FCTRLA; /**< \brief Offset: 0x0C (R/W 32) Recoverable Fault A Configuration */
- __IO TCC_FCTRLB_Type FCTRLB; /**< \brief Offset: 0x10 (R/W 32) Recoverable Fault B Configuration */
- __IO TCC_WEXCTRL_Type WEXCTRL; /**< \brief Offset: 0x14 (R/W 32) Waveform Extension Configuration */
- __IO TCC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x18 (R/W 32) Driver Control */
- RoReg8 Reserved2[0x2];
- __IO TCC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x1E (R/W 8) Debug Control */
- RoReg8 Reserved3[0x1];
- __IO TCC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x20 (R/W 32) Event Control */
- __IO TCC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x24 (R/W 32) Interrupt Enable Clear */
- __IO TCC_INTENSET_Type INTENSET; /**< \brief Offset: 0x28 (R/W 32) Interrupt Enable Set */
- __IO TCC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x2C (R/W 32) Interrupt Flag Status and Clear */
- __IO TCC_STATUS_Type STATUS; /**< \brief Offset: 0x30 (R/W 32) Status */
- __IO TCC_COUNT_Type COUNT; /**< \brief Offset: 0x34 (R/W 32) Count */
- __IO TCC_PATT_Type PATT; /**< \brief Offset: 0x38 (R/W 16) Pattern */
- RoReg8 Reserved4[0x2];
- __IO TCC_WAVE_Type WAVE; /**< \brief Offset: 0x3C (R/W 32) Waveform Control */
- __IO TCC_PER_Type PER; /**< \brief Offset: 0x40 (R/W 32) Period */
- __IO TCC_CC_Type CC[4]; /**< \brief Offset: 0x44 (R/W 32) Compare and Capture */
- RoReg8 Reserved5[0x10];
- __IO TCC_PATTB_Type PATTB; /**< \brief Offset: 0x64 (R/W 16) Pattern Buffer */
- RoReg8 Reserved6[0x2];
- __IO TCC_WAVEB_Type WAVEB; /**< \brief Offset: 0x68 (R/W 32) Waveform Control Buffer */
- __IO TCC_PERB_Type PERB; /**< \brief Offset: 0x6C (R/W 32) Period Buffer */
- __IO TCC_CCB_Type CCB[4]; /**< \brief Offset: 0x70 (R/W 32) Compare and Capture Buffer */
+ __IO TCC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */
+ __IO TCC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
+ __IO TCC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
+ RoReg8 Reserved1[0x2];
+ __I TCC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x08 (R/ 32) Synchronization Busy */
+ __IO TCC_FCTRLA_Type FCTRLA; /**< \brief Offset: 0x0C (R/W 32) Recoverable Fault A Configuration */
+ __IO TCC_FCTRLB_Type FCTRLB; /**< \brief Offset: 0x10 (R/W 32) Recoverable Fault B Configuration */
+ __IO TCC_WEXCTRL_Type WEXCTRL; /**< \brief Offset: 0x14 (R/W 32) Waveform Extension Configuration */
+ __IO TCC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x18 (R/W 32) Driver Control */
+ RoReg8 Reserved2[0x2];
+ __IO TCC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x1E (R/W 8) Debug Control */
+ RoReg8 Reserved3[0x1];
+ __IO TCC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x20 (R/W 32) Event Control */
+ __IO TCC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x24 (R/W 32) Interrupt Enable Clear */
+ __IO TCC_INTENSET_Type INTENSET; /**< \brief Offset: 0x28 (R/W 32) Interrupt Enable Set */
+ __IO TCC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x2C (R/W 32) Interrupt Flag Status and Clear */
+ __IO TCC_STATUS_Type STATUS; /**< \brief Offset: 0x30 (R/W 32) Status */
+ __IO TCC_COUNT_Type COUNT; /**< \brief Offset: 0x34 (R/W 32) Count */
+ __IO TCC_PATT_Type PATT; /**< \brief Offset: 0x38 (R/W 16) Pattern */
+ RoReg8 Reserved4[0x2];
+ __IO TCC_WAVE_Type WAVE; /**< \brief Offset: 0x3C (R/W 32) Waveform Control */
+ __IO TCC_PER_Type PER; /**< \brief Offset: 0x40 (R/W 32) Period */
+ __IO TCC_CC_Type CC[4]; /**< \brief Offset: 0x44 (R/W 32) Compare and Capture */
+ RoReg8 Reserved5[0x10];
+ __IO TCC_PATTB_Type PATTB; /**< \brief Offset: 0x64 (R/W 16) Pattern Buffer */
+ RoReg8 Reserved6[0x2];
+ __IO TCC_WAVEB_Type WAVEB; /**< \brief Offset: 0x68 (R/W 32) Waveform Control Buffer */
+ __IO TCC_PERB_Type PERB; /**< \brief Offset: 0x6C (R/W 32) Period Buffer */
+ __IO TCC_CCB_Type CCB[4]; /**< \brief Offset: 0x70 (R/W 32) Compare and Capture Buffer */
} Tcc;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_usb.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_usb.h
index da019a8cc1e..6c9ee674356 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_usb.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_usb.h
@@ -56,14 +56,14 @@
/* -------- USB_CTRLA : (USB Offset: 0x000) (R/W 8) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t SWRST:1; /*!< bit: 0 Software Reset */
- uint8_t ENABLE:1; /*!< bit: 1 Enable */
- uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby Mode */
- uint8_t :4; /*!< bit: 3.. 6 Reserved */
- uint8_t MODE:1; /*!< bit: 7 Operating Mode */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable */
+ uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby Mode */
+ uint8_t :4; /*!< bit: 3.. 6 Reserved */
+ uint8_t MODE:1; /*!< bit: 7 Operating Mode */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} USB_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -87,12 +87,12 @@ typedef union {
/* -------- USB_SYNCBUSY : (USB Offset: 0x002) (R/ 8) Synchronization Busy -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
- uint8_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} USB_SYNCBUSY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -108,12 +108,12 @@ typedef union {
/* -------- USB_QOSCTRL : (USB Offset: 0x003) (R/W 8) USB Quality Of Service -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t CQOS:2; /*!< bit: 0.. 1 Configuration Quality of Service */
- uint8_t DQOS:2; /*!< bit: 2.. 3 Data Quality of Service */
- uint8_t :4; /*!< bit: 4.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t CQOS:2; /*!< bit: 0.. 1 Configuration Quality of Service */
+ uint8_t DQOS:2; /*!< bit: 2.. 3 Data Quality of Service */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} USB_QOSCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -147,20 +147,20 @@ typedef union {
/* -------- USB_DEVICE_CTRLB : (USB Offset: 0x008) (R/W 16) DEVICE DEVICE Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t DETACH:1; /*!< bit: 0 Detach */
- uint16_t UPRSM:1; /*!< bit: 1 Upstream Resume */
- uint16_t SPDCONF:2; /*!< bit: 2.. 3 Speed Configuration */
- uint16_t NREPLY:1; /*!< bit: 4 No Reply */
- uint16_t TSTJ:1; /*!< bit: 5 Test mode J */
- uint16_t TSTK:1; /*!< bit: 6 Test mode K */
- uint16_t TSTPCKT:1; /*!< bit: 7 Test packet mode */
- uint16_t OPMODE2:1; /*!< bit: 8 Specific Operational Mode */
- uint16_t GNAK:1; /*!< bit: 9 Global NAK */
- uint16_t LPMHDSK:2; /*!< bit: 10..11 Link Power Management Handshake */
- uint16_t :4; /*!< bit: 12..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t DETACH:1; /*!< bit: 0 Detach */
+ uint16_t UPRSM:1; /*!< bit: 1 Upstream Resume */
+ uint16_t SPDCONF:2; /*!< bit: 2.. 3 Speed Configuration */
+ uint16_t NREPLY:1; /*!< bit: 4 No Reply */
+ uint16_t TSTJ:1; /*!< bit: 5 Test mode J */
+ uint16_t TSTK:1; /*!< bit: 6 Test mode K */
+ uint16_t TSTPCKT:1; /*!< bit: 7 Test packet mode */
+ uint16_t OPMODE2:1; /*!< bit: 8 Specific Operational Mode */
+ uint16_t GNAK:1; /*!< bit: 9 Global NAK */
+ uint16_t LPMHDSK:2; /*!< bit: 10..11 Link Power Management Handshake */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} USB_DEVICE_CTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -210,21 +210,21 @@ typedef union {
/* -------- USB_HOST_CTRLB : (USB Offset: 0x008) (R/W 16) HOST HOST Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t :1; /*!< bit: 0 Reserved */
- uint16_t RESUME:1; /*!< bit: 1 Send USB Resume */
- uint16_t SPDCONF:2; /*!< bit: 2.. 3 Speed Configuration for Host */
- uint16_t :1; /*!< bit: 4 Reserved */
- uint16_t TSTJ:1; /*!< bit: 5 Test mode J */
- uint16_t TSTK:1; /*!< bit: 6 Test mode K */
- uint16_t :1; /*!< bit: 7 Reserved */
- uint16_t SOFE:1; /*!< bit: 8 Start of Frame Generation Enable */
- uint16_t BUSRESET:1; /*!< bit: 9 Send USB Reset */
- uint16_t VBUSOK:1; /*!< bit: 10 VBUS is OK */
- uint16_t L1RESUME:1; /*!< bit: 11 Send L1 Resume */
- uint16_t :4; /*!< bit: 12..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t :1; /*!< bit: 0 Reserved */
+ uint16_t RESUME:1; /*!< bit: 1 Send USB Resume */
+ uint16_t SPDCONF:2; /*!< bit: 2.. 3 Speed Configuration for Host */
+ uint16_t :1; /*!< bit: 4 Reserved */
+ uint16_t TSTJ:1; /*!< bit: 5 Test mode J */
+ uint16_t TSTK:1; /*!< bit: 6 Test mode K */
+ uint16_t :1; /*!< bit: 7 Reserved */
+ uint16_t SOFE:1; /*!< bit: 8 Start of Frame Generation Enable */
+ uint16_t BUSRESET:1; /*!< bit: 9 Send USB Reset */
+ uint16_t VBUSOK:1; /*!< bit: 10 VBUS is OK */
+ uint16_t L1RESUME:1; /*!< bit: 11 Send L1 Resume */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} USB_HOST_CTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -257,11 +257,11 @@ typedef union {
/* -------- USB_DEVICE_DADD : (USB Offset: 0x00A) (R/W 8) DEVICE DEVICE Device Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DADD:7; /*!< bit: 0.. 6 Device Address */
- uint8_t ADDEN:1; /*!< bit: 7 Device Address Enable */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DADD:7; /*!< bit: 0.. 6 Device Address */
+ uint8_t ADDEN:1; /*!< bit: 7 Device Address Enable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} USB_DEVICE_DADD_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -278,12 +278,12 @@ typedef union {
/* -------- USB_HOST_HSOFC : (USB Offset: 0x00A) (R/W 8) HOST HOST Host Start Of Frame Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t FLENC:4; /*!< bit: 0.. 3 Frame Length Control */
- uint8_t :3; /*!< bit: 4.. 6 Reserved */
- uint8_t FLENCE:1; /*!< bit: 7 Frame Length Control Enable */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t FLENC:4; /*!< bit: 0.. 3 Frame Length Control */
+ uint8_t :3; /*!< bit: 4.. 6 Reserved */
+ uint8_t FLENCE:1; /*!< bit: 7 Frame Length Control Enable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} USB_HOST_HSOFC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -300,13 +300,13 @@ typedef union {
/* -------- USB_DEVICE_STATUS : (USB Offset: 0x00C) (R/ 8) DEVICE DEVICE Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t :2; /*!< bit: 0.. 1 Reserved */
- uint8_t SPEED:2; /*!< bit: 2.. 3 Speed Status */
- uint8_t :2; /*!< bit: 4.. 5 Reserved */
- uint8_t LINESTATE:2; /*!< bit: 6.. 7 USB Line State Status */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t :2; /*!< bit: 0.. 1 Reserved */
+ uint8_t SPEED:2; /*!< bit: 2.. 3 Speed Status */
+ uint8_t :2; /*!< bit: 4.. 5 Reserved */
+ uint8_t LINESTATE:2; /*!< bit: 6.. 7 USB Line State Status */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} USB_DEVICE_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -336,13 +336,13 @@ typedef union {
/* -------- USB_HOST_STATUS : (USB Offset: 0x00C) (R/W 8) HOST HOST Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t :2; /*!< bit: 0.. 1 Reserved */
- uint8_t SPEED:2; /*!< bit: 2.. 3 Speed Status */
- uint8_t :2; /*!< bit: 4.. 5 Reserved */
- uint8_t LINESTATE:2; /*!< bit: 6.. 7 USB Line State Status */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t :2; /*!< bit: 0.. 1 Reserved */
+ uint8_t SPEED:2; /*!< bit: 2.. 3 Speed Status */
+ uint8_t :2; /*!< bit: 4.. 5 Reserved */
+ uint8_t LINESTATE:2; /*!< bit: 6.. 7 USB Line State Status */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} USB_HOST_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -360,11 +360,11 @@ typedef union {
/* -------- USB_FSMSTATUS : (USB Offset: 0x00D) (R/ 8) Finite State Machine Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t FSMSTATE:6; /*!< bit: 0.. 5 Fine State Machine Status */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t FSMSTATE:6; /*!< bit: 0.. 5 Fine State Machine Status */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} USB_FSMSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -393,13 +393,13 @@ typedef union {
/* -------- USB_DEVICE_FNUM : (USB Offset: 0x010) (R/ 16) DEVICE DEVICE Device Frame Number -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t MFNUM:3; /*!< bit: 0.. 2 Micro Frame Number */
- uint16_t FNUM:11; /*!< bit: 3..13 Frame Number */
- uint16_t :1; /*!< bit: 14 Reserved */
- uint16_t FNCERR:1; /*!< bit: 15 Frame Number CRC Error */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t MFNUM:3; /*!< bit: 0.. 2 Micro Frame Number */
+ uint16_t FNUM:11; /*!< bit: 3..13 Frame Number */
+ uint16_t :1; /*!< bit: 14 Reserved */
+ uint16_t FNCERR:1; /*!< bit: 15 Frame Number CRC Error */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} USB_DEVICE_FNUM_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -419,12 +419,12 @@ typedef union {
/* -------- USB_HOST_FNUM : (USB Offset: 0x010) (R/W 16) HOST HOST Host Frame Number -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t MFNUM:3; /*!< bit: 0.. 2 Micro Frame Number */
- uint16_t FNUM:11; /*!< bit: 3..13 Frame Number */
- uint16_t :2; /*!< bit: 14..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t MFNUM:3; /*!< bit: 0.. 2 Micro Frame Number */
+ uint16_t FNUM:11; /*!< bit: 3..13 Frame Number */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} USB_HOST_FNUM_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -442,10 +442,10 @@ typedef union {
/* -------- USB_HOST_FLENHIGH : (USB Offset: 0x012) (R/ 8) HOST HOST Host Frame Length -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t FLENHIGH:8; /*!< bit: 0.. 7 Frame Length */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t FLENHIGH:8; /*!< bit: 0.. 7 Frame Length */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} USB_HOST_FLENHIGH_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -460,20 +460,20 @@ typedef union {
/* -------- USB_DEVICE_INTENCLR : (USB Offset: 0x014) (R/W 16) DEVICE DEVICE Device Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t SUSPEND:1; /*!< bit: 0 Suspend Interrupt Enable */
- uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame Interrupt Enable in High Speed Mode */
- uint16_t SOF:1; /*!< bit: 2 Start Of Frame Interrupt Enable */
- uint16_t EORST:1; /*!< bit: 3 End of Reset Interrupt Enable */
- uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */
- uint16_t EORSM:1; /*!< bit: 5 End Of Resume Interrupt Enable */
- uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume Interrupt Enable */
- uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */
- uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet Interrupt Enable */
- uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend Interrupt Enable */
- uint16_t :6; /*!< bit: 10..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t SUSPEND:1; /*!< bit: 0 Suspend Interrupt Enable */
+ uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame Interrupt Enable in High Speed Mode */
+ uint16_t SOF:1; /*!< bit: 2 Start Of Frame Interrupt Enable */
+ uint16_t EORST:1; /*!< bit: 3 End of Reset Interrupt Enable */
+ uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */
+ uint16_t EORSM:1; /*!< bit: 5 End Of Resume Interrupt Enable */
+ uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume Interrupt Enable */
+ uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */
+ uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet Interrupt Enable */
+ uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend Interrupt Enable */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} USB_DEVICE_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -505,19 +505,19 @@ typedef union {
/* -------- USB_HOST_INTENCLR : (USB Offset: 0x014) (R/W 16) HOST HOST Host Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t :2; /*!< bit: 0.. 1 Reserved */
- uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame Interrupt Disable */
- uint16_t RST:1; /*!< bit: 3 BUS Reset Interrupt Disable */
- uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Disable */
- uint16_t DNRSM:1; /*!< bit: 5 DownStream to Device Interrupt Disable */
- uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume from Device Interrupt Disable */
- uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Disable */
- uint16_t DCONN:1; /*!< bit: 8 Device Connection Interrupt Disable */
- uint16_t DDISC:1; /*!< bit: 9 Device Disconnection Interrupt Disable */
- uint16_t :6; /*!< bit: 10..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t :2; /*!< bit: 0.. 1 Reserved */
+ uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame Interrupt Disable */
+ uint16_t RST:1; /*!< bit: 3 BUS Reset Interrupt Disable */
+ uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Disable */
+ uint16_t DNRSM:1; /*!< bit: 5 DownStream to Device Interrupt Disable */
+ uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume from Device Interrupt Disable */
+ uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Disable */
+ uint16_t DCONN:1; /*!< bit: 8 Device Connection Interrupt Disable */
+ uint16_t DDISC:1; /*!< bit: 9 Device Disconnection Interrupt Disable */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} USB_HOST_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -545,20 +545,20 @@ typedef union {
/* -------- USB_DEVICE_INTENSET : (USB Offset: 0x018) (R/W 16) DEVICE DEVICE Device Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t SUSPEND:1; /*!< bit: 0 Suspend Interrupt Enable */
- uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame Interrupt Enable in High Speed Mode */
- uint16_t SOF:1; /*!< bit: 2 Start Of Frame Interrupt Enable */
- uint16_t EORST:1; /*!< bit: 3 End of Reset Interrupt Enable */
- uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */
- uint16_t EORSM:1; /*!< bit: 5 End Of Resume Interrupt Enable */
- uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume Interrupt Enable */
- uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */
- uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet Interrupt Enable */
- uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend Interrupt Enable */
- uint16_t :6; /*!< bit: 10..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t SUSPEND:1; /*!< bit: 0 Suspend Interrupt Enable */
+ uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame Interrupt Enable in High Speed Mode */
+ uint16_t SOF:1; /*!< bit: 2 Start Of Frame Interrupt Enable */
+ uint16_t EORST:1; /*!< bit: 3 End of Reset Interrupt Enable */
+ uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */
+ uint16_t EORSM:1; /*!< bit: 5 End Of Resume Interrupt Enable */
+ uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume Interrupt Enable */
+ uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */
+ uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet Interrupt Enable */
+ uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend Interrupt Enable */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} USB_DEVICE_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -590,19 +590,19 @@ typedef union {
/* -------- USB_HOST_INTENSET : (USB Offset: 0x018) (R/W 16) HOST HOST Host Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t :2; /*!< bit: 0.. 1 Reserved */
- uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame Interrupt Enable */
- uint16_t RST:1; /*!< bit: 3 Bus Reset Interrupt Enable */
- uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */
- uint16_t DNRSM:1; /*!< bit: 5 DownStream to the Device Interrupt Enable */
- uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume fromthe device Interrupt Enable */
- uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */
- uint16_t DCONN:1; /*!< bit: 8 Link Power Management Interrupt Enable */
- uint16_t DDISC:1; /*!< bit: 9 Device Disconnection Interrupt Enable */
- uint16_t :6; /*!< bit: 10..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t :2; /*!< bit: 0.. 1 Reserved */
+ uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame Interrupt Enable */
+ uint16_t RST:1; /*!< bit: 3 Bus Reset Interrupt Enable */
+ uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */
+ uint16_t DNRSM:1; /*!< bit: 5 DownStream to the Device Interrupt Enable */
+ uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume fromthe device Interrupt Enable */
+ uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */
+ uint16_t DCONN:1; /*!< bit: 8 Link Power Management Interrupt Enable */
+ uint16_t DDISC:1; /*!< bit: 9 Device Disconnection Interrupt Enable */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} USB_HOST_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -630,20 +630,20 @@ typedef union {
/* -------- USB_DEVICE_INTFLAG : (USB Offset: 0x01C) (R/W 16) DEVICE DEVICE Device Interrupt Flag -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint16_t SUSPEND:1; /*!< bit: 0 Suspend */
- __I uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame in High Speed Mode */
- __I uint16_t SOF:1; /*!< bit: 2 Start Of Frame */
- __I uint16_t EORST:1; /*!< bit: 3 End of Reset */
- __I uint16_t WAKEUP:1; /*!< bit: 4 Wake Up */
- __I uint16_t EORSM:1; /*!< bit: 5 End Of Resume */
- __I uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume */
- __I uint16_t RAMACER:1; /*!< bit: 7 Ram Access */
- __I uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet */
- __I uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend */
- __I uint16_t :6; /*!< bit: 10..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ __I uint16_t SUSPEND:1; /*!< bit: 0 Suspend */
+ __I uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame in High Speed Mode */
+ __I uint16_t SOF:1; /*!< bit: 2 Start Of Frame */
+ __I uint16_t EORST:1; /*!< bit: 3 End of Reset */
+ __I uint16_t WAKEUP:1; /*!< bit: 4 Wake Up */
+ __I uint16_t EORSM:1; /*!< bit: 5 End Of Resume */
+ __I uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume */
+ __I uint16_t RAMACER:1; /*!< bit: 7 Ram Access */
+ __I uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet */
+ __I uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend */
+ __I uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} USB_DEVICE_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -675,19 +675,19 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register
/* -------- USB_HOST_INTFLAG : (USB Offset: 0x01C) (R/W 16) HOST HOST Host Interrupt Flag -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint16_t :2; /*!< bit: 0.. 1 Reserved */
- __I uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame */
- __I uint16_t RST:1; /*!< bit: 3 Bus Reset */
- __I uint16_t WAKEUP:1; /*!< bit: 4 Wake Up */
- __I uint16_t DNRSM:1; /*!< bit: 5 Downstream */
- __I uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume from the Device */
- __I uint16_t RAMACER:1; /*!< bit: 7 Ram Access */
- __I uint16_t DCONN:1; /*!< bit: 8 Device Connection */
- __I uint16_t DDISC:1; /*!< bit: 9 Device Disconnection */
- __I uint16_t :6; /*!< bit: 10..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ __I uint16_t :2; /*!< bit: 0.. 1 Reserved */
+ __I uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame */
+ __I uint16_t RST:1; /*!< bit: 3 Bus Reset */
+ __I uint16_t WAKEUP:1; /*!< bit: 4 Wake Up */
+ __I uint16_t DNRSM:1; /*!< bit: 5 Downstream */
+ __I uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume from the Device */
+ __I uint16_t RAMACER:1; /*!< bit: 7 Ram Access */
+ __I uint16_t DCONN:1; /*!< bit: 8 Device Connection */
+ __I uint16_t DDISC:1; /*!< bit: 9 Device Disconnection */
+ __I uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} USB_HOST_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -715,22 +715,22 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register
/* -------- USB_DEVICE_EPINTSMRY : (USB Offset: 0x020) (R/ 16) DEVICE DEVICE End Point Interrupt Summary -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t EPINT0:1; /*!< bit: 0 End Point 0 Interrupt */
- uint16_t EPINT1:1; /*!< bit: 1 End Point 1 Interrupt */
- uint16_t EPINT2:1; /*!< bit: 2 End Point 2 Interrupt */
- uint16_t EPINT3:1; /*!< bit: 3 End Point 3 Interrupt */
- uint16_t EPINT4:1; /*!< bit: 4 End Point 4 Interrupt */
- uint16_t EPINT5:1; /*!< bit: 5 End Point 5 Interrupt */
- uint16_t EPINT6:1; /*!< bit: 6 End Point 6 Interrupt */
- uint16_t EPINT7:1; /*!< bit: 7 End Point 7 Interrupt */
- uint16_t :8; /*!< bit: 8..15 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint16_t EPINT:8; /*!< bit: 0.. 7 End Point x Interrupt */
- uint16_t :8; /*!< bit: 8..15 Reserved */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t EPINT0:1; /*!< bit: 0 End Point 0 Interrupt */
+ uint16_t EPINT1:1; /*!< bit: 1 End Point 1 Interrupt */
+ uint16_t EPINT2:1; /*!< bit: 2 End Point 2 Interrupt */
+ uint16_t EPINT3:1; /*!< bit: 3 End Point 3 Interrupt */
+ uint16_t EPINT4:1; /*!< bit: 4 End Point 4 Interrupt */
+ uint16_t EPINT5:1; /*!< bit: 5 End Point 5 Interrupt */
+ uint16_t EPINT6:1; /*!< bit: 6 End Point 6 Interrupt */
+ uint16_t EPINT7:1; /*!< bit: 7 End Point 7 Interrupt */
+ uint16_t :8; /*!< bit: 8..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t EPINT:8; /*!< bit: 0.. 7 End Point x Interrupt */
+ uint16_t :8; /*!< bit: 8..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
} USB_DEVICE_EPINTSMRY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -761,22 +761,22 @@ typedef union {
/* -------- USB_HOST_PINTSMRY : (USB Offset: 0x020) (R/ 16) HOST HOST Pipe Interrupt Summary -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t EPINT0:1; /*!< bit: 0 Pipe 0 Interrupt */
- uint16_t EPINT1:1; /*!< bit: 1 Pipe 1 Interrupt */
- uint16_t EPINT2:1; /*!< bit: 2 Pipe 2 Interrupt */
- uint16_t EPINT3:1; /*!< bit: 3 Pipe 3 Interrupt */
- uint16_t EPINT4:1; /*!< bit: 4 Pipe 4 Interrupt */
- uint16_t EPINT5:1; /*!< bit: 5 Pipe 5 Interrupt */
- uint16_t EPINT6:1; /*!< bit: 6 Pipe 6 Interrupt */
- uint16_t EPINT7:1; /*!< bit: 7 Pipe 7 Interrupt */
- uint16_t :8; /*!< bit: 8..15 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint16_t EPINT:8; /*!< bit: 0.. 7 Pipe x Interrupt */
- uint16_t :8; /*!< bit: 8..15 Reserved */
- } vec; /*!< Structure used for vec access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t EPINT0:1; /*!< bit: 0 Pipe 0 Interrupt */
+ uint16_t EPINT1:1; /*!< bit: 1 Pipe 1 Interrupt */
+ uint16_t EPINT2:1; /*!< bit: 2 Pipe 2 Interrupt */
+ uint16_t EPINT3:1; /*!< bit: 3 Pipe 3 Interrupt */
+ uint16_t EPINT4:1; /*!< bit: 4 Pipe 4 Interrupt */
+ uint16_t EPINT5:1; /*!< bit: 5 Pipe 5 Interrupt */
+ uint16_t EPINT6:1; /*!< bit: 6 Pipe 6 Interrupt */
+ uint16_t EPINT7:1; /*!< bit: 7 Pipe 7 Interrupt */
+ uint16_t :8; /*!< bit: 8..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t EPINT:8; /*!< bit: 0.. 7 Pipe x Interrupt */
+ uint16_t :8; /*!< bit: 8..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
} USB_HOST_PINTSMRY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -807,10 +807,10 @@ typedef union {
/* -------- USB_DESCADD : (USB Offset: 0x024) (R/W 32) Descriptor Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t DESCADD:32; /*!< bit: 0..31 Descriptor Address Value */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t DESCADD:32; /*!< bit: 0..31 Descriptor Address Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} USB_DESCADD_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -825,15 +825,15 @@ typedef union {
/* -------- USB_PADCAL : (USB Offset: 0x028) (R/W 16) USB PAD Calibration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t TRANSP:5; /*!< bit: 0.. 4 USB Pad Transp calibration */
- uint16_t :1; /*!< bit: 5 Reserved */
- uint16_t TRANSN:5; /*!< bit: 6..10 USB Pad Transn calibration */
- uint16_t :1; /*!< bit: 11 Reserved */
- uint16_t TRIM:3; /*!< bit: 12..14 USB Pad Trim calibration */
- uint16_t :1; /*!< bit: 15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t TRANSP:5; /*!< bit: 0.. 4 USB Pad Transp calibration */
+ uint16_t :1; /*!< bit: 5 Reserved */
+ uint16_t TRANSN:5; /*!< bit: 6..10 USB Pad Transn calibration */
+ uint16_t :1; /*!< bit: 11 Reserved */
+ uint16_t TRIM:3; /*!< bit: 12..14 USB Pad Trim calibration */
+ uint16_t :1; /*!< bit: 15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} USB_PADCAL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -854,13 +854,13 @@ typedef union {
/* -------- USB_DEVICE_EPCFG : (USB Offset: 0x100) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t EPTYPE0:3; /*!< bit: 0.. 2 End Point Type0 */
- uint8_t :1; /*!< bit: 3 Reserved */
- uint8_t EPTYPE1:3; /*!< bit: 4.. 6 End Point Type1 */
- uint8_t NYETDIS:1; /*!< bit: 7 NYET Token Disable */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t EPTYPE0:3; /*!< bit: 0.. 2 End Point Type0 */
+ uint8_t :1; /*!< bit: 3 Reserved */
+ uint8_t EPTYPE1:3; /*!< bit: 4.. 6 End Point Type1 */
+ uint8_t NYETDIS:1; /*!< bit: 7 NYET Token Disable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} USB_DEVICE_EPCFG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -880,13 +880,13 @@ typedef union {
/* -------- USB_HOST_PCFG : (USB Offset: 0x100) (R/W 8) HOST HOST_PIPE End Point Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t PTOKEN:2; /*!< bit: 0.. 1 Pipe Token */
- uint8_t BK:1; /*!< bit: 2 Pipe Bank */
- uint8_t PTYPE:3; /*!< bit: 3.. 5 Pipe Type */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t PTOKEN:2; /*!< bit: 0.. 1 Pipe Token */
+ uint8_t BK:1; /*!< bit: 2 Pipe Bank */
+ uint8_t PTYPE:3; /*!< bit: 3.. 5 Pipe Type */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} USB_HOST_PCFG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -906,10 +906,10 @@ typedef union {
/* -------- USB_HOST_BINTERVAL : (USB Offset: 0x103) (R/W 8) HOST HOST_PIPE Bus Access Period of Pipe -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t BITINTERVAL:8; /*!< bit: 0.. 7 Bit Interval */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t BITINTERVAL:8; /*!< bit: 0.. 7 Bit Interval */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} USB_HOST_BINTERVAL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -924,22 +924,22 @@ typedef union {
/* -------- USB_DEVICE_EPSTATUSCLR : (USB Offset: 0x104) ( /W 8) DEVICE DEVICE_ENDPOINT End Point Pipe Status Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle OUT Clear */
- uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle IN Clear */
- uint8_t CURBK:1; /*!< bit: 2 Curren Bank Clear */
- uint8_t :1; /*!< bit: 3 Reserved */
- uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request Clear */
- uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request Clear */
- uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Clear */
- uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Clear */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t :4; /*!< bit: 0.. 3 Reserved */
- uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request Clear */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle OUT Clear */
+ uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle IN Clear */
+ uint8_t CURBK:1; /*!< bit: 2 Curren Bank Clear */
+ uint8_t :1; /*!< bit: 3 Reserved */
+ uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request Clear */
+ uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request Clear */
+ uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Clear */
+ uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Clear */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t :4; /*!< bit: 0.. 3 Reserved */
+ uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request Clear */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} USB_DEVICE_EPSTATUSCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -968,17 +968,17 @@ typedef union {
/* -------- USB_HOST_PSTATUSCLR : (USB Offset: 0x104) ( /W 8) HOST HOST_PIPE End Point Pipe Status Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DTGL:1; /*!< bit: 0 Data Toggle clear */
- uint8_t :1; /*!< bit: 1 Reserved */
- uint8_t CURBK:1; /*!< bit: 2 Curren Bank clear */
- uint8_t :1; /*!< bit: 3 Reserved */
- uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze Clear */
- uint8_t :1; /*!< bit: 5 Reserved */
- uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Clear */
- uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Clear */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DTGL:1; /*!< bit: 0 Data Toggle clear */
+ uint8_t :1; /*!< bit: 1 Reserved */
+ uint8_t CURBK:1; /*!< bit: 2 Curren Bank clear */
+ uint8_t :1; /*!< bit: 3 Reserved */
+ uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze Clear */
+ uint8_t :1; /*!< bit: 5 Reserved */
+ uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Clear */
+ uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Clear */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} USB_HOST_PSTATUSCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1000,22 +1000,22 @@ typedef union {
/* -------- USB_DEVICE_EPSTATUSSET : (USB Offset: 0x105) ( /W 8) DEVICE DEVICE_ENDPOINT End Point Pipe Status Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle OUT Set */
- uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle IN Set */
- uint8_t CURBK:1; /*!< bit: 2 Current Bank Set */
- uint8_t :1; /*!< bit: 3 Reserved */
- uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request Set */
- uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request Set */
- uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Set */
- uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Set */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t :4; /*!< bit: 0.. 3 Reserved */
- uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request Set */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle OUT Set */
+ uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle IN Set */
+ uint8_t CURBK:1; /*!< bit: 2 Current Bank Set */
+ uint8_t :1; /*!< bit: 3 Reserved */
+ uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request Set */
+ uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request Set */
+ uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Set */
+ uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Set */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t :4; /*!< bit: 0.. 3 Reserved */
+ uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request Set */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} USB_DEVICE_EPSTATUSSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1044,17 +1044,17 @@ typedef union {
/* -------- USB_HOST_PSTATUSSET : (USB Offset: 0x105) ( /W 8) HOST HOST_PIPE End Point Pipe Status Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DTGL:1; /*!< bit: 0 Data Toggle Set */
- uint8_t :1; /*!< bit: 1 Reserved */
- uint8_t CURBK:1; /*!< bit: 2 Current Bank Set */
- uint8_t :1; /*!< bit: 3 Reserved */
- uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze Set */
- uint8_t :1; /*!< bit: 5 Reserved */
- uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Set */
- uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Set */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DTGL:1; /*!< bit: 0 Data Toggle Set */
+ uint8_t :1; /*!< bit: 1 Reserved */
+ uint8_t CURBK:1; /*!< bit: 2 Current Bank Set */
+ uint8_t :1; /*!< bit: 3 Reserved */
+ uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze Set */
+ uint8_t :1; /*!< bit: 5 Reserved */
+ uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Set */
+ uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Set */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} USB_HOST_PSTATUSSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1076,22 +1076,22 @@ typedef union {
/* -------- USB_DEVICE_EPSTATUS : (USB Offset: 0x106) (R/ 8) DEVICE DEVICE_ENDPOINT End Point Pipe Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle Out */
- uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle In */
- uint8_t CURBK:1; /*!< bit: 2 Current Bank */
- uint8_t :1; /*!< bit: 3 Reserved */
- uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request */
- uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request */
- uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 ready */
- uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 ready */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t :4; /*!< bit: 0.. 3 Reserved */
- uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle Out */
+ uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle In */
+ uint8_t CURBK:1; /*!< bit: 2 Current Bank */
+ uint8_t :1; /*!< bit: 3 Reserved */
+ uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request */
+ uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request */
+ uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 ready */
+ uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 ready */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t :4; /*!< bit: 0.. 3 Reserved */
+ uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} USB_DEVICE_EPSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1120,17 +1120,17 @@ typedef union {
/* -------- USB_HOST_PSTATUS : (USB Offset: 0x106) (R/ 8) HOST HOST_PIPE End Point Pipe Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t DTGL:1; /*!< bit: 0 Data Toggle */
- uint8_t :1; /*!< bit: 1 Reserved */
- uint8_t CURBK:1; /*!< bit: 2 Current Bank */
- uint8_t :1; /*!< bit: 3 Reserved */
- uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze */
- uint8_t :1; /*!< bit: 5 Reserved */
- uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 ready */
- uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 ready */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t DTGL:1; /*!< bit: 0 Data Toggle */
+ uint8_t :1; /*!< bit: 1 Reserved */
+ uint8_t CURBK:1; /*!< bit: 2 Current Bank */
+ uint8_t :1; /*!< bit: 3 Reserved */
+ uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze */
+ uint8_t :1; /*!< bit: 5 Reserved */
+ uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 ready */
+ uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 ready */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} USB_HOST_PSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1152,24 +1152,24 @@ typedef union {
/* -------- USB_DEVICE_EPINTFLAG : (USB Offset: 0x107) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Interrupt Flag -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 */
- __I uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 */
- __I uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 */
- __I uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 */
- __I uint8_t RXSTP:1; /*!< bit: 4 Received Setup */
- __I uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/out */
- __I uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/out */
- __I uint8_t :1; /*!< bit: 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- __I uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x */
- __I uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x */
- __I uint8_t :1; /*!< bit: 4 Reserved */
- __I uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/out */
- __I uint8_t :1; /*!< bit: 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ __I uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 */
+ __I uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 */
+ __I uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 */
+ __I uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 */
+ __I uint8_t RXSTP:1; /*!< bit: 4 Received Setup */
+ __I uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/out */
+ __I uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/out */
+ __I uint8_t :1; /*!< bit: 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ __I uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x */
+ __I uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x */
+ __I uint8_t :1; /*!< bit: 4 Reserved */
+ __I uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/out */
+ __I uint8_t :1; /*!< bit: 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} USB_DEVICE_EPINTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1204,20 +1204,20 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register
/* -------- USB_HOST_PINTFLAG : (USB Offset: 0x107) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Flag */
- __I uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Flag */
- __I uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Flag */
- __I uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Flag */
- __I uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Flag */
- __I uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Flag */
- __I uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- __I uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Flag */
- __I uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ __I uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Flag */
+ __I uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Flag */
+ __I uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Flag */
+ __I uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Flag */
+ __I uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Flag */
+ __I uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Flag */
+ __I uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ __I uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Flag */
+ __I uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} USB_HOST_PINTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1244,24 +1244,24 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register
/* -------- USB_DEVICE_EPINTENCLR : (USB Offset: 0x108) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Interrupt Clear Flag -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Disable */
- uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Disable */
- uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 Interrupt Disable */
- uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 Interrupt Disable */
- uint8_t RXSTP:1; /*!< bit: 4 Received Setup Interrupt Disable */
- uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/Out Interrupt Disable */
- uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/Out Interrupt Disable */
- uint8_t :1; /*!< bit: 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Disable */
- uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x Interrupt Disable */
- uint8_t :1; /*!< bit: 4 Reserved */
- uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/Out Interrupt Disable */
- uint8_t :1; /*!< bit: 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Disable */
+ uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Disable */
+ uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 Interrupt Disable */
+ uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 Interrupt Disable */
+ uint8_t RXSTP:1; /*!< bit: 4 Received Setup Interrupt Disable */
+ uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/Out Interrupt Disable */
+ uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/Out Interrupt Disable */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Disable */
+ uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x Interrupt Disable */
+ uint8_t :1; /*!< bit: 4 Reserved */
+ uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/Out Interrupt Disable */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} USB_DEVICE_EPINTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1296,20 +1296,20 @@ typedef union {
/* -------- USB_HOST_PINTENCLR : (USB Offset: 0x108) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Disable */
- uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Disable */
- uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Disable */
- uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Disable */
- uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Disable */
- uint8_t STALL:1; /*!< bit: 5 Stall Inetrrupt Disable */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Disable */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Disable */
+ uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Disable */
+ uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Disable */
+ uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Disable */
+ uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Disable */
+ uint8_t STALL:1; /*!< bit: 5 Stall Inetrrupt Disable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Disable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} USB_HOST_PINTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1336,24 +1336,24 @@ typedef union {
/* -------- USB_DEVICE_EPINTENSET : (USB Offset: 0x109) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Interrupt Set Flag -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Enable */
- uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Enable */
- uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 Interrupt Enable */
- uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 Interrupt Enable */
- uint8_t RXSTP:1; /*!< bit: 4 Received Setup Interrupt Enable */
- uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/out Interrupt enable */
- uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/out Interrupt enable */
- uint8_t :1; /*!< bit: 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Enable */
- uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x Interrupt Enable */
- uint8_t :1; /*!< bit: 4 Reserved */
- uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/out Interrupt enable */
- uint8_t :1; /*!< bit: 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Enable */
+ uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Enable */
+ uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 Interrupt Enable */
+ uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 Interrupt Enable */
+ uint8_t RXSTP:1; /*!< bit: 4 Received Setup Interrupt Enable */
+ uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/out Interrupt enable */
+ uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/out Interrupt enable */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Enable */
+ uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x Interrupt Enable */
+ uint8_t :1; /*!< bit: 4 Reserved */
+ uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/out Interrupt enable */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} USB_DEVICE_EPINTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1388,20 +1388,20 @@ typedef union {
/* -------- USB_HOST_PINTENSET : (USB Offset: 0x109) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Enable */
- uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Enable */
- uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Enable */
- uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Enable */
- uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Enable */
- uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Enable */
- uint8_t :2; /*!< bit: 6.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- struct {
- uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Enable */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } vec; /*!< Structure used for vec access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Enable */
+ uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Enable */
+ uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Enable */
+ uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Enable */
+ uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Enable */
+ uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Enable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Enable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
} USB_HOST_PINTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1428,10 +1428,10 @@ typedef union {
/* -------- USB_DEVICE_ADDR : (USB Offset: 0x000) (R/W 32) DEVICE DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t ADDR:32; /*!< bit: 0..31 Adress of data buffer */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t ADDR:32; /*!< bit: 0..31 Adress of data buffer */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} USB_DEVICE_ADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1445,10 +1445,10 @@ typedef union {
/* -------- USB_HOST_ADDR : (USB Offset: 0x000) (R/W 32) HOST HOST_DESC_BANK Host Bank, Adress of Data Buffer -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t ADDR:32; /*!< bit: 0..31 Adress of data buffer */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t ADDR:32; /*!< bit: 0..31 Adress of data buffer */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} USB_HOST_ADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1462,13 +1462,13 @@ typedef union {
/* -------- USB_DEVICE_PCKSIZE : (USB Offset: 0x004) (R/W 32) DEVICE DEVICE_DESC_BANK Endpoint Bank, Packet Size -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t BYTE_COUNT:14; /*!< bit: 0..13 Byte Count */
- uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27 Multi Packet In or Out size */
- uint32_t SIZE:3; /*!< bit: 28..30 Enpoint size */
- uint32_t AUTO_ZLP:1; /*!< bit: 31 Automatic Zero Length Packet */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t BYTE_COUNT:14; /*!< bit: 0..13 Byte Count */
+ uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27 Multi Packet In or Out size */
+ uint32_t SIZE:3; /*!< bit: 28..30 Enpoint size */
+ uint32_t AUTO_ZLP:1; /*!< bit: 31 Automatic Zero Length Packet */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} USB_DEVICE_PCKSIZE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1490,13 +1490,13 @@ typedef union {
/* -------- USB_HOST_PCKSIZE : (USB Offset: 0x004) (R/W 32) HOST HOST_DESC_BANK Host Bank, Packet Size -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint32_t BYTE_COUNT:14; /*!< bit: 0..13 Byte Count */
- uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27 Multi Packet In or Out size */
- uint32_t SIZE:3; /*!< bit: 28..30 Pipe size */
- uint32_t AUTO_ZLP:1; /*!< bit: 31 Automatic Zero Length Packet */
- } bit; /*!< Structure used for bit access */
- uint32_t reg; /*!< Type used for register access */
+ struct {
+ uint32_t BYTE_COUNT:14; /*!< bit: 0..13 Byte Count */
+ uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27 Multi Packet In or Out size */
+ uint32_t SIZE:3; /*!< bit: 28..30 Pipe size */
+ uint32_t AUTO_ZLP:1; /*!< bit: 31 Automatic Zero Length Packet */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
} USB_HOST_PCKSIZE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1518,12 +1518,12 @@ typedef union {
/* -------- USB_DEVICE_EXTREG : (USB Offset: 0x008) (R/W 16) DEVICE DEVICE_DESC_BANK Endpoint Bank, Extended -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t SUBPID:4; /*!< bit: 0.. 3 SUBPID field send with extended token */
- uint16_t VARIABLE:11; /*!< bit: 4..14 Variable field send with extended token */
- uint16_t :1; /*!< bit: 15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t SUBPID:4; /*!< bit: 0.. 3 SUBPID field send with extended token */
+ uint16_t VARIABLE:11; /*!< bit: 4..14 Variable field send with extended token */
+ uint16_t :1; /*!< bit: 15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} USB_DEVICE_EXTREG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1540,12 +1540,12 @@ typedef union {
/* -------- USB_HOST_EXTREG : (USB Offset: 0x008) (R/W 16) HOST HOST_DESC_BANK Host Bank, Extended -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t SUBPID:4; /*!< bit: 0.. 3 SUBPID field send with extended token */
- uint16_t VARIABLE:11; /*!< bit: 4..14 Variable field send with extended token */
- uint16_t :1; /*!< bit: 15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t SUBPID:4; /*!< bit: 0.. 3 SUBPID field send with extended token */
+ uint16_t VARIABLE:11; /*!< bit: 4..14 Variable field send with extended token */
+ uint16_t :1; /*!< bit: 15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} USB_HOST_EXTREG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1562,12 +1562,12 @@ typedef union {
/* -------- USB_DEVICE_STATUS_BK : (USB Offset: 0x00A) (R/W 8) DEVICE DEVICE_DESC_BANK Enpoint Bank, Status of Bank -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t CRCERR:1; /*!< bit: 0 CRC Error Status */
- uint8_t ERRORFLOW:1; /*!< bit: 1 Error Flow Status */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t CRCERR:1; /*!< bit: 0 CRC Error Status */
+ uint8_t ERRORFLOW:1; /*!< bit: 1 Error Flow Status */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} USB_DEVICE_STATUS_BK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1582,12 +1582,12 @@ typedef union {
/* -------- USB_HOST_STATUS_BK : (USB Offset: 0x00A) (R/W 8) HOST HOST_DESC_BANK Host Bank, Status of Bank -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t CRCERR:1; /*!< bit: 0 CRC Error Status */
- uint8_t ERRORFLOW:1; /*!< bit: 1 Error Flow Status */
- uint8_t :6; /*!< bit: 2.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t CRCERR:1; /*!< bit: 0 CRC Error Status */
+ uint8_t ERRORFLOW:1; /*!< bit: 1 Error Flow Status */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} USB_HOST_STATUS_BK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1602,13 +1602,13 @@ typedef union {
/* -------- USB_HOST_CTRL_PIPE : (USB Offset: 0x00C) (R/W 16) HOST HOST_DESC_BANK Host Bank, Host Control Pipe -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t PDADDR:7; /*!< bit: 0.. 6 Pipe Device Adress */
- uint16_t :1; /*!< bit: 7 Reserved */
- uint16_t PEPNUM:4; /*!< bit: 8..11 Pipe Endpoint Number */
- uint16_t PERMAX:4; /*!< bit: 12..15 Pipe Error Max Number */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t PDADDR:7; /*!< bit: 0.. 6 Pipe Device Adress */
+ uint16_t :1; /*!< bit: 7 Reserved */
+ uint16_t PEPNUM:4; /*!< bit: 8..11 Pipe Endpoint Number */
+ uint16_t PERMAX:4; /*!< bit: 12..15 Pipe Error Max Number */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} USB_HOST_CTRL_PIPE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1629,16 +1629,16 @@ typedef union {
/* -------- USB_HOST_STATUS_PIPE : (USB Offset: 0x00E) (R/W 16) HOST HOST_DESC_BANK Host Bank, Host Status Pipe -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint16_t DTGLER:1; /*!< bit: 0 Data Toggle Error */
- uint16_t DAPIDER:1; /*!< bit: 1 Data PID Error */
- uint16_t PIDER:1; /*!< bit: 2 PID Error */
- uint16_t TOUTER:1; /*!< bit: 3 Time Out Error */
- uint16_t CRC16ER:1; /*!< bit: 4 CRC16 Error */
- uint16_t ERCNT:3; /*!< bit: 5.. 7 Pipe Error Count */
- uint16_t :8; /*!< bit: 8..15 Reserved */
- } bit; /*!< Structure used for bit access */
- uint16_t reg; /*!< Type used for register access */
+ struct {
+ uint16_t DTGLER:1; /*!< bit: 0 Data Toggle Error */
+ uint16_t DAPIDER:1; /*!< bit: 1 Data PID Error */
+ uint16_t PIDER:1; /*!< bit: 2 PID Error */
+ uint16_t TOUTER:1; /*!< bit: 3 Time Out Error */
+ uint16_t CRC16ER:1; /*!< bit: 4 CRC16 Error */
+ uint16_t ERCNT:3; /*!< bit: 5.. 7 Pipe Error Count */
+ uint16_t :8; /*!< bit: 8..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
} USB_HOST_STATUS_PIPE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -1662,140 +1662,140 @@ typedef union {
/** \brief UsbDeviceDescBank SRAM registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO USB_DEVICE_ADDR_Type ADDR; /**< \brief Offset: 0x000 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer */
- __IO USB_DEVICE_PCKSIZE_Type PCKSIZE; /**< \brief Offset: 0x004 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Packet Size */
- __IO USB_DEVICE_EXTREG_Type EXTREG; /**< \brief Offset: 0x008 (R/W 16) DEVICE_DESC_BANK Endpoint Bank, Extended */
- __IO USB_DEVICE_STATUS_BK_Type STATUS_BK; /**< \brief Offset: 0x00A (R/W 8) DEVICE_DESC_BANK Enpoint Bank, Status of Bank */
- RoReg8 Reserved1[0x5];
+ __IO USB_DEVICE_ADDR_Type ADDR; /**< \brief Offset: 0x000 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer */
+ __IO USB_DEVICE_PCKSIZE_Type PCKSIZE; /**< \brief Offset: 0x004 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Packet Size */
+ __IO USB_DEVICE_EXTREG_Type EXTREG; /**< \brief Offset: 0x008 (R/W 16) DEVICE_DESC_BANK Endpoint Bank, Extended */
+ __IO USB_DEVICE_STATUS_BK_Type STATUS_BK; /**< \brief Offset: 0x00A (R/W 8) DEVICE_DESC_BANK Enpoint Bank, Status of Bank */
+ RoReg8 Reserved1[0x5];
} UsbDeviceDescBank;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief UsbHostDescBank SRAM registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO USB_HOST_ADDR_Type ADDR; /**< \brief Offset: 0x000 (R/W 32) HOST_DESC_BANK Host Bank, Adress of Data Buffer */
- __IO USB_HOST_PCKSIZE_Type PCKSIZE; /**< \brief Offset: 0x004 (R/W 32) HOST_DESC_BANK Host Bank, Packet Size */
- __IO USB_HOST_EXTREG_Type EXTREG; /**< \brief Offset: 0x008 (R/W 16) HOST_DESC_BANK Host Bank, Extended */
- __IO USB_HOST_STATUS_BK_Type STATUS_BK; /**< \brief Offset: 0x00A (R/W 8) HOST_DESC_BANK Host Bank, Status of Bank */
- RoReg8 Reserved1[0x1];
- __IO USB_HOST_CTRL_PIPE_Type CTRL_PIPE; /**< \brief Offset: 0x00C (R/W 16) HOST_DESC_BANK Host Bank, Host Control Pipe */
- __IO USB_HOST_STATUS_PIPE_Type STATUS_PIPE; /**< \brief Offset: 0x00E (R/W 16) HOST_DESC_BANK Host Bank, Host Status Pipe */
+ __IO USB_HOST_ADDR_Type ADDR; /**< \brief Offset: 0x000 (R/W 32) HOST_DESC_BANK Host Bank, Adress of Data Buffer */
+ __IO USB_HOST_PCKSIZE_Type PCKSIZE; /**< \brief Offset: 0x004 (R/W 32) HOST_DESC_BANK Host Bank, Packet Size */
+ __IO USB_HOST_EXTREG_Type EXTREG; /**< \brief Offset: 0x008 (R/W 16) HOST_DESC_BANK Host Bank, Extended */
+ __IO USB_HOST_STATUS_BK_Type STATUS_BK; /**< \brief Offset: 0x00A (R/W 8) HOST_DESC_BANK Host Bank, Status of Bank */
+ RoReg8 Reserved1[0x1];
+ __IO USB_HOST_CTRL_PIPE_Type CTRL_PIPE; /**< \brief Offset: 0x00C (R/W 16) HOST_DESC_BANK Host Bank, Host Control Pipe */
+ __IO USB_HOST_STATUS_PIPE_Type STATUS_PIPE; /**< \brief Offset: 0x00E (R/W 16) HOST_DESC_BANK Host Bank, Host Status Pipe */
} UsbHostDescBank;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief UsbDeviceEndpoint hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO USB_DEVICE_EPCFG_Type EPCFG; /**< \brief Offset: 0x000 (R/W 8) DEVICE_ENDPOINT End Point Configuration */
- RoReg8 Reserved1[0x3];
- __O USB_DEVICE_EPSTATUSCLR_Type EPSTATUSCLR; /**< \brief Offset: 0x004 ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Clear */
- __O USB_DEVICE_EPSTATUSSET_Type EPSTATUSSET; /**< \brief Offset: 0x005 ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Set */
- __I USB_DEVICE_EPSTATUS_Type EPSTATUS; /**< \brief Offset: 0x006 (R/ 8) DEVICE_ENDPOINT End Point Pipe Status */
- __IO USB_DEVICE_EPINTFLAG_Type EPINTFLAG; /**< \brief Offset: 0x007 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Flag */
- __IO USB_DEVICE_EPINTENCLR_Type EPINTENCLR; /**< \brief Offset: 0x008 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Clear Flag */
- __IO USB_DEVICE_EPINTENSET_Type EPINTENSET; /**< \brief Offset: 0x009 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Set Flag */
- RoReg8 Reserved2[0x16];
+ __IO USB_DEVICE_EPCFG_Type EPCFG; /**< \brief Offset: 0x000 (R/W 8) DEVICE_ENDPOINT End Point Configuration */
+ RoReg8 Reserved1[0x3];
+ __O USB_DEVICE_EPSTATUSCLR_Type EPSTATUSCLR; /**< \brief Offset: 0x004 ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Clear */
+ __O USB_DEVICE_EPSTATUSSET_Type EPSTATUSSET; /**< \brief Offset: 0x005 ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Set */
+ __I USB_DEVICE_EPSTATUS_Type EPSTATUS; /**< \brief Offset: 0x006 (R/ 8) DEVICE_ENDPOINT End Point Pipe Status */
+ __IO USB_DEVICE_EPINTFLAG_Type EPINTFLAG; /**< \brief Offset: 0x007 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Flag */
+ __IO USB_DEVICE_EPINTENCLR_Type EPINTENCLR; /**< \brief Offset: 0x008 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Clear Flag */
+ __IO USB_DEVICE_EPINTENSET_Type EPINTENSET; /**< \brief Offset: 0x009 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Set Flag */
+ RoReg8 Reserved2[0x16];
} UsbDeviceEndpoint;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief UsbHostPipe hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO USB_HOST_PCFG_Type PCFG; /**< \brief Offset: 0x000 (R/W 8) HOST_PIPE End Point Configuration */
- RoReg8 Reserved1[0x2];
- __IO USB_HOST_BINTERVAL_Type BINTERVAL; /**< \brief Offset: 0x003 (R/W 8) HOST_PIPE Bus Access Period of Pipe */
- __O USB_HOST_PSTATUSCLR_Type PSTATUSCLR; /**< \brief Offset: 0x004 ( /W 8) HOST_PIPE End Point Pipe Status Clear */
- __O USB_HOST_PSTATUSSET_Type PSTATUSSET; /**< \brief Offset: 0x005 ( /W 8) HOST_PIPE End Point Pipe Status Set */
- __I USB_HOST_PSTATUS_Type PSTATUS; /**< \brief Offset: 0x006 (R/ 8) HOST_PIPE End Point Pipe Status */
- __IO USB_HOST_PINTFLAG_Type PINTFLAG; /**< \brief Offset: 0x007 (R/W 8) HOST_PIPE Pipe Interrupt Flag */
- __IO USB_HOST_PINTENCLR_Type PINTENCLR; /**< \brief Offset: 0x008 (R/W 8) HOST_PIPE Pipe Interrupt Flag Clear */
- __IO USB_HOST_PINTENSET_Type PINTENSET; /**< \brief Offset: 0x009 (R/W 8) HOST_PIPE Pipe Interrupt Flag Set */
- RoReg8 Reserved2[0x16];
+ __IO USB_HOST_PCFG_Type PCFG; /**< \brief Offset: 0x000 (R/W 8) HOST_PIPE End Point Configuration */
+ RoReg8 Reserved1[0x2];
+ __IO USB_HOST_BINTERVAL_Type BINTERVAL; /**< \brief Offset: 0x003 (R/W 8) HOST_PIPE Bus Access Period of Pipe */
+ __O USB_HOST_PSTATUSCLR_Type PSTATUSCLR; /**< \brief Offset: 0x004 ( /W 8) HOST_PIPE End Point Pipe Status Clear */
+ __O USB_HOST_PSTATUSSET_Type PSTATUSSET; /**< \brief Offset: 0x005 ( /W 8) HOST_PIPE End Point Pipe Status Set */
+ __I USB_HOST_PSTATUS_Type PSTATUS; /**< \brief Offset: 0x006 (R/ 8) HOST_PIPE End Point Pipe Status */
+ __IO USB_HOST_PINTFLAG_Type PINTFLAG; /**< \brief Offset: 0x007 (R/W 8) HOST_PIPE Pipe Interrupt Flag */
+ __IO USB_HOST_PINTENCLR_Type PINTENCLR; /**< \brief Offset: 0x008 (R/W 8) HOST_PIPE Pipe Interrupt Flag Clear */
+ __IO USB_HOST_PINTENSET_Type PINTENSET; /**< \brief Offset: 0x009 (R/W 8) HOST_PIPE Pipe Interrupt Flag Set */
+ RoReg8 Reserved2[0x16];
} UsbHostPipe;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief USB_DEVICE APB hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* USB is Device */
- __IO USB_CTRLA_Type CTRLA; /**< \brief Offset: 0x000 (R/W 8) Control A */
- RoReg8 Reserved1[0x1];
- __I USB_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x002 (R/ 8) Synchronization Busy */
- __IO USB_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x003 (R/W 8) USB Quality Of Service */
- RoReg8 Reserved2[0x4];
- __IO USB_DEVICE_CTRLB_Type CTRLB; /**< \brief Offset: 0x008 (R/W 16) DEVICE Control B */
- __IO USB_DEVICE_DADD_Type DADD; /**< \brief Offset: 0x00A (R/W 8) DEVICE Device Address */
- RoReg8 Reserved3[0x1];
- __I USB_DEVICE_STATUS_Type STATUS; /**< \brief Offset: 0x00C (R/ 8) DEVICE Status */
- __I USB_FSMSTATUS_Type FSMSTATUS; /**< \brief Offset: 0x00D (R/ 8) Finite State Machine Status */
- RoReg8 Reserved4[0x2];
- __I USB_DEVICE_FNUM_Type FNUM; /**< \brief Offset: 0x010 (R/ 16) DEVICE Device Frame Number */
- RoReg8 Reserved5[0x2];
- __IO USB_DEVICE_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x014 (R/W 16) DEVICE Device Interrupt Enable Clear */
- RoReg8 Reserved6[0x2];
- __IO USB_DEVICE_INTENSET_Type INTENSET; /**< \brief Offset: 0x018 (R/W 16) DEVICE Device Interrupt Enable Set */
- RoReg8 Reserved7[0x2];
- __IO USB_DEVICE_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x01C (R/W 16) DEVICE Device Interrupt Flag */
- RoReg8 Reserved8[0x2];
- __I USB_DEVICE_EPINTSMRY_Type EPINTSMRY; /**< \brief Offset: 0x020 (R/ 16) DEVICE End Point Interrupt Summary */
- RoReg8 Reserved9[0x2];
- __IO USB_DESCADD_Type DESCADD; /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */
- __IO USB_PADCAL_Type PADCAL; /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */
- RoReg8 Reserved10[0xD6];
- UsbDeviceEndpoint DeviceEndpoint[8]; /**< \brief Offset: 0x100 UsbDeviceEndpoint groups [EPT_NUM] */
+ __IO USB_CTRLA_Type CTRLA; /**< \brief Offset: 0x000 (R/W 8) Control A */
+ RoReg8 Reserved1[0x1];
+ __I USB_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x002 (R/ 8) Synchronization Busy */
+ __IO USB_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x003 (R/W 8) USB Quality Of Service */
+ RoReg8 Reserved2[0x4];
+ __IO USB_DEVICE_CTRLB_Type CTRLB; /**< \brief Offset: 0x008 (R/W 16) DEVICE Control B */
+ __IO USB_DEVICE_DADD_Type DADD; /**< \brief Offset: 0x00A (R/W 8) DEVICE Device Address */
+ RoReg8 Reserved3[0x1];
+ __I USB_DEVICE_STATUS_Type STATUS; /**< \brief Offset: 0x00C (R/ 8) DEVICE Status */
+ __I USB_FSMSTATUS_Type FSMSTATUS; /**< \brief Offset: 0x00D (R/ 8) Finite State Machine Status */
+ RoReg8 Reserved4[0x2];
+ __I USB_DEVICE_FNUM_Type FNUM; /**< \brief Offset: 0x010 (R/ 16) DEVICE Device Frame Number */
+ RoReg8 Reserved5[0x2];
+ __IO USB_DEVICE_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x014 (R/W 16) DEVICE Device Interrupt Enable Clear */
+ RoReg8 Reserved6[0x2];
+ __IO USB_DEVICE_INTENSET_Type INTENSET; /**< \brief Offset: 0x018 (R/W 16) DEVICE Device Interrupt Enable Set */
+ RoReg8 Reserved7[0x2];
+ __IO USB_DEVICE_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x01C (R/W 16) DEVICE Device Interrupt Flag */
+ RoReg8 Reserved8[0x2];
+ __I USB_DEVICE_EPINTSMRY_Type EPINTSMRY; /**< \brief Offset: 0x020 (R/ 16) DEVICE End Point Interrupt Summary */
+ RoReg8 Reserved9[0x2];
+ __IO USB_DESCADD_Type DESCADD; /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */
+ __IO USB_PADCAL_Type PADCAL; /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */
+ RoReg8 Reserved10[0xD6];
+ UsbDeviceEndpoint DeviceEndpoint[8]; /**< \brief Offset: 0x100 UsbDeviceEndpoint groups [EPT_NUM] */
} UsbDevice;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief USB_HOST hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* USB is Host */
- __IO USB_CTRLA_Type CTRLA; /**< \brief Offset: 0x000 (R/W 8) Control A */
- RoReg8 Reserved1[0x1];
- __I USB_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x002 (R/ 8) Synchronization Busy */
- __IO USB_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x003 (R/W 8) USB Quality Of Service */
- RoReg8 Reserved2[0x4];
- __IO USB_HOST_CTRLB_Type CTRLB; /**< \brief Offset: 0x008 (R/W 16) HOST Control B */
- __IO USB_HOST_HSOFC_Type HSOFC; /**< \brief Offset: 0x00A (R/W 8) HOST Host Start Of Frame Control */
- RoReg8 Reserved3[0x1];
- __IO USB_HOST_STATUS_Type STATUS; /**< \brief Offset: 0x00C (R/W 8) HOST Status */
- __I USB_FSMSTATUS_Type FSMSTATUS; /**< \brief Offset: 0x00D (R/ 8) Finite State Machine Status */
- RoReg8 Reserved4[0x2];
- __IO USB_HOST_FNUM_Type FNUM; /**< \brief Offset: 0x010 (R/W 16) HOST Host Frame Number */
- __I USB_HOST_FLENHIGH_Type FLENHIGH; /**< \brief Offset: 0x012 (R/ 8) HOST Host Frame Length */
- RoReg8 Reserved5[0x1];
- __IO USB_HOST_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x014 (R/W 16) HOST Host Interrupt Enable Clear */
- RoReg8 Reserved6[0x2];
- __IO USB_HOST_INTENSET_Type INTENSET; /**< \brief Offset: 0x018 (R/W 16) HOST Host Interrupt Enable Set */
- RoReg8 Reserved7[0x2];
- __IO USB_HOST_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x01C (R/W 16) HOST Host Interrupt Flag */
- RoReg8 Reserved8[0x2];
- __I USB_HOST_PINTSMRY_Type PINTSMRY; /**< \brief Offset: 0x020 (R/ 16) HOST Pipe Interrupt Summary */
- RoReg8 Reserved9[0x2];
- __IO USB_DESCADD_Type DESCADD; /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */
- __IO USB_PADCAL_Type PADCAL; /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */
- RoReg8 Reserved10[0xD6];
- UsbHostPipe HostPipe[8]; /**< \brief Offset: 0x100 UsbHostPipe groups [EPT_NUM*HOST_IMPLEMENTED] */
+ __IO USB_CTRLA_Type CTRLA; /**< \brief Offset: 0x000 (R/W 8) Control A */
+ RoReg8 Reserved1[0x1];
+ __I USB_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x002 (R/ 8) Synchronization Busy */
+ __IO USB_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x003 (R/W 8) USB Quality Of Service */
+ RoReg8 Reserved2[0x4];
+ __IO USB_HOST_CTRLB_Type CTRLB; /**< \brief Offset: 0x008 (R/W 16) HOST Control B */
+ __IO USB_HOST_HSOFC_Type HSOFC; /**< \brief Offset: 0x00A (R/W 8) HOST Host Start Of Frame Control */
+ RoReg8 Reserved3[0x1];
+ __IO USB_HOST_STATUS_Type STATUS; /**< \brief Offset: 0x00C (R/W 8) HOST Status */
+ __I USB_FSMSTATUS_Type FSMSTATUS; /**< \brief Offset: 0x00D (R/ 8) Finite State Machine Status */
+ RoReg8 Reserved4[0x2];
+ __IO USB_HOST_FNUM_Type FNUM; /**< \brief Offset: 0x010 (R/W 16) HOST Host Frame Number */
+ __I USB_HOST_FLENHIGH_Type FLENHIGH; /**< \brief Offset: 0x012 (R/ 8) HOST Host Frame Length */
+ RoReg8 Reserved5[0x1];
+ __IO USB_HOST_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x014 (R/W 16) HOST Host Interrupt Enable Clear */
+ RoReg8 Reserved6[0x2];
+ __IO USB_HOST_INTENSET_Type INTENSET; /**< \brief Offset: 0x018 (R/W 16) HOST Host Interrupt Enable Set */
+ RoReg8 Reserved7[0x2];
+ __IO USB_HOST_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x01C (R/W 16) HOST Host Interrupt Flag */
+ RoReg8 Reserved8[0x2];
+ __I USB_HOST_PINTSMRY_Type PINTSMRY; /**< \brief Offset: 0x020 (R/ 16) HOST Pipe Interrupt Summary */
+ RoReg8 Reserved9[0x2];
+ __IO USB_DESCADD_Type DESCADD; /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */
+ __IO USB_PADCAL_Type PADCAL; /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */
+ RoReg8 Reserved10[0xD6];
+ UsbHostPipe HostPipe[8]; /**< \brief Offset: 0x100 UsbHostPipe groups [EPT_NUM*HOST_IMPLEMENTED] */
} UsbHost;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief USB_DEVICE Descriptor SRAM registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* USB is Device */
- UsbDeviceDescBank DeviceDescBank[2]; /**< \brief Offset: 0x000 UsbDeviceDescBank groups */
+ UsbDeviceDescBank DeviceDescBank[2]; /**< \brief Offset: 0x000 UsbDeviceDescBank groups */
} UsbDeviceDescriptor;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief USB_HOST Descriptor SRAM registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* USB is Host */
- UsbHostDescBank HostDescBank[2]; /**< \brief Offset: 0x000 UsbHostDescBank groups [2*HOST_IMPLEMENTED] */
+ UsbHostDescBank HostDescBank[2]; /**< \brief Offset: 0x000 UsbHostDescBank groups [2*HOST_IMPLEMENTED] */
} UsbHostDescriptor;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SECTION_USB_DESCRIPTOR
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- UsbDevice DEVICE; /**< \brief Offset: 0x000 USB is Device */
- UsbHost HOST; /**< \brief Offset: 0x000 USB is Host */
+ UsbDevice DEVICE; /**< \brief Offset: 0x000 USB is Device */
+ UsbHost HOST; /**< \brief Offset: 0x000 USB is Host */
} Usb;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_wdt.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_wdt.h
index 9f53b7670c5..bb4f4107191 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_wdt.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_wdt.h
@@ -56,14 +56,14 @@
/* -------- WDT_CTRL : (WDT Offset: 0x0) (R/W 8) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t :1; /*!< bit: 0 Reserved */
- uint8_t ENABLE:1; /*!< bit: 1 Enable */
- uint8_t WEN:1; /*!< bit: 2 Watchdog Timer Window Mode Enable */
- uint8_t :4; /*!< bit: 3.. 6 Reserved */
- uint8_t ALWAYSON:1; /*!< bit: 7 Always-On */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t :1; /*!< bit: 0 Reserved */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable */
+ uint8_t WEN:1; /*!< bit: 2 Watchdog Timer Window Mode Enable */
+ uint8_t :4; /*!< bit: 3.. 6 Reserved */
+ uint8_t ALWAYSON:1; /*!< bit: 7 Always-On */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} WDT_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -81,11 +81,11 @@ typedef union {
/* -------- WDT_CONFIG : (WDT Offset: 0x1) (R/W 8) Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t PER:4; /*!< bit: 0.. 3 Time-Out Period */
- uint8_t WINDOW:4; /*!< bit: 4.. 7 Window Mode Time-Out Period */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t PER:4; /*!< bit: 0.. 3 Time-Out Period */
+ uint8_t WINDOW:4; /*!< bit: 4.. 7 Window Mode Time-Out Period */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} WDT_CONFIG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -151,11 +151,11 @@ typedef union {
/* -------- WDT_EWCTRL : (WDT Offset: 0x2) (R/W 8) Early Warning Interrupt Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t EWOFFSET:4; /*!< bit: 0.. 3 Early Warning Interrupt Time Offset */
- uint8_t :4; /*!< bit: 4.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t EWOFFSET:4; /*!< bit: 0.. 3 Early Warning Interrupt Time Offset */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} WDT_EWCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -194,11 +194,11 @@ typedef union {
/* -------- WDT_INTENCLR : (WDT Offset: 0x4) (R/W 8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} WDT_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -212,11 +212,11 @@ typedef union {
/* -------- WDT_INTENSET : (WDT Offset: 0x5) (R/W 8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */
- uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} WDT_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -230,11 +230,11 @@ typedef union {
/* -------- WDT_INTFLAG : (WDT Offset: 0x6) (R/W 8) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
- struct {
- __I uint8_t EW:1; /*!< bit: 0 Early Warning */
- __I uint8_t :7; /*!< bit: 1.. 7 Reserved */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ __I uint8_t EW:1; /*!< bit: 0 Early Warning */
+ __I uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} WDT_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -248,11 +248,11 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register
/* -------- WDT_STATUS : (WDT Offset: 0x7) (R/ 8) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t :7; /*!< bit: 0.. 6 Reserved */
- uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t :7; /*!< bit: 0.. 6 Reserved */
+ uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} WDT_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -266,10 +266,10 @@ typedef union {
/* -------- WDT_CLEAR : (WDT Offset: 0x8) ( /W 8) Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
- struct {
- uint8_t CLEAR:8; /*!< bit: 0.. 7 Watchdog Clear */
- } bit; /*!< Structure used for bit access */
- uint8_t reg; /*!< Type used for register access */
+ struct {
+ uint8_t CLEAR:8; /*!< bit: 0.. 7 Watchdog Clear */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
} WDT_CLEAR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@@ -286,15 +286,15 @@ typedef union {
/** \brief WDT hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
- __IO WDT_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */
- __IO WDT_CONFIG_Type CONFIG; /**< \brief Offset: 0x1 (R/W 8) Configuration */
- __IO WDT_EWCTRL_Type EWCTRL; /**< \brief Offset: 0x2 (R/W 8) Early Warning Interrupt Control */
- RoReg8 Reserved1[0x1];
- __IO WDT_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */
- __IO WDT_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */
- __IO WDT_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */
- __I WDT_STATUS_Type STATUS; /**< \brief Offset: 0x7 (R/ 8) Status */
- __O WDT_CLEAR_Type CLEAR; /**< \brief Offset: 0x8 ( /W 8) Clear */
+ __IO WDT_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */
+ __IO WDT_CONFIG_Type CONFIG; /**< \brief Offset: 0x1 (R/W 8) Configuration */
+ __IO WDT_EWCTRL_Type EWCTRL; /**< \brief Offset: 0x2 (R/W 8) Early Warning Interrupt Control */
+ RoReg8 Reserved1[0x1];
+ __IO WDT_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */
+ __IO WDT_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */
+ __IO WDT_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */
+ __I WDT_STATUS_Type STATUS; /**< \brief Offset: 0x7 (R/ 8) Status */
+ __O WDT_CLEAR_Type CLEAR; /**< \brief Offset: 0x8 ( /W 8) Clear */
} Wdt;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_ac.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_ac.h
index ca428877ea1..18d441ec3ac 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_ac.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_ac.h
@@ -81,7 +81,7 @@
#define AC_CMP_NUM 2 // Number of comparators
#define AC_GCLK_ID_ANA 32 // Index of Generic Clock for analog
#define AC_GCLK_ID_DIG 31 // Index of Generic Clock for digital
-#define AC_NUM_CMP 2
+#define AC_NUM_CMP 2
#define AC_PAIRS 1 // Number of pairs of comparators
#endif /* _SAMR21_AC_INSTANCE_ */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_gclk.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_gclk.h
index 41bc085297a..96fd76c35f0 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_gclk.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_gclk.h
@@ -60,20 +60,20 @@
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for GCLK peripheral ========== */
-#define GCLK_GENDIV_BITS 16
+#define GCLK_GENDIV_BITS 16
#define GCLK_GEN_NUM 9 // Number of Generic Clock Generators
#define GCLK_GEN_NUM_MSB 8 // Number of Generic Clock Generators - 1
#define GCLK_GEN_SOURCE_NUM_MSB 8 // Number of Generic Clock Sources - 1
#define GCLK_NUM 37 // Number of Generic Clock Users
-#define GCLK_SOURCE_DFLL48M 7
-#define GCLK_SOURCE_FDPLL 8
-#define GCLK_SOURCE_GCLKGEN1 2
-#define GCLK_SOURCE_GCLKIN 1
+#define GCLK_SOURCE_DFLL48M 7
+#define GCLK_SOURCE_FDPLL 8
+#define GCLK_SOURCE_GCLKGEN1 2
+#define GCLK_SOURCE_GCLKIN 1
#define GCLK_SOURCE_NUM 9 // Number of Generic Clock Sources
-#define GCLK_SOURCE_OSCULP32K 3
-#define GCLK_SOURCE_OSC8M 6
-#define GCLK_SOURCE_OSC32K 4
-#define GCLK_SOURCE_XOSC 0
-#define GCLK_SOURCE_XOSC32K 5
+#define GCLK_SOURCE_OSCULP32K 3
+#define GCLK_SOURCE_OSC8M 6
+#define GCLK_SOURCE_OSC32K 4
+#define GCLK_SOURCE_XOSC 0
+#define GCLK_SOURCE_XOSC32K 5
#endif /* _SAMR21_GCLK_INSTANCE_ */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_nvmctrl.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_nvmctrl.h
index ca040fdc636..4f95860e732 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_nvmctrl.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_nvmctrl.h
@@ -74,16 +74,16 @@
#define NVMCTRL_AUX3_ADDRESS 0x0080A000
#define NVMCTRL_CLK_AHB_ID 4 // Index of AHB Clock in PM.AHBMASK register
#define NVMCTRL_FACTORY_WORD_IMPLEMENTED_MASK 0xC0000007FFFFFFFF
-#define NVMCTRL_FLASH_SIZE 262144
+#define NVMCTRL_FLASH_SIZE 262144
#define NVMCTRL_LOCKBIT_ADDRESS 0x00802000
-#define NVMCTRL_PAGES 4096
-#define NVMCTRL_PAGE_HW 32
-#define NVMCTRL_PAGE_SIZE 64
-#define NVMCTRL_PAGE_W 16
-#define NVMCTRL_PMSB 3
-#define NVMCTRL_PSZ_BITS 6
-#define NVMCTRL_ROW_PAGES 4
-#define NVMCTRL_ROW_SIZE 256
+#define NVMCTRL_PAGES 4096
+#define NVMCTRL_PAGE_HW 32
+#define NVMCTRL_PAGE_SIZE 64
+#define NVMCTRL_PAGE_W 16
+#define NVMCTRL_PMSB 3
+#define NVMCTRL_PSZ_BITS 6
+#define NVMCTRL_ROW_PAGES 4
+#define NVMCTRL_ROW_SIZE 256
#define NVMCTRL_TEMP_LOG_ADDRESS 0x00806030
#define NVMCTRL_USER_PAGE_ADDRESS 0x00800000
#define NVMCTRL_USER_PAGE_OFFSET 0x00800000
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_pm.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_pm.h
index 489baa2e6cb..c7d06c6c620 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_pm.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_pm.h
@@ -78,10 +78,10 @@
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for PM peripheral ========== */
-#define PM_CTRL_MCSEL_DFLL48M 3
-#define PM_CTRL_MCSEL_GCLK 0
-#define PM_CTRL_MCSEL_OSC8M 1
-#define PM_CTRL_MCSEL_XOSC 2
-#define PM_PM_CLK_APB_NUM 2
+#define PM_CTRL_MCSEL_DFLL48M 3
+#define PM_CTRL_MCSEL_GCLK 0
+#define PM_CTRL_MCSEL_OSC8M 1
+#define PM_CTRL_MCSEL_XOSC 2
+#define PM_PM_CLK_APB_NUM 2
#endif /* _SAMR21_PM_INSTANCE_ */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_rfctrl.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_rfctrl.h
index cab774174d4..60cdb6b2e42 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_rfctrl.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_rfctrl.h
@@ -52,6 +52,6 @@
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for RFCTRL peripheral ========== */
-#define RFCTRL_FBUSMSB 5
+#define RFCTRL_FBUSMSB 5
#endif /* _SAMR21_RFCTRL_INSTANCE_ */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_sbmatrix.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_sbmatrix.h
index 840931954e5..f8dd7396cc7 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_sbmatrix.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_sbmatrix.h
@@ -146,7 +146,7 @@
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for SBMATRIX peripheral ========== */
-#define SBMATRIX_DEFINED
+#define SBMATRIX_DEFINED
/* ========== Instance parameters for SBMATRIX ========== */
#define SBMATRIX_SLAVE_FLASH 0
#define SBMATRIX_SLAVE_HPB0 1
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom0.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom0.h
index ac8bd1b779c..1849d435317 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom0.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom0.h
@@ -138,6 +138,6 @@
#define SERCOM0_DMAC_ID_TX 2 // Index of DMA TX trigger
#define SERCOM0_GCLK_ID_CORE 20 // Index of Generic Clock for Core
#define SERCOM0_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout
-#define SERCOM0_INT_MSB 6
+#define SERCOM0_INT_MSB 6
#endif /* _SAMR21_SERCOM0_INSTANCE_ */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom1.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom1.h
index 4e732a52e60..6c0674bc2e0 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom1.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom1.h
@@ -138,6 +138,6 @@
#define SERCOM1_DMAC_ID_TX 4 // Index of DMA TX trigger
#define SERCOM1_GCLK_ID_CORE 21 // Index of Generic Clock for Core
#define SERCOM1_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout
-#define SERCOM1_INT_MSB 6
+#define SERCOM1_INT_MSB 6
#endif /* _SAMR21_SERCOM1_INSTANCE_ */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom2.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom2.h
index 3f588f005cd..517225b90c7 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom2.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom2.h
@@ -138,6 +138,6 @@
#define SERCOM2_DMAC_ID_TX 6 // Index of DMA TX trigger
#define SERCOM2_GCLK_ID_CORE 22 // Index of Generic Clock for Core
#define SERCOM2_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout
-#define SERCOM2_INT_MSB 6
+#define SERCOM2_INT_MSB 6
#endif /* _SAMR21_SERCOM2_INSTANCE_ */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom3.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom3.h
index 7eb3429c8d3..8f69e39808a 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom3.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom3.h
@@ -138,6 +138,6 @@
#define SERCOM3_DMAC_ID_TX 8 // Index of DMA TX trigger
#define SERCOM3_GCLK_ID_CORE 23 // Index of Generic Clock for Core
#define SERCOM3_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout
-#define SERCOM3_INT_MSB 6
+#define SERCOM3_INT_MSB 6
#endif /* _SAMR21_SERCOM3_INSTANCE_ */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom4.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom4.h
index f498aaecb77..52497513dfc 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom4.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom4.h
@@ -138,6 +138,6 @@
#define SERCOM4_DMAC_ID_TX 10 // Index of DMA TX trigger
#define SERCOM4_GCLK_ID_CORE 24 // Index of Generic Clock for Core
#define SERCOM4_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout
-#define SERCOM4_INT_MSB 6
+#define SERCOM4_INT_MSB 6
#endif /* _SAMR21_SERCOM4_INSTANCE_ */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom5.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom5.h
index c0dff13035e..12f9a889835 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom5.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom5.h
@@ -138,6 +138,6 @@
#define SERCOM5_DMAC_ID_TX 12 // Index of DMA TX trigger
#define SERCOM5_GCLK_ID_CORE 25 // Index of Generic Clock for Core
#define SERCOM5_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout
-#define SERCOM5_INT_MSB 6
+#define SERCOM5_INT_MSB 6
#endif /* _SAMR21_SERCOM5_INSTANCE_ */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_sysctrl.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_sysctrl.h
index 278eb5debea..d7757ad16c5 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_sysctrl.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_sysctrl.h
@@ -90,31 +90,31 @@
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for SYSCTRL peripheral ========== */
-#define SYSCTRL_BGAP_CALIB_MSB 11
-#define SYSCTRL_BOD33_CALIB_MSB 5
-#define SYSCTRL_DFLL48M_COARSE_MSB 5
-#define SYSCTRL_DFLL48M_FINE_MSB 9
+#define SYSCTRL_BGAP_CALIB_MSB 11
+#define SYSCTRL_BOD33_CALIB_MSB 5
+#define SYSCTRL_DFLL48M_COARSE_MSB 5
+#define SYSCTRL_DFLL48M_FINE_MSB 9
#define SYSCTRL_GCLK_ID_DFLL48 0 // Index of Generic Clock for DFLL48
#define SYSCTRL_GCLK_ID_FDPLL 1 // Index of Generic Clock for DPLL
#define SYSCTRL_GCLK_ID_FDPLL32K 2 // Index of Generic Clock for DPLL 32K
-#define SYSCTRL_OSC32K_COARSE_CALIB_MSB 6
-#define SYSCTRL_POR33_ENTEST_MSB 1
-#define SYSCTRL_ULPVREF_DIVLEV_MSB 3
-#define SYSCTRL_ULPVREG_FORCEGAIN_MSB 1
-#define SYSCTRL_ULPVREG_RAMREFSEL_MSB 2
-#define SYSCTRL_VREF_CONTROL_MSB 48
-#define SYSCTRL_VREF_STATUS_MSB 7
-#define SYSCTRL_VREG_LEVEL_MSB 2
-#define SYSCTRL_BOD12_VERSION 0x111
-#define SYSCTRL_BOD33_VERSION 0x111
-#define SYSCTRL_DFLL48M_VERSION 0x301
-#define SYSCTRL_FDPLL_VERSION 0x111
-#define SYSCTRL_OSCULP32K_VERSION 0x111
-#define SYSCTRL_OSC8M_VERSION 0x120
-#define SYSCTRL_OSC32K_VERSION 0x1101
-#define SYSCTRL_VREF_VERSION 0x200
-#define SYSCTRL_VREG_VERSION 0x201
-#define SYSCTRL_XOSC_VERSION 0x1111
-#define SYSCTRL_XOSC32K_VERSION 0x1111
+#define SYSCTRL_OSC32K_COARSE_CALIB_MSB 6
+#define SYSCTRL_POR33_ENTEST_MSB 1
+#define SYSCTRL_ULPVREF_DIVLEV_MSB 3
+#define SYSCTRL_ULPVREG_FORCEGAIN_MSB 1
+#define SYSCTRL_ULPVREG_RAMREFSEL_MSB 2
+#define SYSCTRL_VREF_CONTROL_MSB 48
+#define SYSCTRL_VREF_STATUS_MSB 7
+#define SYSCTRL_VREG_LEVEL_MSB 2
+#define SYSCTRL_BOD12_VERSION 0x111
+#define SYSCTRL_BOD33_VERSION 0x111
+#define SYSCTRL_DFLL48M_VERSION 0x301
+#define SYSCTRL_FDPLL_VERSION 0x111
+#define SYSCTRL_OSCULP32K_VERSION 0x111
+#define SYSCTRL_OSC8M_VERSION 0x120
+#define SYSCTRL_OSC32K_VERSION 0x1101
+#define SYSCTRL_VREF_VERSION 0x200
+#define SYSCTRL_VREG_VERSION 0x201
+#define SYSCTRL_XOSC_VERSION 0x1111
+#define SYSCTRL_XOSC32K_VERSION 0x1111
#endif /* _SAMR21_SYSCTRL_INSTANCE_ */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_tc3.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_tc3.h
index c3a57f3b4f5..987f85240bd 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_tc3.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_tc3.h
@@ -103,7 +103,7 @@
#define TC3_DMAC_ID_MC_SIZE 2
#define TC3_DMAC_ID_OVF 24 // Indexes of DMA Overflow trigger
#define TC3_GCLK_ID 27 // Index of Generic Clock
-#define TC3_MASTER 0
+#define TC3_MASTER 0
#define TC3_OW_NUM 2 // Number of Output Waveforms
#define TC3_PERIOD_EXT 0 // Period feature implemented
#define TC3_SHADOW_EXT 0 // Shadow feature implemented
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_tc4.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_tc4.h
index 382c71c45cd..598dc7b9008 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_tc4.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_tc4.h
@@ -103,7 +103,7 @@
#define TC4_DMAC_ID_MC_SIZE 2
#define TC4_DMAC_ID_OVF 27 // Indexes of DMA Overflow trigger
#define TC4_GCLK_ID 28 // Index of Generic Clock
-#define TC4_MASTER 1
+#define TC4_MASTER 1
#define TC4_OW_NUM 2 // Number of Output Waveforms
#define TC4_PERIOD_EXT 0 // Period feature implemented
#define TC4_SHADOW_EXT 0 // Shadow feature implemented
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_tc5.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_tc5.h
index f7f98af2cdd..3d0518800bd 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_tc5.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_tc5.h
@@ -103,7 +103,7 @@
#define TC5_DMAC_ID_MC_SIZE 2
#define TC5_DMAC_ID_OVF 30 // Indexes of DMA Overflow trigger
#define TC5_GCLK_ID 28 // Index of Generic Clock
-#define TC5_MASTER 0
+#define TC5_MASTER 0
#define TC5_OW_NUM 2 // Number of Output Waveforms
#define TC5_PERIOD_EXT 0 // Period feature implemented
#define TC5_SHADOW_EXT 0 // Shadow feature implemented
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_tcc0.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_tcc0.h
index 8d7371ae4c4..5912bfbc8d2 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_tcc0.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_tcc0.h
@@ -124,7 +124,7 @@
#define TCC0_OTMX 1 // Output Matrix feature implemented
#define TCC0_OW_NUM 8 // Number of Output Waveforms
#define TCC0_PG 1 // Pattern Generation feature implemented
-#define TCC0_SIZE 24
+#define TCC0_SIZE 24
#define TCC0_SWAP 1 // DTI outputs swap feature implemented
#define TCC0_TYPE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_tcc1.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_tcc1.h
index 441fdbbc74b..da2ff09f445 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_tcc1.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_tcc1.h
@@ -112,7 +112,7 @@
#define TCC1_OTMX 0 // Output Matrix feature implemented
#define TCC1_OW_NUM 4 // Number of Output Waveforms
#define TCC1_PG 1 // Pattern Generation feature implemented
-#define TCC1_SIZE 24
+#define TCC1_SIZE 24
#define TCC1_SWAP 0 // DTI outputs swap feature implemented
#define TCC1_TYPE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_tcc2.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_tcc2.h
index 559a82bf9b4..6090fc62969 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_tcc2.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_tcc2.h
@@ -108,7 +108,7 @@
#define TCC2_OTMX 0 // Output Matrix feature implemented
#define TCC2_OW_NUM 2 // Number of Output Waveforms
#define TCC2_PG 0 // Pattern Generation feature implemented
-#define TCC2_SIZE 16
+#define TCC2_SIZE 16
#define TCC2_SWAP 0 // DTI outputs swap feature implemented
#define TCC2_TYPE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/samr21.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/samr21.h
index 90a489d30df..769e7004d06 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/samr21.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/samr21.h
@@ -50,19 +50,19 @@
*/
#if defined(__SAMR21E16A__) || defined(__ATSAMR21E16A__)
- #include "samr21e16a.h"
+#include "samr21e16a.h"
#elif defined(__SAMR21E17A__) || defined(__ATSAMR21E17A__)
- #include "samr21e17a.h"
+#include "samr21e17a.h"
#elif defined(__SAMR21E18A__) || defined(__ATSAMR21E18A__)
- #include "samr21e18a.h"
+#include "samr21e18a.h"
#elif defined(__SAMR21G16A__) || defined(__ATSAMR21G16A__)
- #include "samr21g16a.h"
+#include "samr21g16a.h"
#elif defined(__SAMR21G17A__) || defined(__ATSAMR21G17A__)
- #include "samr21g17a.h"
+#include "samr21g17a.h"
#elif defined(__SAMR21G18A__) || defined(__ATSAMR21G18A__)
- #include "samr21g18a.h"
+#include "samr21g18a.h"
#else
- #error Library does not support the specified device.
+#error Library does not support the specified device.
#endif
#endif /* _SAMR21_ */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/samr21e16a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/samr21e16a.h
index 6bb342d5002..2208878819a 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/samr21e16a.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/samr21e16a.h
@@ -56,7 +56,7 @@
/*@{*/
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -90,99 +90,97 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
-typedef enum IRQn
-{
- /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
- /****** SAMR21E16A-specific Interrupt Numbers ***********************/
- PM_IRQn = 0, /**< 0 SAMR21E16A Power Manager (PM) */
- SYSCTRL_IRQn = 1, /**< 1 SAMR21E16A System Control (SYSCTRL) */
- WDT_IRQn = 2, /**< 2 SAMR21E16A Watchdog Timer (WDT) */
- RTC_IRQn = 3, /**< 3 SAMR21E16A Real-Time Counter (RTC) */
- EIC_IRQn = 4, /**< 4 SAMR21E16A External Interrupt Controller (EIC) */
- NVMCTRL_IRQn = 5, /**< 5 SAMR21E16A Non-Volatile Memory Controller (NVMCTRL) */
- DMAC_IRQn = 6, /**< 6 SAMR21E16A Direct Memory Access Controller (DMAC) */
- USB_IRQn = 7, /**< 7 SAMR21E16A Universal Serial Bus (USB) */
- EVSYS_IRQn = 8, /**< 8 SAMR21E16A Event System Interface (EVSYS) */
- SERCOM0_IRQn = 9, /**< 9 SAMR21E16A Serial Communication Interface 0 (SERCOM0) */
- SERCOM1_IRQn = 10, /**< 10 SAMR21E16A Serial Communication Interface 1 (SERCOM1) */
- SERCOM2_IRQn = 11, /**< 11 SAMR21E16A Serial Communication Interface 2 (SERCOM2) */
- SERCOM3_IRQn = 12, /**< 12 SAMR21E16A Serial Communication Interface 3 (SERCOM3) */
- SERCOM4_IRQn = 13, /**< 13 SAMR21E16A Serial Communication Interface 4 (SERCOM4) */
- SERCOM5_IRQn = 14, /**< 14 SAMR21E16A Serial Communication Interface 5 (SERCOM5) */
- TCC0_IRQn = 15, /**< 15 SAMR21E16A Timer Counter Control 0 (TCC0) */
- TCC1_IRQn = 16, /**< 16 SAMR21E16A Timer Counter Control 1 (TCC1) */
- TCC2_IRQn = 17, /**< 17 SAMR21E16A Timer Counter Control 2 (TCC2) */
- TC3_IRQn = 18, /**< 18 SAMR21E16A Basic Timer Counter 3 (TC3) */
- TC4_IRQn = 19, /**< 19 SAMR21E16A Basic Timer Counter 4 (TC4) */
- TC5_IRQn = 20, /**< 20 SAMR21E16A Basic Timer Counter 5 (TC5) */
- TC6_IRQn = 21, /**< 21 SAMR21E16A Basic Timer Counter 6 (TC6) */
- TC7_IRQn = 22, /**< 22 SAMR21E16A Basic Timer Counter 7 (TC7) */
- ADC_IRQn = 23, /**< 23 SAMR21E16A Analog Digital Converter (ADC) */
- AC_IRQn = 24, /**< 24 SAMR21E16A Analog Comparators (AC) */
- DAC_IRQn = 25, /**< 25 SAMR21E16A Digital Analog Converter (DAC) */
- PTC_IRQn = 26, /**< 26 SAMR21E16A Peripheral Touch Controller (PTC) */
- I2S_IRQn = 27, /**< 27 SAMR21E16A Inter-IC Sound Interface (I2S) */
-
- PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+typedef enum IRQn {
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMR21E16A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMR21E16A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMR21E16A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMR21E16A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMR21E16A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMR21E16A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMR21E16A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMR21E16A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMR21E16A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMR21E16A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMR21E16A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMR21E16A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMR21E16A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMR21E16A Serial Communication Interface 3 (SERCOM3) */
+ SERCOM4_IRQn = 13, /**< 13 SAMR21E16A Serial Communication Interface 4 (SERCOM4) */
+ SERCOM5_IRQn = 14, /**< 14 SAMR21E16A Serial Communication Interface 5 (SERCOM5) */
+ TCC0_IRQn = 15, /**< 15 SAMR21E16A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMR21E16A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMR21E16A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMR21E16A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMR21E16A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMR21E16A Basic Timer Counter 5 (TC5) */
+ TC6_IRQn = 21, /**< 21 SAMR21E16A Basic Timer Counter 6 (TC6) */
+ TC7_IRQn = 22, /**< 22 SAMR21E16A Basic Timer Counter 7 (TC7) */
+ ADC_IRQn = 23, /**< 23 SAMR21E16A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMR21E16A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMR21E16A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMR21E16A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMR21E16A Inter-IC Sound Interface (I2S) */
+
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
-
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnReservedM12;
- void* pfnReservedM11;
- void* pfnReservedM10;
- void* pfnReservedM9;
- void* pfnReservedM8;
- void* pfnReservedM7;
- void* pfnReservedM6;
- void* pfnSVC_Handler;
- void* pfnReservedM4;
- void* pfnReservedM3;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
-
- /* Peripheral handlers */
- void* pfnPM_Handler; /* 0 Power Manager */
- void* pfnSYSCTRL_Handler; /* 1 System Control */
- void* pfnWDT_Handler; /* 2 Watchdog Timer */
- void* pfnRTC_Handler; /* 3 Real-Time Counter */
- void* pfnEIC_Handler; /* 4 External Interrupt Controller */
- void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
- void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
- void* pfnUSB_Handler; /* 7 Universal Serial Bus */
- void* pfnEVSYS_Handler; /* 8 Event System Interface */
- void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
- void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
- void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
- void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
- void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
- void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
- void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
- void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
- void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
- void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
- void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
- void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
- void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
- void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
- void* pfnADC_Handler; /* 23 Analog Digital Converter */
- void* pfnAC_Handler; /* 24 Analog Comparators */
- void* pfnDAC_Handler; /* 25 Digital Analog Converter */
- void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
- void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
- void* pfnReserved28;
+typedef struct _DeviceVectors {
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
+ void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
+ void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+ void* pfnReserved28;
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@@ -227,7 +225,7 @@ void I2S_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/samr21e17a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/samr21e17a.h
index 7931cbe4d20..e4c3c23319e 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/samr21e17a.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/samr21e17a.h
@@ -56,7 +56,7 @@
/*@{*/
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -90,99 +90,97 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
-typedef enum IRQn
-{
- /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
- /****** SAMR21E17A-specific Interrupt Numbers ***********************/
- PM_IRQn = 0, /**< 0 SAMR21E17A Power Manager (PM) */
- SYSCTRL_IRQn = 1, /**< 1 SAMR21E17A System Control (SYSCTRL) */
- WDT_IRQn = 2, /**< 2 SAMR21E17A Watchdog Timer (WDT) */
- RTC_IRQn = 3, /**< 3 SAMR21E17A Real-Time Counter (RTC) */
- EIC_IRQn = 4, /**< 4 SAMR21E17A External Interrupt Controller (EIC) */
- NVMCTRL_IRQn = 5, /**< 5 SAMR21E17A Non-Volatile Memory Controller (NVMCTRL) */
- DMAC_IRQn = 6, /**< 6 SAMR21E17A Direct Memory Access Controller (DMAC) */
- USB_IRQn = 7, /**< 7 SAMR21E17A Universal Serial Bus (USB) */
- EVSYS_IRQn = 8, /**< 8 SAMR21E17A Event System Interface (EVSYS) */
- SERCOM0_IRQn = 9, /**< 9 SAMR21E17A Serial Communication Interface 0 (SERCOM0) */
- SERCOM1_IRQn = 10, /**< 10 SAMR21E17A Serial Communication Interface 1 (SERCOM1) */
- SERCOM2_IRQn = 11, /**< 11 SAMR21E17A Serial Communication Interface 2 (SERCOM2) */
- SERCOM3_IRQn = 12, /**< 12 SAMR21E17A Serial Communication Interface 3 (SERCOM3) */
- SERCOM4_IRQn = 13, /**< 13 SAMR21E17A Serial Communication Interface 4 (SERCOM4) */
- SERCOM5_IRQn = 14, /**< 14 SAMR21E17A Serial Communication Interface 5 (SERCOM5) */
- TCC0_IRQn = 15, /**< 15 SAMR21E17A Timer Counter Control 0 (TCC0) */
- TCC1_IRQn = 16, /**< 16 SAMR21E17A Timer Counter Control 1 (TCC1) */
- TCC2_IRQn = 17, /**< 17 SAMR21E17A Timer Counter Control 2 (TCC2) */
- TC3_IRQn = 18, /**< 18 SAMR21E17A Basic Timer Counter 3 (TC3) */
- TC4_IRQn = 19, /**< 19 SAMR21E17A Basic Timer Counter 4 (TC4) */
- TC5_IRQn = 20, /**< 20 SAMR21E17A Basic Timer Counter 5 (TC5) */
- TC6_IRQn = 21, /**< 21 SAMR21E17A Basic Timer Counter 6 (TC6) */
- TC7_IRQn = 22, /**< 22 SAMR21E17A Basic Timer Counter 7 (TC7) */
- ADC_IRQn = 23, /**< 23 SAMR21E17A Analog Digital Converter (ADC) */
- AC_IRQn = 24, /**< 24 SAMR21E17A Analog Comparators (AC) */
- DAC_IRQn = 25, /**< 25 SAMR21E17A Digital Analog Converter (DAC) */
- PTC_IRQn = 26, /**< 26 SAMR21E17A Peripheral Touch Controller (PTC) */
- I2S_IRQn = 27, /**< 27 SAMR21E17A Inter-IC Sound Interface (I2S) */
-
- PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+typedef enum IRQn {
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMR21E17A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMR21E17A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMR21E17A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMR21E17A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMR21E17A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMR21E17A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMR21E17A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMR21E17A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMR21E17A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMR21E17A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMR21E17A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMR21E17A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMR21E17A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMR21E17A Serial Communication Interface 3 (SERCOM3) */
+ SERCOM4_IRQn = 13, /**< 13 SAMR21E17A Serial Communication Interface 4 (SERCOM4) */
+ SERCOM5_IRQn = 14, /**< 14 SAMR21E17A Serial Communication Interface 5 (SERCOM5) */
+ TCC0_IRQn = 15, /**< 15 SAMR21E17A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMR21E17A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMR21E17A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMR21E17A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMR21E17A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMR21E17A Basic Timer Counter 5 (TC5) */
+ TC6_IRQn = 21, /**< 21 SAMR21E17A Basic Timer Counter 6 (TC6) */
+ TC7_IRQn = 22, /**< 22 SAMR21E17A Basic Timer Counter 7 (TC7) */
+ ADC_IRQn = 23, /**< 23 SAMR21E17A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMR21E17A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMR21E17A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMR21E17A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMR21E17A Inter-IC Sound Interface (I2S) */
+
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
-
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnReservedM12;
- void* pfnReservedM11;
- void* pfnReservedM10;
- void* pfnReservedM9;
- void* pfnReservedM8;
- void* pfnReservedM7;
- void* pfnReservedM6;
- void* pfnSVC_Handler;
- void* pfnReservedM4;
- void* pfnReservedM3;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
-
- /* Peripheral handlers */
- void* pfnPM_Handler; /* 0 Power Manager */
- void* pfnSYSCTRL_Handler; /* 1 System Control */
- void* pfnWDT_Handler; /* 2 Watchdog Timer */
- void* pfnRTC_Handler; /* 3 Real-Time Counter */
- void* pfnEIC_Handler; /* 4 External Interrupt Controller */
- void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
- void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
- void* pfnUSB_Handler; /* 7 Universal Serial Bus */
- void* pfnEVSYS_Handler; /* 8 Event System Interface */
- void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
- void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
- void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
- void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
- void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
- void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
- void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
- void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
- void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
- void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
- void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
- void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
- void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
- void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
- void* pfnADC_Handler; /* 23 Analog Digital Converter */
- void* pfnAC_Handler; /* 24 Analog Comparators */
- void* pfnDAC_Handler; /* 25 Digital Analog Converter */
- void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
- void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
- void* pfnReserved28;
+typedef struct _DeviceVectors {
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
+ void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
+ void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+ void* pfnReserved28;
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@@ -227,7 +225,7 @@ void I2S_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/samr21e18a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/samr21e18a.h
index 8c9dcbb27bc..2e4e3dd90a1 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/samr21e18a.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/samr21e18a.h
@@ -56,7 +56,7 @@
/*@{*/
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -90,99 +90,97 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
-typedef enum IRQn
-{
- /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
- /****** SAMR21E18A-specific Interrupt Numbers ***********************/
- PM_IRQn = 0, /**< 0 SAMR21E18A Power Manager (PM) */
- SYSCTRL_IRQn = 1, /**< 1 SAMR21E18A System Control (SYSCTRL) */
- WDT_IRQn = 2, /**< 2 SAMR21E18A Watchdog Timer (WDT) */
- RTC_IRQn = 3, /**< 3 SAMR21E18A Real-Time Counter (RTC) */
- EIC_IRQn = 4, /**< 4 SAMR21E18A External Interrupt Controller (EIC) */
- NVMCTRL_IRQn = 5, /**< 5 SAMR21E18A Non-Volatile Memory Controller (NVMCTRL) */
- DMAC_IRQn = 6, /**< 6 SAMR21E18A Direct Memory Access Controller (DMAC) */
- USB_IRQn = 7, /**< 7 SAMR21E18A Universal Serial Bus (USB) */
- EVSYS_IRQn = 8, /**< 8 SAMR21E18A Event System Interface (EVSYS) */
- SERCOM0_IRQn = 9, /**< 9 SAMR21E18A Serial Communication Interface 0 (SERCOM0) */
- SERCOM1_IRQn = 10, /**< 10 SAMR21E18A Serial Communication Interface 1 (SERCOM1) */
- SERCOM2_IRQn = 11, /**< 11 SAMR21E18A Serial Communication Interface 2 (SERCOM2) */
- SERCOM3_IRQn = 12, /**< 12 SAMR21E18A Serial Communication Interface 3 (SERCOM3) */
- SERCOM4_IRQn = 13, /**< 13 SAMR21E18A Serial Communication Interface 4 (SERCOM4) */
- SERCOM5_IRQn = 14, /**< 14 SAMR21E18A Serial Communication Interface 5 (SERCOM5) */
- TCC0_IRQn = 15, /**< 15 SAMR21E18A Timer Counter Control 0 (TCC0) */
- TCC1_IRQn = 16, /**< 16 SAMR21E18A Timer Counter Control 1 (TCC1) */
- TCC2_IRQn = 17, /**< 17 SAMR21E18A Timer Counter Control 2 (TCC2) */
- TC3_IRQn = 18, /**< 18 SAMR21E18A Basic Timer Counter 3 (TC3) */
- TC4_IRQn = 19, /**< 19 SAMR21E18A Basic Timer Counter 4 (TC4) */
- TC5_IRQn = 20, /**< 20 SAMR21E18A Basic Timer Counter 5 (TC5) */
- TC6_IRQn = 21, /**< 21 SAMR21E18A Basic Timer Counter 6 (TC6) */
- TC7_IRQn = 22, /**< 22 SAMR21E18A Basic Timer Counter 7 (TC7) */
- ADC_IRQn = 23, /**< 23 SAMR21E18A Analog Digital Converter (ADC) */
- AC_IRQn = 24, /**< 24 SAMR21E18A Analog Comparators (AC) */
- DAC_IRQn = 25, /**< 25 SAMR21E18A Digital Analog Converter (DAC) */
- PTC_IRQn = 26, /**< 26 SAMR21E18A Peripheral Touch Controller (PTC) */
- I2S_IRQn = 27, /**< 27 SAMR21E18A Inter-IC Sound Interface (I2S) */
-
- PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+typedef enum IRQn {
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMR21E18A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMR21E18A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMR21E18A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMR21E18A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMR21E18A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMR21E18A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMR21E18A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMR21E18A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMR21E18A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMR21E18A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMR21E18A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMR21E18A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMR21E18A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMR21E18A Serial Communication Interface 3 (SERCOM3) */
+ SERCOM4_IRQn = 13, /**< 13 SAMR21E18A Serial Communication Interface 4 (SERCOM4) */
+ SERCOM5_IRQn = 14, /**< 14 SAMR21E18A Serial Communication Interface 5 (SERCOM5) */
+ TCC0_IRQn = 15, /**< 15 SAMR21E18A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMR21E18A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMR21E18A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMR21E18A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMR21E18A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMR21E18A Basic Timer Counter 5 (TC5) */
+ TC6_IRQn = 21, /**< 21 SAMR21E18A Basic Timer Counter 6 (TC6) */
+ TC7_IRQn = 22, /**< 22 SAMR21E18A Basic Timer Counter 7 (TC7) */
+ ADC_IRQn = 23, /**< 23 SAMR21E18A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMR21E18A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMR21E18A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMR21E18A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMR21E18A Inter-IC Sound Interface (I2S) */
+
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
-
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnReservedM12;
- void* pfnReservedM11;
- void* pfnReservedM10;
- void* pfnReservedM9;
- void* pfnReservedM8;
- void* pfnReservedM7;
- void* pfnReservedM6;
- void* pfnSVC_Handler;
- void* pfnReservedM4;
- void* pfnReservedM3;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
-
- /* Peripheral handlers */
- void* pfnPM_Handler; /* 0 Power Manager */
- void* pfnSYSCTRL_Handler; /* 1 System Control */
- void* pfnWDT_Handler; /* 2 Watchdog Timer */
- void* pfnRTC_Handler; /* 3 Real-Time Counter */
- void* pfnEIC_Handler; /* 4 External Interrupt Controller */
- void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
- void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
- void* pfnUSB_Handler; /* 7 Universal Serial Bus */
- void* pfnEVSYS_Handler; /* 8 Event System Interface */
- void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
- void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
- void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
- void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
- void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
- void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
- void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
- void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
- void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
- void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
- void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
- void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
- void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
- void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
- void* pfnADC_Handler; /* 23 Analog Digital Converter */
- void* pfnAC_Handler; /* 24 Analog Comparators */
- void* pfnDAC_Handler; /* 25 Digital Analog Converter */
- void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
- void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
- void* pfnReserved28;
+typedef struct _DeviceVectors {
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
+ void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
+ void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+ void* pfnReserved28;
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@@ -227,7 +225,7 @@ void I2S_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/samr21g16a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/samr21g16a.h
index 6ceab69a848..42d7c79af54 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/samr21g16a.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/samr21g16a.h
@@ -56,7 +56,7 @@
/*@{*/
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -90,99 +90,97 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
-typedef enum IRQn
-{
- /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
- /****** SAMR21G16A-specific Interrupt Numbers ***********************/
- PM_IRQn = 0, /**< 0 SAMR21G16A Power Manager (PM) */
- SYSCTRL_IRQn = 1, /**< 1 SAMR21G16A System Control (SYSCTRL) */
- WDT_IRQn = 2, /**< 2 SAMR21G16A Watchdog Timer (WDT) */
- RTC_IRQn = 3, /**< 3 SAMR21G16A Real-Time Counter (RTC) */
- EIC_IRQn = 4, /**< 4 SAMR21G16A External Interrupt Controller (EIC) */
- NVMCTRL_IRQn = 5, /**< 5 SAMR21G16A Non-Volatile Memory Controller (NVMCTRL) */
- DMAC_IRQn = 6, /**< 6 SAMR21G16A Direct Memory Access Controller (DMAC) */
- USB_IRQn = 7, /**< 7 SAMR21G16A Universal Serial Bus (USB) */
- EVSYS_IRQn = 8, /**< 8 SAMR21G16A Event System Interface (EVSYS) */
- SERCOM0_IRQn = 9, /**< 9 SAMR21G16A Serial Communication Interface 0 (SERCOM0) */
- SERCOM1_IRQn = 10, /**< 10 SAMR21G16A Serial Communication Interface 1 (SERCOM1) */
- SERCOM2_IRQn = 11, /**< 11 SAMR21G16A Serial Communication Interface 2 (SERCOM2) */
- SERCOM3_IRQn = 12, /**< 12 SAMR21G16A Serial Communication Interface 3 (SERCOM3) */
- SERCOM4_IRQn = 13, /**< 13 SAMR21G16A Serial Communication Interface 4 (SERCOM4) */
- SERCOM5_IRQn = 14, /**< 14 SAMR21G16A Serial Communication Interface 5 (SERCOM5) */
- TCC0_IRQn = 15, /**< 15 SAMR21G16A Timer Counter Control 0 (TCC0) */
- TCC1_IRQn = 16, /**< 16 SAMR21G16A Timer Counter Control 1 (TCC1) */
- TCC2_IRQn = 17, /**< 17 SAMR21G16A Timer Counter Control 2 (TCC2) */
- TC3_IRQn = 18, /**< 18 SAMR21G16A Basic Timer Counter 3 (TC3) */
- TC4_IRQn = 19, /**< 19 SAMR21G16A Basic Timer Counter 4 (TC4) */
- TC5_IRQn = 20, /**< 20 SAMR21G16A Basic Timer Counter 5 (TC5) */
- TC6_IRQn = 21, /**< 21 SAMR21G16A Basic Timer Counter 6 (TC6) */
- TC7_IRQn = 22, /**< 22 SAMR21G16A Basic Timer Counter 7 (TC7) */
- ADC_IRQn = 23, /**< 23 SAMR21G16A Analog Digital Converter (ADC) */
- AC_IRQn = 24, /**< 24 SAMR21G16A Analog Comparators (AC) */
- DAC_IRQn = 25, /**< 25 SAMR21G16A Digital Analog Converter (DAC) */
- PTC_IRQn = 26, /**< 26 SAMR21G16A Peripheral Touch Controller (PTC) */
- I2S_IRQn = 27, /**< 27 SAMR21G16A Inter-IC Sound Interface (I2S) */
-
- PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+typedef enum IRQn {
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMR21G16A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMR21G16A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMR21G16A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMR21G16A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMR21G16A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMR21G16A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMR21G16A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMR21G16A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMR21G16A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMR21G16A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMR21G16A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMR21G16A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMR21G16A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMR21G16A Serial Communication Interface 3 (SERCOM3) */
+ SERCOM4_IRQn = 13, /**< 13 SAMR21G16A Serial Communication Interface 4 (SERCOM4) */
+ SERCOM5_IRQn = 14, /**< 14 SAMR21G16A Serial Communication Interface 5 (SERCOM5) */
+ TCC0_IRQn = 15, /**< 15 SAMR21G16A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMR21G16A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMR21G16A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMR21G16A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMR21G16A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMR21G16A Basic Timer Counter 5 (TC5) */
+ TC6_IRQn = 21, /**< 21 SAMR21G16A Basic Timer Counter 6 (TC6) */
+ TC7_IRQn = 22, /**< 22 SAMR21G16A Basic Timer Counter 7 (TC7) */
+ ADC_IRQn = 23, /**< 23 SAMR21G16A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMR21G16A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMR21G16A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMR21G16A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMR21G16A Inter-IC Sound Interface (I2S) */
+
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
-
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnReservedM12;
- void* pfnReservedM11;
- void* pfnReservedM10;
- void* pfnReservedM9;
- void* pfnReservedM8;
- void* pfnReservedM7;
- void* pfnReservedM6;
- void* pfnSVC_Handler;
- void* pfnReservedM4;
- void* pfnReservedM3;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
-
- /* Peripheral handlers */
- void* pfnPM_Handler; /* 0 Power Manager */
- void* pfnSYSCTRL_Handler; /* 1 System Control */
- void* pfnWDT_Handler; /* 2 Watchdog Timer */
- void* pfnRTC_Handler; /* 3 Real-Time Counter */
- void* pfnEIC_Handler; /* 4 External Interrupt Controller */
- void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
- void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
- void* pfnUSB_Handler; /* 7 Universal Serial Bus */
- void* pfnEVSYS_Handler; /* 8 Event System Interface */
- void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
- void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
- void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
- void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
- void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
- void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
- void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
- void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
- void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
- void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
- void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
- void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
- void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
- void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
- void* pfnADC_Handler; /* 23 Analog Digital Converter */
- void* pfnAC_Handler; /* 24 Analog Comparators */
- void* pfnDAC_Handler; /* 25 Digital Analog Converter */
- void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
- void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
- void* pfnReserved28;
+typedef struct _DeviceVectors {
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
+ void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
+ void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+ void* pfnReserved28;
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@@ -227,7 +225,7 @@ void I2S_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/samr21g17a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/samr21g17a.h
index 6f2e69f2247..44ba21d89b2 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/samr21g17a.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/samr21g17a.h
@@ -56,7 +56,7 @@
/*@{*/
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -90,99 +90,97 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
-typedef enum IRQn
-{
- /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
- /****** SAMR21G17A-specific Interrupt Numbers ***********************/
- PM_IRQn = 0, /**< 0 SAMR21G17A Power Manager (PM) */
- SYSCTRL_IRQn = 1, /**< 1 SAMR21G17A System Control (SYSCTRL) */
- WDT_IRQn = 2, /**< 2 SAMR21G17A Watchdog Timer (WDT) */
- RTC_IRQn = 3, /**< 3 SAMR21G17A Real-Time Counter (RTC) */
- EIC_IRQn = 4, /**< 4 SAMR21G17A External Interrupt Controller (EIC) */
- NVMCTRL_IRQn = 5, /**< 5 SAMR21G17A Non-Volatile Memory Controller (NVMCTRL) */
- DMAC_IRQn = 6, /**< 6 SAMR21G17A Direct Memory Access Controller (DMAC) */
- USB_IRQn = 7, /**< 7 SAMR21G17A Universal Serial Bus (USB) */
- EVSYS_IRQn = 8, /**< 8 SAMR21G17A Event System Interface (EVSYS) */
- SERCOM0_IRQn = 9, /**< 9 SAMR21G17A Serial Communication Interface 0 (SERCOM0) */
- SERCOM1_IRQn = 10, /**< 10 SAMR21G17A Serial Communication Interface 1 (SERCOM1) */
- SERCOM2_IRQn = 11, /**< 11 SAMR21G17A Serial Communication Interface 2 (SERCOM2) */
- SERCOM3_IRQn = 12, /**< 12 SAMR21G17A Serial Communication Interface 3 (SERCOM3) */
- SERCOM4_IRQn = 13, /**< 13 SAMR21G17A Serial Communication Interface 4 (SERCOM4) */
- SERCOM5_IRQn = 14, /**< 14 SAMR21G17A Serial Communication Interface 5 (SERCOM5) */
- TCC0_IRQn = 15, /**< 15 SAMR21G17A Timer Counter Control 0 (TCC0) */
- TCC1_IRQn = 16, /**< 16 SAMR21G17A Timer Counter Control 1 (TCC1) */
- TCC2_IRQn = 17, /**< 17 SAMR21G17A Timer Counter Control 2 (TCC2) */
- TC3_IRQn = 18, /**< 18 SAMR21G17A Basic Timer Counter 3 (TC3) */
- TC4_IRQn = 19, /**< 19 SAMR21G17A Basic Timer Counter 4 (TC4) */
- TC5_IRQn = 20, /**< 20 SAMR21G17A Basic Timer Counter 5 (TC5) */
- TC6_IRQn = 21, /**< 21 SAMR21G17A Basic Timer Counter 6 (TC6) */
- TC7_IRQn = 22, /**< 22 SAMR21G17A Basic Timer Counter 7 (TC7) */
- ADC_IRQn = 23, /**< 23 SAMR21G17A Analog Digital Converter (ADC) */
- AC_IRQn = 24, /**< 24 SAMR21G17A Analog Comparators (AC) */
- DAC_IRQn = 25, /**< 25 SAMR21G17A Digital Analog Converter (DAC) */
- PTC_IRQn = 26, /**< 26 SAMR21G17A Peripheral Touch Controller (PTC) */
- I2S_IRQn = 27, /**< 27 SAMR21G17A Inter-IC Sound Interface (I2S) */
-
- PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+typedef enum IRQn {
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMR21G17A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMR21G17A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMR21G17A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMR21G17A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMR21G17A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMR21G17A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMR21G17A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMR21G17A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMR21G17A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMR21G17A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMR21G17A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMR21G17A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMR21G17A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMR21G17A Serial Communication Interface 3 (SERCOM3) */
+ SERCOM4_IRQn = 13, /**< 13 SAMR21G17A Serial Communication Interface 4 (SERCOM4) */
+ SERCOM5_IRQn = 14, /**< 14 SAMR21G17A Serial Communication Interface 5 (SERCOM5) */
+ TCC0_IRQn = 15, /**< 15 SAMR21G17A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMR21G17A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMR21G17A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMR21G17A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMR21G17A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMR21G17A Basic Timer Counter 5 (TC5) */
+ TC6_IRQn = 21, /**< 21 SAMR21G17A Basic Timer Counter 6 (TC6) */
+ TC7_IRQn = 22, /**< 22 SAMR21G17A Basic Timer Counter 7 (TC7) */
+ ADC_IRQn = 23, /**< 23 SAMR21G17A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMR21G17A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMR21G17A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMR21G17A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMR21G17A Inter-IC Sound Interface (I2S) */
+
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
-
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnReservedM12;
- void* pfnReservedM11;
- void* pfnReservedM10;
- void* pfnReservedM9;
- void* pfnReservedM8;
- void* pfnReservedM7;
- void* pfnReservedM6;
- void* pfnSVC_Handler;
- void* pfnReservedM4;
- void* pfnReservedM3;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
-
- /* Peripheral handlers */
- void* pfnPM_Handler; /* 0 Power Manager */
- void* pfnSYSCTRL_Handler; /* 1 System Control */
- void* pfnWDT_Handler; /* 2 Watchdog Timer */
- void* pfnRTC_Handler; /* 3 Real-Time Counter */
- void* pfnEIC_Handler; /* 4 External Interrupt Controller */
- void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
- void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
- void* pfnUSB_Handler; /* 7 Universal Serial Bus */
- void* pfnEVSYS_Handler; /* 8 Event System Interface */
- void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
- void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
- void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
- void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
- void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
- void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
- void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
- void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
- void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
- void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
- void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
- void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
- void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
- void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
- void* pfnADC_Handler; /* 23 Analog Digital Converter */
- void* pfnAC_Handler; /* 24 Analog Comparators */
- void* pfnDAC_Handler; /* 25 Digital Analog Converter */
- void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
- void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
- void* pfnReserved28;
+typedef struct _DeviceVectors {
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
+ void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
+ void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+ void* pfnReserved28;
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@@ -227,7 +225,7 @@ void I2S_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/samr21g18a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/samr21g18a.h
index 99009a892ce..49123bb9597 100644
--- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/samr21g18a.h
+++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/samr21g18a.h
@@ -56,7 +56,7 @@
/*@{*/
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@@ -90,99 +90,97 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
-typedef enum IRQn
-{
- /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
- /****** SAMR21G18A-specific Interrupt Numbers ***********************/
- PM_IRQn = 0, /**< 0 SAMR21G18A Power Manager (PM) */
- SYSCTRL_IRQn = 1, /**< 1 SAMR21G18A System Control (SYSCTRL) */
- WDT_IRQn = 2, /**< 2 SAMR21G18A Watchdog Timer (WDT) */
- RTC_IRQn = 3, /**< 3 SAMR21G18A Real-Time Counter (RTC) */
- EIC_IRQn = 4, /**< 4 SAMR21G18A External Interrupt Controller (EIC) */
- NVMCTRL_IRQn = 5, /**< 5 SAMR21G18A Non-Volatile Memory Controller (NVMCTRL) */
- DMAC_IRQn = 6, /**< 6 SAMR21G18A Direct Memory Access Controller (DMAC) */
- USB_IRQn = 7, /**< 7 SAMR21G18A Universal Serial Bus (USB) */
- EVSYS_IRQn = 8, /**< 8 SAMR21G18A Event System Interface (EVSYS) */
- SERCOM0_IRQn = 9, /**< 9 SAMR21G18A Serial Communication Interface 0 (SERCOM0) */
- SERCOM1_IRQn = 10, /**< 10 SAMR21G18A Serial Communication Interface 1 (SERCOM1) */
- SERCOM2_IRQn = 11, /**< 11 SAMR21G18A Serial Communication Interface 2 (SERCOM2) */
- SERCOM3_IRQn = 12, /**< 12 SAMR21G18A Serial Communication Interface 3 (SERCOM3) */
- SERCOM4_IRQn = 13, /**< 13 SAMR21G18A Serial Communication Interface 4 (SERCOM4) */
- SERCOM5_IRQn = 14, /**< 14 SAMR21G18A Serial Communication Interface 5 (SERCOM5) */
- TCC0_IRQn = 15, /**< 15 SAMR21G18A Timer Counter Control 0 (TCC0) */
- TCC1_IRQn = 16, /**< 16 SAMR21G18A Timer Counter Control 1 (TCC1) */
- TCC2_IRQn = 17, /**< 17 SAMR21G18A Timer Counter Control 2 (TCC2) */
- TC3_IRQn = 18, /**< 18 SAMR21G18A Basic Timer Counter 3 (TC3) */
- TC4_IRQn = 19, /**< 19 SAMR21G18A Basic Timer Counter 4 (TC4) */
- TC5_IRQn = 20, /**< 20 SAMR21G18A Basic Timer Counter 5 (TC5) */
- TC6_IRQn = 21, /**< 21 SAMR21G18A Basic Timer Counter 6 (TC6) */
- TC7_IRQn = 22, /**< 22 SAMR21G18A Basic Timer Counter 7 (TC7) */
- ADC_IRQn = 23, /**< 23 SAMR21G18A Analog Digital Converter (ADC) */
- AC_IRQn = 24, /**< 24 SAMR21G18A Analog Comparators (AC) */
- DAC_IRQn = 25, /**< 25 SAMR21G18A Digital Analog Converter (DAC) */
- PTC_IRQn = 26, /**< 26 SAMR21G18A Peripheral Touch Controller (PTC) */
- I2S_IRQn = 27, /**< 27 SAMR21G18A Inter-IC Sound Interface (I2S) */
-
- PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+typedef enum IRQn {
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMR21G18A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMR21G18A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMR21G18A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMR21G18A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMR21G18A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMR21G18A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMR21G18A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMR21G18A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMR21G18A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMR21G18A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMR21G18A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMR21G18A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMR21G18A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMR21G18A Serial Communication Interface 3 (SERCOM3) */
+ SERCOM4_IRQn = 13, /**< 13 SAMR21G18A Serial Communication Interface 4 (SERCOM4) */
+ SERCOM5_IRQn = 14, /**< 14 SAMR21G18A Serial Communication Interface 5 (SERCOM5) */
+ TCC0_IRQn = 15, /**< 15 SAMR21G18A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMR21G18A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMR21G18A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMR21G18A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMR21G18A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMR21G18A Basic Timer Counter 5 (TC5) */
+ TC6_IRQn = 21, /**< 21 SAMR21G18A Basic Timer Counter 6 (TC6) */
+ TC7_IRQn = 22, /**< 22 SAMR21G18A Basic Timer Counter 7 (TC7) */
+ ADC_IRQn = 23, /**< 23 SAMR21G18A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMR21G18A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMR21G18A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMR21G18A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMR21G18A Inter-IC Sound Interface (I2S) */
+
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
-
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnReservedM12;
- void* pfnReservedM11;
- void* pfnReservedM10;
- void* pfnReservedM9;
- void* pfnReservedM8;
- void* pfnReservedM7;
- void* pfnReservedM6;
- void* pfnSVC_Handler;
- void* pfnReservedM4;
- void* pfnReservedM3;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
-
- /* Peripheral handlers */
- void* pfnPM_Handler; /* 0 Power Manager */
- void* pfnSYSCTRL_Handler; /* 1 System Control */
- void* pfnWDT_Handler; /* 2 Watchdog Timer */
- void* pfnRTC_Handler; /* 3 Real-Time Counter */
- void* pfnEIC_Handler; /* 4 External Interrupt Controller */
- void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
- void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
- void* pfnUSB_Handler; /* 7 Universal Serial Bus */
- void* pfnEVSYS_Handler; /* 8 Event System Interface */
- void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
- void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
- void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
- void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
- void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
- void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
- void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
- void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
- void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
- void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
- void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
- void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
- void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
- void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
- void* pfnADC_Handler; /* 23 Analog Digital Converter */
- void* pfnAC_Handler; /* 24 Analog Comparators */
- void* pfnDAC_Handler; /* 25 Digital Analog Converter */
- void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
- void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
- void* pfnReserved28;
+typedef struct _DeviceVectors {
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
+ void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
+ void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+ void* pfnReserved28;
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@@ -227,7 +225,7 @@ void I2S_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */