diff --git a/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3328-dram-dmc.dtsi b/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3328-dram-dmc.dtsi new file mode 100644 index 00000000000000..a9e599f64baf4b --- /dev/null +++ b/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3328-dram-dmc.dtsi @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. + */ + +#include "rk3328-dram-default-timing.dtsi" + +/ { + dmc: dmc { + compatible = "rockchip,rk3328-dmc"; + devfreq-events = <&dfi>; + center-supply = <&vdd_log>; + clocks = <&cru SCLK_DDRCLK>; + clock-names = "dmc_clk"; + operating-points-v2 = <&dmc_opp_table>; + ddr_timing = <&ddr_timing>; + upthreshold = <40>; + downdifferential = <20>; + auto-min-freq = <786000>; + auto-freq-en = <0>; + #cooling-cells = <2>; + + ddr_power_model: ddr_power_model { + compatible = "ddr_power_model"; + dynamic-power-coefficient = <120>; + static-power-coefficient = <200>; + ts = <32000 4700 (-80) 2>; + thermal-zone = "soc-thermal"; + }; + }; + + dmc_opp_table: dmc-opp-table { + compatible = "operating-points-v2"; + + rockchip,leakage-voltage-sel = < + 1 10 0 + 11 254 1 + >; + nvmem-cells = <&logic_leakage>; + nvmem-cell-names = "ddr_leakage"; + + opp-786000000 { + opp-hz = /bits/ 64 <786000000>; + opp-microvolt = <1075000>; + opp-microvolt-L0 = <1075000>; + opp-microvolt-L1 = <1050000>; + }; + opp-798000000 { + opp-hz = /bits/ 64 <798000000>; + opp-microvolt = <1075000>; + opp-microvolt-L0 = <1075000>; + opp-microvolt-L1 = <1050000>; + }; + opp-840000000 { + opp-hz = /bits/ 64 <840000000>; + opp-microvolt = <1075000>; + opp-microvolt-L0 = <1075000>; + opp-microvolt-L1 = <1050000>; + }; + opp-924000000 { + opp-hz = /bits/ 64 <924000000>; + opp-microvolt = <1100000>; + opp-microvolt-L0 = <1100000>; + opp-microvolt-L1 = <1075000>; + }; + opp-1056000000 { + opp-hz = /bits/ 64 <1056000000>; + opp-microvolt = <1175000>; + opp-microvolt-L0 = <1175000>; + opp-microvolt-L1 = <1150000>; + }; + }; +}; diff --git a/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c-plus.dts b/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c-plus.dts new file mode 100644 index 00000000000000..16a1958e457277 --- /dev/null +++ b/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c-plus.dts @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyarm.com) + * + * Copyright (c) 2023 Tianling Shen + */ + +/dts-v1/; +#include "rk3328-nanopi-r2c.dts" + +/ { + model = "FriendlyElec NanoPi R2C Plus"; + compatible = "friendlyarm,nanopi-r2c-plus", "rockchip,rk3328"; + + aliases { + mmc1 = &emmc; + }; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + max-frequency = <150000000>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + vmmc-supply = <&vcc_io_33>; + vqmmc-supply = <&vcc18_emmc>; + status = "okay"; +}; diff --git a/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s-plus.dts b/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s-plus.dts new file mode 100644 index 00000000000000..4b9ced67742d26 --- /dev/null +++ b/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s-plus.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * (C) Copyright 2018 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyarm.com) + * + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + */ + +/dts-v1/; +#include "rk3328-nanopi-r2s.dts" + +/ { + compatible = "friendlyarm,nanopi-r2s-plus", "rockchip,rk3328"; + model = "FriendlyElec NanoPi R2S Plus"; + + aliases { + mmc1 = &emmc; + }; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + disable-wp; + mmc-hs200-1_8v; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + status = "okay"; +}; diff --git a/target/linux/rockchip/patches-6.6/035-01-v6.12-mmc-dw_mmc-rockchip-Add-internal-phase-support.patch b/target/linux/rockchip/patches-6.6/035-01-v6.12-mmc-dw_mmc-rockchip-Add-internal-phase-support.patch new file mode 100644 index 00000000000000..663adaa9e6ffc1 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/035-01-v6.12-mmc-dw_mmc-rockchip-Add-internal-phase-support.patch @@ -0,0 +1,260 @@ +From 59903441f5e49d46478fefcccec41e2ba896b740 Mon Sep 17 00:00:00 2001 +From: Shawn Lin +Date: Wed, 28 Aug 2024 15:24:55 +0000 +Subject: [PATCH] mmc: dw_mmc-rockchip: Add internal phase support + +Some Rockchip devices put the phase settings into the dw_mmc controller. + +When the feature is present, the ciu-drive and ciu-sample clocks are +not used and the phase configuration is done directly through the mmc +controller. + +Signed-off-by: Shawn Lin +Signed-off-by: Detlev Casanova +Acked-by: Shawn Lin +Reviewed-by: Heiko Stuebner +Link: https://lore.kernel.org/r/010201919996fdae-8a9f843e-00a8-4131-98bf-a9da4ed04bfd-000000@eu-west-1.amazonses.com +Signed-off-by: Ulf Hansson +--- + drivers/mmc/host/dw_mmc-rockchip.c | 171 +++++++++++++++++++++++++++-- + 1 file changed, 160 insertions(+), 11 deletions(-) + +--- a/drivers/mmc/host/dw_mmc-rockchip.c ++++ b/drivers/mmc/host/dw_mmc-rockchip.c +@@ -15,7 +15,17 @@ + #include "dw_mmc.h" + #include "dw_mmc-pltfm.h" + +-#define RK3288_CLKGEN_DIV 2 ++#define RK3288_CLKGEN_DIV 2 ++#define SDMMC_TIMING_CON0 0x130 ++#define SDMMC_TIMING_CON1 0x134 ++#define ROCKCHIP_MMC_DELAY_SEL BIT(10) ++#define ROCKCHIP_MMC_DEGREE_MASK 0x3 ++#define ROCKCHIP_MMC_DEGREE_OFFSET 1 ++#define ROCKCHIP_MMC_DELAYNUM_OFFSET 2 ++#define ROCKCHIP_MMC_DELAYNUM_MASK (0xff << ROCKCHIP_MMC_DELAYNUM_OFFSET) ++#define ROCKCHIP_MMC_DELAY_ELEMENT_PSEC 60 ++#define HIWORD_UPDATE(val, mask, shift) \ ++ ((val) << (shift) | (mask) << ((shift) + 16)) + + static const unsigned int freqs[] = { 100000, 200000, 300000, 400000 }; + +@@ -24,8 +34,143 @@ struct dw_mci_rockchip_priv_data { + struct clk *sample_clk; + int default_sample_phase; + int num_phases; ++ bool internal_phase; + }; + ++/* ++ * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to ++ * simplify calculations. So 45degs could be anywhere between 33deg and 57.8deg. ++ */ ++static int rockchip_mmc_get_internal_phase(struct dw_mci *host, bool sample) ++{ ++ unsigned long rate = clk_get_rate(host->ciu_clk); ++ u32 raw_value; ++ u16 degrees; ++ u32 delay_num = 0; ++ ++ /* Constant signal, no measurable phase shift */ ++ if (!rate) ++ return 0; ++ ++ if (sample) ++ raw_value = mci_readl(host, TIMING_CON1); ++ else ++ raw_value = mci_readl(host, TIMING_CON0); ++ ++ raw_value >>= ROCKCHIP_MMC_DEGREE_OFFSET; ++ degrees = (raw_value & ROCKCHIP_MMC_DEGREE_MASK) * 90; ++ ++ if (raw_value & ROCKCHIP_MMC_DELAY_SEL) { ++ /* degrees/delaynum * 1000000 */ ++ unsigned long factor = (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10) * ++ 36 * (rate / 10000); ++ ++ delay_num = (raw_value & ROCKCHIP_MMC_DELAYNUM_MASK); ++ delay_num >>= ROCKCHIP_MMC_DELAYNUM_OFFSET; ++ degrees += DIV_ROUND_CLOSEST(delay_num * factor, 1000000); ++ } ++ ++ return degrees % 360; ++} ++ ++static int rockchip_mmc_get_phase(struct dw_mci *host, bool sample) ++{ ++ struct dw_mci_rockchip_priv_data *priv = host->priv; ++ struct clk *clock = sample ? priv->sample_clk : priv->drv_clk; ++ ++ if (priv->internal_phase) ++ return rockchip_mmc_get_internal_phase(host, sample); ++ else ++ return clk_get_phase(clock); ++} ++ ++static int rockchip_mmc_set_internal_phase(struct dw_mci *host, bool sample, int degrees) ++{ ++ unsigned long rate = clk_get_rate(host->ciu_clk); ++ u8 nineties, remainder; ++ u8 delay_num; ++ u32 raw_value; ++ u32 delay; ++ ++ /* ++ * The below calculation is based on the output clock from ++ * MMC host to the card, which expects the phase clock inherits ++ * the clock rate from its parent, namely the output clock ++ * provider of MMC host. However, things may go wrong if ++ * (1) It is orphan. ++ * (2) It is assigned to the wrong parent. ++ * ++ * This check help debug the case (1), which seems to be the ++ * most likely problem we often face and which makes it difficult ++ * for people to debug unstable mmc tuning results. ++ */ ++ if (!rate) { ++ dev_err(host->dev, "%s: invalid clk rate\n", __func__); ++ return -EINVAL; ++ } ++ ++ nineties = degrees / 90; ++ remainder = (degrees % 90); ++ ++ /* ++ * Due to the inexact nature of the "fine" delay, we might ++ * actually go non-monotonic. We don't go _too_ monotonic ++ * though, so we should be OK. Here are options of how we may ++ * work: ++ * ++ * Ideally we end up with: ++ * 1.0, 2.0, ..., 69.0, 70.0, ..., 89.0, 90.0 ++ * ++ * On one extreme (if delay is actually 44ps): ++ * .73, 1.5, ..., 50.6, 51.3, ..., 65.3, 90.0 ++ * The other (if delay is actually 77ps): ++ * 1.3, 2.6, ..., 88.6. 89.8, ..., 114.0, 90 ++ * ++ * It's possible we might make a delay that is up to 25 ++ * degrees off from what we think we're making. That's OK ++ * though because we should be REALLY far from any bad range. ++ */ ++ ++ /* ++ * Convert to delay; do a little extra work to make sure we ++ * don't overflow 32-bit / 64-bit numbers. ++ */ ++ delay = 10000000; /* PSECS_PER_SEC / 10000 / 10 */ ++ delay *= remainder; ++ delay = DIV_ROUND_CLOSEST(delay, ++ (rate / 1000) * 36 * ++ (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10)); ++ ++ delay_num = (u8) min_t(u32, delay, 255); ++ ++ raw_value = delay_num ? ROCKCHIP_MMC_DELAY_SEL : 0; ++ raw_value |= delay_num << ROCKCHIP_MMC_DELAYNUM_OFFSET; ++ raw_value |= nineties; ++ ++ if (sample) ++ mci_writel(host, TIMING_CON1, HIWORD_UPDATE(raw_value, 0x07ff, 1)); ++ else ++ mci_writel(host, TIMING_CON0, HIWORD_UPDATE(raw_value, 0x07ff, 1)); ++ ++ dev_dbg(host->dev, "set %s_phase(%d) delay_nums=%u actual_degrees=%d\n", ++ sample ? "sample" : "drv", degrees, delay_num, ++ rockchip_mmc_get_phase(host, sample) ++ ); ++ ++ return 0; ++} ++ ++static int rockchip_mmc_set_phase(struct dw_mci *host, bool sample, int degrees) ++{ ++ struct dw_mci_rockchip_priv_data *priv = host->priv; ++ struct clk *clock = sample ? priv->sample_clk : priv->drv_clk; ++ ++ if (priv->internal_phase) ++ return rockchip_mmc_set_internal_phase(host, sample, degrees); ++ else ++ return clk_set_phase(clock, degrees); ++} ++ + static void dw_mci_rk3288_set_ios(struct dw_mci *host, struct mmc_ios *ios) + { + struct dw_mci_rockchip_priv_data *priv = host->priv; +@@ -64,7 +209,7 @@ static void dw_mci_rk3288_set_ios(struct + + /* Make sure we use phases which we can enumerate with */ + if (!IS_ERR(priv->sample_clk) && ios->timing <= MMC_TIMING_SD_HS) +- clk_set_phase(priv->sample_clk, priv->default_sample_phase); ++ rockchip_mmc_set_phase(host, true, priv->default_sample_phase); + + /* + * Set the drive phase offset based on speed mode to achieve hold times. +@@ -127,7 +272,7 @@ static void dw_mci_rk3288_set_ios(struct + break; + } + +- clk_set_phase(priv->drv_clk, phase); ++ rockchip_mmc_set_phase(host, false, phase); + } + } + +@@ -151,6 +296,7 @@ static int dw_mci_rk3288_execute_tuning( + int longest_range_len = -1; + int longest_range = -1; + int middle_phase; ++ int phase; + + if (IS_ERR(priv->sample_clk)) { + dev_err(host->dev, "Tuning clock (sample_clk) not defined.\n"); +@@ -164,8 +310,10 @@ static int dw_mci_rk3288_execute_tuning( + + /* Try each phase and extract good ranges */ + for (i = 0; i < priv->num_phases; ) { +- clk_set_phase(priv->sample_clk, +- TUNING_ITERATION_TO_PHASE(i, priv->num_phases)); ++ rockchip_mmc_set_phase(host, true, ++ TUNING_ITERATION_TO_PHASE( ++ i, ++ priv->num_phases)); + + v = !mmc_send_tuning(mmc, opcode, NULL); + +@@ -211,7 +359,8 @@ static int dw_mci_rk3288_execute_tuning( + } + + if (ranges[0].start == 0 && ranges[0].end == priv->num_phases - 1) { +- clk_set_phase(priv->sample_clk, priv->default_sample_phase); ++ rockchip_mmc_set_phase(host, true, priv->default_sample_phase); ++ + dev_info(host->dev, "All phases work, using default phase %d.", + priv->default_sample_phase); + goto free; +@@ -248,12 +397,10 @@ static int dw_mci_rk3288_execute_tuning( + + middle_phase = ranges[longest_range].start + longest_range_len / 2; + middle_phase %= priv->num_phases; +- dev_info(host->dev, "Successfully tuned phase to %d\n", +- TUNING_ITERATION_TO_PHASE(middle_phase, priv->num_phases)); ++ phase = TUNING_ITERATION_TO_PHASE(middle_phase, priv->num_phases); ++ dev_info(host->dev, "Successfully tuned phase to %d\n", phase); + +- clk_set_phase(priv->sample_clk, +- TUNING_ITERATION_TO_PHASE(middle_phase, +- priv->num_phases)); ++ rockchip_mmc_set_phase(host, true, phase); + + free: + kfree(ranges); +@@ -287,6 +434,8 @@ static int dw_mci_rk3288_parse_dt(struct + + host->priv = priv; + ++ priv->internal_phase = false; ++ + return 0; + } + diff --git a/target/linux/rockchip/patches-6.6/035-02-v6.12-mmc-dw_mmc-rockchip-Add-support-for-rk3576-SoCs.patch b/target/linux/rockchip/patches-6.6/035-02-v6.12-mmc-dw_mmc-rockchip-Add-support-for-rk3576-SoCs.patch new file mode 100644 index 00000000000000..402c0026b98f7e --- /dev/null +++ b/target/linux/rockchip/patches-6.6/035-02-v6.12-mmc-dw_mmc-rockchip-Add-support-for-rk3576-SoCs.patch @@ -0,0 +1,111 @@ +From 73abb1f16e28d5a41d0abea779a3f0b75cf8823e Mon Sep 17 00:00:00 2001 +From: Detlev Casanova +Date: Wed, 28 Aug 2024 15:24:56 +0000 +Subject: [PATCH] mmc: dw_mmc-rockchip: Add support for rk3576 SoCs + +On rk3576 the tunable clocks are inside the controller itself, removing +the need for the "ciu-drive" and "ciu-sample" clocks. + +That makes it a new type of controller that has its own dt_parse function. + +Signed-off-by: Detlev Casanova +Reviewed-by: Heiko Stuebner +Link: https://lore.kernel.org/r/010201919997044d-c3a008d1-afbc-462f-a928-fc1ece785bdb-000000@eu-west-1.amazonses.com +Signed-off-by: Ulf Hansson +--- + drivers/mmc/host/dw_mmc-rockchip.c | 48 ++++++++++++++++++++++++++---- + 1 file changed, 43 insertions(+), 5 deletions(-) + +--- a/drivers/mmc/host/dw_mmc-rockchip.c ++++ b/drivers/mmc/host/dw_mmc-rockchip.c +@@ -407,7 +407,7 @@ free: + return ret; + } + +-static int dw_mci_rk3288_parse_dt(struct dw_mci *host) ++static int dw_mci_common_parse_dt(struct dw_mci *host) + { + struct device_node *np = host->dev->of_node; + struct dw_mci_rockchip_priv_data *priv; +@@ -417,13 +417,29 @@ static int dw_mci_rk3288_parse_dt(struct + return -ENOMEM; + + if (of_property_read_u32(np, "rockchip,desired-num-phases", +- &priv->num_phases)) ++ &priv->num_phases)) + priv->num_phases = 360; + + if (of_property_read_u32(np, "rockchip,default-sample-phase", +- &priv->default_sample_phase)) ++ &priv->default_sample_phase)) + priv->default_sample_phase = 0; + ++ host->priv = priv; ++ ++ return 0; ++} ++ ++static int dw_mci_rk3288_parse_dt(struct dw_mci *host) ++{ ++ struct dw_mci_rockchip_priv_data *priv; ++ int err; ++ ++ err = dw_mci_common_parse_dt(host); ++ if (err) ++ return err; ++ ++ priv = host->priv; ++ + priv->drv_clk = devm_clk_get(host->dev, "ciu-drive"); + if (IS_ERR(priv->drv_clk)) + dev_dbg(host->dev, "ciu-drive not available\n"); +@@ -432,13 +448,25 @@ static int dw_mci_rk3288_parse_dt(struct + if (IS_ERR(priv->sample_clk)) + dev_dbg(host->dev, "ciu-sample not available\n"); + +- host->priv = priv; +- + priv->internal_phase = false; + + return 0; + } + ++static int dw_mci_rk3576_parse_dt(struct dw_mci *host) ++{ ++ struct dw_mci_rockchip_priv_data *priv; ++ int err = dw_mci_common_parse_dt(host); ++ if (err) ++ return err; ++ ++ priv = host->priv; ++ ++ priv->internal_phase = true; ++ ++ return 0; ++} ++ + static int dw_mci_rockchip_init(struct dw_mci *host) + { + int ret, i; +@@ -480,11 +508,21 @@ static const struct dw_mci_drv_data rk32 + .init = dw_mci_rockchip_init, + }; + ++static const struct dw_mci_drv_data rk3576_drv_data = { ++ .common_caps = MMC_CAP_CMD23, ++ .set_ios = dw_mci_rk3288_set_ios, ++ .execute_tuning = dw_mci_rk3288_execute_tuning, ++ .parse_dt = dw_mci_rk3576_parse_dt, ++ .init = dw_mci_rockchip_init, ++}; ++ + static const struct of_device_id dw_mci_rockchip_match[] = { + { .compatible = "rockchip,rk2928-dw-mshc", + .data = &rk2928_drv_data }, + { .compatible = "rockchip,rk3288-dw-mshc", + .data = &rk3288_drv_data }, ++ { .compatible = "rockchip,rk3576-dw-mshc", ++ .data = &rk3576_drv_data }, + {}, + }; + MODULE_DEVICE_TABLE(of, dw_mci_rockchip_match); diff --git a/target/linux/rockchip/patches-6.6/301-pinctrl-rockchip-add-rk3528-support.patch b/target/linux/rockchip/patches-6.6/301-pinctrl-rockchip-add-rk3528-support.patch deleted file mode 100644 index b8bf869eb99418..00000000000000 --- a/target/linux/rockchip/patches-6.6/301-pinctrl-rockchip-add-rk3528-support.patch +++ /dev/null @@ -1,269 +0,0 @@ -From ee5af82a6f88fd28849ea6d98cf43fbe9cbbbb19 Mon Sep 17 00:00:00 2001 -From: Steven Liu -Date: Thu, 11 Aug 2022 15:15:28 +0800 -Subject: [PATCH] pinctrl: rockchip: add rk3528 support - -Signed-off-by: Steven Liu -Change-Id: I2c1d32907168caf8a8afee6d1f742795b3d13536 ---- - drivers/pinctrl/pinctrl-rockchip.c | 196 ++++++++++++++++++++++++++++- - drivers/pinctrl/pinctrl-rockchip.h | 1 + - 2 files changed, 196 insertions(+), 1 deletion(-) - ---- a/drivers/pinctrl/pinctrl-rockchip.c -+++ b/drivers/pinctrl/pinctrl-rockchip.c -@@ -2036,6 +2036,150 @@ static int rk3568_calc_pull_reg_and_bit( - return 0; - } - -+#define RK3528_DRV_BITS_PER_PIN 8 -+#define RK3528_DRV_PINS_PER_REG 2 -+#define RK3528_DRV_GPIO0_OFFSET 0x100 -+#define RK3528_DRV_GPIO1_OFFSET 0x20120 -+#define RK3528_DRV_GPIO2_OFFSET 0x30160 -+#define RK3528_DRV_GPIO3_OFFSET 0x20190 -+#define RK3528_DRV_GPIO4_OFFSET 0x101C0 -+ -+static int rk3528_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, -+ int pin_num, struct regmap **regmap, -+ int *reg, u8 *bit) -+{ -+ struct rockchip_pinctrl *info = bank->drvdata; -+ -+ *regmap = info->regmap_base; -+ switch (bank->bank_num) { -+ case 0: -+ *reg = RK3528_DRV_GPIO0_OFFSET; -+ break; -+ -+ case 1: -+ *reg = RK3528_DRV_GPIO1_OFFSET; -+ break; -+ -+ case 2: -+ *reg = RK3528_DRV_GPIO2_OFFSET; -+ break; -+ -+ case 3: -+ *reg = RK3528_DRV_GPIO3_OFFSET; -+ break; -+ -+ case 4: -+ *reg = RK3528_DRV_GPIO4_OFFSET; -+ break; -+ -+ default: -+ dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num); -+ break; -+ } -+ -+ *reg += ((pin_num / RK3528_DRV_PINS_PER_REG) * 4); -+ *bit = pin_num % RK3528_DRV_PINS_PER_REG; -+ *bit *= RK3528_DRV_BITS_PER_PIN; -+ -+ return 0; -+} -+ -+#define RK3528_PULL_BITS_PER_PIN 2 -+#define RK3528_PULL_PINS_PER_REG 8 -+#define RK3528_PULL_GPIO0_OFFSET 0x200 -+#define RK3528_PULL_GPIO1_OFFSET 0x20210 -+#define RK3528_PULL_GPIO2_OFFSET 0x30220 -+#define RK3528_PULL_GPIO3_OFFSET 0x20230 -+#define RK3528_PULL_GPIO4_OFFSET 0x10240 -+ -+static int rk3528_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, -+ int pin_num, struct regmap **regmap, -+ int *reg, u8 *bit) -+{ -+ struct rockchip_pinctrl *info = bank->drvdata; -+ -+ *regmap = info->regmap_base; -+ switch (bank->bank_num) { -+ case 0: -+ *reg = RK3528_PULL_GPIO0_OFFSET; -+ break; -+ -+ case 1: -+ *reg = RK3528_PULL_GPIO1_OFFSET; -+ break; -+ -+ case 2: -+ *reg = RK3528_PULL_GPIO2_OFFSET; -+ break; -+ -+ case 3: -+ *reg = RK3528_PULL_GPIO3_OFFSET; -+ break; -+ -+ case 4: -+ *reg = RK3528_PULL_GPIO4_OFFSET; -+ break; -+ -+ default: -+ dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num); -+ break; -+ } -+ -+ *reg += ((pin_num / RK3528_PULL_PINS_PER_REG) * 4); -+ *bit = pin_num % RK3528_PULL_PINS_PER_REG; -+ *bit *= RK3528_PULL_BITS_PER_PIN; -+ -+ return 0; -+} -+ -+#define RK3528_SMT_BITS_PER_PIN 1 -+#define RK3528_SMT_PINS_PER_REG 8 -+#define RK3528_SMT_GPIO0_OFFSET 0x400 -+#define RK3528_SMT_GPIO1_OFFSET 0x20410 -+#define RK3528_SMT_GPIO2_OFFSET 0x30420 -+#define RK3528_SMT_GPIO3_OFFSET 0x20430 -+#define RK3528_SMT_GPIO4_OFFSET 0x10440 -+ -+static int rk3528_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, -+ int pin_num, -+ struct regmap **regmap, -+ int *reg, u8 *bit) -+{ -+ struct rockchip_pinctrl *info = bank->drvdata; -+ -+ *regmap = info->regmap_base; -+ switch (bank->bank_num) { -+ case 0: -+ *reg = RK3528_SMT_GPIO0_OFFSET; -+ break; -+ -+ case 1: -+ *reg = RK3528_SMT_GPIO1_OFFSET; -+ break; -+ -+ case 2: -+ *reg = RK3528_SMT_GPIO2_OFFSET; -+ break; -+ -+ case 3: -+ *reg = RK3528_SMT_GPIO3_OFFSET; -+ break; -+ -+ case 4: -+ *reg = RK3528_SMT_GPIO4_OFFSET; -+ break; -+ -+ default: -+ dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num); -+ break; -+ } -+ -+ *reg += ((pin_num / RK3528_SMT_PINS_PER_REG) * 4); -+ *bit = pin_num % RK3528_SMT_PINS_PER_REG; -+ *bit *= RK3528_SMT_BITS_PER_PIN; -+ return 0; -+} -+ - #define RK3568_DRV_PMU_OFFSET 0x70 - #define RK3568_DRV_GRF_OFFSET 0x200 - #define RK3568_DRV_BITS_PER_PIN 8 -@@ -2495,6 +2639,10 @@ static int rockchip_set_drive_perpin(str - rmask_bits = RK3588_DRV_BITS_PER_PIN; - ret = strength; - goto config; -+ } else if (ctrl->type == RK3528) { -+ rmask_bits = RK3528_DRV_BITS_PER_PIN; -+ ret = (1 << (strength + 1)) - 1; -+ goto config; - } else if (ctrl->type == RK3568) { - rmask_bits = RK3568_DRV_BITS_PER_PIN; - ret = (1 << (strength + 1)) - 1; -@@ -2639,6 +2787,7 @@ static int rockchip_get_pull(struct rock - case RK3328: - case RK3368: - case RK3399: -+ case RK3528: - case RK3568: - case RK3576: - case RK3588: -@@ -2699,6 +2848,7 @@ static int rockchip_set_pull(struct rock - case RK3328: - case RK3368: - case RK3399: -+ case RK3528: - case RK3568: - case RK3576: - case RK3588: -@@ -2965,6 +3115,7 @@ static bool rockchip_pinconf_pull_valid( - case RK3328: - case RK3368: - case RK3399: -+ case RK3528: - case RK3568: - case RK3576: - case RK3588: -@@ -4091,6 +4242,49 @@ static struct rockchip_pin_ctrl rk3399_p - .drv_calc_reg = rk3399_calc_drv_reg_and_bit, - }; - -+static struct rockchip_pin_bank rk3528_pin_banks[] = { -+ PIN_BANK_IOMUX_FLAGS_OFFSET(0, 32, "gpio0", -+ IOMUX_WIDTH_4BIT, -+ IOMUX_WIDTH_4BIT, -+ IOMUX_WIDTH_4BIT, -+ IOMUX_WIDTH_4BIT, -+ 0, 0, 0, 0), -+ PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1", -+ IOMUX_WIDTH_4BIT, -+ IOMUX_WIDTH_4BIT, -+ IOMUX_WIDTH_4BIT, -+ IOMUX_WIDTH_4BIT, -+ 0x20020, 0x20028, 0x20030, 0x20038), -+ PIN_BANK_IOMUX_FLAGS_OFFSET(2, 32, "gpio2", -+ IOMUX_WIDTH_4BIT, -+ IOMUX_WIDTH_4BIT, -+ IOMUX_WIDTH_4BIT, -+ IOMUX_WIDTH_4BIT, -+ 0x30040, 0, 0, 0), -+ PIN_BANK_IOMUX_FLAGS_OFFSET(3, 32, "gpio3", -+ IOMUX_WIDTH_4BIT, -+ IOMUX_WIDTH_4BIT, -+ IOMUX_WIDTH_4BIT, -+ IOMUX_WIDTH_4BIT, -+ 0x20060, 0x20068, 0x20070, 0), -+ PIN_BANK_IOMUX_FLAGS_OFFSET(4, 32, "gpio4", -+ IOMUX_WIDTH_4BIT, -+ IOMUX_WIDTH_4BIT, -+ IOMUX_WIDTH_4BIT, -+ IOMUX_WIDTH_4BIT, -+ 0x10080, 0x10088, 0x10090, 0x10098), -+}; -+ -+static struct rockchip_pin_ctrl rk3528_pin_ctrl __maybe_unused = { -+ .pin_banks = rk3528_pin_banks, -+ .nr_banks = ARRAY_SIZE(rk3528_pin_banks), -+ .label = "RK3528-GPIO", -+ .type = RK3528, -+ .pull_calc_reg = rk3528_calc_pull_reg_and_bit, -+ .drv_calc_reg = rk3528_calc_drv_reg_and_bit, -+ .schmitt_calc_reg = rk3528_calc_schmitt_reg_and_bit, -+}; -+ - static struct rockchip_pin_bank rk3568_pin_banks[] = { - PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT, - IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT, -@@ -4215,6 +4409,8 @@ static const struct of_device_id rockchi - .data = &rk3368_pin_ctrl }, - { .compatible = "rockchip,rk3399-pinctrl", - .data = &rk3399_pin_ctrl }, -+ { .compatible = "rockchip,rk3528-pinctrl", -+ .data = &rk3528_pin_ctrl }, - { .compatible = "rockchip,rk3568-pinctrl", - .data = &rk3568_pin_ctrl }, - { .compatible = "rockchip,rk3576-pinctrl", ---- a/drivers/pinctrl/pinctrl-rockchip.h -+++ b/drivers/pinctrl/pinctrl-rockchip.h -@@ -196,6 +196,7 @@ enum rockchip_pinctrl_type { - RK3328, - RK3368, - RK3399, -+ RK3528, - RK3568, - RK3576, - RK3588, diff --git a/target/linux/rockchip/patches-6.6/302-thermal-rockchip-add-support-for-rk3528.patch b/target/linux/rockchip/patches-6.6/302-thermal-rockchip-add-support-for-rk3528.patch deleted file mode 100644 index 600229e78fbac9..00000000000000 --- a/target/linux/rockchip/patches-6.6/302-thermal-rockchip-add-support-for-rk3528.patch +++ /dev/null @@ -1,191 +0,0 @@ -From 1e244fb37e21ce92a32b203cb030510bc3b42d29 Mon Sep 17 00:00:00 2001 -From: Shaohan Yao -Date: Fri, 9 Sep 2022 14:34:08 +0800 -Subject: [PATCH] thermal: rockchip: Support the rk3528 SoC in thermal driver - -There are one Temperature Sensor on rk3528, channel 0 is for chip. - -Signed-off-by: Shaohan Yao -Change-Id: Ib5bbb81615fe9fab80f26cdd2098cfb56746ca15 ---- - drivers/thermal/rockchip_thermal.c | 107 +++++++++++++++++++++++++++++ - 1 file changed, 107 insertions(+) - ---- a/drivers/thermal/rockchip_thermal.c -+++ b/drivers/thermal/rockchip_thermal.c -@@ -185,6 +185,8 @@ struct rockchip_thermal_data { - #define TSADCV2_AUTO_PERIOD_HT 0x6c - #define TSADCV3_AUTO_PERIOD 0x154 - #define TSADCV3_AUTO_PERIOD_HT 0x158 -+#define TSADCV9_Q_MAX 0x210 -+#define TSADCV9_FLOW_CON 0x218 - - #define TSADCV2_AUTO_EN BIT(0) - #define TSADCV2_AUTO_EN_MASK BIT(16) -@@ -195,6 +197,7 @@ struct rockchip_thermal_data { - #define TSADCV2_AUTO_TSHUT_POLARITY_MASK BIT(24) - - #define TSADCV3_AUTO_Q_SEL_EN BIT(1) -+#define TSADCV3_AUTO_Q_SEL_EN_MASK BIT(17) - - #define TSADCV2_INT_SRC_EN(chn) BIT(chn) - #define TSADCV2_INT_SRC_EN_MASK(chn) BIT(16 + (chn)) -@@ -208,9 +211,12 @@ struct rockchip_thermal_data { - #define TSADCV2_DATA_MASK 0xfff - #define TSADCV3_DATA_MASK 0x3ff - #define TSADCV4_DATA_MASK 0x1ff -+#define TSADCV5_DATA_MASK 0x7ff - - #define TSADCV2_HIGHT_INT_DEBOUNCE_COUNT 4 - #define TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT 4 -+#define TSADCV3_HIGHT_INT_DEBOUNCE 0x14c -+#define TSADCV3_HIGHT_TSHUT_DEBOUNCE 0x150 - #define TSADCV2_AUTO_PERIOD_TIME 250 /* 250ms */ - #define TSADCV2_AUTO_PERIOD_HT_TIME 50 /* 50ms */ - #define TSADCV3_AUTO_PERIOD_TIME 1875 /* 2.5ms */ -@@ -220,6 +226,9 @@ struct rockchip_thermal_data { - #define TSADCV5_AUTO_PERIOD_HT_TIME 1622 /* 2.5ms */ - #define TSADCV6_AUTO_PERIOD_TIME 5000 /* 2.5ms */ - #define TSADCV6_AUTO_PERIOD_HT_TIME 5000 /* 2.5ms */ -+#define TSADCV7_AUTO_PERIOD_TIME 3000 /* 2.5ms */ -+#define TSADCV7_AUTO_PERIOD_HT_TIME 3000 /* 2.5ms */ -+#define TSADCV3_Q_MAX_VAL 0x7ff /* 11bit 2047 */ - - #define TSADCV2_USER_INTER_PD_SOC 0x340 /* 13 clocks */ - #define TSADCV5_USER_INTER_PD_SOC 0xfc0 /* 97us, at least 90us */ -@@ -230,6 +239,8 @@ struct rockchip_thermal_data { - - #define PX30_GRF_SOC_CON2 0x0408 - -+#define RK3528_GRF_TSADC_CON 0x40030 -+ - #define RK3568_GRF_TSADC_CON 0x0600 - #define RK3568_GRF_TSADC_ANA_REG0 (0x10001 << 0) - #define RK3568_GRF_TSADC_ANA_REG1 (0x10001 << 1) -@@ -497,6 +508,45 @@ static const struct tsadc_table rk3399_c - {TSADCV3_DATA_MASK, 125000}, - }; - -+static const struct tsadc_table rk3528_code_table[] = { -+ {0, -40000}, -+ {1419, -40000}, -+ {1427, -35000}, -+ {1435, -30000}, -+ {1443, -25000}, -+ {1452, -20000}, -+ {1460, -15000}, -+ {1468, -10000}, -+ {1477, -5000}, -+ {1486, 0}, -+ {1494, 5000}, -+ {1502, 10000}, -+ {1510, 15000}, -+ {1519, 20000}, -+ {1527, 25000}, -+ {1535, 30000}, -+ {1544, 35000}, -+ {1552, 40000}, -+ {1561, 45000}, -+ {1569, 50000}, -+ {1578, 55000}, -+ {1586, 60000}, -+ {1594, 65000}, -+ {1603, 70000}, -+ {1612, 75000}, -+ {1620, 80000}, -+ {1628, 85000}, -+ {1637, 90000}, -+ {1646, 95000}, -+ {1654, 100000}, -+ {1662, 105000}, -+ {1671, 110000}, -+ {1679, 115000}, -+ {1688, 120000}, -+ {1696, 125000}, -+ {TSADCV5_DATA_MASK, 125000}, -+}; -+ - static const struct tsadc_table rk3568_code_table[] = { - {0, -40000}, - {1584, -40000}, -@@ -834,6 +884,37 @@ static void rk_tsadcv8_initialize(struct - regs + TSADCV2_AUTO_CON); - } - -+static void rk_tsadcv11_initialize(struct regmap *grf, void __iomem *regs, -+ enum tshut_polarity tshut_polarity) -+{ -+ writel_relaxed(TSADCV7_AUTO_PERIOD_TIME, regs + TSADCV3_AUTO_PERIOD); -+ writel_relaxed(TSADCV7_AUTO_PERIOD_HT_TIME, -+ regs + TSADCV3_AUTO_PERIOD_HT); -+ writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT, -+ regs + TSADCV3_HIGHT_INT_DEBOUNCE); -+ writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT, -+ regs + TSADCV3_HIGHT_TSHUT_DEBOUNCE); -+ writel_relaxed(TSADCV3_Q_MAX_VAL, regs + TSADCV9_Q_MAX); -+ writel_relaxed(TSADCV3_AUTO_Q_SEL_EN | TSADCV3_AUTO_Q_SEL_EN_MASK, -+ regs + TSADCV2_AUTO_CON); -+ if (tshut_polarity == TSHUT_HIGH_ACTIVE) -+ writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_HIGH | -+ TSADCV2_AUTO_TSHUT_POLARITY_MASK, -+ regs + TSADCV2_AUTO_CON); -+ else -+ writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_MASK, -+ regs + TSADCV2_AUTO_CON); -+ -+ if (!IS_ERR(grf)) { -+ regmap_write(grf, RK3528_GRF_TSADC_CON, RK3568_GRF_TSADC_TSEN); -+ udelay(15); -+ regmap_write(grf, RK3528_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG0); -+ regmap_write(grf, RK3528_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG1); -+ regmap_write(grf, RK3528_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG2); -+ usleep_range(100, 200); -+ } -+} -+ - static void rk_tsadcv2_irq_ack(void __iomem *regs) - { - u32 val; -@@ -1258,6 +1339,31 @@ static const struct rockchip_tsadc_chip - }, - }; - -+static const struct rockchip_tsadc_chip rk3528_tsadc_data = { -+ /* cpu, gpu */ -+ .chn_offset = 0, -+ .chn_num = 1, /* one channels for tsadc */ -+ -+ .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ -+ .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ -+ .tshut_temp = 95000, -+ -+ .initialize = rk_tsadcv11_initialize, -+ .irq_ack = rk_tsadcv4_irq_ack, -+ .control = rk_tsadcv4_control, -+ .get_temp = rk_tsadcv4_get_temp, -+ .set_alarm_temp = rk_tsadcv3_alarm_temp, -+ .set_tshut_temp = rk_tsadcv3_tshut_temp, -+ .set_tshut_mode = rk_tsadcv3_tshut_mode, -+ -+ .table = { -+ .id = rk3528_code_table, -+ .length = ARRAY_SIZE(rk3528_code_table), -+ .data_mask = TSADCV2_DATA_MASK, -+ .mode = ADC_INCREMENT, -+ }, -+}; -+ - static const struct rockchip_tsadc_chip rk3568_tsadc_data = { - /* cpu, gpu */ - .chn_offset = 0, -@@ -1338,6 +1444,10 @@ static const struct of_device_id of_rock - .data = (void *)&rk3399_tsadc_data, - }, - { -+ .compatible = "rockchip,rk3528-tsadc", -+ .data = (void *)&rk3528_tsadc_data, -+ }, -+ { - .compatible = "rockchip,rk3568-tsadc", - .data = (void *)&rk3568_tsadc_data, - }, diff --git a/target/linux/rockchip/patches-6.6/304-soc-rockchip-power-domain-add-rk3528-support.patch b/target/linux/rockchip/patches-6.6/304-soc-rockchip-power-domain-add-rk3528-support.patch deleted file mode 100644 index 842dd18559baa4..00000000000000 --- a/target/linux/rockchip/patches-6.6/304-soc-rockchip-power-domain-add-rk3528-support.patch +++ /dev/null @@ -1,103 +0,0 @@ -From 2ed777fcd035089bd7996bfa09c023521ecf0e24 Mon Sep 17 00:00:00 2001 -From: Finley Xiao -Date: Fri, 30 Sep 2022 20:11:50 +0800 -Subject: [PATCH] soc: rockchip: power-domain: add power domain support for - rk3528 - -This driver is modified to support RK3528 SoCs. - -Signed-off-by: Finley Xiao -Change-Id: If024916eb7b52ec86ff7533aedefc1bda457b612 ---- - drivers/pmdomain/rockchip/pm-domains.c | 47 +++++++++++++++++++++++++++++++ - 1 file changed, 47 insertions(+) - ---- a/drivers/pmdomain/rockchip/pm-domains.c -+++ b/drivers/pmdomain/rockchip/pm-domains.c -@@ -30,6 +30,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -128,6 +129,20 @@ struct rockchip_pmu { - .active_wakeup = wakeup, \ - } - -+#define DOMAIN_M_A(_name, pwr, status, req, idle, ack, always, wakeup) \ -+{ \ -+ .name = _name, \ -+ .pwr_w_mask = (pwr) << 16, \ -+ .pwr_mask = (pwr), \ -+ .status_mask = (status), \ -+ .req_w_mask = (req) << 16, \ -+ .req_mask = (req), \ -+ .idle_mask = (idle), \ -+ .ack_mask = (ack), \ -+ .always_on = always, \ -+ .active_wakeup = wakeup, \ -+} -+ - #define DOMAIN_M_O_R(_name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, ack, wakeup) \ - { \ - .name = _name, \ -@@ -193,6 +208,9 @@ struct rockchip_pmu { - #define DOMAIN_RK3399(name, pwr, status, req, wakeup) \ - DOMAIN(name, pwr, status, req, req, req, wakeup) - -+#define DOMAIN_RK3528(name, pwr, req, always, wakeup) \ -+ DOMAIN_M_A(name, pwr, pwr, req, req, req, always, wakeup) -+ - #define DOMAIN_RK3568(name, pwr, req, wakeup) \ - DOMAIN_M(name, pwr, pwr, req, req, req, wakeup) - -@@ -1173,6 +1191,18 @@ static const struct rockchip_domain_info - [RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399("sdioaudio", BIT(31), BIT(31), BIT(29), true), - }; - -+static const struct rockchip_domain_info rk3528_pm_domains[] = { -+ [RK3528_PD_PMU] = DOMAIN_RK3528("pmu", 0, BIT(0), true, false), -+ [RK3528_PD_BUS] = DOMAIN_RK3528("bus", 0, BIT(1), true, false), -+ [RK3528_PD_DDR] = DOMAIN_RK3528("ddr", 0, BIT(2), true, false), -+ [RK3528_PD_MSCH] = DOMAIN_RK3528("msch", 0, BIT(3), true, false), -+ [RK3528_PD_GPU] = DOMAIN_RK3528("gpu", BIT(0), BIT(4), true, false), -+ [RK3528_PD_RKVDEC] = DOMAIN_RK3528("vdec", 0, BIT(5), true, false), -+ [RK3528_PD_RKVENC] = DOMAIN_RK3528("venc", 0, BIT(6), true, false), -+ [RK3528_PD_VO] = DOMAIN_RK3528("vo", 0, BIT(7), true, false), -+ [RK3528_PD_VPU] = DOMAIN_RK3528("vpu", 0, BIT(8), true, false), -+}; -+ - static const struct rockchip_domain_info rk3568_pm_domains[] = { - [RK3568_PD_NPU] = DOMAIN_RK3568("npu", BIT(1), BIT(2), false), - [RK3568_PD_GPU] = DOMAIN_RK3568("gpu", BIT(0), BIT(1), false), -@@ -1374,6 +1404,17 @@ static const struct rockchip_pmu_info rk - .domain_info = rk3399_pm_domains, - }; - -+static const struct rockchip_pmu_info rk3528_pmu = { -+ .pwr_offset = 0x1210, -+ .status_offset = 0x1230, -+ .req_offset = 0x1110, -+ .idle_offset = 0x1128, -+ .ack_offset = 0x1120, -+ -+ .num_domains = ARRAY_SIZE(rk3528_pm_domains), -+ .domain_info = rk3528_pm_domains, -+}; -+ - static const struct rockchip_pmu_info rk3568_pmu = { - .pwr_offset = 0xa0, - .status_offset = 0x98, -@@ -1473,6 +1514,10 @@ static const struct of_device_id rockchi - .data = (void *)&rk3399_pmu, - }, - { -+ .compatible = "rockchip,rk3528-power-controller", -+ .data = (void *)&rk3528_pmu, -+ }, -+ { - .compatible = "rockchip,rk3568-power-controller", - .data = (void *)&rk3568_pmu, - }, diff --git a/target/linux/rockchip/patches-6.6/305-clk-rockchip-add-clock-controller-for-the-RK3528.patch b/target/linux/rockchip/patches-6.6/305-clk-rockchip-add-clock-controller-for-the-RK3528.patch deleted file mode 100644 index a61b532b7ceee6..00000000000000 --- a/target/linux/rockchip/patches-6.6/305-clk-rockchip-add-clock-controller-for-the-RK3528.patch +++ /dev/null @@ -1,179 +0,0 @@ -From 16f512f1e10375dc48aa6c26cedeb7079aba01de Mon Sep 17 00:00:00 2001 -From: Joseph Chen -Date: Sat, 13 Aug 2022 01:15:20 +0000 -Subject: [PATCH] clk: rockchip: Add clock controller for the RK3528 - -Add the clock tree definition for the new RK3528 SoC. - -gmac1 clocks are all controlled by GRF, but CRU helps to abstract -these two clocks for gmac1 since the clock source is from CRU. - -The io-in clocks are module phy output clock, gating child -clocks by disabling phy output but not CRU gate. - -Add gmac0 clocks. -They are all orphans if clk_gmac0_io_i is not registered by -GMAC driver. But it's fine that GMAC driver only get it but -not to set/get rate. - -Add CLK_SET_RATE_PARENT for mclk_sai_i2s0/1. -Allowed to change parent rate. - -Add CLK_SET_RATE_NO_REPARENT for dclk_vop0. -dclk_vop0 is often used for HDMI, it prefers parent clock from -clk_hdmiphy_pixel_io for better clock quality and any rate. -It assigns clk_hdmiphy_pixel_io as parent in dts and hope not to -change parent any more. - -Add CLK_SET_RATE_PARENT for aclk_gpu. -Allow aclk_gpu and aclk_gpu_mali to change parent rate. - -Add CLK_SET_RATE_PARENT for aclk_rkvdec_pvtmux_root. -Allow aclk_rkvdec_pvtmux_root and aclk_rkvdec to change parent rate. - -set aclk_m_core = core_clk/2. -aclk_m_core signoff is 550M, but we set div=2 for better -performance. - -Add CLK_IS_CRITICAL for clk_32k. -Mainly for pvtpll during reboot stage. - -Add CLK_IS_CRITICAL for all IOC clocks. -IOC doesn't share clock with GRF. The iomux can't be changed if they -are disabled. - -Disable aclk_{vpu,vpu_l,vo}_root rate change -They are all shared by multiple modules, disable rate change -by modules. - -Don't register clk_uart_jtag -It's for force jtag uart delay counter. It must be open -for box product without tf card but with uart0. - -Signed-off-by: Joseph Chen -Signed-off-by: Elaine Zhang -Change-Id: I09745b6a31484d6a27f04e608268d9738c1fe224 ---- - drivers/clk/rockchip/Kconfig | 7 + - drivers/clk/rockchip/Makefile | 1 + - drivers/clk/rockchip/clk-rk3528.c | 1187 +++++++++++++++++++++++++++++ - drivers/clk/rockchip/clk.h | 28 + - 4 files changed, 1223 insertions(+) - create mode 100644 drivers/clk/rockchip/clk-rk3528.c - ---- a/drivers/clk/rockchip/Kconfig -+++ b/drivers/clk/rockchip/Kconfig -@@ -93,6 +93,13 @@ config CLK_RK3399 - help - Build the driver for RK3399 Clock Driver. - -+config CLK_RK3528 -+ bool "Rockchip RK3528 clock controller support" -+ depends on ARM64 || COMPILE_TEST -+ default y -+ help -+ Build the driver for RK3528 Clock Driver. -+ - config CLK_RK3568 - bool "Rockchip RK3568 clock controller support" - depends on ARM64 || COMPILE_TEST ---- a/drivers/clk/rockchip/Makefile -+++ b/drivers/clk/rockchip/Makefile -@@ -27,6 +27,7 @@ obj-$(CONFIG_CLK_RK3308) += clk-r - obj-$(CONFIG_CLK_RK3328) += clk-rk3328.o - obj-$(CONFIG_CLK_RK3368) += clk-rk3368.o - obj-$(CONFIG_CLK_RK3399) += clk-rk3399.o -+obj-$(CONFIG_CLK_RK3528) += clk-rk3528.o - obj-$(CONFIG_CLK_RK3568) += clk-rk3568.o - obj-$(CONFIG_CLK_RK3576) += clk-rk3576.o rst-rk3576.o - obj-$(CONFIG_CLK_RK3588) += clk-rk3588.o rst-rk3588.o ---- a/drivers/clk/rockchip/clk.c -+++ b/drivers/clk/rockchip/clk.c -@@ -527,6 +527,14 @@ void rockchip_clk_register_branches(stru - ctx->reg_base + list->gate_offset, - list->gate_shift, list->gate_flags, &ctx->lock); - break; -+ case branch_gate_no_set_rate: -+ flags &= ~CLK_SET_RATE_PARENT; -+ -+ clk = clk_register_gate(NULL, list->name, -+ list->parent_names[0], flags, -+ ctx->reg_base + list->gate_offset, -+ list->gate_shift, list->gate_flags, &ctx->lock); -+ break; - case branch_composite: - clk = rockchip_clk_register_branch(list->name, - list->parent_names, list->num_parents, ---- a/drivers/clk/rockchip/clk.h -+++ b/drivers/clk/rockchip/clk.h -@@ -207,6 +207,34 @@ struct clk; - #define RK3399_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x100) - #define RK3399_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x110) - -+#define RK3528_PMU_CRU_BASE 0x10000 -+#define RK3528_PCIE_CRU_BASE 0x20000 -+#define RK3528_DDRPHY_CRU_BASE 0x28000 -+#define RK3528_VPU_GRF_BASE 0x40000 -+#define RK3528_VO_GRF_BASE 0x60000 -+#define RK3528_SDMMC_CON0 (RK3528_VO_GRF_BASE + 0x24) -+#define RK3528_SDMMC_CON1 (RK3528_VO_GRF_BASE + 0x28) -+#define RK3528_SDIO0_CON0 (RK3528_VPU_GRF_BASE + 0x4) -+#define RK3528_SDIO0_CON1 (RK3528_VPU_GRF_BASE + 0x8) -+#define RK3528_SDIO1_CON0 (RK3528_VPU_GRF_BASE + 0xc) -+#define RK3528_SDIO1_CON1 (RK3528_VPU_GRF_BASE + 0x10) -+#define RK3528_PLL_CON(x) RK2928_PLL_CON(x) -+#define RK3528_PCIE_PLL_CON(x) ((x) * 0x4 + RK3528_PCIE_CRU_BASE) -+#define RK3528_DDRPHY_PLL_CON(x) ((x) * 0x4 + RK3528_DDRPHY_CRU_BASE) -+#define RK3528_MODE_CON 0x280 -+#define RK3528_CLKSEL_CON(x) ((x) * 0x4 + 0x300) -+#define RK3528_CLKGATE_CON(x) ((x) * 0x4 + 0x800) -+#define RK3528_SOFTRST_CON(x) ((x) * 0x4 + 0xa00) -+#define RK3528_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PMU_CRU_BASE) -+#define RK3528_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RK3528_PMU_CRU_BASE) -+#define RK3528_PCIE_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PCIE_CRU_BASE) -+#define RK3528_PCIE_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RK3528_PCIE_CRU_BASE) -+#define RK3528_DDRPHY_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RK3528_DDRPHY_CRU_BASE) -+#define RK3528_DDRPHY_MODE_CON (0x280 + RK3528_DDRPHY_CRU_BASE) -+#define RK3528_GLB_CNT_TH 0xc00 -+#define RK3528_GLB_SRST_FST 0xc08 -+#define RK3528_GLB_SRST_SND 0xc0c -+ - #define RK3568_PLL_CON(x) RK2928_PLL_CON(x) - #define RK3568_MODE_CON0 0xc0 - #define RK3568_MISC_CON0 0xc4 -@@ -461,6 +489,7 @@ struct rockchip_pll_clock { - }; - - #define ROCKCHIP_PLL_SYNC_RATE BIT(0) -+#define ROCKCHIP_PLL_FIXED_MODE BIT(1) - - #define PLL(_type, _id, _name, _pnames, _flags, _con, _mode, _mshift, \ - _lshift, _pflags, _rtable) \ -@@ -569,6 +598,7 @@ enum rockchip_clk_branch_type { - branch_muxgrf, - branch_divider, - branch_fraction_divider, -+ branch_gate_no_set_rate, - branch_gate, - branch_mmc, - branch_inverter, -@@ -889,6 +919,19 @@ struct rockchip_clk_branch { - .name = cname, \ - .parent_names = (const char *[]){ pname }, \ - .num_parents = 1, \ -+ .flags = f, \ -+ .gate_offset = o, \ -+ .gate_shift = b, \ -+ .gate_flags = gf, \ -+ } -+ -+#define GATE_NO_SET_RATE(_id, cname, pname, f, o, b, gf) \ -+ { \ -+ .id = _id, \ -+ .branch_type = branch_gate_no_set_rate, \ -+ .name = cname, \ -+ .parent_names = (const char *[]){ pname }, \ -+ .num_parents = 1, \ - .flags = f, \ - .gate_offset = o, \ - .gate_shift = b, \ diff --git a/target/linux/rockchip/patches-6.6/306-ethernet-stmmac-dwmac-rk3528-add-GMAC-support.patch b/target/linux/rockchip/patches-6.6/306-ethernet-stmmac-dwmac-rk3528-add-GMAC-support.patch deleted file mode 100644 index b75531d4349bdb..00000000000000 --- a/target/linux/rockchip/patches-6.6/306-ethernet-stmmac-dwmac-rk3528-add-GMAC-support.patch +++ /dev/null @@ -1,227 +0,0 @@ -From 61c0ac431798861b0696ccc549138b2eec8a4766 Mon Sep 17 00:00:00 2001 -From: David Wu -Date: Sat, 24 Sep 2022 18:29:52 +0800 -Subject: [PATCH] ethernet: stmmac: dwmac-rk: Add GMAC support for RK3528 - -Add constants and callback functions for the dwmac on RK3528 Soc. -As can be seen, the base structure is the same. In addition, there -is an internal phy inside with Gmac0. - -Signed-off-by: David Wu -Change-Id: I8a69a1239ed3ae91bfe44c96287210da758f9cf9 ---- - .../net/ethernet/stmicro/stmmac/dwmac-rk.c | 179 +++++++++++++++++- - 1 file changed, 173 insertions(+), 6 deletions(-) - ---- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c -+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c -@@ -1142,6 +1142,201 @@ static const struct rk_gmac_ops rk3399_o - .set_rmii_speed = rk3399_set_rmii_speed, - }; - -+#define RK3528_VO_GRF_GMAC_CON 0X60018 -+#define RK3528_VPU_GRF_GMAC_CON5 0X40018 -+#define RK3528_VPU_GRF_GMAC_CON6 0X4001c -+ -+#define RK3528_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) -+#define RK3528_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) -+#define RK3528_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14) -+#define RK3528_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14) -+ -+#define RK3528_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 8) -+#define RK3528_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 0) -+ -+#define RK3528_GMAC0_PHY_INTF_SEL_RMII GRF_BIT(1) -+#define RK3528_GMAC1_PHY_INTF_SEL_RGMII GRF_CLR_BIT(8) -+#define RK3528_GMAC1_PHY_INTF_SEL_RMII GRF_BIT(8) -+ -+#define RK3528_GMAC1_CLK_SELET_CRU GRF_CLR_BIT(12) -+#define RK3528_GMAC1_CLK_SELET_IO GRF_BIT(12) -+ -+#define RK3528_GMAC0_CLK_RMII_DIV2 GRF_BIT(3) -+#define RK3528_GMAC0_CLK_RMII_DIV20 GRF_CLR_BIT(3) -+#define RK3528_GMAC1_CLK_RMII_DIV2 GRF_BIT(10) -+#define RK3528_GMAC1_CLK_RMII_DIV20 GRF_CLR_BIT(10) -+ -+#define RK3528_GMAC1_CLK_RGMII_DIV1 \ -+ (GRF_CLR_BIT(11) | GRF_CLR_BIT(10)) -+#define RK3528_GMAC1_CLK_RGMII_DIV5 \ -+ (GRF_BIT(11) | GRF_BIT(10)) -+#define RK3528_GMAC1_CLK_RGMII_DIV50 \ -+ (GRF_BIT(11) | GRF_CLR_BIT(10)) -+ -+#define RK3528_GMAC0_CLK_RMII_GATE GRF_BIT(2) -+#define RK3528_GMAC0_CLK_RMII_NOGATE GRF_CLR_BIT(2) -+#define RK3528_GMAC1_CLK_RMII_GATE GRF_BIT(9) -+#define RK3528_GMAC1_CLK_RMII_NOGATE GRF_CLR_BIT(9) -+ -+#define RK3528_VO_GRF_MACPHY_CON0 0X6001c -+#define RK3528_VO_GRF_MACPHY_CON1 0X60020 -+ -+static void rk3528_set_to_rgmii(struct rk_priv_data *bsp_priv, -+ int tx_delay, int rx_delay) -+{ -+ struct device *dev = &bsp_priv->pdev->dev; -+ -+ if (IS_ERR(bsp_priv->grf)) { -+ dev_err(dev, "Missing rockchip,grf property\n"); -+ return; -+ } -+ -+ regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, -+ RK3528_GMAC1_PHY_INTF_SEL_RGMII); -+ -+ regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, -+ RK3528_GMAC_CLK_RX_DL_CFG(rx_delay) | -+ RK3528_GMAC_CLK_TX_DL_CFG(tx_delay)); -+ -+ regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON6, -+ RK3528_GMAC_CLK_RX_DL_CFG(rx_delay) | -+ RK3528_GMAC_CLK_TX_DL_CFG(tx_delay)); -+} -+ -+static void rk3528_set_to_rmii(struct rk_priv_data *bsp_priv) -+{ -+ struct device *dev = &bsp_priv->pdev->dev; -+ unsigned int id = bsp_priv->id; -+ -+ if (IS_ERR(bsp_priv->grf)) { -+ dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); -+ return; -+ } -+ -+ if (id == 1) -+ regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, -+ RK3528_GMAC1_PHY_INTF_SEL_RMII); -+ else -+ regmap_write(bsp_priv->grf, RK3528_VO_GRF_GMAC_CON, -+ RK3528_GMAC0_PHY_INTF_SEL_RMII); -+} -+ -+static void rk3528_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) -+{ -+ struct device *dev = &bsp_priv->pdev->dev; -+ unsigned int val = 0; -+ -+ switch (speed) { -+ case 10: -+ val = RK3528_GMAC1_CLK_RGMII_DIV50; -+ break; -+ case 100: -+ val = RK3528_GMAC1_CLK_RGMII_DIV5; -+ break; -+ case 1000: -+ val = RK3528_GMAC1_CLK_RGMII_DIV1; -+ break; -+ default: -+ goto err; -+ } -+ -+ regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, val); -+ return; -+err: -+ dev_err(dev, "unknown RGMII speed value for GMAC speed=%d", speed); -+} -+ -+static void rk3528_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) -+{ -+ struct device *dev = &bsp_priv->pdev->dev; -+ unsigned int val, offset, id = bsp_priv->id; -+ -+ switch (speed) { -+ case 10: -+ val = (id == 1) ? RK3528_GMAC1_CLK_RMII_DIV20 : -+ RK3528_GMAC0_CLK_RMII_DIV20; -+ break; -+ case 100: -+ val = (id == 1) ? RK3528_GMAC1_CLK_RMII_DIV2 : -+ RK3528_GMAC0_CLK_RMII_DIV2; -+ break; -+ default: -+ goto err; -+ } -+ -+ offset = (id == 1) ? RK3528_VPU_GRF_GMAC_CON5 : RK3528_VO_GRF_GMAC_CON; -+ regmap_write(bsp_priv->grf, offset, val); -+ -+ return; -+err: -+ dev_err(dev, "unknown RMII speed value for GMAC speed=%d", speed); -+} -+ -+static void rk3528_set_clock_selection(struct rk_priv_data *bsp_priv, -+ bool input, bool enable) -+{ -+ unsigned int value, id = bsp_priv->id; -+ -+ if (id == 1) { -+ value = input ? RK3528_GMAC1_CLK_SELET_IO : -+ RK3528_GMAC1_CLK_SELET_CRU; -+ value |= enable ? RK3528_GMAC1_CLK_RMII_NOGATE : -+ RK3528_GMAC1_CLK_RMII_GATE; -+ regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, value); -+ } else { -+ value = enable ? RK3528_GMAC0_CLK_RMII_NOGATE : -+ RK3528_GMAC0_CLK_RMII_GATE; -+ regmap_write(bsp_priv->grf, RK3528_VO_GRF_GMAC_CON, value); -+ } -+} -+ -+/* Integrated FEPHY */ -+#define RK_FEPHY_SHUTDOWN GRF_BIT(1) -+#define RK_FEPHY_POWERUP GRF_CLR_BIT(1) -+#define RK_FEPHY_INTERNAL_RMII_SEL GRF_BIT(6) -+#define RK_FEPHY_24M_CLK_SEL (GRF_BIT(8) | GRF_BIT(9)) -+#define RK_FEPHY_PHY_ID GRF_BIT(11) -+ -+#define RK_FEPHY_BGS HIWORD_UPDATE(0x0, 0xf, 0) -+ -+static void rk3528_integrated_sphy_power(struct rk_priv_data *priv) -+{ -+ struct device *dev = &priv->pdev->dev; -+ -+ if (IS_ERR(priv->grf) || !priv->phy_reset) { -+ dev_err(dev, "%s: Missing rockchip,grf or phy_reset property\n", -+ __func__); -+ return; -+ } -+ -+ unsigned int bgs = RK_FEPHY_BGS; -+ -+ reset_control_assert(priv->phy_reset); -+ udelay(20); -+ regmap_write(priv->grf, RK3528_VO_GRF_MACPHY_CON0, -+ RK_FEPHY_POWERUP | -+ RK_FEPHY_INTERNAL_RMII_SEL | -+ RK_FEPHY_24M_CLK_SEL | -+ RK_FEPHY_PHY_ID); -+ -+ /*if (priv->otp_data > 0) -+ bgs = HIWORD_UPDATE(priv->otp_data, 0xf, 0);*/ -+ -+ regmap_write(priv->grf, RK3528_VO_GRF_MACPHY_CON1, bgs); -+ usleep_range(10 * 1000, 12 * 1000); -+ reset_control_deassert(priv->phy_reset); -+ usleep_range(50 * 1000, 60 * 1000); -+} -+ -+static const struct rk_gmac_ops rk3528_ops = { -+ .set_to_rgmii = rk3528_set_to_rgmii, -+ .set_to_rmii = rk3528_set_to_rmii, -+ .set_rgmii_speed = rk3528_set_rgmii_speed, -+ .set_rmii_speed = rk3528_set_rmii_speed, -+ .set_clock_selection = rk3528_set_clock_selection, -+ .integrated_phy_powerup = rk3528_integrated_sphy_power, -+}; -+ - #define RK3568_GRF_GMAC0_CON0 0x0380 - #define RK3568_GRF_GMAC0_CON1 0x0384 - #define RK3568_GRF_GMAC1_CON0 0x0388 -@@ -2261,6 +2456,7 @@ static const struct of_device_id rk_gmac - { .compatible = "rockchip,rk3366-gmac", .data = &rk3366_ops }, - { .compatible = "rockchip,rk3368-gmac", .data = &rk3368_ops }, - { .compatible = "rockchip,rk3399-gmac", .data = &rk3399_ops }, -+ { .compatible = "rockchip,rk3528-gmac", .data = &rk3528_ops }, - { .compatible = "rockchip,rk3568-gmac", .data = &rk3568_ops }, - { .compatible = "rockchip,rk3576-gmac", .data = &rk3576_ops }, - { .compatible = "rockchip,rk3588-gmac", .data = &rk3588_ops }, diff --git a/target/linux/rockchip/patches-6.6/307-phy-rockchip-inno-usb2-add-phy-support-for-rk3528.patch b/target/linux/rockchip/patches-6.6/307-phy-rockchip-inno-usb2-add-phy-support-for-rk3528.patch deleted file mode 100644 index 31eb31f92fda24..00000000000000 --- a/target/linux/rockchip/patches-6.6/307-phy-rockchip-inno-usb2-add-phy-support-for-rk3528.patch +++ /dev/null @@ -1,64 +0,0 @@ ---- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c -@@ -1813,6 +1813,53 @@ static const struct rockchip_usb2phy_cfg - { /* sentinel */ } - }; - -+static const struct rockchip_usb2phy_cfg rk3528_phy_cfgs[] = { -+ { -+ .reg = 0xffdf0000, -+ .num_ports = 2, -+ .clkout_ctl = { 0x041c, 7, 2, 0, 0x27 }, -+ .port_cfgs = { -+ [USB2PHY_PORT_OTG] = { -+ .phy_sus = { 0x6004c, 15, 0, 0, 0x1d1 }, -+ .bvalid_det_en = { 0x60074, 3, 2, 0, 3 }, -+ .bvalid_det_st = { 0x60078, 3, 2, 0, 3 }, -+ .bvalid_det_clr = { 0x6007c, 3, 2, 0, 3 }, -+ .id_det_en = { 0x60074, 5, 4, 0, 3 }, -+ .id_det_st = { 0x60078, 5, 4, 0, 3 }, -+ .id_det_clr = { 0x6007c, 5, 4, 0, 3 }, -+ .ls_det_en = { 0x60074, 0, 0, 0, 1 }, -+ .ls_det_st = { 0x60078, 0, 0, 0, 1 }, -+ .ls_det_clr = { 0x6007c, 0, 0, 0, 1 }, -+ .utmi_avalid = { 0x6006c, 1, 1, 0, 1 }, -+ .utmi_bvalid = { 0x6006c, 0, 0, 0, 1 }, -+ .utmi_id = { 0x6006c, 6, 6, 0, 1 }, -+ .utmi_ls = { 0x6006c, 5, 4, 0, 1 }, -+ }, -+ [USB2PHY_PORT_HOST] = { -+ .phy_sus = { 0x6005c, 15, 0, 0x1d2, 0x1d1 }, -+ .ls_det_en = { 0x60090, 0, 0, 0, 1 }, -+ .ls_det_st = { 0x60094, 0, 0, 0, 1 }, -+ .ls_det_clr = { 0x60098, 0, 0, 0, 1 }, -+ .utmi_ls = { 0x6006c, 13, 12, 0, 1 }, -+ .utmi_hstdet = { 0x6006c, 15, 15, 0, 1 } -+ } -+ }, -+ .chg_det = { -+ .opmode = { 0x6004c, 3, 0, 5, 1 }, -+ .cp_det = { 0x6006c, 19, 19, 0, 1 }, -+ .dcp_det = { 0x6006c, 18, 18, 0, 1 }, -+ .dp_det = { 0x6006c, 20, 20, 0, 1 }, -+ .idm_sink_en = { 0x60058, 1, 1, 0, 1 }, -+ .idp_sink_en = { 0x60058, 0, 0, 0, 1 }, -+ .idp_src_en = { 0x60058, 2, 2, 0, 1 }, -+ .rdm_pdwn_en = { 0x60058, 3, 3, 0, 1 }, -+ .vdm_src_en = { 0x60058, 5, 5, 0, 1 }, -+ .vdp_src_en = { 0x60058, 4, 4, 0, 1 }, -+ }, -+ }, -+ { /* sentinel */ } -+}; -+ - static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = { - { - .reg = 0xfe8a0000, -@@ -2127,6 +2174,7 @@ static const struct of_device_id rockchi - { .compatible = "rockchip,rk3328-usb2phy", .data = &rk3328_phy_cfgs }, - { .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs }, - { .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs }, -+ { .compatible = "rockchip,rk3528-usb2phy", .data = &rk3528_phy_cfgs }, - { .compatible = "rockchip,rk3568-usb2phy", .data = &rk3568_phy_cfgs }, - { .compatible = "rockchip,rk3576-usb2phy", .data = &rk3576_phy_cfgs }, - { .compatible = "rockchip,rk3588-usb2phy", .data = &rk3588_phy_cfgs }, diff --git a/target/linux/rockchip/patches-6.6/308-phy-rockchip-naneng-combphy-add-support-rk3528.patch b/target/linux/rockchip/patches-6.6/308-phy-rockchip-naneng-combphy-add-support-rk3528.patch deleted file mode 100644 index 8aca368f32a997..00000000000000 --- a/target/linux/rockchip/patches-6.6/308-phy-rockchip-naneng-combphy-add-support-rk3528.patch +++ /dev/null @@ -1,170 +0,0 @@ -From 432666b59bdbef2c386e92dd88be4206203ff8ac Mon Sep 17 00:00:00 2001 -From: Jon Lin -Date: Sat, 8 Oct 2022 15:48:37 +0800 -Subject: [PATCH] phy: rockchip: naneng-combphy: add support rk3528 - -1. The layout of controller registers has changed, remove legacy config; -2. Using the default value for grf register; -3. sync to use rk3568 parameter for phy PLL, signal test pass -4. Add 24MHz refclk for rk3528 PCIe, Enable the counting clock of the -rterm detect by setting tx_trim[14] bit for rx detecting. -5. set SSC modulation frequency to 31.5KHz - -Change-Id: I45742c416d452037e61b7a7b8765269931d56402 -Signed-off-by: Jon Lin -Signed-off-by: Jianwei Zheng ---- - .../rockchip/phy-rockchip-naneng-combphy.c | 139 +++++++++++++++++- - 1 file changed, 138 insertions(+), 1 deletion(-) - ---- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c -+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c -@@ -97,7 +97,7 @@ - struct rockchip_combphy_priv; - - struct combphy_reg { -- u16 offset; -+ u32 offset; - u16 bitend; - u16 bitstart; - u16 disable; -@@ -107,6 +107,7 @@ struct combphy_reg { - struct rockchip_combphy_grfcfg { - struct combphy_reg pcie_mode_set; - struct combphy_reg usb_mode_set; -+ struct combphy_reg u3otg0_port_en; - struct combphy_reg sgmii_mode_set; - struct combphy_reg qsgmii_mode_set; - struct combphy_reg pipe_rxterm_set; -@@ -393,6 +394,120 @@ static int rockchip_combphy_probe(struct - return PTR_ERR_OR_ZERO(phy_provider); - } - -+static int rk3528_combphy_cfg(struct rockchip_combphy_priv *priv) -+{ -+ const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; -+ unsigned long rate; -+ u32 val; -+ -+ switch (priv->type) { -+ case PHY_TYPE_PCIE: -+ /* Set SSC downward spread spectrum. */ -+ val = readl(priv->mmio + 0x18); -+ val &= ~GENMASK(5, 4); -+ val |= 0x01 << 4; -+ writel(val, priv->mmio + 0x18); -+ -+ rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true); -+ rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true); -+ rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true); -+ rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true); -+ break; -+ -+ case PHY_TYPE_USB3: -+ /* Set SSC downward spread spectrum. */ -+ val = readl(priv->mmio + 0x18); -+ val &= ~GENMASK(5, 4); -+ val |= 0x01 << 4; -+ writel(val, priv->mmio + 0x18); -+ -+ /* Enable adaptive CTLE for USB3.0 Rx. */ -+ val = readl(priv->mmio + 0x200); -+ val &= ~GENMASK(17, 17); -+ val |= 0x01 << 17; -+ writel(val, priv->mmio + 0x200); -+ -+ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); -+ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); -+ rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true); -+ break; -+ -+ default: -+ dev_err(priv->dev, "incompatible PHY type\n"); -+ return -EINVAL; -+ } -+ -+ rate = clk_get_rate(priv->refclk); -+ -+ switch (rate) { -+ case REF_CLOCK_24MHz: -+ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_24m, true); -+ if (priv->type == PHY_TYPE_USB3) { -+ /* Set ssc_cnt[10:0]=00101111101 & 31.5KHz. */ -+ val = readl(priv->mmio + 0x100); -+ val &= ~GENMASK(10, 0); -+ val |= 0x17d; -+ writel(val, priv->mmio + 0x100); -+ } else if (priv->type == PHY_TYPE_PCIE) { -+ /* tx_trim[14]=1, Enable the counting clock of the rterm detect */ -+ val = readl(priv->mmio + 0x218); -+ val |= (1 << 14); -+ writel(val, priv->mmio + 0x218); -+ } -+ break; -+ -+ case REF_CLOCK_100MHz: -+ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); -+ if (priv->type == PHY_TYPE_PCIE) { -+ /* PLL KVCO tuning fine. */ -+ val = readl(priv->mmio + 0x18); -+ val &= ~(0x7 << 10); -+ val |= 0x2 << 10; -+ writel(val, priv->mmio + 0x18); -+ -+ /* su_trim[6:4]=111, [10:7]=1001, [2:0]=000 */ -+ val = readl(priv->mmio + 0x108); -+ val &= ~(0x7f7); -+ val |= 0x4f0; -+ writel(val, priv->mmio + 0x108); -+ } -+ break; -+ -+ default: -+ dev_err(priv->dev, "unsupported rate: %lu\n", rate); -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ -+static const struct rockchip_combphy_grfcfg rk3528_combphy_grfcfgs = { -+ /* pipe-phy-grf */ -+ .pcie_mode_set = { 0x48000, 5, 0, 0x00, 0x11 }, -+ .usb_mode_set = { 0x48000, 5, 0, 0x00, 0x04 }, -+ .pipe_rxterm_set = { 0x48000, 12, 12, 0x00, 0x01 }, -+ .pipe_txelec_set = { 0x48004, 1, 1, 0x00, 0x01 }, -+ .pipe_txcomp_set = { 0x48004, 4, 4, 0x00, 0x01 }, -+ .pipe_clk_24m = { 0x48004, 14, 13, 0x00, 0x00 }, -+ .pipe_clk_100m = { 0x48004, 14, 13, 0x00, 0x02 }, -+ .pipe_rxterm_sel = { 0x48008, 8, 8, 0x00, 0x01 }, -+ .pipe_txelec_sel = { 0x48008, 12, 12, 0x00, 0x01 }, -+ .pipe_txcomp_sel = { 0x48008, 15, 15, 0x00, 0x01 }, -+ .pipe_clk_ext = { 0x4800c, 9, 8, 0x02, 0x01 }, -+ .pipe_phy_status = { 0x48034, 6, 6, 0x01, 0x00 }, -+ .con0_for_pcie = { 0x48000, 15, 0, 0x00, 0x110 }, -+ .con1_for_pcie = { 0x48004, 15, 0, 0x00, 0x00 }, -+ .con2_for_pcie = { 0x48008, 15, 0, 0x00, 0x101 }, -+ .con3_for_pcie = { 0x4800c, 15, 0, 0x00, 0x0200 }, -+ /* pipe-grf */ -+ .u3otg0_port_en = { 0x40044, 15, 0, 0x0181, 0x1100 }, -+}; -+ -+static const struct rockchip_combphy_cfg rk3528_combphy_cfgs = { -+ .grfcfg = &rk3528_combphy_grfcfgs, -+ .combphy_cfg = rk3528_combphy_cfg, -+}; -+ - static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv) - { - const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; -@@ -1047,6 +1162,10 @@ static const struct rockchip_combphy_cfg - - static const struct of_device_id rockchip_combphy_of_match[] = { - { -+ .compatible = "rockchip,rk3528-naneng-combphy", -+ .data = &rk3528_combphy_cfgs, -+ }, -+ { - .compatible = "rockchip,rk3568-naneng-combphy", - .data = &rk3568_combphy_cfgs, - }, diff --git a/target/linux/rockchip/patches-6.6/309-mmc-sdhci-of-dwcmshc-pcie-support-for-rk3528.patch b/target/linux/rockchip/patches-6.6/309-mmc-sdhci-of-dwcmshc-pcie-support-for-rk3528.patch deleted file mode 100644 index 2f636b814a1a66..00000000000000 --- a/target/linux/rockchip/patches-6.6/309-mmc-sdhci-of-dwcmshc-pcie-support-for-rk3528.patch +++ /dev/null @@ -1,107 +0,0 @@ ---- a/drivers/mmc/host/sdhci-of-dwcmshc.c -+++ b/drivers/mmc/host/sdhci-of-dwcmshc.c -@@ -296,19 +296,20 @@ static void dwcmshc_rk3568_set_clock(str - 0x3 << 19; /* post-change delay */ - sdhci_writel(host, extra, dwc_priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL); - -- if (host->mmc->ios.timing == MMC_TIMING_MMC_HS200 || -- host->mmc->ios.timing == MMC_TIMING_MMC_HS400) -+ if (host->mmc->ios.timing == MMC_TIMING_MMC_HS200) - txclk_tapnum = priv->txclk_tapnum; - -- if ((priv->devtype == DWCMSHC_RK3588) && host->mmc->ios.timing == MMC_TIMING_MMC_HS400) { -+ if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400) { - txclk_tapnum = DLL_TXCLK_TAPNUM_90_DEGREES; - -- extra = DLL_CMDOUT_SRC_CLK_NEG | -- DLL_CMDOUT_EN_SRC_CLK_NEG | -- DWCMSHC_EMMC_DLL_DLYENA | -- DLL_CMDOUT_TAPNUM_90_DEGREES | -- DLL_CMDOUT_TAPNUM_FROM_SW; -- sdhci_writel(host, extra, DECMSHC_EMMC_DLL_CMDOUT); -+ if (priv->devtype != DWCMSHC_RK3568) { -+ extra = DLL_CMDOUT_SRC_CLK_NEG | -+ DLL_CMDOUT_EN_SRC_CLK_NEG | -+ DWCMSHC_EMMC_DLL_DLYENA | -+ DLL_CMDOUT_TAPNUM_90_DEGREES | -+ DLL_CMDOUT_TAPNUM_FROM_SW; -+ sdhci_writel(host, extra, DECMSHC_EMMC_DLL_CMDOUT); -+ } - } - - extra = DWCMSHC_EMMC_DLL_DLYENA | -@@ -356,6 +357,15 @@ static const struct sdhci_ops sdhci_dwcm - .adma_write_desc = dwcmshc_adma_write_desc, - }; - -+static const struct sdhci_ops sdhci_dwcmshc_rk3528_ops = { -+ .set_clock = dwcmshc_rk3568_set_clock, -+ .set_bus_width = sdhci_set_bus_width, -+ .set_uhs_signaling = dwcmshc_set_uhs_signaling, -+ .get_max_clock = sdhci_pltfm_clk_get_max_clock, -+ .reset = rk35xx_sdhci_reset, -+ .adma_write_desc = dwcmshc_adma_write_desc, -+}; -+ - static const struct sdhci_pltfm_data sdhci_dwcmshc_pdata = { - .ops = &sdhci_dwcmshc_ops, - .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, -@@ -379,6 +389,14 @@ static const struct sdhci_pltfm_data sdh - SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN, - }; - -+static const struct sdhci_pltfm_data sdhci_dwcmshc_rk3528_pdata = { -+ .ops = &sdhci_dwcmshc_rk3528_ops, -+ .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | -+ SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, -+ .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | -+ SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN, -+}; -+ - static int dwcmshc_rk35xx_init(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv) - { - int err; -@@ -444,6 +462,10 @@ static const struct of_device_id sdhci_d - .data = &sdhci_dwcmshc_rk35xx_pdata, - }, - { -+ .compatible = "rockchip,rk3528-dwcmshc", -+ .data = &sdhci_dwcmshc_rk3528_pdata, -+ }, -+ { - .compatible = "snps,dwcmshc-sdhci", - .data = &sdhci_dwcmshc_pdata, - }, -@@ -523,17 +545,18 @@ static int dwcmshc_probe(struct platform - host->mmc_host_ops.request = dwcmshc_request; - host->mmc_host_ops.hs400_enhanced_strobe = dwcmshc_hs400_enhanced_strobe; - -- if (pltfm_data == &sdhci_dwcmshc_rk35xx_pdata) { -+ if ((pltfm_data == &sdhci_dwcmshc_rk35xx_pdata) || -+ (pltfm_data == &sdhci_dwcmshc_rk3528_pdata)) { - rk_priv = devm_kzalloc(&pdev->dev, sizeof(struct rk35xx_priv), GFP_KERNEL); - if (!rk_priv) { - err = -ENOMEM; - goto err_clk; - } - -- if (of_device_is_compatible(pdev->dev.of_node, "rockchip,rk3588-dwcmshc")) -- rk_priv->devtype = DWCMSHC_RK3588; -- else -+ if (of_device_is_compatible(pdev->dev.of_node, "rockchip,rk3568-dwcmshc")) - rk_priv->devtype = DWCMSHC_RK3568; -+ else -+ rk_priv->devtype = DWCMSHC_RK3588; - - priv->priv = rk_priv; - ---- a/drivers/pci/controller/dwc/Makefile -+++ b/drivers/pci/controller/dwc/Makefile -@@ -17,6 +17,7 @@ obj-$(CONFIG_PCIE_QCOM_EP) += pcie-qcom- - obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o - obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o - obj-$(CONFIG_PCIE_ROCKCHIP_DW_HOST) += pcie-dw-rockchip.o -+obj-$(CONFIG_PCIE_ROCKCHIP_DW_HOST) += pcie-dw-rkvendor.o - obj-$(CONFIG_PCIE_INTEL_GW) += pcie-intel-gw.o - obj-$(CONFIG_PCIE_KEEMBAY) += pcie-keembay.o - obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o