diff --git a/include/image.mk b/include/image.mk index b6b796dd972c1d..284298e5ed69a2 100644 --- a/include/image.mk +++ b/include/image.mk @@ -279,12 +279,11 @@ endef define Image/Manifest $(call opkg,$(TARGET_DIR_ORIG)) list-installed > \ $(BIN_DIR)/$(IMG_PREFIX)$(if $(PROFILE_SANITIZED),-$(PROFILE_SANITIZED)).manifest -ifndef IB - $(if $(CONFIG_JSON_CYCLONEDX_SBOM), \ - $(SCRIPT_DIR)/package-metadata.pl imgcyclonedxsbom \ - $(TMP_DIR)/.packageinfo \ +ifneq ($(CONFIG_JSON_CYCLONEDX_SBOM),) + $(SCRIPT_DIR)/package-metadata.pl imgcyclonedxsbom \ + $(if $(IB),$(TOPDIR)/.packageinfo, $(TMP_DIR)/.packageinfo) \ $(BIN_DIR)/$(IMG_PREFIX)$(if $(PROFILE_SANITIZED),-$(PROFILE_SANITIZED)).manifest > \ - $(BIN_DIR)/$(IMG_PREFIX)$(if $(PROFILE_SANITIZED),-$(PROFILE_SANITIZED)).bom.cdx.json) + $(BIN_DIR)/$(IMG_PREFIX)$(if $(PROFILE_SANITIZED),-$(PROFILE_SANITIZED)).bom.cdx.json endif endef diff --git a/include/package-dumpinfo.mk b/include/package-dumpinfo.mk index fc25099ad30e92..e180c770e3df27 100644 --- a/include/package-dumpinfo.mk +++ b/include/package-dumpinfo.mk @@ -44,7 +44,6 @@ $(if $(KCONFIG),Kernel-Config: $(KCONFIG) )$(if $(BUILDONLY),Build-Only: $(BUILDONLY) )$(if $(HIDDEN),Hidden: $(HIDDEN) )Description: $(if $(Package/$(1)/description),$(Package/$(1)/description),$(TITLE)) -$(MAINTAINER) @@ $(if $(Package/$(1)/config),Config: $(Package/$(1)/config) diff --git a/include/trusted-firmware-a.mk b/include/trusted-firmware-a.mk index 0c0118e092bec5..e469dae9840087 100644 --- a/include/trusted-firmware-a.mk +++ b/include/trusted-firmware-a.mk @@ -63,9 +63,11 @@ define Build/Trusted-Firmware-A/Target URL:=https://www.trustedfirmware.org/projects/tf-a/ endef - define Package/trusted-firmware-a-$(1)/install + ifndef Package/trusted-firmware-a-$(1)/install + define Package/trusted-firmware-a-$(1)/install $$(Package/trusted-firmware-a/install) - endef + endef + endif endef define Build/Configure/Trusted-Firmware-A diff --git a/package/boot/arm-trusted-firmware-mediatek/Makefile b/package/boot/arm-trusted-firmware-mediatek/Makefile index c065c7e67d3019..37d71e183c3390 100644 --- a/package/boot/arm-trusted-firmware-mediatek/Makefile +++ b/package/boot/arm-trusted-firmware-mediatek/Makefile @@ -33,6 +33,7 @@ define Trusted-Firmware-A/Default NAND_TYPE:= BOARD_QFN:= DRAM_USE_COMB:= + RAM_BOOT_UART_DL:= USE_UBI:= endef @@ -113,6 +114,17 @@ define Trusted-Firmware-A/mt7622-sdmmc-2ddr DDR3_FLYBY:=1 endef +define Trusted-Firmware-A/mt7981-ram-ddr4 + NAME:=MediaTek MT7981 (RAM, DDR4) + BOOT_DEVICE:=ram + BUILD_SUBTARGET:=filogic + PLAT:=mt7981 + DDR_TYPE:=ddr4 + RAM_BOOT_UART_DL:=1 + HIDDEN:= + DEFAULT:=TARGET_mediatek_filogic +endef + define Trusted-Firmware-A/mt7981-emmc-ddr4 NAME:=MediaTek MT7981 (eMMC, DDR4) BOOT_DEVICE:=emmc @@ -137,6 +149,17 @@ define Trusted-Firmware-A/mt7981-nor-ddr3 DDR_TYPE:=ddr3 endef +define Trusted-Firmware-A/mt7981-ram-ddr3 + NAME:=MediaTek MT7981 (RAM, DDR3) + BOOT_DEVICE:=ram + BUILD_SUBTARGET:=filogic + PLAT:=mt7981 + DDR_TYPE:=ddr3 + RAM_BOOT_UART_DL:=1 + HIDDEN:= + DEFAULT:=TARGET_mediatek_filogic +endef + define Trusted-Firmware-A/mt7981-emmc-ddr3 NAME:=MediaTek MT7981 (eMMC, DDR3) BOOT_DEVICE:=emmc @@ -169,6 +192,17 @@ define Trusted-Firmware-A/mt7981-spim-nand-ddr3 DDR_TYPE:=ddr3 endef +define Trusted-Firmware-A/mt7986-ram-ddr4 + NAME:=MediaTek MT7986 (RAM, DDR4) + BOOT_DEVICE:=ram + BUILD_SUBTARGET:=filogic + PLAT:=mt7986 + DDR_TYPE:=ddr4 + RAM_BOOT_UART_DL:=1 + HIDDEN:= + DEFAULT:=TARGET_mediatek_filogic +endef + define Trusted-Firmware-A/mt7986-nor-ddr4 NAME:=MediaTek MT7986 (SPI-NOR, DDR4) BOOT_DEVICE:=nor @@ -229,6 +263,17 @@ define Trusted-Firmware-A/mt7986-spim-nand-4k-ddr4 NAND_TYPE:=spim:4k+256 endef +define Trusted-Firmware-A/mt7986-ram-ddr3 + NAME:=MediaTek MT7986 (RAM, DDR3) + BOOT_DEVICE:=ram + BUILD_SUBTARGET:=filogic + PLAT:=mt7986 + DDR_TYPE:=ddr3 + RAM_BOOT_UART_DL:=1 + HIDDEN:= + DEFAULT:=TARGET_mediatek_filogic +endef + define Trusted-Firmware-A/mt7986-nor-ddr3 NAME:=MediaTek MT7986 (SPI-NOR, DDR3) BOOT_DEVICE:=nor @@ -349,6 +394,17 @@ define Trusted-Firmware-A/mt7988-spim-nand-ddr4 DDR_TYPE:=ddr4 endef +define Trusted-Firmware-A/mt7988-ram-comb + NAME:=MediaTek MT7988 (RAM) + BOOT_DEVICE:=ram + BUILD_SUBTARGET:=filogic + PLAT:=mt7988 + DRAM_USE_COMB:=1 + RAM_BOOT_UART_DL:=1 + HIDDEN:= + DEFAULT:=TARGET_mediatek_filogic +endef + define Trusted-Firmware-A/mt7988-nor-comb NAME:=MediaTek MT7988 (SPI-NOR) BOOT_DEVICE:=nor @@ -418,18 +474,22 @@ TFA_TARGETS:= \ mt7622-emmc-2ddr \ mt7622-sdmmc-1ddr \ mt7622-sdmmc-2ddr \ + mt7981-ram-ddr3 \ mt7981-emmc-ddr3 \ mt7981-nor-ddr3 \ mt7981-sdmmc-ddr3 \ mt7981-snand-ddr3 \ mt7981-spim-nand-ddr3 \ + mt7981-ram-ddr4 \ mt7981-emmc-ddr4 \ mt7981-spim-nand-ddr4 \ + mt7986-ram-ddr3 \ mt7986-emmc-ddr3 \ mt7986-nor-ddr3 \ mt7986-sdmmc-ddr3 \ mt7986-snand-ddr3 \ mt7986-spim-nand-ddr3 \ + mt7986-ram-ddr4 \ mt7986-emmc-ddr4 \ mt7986-nor-ddr4 \ mt7986-sdmmc-ddr4 \ @@ -447,6 +507,7 @@ TFA_TARGETS:= \ mt7988-sdmmc-ddr4 \ mt7988-snand-ddr4 \ mt7988-spim-nand-ddr4 \ + mt7988-ram-comb \ mt7988-emmc-comb \ mt7988-nor-comb \ mt7988-sdmmc-comb \ @@ -464,9 +525,20 @@ TFA_MAKE_FLAGS += \ HAVE_DRAM_OBJ_FILE=yes \ $(if $(DDR3_FLYBY),DDR3_FLYBY=1) \ $(if $(DRAM_USE_COMB),DRAM_USE_COMB=1) \ + $(if $(RAM_BOOT_UART_DL),RAM_BOOT_UART_DL=1) \ $(if $(USE_UBI),UBI=1 $(if $(findstring mt7622,$(PLAT)),OVERRIDE_UBI_START_ADDR=0x80000)) \ all +define Package/trusted-firmware-a-ram/install + $(INSTALL_DIR) $(STAGING_DIR_IMAGE) + $(INSTALL_DATA) $(PKG_BUILD_DIR)/build/$(PLAT)/release/bl2.bin $(BIN_DIR)/$(BUILD_VARIANT)-bl2.bin +endef +Package/trusted-firmware-a-mt7981-ram-ddr3/install = $(Package/trusted-firmware-a-ram/install) +Package/trusted-firmware-a-mt7981-ram-ddr4/install = $(Package/trusted-firmware-a-ram/install) +Package/trusted-firmware-a-mt7986-ram-ddr3/install = $(Package/trusted-firmware-a-ram/install) +Package/trusted-firmware-a-mt7986-ram-ddr4/install = $(Package/trusted-firmware-a-ram/install) +Package/trusted-firmware-a-mt7988-ram-comb/install = $(Package/trusted-firmware-a-ram/install) + define Package/trusted-firmware-a/install $(INSTALL_DIR) $(STAGING_DIR_IMAGE) $(INSTALL_DATA) $(PKG_BUILD_DIR)/build/$(PLAT)/release/bl2.img $(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-bl2.img diff --git a/package/boot/uboot-envtools/files/mediatek_filogic b/package/boot/uboot-envtools/files/mediatek_filogic index 7d46e73dbe166a..c439af12c88b81 100644 --- a/package/boot/uboot-envtools/files/mediatek_filogic +++ b/package/boot/uboot-envtools/files/mediatek_filogic @@ -39,6 +39,7 @@ asus,rt-ax59u) bananapi,bpi-r3|\ bananapi,bpi-r3-mini|\ bananapi,bpi-r4|\ +bananapi,bpi-r4-poe|\ jdcloud,re-cp-03) . /lib/upgrade/common.sh diff --git a/package/boot/uboot-envtools/files/mediatek_mt7622 b/package/boot/uboot-envtools/files/mediatek_mt7622 index c8d385748449f3..6698e06ee352c0 100644 --- a/package/boot/uboot-envtools/files/mediatek_mt7622 +++ b/package/boot/uboot-envtools/files/mediatek_mt7622 @@ -57,6 +57,9 @@ ubnt,unifi-6-lr-v2-ubootmod|\ ubnt,unifi-6-lr-v3-ubootmod) ubootenv_add_uci_config "/dev/mtd$(find_mtd_index "u-boot-env")" "0x0" "0x4000" "0x1000" ;; +ubnt,unifi-6-lr-v2) + ubootenv_add_uci_config "/dev/mtd3" "0x0" "0x1000" "0x1000" "1" + ;; xiaomi,redmi-router-ax6s) ubootenv_add_uci_config "/dev/mtd3" "0x0" "0x10000" "0x40000" ;; diff --git a/package/boot/uboot-mediatek/Makefile b/package/boot/uboot-mediatek/Makefile index c8213f7a538ae2..470b4db4fa7f00 100644 --- a/package/boot/uboot-mediatek/Makefile +++ b/package/boot/uboot-mediatek/Makefile @@ -580,6 +580,42 @@ define U-Boot/mt7988_bananapi_bpi-r4-snand DEPENDS:=+trusted-firmware-a-mt7988-spim-nand-ubi-comb endef +define U-Boot/mt7988_bananapi_bpi-r4-poe-emmc + NAME:=BananaPi BPi-R4 2.5GE + BUILD_SUBTARGET:=filogic + BUILD_DEVICES:=bananapi_bpi-r4-poe + UBOOT_CONFIG:=mt7988a_bananapi_bpi-r4-poe-emmc + UBOOT_IMAGE:=u-boot.fip + BL2_BOOTDEV:=emmc + BL2_SOC:=mt7988 + BL2_DDRTYPE:=comb + DEPENDS:=+trusted-firmware-a-mt7988-emmc-comb +endef + +define U-Boot/mt7988_bananapi_bpi-r4-poe-sdmmc + NAME:=BananaPi BPi-R4 2.5GE + BUILD_SUBTARGET:=filogic + BUILD_DEVICES:=bananapi_bpi-r4-poe + UBOOT_CONFIG:=mt7988a_bananapi_bpi-r4-poe-sdmmc + UBOOT_IMAGE:=u-boot.fip + BL2_BOOTDEV:=sdmmc + BL2_SOC:=mt7988 + BL2_DDRTYPE:=comb + DEPENDS:=+trusted-firmware-a-mt7988-sdmmc-comb +endef + +define U-Boot/mt7988_bananapi_bpi-r4-poe-snand + NAME:=BananaPi BPi-R4 2.5GE + BUILD_SUBTARGET:=filogic + BUILD_DEVICES:=bananapi_bpi-r4-poe + UBOOT_CONFIG:=mt7988a_bananapi_bpi-r4-poe-snand + UBOOT_IMAGE:=u-boot.fip + BL2_BOOTDEV:=spim-nand-ubi + BL2_SOC:=mt7988 + BL2_DDRTYPE:=comb + DEPENDS:=+trusted-firmware-a-mt7988-spim-nand-ubi-comb +endef + define U-Boot/mt7988_rfb-spim-nand NAME:=MT7988 Reference Board BUILD_SUBTARGET:=filogic @@ -691,6 +727,9 @@ UBOOT_TARGETS := \ mt7988_bananapi_bpi-r4-emmc \ mt7988_bananapi_bpi-r4-sdmmc \ mt7988_bananapi_bpi-r4-snand \ + mt7988_bananapi_bpi-r4-poe-emmc \ + mt7988_bananapi_bpi-r4-poe-sdmmc \ + mt7988_bananapi_bpi-r4-poe-snand \ mt7988_rfb-spim-nand \ mt7988_rfb-snand \ mt7988_rfb-nor \ diff --git a/package/boot/uboot-mediatek/patches/401-update-u7623-defconfig.patch b/package/boot/uboot-mediatek/patches/401-update-u7623-defconfig.patch index 6528b165f522d8..58c62dc3efd3ad 100644 --- a/package/boot/uboot-mediatek/patches/401-update-u7623-defconfig.patch +++ b/package/boot/uboot-mediatek/patches/401-update-u7623-defconfig.patch @@ -186,7 +186,7 @@ +reset_factory=eraseenv && reset +_init_env=setenv _init_env ; saveenv ; saveenv +_firstboot=setenv _firstboot ; run _switch_to_menu _update_bootdev _init_env boot_first -+_update_bootdev=setenv _update_bootdev ; setenv bootargs "$console root=/dev/mmcblk0p65" ++_update_bootdev=setenv _update_bootdev ; setenv bootargs "$console root=/dev/fit0 rootwait" +_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title +_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title $ver" --- a/arch/arm/dts/mt7623a-unielec-u7623-02-emmc.dts diff --git a/package/boot/uboot-mediatek/patches/450-add-bpi-r4.patch b/package/boot/uboot-mediatek/patches/450-add-bpi-r4.patch index 5fb956a2e3a3d4..0a69e74e02d0f4 100644 --- a/package/boot/uboot-mediatek/patches/450-add-bpi-r4.patch +++ b/package/boot/uboot-mediatek/patches/450-add-bpi-r4.patch @@ -996,3 +996,753 @@ + non-removable; + status = "okay"; +}; +--- /dev/null ++++ b/configs/mt7988a_bananapi_bpi-r4-poe-emmc_defconfig +@@ -0,0 +1,180 @@ ++CONFIG_ARM=y ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y ++CONFIG_POSITION_INDEPENDENT=y ++CONFIG_ARCH_MEDIATEK=y ++CONFIG_TEXT_BASE=0x41e00000 ++CONFIG_SYS_MALLOC_F_LEN=0x4000 ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_SYS_PROMPT="MT7988> " ++CONFIG_TARGET_MT7988=y ++CONFIG_DEBUG_UART_BASE=0x11000000 ++CONFIG_DEBUG_UART_CLOCK=40000000 ++CONFIG_SYS_LOAD_ADDR=0x50000000 ++CONFIG_DEBUG_UART=y ++CONFIG_SYS_CBSIZE=512 ++CONFIG_SYS_PBSIZE=1049 ++CONFIG_DEFAULT_DEVICE_TREE="mt7988a-bananapi-bpi-r4-emmc" ++CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r4-poe_emmc_env" ++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7988a-bpi-r4-emmc.dtb" ++CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_OF_SYSTEM_SETUP=y ++CONFIG_SMBIOS_PRODUCT_NAME="" ++CONFIG_AUTOBOOT_KEYED=y ++CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_MENU_SHOW=y ++CONFIG_CFB_CONSOLE_ANSI=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_GPIO_HOG=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_FIT=y ++CONFIG_FIT_ENABLE_SHA256_SUPPORT=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y ++CONFIG_LOGLEVEL=7 ++CONFIG_LOG=y ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_BOOTP=y ++CONFIG_CMD_BUTTON=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_CPU=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DM=y ++CONFIG_CMD_DNS=y ++CONFIG_CMD_ECHO=y ++CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_ERASEENV=y ++CONFIG_CMD_EXT4=y ++CONFIG_CMD_FAT=y ++CONFIG_CMD_FDT=y ++CONFIG_CMD_FS_GENERIC=y ++CONFIG_CMD_FS_UUID=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_HASH=y ++CONFIG_CMD_ITEST=y ++CONFIG_CMD_LED=y ++CONFIG_CMD_LICENSE=y ++CONFIG_CMD_LINK_LOCAL=y ++# CONFIG_CMD_MBR is not set ++CONFIG_CMD_MMC=y ++CONFIG_CMD_MTD=y ++CONFIG_CMD_PCI=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_PING=y ++CONFIG_CMD_PXE=y ++CONFIG_CMD_PWM=y ++CONFIG_CMD_SMC=y ++CONFIG_CMD_TFTPBOOT=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_UBI=y ++CONFIG_CMD_UBI_RENAME=y ++CONFIG_CMD_UBIFS=y ++CONFIG_CMD_ASKENV=y ++CONFIG_CMD_PART=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_SETEXPR=y ++CONFIG_CMD_SLEEP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_SOURCE=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_UUID=y ++CONFIG_DISPLAY_CPUINFO=y ++CONFIG_DM_MMC=y ++CONFIG_DM_MTD=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_DM_USB=y ++CONFIG_DM_PWM=y ++CONFIG_PWM_MTK=y ++CONFIG_HUSH_PARSER=y ++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_VERSION_VARIABLE=y ++CONFIG_PARTITION_UUIDS=y ++CONFIG_NETCONSOLE=y ++CONFIG_DM_GPIO=y ++CONFIG_DM_SCSI=y ++CONFIG_AHCI=y ++CONFIG_AHCI_PCI=y ++CONFIG_SCSI_AHCI=y ++CONFIG_SCSI=y ++CONFIG_CMD_SCSI=y ++CONFIG_PHY=y ++CONFIG_PHY_MTK_TPHY=y ++CONFIG_MTK_AHCI=y ++CONFIG_PCI=y ++CONFIG_MTD=y ++CONFIG_MTD_UBI_FASTMAP=y ++CONFIG_DM_PCI=y ++CONFIG_PCIE_MEDIATEK=y ++CONFIG_PRE_CONSOLE_BUFFER=y ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 ++CONFIG_RAM=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_MMC=y ++CONFIG_MMC_DEFAULT_DEV=1 ++CONFIG_MMC_SUPPORTS_TUNING=y ++CONFIG_SPI=y ++CONFIG_DM_SPI=y ++CONFIG_MTK_SPI_NAND=y ++CONFIG_MTK_SPI_NAND_MTD=y ++CONFIG_SYSRESET_WATCHDOG=y ++CONFIG_WDT_MTK=y ++CONFIG_LZO=y ++CONFIG_ZSTD=y ++CONFIG_HEXDUMP=y ++CONFIG_RANDOM_UUID=y ++CONFIG_REGEX=y ++CONFIG_USB=y ++CONFIG_USB_HOST=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_MTK=y ++CONFIG_USB_STORAGE=y ++CONFIG_OF_EMBED=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_IS_IN_MMC=y ++CONFIG_ENV_OFFSET=0x400000 ++CONFIG_ENV_OFFSET_REDUND=0x440000 ++CONFIG_ENV_SIZE=0x40000 ++CONFIG_ENV_SIZE_REDUND=0x40000 ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_CLK=y ++CONFIG_SUPPORT_EMMC_BOOT=y ++CONFIG_MMC_HS200_SUPPORT=y ++CONFIG_MMC_MTK=y ++CONFIG_PHY_FIXED=y ++CONFIG_DM_ETH=y ++CONFIG_MEDIATEK_ETH=y ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7988=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_MTD_SPI_NAND=y ++CONFIG_MTK_SPIM=y ++#CONFIG_MTK_SNOR=y ++CONFIG_DM_SPI_FLASH=y ++CONFIG_SPI_FLASH_MTD=y ++CONFIG_SPI_FLASH_WINBOND=y ++# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set ++CONFIG_CMD_SF=y ++CONFIG_CMD_NAND=y ++CONFIG_CMD_NAND_TRIMFFS=y ++CONFIG_LMB_MAX_REGIONS=64 ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" +--- /dev/null ++++ b/configs/mt7988a_bananapi_bpi-r4-poe-sdmmc_defconfig +@@ -0,0 +1,180 @@ ++CONFIG_ARM=y ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y ++CONFIG_POSITION_INDEPENDENT=y ++CONFIG_ARCH_MEDIATEK=y ++CONFIG_TEXT_BASE=0x41e00000 ++CONFIG_SYS_MALLOC_F_LEN=0x4000 ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_SYS_PROMPT="MT7988> " ++CONFIG_TARGET_MT7988=y ++CONFIG_DEBUG_UART_BASE=0x11000000 ++CONFIG_DEBUG_UART_CLOCK=40000000 ++CONFIG_SYS_LOAD_ADDR=0x50000000 ++CONFIG_DEBUG_UART=y ++CONFIG_SYS_CBSIZE=512 ++CONFIG_SYS_PBSIZE=1049 ++CONFIG_DEFAULT_DEVICE_TREE="mt7988a-bananapi-bpi-r4-sd" ++CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r4-poe_sdmmc_env" ++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7988a-bpi-r4-sd.dtb" ++CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_OF_SYSTEM_SETUP=y ++CONFIG_SMBIOS_PRODUCT_NAME="" ++CONFIG_AUTOBOOT_KEYED=y ++CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_MENU_SHOW=y ++CONFIG_CFB_CONSOLE_ANSI=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_GPIO_HOG=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_FIT=y ++CONFIG_FIT_ENABLE_SHA256_SUPPORT=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y ++CONFIG_LOGLEVEL=7 ++CONFIG_LOG=y ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_BOOTP=y ++CONFIG_CMD_BUTTON=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_CPU=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DM=y ++CONFIG_CMD_DNS=y ++CONFIG_CMD_ECHO=y ++CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_ERASEENV=y ++CONFIG_CMD_EXT4=y ++CONFIG_CMD_FAT=y ++CONFIG_CMD_FDT=y ++CONFIG_CMD_FS_GENERIC=y ++CONFIG_CMD_FS_UUID=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_HASH=y ++CONFIG_CMD_ITEST=y ++CONFIG_CMD_LED=y ++CONFIG_CMD_LICENSE=y ++CONFIG_CMD_LINK_LOCAL=y ++# CONFIG_CMD_MBR is not set ++CONFIG_CMD_MMC=y ++CONFIG_CMD_MTD=y ++CONFIG_CMD_PCI=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_PING=y ++CONFIG_CMD_PXE=y ++CONFIG_CMD_PWM=y ++CONFIG_CMD_SMC=y ++CONFIG_CMD_TFTPBOOT=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_UBI=y ++CONFIG_CMD_UBI_RENAME=y ++CONFIG_CMD_UBIFS=y ++CONFIG_CMD_ASKENV=y ++CONFIG_CMD_PART=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_SETEXPR=y ++CONFIG_CMD_SLEEP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_SOURCE=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_UUID=y ++CONFIG_DISPLAY_CPUINFO=y ++CONFIG_DM_MMC=y ++CONFIG_DM_MTD=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_DM_USB=y ++CONFIG_DM_PWM=y ++CONFIG_PWM_MTK=y ++CONFIG_HUSH_PARSER=y ++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_VERSION_VARIABLE=y ++CONFIG_PARTITION_UUIDS=y ++CONFIG_NETCONSOLE=y ++CONFIG_DM_GPIO=y ++CONFIG_DM_SCSI=y ++CONFIG_AHCI=y ++CONFIG_AHCI_PCI=y ++CONFIG_SCSI_AHCI=y ++CONFIG_SCSI=y ++CONFIG_CMD_SCSI=y ++CONFIG_PHY=y ++CONFIG_PHY_MTK_TPHY=y ++CONFIG_MTK_AHCI=y ++CONFIG_PCI=y ++CONFIG_MTD=y ++CONFIG_MTD_UBI_FASTMAP=y ++CONFIG_DM_PCI=y ++CONFIG_PCIE_MEDIATEK=y ++CONFIG_PRE_CONSOLE_BUFFER=y ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 ++CONFIG_RAM=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_MMC=y ++CONFIG_MMC_DEFAULT_DEV=1 ++CONFIG_MMC_SUPPORTS_TUNING=y ++CONFIG_SPI=y ++CONFIG_DM_SPI=y ++CONFIG_MTK_SPI_NAND=y ++CONFIG_MTK_SPI_NAND_MTD=y ++CONFIG_SYSRESET_WATCHDOG=y ++CONFIG_WDT_MTK=y ++CONFIG_LZO=y ++CONFIG_ZSTD=y ++CONFIG_HEXDUMP=y ++CONFIG_RANDOM_UUID=y ++CONFIG_REGEX=y ++CONFIG_USB=y ++CONFIG_USB_HOST=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_MTK=y ++CONFIG_USB_STORAGE=y ++CONFIG_OF_EMBED=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_IS_IN_MMC=y ++CONFIG_ENV_OFFSET=0x400000 ++CONFIG_ENV_OFFSET_REDUND=0x440000 ++CONFIG_ENV_SIZE=0x40000 ++CONFIG_ENV_SIZE_REDUND=0x40000 ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_CLK=y ++CONFIG_SUPPORT_EMMC_BOOT=y ++CONFIG_MMC_HS200_SUPPORT=y ++CONFIG_MMC_MTK=y ++CONFIG_PHY_FIXED=y ++CONFIG_DM_ETH=y ++CONFIG_MEDIATEK_ETH=y ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7988=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_MTD_SPI_NAND=y ++CONFIG_MTK_SPIM=y ++#CONFIG_MTK_SNOR=y ++CONFIG_DM_SPI_FLASH=y ++CONFIG_SPI_FLASH_MTD=y ++CONFIG_SPI_FLASH_WINBOND=y ++# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set ++CONFIG_CMD_SF=y ++CONFIG_CMD_NAND=y ++CONFIG_CMD_NAND_TRIMFFS=y ++CONFIG_LMB_MAX_REGIONS=64 ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" +--- /dev/null ++++ b/configs/mt7988a_bananapi_bpi-r4-poe-snand_defconfig +@@ -0,0 +1,182 @@ ++CONFIG_ARM=y ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y ++CONFIG_POSITION_INDEPENDENT=y ++CONFIG_ARCH_MEDIATEK=y ++CONFIG_TEXT_BASE=0x41e00000 ++CONFIG_SYS_MALLOC_F_LEN=0x4000 ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_SYS_PROMPT="MT7988> " ++CONFIG_TARGET_MT7988=y ++CONFIG_DEBUG_UART_BASE=0x11000000 ++CONFIG_DEBUG_UART_CLOCK=40000000 ++CONFIG_SYS_LOAD_ADDR=0x50000000 ++CONFIG_DEBUG_UART=y ++CONFIG_SYS_CBSIZE=512 ++CONFIG_SYS_PBSIZE=1049 ++CONFIG_DEFAULT_DEVICE_TREE="mt7988a-bananapi-bpi-r4-emmc" ++CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r4-poe_snand_env" ++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7988a-bpi-r4-emmc.dtb" ++CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_OF_SYSTEM_SETUP=y ++CONFIG_SMBIOS_PRODUCT_NAME="" ++CONFIG_AUTOBOOT_KEYED=y ++CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_MENU_SHOW=y ++CONFIG_CFB_CONSOLE_ANSI=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_GPIO_HOG=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_FIT=y ++CONFIG_FIT_ENABLE_SHA256_SUPPORT=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y ++CONFIG_LOGLEVEL=7 ++CONFIG_LOG=y ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_BOOTP=y ++CONFIG_CMD_BUTTON=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_CPU=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DM=y ++CONFIG_CMD_DNS=y ++CONFIG_CMD_ECHO=y ++CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_ERASEENV=y ++CONFIG_CMD_EXT4=y ++CONFIG_CMD_FAT=y ++CONFIG_CMD_FDT=y ++CONFIG_CMD_FS_GENERIC=y ++CONFIG_CMD_FS_UUID=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_HASH=y ++CONFIG_CMD_ITEST=y ++CONFIG_CMD_LED=y ++CONFIG_CMD_LICENSE=y ++CONFIG_CMD_LINK_LOCAL=y ++# CONFIG_CMD_MBR is not set ++CONFIG_CMD_MMC=y ++CONFIG_CMD_MTD=y ++CONFIG_CMD_PCI=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_PING=y ++CONFIG_CMD_PXE=y ++CONFIG_CMD_PWM=y ++CONFIG_CMD_SMC=y ++CONFIG_CMD_TFTPBOOT=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_UBI=y ++CONFIG_CMD_UBI_RENAME=y ++CONFIG_CMD_UBIFS=y ++CONFIG_CMD_ASKENV=y ++CONFIG_CMD_PART=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_SETEXPR=y ++CONFIG_CMD_SLEEP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_SOURCE=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_UUID=y ++CONFIG_DISPLAY_CPUINFO=y ++CONFIG_DM_MMC=y ++CONFIG_DM_MTD=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_DM_USB=y ++CONFIG_DM_PWM=y ++CONFIG_PWM_MTK=y ++CONFIG_HUSH_PARSER=y ++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_VERSION_VARIABLE=y ++CONFIG_PARTITION_UUIDS=y ++CONFIG_NETCONSOLE=y ++CONFIG_DM_GPIO=y ++CONFIG_DM_SCSI=y ++CONFIG_AHCI=y ++CONFIG_AHCI_PCI=y ++CONFIG_SCSI_AHCI=y ++CONFIG_SCSI=y ++CONFIG_CMD_SCSI=y ++CONFIG_PHY=y ++CONFIG_PHY_MTK_TPHY=y ++CONFIG_MTK_AHCI=y ++CONFIG_PCI=y ++CONFIG_MTD=y ++CONFIG_MTD_UBI_FASTMAP=y ++CONFIG_DM_PCI=y ++CONFIG_PCIE_MEDIATEK=y ++CONFIG_PINCTRL_MT7988=y ++CONFIG_PRE_CONSOLE_BUFFER=y ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 ++CONFIG_RAM=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_MMC=y ++CONFIG_MMC_DEFAULT_DEV=1 ++CONFIG_MMC_SUPPORTS_TUNING=y ++CONFIG_SPI=y ++CONFIG_DM_SPI=y ++CONFIG_MTK_SPI_NAND=y ++CONFIG_MTK_SPI_NAND_MTD=y ++CONFIG_SYSRESET_WATCHDOG=y ++CONFIG_WDT_MTK=y ++CONFIG_LZO=y ++CONFIG_ZSTD=y ++CONFIG_HEXDUMP=y ++CONFIG_RANDOM_UUID=y ++CONFIG_REGEX=y ++CONFIG_USB=y ++CONFIG_USB_HOST=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_MTK=y ++CONFIG_USB_STORAGE=y ++CONFIG_OF_EMBED=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_IS_IN_UBI=y ++CONFIG_ENV_UBI_PART="ubi" ++CONFIG_ENV_SIZE=0x1f000 ++CONFIG_ENV_SIZE_REDUND=0x1f000 ++CONFIG_ENV_UBI_VOLUME="ubootenv" ++CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2" ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_CLK=y ++CONFIG_SUPPORT_EMMC_BOOT=y ++CONFIG_MMC_HS200_SUPPORT=y ++CONFIG_MMC_MTK=y ++CONFIG_PHY_FIXED=y ++CONFIG_DM_ETH=y ++CONFIG_MEDIATEK_ETH=y ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7988=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_MTD_SPI_NAND=y ++CONFIG_MTK_SPIM=y ++#CONFIG_MTK_SNOR=y ++CONFIG_DM_SPI_FLASH=y ++CONFIG_SPI_FLASH_MTD=y ++CONFIG_SPI_FLASH_WINBOND=y ++# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set ++CONFIG_CMD_SF=y ++CONFIG_CMD_NAND=y ++CONFIG_CMD_NAND_TRIMFFS=y ++CONFIG_LMB_MAX_REGIONS=64 ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" +--- /dev/null ++++ b/bananapi_bpi-r4-poe_emmc_env +@@ -0,0 +1,57 @@ ++ipaddr=192.168.1.1 ++serverip=192.168.1.254 ++loadaddr=0x50000000 ++bootargs=console=ttyS0,115200n1 pci=pcie_bus_perf root=/dev/fit0 rootwait ++bootcmd=if pstore check ; then run boot_recovery ; else run boot_emmc ; fi ++bootconf=config-mt7988a-bananapi-bpi-r4-poe ++bootconf_base=config-mt7988a-bananapi-bpi-r4-poe ++bootconf_emmc=mt7988a-bananapi-bpi-r4-emmc ++bootconf_extra= ++bootdelay=0 ++bootfile=openwrt-mediatek-filogic-bananapi_bpi-r4-poe-initramfs-recovery.itb ++bootfile_bl2=openwrt-mediatek-filogic-bananapi_bpi-r4-poe-emmc-preloader.bin ++bootfile_fip=openwrt-mediatek-filogic-bananapi_bpi-r4-poe-emmc-bl31-uboot.fip ++bootfile_upg=openwrt-mediatek-filogic-bananapi_bpi-r4-poe-squashfs-sysupgrade.itb ++bootled_pwr=green:status ++bootled_rec=blue:status ++bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60 ++bootmenu_default=0 ++bootmenu_delay=0 ++bootmenu_title= ( ( ( OpenWrt ) ) ) [eMMC] ++bootmenu_0=Initialize environment.=run _firstboot ++bootmenu_0d=Run default boot command.=run boot_default ++bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return ++bootmenu_2=Boot production system from eMMC.=run boot_production ; run bootmenu_confirm_return ++bootmenu_3=Boot recovery system from eMMC.=run boot_recovery ; run bootmenu_confirm_return ++bootmenu_4=Load production system via TFTP then write to eMMC.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_5=Load recovery system via TFTP then write to eMMC.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_6=Load BL31+U-Boot FIP via TFTP then write to eMMC.=run boot_tftp_write_fip ; run bootmenu_confirm_return ++bootmenu_7=Load BL2 preloader via TFTP then write to eMMC.=run boot_tftp_write_bl2 ; run bootmenu_confirm_return ++bootmenu_8=Reboot.=reset ++bootmenu_9=Reset all settings to factory defaults.=run reset_factory ; reset ++boot_first=if button reset ; then led $bootled_rec on ; run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu ++boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever ++boot_production=led $bootled_pwr on ; run emmc_read_production && bootm $loadaddr#$bootconf#$bootconf_emmc#$bootconf_extra ; led $bootled_pwr off ++boot_recovery=led $bootled_rec on ; run emmc_read_recovery && bootm $loadaddr#$bootconf#$bootconf_emmc#$bootconf_extra ; led $bootled_rec off ++boot_emmc=run boot_production ; run boot_recovery ++boot_tftp_forever=led $bootled_rec on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done ++boot_tftp_production=tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run emmc_write_production ; if env exists noboot ; then else bootm $loadaddr#$bootconf#$bootconf_emmc#$bootconf_extra ; fi ++boot_tftp_recovery=tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run emmc_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf#$bootconf_emmc ; fi ++boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run emmc_write_fip ++boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run emmc_write_bl2 ++boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf ++mmc_write_vol=imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc erase 0x$part_addr 0x$image_size && mmc write $loadaddr 0x$part_addr 0x$image_size ++mmc_read_vol=mmc read $loadaddr $part_addr 0x100 && imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc read $loadaddr 0x$part_addr 0x$image_size && setexpr filesize $image_size * 0x200 ++part_default=production ++part_recovery=recovery ++reset_factory=eraseenv && reset ++emmc_read_production=part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_read_vol ++emmc_read_recovery=part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_read_vol ++emmc_write_bl2=mmc partconf 0 1 1 1 && mmc erase 0x0 0x400 && mmc write $fileaddr 0x0 0x400 ; mmc partconf 0 1 1 0 ++emmc_write_fip=mmc erase 0x3400 0x2000 && mmc write $fileaddr 0x3400 0x2000 && mmc erase 0x2000 0x800 ++emmc_write_production=part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_write_vol ++emmc_write_recovery=part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_write_vol ++_init_env=setenv _init_env ; setenv _create_env ; saveenv ; saveenv ++_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; run boot_first ++_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title ++_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title $ver" +--- /dev/null ++++ b/bananapi_bpi-r4-poe_sdmmc_env +@@ -0,0 +1,66 @@ ++ipaddr=192.168.1.1 ++serverip=192.168.1.254 ++loadaddr=0x50000000 ++bootargs=console=ttyS0,115200n1 pci=pcie_bus_perf root=/dev/fit0 rootwait ++bootcmd=if pstore check ; then run boot_recovery ; else run boot_sdmmc ; fi ++bootconf=config-mt7988a-bananapi-bpi-r4-poe ++bootconf_sd=mt7988a-bananapi-bpi-r4-sd ++bootconf_emmc=mt7988a-bananapi-bpi-r4-emmc ++bootconf_extra= ++bootdelay=0 ++bootfile=openwrt-mediatek-filogic-bananapi_bpi-r4-poe-initramfs-recovery.itb ++bootfile_upg=openwrt-mediatek-filogic-bananapi_bpi-r4-poe-squashfs-sysupgrade.itb ++bootled_pwr=green:status ++bootled_rec=blue:status ++bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60 ++bootmenu_default=0 ++bootmenu_delay=0 ++bootmenu_title= ( ( ( OpenWrt ) ) ) [SD card] ++bootmenu_0=Initialize environment.=run _firstboot ++bootmenu_0d=Run default boot command.=run boot_default ++bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return ++bootmenu_2=Boot production system from SD card.=run boot_production ; run bootmenu_confirm_return ++bootmenu_3=Boot recovery system from SD card.=run boot_recovery ; run bootmenu_confirm_return ++bootmenu_4=Load production system via TFTP then write to SD card.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_5=Load recovery system via TFTP then write to SD card.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_6=Install bootloader, recovery and production to NAND.=if nand info ; then run ubi_init ; else echo "NAND not detected" ; fi ; run bootmenu_confirm_return ++bootmenu_7=Reboot.=reset ++bootmenu_8=Reset all settings to factory defaults.=run reset_factory ; reset ++boot_first=if button reset ; then led $bootled_rec on ; run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu ++boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever ++boot_production=led $bootled_pwr on ; run sdmmc_read_production && bootm $loadaddr#$bootconf#$bootconf_sd#$bootconf_extra ; led $bootled_pwr off ++boot_recovery=led $bootled_rec on ; run sdmmc_read_recovery && bootm $loadaddr#$bootconf#$bootconf_emmc ; led $bootled_rec off ++boot_sdmmc=run boot_production ; run boot_recovery ++boot_tftp_forever=led $bootled_rec on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done ++boot_tftp_production=tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run sdmmc_write_production ; if env exists noboot ; then else bootm $loadaddr#$bootconf#$bootconf_sd#$bootconf_extra ; fi ++boot_tftp_recovery=tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run sdmmc_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf#$bootconf_sd ; fi ++boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf#$bootconf_sd ++mmc_write_vol=imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc erase 0x$part_addr 0x$image_size && mmc write $loadaddr 0x$part_addr 0x$image_size ++mmc_read_vol=mmc read $loadaddr $part_addr 0x100 && imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc read $loadaddr 0x$part_addr 0x$image_size && setexpr filesize $image_size * 0x200 ++part_default=production ++part_recovery=recovery ++reset_factory=eraseenv && reset ++sdmmc_read_production=part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_read_vol ++sdmmc_read_recovery=part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_read_vol ++sdmmc_read_snand_bl2=part start mmc 0 install part_addr && mmc read $loadaddr $part_addr 0x400 ++sdmmc_read_snand_fip=part start mmc 0 install part_addr && setexpr offset $part_addr + 0x800 && mmc read $loadaddr $offset 0x1000 ++sdmmc_read_emmc_install=part start mmc 0 install part_addr && setexpr offset $part_addr + 0x3800 && mmc read $loadaddr $offset 0x4000 ++sdmmc_write_production=part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_write_vol ++sdmmc_write_recovery=part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_write_vol ++snand_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr 0x0 0x80000 && mtd write bl2 $loadaddr 0x80000 0x80000 && mtd write bl2 $loadaddr 0x100000 0x80000 && mtd write bl2 $loadaddr 0x180000 0x80000 ++ubi_create_env=ubi create ubootenv 0x100000 dynamic 1 ; ubi create ubootenv2 0x100000 dynamic 2 ++ubi_format=ubi detach ; mtd erase ubi && ubi part ubi ++ubi_init=run ubi_format && run ubi_init_bl && run ubi_create_env && run ubi_init_openwrt && run ubi_init_emmc_install ++ubi_init_openwrt=run sdmmc_read_recovery && iminfo $loadaddr && run ubi_write_recovery ; run sdmmc_read_production && iminfo $loadaddr && run ubi_write_production ++ubi_init_bl=run sdmmc_read_snand_bl2 && run snand_write_bl2 && run sdmmc_read_snand_fip && run ubi_write_fip ++ubi_init_emmc_install=run sdmmc_read_emmc_install && run ubi_write_emmc_install ++ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi ++ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data ++ubi_write_fip=run ubi_remove_rootfs ; ubi check fip && ubi remove fip ; ubi create fip 0x200000 static ; ubi write $loadaddr fip 0x200000 ++ubi_write_emmc_install=ubi check emmc_install && ubi remove emmc_install ; ubi create emmc_install 0x800000 dynamic ; ubi write $loadaddr emmc_install 0x800000 ++ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic && ubi write $loadaddr fit $filesize ++ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic && ubi write $loadaddr recovery $filesize ++_init_env=setenv _init_env ; setenv _create_env ; saveenv ; saveenv ++_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; run boot_first ++_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title ++_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title $ver" +--- /dev/null ++++ b/bananapi_bpi-r4-poe_snand_env +@@ -0,0 +1,67 @@ ++ipaddr=192.168.1.1 ++serverip=192.168.1.254 ++loadaddr=0x50000000 ++bootargs=console=ttyS0,115200n1 pci=pcie_bus_perf root=/dev/fit0 rootwait ubi.block=0,fit ++bootconf=config-mt7988a-bananapi-bpi-r4-poe ++bootconf_extra=mt7988a-bananapi-bpi-r4-emmc ++bootcmd=if pstore check ; then run boot_recovery ; else run boot_ubi ; fi ++bootdelay=0 ++bootfile=openwrt-mediatek-filogic-bananapi_bpi-r4-poe-initramfs-recovery.itb ++bootfile_bl2=openwrt-mediatek-filogic-bananapi_bpi-r4-poe-snand-preloader.bin ++bootfile_fip=openwrt-mediatek-filogic-bananapi_bpi-r4-poe-snand-bl31-uboot.fip ++bootfile_upg=openwrt-mediatek-filogic-bananapi_bpi-r4-poe-squashfs-sysupgrade.itb ++bootled_pwr=green:status ++bootled_rec=blue:status ++bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60 ++bootmenu_default=0 ++bootmenu_delay=0 ++bootmenu_title= ( ( ( OpenWrt ) ) ) [SPI-NAND] ++bootmenu_0=Initialize environment.=run _firstboot ++bootmenu_0d=Run default boot command.=run boot_default ++bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return ++bootmenu_2=Boot production system from NAND.=run boot_production ; run bootmenu_confirm_return ++bootmenu_3=Boot recovery system from NAND.=run boot_recovery ; run bootmenu_confirm_return ++bootmenu_4=Load production system via TFTP then write to NAND.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_5=Load recovery system via TFTP then write to NAND.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_6=Load BL31+U-Boot FIP via TFTP then write to NAND.=run boot_tftp_write_fip ; run bootmenu_confirm_return ++bootmenu_7=Load BL2 preloader via TFTP then write to NAND.=run boot_tftp_write_bl2 ; run bootmenu_confirm_return ++bootmenu_8=Install bootloader, recovery and production to eMMC.=if mmc partconf 0 ; then run emmc_init ; else echo "eMMC not detected" ; fi ; run bootmenu_confirm_return ++bootmenu_9=Reboot.=reset ++bootmenu_10=Reset all settings to factory defaults.=run reset_factory ; reset ++boot_first=if button reset ; then led $bootled_rec on ; run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu ++boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever ++boot_production=led $bootled_pwr on ; run ubi_read_production && bootm $loadaddr#$bootconf#$bootconf_extra ; led $bootled_pwr off ++boot_recovery=led $bootled_rec on ; run ubi_read_recovery && bootm $loadaddr#$bootconf ; led $bootled_rec off ++boot_ubi=run boot_production ; run boot_recovery ++boot_tftp_forever=led $bootled_rec on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done ++boot_tftp_production=tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run ubi_write_production ; if env exists noboot ; then else bootm $loadaddr#$bootconf#$bootconf_extra ; fi ++boot_tftp_recovery=tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run ubi_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi ++boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf ++boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run ubi_write_fip && run reset_factory ++boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run snand_write_bl2 ++part_default=production ++part_recovery=recovery ++reset_factory=ubi part ubi ; mw $loadaddr 0x0 0x800 ; ubi write $loadaddr ubootenv 0x800 ; ubi write $loadaddr ubootenv2 0x800 ++snand_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr 0x0 0x80000 && mtd write bl2 $loadaddr 0x80000 0x80000 && mtd write bl2 $loadaddr 0x100000 0x80000 && mtd write bl2 $loadaddr 0x180000 0x80000 ++ubi_create_env=ubi check ubootenv || ubi create ubootenv 0x100000 dynamic 1 ; ubi check ubootenv2 || ubi create ubootenv2 0x100000 dynamic 2 ++ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi ++ubi_read_production=ubi read $loadaddr fit && iminfo $loadaddr && run ubi_prepare_rootfs ++ubi_read_recovery=ubi check recovery && ubi read $loadaddr recovery ++ubi_read_emmc_install=ubi check emmc_install && ubi read $loadaddr emmc_install ++ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data ++ubi_write_fip=run ubi_remove_rootfs ; ubi check fip && ubi remove fip ; ubi create fip 0x200000 static ; ubi write $loadaddr fip 0x200000 ++ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic && ubi write $loadaddr fit $filesize ++ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic && ubi write $loadaddr recovery $filesize ++mmc_write_vol=imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc erase 0x$part_addr 0x$image_size && mmc write $loadaddr 0x$part_addr 0x$image_size ++emmc_init=mmc dev 0 && mmc bootbus 0 0 0 0 && run emmc_init_bl && run emmc_init_openwrt ; env default bootcmd ; saveenv ; saveenv ++emmc_init_bl=run ubi_read_emmc_install && setenv fileaddr $loadaddr && run emmc_write_bl2 && setexpr fileaddr $loadaddr + 0x100000 && run emmc_write_fip && setexpr fileaddr $loadaddr + 0x500000 && run emmc_write_hdr ++emmc_init_openwrt=run ubi_read_recovery && iminfo $loadaddr && run emmc_write_recovery ; run ubi_read_production && iminfo $loadaddr && run emmc_write_production ++emmc_write_bl2=mmc partconf 0 1 1 1 && mmc erase 0x0 0x400 && mmc write $fileaddr 0x0 0x400 ; mmc partconf 0 1 1 0 ++emmc_write_fip=mmc erase 0x3400 0x2000 && mmc write $fileaddr 0x3400 0x2000 && mmc erase 0x2000 0x800 ++emmc_write_hdr=mmc erase 0x0 0x40 && mmc write $fileaddr 0x0 0x40 ++emmc_write_production=part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_write_vol ++emmc_write_recovery=part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_write_vol ++_init_env=setenv _init_env ; run ubi_create_env ; saveenv ; saveenv ++_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; run boot_first ++_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title ++_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title $ver" diff --git a/package/devel/kselftests-bpf/Makefile b/package/devel/kselftests-bpf/Makefile index 0a5b874e04db7d..d69e1e6dc3dc63 100644 --- a/package/devel/kselftests-bpf/Makefile +++ b/package/devel/kselftests-bpf/Makefile @@ -13,7 +13,7 @@ PKG_VERSION:=$(LINUX_VERSION) PKG_RELEASE:=1 PKG_MAINTAINER:=Tony Ambardar -PKG_BUILD_FLAGS:=gc-sections lto +PKG_BUILD_FLAGS:=no-lto PKG_BUILD_PARALLEL:=1 PKG_FLAGS:=nonshared @@ -23,8 +23,9 @@ include $(INCLUDE_DIR)/nls.mk define Package/kselftests-bpf SECTION:=devel CATEGORY:=Development - DEPENDS:= +libelf +zlib +libpthread +librt @!IN_SDK \ - @KERNEL_DEBUG_FS @KERNEL_DEBUG_INFO_BTF @KERNEL_BPF_EVENTS + DEPENDS:= \ + +libelf +zlib +libpthread +librt @!IN_SDK \ + @KERNEL_DEBUG_FS @KERNEL_DEBUG_INFO_BTF @KERNEL_BPF_EVENTS TITLE:=Linux Kernel Selftests (BPF) URL:=http://www.kernel.org endef @@ -33,31 +34,40 @@ define Package/kselftests-bpf/description kselftests-bpf is the Linux kernel BPF test suite endef -TEST_TARGET = test_verifier +EXE_TARGETS = test_verifier + +MOD_TARGETS = $(if $(call kernel_patchver_ge,6.4),bpf_testmod.ko) MAKE_PATH:=tools/testing/selftests/bpf MAKE_VARS = \ ARCH="$(LINUX_KARCH)" \ CROSS_COMPILE="$(TARGET_CROSS)" \ - SAN_CFLAGS="$(TARGET_CFLAGS) $(TARGET_CPPFLAGS)" \ + EXTRA_CFLAGS="$(TARGET_CFLAGS) $(TARGET_CPPFLAGS)" \ LDLIBS="$(TARGET_LDFLAGS)" \ TOOLCHAIN_INCLUDE="$(TOOLCHAIN_INC_DIRS)" \ - VMLINUX_BTF="$(LINUX_DIR)/vmlinux" + KBUILD_OUTPUT="$(LINUX_DIR)" MAKE_FLAGS = \ $(if $(findstring c,$(OPENWRT_VERBOSE)),V=1,V='') \ - O=$(PKG_BUILD_DIR) + OUTPUT=$(PKG_BUILD_DIR) define Build/Compile +$(MAKE_VARS) \ $(MAKE) $(PKG_JOBS) -C $(LINUX_DIR)/$(MAKE_PATH) \ - $(MAKE_FLAGS) $(TEST_TARGET) ; + $(MAKE_FLAGS) $(EXE_TARGETS) $(MOD_TARGETS) ; endef define Package/kselftests-bpf/install - $(INSTALL_DIR) $(1)/usr/bin - $(INSTALL_BIN) $(PKG_BUILD_DIR)/$(TEST_TARGET) $(1)/usr/bin/ + $(INSTALL_DIR) $(1)/usr/libexec/$(PKG_NAME) + $(foreach tgt,$(MOD_TARGETS), \ + $(INSTALL_DATA) \ + $(PKG_BUILD_DIR)/$(tgt) $(1)/usr/libexec/$(PKG_NAME); \ + ) + $(foreach tgt,$(EXE_TARGETS), \ + $(INSTALL_BIN) \ + $(PKG_BUILD_DIR)/$(tgt) $(1)/usr/libexec/$(PKG_NAME); \ +) endef $(eval $(call BuildPackage,kselftests-bpf)) diff --git a/package/kernel/qca-nss-dp/Makefile b/package/kernel/qca-nss-dp/Makefile index e6c380aead69ec..a917f0518cdcb6 100644 --- a/package/kernel/qca-nss-dp/Makefile +++ b/package/kernel/qca-nss-dp/Makefile @@ -1,13 +1,13 @@ include $(TOPDIR)/rules.mk PKG_NAME:=qca-nss-dp -PKG_RELEASE:=3 +PKG_RELEASE:=1 PKG_SOURCE_URL:=https://git.codelinaro.org/clo/qsdk/oss/lklm/nss-dp.git PKG_SOURCE_PROTO:=git -PKG_SOURCE_DATE:=2023-06-06 -PKG_SOURCE_VERSION:=fa67464466f69f00967cc373d1bdd6025f57eb89 -PKG_MIRROR_HASH:=39329770042c85b32780cd12eef2aad2c5df79f34d1b7081e5ba1e1cc0b1b161 +PKG_SOURCE_DATE:=2024-04-16 +PKG_SOURCE_VERSION:=5bf8b91e9fc209f175f9a58723b03055ace3d581 +PKG_MIRROR_HASH:=e86b04ea674c18fb69cd09a45ccab50317b85117e40d76c8457052c2e55d7c18 PKG_BUILD_PARALLEL:=1 PKG_FLAGS:=nonshared diff --git a/package/kernel/qca-nss-dp/patches/0006-nss_dp_main-Use-a-phy-handle-property-to-connect-to-.patch b/package/kernel/qca-nss-dp/patches/0006-nss_dp_main-Use-a-phy-handle-property-to-connect-to-.patch index 0432b82dda3f5c..20a7e6b3502fb2 100644 --- a/package/kernel/qca-nss-dp/patches/0006-nss_dp_main-Use-a-phy-handle-property-to-connect-to-.patch +++ b/package/kernel/qca-nss-dp/patches/0006-nss_dp_main-Use-a-phy-handle-property-to-connect-to-.patch @@ -26,7 +26,7 @@ Signed-off-by: Robert Marko --- a/include/nss_dp_dev.h +++ b/include/nss_dp_dev.h -@@ -202,13 +202,10 @@ struct nss_dp_dev { +@@ -225,13 +225,10 @@ struct nss_dp_dev { unsigned long drv_flags; /* Driver specific feature flags */ /* Phy related stuff */ @@ -43,7 +43,7 @@ Signed-off-by: Robert Marko --- a/nss_dp_main.c +++ b/nss_dp_main.c -@@ -418,7 +418,7 @@ static int nss_dp_open(struct net_device +@@ -436,7 +436,7 @@ static int nss_dp_open(struct net_device netif_start_queue(netdev); @@ -52,7 +52,7 @@ Signed-off-by: Robert Marko /* Notify data plane link is up */ if (dp_priv->data_plane_ops->link_state(dp_priv->dpc, 1)) { netdev_dbg(netdev, "Data plane set link failed\n"); -@@ -615,6 +615,12 @@ static int32_t nss_dp_of_get_pdata(struc +@@ -633,6 +633,12 @@ static int32_t nss_dp_of_get_pdata(struc return -EFAULT; } @@ -65,7 +65,7 @@ Signed-off-by: Robert Marko if (of_property_read_u32(np, "qcom,mactype", &hal_pdata->mactype)) { pr_err("%s: error reading mactype\n", np->name); return -EFAULT; -@@ -635,18 +641,6 @@ static int32_t nss_dp_of_get_pdata(struc +@@ -653,18 +659,6 @@ static int32_t nss_dp_of_get_pdata(struc return -EFAULT; #endif @@ -84,7 +84,7 @@ Signed-off-by: Robert Marko #if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 1, 0)) maddr = (uint8_t *)of_get_mac_address(np); #if (LINUX_VERSION_CODE > KERNEL_VERSION(5, 4, 0)) -@@ -695,56 +689,6 @@ static int32_t nss_dp_of_get_pdata(struc +@@ -753,56 +747,6 @@ static int32_t nss_dp_of_get_pdata(struc return 0; } @@ -141,7 +141,7 @@ Signed-off-by: Robert Marko #ifdef CONFIG_NET_SWITCHDEV /* * nss_dp_is_phy_dev() -@@ -803,7 +747,6 @@ static int32_t nss_dp_probe(struct platf +@@ -861,7 +805,6 @@ static int32_t nss_dp_probe(struct platf struct device_node *np = pdev->dev.of_node; struct nss_gmac_hal_platform_data gmac_hal_pdata; int32_t ret = 0; @@ -149,7 +149,7 @@ Signed-off-by: Robert Marko #if defined(NSS_DP_PPE_SUPPORT) uint32_t vsi_id; fal_port_t port_id; -@@ -880,22 +823,14 @@ static int32_t nss_dp_probe(struct platf +@@ -940,22 +883,15 @@ static int32_t nss_dp_probe(struct platf dp_priv->drv_flags |= NSS_DP_PRIV_FLAG(INIT_DONE); @@ -161,20 +161,22 @@ Signed-off-by: Robert Marko - } - snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, - dp_priv->miibus->id, dp_priv->phy_mdio_addr); -- + if (dp_priv->phy_node) { - SET_NETDEV_DEV(netdev, &pdev->dev); - dp_priv->phydev = phy_connect(netdev, phy_id, - &nss_dp_adjust_link, - dp_priv->phy_mii_type); - if (IS_ERR(dp_priv->phydev)) { - netdev_dbg(netdev, "failed to connect to phy device\n"); +- goto phy_setup_fail; +- } + dp_priv->phydev = of_phy_connect(netdev, dp_priv->phy_node, -+ &nss_dp_adjust_link, 0, -+ dp_priv->phy_mii_type); ++ &nss_dp_adjust_link, 0, ++ dp_priv->phy_mii_type); + if (!(dp_priv->phydev)) { + netdev_err(netdev, "failed to connect to phy device\n"); - goto phy_setup_fail; - } ++ goto phy_setup_fail; ++ } } + + #if defined(NSS_DP_PPE_SUPPORT) diff --git a/package/kernel/qca-nss-dp/patches/0008-nss-dp-allow-setting-netdev-name-from-DTS.patch b/package/kernel/qca-nss-dp/patches/0008-nss-dp-allow-setting-netdev-name-from-DTS.patch index e90bf32ced7707..d70284dfb51414 100644 --- a/package/kernel/qca-nss-dp/patches/0008-nss-dp-allow-setting-netdev-name-from-DTS.patch +++ b/package/kernel/qca-nss-dp/patches/0008-nss-dp-allow-setting-netdev-name-from-DTS.patch @@ -15,7 +15,7 @@ Signed-off-by: Robert Marko --- a/nss_dp_main.c +++ b/nss_dp_main.c -@@ -746,18 +746,29 @@ static int32_t nss_dp_probe(struct platf +@@ -804,18 +804,29 @@ static int32_t nss_dp_probe(struct platf struct nss_dp_dev *dp_priv; struct device_node *np = pdev->dev.of_node; struct nss_gmac_hal_platform_data gmac_hal_pdata; diff --git a/package/kernel/qca-nss-dp/patches/0009-nss-dp-switchdev-fix-FDB-roaming.patch b/package/kernel/qca-nss-dp/patches/0009-nss-dp-switchdev-fix-FDB-roaming.patch index ec10bdc2d98b52..7fccfac76df3c5 100644 --- a/package/kernel/qca-nss-dp/patches/0009-nss-dp-switchdev-fix-FDB-roaming.patch +++ b/package/kernel/qca-nss-dp/patches/0009-nss-dp-switchdev-fix-FDB-roaming.patch @@ -31,7 +31,7 @@ Signed-off-by: Robert Marko #define NSS_DP_SWITCH_ID 0 #define NSS_DP_SW_ETHTYPE_PID 0 /* PPE ethtype profile ID for slow protocols */ -@@ -521,7 +523,76 @@ static struct notifier_block *nss_dp_sw_ +@@ -534,7 +536,76 @@ static struct notifier_block *nss_dp_sw_ #else diff --git a/package/kernel/qca-nss-dp/patches/0010-nss-dp-include-net-netdev_rx_queue.h.patch b/package/kernel/qca-nss-dp/patches/0010-nss-dp-include-net-netdev_rx_queue.h.patch deleted file mode 100644 index ddbf342868ab97..00000000000000 --- a/package/kernel/qca-nss-dp/patches/0010-nss-dp-include-net-netdev_rx_queue.h.patch +++ /dev/null @@ -1,25 +0,0 @@ -From 01ec275bd0942ddc6b80e1d3671cdc66be670f57 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Fri, 1 Sep 2023 12:23:58 +0200 -Subject: [PATCH] nss-dp: include - -Since 6.5 netdev_rx_queue was moved out of netdevice.h so include the new -header since that is where it lives now. - -Signed-off-by: Robert Marko ---- - nss_dp_main.c | 3 +++ - 1 file changed, 3 insertions(+) - ---- a/nss_dp_main.c -+++ b/nss_dp_main.c -@@ -34,6 +34,9 @@ - #if defined(NSS_DP_MAC_POLL_SUPPORT) - #include - #endif -+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6, 5, 0)) -+#include -+#endif - - #include "nss_dp_hal.h" - diff --git a/package/kernel/qca-nss-dp/patches/0011-02-nss_dp_switchdev-correctly-unregister-notifier-on-dp.patch b/package/kernel/qca-nss-dp/patches/0011-02-nss_dp_switchdev-correctly-unregister-notifier-on-dp.patch index e0a47cfca00332..8379fcf20cc1af 100644 --- a/package/kernel/qca-nss-dp/patches/0011-02-nss_dp_switchdev-correctly-unregister-notifier-on-dp.patch +++ b/package/kernel/qca-nss-dp/patches/0011-02-nss_dp_switchdev-correctly-unregister-notifier-on-dp.patch @@ -16,7 +16,7 @@ Signed-off-by: Christian Marangi --- a/include/nss_dp_dev.h +++ b/include/nss_dp_dev.h -@@ -312,6 +312,7 @@ void nss_dp_set_ethtool_ops(struct net_d +@@ -349,6 +349,7 @@ void nss_dp_set_ethtool_ops(struct net_d */ #ifdef CONFIG_NET_SWITCHDEV void nss_dp_switchdev_setup(struct net_device *dev); @@ -26,7 +26,7 @@ Signed-off-by: Christian Marangi --- a/nss_dp_main.c +++ b/nss_dp_main.c -@@ -913,6 +913,10 @@ static int nss_dp_remove(struct platform +@@ -972,6 +972,10 @@ static int nss_dp_remove(struct platform if (!dp_priv) continue; @@ -39,7 +39,7 @@ Signed-off-by: Christian Marangi --- a/nss_dp_switchdev.c +++ b/nss_dp_switchdev.c -@@ -635,4 +635,17 @@ void nss_dp_switchdev_setup(struct net_d +@@ -648,4 +648,17 @@ void nss_dp_switchdev_setup(struct net_d switch_init_done = true; } diff --git a/package/kernel/qca-nss-dp/patches/0011-03-nss_dp_main-swap-dp_exit-function-call.patch b/package/kernel/qca-nss-dp/patches/0011-03-nss_dp_main-swap-dp_exit-function-call.patch index 7ffde3d2860fc3..68a9821cebabec 100644 --- a/package/kernel/qca-nss-dp/patches/0011-03-nss_dp_main-swap-dp_exit-function-call.patch +++ b/package/kernel/qca-nss-dp/patches/0011-03-nss_dp_main-swap-dp_exit-function-call.patch @@ -15,7 +15,7 @@ Signed-off-by: Christian Marangi --- a/nss_dp_main.c +++ b/nss_dp_main.c -@@ -1082,6 +1082,8 @@ int __init nss_dp_init(void) +@@ -1163,6 +1163,8 @@ int __init nss_dp_init(void) */ void __exit nss_dp_exit(void) { @@ -24,7 +24,7 @@ Signed-off-by: Christian Marangi /* * TODO Move this to soc_ops */ -@@ -1089,8 +1091,6 @@ void __exit nss_dp_exit(void) +@@ -1170,8 +1172,6 @@ void __exit nss_dp_exit(void) nss_dp_hal_cleanup(); dp_global_ctx.common_init_done = false; } diff --git a/package/kernel/qca-nss-dp/patches/0011-04-nss_dp_main-call-unregister_netdev-first-in-dp_remov.patch b/package/kernel/qca-nss-dp/patches/0011-04-nss_dp_main-call-unregister_netdev-first-in-dp_remov.patch index 20e87459f8d220..2721d2cfba2ab2 100644 --- a/package/kernel/qca-nss-dp/patches/0011-04-nss_dp_main-call-unregister_netdev-first-in-dp_remov.patch +++ b/package/kernel/qca-nss-dp/patches/0011-04-nss_dp_main-call-unregister_netdev-first-in-dp_remov.patch @@ -15,7 +15,7 @@ Signed-off-by: Christian Marangi --- a/nss_dp_main.c +++ b/nss_dp_main.c -@@ -920,6 +920,9 @@ static int nss_dp_remove(struct platform +@@ -979,6 +979,9 @@ static int nss_dp_remove(struct platform dp_ops = dp_priv->data_plane_ops; hal_ops = dp_priv->gmac_hal_ops; @@ -25,7 +25,7 @@ Signed-off-by: Christian Marangi if (dp_priv->phydev) phy_disconnect(dp_priv->phydev); -@@ -931,7 +934,6 @@ static int nss_dp_remove(struct platform +@@ -990,7 +993,6 @@ static int nss_dp_remove(struct platform #endif hal_ops->exit(dp_priv->gmac_hal_ctx); dp_ops->deinit(dp_priv->dpc); diff --git a/package/kernel/qca-nss-dp/patches/0011-05-nss_dp_main-use-phy_detach-instead-of-disconnect-in-.patch b/package/kernel/qca-nss-dp/patches/0011-05-nss_dp_main-use-phy_detach-instead-of-disconnect-in-.patch index 6e87e4e8c4c04a..3c99cae2d502aa 100644 --- a/package/kernel/qca-nss-dp/patches/0011-05-nss_dp_main-use-phy_detach-instead-of-disconnect-in-.patch +++ b/package/kernel/qca-nss-dp/patches/0011-05-nss_dp_main-use-phy_detach-instead-of-disconnect-in-.patch @@ -15,7 +15,7 @@ Signed-off-by: Christian Marangi --- a/nss_dp_main.c +++ b/nss_dp_main.c -@@ -924,7 +924,7 @@ static int nss_dp_remove(struct platform +@@ -983,7 +983,7 @@ static int nss_dp_remove(struct platform unregister_netdev(dp_priv->netdev); if (dp_priv->phydev) diff --git a/package/kernel/qca-ssdk/Makefile b/package/kernel/qca-ssdk/Makefile index bbe9f120514627..ed18f17504dbef 100644 --- a/package/kernel/qca-ssdk/Makefile +++ b/package/kernel/qca-ssdk/Makefile @@ -1,13 +1,13 @@ include $(TOPDIR)/rules.mk PKG_NAME:=qca-ssdk -PKG_RELEASE:=6 +PKG_RELEASE:=1 PKG_SOURCE_URL:=https://git.codelinaro.org/clo/qsdk/oss/lklm/qca-ssdk.git PKG_SOURCE_PROTO:=git -PKG_SOURCE_DATE:=2023-10-04 -PKG_SOURCE_VERSION:=23a5aa4a4d5834da7a07efb58baebfbee91786b0 -PKG_MIRROR_HASH:=53fb201053b3aca004c4da07b06a0608b0b3322a2062b1f7ab3b3a7871ddabcb +PKG_SOURCE_DATE:=2024-04-17 +PKG_SOURCE_VERSION:=3d060f7ad70d087f6b0452abe79ab6d042e8cd53 +PKG_MIRROR_HASH:=6f5e390b294e699491584094f5d7eb941de6237ad8c5320191e9e306fbcd8eb5 PKG_FLAGS:=nonshared PKG_BUILD_PARALLEL:=1 diff --git a/package/kernel/qca-ssdk/patches/0001-config-identify-kernel-6.6.patch b/package/kernel/qca-ssdk/patches/0001-config-identify-kernel-6.6.patch deleted file mode 100644 index 2dc092326306b3..00000000000000 --- a/package/kernel/qca-ssdk/patches/0001-config-identify-kernel-6.6.patch +++ /dev/null @@ -1,47 +0,0 @@ -From f6c0115daaac586740e873a3b8145c5370a73dce Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Sat, 17 Feb 2024 13:02:31 +0100 -Subject: [PATCH] config: identify kernel 6.6 - -Identify kernel 6.6 so it can be compiled against. - -Signed-off-by: Robert Marko ---- - config | 5 +++++ - make/linux_opt.mk | 4 ++-- - 2 files changed, 7 insertions(+), 2 deletions(-) - ---- a/config -+++ b/config -@@ -27,6 +27,11 @@ endif - ifeq ($(KVER),$(filter 6.1%,$(KVER))) - OS_VER=6_1 - endif -+ -+ifeq ($(KVER),$(filter 6.6%,$(KVER))) -+ OS_VER=6_6 -+endif -+ - ifeq ($(KVER), 3.4.0) - OS_VER=3_4 - endif ---- a/make/linux_opt.mk -+++ b/make/linux_opt.mk -@@ -450,7 +450,7 @@ ifeq (KSLIB, $(MODULE_TYPE)) - KASAN_SHADOW_SCALE_SHIFT := 3 - endif - -- ifeq ($(OS_VER),$(filter 5_4 6_1, $(OS_VER))) -+ ifeq ($(OS_VER),$(filter 5_4 6_1 6_6, $(OS_VER))) - ifeq ($(ARCH), arm64) - KASAN_OPTION += -DKASAN_SHADOW_SCALE_SHIFT=$(KASAN_SHADOW_SCALE_SHIFT) - endif -@@ -481,7 +481,7 @@ ifeq (KSLIB, $(MODULE_TYPE)) - - endif - -- ifeq ($(OS_VER),$(filter 4_4 5_4 6_1, $(OS_VER))) -+ ifeq ($(OS_VER),$(filter 4_4 5_4 6_1 6_6, $(OS_VER))) - MODULE_CFLAG += -DKVER34 - MODULE_CFLAG += -DKVER32 - MODULE_CFLAG += -DLNX26_22 diff --git a/package/kernel/qca-ssdk/patches/101-hsl_phy-add-support-for-detection-PSGMII-PHY-mode.patch b/package/kernel/qca-ssdk/patches/101-hsl_phy-add-support-for-detection-PSGMII-PHY-mode.patch index c27902c4ce1d8c..9d028992a7298b 100644 --- a/package/kernel/qca-ssdk/patches/101-hsl_phy-add-support-for-detection-PSGMII-PHY-mode.patch +++ b/package/kernel/qca-ssdk/patches/101-hsl_phy-add-support-for-detection-PSGMII-PHY-mode.patch @@ -13,7 +13,7 @@ Signed-off-by: Christian Marangi --- a/src/hsl/phy/hsl_phy.c +++ b/src/hsl/phy/hsl_phy.c -@@ -1335,6 +1335,9 @@ hsl_port_phydev_interface_mode_status_ge +@@ -1322,6 +1322,9 @@ hsl_port_phydev_interface_mode_status_ge case PHY_INTERFACE_MODE_10GKR: *interface_mode_status = PORT_10GBASE_R; break; diff --git a/package/kernel/qca-ssdk/patches/102-qca-ssdk-support-selecting-PCS-channel-for-PORT3-on-.patch b/package/kernel/qca-ssdk/patches/102-qca-ssdk-support-selecting-PCS-channel-for-PORT3-on-.patch index 5e390d8ee339c0..db84ea1422f1b8 100644 --- a/package/kernel/qca-ssdk/patches/102-qca-ssdk-support-selecting-PCS-channel-for-PORT3-on-.patch +++ b/package/kernel/qca-ssdk/patches/102-qca-ssdk-support-selecting-PCS-channel-for-PORT3-on-.patch @@ -24,15 +24,15 @@ Signed-off-by: Mantas Pucka --- a/include/init/ssdk_dts.h +++ b/include/init/ssdk_dts.h -@@ -101,6 +101,7 @@ typedef struct +@@ -99,6 +99,7 @@ typedef struct a_uint32_t emu_chip_ver; /*only valid when is_emulation is true*/ a_uint32_t clk_mode; a_uint32_t pcie_hw_base; + a_uint32_t port3_pcs_channel; + led_ctrl_pattern_t source_pattern[SSDK_MAX_PORT_NUM][PORT_LED_SOURCE_MAX]; } ssdk_dt_cfg; - #define SSDK_MAX_NR_ETH 6 -@@ -162,6 +163,7 @@ a_uint32_t ssdk_device_id_get(a_uint32_t +@@ -161,6 +162,7 @@ a_uint32_t ssdk_device_id_get(a_uint32_t struct device_node *ssdk_dts_node_get(a_uint32_t dev_id); struct clk *ssdk_dts_essclk_get(a_uint32_t dev_id); struct clk *ssdk_dts_cmnclk_get(a_uint32_t dev_id); @@ -62,7 +62,7 @@ Signed-off-by: Mantas Pucka cppe_port_mux_ctrl.bf.port4_pcs_sel = --- a/src/adpt/hppe/adpt_hppe_uniphy.c +++ b/src/adpt/hppe/adpt_hppe_uniphy.c -@@ -1122,9 +1122,6 @@ __adpt_hppe_uniphy_psgmii_mode_set(a_uin +@@ -1160,9 +1160,6 @@ __adpt_hppe_uniphy_psgmii_mode_set(a_uin { a_uint32_t i; sw_error_t rv = SW_OK; @@ -72,7 +72,7 @@ Signed-off-by: Mantas Pucka union uniphy_mode_ctrl_u uniphy_mode_ctrl; -@@ -1134,9 +1131,7 @@ __adpt_hppe_uniphy_psgmii_mode_set(a_uin +@@ -1172,9 +1169,7 @@ __adpt_hppe_uniphy_psgmii_mode_set(a_uin SSDK_DEBUG("uniphy %d is psgmii mode\n", uniphy_index); #if defined(CPPE) if (adpt_ppe_type_get(dev_id) == CPPE_TYPE) { @@ -92,14 +92,14 @@ Signed-off-by: Mantas Pucka +a_uint32_t ssdk_dts_port3_pcs_channel_get(a_uint32_t dev_id) +{ + ssdk_dt_cfg* cfg = ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]; -+ ++ + return cfg->port3_pcs_channel; +} + - #ifndef BOARD_AR71XX #if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)) static void ssdk_dt_parse_mac_mode(a_uint32_t dev_id, -@@ -306,6 +313,25 @@ static void ssdk_dt_parse_mac_mode(a_uin + struct device_node *switch_node, ssdk_init_cfg *cfg) +@@ -305,6 +312,25 @@ static void ssdk_dt_parse_mac_mode(a_uin return; } @@ -109,7 +109,7 @@ Signed-off-by: Mantas Pucka +{ + const __be32 *port3_pcs_channel; + a_uint32_t len = 0; -+ ++ + port3_pcs_channel = of_get_property(switch_node, "port3_pcs_channel", &len); + if (!port3_pcs_channel) { + ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->port3_pcs_channel = 2; @@ -125,7 +125,7 @@ Signed-off-by: Mantas Pucka #ifdef IN_UNIPHY static void ssdk_dt_parse_uniphy(a_uint32_t dev_id) { -@@ -1292,6 +1318,7 @@ sw_error_t ssdk_dt_parse(ssdk_init_cfg * +@@ -1347,6 +1373,7 @@ sw_error_t ssdk_dt_parse(ssdk_init_cfg * rv = ssdk_dt_parse_access_mode(switch_node, ssdk_dt_priv); SW_RTN_ON_ERROR(rv); ssdk_dt_parse_mac_mode(*dev_id, switch_node, cfg); diff --git a/package/kernel/qca-ssdk/patches/103-mdio-adapt-to-C22-and-C45-read-write-split.patch b/package/kernel/qca-ssdk/patches/103-mdio-adapt-to-C22-and-C45-read-write-split.patch deleted file mode 100644 index 7ddca554ecbd50..00000000000000 --- a/package/kernel/qca-ssdk/patches/103-mdio-adapt-to-C22-and-C45-read-write-split.patch +++ /dev/null @@ -1,98 +0,0 @@ -From bdae481e89cbe551068a99028bb57119b59f5ff4 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Tue, 26 Mar 2024 12:19:49 +0100 -Subject: [PATCH] mdio: adapt to C22 and C45 read/write split - -Kernel 6.3 has introduced separate C45 read/write operations, and thus -split them out of the C22 operations completely so the old way of marking -C45 reads and writes via the register value does not work anymore. - -This is causing SSDK to fail and find C45 only PHY-s such as Aquantia ones: -[ 22.187877] ssdk_phy_driver_init[371]:INFO:dev_id = 0, phy_adress = 8, phy_id = 0x0 phytype doesn't match -[ 22.209924] ssdk_phy_driver_init[371]:INFO:dev_id = 0, phy_adress = 0, phy_id = 0x0 phytype doesn't match - -This in turn causes USXGMII MAC autoneg bit to not get set and then UNIPHY -autoneg will time out, causing the 10G ports not to work: -[ 37.292784] uniphy autoneg time out! - -So, lets detect C45 reads and writes by the magic BIT(30) in the register -argument and if so call separate C45 mdiobus read/write functions. - -Signed-off-by: Robert Marko ---- - include/init/ssdk_plat.h | 7 +++++++ - src/init/ssdk_plat.c | 30 ++++++++++++++++++++++++++++++ - 2 files changed, 37 insertions(+) - ---- a/include/init/ssdk_plat.h -+++ b/include/init/ssdk_plat.h -@@ -505,3 +505,10 @@ void ssdk_plat_exit(a_uint32_t dev_id); - - #endif - /*qca808x_end*/ -+ -+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6,3,0)) -+#define MII_ADDR_C45 (1<<30) -+#define MII_DEVADDR_C45_SHIFT 16 -+#define MII_DEVADDR_C45_MASK GENMASK(20, 16) -+#define MII_REGADDR_C45_MASK GENMASK(15, 0) -+#endif ---- a/src/init/ssdk_plat.c -+++ b/src/init/ssdk_plat.c -@@ -356,6 +356,18 @@ phy_addr_validation_check(a_uint32_t phy - return A_TRUE; - } - -+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6,3,0)) -+static inline u16 mdiobus_c45_regad(u32 regnum) -+{ -+ return FIELD_GET(MII_REGADDR_C45_MASK, regnum); -+} -+ -+static inline u16 mdiobus_c45_devad(u32 regnum) -+{ -+ return FIELD_GET(MII_DEVADDR_C45_MASK, regnum); -+} -+#endif -+ - sw_error_t - qca_ar8327_phy_read(a_uint32_t dev_id, a_uint32_t phy_addr, - a_uint32_t reg, a_uint16_t* data) -@@ -371,9 +383,18 @@ qca_ar8327_phy_read(a_uint32_t dev_id, a - if (!bus) - return SW_NOT_SUPPORTED; - phy_addr = TO_PHY_ADDR(phy_addr); -+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6,3,0)) -+ mutex_lock(&bus->mdio_lock); -+ if (reg & MII_ADDR_C45) -+ *data = __mdiobus_c45_read(bus, phy_addr, mdiobus_c45_devad(reg), mdiobus_c45_regad(reg)); -+ else -+ *data = __mdiobus_read(bus, phy_addr, reg); -+ mutex_unlock(&bus->mdio_lock); -+#else - mutex_lock(&bus->mdio_lock); - *data = __mdiobus_read(bus, phy_addr, reg); - mutex_unlock(&bus->mdio_lock); -+#endif - - return 0; - } -@@ -393,9 +414,18 @@ qca_ar8327_phy_write(a_uint32_t dev_id, - if (!bus) - return SW_NOT_SUPPORTED; - phy_addr = TO_PHY_ADDR(phy_addr); -+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6,3,0)) -+ mutex_lock(&bus->mdio_lock); -+ if (reg & MII_ADDR_C45) -+ __mdiobus_c45_write(bus, phy_addr, mdiobus_c45_devad(reg), mdiobus_c45_regad(reg), data); -+ else -+ __mdiobus_write(bus, phy_addr, reg, data); -+ mutex_unlock(&bus->mdio_lock); -+#else - mutex_lock(&bus->mdio_lock); - __mdiobus_write(bus, phy_addr, reg, data); - mutex_unlock(&bus->mdio_lock); -+#endif - - return 0; - } diff --git a/package/kernel/qca-ssdk/patches/200-allow-parallel-build.patch b/package/kernel/qca-ssdk/patches/200-allow-parallel-build.patch index 5635c2fdcfb307..6c28e0ff2ebd68 100644 --- a/package/kernel/qca-ssdk/patches/200-allow-parallel-build.patch +++ b/package/kernel/qca-ssdk/patches/200-allow-parallel-build.patch @@ -40,7 +40,7 @@ kslib_c: --- a/make/linux_opt.mk +++ b/make/linux_opt.mk -@@ -777,6 +777,6 @@ LOCAL_CFLAGS += $(CPU_CFLAG) -D"KBUILD_M +@@ -778,6 +778,6 @@ LOCAL_CFLAGS += $(CPU_CFLAG) -D"KBUILD_M #################################################################### # cflags for LNX Modules-Style Makefile #################################################################### diff --git a/package/kernel/qca-ssdk/patches/201-fix-compile-warnings.patch b/package/kernel/qca-ssdk/patches/201-fix-compile-warnings.patch new file mode 100644 index 00000000000000..5b57f41975bbca --- /dev/null +++ b/package/kernel/qca-ssdk/patches/201-fix-compile-warnings.patch @@ -0,0 +1,31 @@ +--- a/src/fal/fal_port_ctrl.c ++++ b/src/fal/fal_port_ctrl.c +@@ -2089,7 +2089,7 @@ fal_port_hibernate_get (a_uint32_t dev_i + */ + sw_error_t + fal_port_cdt (a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair, +- a_uint32_t * cable_status, a_uint32_t * cable_len) ++ fal_cable_status_t * cable_status, a_uint32_t * cable_len) + { + sw_error_t rv; + +--- a/src/fal/fal_portvlan.c ++++ b/src/fal/fal_portvlan.c +@@ -2173,7 +2173,7 @@ fal_netisolate_get(a_uint32_t dev_id, a_ + * @return SW_OK or error code + */ + sw_error_t +-fal_eg_trans_filter_bypass_en_set(a_uint32_t dev_id, a_bool_t enable) ++fal_eg_trans_filter_bypass_en_set(a_uint32_t dev_id, a_uint32_t enable) + { + sw_error_t rv; + +@@ -2190,7 +2190,7 @@ fal_eg_trans_filter_bypass_en_set(a_uint + * @return SW_OK or error code + */ + sw_error_t +-fal_eg_trans_filter_bypass_en_get(a_uint32_t dev_id, a_bool_t* enable) ++fal_eg_trans_filter_bypass_en_get(a_uint32_t dev_id, a_uint32_t* enable) + { + sw_error_t rv; + diff --git a/package/libs/libbpf/Makefile b/package/libs/libbpf/Makefile index 666786e9f64758..6b894972a763c7 100644 --- a/package/libs/libbpf/Makefile +++ b/package/libs/libbpf/Makefile @@ -8,13 +8,13 @@ include $(TOPDIR)/rules.mk PKG_NAME:=libbpf -PKG_VERSION:=1.4.0 +PKG_VERSION:=1.4.1 PKG_RELEASE:=1 PKG_SOURCE_URL:=https://github.com/libbpf/libbpf -PKG_MIRROR_HASH:=4c37636699c604de345937bdbdf8f2e6ce69cbf768a4aa669c32b542e5302de6 +PKG_MIRROR_HASH:=46469f720ed246529e46d84a6444ae1c1a1eaf2a717a5a055c9973bb52159ec3 PKG_SOURCE_PROTO:=git -PKG_SOURCE_VERSION:=v1.4.0 +PKG_SOURCE_VERSION:=v1.4.1 PKG_ABI_VERSION:=$(firstword $(subst .,$(space),$(PKG_VERSION))) PKG_MAINTAINER:=Tony Ambardar diff --git a/package/libs/mbedtls/Makefile b/package/libs/mbedtls/Makefile index 568ca283085bab..8990db6fdc82e1 100644 --- a/package/libs/mbedtls/Makefile +++ b/package/libs/mbedtls/Makefile @@ -156,6 +156,7 @@ define Build/InstallDev $(INSTALL_DIR) $(1)/usr/lib $(CP) $(PKG_INSTALL_DIR)/usr/lib/lib*.so* $(1)/usr/lib/ $(CP) $(PKG_INSTALL_DIR)/usr/lib/lib*.a $(1)/usr/lib/ + $(CP) $(PKG_INSTALL_DIR)/usr/lib/cmake $(1)/usr/lib/ $(INSTALL_DIR) $(1)/usr/lib/pkgconfig $(CP) \ $(PKG_INSTALL_DIR)/usr/lib/pkgconfig/mbedcrypto.pc \ diff --git a/package/network/services/dropbear/Makefile b/package/network/services/dropbear/Makefile index b0f486f990a996..abb46157ea4f78 100644 --- a/package/network/services/dropbear/Makefile +++ b/package/network/services/dropbear/Makefile @@ -9,7 +9,7 @@ include $(TOPDIR)/rules.mk PKG_NAME:=dropbear PKG_VERSION:=2022.83 -PKG_RELEASE:=1 +PKG_RELEASE:=2 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2 PKG_SOURCE_URL:= \ @@ -57,7 +57,7 @@ define Package/dropbear CATEGORY:=Base system TITLE:=Small SSH2 client/server DEPENDS:= +DROPBEAR_ZLIB:zlib - ALTERNATIVES:= + ALTERNATIVES:=100:/usr/bin/ssh-keygen:/usr/sbin/dropbear $(if $(CONFIG_DROPBEAR_SCP),ALTERNATIVES+= \ 100:/usr/bin/scp:/usr/sbin/dropbear,) $(if $(CONFIG_DROPBEAR_DBCLIENT),ALTERNATIVES+= \ diff --git a/package/network/services/odhcpd/Makefile b/package/network/services/odhcpd/Makefile index 55a24a90e532cb..4092588353ba75 100644 --- a/package/network/services/odhcpd/Makefile +++ b/package/network/services/odhcpd/Makefile @@ -12,9 +12,9 @@ PKG_RELEASE:=1 PKG_SOURCE_PROTO:=git PKG_SOURCE_URL=$(PROJECT_GIT)/project/odhcpd.git -PKG_MIRROR_HASH:=08fddf4294929d1713e0c3f7b258f8c7bf4abe731d5f34fceb797faa411f7a58 -PKG_SOURCE_DATE:=2023-10-24 -PKG_SOURCE_VERSION:=d8118f6e76e5519881f9a37137c3a06b3cb60fd2 +PKG_MIRROR_HASH:=f6e1c18551a00e01229fa12caa7b3fe33ad82785150fedcbe615fcc651ba2876 +PKG_SOURCE_DATE:=2024-05-08 +PKG_SOURCE_VERSION:=a29882318a4ccb3ae26f7cc0145e06ad4ead224b PKG_MAINTAINER:=Hans Dedecker PKG_LICENSE:=GPL-2.0 diff --git a/target/linux/armsr/Makefile b/target/linux/armsr/Makefile index 7de77decb55390..c2e57e52da6019 100644 --- a/target/linux/armsr/Makefile +++ b/target/linux/armsr/Makefile @@ -10,6 +10,7 @@ FEATURES:=fpu pci pcie rtc usb boot-part rootfs-part FEATURES+=cpiogz ext4 ramdisk squashfs targz vmdk KERNEL_PATCHVER:=6.1 +KERNEL_TESTING_PATCHVER:=6.6 include $(INCLUDE_DIR)/target.mk diff --git a/target/linux/armsr/armv7/config-6.6 b/target/linux/armsr/armv7/config-6.6 new file mode 100644 index 00000000000000..18f5cd7c79a067 --- /dev/null +++ b/target/linux/armsr/armv7/config-6.6 @@ -0,0 +1,83 @@ +CONFIG_ALIGNMENT_TRAP=y +CONFIG_ARCH_32BIT_OFF_T=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_MMAP_RND_BITS=8 +CONFIG_ARCH_MULTIPLATFORM=y +# CONFIG_ARCH_MULTI_V4 is not set +# CONFIG_ARCH_MULTI_V4T is not set +CONFIG_ARCH_MULTI_V6_V7=y +CONFIG_ARCH_MULTI_V7=y +CONFIG_ARCH_NR_GPIO=0 +CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y +CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_ARCH_VIRT=y +CONFIG_ARM=y +CONFIG_ARM_CPU_SUSPEND=y +CONFIG_ARM_HAS_SG_CHAIN=y +CONFIG_ARM_HEAVY_MB=y +# CONFIG_ARM_HIGHBANK_CPUIDLE is not set +CONFIG_ARM_L1_CACHE_SHIFT=6 +CONFIG_ARM_L1_CACHE_SHIFT_6=y +CONFIG_ARM_LPAE=y +CONFIG_ARM_PATCH_IDIV=y +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_ARM_PSCI=y +CONFIG_ARM_THUMB=y +CONFIG_ARM_UNWIND=y +CONFIG_ARM_VIRT_EXT=y +CONFIG_AUTO_ZRELADDR=y +CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y +CONFIG_CACHE_L2X0=y +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_SPECTRE=y +CONFIG_CPU_THUMB_CAPABLE=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_V7=y +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" +CONFIG_DMA_OPS=y +CONFIG_EDAC_ATOMIC_SCRUB=y +CONFIG_GENERIC_IRQ_MULTI_HANDLER=y +CONFIG_GENERIC_VDSO_32=y +CONFIG_HARDEN_BRANCH_PREDICTOR=y +CONFIG_HAVE_SMP=y +CONFIG_HZ_FIXED=0 +CONFIG_HZ_PERIODIC=y +CONFIG_MIGHT_HAVE_CACHE_L2X0=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_NEON=y +CONFIG_NR_CPUS=4 +CONFIG_OLD_SIGACTION=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_OUTER_CACHE=y +CONFIG_OUTER_CACHE_SYNC=y +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PHYS_OFFSET=0 +CONFIG_RTC_MC146818_LIB=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SMP_ON_UP=y +CONFIG_SWP_EMULATE=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +CONFIG_UNWINDER_ARM=y +# CONFIG_UNWINDER_FRAME_POINTER is not set +CONFIG_USE_OF=y +CONFIG_VFP=y +CONFIG_VFPv3=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_BCJ=y +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_ZBOOT_ROM_TEXT=0x0 diff --git a/target/linux/armsr/armv8/config-6.6 b/target/linux/armsr/armv8/config-6.6 new file mode 100644 index 00000000000000..aa5774a7b656a6 --- /dev/null +++ b/target/linux/armsr/armv8/config-6.6 @@ -0,0 +1,852 @@ +CONFIG_64BIT=y +CONFIG_ACPI_APEI=y +# CONFIG_ACPI_FFH is not set +# CONFIG_ACPI_FPDT is not set +CONFIG_ACPI_HMAT=y +CONFIG_ACPI_PCC=y +CONFIG_AHCI_IMX=y +CONFIG_AHCI_MVEBU=y +CONFIG_AHCI_QORIQ=y +CONFIG_AMPERE_ERRATUM_AC03_CPU_38=y +CONFIG_ARCH_BCM=y +CONFIG_ARCH_BCM2835=y +# CONFIG_ARCH_BCMBCA is not set +CONFIG_ARCH_BCM_IPROC=y +CONFIG_ARCH_BRCMSTB=y +CONFIG_ARCH_HISI=y +CONFIG_ARCH_INTEL_SOCFPGA=y +CONFIG_ARCH_LAYERSCAPE=y +CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y +CONFIG_ARCH_MMAP_RND_BITS=18 +CONFIG_ARCH_MMAP_RND_BITS_MAX=24 +CONFIG_ARCH_MMAP_RND_BITS_MIN=18 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 +CONFIG_ARCH_MVEBU=y +CONFIG_ARCH_MXC=y +CONFIG_ARCH_NXP=y +CONFIG_ARCH_PROC_KCORE_TEXT=y +CONFIG_ARCH_R8A774A1=y +CONFIG_ARCH_R8A774B1=y +CONFIG_ARCH_R8A774C0=y +CONFIG_ARCH_R8A774E1=y +# CONFIG_ARCH_R8A77950 is not set +# CONFIG_ARCH_R8A77951 is not set +# CONFIG_ARCH_R8A77960 is not set +# CONFIG_ARCH_R8A77961 is not set +# CONFIG_ARCH_R8A77965 is not set +# CONFIG_ARCH_R8A77970 is not set +# CONFIG_ARCH_R8A77980 is not set +# CONFIG_ARCH_R8A77990 is not set +# CONFIG_ARCH_R8A77995 is not set +# CONFIG_ARCH_R8A779A0 is not set +# CONFIG_ARCH_R8A779F0 is not set +# CONFIG_ARCH_R8A779G0 is not set +CONFIG_ARCH_R9A07G043=y +CONFIG_ARCH_R9A07G044=y +CONFIG_ARCH_R9A07G054=y +CONFIG_ARCH_R9A09G011=y +CONFIG_ARCH_RENESAS=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_ARCH_STACKWALK=y +CONFIG_ARCH_SUNXI=y +CONFIG_ARCH_SYNQUACER=y +CONFIG_ARCH_THUNDER=y +CONFIG_ARCH_THUNDER2=y +CONFIG_ARCH_VEXPRESS=y +CONFIG_ARCH_WANTS_NO_INSTR=y +CONFIG_ARCH_ZYNQMP=y +CONFIG_ARM64=y +CONFIG_ARM64_4K_PAGES=y +CONFIG_ARM64_AMU_EXTN=y +CONFIG_ARM64_BTI=y +CONFIG_ARM64_CNP=y +CONFIG_ARM64_CRYPTO=y +CONFIG_ARM64_E0PD=y +CONFIG_ARM64_EPAN=y +CONFIG_ARM64_ERRATUM_1024718=y +CONFIG_ARM64_ERRATUM_1165522=y +CONFIG_ARM64_ERRATUM_1286807=y +CONFIG_ARM64_ERRATUM_1319367=y +CONFIG_ARM64_ERRATUM_1418040=y +CONFIG_ARM64_ERRATUM_1463225=y +CONFIG_ARM64_ERRATUM_1508412=y +CONFIG_ARM64_ERRATUM_1530923=y +CONFIG_ARM64_ERRATUM_1542419=y +CONFIG_ARM64_ERRATUM_1742098=y +CONFIG_ARM64_ERRATUM_2051678=y +CONFIG_ARM64_ERRATUM_2054223=y +CONFIG_ARM64_ERRATUM_2067961=y +CONFIG_ARM64_ERRATUM_2077057=y +CONFIG_ARM64_ERRATUM_2441007=y +CONFIG_ARM64_ERRATUM_2441009=y +CONFIG_ARM64_ERRATUM_2457168=y +CONFIG_ARM64_ERRATUM_2658417=y +CONFIG_ARM64_ERRATUM_819472=y +CONFIG_ARM64_ERRATUM_824069=y +CONFIG_ARM64_ERRATUM_826319=y +CONFIG_ARM64_ERRATUM_827319=y +CONFIG_ARM64_ERRATUM_832075=y +CONFIG_ARM64_ERRATUM_834220=y +CONFIG_ARM64_ERRATUM_843419=y +CONFIG_ARM64_ERRATUM_845719=y +CONFIG_ARM64_HW_AFDBM=y +CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y +CONFIG_ARM64_MTE=y +CONFIG_ARM64_PAGE_SHIFT=12 +CONFIG_ARM64_PAN=y +CONFIG_ARM64_PA_BITS=48 +CONFIG_ARM64_PA_BITS_48=y +CONFIG_ARM64_PTR_AUTH=y +CONFIG_ARM64_PTR_AUTH_KERNEL=y +CONFIG_ARM64_RAS_EXTN=y +CONFIG_ARM64_SME=y +CONFIG_ARM64_SVE=y +CONFIG_ARM64_TAGGED_ADDR_ABI=y +CONFIG_ARM64_TLB_RANGE=y +CONFIG_ARM64_VA_BITS=48 +CONFIG_ARM64_VA_BITS_48=y +CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y +CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y +CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y +CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE=y +# CONFIG_ARMADA_37XX_RWTM_MBOX is not set +CONFIG_ARMADA_37XX_WATCHDOG=y +CONFIG_ARMADA_THERMAL=y +CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y +# CONFIG_ARM_DMC620_PMU is not set +# CONFIG_ARM_MHU_V2 is not set +CONFIG_ARM_PSCI_CPUIDLE=y +CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y +CONFIG_ARM_SBSA_WATCHDOG=y +CONFIG_ARM_SCPI_POWER_DOMAIN=y +CONFIG_ARM_SCPI_PROTOCOL=y +CONFIG_ARM_SMCCC_SOC_ID=y +CONFIG_ARM_SMC_WATCHDOG=y +CONFIG_ARM_SMMU=y +# CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT is not set +# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set +CONFIG_ARM_SMMU_V3=y +# CONFIG_ARM_SMMU_V3_PMU is not set +# CONFIG_ARM_SMMU_V3_SVA is not set +CONFIG_ATOMIC64_SELFTEST=y +CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y +# CONFIG_AXI_DMAC is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +# CONFIG_BCM2711_THERMAL is not set +CONFIG_BCM2835_MBOX=y +CONFIG_BCM2835_POWER=y +# CONFIG_BCM2835_THERMAL is not set +# CONFIG_BCM2835_VCHIQ is not set +CONFIG_BCM2835_WDT=y +# CONFIG_BCMASP is not set +# CONFIG_BCMGENET is not set +# CONFIG_BCM_CYGNUS_PHY is not set +# CONFIG_BCM_FLEXRM_MBOX is not set +# CONFIG_BCM_NS_THERMAL is not set +# CONFIG_BCM_PDC_MBOX is not set +# CONFIG_BCM_SR_THERMAL is not set +CONFIG_BCM_VIDEOCORE=y +# CONFIG_BGMAC_PLATFORM is not set +CONFIG_BLK_PM=y +# CONFIG_BRCMSTB_PM is not set +# CONFIG_BRCMSTB_THERMAL is not set +CONFIG_BRCM_USB_PINMAP=y +CONFIG_CAVIUM_ERRATUM_22375=y +CONFIG_CAVIUM_ERRATUM_23144=y +CONFIG_CAVIUM_ERRATUM_23154=y +CONFIG_CAVIUM_ERRATUM_27456=y +CONFIG_CAVIUM_ERRATUM_30115=y +CONFIG_CAVIUM_TX2_ERRATUM_219=y +CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y +CONFIG_CLK_BCM2711_DVP=y +CONFIG_CLK_BCM2835=y +CONFIG_CLK_BCM_NS2=y +CONFIG_CLK_BCM_SR=y +CONFIG_CLK_IMX8MM=y +CONFIG_CLK_IMX8MN=y +CONFIG_CLK_IMX8MP=y +CONFIG_CLK_IMX8MQ=y +CONFIG_CLK_IMX8QXP=y +CONFIG_CLK_IMX8ULP=y +CONFIG_CLK_IMX93=y +CONFIG_CLK_INTEL_SOCFPGA=y +CONFIG_CLK_INTEL_SOCFPGA64=y +CONFIG_CLK_LS1028A_PLLDIG=y +CONFIG_CLK_PX30=y +CONFIG_CLK_QORIQ=y +CONFIG_CLK_RASPBERRYPI=y +CONFIG_CLK_RCAR_USB2_CLOCK_SEL=y +CONFIG_CLK_RENESAS=y +CONFIG_CLK_RK3308=y +CONFIG_CLK_RK3328=y +CONFIG_CLK_RK3368=y +CONFIG_CLK_RK3399=y +CONFIG_CLK_RK3568=y +CONFIG_CLK_RK3588=y +CONFIG_CLK_SP810=y +CONFIG_CLK_SUNXI=y +CONFIG_CLK_SUNXI_CLOCKS=y +# CONFIG_CLK_SUNXI_PRCM_SUN6I is not set +# CONFIG_CLK_SUNXI_PRCM_SUN8I is not set +# CONFIG_CLK_SUNXI_PRCM_SUN9I is not set +CONFIG_CLK_VEXPRESS_OSC=y +CONFIG_CMA=y +CONFIG_CMA_ALIGNMENT=8 +CONFIG_CMA_AREAS=19 +# CONFIG_CMA_DEBUG is not set +# CONFIG_CMA_DEBUGFS is not set +CONFIG_CMA_SIZE_MBYTES=32 +# CONFIG_CMA_SIZE_SEL_MAX is not set +CONFIG_CMA_SIZE_SEL_MBYTES=y +# CONFIG_CMA_SIZE_SEL_MIN is not set +# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set +# CONFIG_CMA_SYSFS is not set +# CONFIG_COMMON_CLK_FSL_FLEXSPI is not set +# CONFIG_COMMON_CLK_FSL_SAI is not set +CONFIG_COMMON_CLK_HI3516CV300=y +CONFIG_COMMON_CLK_HI3519=y +CONFIG_COMMON_CLK_HI3559A=y +CONFIG_COMMON_CLK_HI3660=y +CONFIG_COMMON_CLK_HI3670=y +CONFIG_COMMON_CLK_HI3798CV200=y +CONFIG_COMMON_CLK_HI6220=y +CONFIG_COMMON_CLK_HI655X=y +CONFIG_COMMON_CLK_ROCKCHIP=y +CONFIG_COMMON_CLK_SCPI=y +CONFIG_COMMON_CLK_ZYNQMP=y +CONFIG_COMMON_RESET_HI3660=y +CONFIG_COMMON_RESET_HI6220=y +# CONFIG_COMPAT_32BIT_TIME is not set +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_MENU=y +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_CPU_PM=y +CONFIG_CRYPTO_AES_ARM64=y +CONFIG_CRYPTO_AES_ARM64_BS=y +CONFIG_CRYPTO_AES_ARM64_CE=y +CONFIG_CRYPTO_AES_ARM64_CE_BLK=y +CONFIG_CRYPTO_AES_ARM64_CE_CCM=y +CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y +CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y +CONFIG_CRYPTO_CHACHA20=y +CONFIG_CRYPTO_CHACHA20_NEON=y +CONFIG_CRYPTO_CRYPTD=y +# CONFIG_CRYPTO_DEV_ALLWINNER is not set +# CONFIG_CRYPTO_DEV_BCM_SPU is not set +# CONFIG_CRYPTO_DEV_FSL_DPAA2_CAAM is not set +# CONFIG_CRYPTO_DEV_HISI_HPRE is not set +# CONFIG_CRYPTO_DEV_HISI_SEC2 is not set +# CONFIG_CRYPTO_DEV_HISI_TRNG is not set +# CONFIG_CRYPTO_DEV_OCTEONTX2_CPT is not set +# CONFIG_CRYPTO_DEV_ROCKCHIP is not set +# CONFIG_CRYPTO_DEV_ZYNQMP_AES is not set +# CONFIG_CRYPTO_DEV_ZYNQMP_SHA3 is not set +CONFIG_CRYPTO_GHASH_ARM64_CE=y +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y +CONFIG_CRYPTO_POLYVAL_ARM64_CE=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA1_ARM64_CE=y +CONFIG_CRYPTO_SHA256_ARM64=y +CONFIG_CRYPTO_SHA2_ARM64_CE=y +CONFIG_CRYPTO_SHA512_ARM64=y +CONFIG_CRYPTO_SIMD=y +# CONFIG_CRYPTO_SM4_ARM64_CE_BLK is not set +# CONFIG_CRYPTO_SM4_ARM64_CE_CCM is not set +# CONFIG_CRYPTO_SM4_ARM64_CE_GCM is not set +# CONFIG_CRYPTO_SM4_ARM64_NEON_BLK is not set +# CONFIG_DEV_DAX_HMEM is not set +CONFIG_DMA_BCM2835=y +CONFIG_DMA_CMA=y +CONFIG_DMA_DIRECT_REMAP=y +# CONFIG_DMA_NUMA_CMA is not set +CONFIG_DMA_SHARED_BUFFER=y +CONFIG_DMA_SUN6I=y +CONFIG_DRM=y +CONFIG_DRM_BOCHS=y +CONFIG_DRM_BRIDGE=y +# CONFIG_DRM_FSL_LDB is not set +CONFIG_DRM_GEM_SHMEM_HELPER=y +# CONFIG_DRM_IMX8QM_LDB is not set +# CONFIG_DRM_IMX8QXP_LDB is not set +# CONFIG_DRM_IMX8QXP_PIXEL_COMBINER is not set +# CONFIG_DRM_IMX8QXP_PIXEL_LINK is not set +# CONFIG_DRM_IMX8QXP_PIXEL_LINK_TO_DPI is not set +# CONFIG_DRM_IMX_DCSS is not set +# CONFIG_DRM_IMX_LCDC is not set +CONFIG_DRM_KMS_HELPER=y +CONFIG_DRM_PANEL=y +CONFIG_DRM_PANEL_BRIDGE=y +# CONFIG_DRM_PANEL_HIMAX_HX8394 is not set +# CONFIG_DRM_PANEL_JADARD_JD9365DA_H3 is not set +# CONFIG_DRM_PANEL_NEWVISION_NV3051D is not set +# CONFIG_DRM_PANEL_NOVATEK_NT36523 is not set +CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y +# CONFIG_DRM_PANEL_SONY_TD4353_JDI is not set +# CONFIG_DRM_PANEL_STARTEK_KD070FHFID015 is not set +# CONFIG_DRM_PANEL_VISIONOX_R66451 is not set +# CONFIG_DRM_PANEL_VISIONOX_VTDR6130 is not set +CONFIG_DRM_QXL=y +# CONFIG_DRM_RCAR_DU is not set +# CONFIG_DRM_ROCKCHIP is not set +# CONFIG_DRM_RZG2L_MIPI_DSI is not set +# CONFIG_DRM_SHMOBILE is not set +CONFIG_DRM_TTM=y +CONFIG_DRM_TTM_HELPER=y +# CONFIG_DRM_V3D is not set +CONFIG_DRM_VIRTIO_GPU=y +CONFIG_DRM_VIRTIO_GPU_KMS=y +CONFIG_DRM_VRAM_HELPER=y +# CONFIG_DWMAC_SUN8I is not set +# CONFIG_DWMAC_SUNXI is not set +CONFIG_DW_WATCHDOG=y +CONFIG_EFI_CAPSULE_LOADER=y +CONFIG_EFI_CUSTOM_SSDT_OVERLAYS=y +CONFIG_EFI_SOFT_RESERVE=y +CONFIG_EFI_VARS_PSTORE=y +# CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE is not set +CONFIG_FB=y +CONFIG_FB_ARMCLCD=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_IMAGEBLIT=y +CONFIG_FB_CMDLINE=y +CONFIG_FB_MODE_HELPERS=y +CONFIG_FB_MX3=y +# CONFIG_FB_SH_MOBILE_LCDC is not set +# CONFIG_FB_XILINX is not set +CONFIG_FRAME_POINTER=y +# CONFIG_FSL_DPAA is not set +# CONFIG_FSL_DPAA2_QDMA is not set +CONFIG_FSL_ERRATUM_A008585=y +# CONFIG_FSL_IMX8_DDR_PMU is not set +# CONFIG_FSL_PQ_MDIO is not set +CONFIG_FUJITSU_ERRATUM_010001=y +CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y +CONFIG_GENERIC_CSUM=y +CONFIG_GENERIC_FIND_FIRST_BIT=y +# CONFIG_GIANFAR is not set +CONFIG_GPIO_BCM_XGS_IPROC=y +CONFIG_GPIO_BRCMSTB=y +CONFIG_GPIO_GENERIC=y +CONFIG_GPIO_GENERIC_PLATFORM=y +CONFIG_GPIO_MPC8XXX=y +CONFIG_GPIO_MXC=y +CONFIG_GPIO_RASPBERRYPI_EXP=y +CONFIG_GPIO_ROCKCHIP=y +CONFIG_GPIO_THUNDERX=y +CONFIG_GPIO_XLP=y +CONFIG_GPIO_ZYNQ=y +CONFIG_GPIO_ZYNQMP_MODEPIN=y +CONFIG_HDMI=y +CONFIG_HI3660_MBOX=y +CONFIG_HI6220_MBOX=y +CONFIG_HISILICON_ERRATUM_161600802=y +CONFIG_HISILICON_LPC=y +CONFIG_HISI_PMU=y +CONFIG_HISI_THERMAL=y +CONFIG_HOTPLUG_PCI=y +CONFIG_HOTPLUG_PCI_ACPI=y +# CONFIG_HOTPLUG_PCI_ACPI_IBM is not set +# CONFIG_HOTPLUG_PCI_CPCI is not set +# CONFIG_HOTPLUG_PCI_PCIE is not set +# CONFIG_HOTPLUG_PCI_SHPC is not set +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_ARM_SMCCC_TRNG=y +# CONFIG_HW_RANDOM_HISI is not set +# CONFIG_HW_RANDOM_HISTB is not set +CONFIG_HW_RANDOM_VIRTIO=y +CONFIG_I2C=y +CONFIG_I2C_ALGOBIT=y +CONFIG_I2C_ALTERA=y +# CONFIG_I2C_BCM2835 is not set +CONFIG_I2C_BOARDINFO=y +# CONFIG_I2C_HIX5HD2 is not set +CONFIG_I2C_IMX=y +CONFIG_I2C_IMX_LPI2C=y +CONFIG_I2C_RIIC=y +# CONFIG_I2C_RZV2M is not set +# CONFIG_I2C_SLAVE_TESTUNIT is not set +CONFIG_I2C_SYNQUACER=y +CONFIG_I2C_THUNDERX=y +# CONFIG_I2C_XLP9XX is not set +CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 +# CONFIG_IMX2_WDT is not set +# CONFIG_IMX8MM_THERMAL is not set +# CONFIG_IMX8QXP_ADC is not set +# CONFIG_IMX93_ADC is not set +# CONFIG_IMX_DMA is not set +# CONFIG_IMX_DSP is not set +CONFIG_IMX_INTMUX=y +CONFIG_IMX_IRQSTEER=y +CONFIG_IMX_MBOX=y +# CONFIG_IMX_MU_MSI is not set +CONFIG_IMX_SCU=y +CONFIG_IMX_SCU_PD=y +# CONFIG_IMX_SC_THERMAL is not set +# CONFIG_IMX_SC_WDT is not set +# CONFIG_IMX_SDMA is not set +# CONFIG_IMX_WEIM is not set +# CONFIG_INPUT_BBNSM_PWRKEY is not set +# CONFIG_INPUT_HISI_POWERKEY is not set +# CONFIG_INPUT_IBM_PANEL is not set +# CONFIG_INTEL_STRATIX10_RSU is not set +# CONFIG_INTEL_STRATIX10_SERVICE is not set +CONFIG_INTERCONNECT=y +CONFIG_INTERCONNECT_IMX=y +CONFIG_INTERCONNECT_IMX8MM=y +CONFIG_INTERCONNECT_IMX8MN=y +CONFIG_INTERCONNECT_IMX8MP=y +CONFIG_INTERCONNECT_IMX8MQ=y +# CONFIG_IOMMUFD is not set +# CONFIG_IOMMU_DEBUGFS is not set +# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set +CONFIG_IOMMU_DEFAULT_DMA_STRICT=y +CONFIG_IOMMU_DEFAULT_PASSTHROUGH=y +# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set +# CONFIG_IOMMU_IO_PGTABLE_DART is not set +# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set +CONFIG_IOMMU_SUPPORT=y +# CONFIG_IPMMU_VMSA is not set +# CONFIG_K3_DMA is not set +CONFIG_KCMP=y +# CONFIG_KEYBOARD_IMX_SC_KEY is not set +# CONFIG_KEYBOARD_SUN4I_LRADC is not set +CONFIG_KSM=y +# CONFIG_KUNPENG_HCCS is not set +CONFIG_KVM=y +CONFIG_LCD_CLASS_DEVICE=m +# CONFIG_LCD_PLATFORM is not set +# CONFIG_MAILBOX_TEST is not set +CONFIG_MARVELL_10G_PHY=y +# CONFIG_MARVELL_CN10K_DDR_PMU is not set +# CONFIG_MARVELL_CN10K_TAD_PMU is not set +# CONFIG_MARVELL_GTI_WDT is not set +CONFIG_MDIO_BCM_IPROC=y +CONFIG_MDIO_BUS_MUX_BCM_IPROC=y +CONFIG_MDIO_SUN4I=y +# CONFIG_MFD_ALTERA_A10SR is not set +CONFIG_MFD_ALTERA_SYSMGR=y +# CONFIG_MFD_AXP20X_RSB is not set +CONFIG_MFD_CORE=y +CONFIG_MFD_HI655X_PMIC=y +# CONFIG_MFD_KHADAS_MCU is not set +CONFIG_MFD_SUN4I_GPADC=y +# CONFIG_MFD_SUN6I_PRCM is not set +CONFIG_MFD_SYSCON=y +CONFIG_MFD_VEXPRESS_SYSREG=y +CONFIG_MMC=y +CONFIG_MMC_ARMMMCI=y +CONFIG_MMC_BCM2835=y +CONFIG_MMC_BLOCK=y +CONFIG_MMC_CAVIUM_THUNDERX=y +CONFIG_MMC_DW=y +# CONFIG_MMC_DW_BLUEFIELD is not set +# CONFIG_MMC_DW_EXYNOS is not set +# CONFIG_MMC_DW_HI3798CV200 is not set +# CONFIG_MMC_DW_K3 is not set +# CONFIG_MMC_DW_PCI is not set +CONFIG_MMC_DW_PLTFM=y +CONFIG_MMC_DW_ROCKCHIP=y +# CONFIG_MMC_MXC is not set +CONFIG_MMC_RICOH_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ACPI=y +CONFIG_MMC_SDHCI_CADENCE=y +CONFIG_MMC_SDHCI_ESDHC_IMX=y +CONFIG_MMC_SDHCI_IPROC=y +CONFIG_MMC_SDHCI_OF_ESDHC=y +CONFIG_MMC_SDHCI_PCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHI=y +CONFIG_MMC_SDHI_INTERNAL_DMAC=y +# CONFIG_MMC_SDHI_SYS_DMAC is not set +# CONFIG_MMC_SH_MMCIF is not set +CONFIG_MMC_SUNXI=y +CONFIG_MODULES_USE_ELF_RELA=y +# CONFIG_MVNETA is not set +# CONFIG_MVPP2 is not set +# CONFIG_MV_XOR is not set +# CONFIG_MX3_IPU is not set +CONFIG_MXC_CLK=y +CONFIG_MXC_CLK_SCU=y +# CONFIG_MXS_DMA is not set +CONFIG_NEED_SG_DMA_LENGTH=y +# CONFIG_NET_VENDOR_ALLWINNER is not set +CONFIG_NODES_SHIFT=4 +CONFIG_NOP_USB_XCEIV=y +CONFIG_NO_HZ=y +CONFIG_NO_HZ_COMMON=y +CONFIG_NO_HZ_IDLE=y +CONFIG_NR_CPUS=256 +CONFIG_NUMA=y +CONFIG_NUMA_BALANCING=y +CONFIG_NUMA_BALANCING_DEFAULT_ENABLED=y +# CONFIG_NVHE_EL2_DEBUG is not set +CONFIG_NVIDIA_CARMEL_CNP_ERRATUM=y +# CONFIG_NVMEM_IMX_IIM is not set +# CONFIG_NVMEM_IMX_OCOTP_ELE is not set +CONFIG_NVMEM_IMX_OCOTP_SCU=y +# CONFIG_NVMEM_LAYERSCAPE_SFP is not set +CONFIG_NVMEM_ROCKCHIP_EFUSE=y +# CONFIG_NVMEM_ROCKCHIP_OTP is not set +# CONFIG_NVMEM_SNVS_LPGPR is not set +# CONFIG_NVMEM_SUNXI_SID is not set +# CONFIG_NVMEM_ZYNQMP is not set +CONFIG_PCC=y +CONFIG_PCIEAER=y +CONFIG_PCIEASPM=y +CONFIG_PCIEASPM_DEFAULT=y +# CONFIG_PCIEASPM_PERFORMANCE is not set +# CONFIG_PCIEASPM_POWERSAVE is not set +# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set +CONFIG_PCIEPORTBUS=y +CONFIG_PCIE_ARMADA_8K=y +CONFIG_PCIE_BRCMSTB=y +CONFIG_PCIE_HISI_STB=y +CONFIG_PCIE_IPROC_MSI=y +CONFIG_PCIE_IPROC_PLATFORM=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_PCIE_MOBIVEIL_PLAT=y +# CONFIG_PCIE_RCAR_EP is not set +CONFIG_PCIE_RCAR_HOST=y +CONFIG_PCIE_ROCKCHIP=y +# CONFIG_PCIE_ROCKCHIP_DW_HOST is not set +CONFIG_PCIE_ROCKCHIP_HOST=y +CONFIG_PCIE_XILINX_CPM=y +CONFIG_PCIE_XILINX_NWL=y +CONFIG_PCI_AARDVARK=y +CONFIG_PCI_HISI=y +CONFIG_PCI_HOST_THUNDER_ECAM=y +CONFIG_PCI_HOST_THUNDER_PEM=y +CONFIG_PCI_IMX6=y +CONFIG_PCI_IMX6_HOST=y +CONFIG_PCI_IOV=y +CONFIG_PCI_LAYERSCAPE=y +CONFIG_PCI_PASID=y +# CONFIG_PCI_RCAR_GEN2 is not set +CONFIG_PHY_BCM_SR_PCIE=y +CONFIG_PHY_BCM_SR_USB=y +CONFIG_PHY_BRCM_SATA=y +CONFIG_PHY_BRCM_USB=y +CONFIG_PHY_FSL_IMX8M_PCIE=y +# CONFIG_PHY_FSL_LYNX_28G is not set +CONFIG_PHY_HI3660_USB=y +CONFIG_PHY_HI3670_PCIE=y +CONFIG_PHY_HI3670_USB=y +CONFIG_PHY_HI6220_USB=y +CONFIG_PHY_HISI_INNO_USB2=y +# CONFIG_PHY_HISTB_COMBPHY is not set +# CONFIG_PHY_MIXEL_LVDS_PHY is not set +CONFIG_PHY_MVEBU_A3700_COMPHY=y +CONFIG_PHY_MVEBU_A3700_UTMI=y +CONFIG_PHY_MVEBU_A38X_COMPHY=y +CONFIG_PHY_MVEBU_CP110_COMPHY=y +CONFIG_PHY_NS2_PCIE=y +CONFIG_PHY_NS2_USB_DRD=y +# CONFIG_PHY_R8A779F0_ETHERNET_SERDES is not set +# CONFIG_PHY_RCAR_GEN2 is not set +CONFIG_PHY_RCAR_GEN3_PCIE=y +CONFIG_PHY_RCAR_GEN3_USB2=y +CONFIG_PHY_RCAR_GEN3_USB3=y +# CONFIG_PHY_ROCKCHIP_DP is not set +# CONFIG_PHY_ROCKCHIP_DPHY_RX0 is not set +CONFIG_PHY_ROCKCHIP_EMMC=y +# CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY is not set +# CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY is not set +# CONFIG_PHY_ROCKCHIP_INNO_HDMI is not set +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +# CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY is not set +CONFIG_PHY_ROCKCHIP_PCIE=y +CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y +CONFIG_PHY_ROCKCHIP_TYPEC=y +# CONFIG_PHY_ROCKCHIP_USB is not set +CONFIG_PHY_SUN4I_USB=y +CONFIG_PHY_SUN50I_USB3=y +# CONFIG_PHY_SUN6I_MIPI_DPHY is not set +CONFIG_PHY_SUN9I_USB=y +# CONFIG_PHY_XILINX_ZYNQMP is not set +CONFIG_PINCTRL_IMX=y +CONFIG_PINCTRL_IMX8DXL=y +CONFIG_PINCTRL_IMX8MM=y +CONFIG_PINCTRL_IMX8MN=y +CONFIG_PINCTRL_IMX8MP=y +CONFIG_PINCTRL_IMX8MQ=y +CONFIG_PINCTRL_IMX8QM=y +CONFIG_PINCTRL_IMX8QXP=y +CONFIG_PINCTRL_IMX8ULP=y +CONFIG_PINCTRL_IMX93=y +# CONFIG_PINCTRL_IMXRT1050 is not set +# CONFIG_PINCTRL_IMXRT1170 is not set +CONFIG_PINCTRL_IMX_SCU=y +CONFIG_PINCTRL_IPROC_GPIO=y +CONFIG_PINCTRL_NS2_MUX=y +CONFIG_PINCTRL_ROCKCHIP=y +# CONFIG_PINCTRL_SUN20I_D1 is not set +CONFIG_PINCTRL_SUN4I_A10=y +CONFIG_PINCTRL_SUN50I_A100=y +CONFIG_PINCTRL_SUN50I_A100_R=y +CONFIG_PINCTRL_SUN50I_A64=y +CONFIG_PINCTRL_SUN50I_A64_R=y +CONFIG_PINCTRL_SUN50I_H5=y +CONFIG_PINCTRL_SUN50I_H6=y +CONFIG_PINCTRL_SUN50I_H616=y +CONFIG_PINCTRL_SUN50I_H616_R=y +CONFIG_PINCTRL_SUN50I_H6_R=y +CONFIG_PINCTRL_SUN5I=y +# CONFIG_PINCTRL_SUN6I_A31 is not set +# CONFIG_PINCTRL_SUN6I_A31_R is not set +# CONFIG_PINCTRL_SUN8I_A23 is not set +# CONFIG_PINCTRL_SUN8I_A23_R is not set +# CONFIG_PINCTRL_SUN8I_A33 is not set +# CONFIG_PINCTRL_SUN8I_A83T is not set +# CONFIG_PINCTRL_SUN8I_A83T_R is not set +# CONFIG_PINCTRL_SUN8I_H3 is not set +# CONFIG_PINCTRL_SUN8I_H3_R is not set +# CONFIG_PINCTRL_SUN8I_V3S is not set +# CONFIG_PINCTRL_SUN9I_A80 is not set +# CONFIG_PINCTRL_SUN9I_A80_R is not set +CONFIG_PINCTRL_ZYNQMP=y +CONFIG_PM=y +CONFIG_PM_CLK=y +CONFIG_PM_GENERIC_DOMAINS=y +CONFIG_PM_GENERIC_DOMAINS_OF=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_HISI=y +CONFIG_POWER_RESET_VEXPRESS=y +CONFIG_POWER_SUPPLY=y +# CONFIG_PTP_1588_CLOCK_DTE is not set +# CONFIG_PWM_BCM2835 is not set +CONFIG_QCOM_FALKOR_ERRATUM_1003=y +CONFIG_QCOM_FALKOR_ERRATUM_1009=y +CONFIG_QCOM_FALKOR_ERRATUM_E1041=y +CONFIG_QCOM_QDF2400_ERRATUM_0065=y +CONFIG_QORIQ_THERMAL=y +CONFIG_QUEUED_RWLOCKS=y +CONFIG_QUEUED_SPINLOCKS=y +CONFIG_RANDOMIZE_BASE=y +CONFIG_RANDOMIZE_MODULE_REGION_FULL=y +CONFIG_RANDSTRUCT_NONE=y +CONFIG_RASPBERRYPI_FIRMWARE=y +CONFIG_RASPBERRYPI_POWER=y +# CONFIG_RAVB is not set +CONFIG_RCAR_DMAC=y +# CONFIG_RCAR_GEN3_THERMAL is not set +# CONFIG_RCAR_THERMAL is not set +CONFIG_REGMAP=y +CONFIG_REGMAP_MMIO=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_ANATOP=y +CONFIG_REGULATOR_AXP20X=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_HI655X=y +CONFIG_REGULATOR_PFUZE100=y +# CONFIG_REGULATOR_VEXPRESS is not set +CONFIG_RELOCATABLE=y +# CONFIG_RENESAS_ETHER_SWITCH is not set +CONFIG_RENESAS_OSTM=y +# CONFIG_RENESAS_RZAWDT is not set +# CONFIG_RENESAS_RZG2LWDT is not set +# CONFIG_RENESAS_RZN1WDT is not set +CONFIG_RENESAS_USB_DMAC=y +# CONFIG_RENESAS_WDT is not set +# CONFIG_RESET_BRCMSTB is not set +CONFIG_RESET_IMX7=y +# CONFIG_RESET_RASPBERRYPI is not set +CONFIG_RESET_RZG2L_USBPHY_CTRL=y +CONFIG_ROCKCHIP_IODOMAIN=y +CONFIG_ROCKCHIP_IOMMU=y +# CONFIG_ROCKCHIP_MBOX is not set +CONFIG_ROCKCHIP_PM_DOMAINS=y +# CONFIG_ROCKCHIP_SARADC is not set +# CONFIG_ROCKCHIP_THERMAL is not set +CONFIG_RODATA_FULL_DEFAULT_ENABLED=y +# CONFIG_RTC_DRV_BBNSM is not set +# CONFIG_RTC_DRV_BRCMSTB is not set +# CONFIG_RTC_DRV_FSL_FTM_ALARM is not set +# CONFIG_RTC_DRV_IMXDI is not set +# CONFIG_RTC_DRV_IMX_SC is not set +CONFIG_RTC_DRV_MV=y +# CONFIG_RTC_DRV_MXC is not set +# CONFIG_RTC_DRV_MXC_V2 is not set +# CONFIG_RTC_DRV_SH is not set +CONFIG_RTC_I2C_AND_SPI=y +# CONFIG_RZG2L_ADC is not set +# CONFIG_RZG2L_THERMAL is not set +CONFIG_RZ_DMAC=y +CONFIG_RZ_MTU3=y +CONFIG_SATA_SIL24=y +# CONFIG_SCHED_CORE is not set +CONFIG_SCHED_MC=y +CONFIG_SCHED_SMT=y +# CONFIG_SENSORS_ARM_SCPI is not set +CONFIG_SERIAL_8250_BCM2835AUX=y +CONFIG_SERIAL_8250_BCM7271=y +# CONFIG_SERIAL_8250_EXAR is not set +CONFIG_SERIAL_8250_FSL=y +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_FSL_LINFLEXUART=y +CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE=y +CONFIG_SERIAL_FSL_LPUART=y +CONFIG_SERIAL_FSL_LPUART_CONSOLE=y +CONFIG_SERIAL_IMX=y +CONFIG_SERIAL_IMX_CONSOLE=y +CONFIG_SERIAL_IMX_EARLYCON=y +CONFIG_SERIAL_MVEBU_CONSOLE=y +CONFIG_SERIAL_MVEBU_UART=y +CONFIG_SERIAL_SAMSUNG=y +CONFIG_SERIAL_SAMSUNG_CONSOLE=y +CONFIG_SERIAL_SH_SCI=y +CONFIG_SERIAL_SH_SCI_CONSOLE=y +CONFIG_SERIAL_SH_SCI_DMA=y +CONFIG_SERIAL_SH_SCI_EARLYCON=y +CONFIG_SERIAL_SH_SCI_NR_UARTS=18 +# CONFIG_SMC91X is not set +# CONFIG_SND_SOC_RCAR is not set +# CONFIG_SND_SOC_RZ is not set +# CONFIG_SND_SOC_SH4_FSI is not set +# CONFIG_SND_SUN4I_I2S is not set +# CONFIG_SND_SUN50I_CODEC_ANALOG is not set +# CONFIG_SND_SUN50I_DMIC is not set +# CONFIG_SND_SUN8I_CODEC is not set +# CONFIG_SND_SUN8I_CODEC_ANALOG is not set +# CONFIG_SNI_NETSEC is not set +CONFIG_SOCIONEXT_SYNQUACER_PREITS=y +CONFIG_SOC_IMX8M=y +CONFIG_SOC_IMX9=y +CONFIG_SPARSEMEM=y +CONFIG_SPARSEMEM_EXTREME=y +CONFIG_SPARSEMEM_VMEMMAP=y +CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y +CONFIG_SPI_ARMADA_3700=y +# CONFIG_SPI_BCM2835 is not set +CONFIG_SPI_FSL_LPSPI=y +# CONFIG_SPI_FSL_QUADSPI is not set +# CONFIG_SPI_HISI_KUNPENG is not set +# CONFIG_SPI_HISI_SFC is not set +# CONFIG_SPI_HISI_SFC_V3XX is not set +CONFIG_SPI_IMX=y +# CONFIG_SPI_ROCKCHIP_SFC is not set +# CONFIG_SPI_RSPI is not set +# CONFIG_SPI_RZV2M_CSI is not set +# CONFIG_SPI_SH_HSPI is not set +# CONFIG_SPI_SH_MSIOF is not set +# CONFIG_SPI_SUN4I is not set +# CONFIG_SPI_SUN6I is not set +# CONFIG_SPI_SYNQUACER is not set +CONFIG_SPI_THUNDERX=y +# CONFIG_SPI_XLP is not set +# CONFIG_SSIF_IPMI_BMC is not set +CONFIG_STUB_CLK_HI3660=y +CONFIG_STUB_CLK_HI6220=y +# CONFIG_SUN20I_GPADC is not set +# CONFIG_SUN20I_PPU is not set +CONFIG_SUN50I_A100_CCU=y +CONFIG_SUN50I_A100_R_CCU=y +CONFIG_SUN50I_A64_CCU=y +CONFIG_SUN50I_H616_CCU=y +CONFIG_SUN50I_H6_CCU=y +CONFIG_SUN50I_H6_R_CCU=y +CONFIG_SUN50I_IOMMU=y +CONFIG_SUN6I_MSGBOX=y +CONFIG_SUN6I_RTC_CCU=y +# CONFIG_SUN8I_A83T_CCU is not set +CONFIG_SUN8I_DE2_CCU=y +# CONFIG_SUN8I_H3_CCU is not set +CONFIG_SUN8I_R_CCU=y +CONFIG_SUN8I_THERMAL=y +CONFIG_SUNXI_CCU=y +CONFIG_SUNXI_RSB=y +CONFIG_SUNXI_WATCHDOG=y +CONFIG_SYNC_FILE=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +# CONFIG_TCG_TIS_SYNQUACER is not set +CONFIG_THREAD_INFO_IN_TASK=y +# CONFIG_THUNDERX2_PMU is not set +CONFIG_TRANSPARENT_HUGEPAGE=y +CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y +# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set +# CONFIG_TURRIS_MOX_RWTM is not set +CONFIG_TYPEC=y +# CONFIG_TYPEC_ANX7411 is not set +# CONFIG_TYPEC_DP_ALTMODE is not set +# CONFIG_TYPEC_FUSB302 is not set +# CONFIG_TYPEC_HD3SS3220 is not set +# CONFIG_TYPEC_MUX_FSA4480 is not set +# CONFIG_TYPEC_MUX_GPIO_SBU is not set +# CONFIG_TYPEC_MUX_NB7VPQ904M is not set +# CONFIG_TYPEC_MUX_PI3USB30532 is not set +# CONFIG_TYPEC_RT1711H is not set +# CONFIG_TYPEC_RT1719 is not set +# CONFIG_TYPEC_STUSB160X is not set +CONFIG_TYPEC_TCPCI=y +# CONFIG_TYPEC_TCPCI_MAXIM is not set +CONFIG_TYPEC_TCPM=y +# CONFIG_TYPEC_TPS6598X is not set +# CONFIG_TYPEC_WUSB3801 is not set +# CONFIG_UACCE is not set +CONFIG_UNMAP_KERNEL_AT_EL0=y +# CONFIG_USB_BRCMSTB is not set +# CONFIG_USB_CDNS2_UDC is not set +CONFIG_USB_CHIPIDEA=y +CONFIG_USB_CHIPIDEA_GENERIC=y +CONFIG_USB_CHIPIDEA_HOST=y +CONFIG_USB_CHIPIDEA_IMX=y +CONFIG_USB_CHIPIDEA_PCI=y +CONFIG_USB_CHIPIDEA_UDC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_DUAL_ROLE=y +# CONFIG_USB_DWC3_GADGET is not set +CONFIG_USB_DWC3_HAPS=y +# CONFIG_USB_DWC3_HOST is not set +CONFIG_USB_DWC3_IMX8MP=y +# CONFIG_USB_DWC3_OF_SIMPLE is not set +CONFIG_USB_DWC3_PCI=y +# CONFIG_USB_DWC3_ULPI is not set +CONFIG_USB_DWC3_XILINX=y +CONFIG_USB_EHCI_FSL=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_HCD_ORION=y +CONFIG_USB_EHCI_HCD_PLATFORM=y +# CONFIG_USB_EMXX is not set +CONFIG_USB_GADGET=y +CONFIG_USB_MXS_PHY=y +CONFIG_USB_OHCI_EXYNOS=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_HCD_PCI=y +CONFIG_USB_OHCI_HCD_PLATFORM=y +CONFIG_USB_OTG=y +CONFIG_USB_OTG_FSM=y +CONFIG_USB_RENESAS_USB3=y +CONFIG_USB_RENESAS_USBF=y +CONFIG_USB_RENESAS_USBHS=y +CONFIG_USB_RENESAS_USBHS_HCD=y +CONFIG_USB_RENESAS_USBHS_UDC=y +CONFIG_USB_RZV2M_USB3DRD=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_HISTB=y +CONFIG_USB_XHCI_MVEBU=y +CONFIG_USB_XHCI_PLATFORM=y +# CONFIG_USB_XHCI_RCAR is not set +CONFIG_USB_XHCI_RZV2M=y +CONFIG_VEXPRESS_CONFIG=y +# CONFIG_VFIO_AMBA is not set +CONFIG_VIDEOMODE_HELPERS=y +# CONFIG_VIDEO_IMX7_CSI is not set +# CONFIG_VIDEO_IMX8MQ_MIPI_CSI2 is not set +# CONFIG_VIDEO_IMX8_ISI is not set +# CONFIG_VIDEO_RZG2L_CRU is not set +# CONFIG_VIDEO_RZG2L_CSI2 is not set +CONFIG_VIRTIO_DMA_SHARED_BUFFER=y +# CONFIG_VIRTIO_IOMMU is not set +CONFIG_VIRTUALIZATION=y +CONFIG_VMAP_STACK=y +CONFIG_WDAT_WDT=y +# CONFIG_XILINX_AMS is not set +# CONFIG_XILINX_INTC is not set +CONFIG_XLNX_EVENT_MANAGER=y +CONFIG_ZONE_DMA32=y +CONFIG_ZYNQMP_FIRMWARE=y +# CONFIG_ZYNQMP_FIRMWARE_DEBUG is not set +CONFIG_ZYNQMP_PM_DOMAINS=y +CONFIG_ZYNQMP_POWER=y diff --git a/target/linux/armsr/base-files/etc/board.d/03_gpio_switches b/target/linux/armsr/base-files/etc/board.d/03_gpio_switches index cf07bc0f54fbc0..72f310277ae311 100644 --- a/target/linux/armsr/base-files/etc/board.d/03_gpio_switches +++ b/target/linux/armsr/base-files/etc/board.d/03_gpio_switches @@ -3,18 +3,26 @@ . /lib/functions/uci-defaults.sh +KERNEL_MAJOR=$(uname -r | awk -F '.' '{print $1}') +KERNEL_MINOR=$(uname -r | awk -F '.' '{print $2}') + board_config_update board=$(board_name) case "$board" in traverse,ten64) - ucidef_add_gpio_switch "lte_reset" "Cell Modem Reset" "376" - ucidef_add_gpio_switch "lte_power" "Cell Modem Power" "377" - ucidef_add_gpio_switch "lte_disable" "Cell Modem Airplane mode" "378" - ucidef_add_gpio_switch "gnss_disable" "Cell Modem Disable GNSS receiver" "379" - ucidef_add_gpio_switch "lower_sfp_txidsable" "Lower SFP+ TX Disable" "369" - ucidef_add_gpio_switch "upper_sfp_txdisable" "Upper SFP+ TX Disable" "373" + if [ "${KERNEL_MAJOR}" -ge "6" ] && [ "${KERNEL_MINOR}" -ge "6" ]; then + I2C_GPIO_BASE=640 + else + I2C_GPIO_BASE=368 + fi + ucidef_add_gpio_switch "lte_reset" "Cell Modem Reset" "$(($I2C_GPIO_BASE + 8))" + ucidef_add_gpio_switch "lte_power" "Cell Modem Power" "$(($I2C_GPIO_BASE + 9))" + ucidef_add_gpio_switch "lte_disable" "Cell Modem Airplane mode" "$((I2C_GPIO_BASE + 10))" + ucidef_add_gpio_switch "gnss_disable" "Cell Modem Disable GNSS receiver" "$(($I2C_GPIO_BASE + 11))" + ucidef_add_gpio_switch "lower_sfp_txidsable" "Lower SFP+ TX Disable" "$(($I2C_GPIO_BASE + 1))" + ucidef_add_gpio_switch "upper_sfp_txdisable" "Upper SFP+ TX Disable" "$(($I2C_GPIO_BASE + 5))" ;; esac diff --git a/target/linux/armsr/base-files/etc/uci-defaults/05-migrate-ten64-gpio b/target/linux/armsr/base-files/etc/uci-defaults/05-migrate-ten64-gpio new file mode 100644 index 00000000000000..dc8648e57059ab --- /dev/null +++ b/target/linux/armsr/base-files/etc/uci-defaults/05-migrate-ten64-gpio @@ -0,0 +1,37 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-2.0-or-later + +# This script migrates GPIO switch pin numbers +# from kernel versions prior to 6.6 +# See https://lists.openwrt.org/pipermail/openwrt-devel/2024-March/042448.html + +. /lib/functions.sh + +ten64_update_gpioswitch_num() { + local section="$1" + config_get gpio_pin "${section}" gpio_pin + config_get gpio_name "${section}" name + if [ -z "${gpio_pin}" ]; then + return + fi + local this_pin_name=$(uci get "system.${section}.name") + if [ "${gpio_pin}" -lt 640 ]; then + new_pin_value=$(( $gpio_pin + 272 )) + uci set "system.${section}.gpio_pin=${new_pin_value}" + fi +} + +board=$(board_name) +if [ "${board}" != "traverse,ten64" ]; then + exit 0 +fi + +KERNEL_MINOR=$(uname -r | awk -F '.' '{print $2}') +if [ "${KERNEL_MINOR}" -lt "6" ]; then + exit 0 +fi + +config_load system +config_foreach ten64_update_gpioswitch_num gpio_switch + +exit 0 \ No newline at end of file diff --git a/target/linux/armsr/config-6.6 b/target/linux/armsr/config-6.6 new file mode 100644 index 00000000000000..8b4f291c9f908d --- /dev/null +++ b/target/linux/armsr/config-6.6 @@ -0,0 +1,338 @@ +CONFIG_64BIT=y +CONFIG_9P_FS=y +# CONFIG_9P_FS_POSIX_ACL is not set +# CONFIG_9P_FS_SECURITY is not set +# CONFIG_A64FX_DIAG is not set +CONFIG_ACPI=y +CONFIG_ACPI_AC=y +CONFIG_ACPI_APEI=y +CONFIG_ACPI_APEI_EINJ=y +# CONFIG_ACPI_APEI_ERST_DEBUG is not set +CONFIG_ACPI_APEI_GHES=y +CONFIG_ACPI_APEI_MEMORY_FAILURE=y +CONFIG_ACPI_APEI_PCIEAER=y +CONFIG_ACPI_BATTERY=y +# CONFIG_ACPI_BGRT is not set +CONFIG_ACPI_BUTTON=y +CONFIG_ACPI_CCA_REQUIRED=y +CONFIG_ACPI_CONTAINER=y +CONFIG_ACPI_CPPC_CPUFREQ=y +# CONFIG_ACPI_DEBUG is not set +# CONFIG_ACPI_DEBUGGER is not set +# CONFIG_ACPI_DOCK is not set +# CONFIG_ACPI_EC_DEBUGFS is not set +CONFIG_ACPI_FAN=y +CONFIG_ACPI_GENERIC_GSI=y +CONFIG_ACPI_GTDT=y +CONFIG_ACPI_HOTPLUG_CPU=y +CONFIG_ACPI_I2C_OPREGION=y +CONFIG_ACPI_IORT=y +CONFIG_ACPI_MCFG=y +# CONFIG_ACPI_PCI_SLOT is not set +# CONFIG_ACPI_PFRUT is not set +CONFIG_ACPI_PPTT=y +CONFIG_ACPI_PRMT=y +CONFIG_ACPI_PROCESSOR=y +CONFIG_ACPI_PROCESSOR_IDLE=y +CONFIG_ACPI_REDUCED_HARDWARE_ONLY=y +CONFIG_ACPI_SPCR_TABLE=y +CONFIG_ACPI_THERMAL=y +# CONFIG_ACPI_TINY_POWER_BUTTON is not set +# CONFIG_ALIBABA_UNCORE_DRW_PMU is not set +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_KEEP_MEMBLOCK=y +CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y +CONFIG_ARCH_MMAP_RND_BITS=18 +CONFIG_ARCH_MMAP_RND_BITS_MAX=24 +CONFIG_ARCH_MMAP_RND_BITS_MIN=18 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 +CONFIG_ARCH_PROC_KCORE_TEXT=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_STACKWALK=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_WANTS_NO_INSTR=y +CONFIG_ARM64=y +CONFIG_ARM64_4K_PAGES=y +# CONFIG_ARM64_ACPI_PARKING_PROTOCOL is not set +CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y +CONFIG_ARM64_PAGE_SHIFT=12 +CONFIG_ARM64_PA_BITS=48 +CONFIG_ARM64_PA_BITS_48=y +CONFIG_ARM64_TAGGED_ADDR_ABI=y +CONFIG_ARM64_VA_BITS=39 +CONFIG_ARM64_VA_BITS_39=y +CONFIG_ARM_AMBA=y +CONFIG_ARM_ARCH_TIMER=y +CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y +CONFIG_ARM_GIC=y +CONFIG_ARM_GIC_V2M=y +CONFIG_ARM_GIC_V3=y +CONFIG_ARM_GIC_V3_ITS=y +CONFIG_ARM_GIC_V3_ITS_PCI=y +CONFIG_ARM_PSCI_FW=y +# CONFIG_ARM_SMMU_V3_PMU is not set +CONFIG_ATA=y +CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y +CONFIG_BALLOON_COMPACTION=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_NVME=y +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_MQ_PCI=y +CONFIG_BLK_MQ_VIRTIO=y +CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_COMMON_CLK=y +# CONFIG_COMPAT_32BIT_TIME is not set +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_LADDER=y +CONFIG_CPU_PM=y +CONFIG_CPU_RMAP=y +CONFIG_CRC16=y +CONFIG_CRYPTO_CRC32=y +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_RNG2=y +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DMADEVICES=y +CONFIG_DMA_ACPI=y +CONFIG_DMA_DIRECT_REMAP=y +CONFIG_DMA_ENGINE=y +CONFIG_DMA_OF=y +CONFIG_DMA_REMAP=y +CONFIG_DMI=y +CONFIG_DMIID=y +CONFIG_DMI_SYSFS=y +CONFIG_DTC=y +CONFIG_EDAC_SUPPORT=y +CONFIG_EFI=y +CONFIG_EFIVAR_FS=y +CONFIG_EFI_ARMSTUB_DTB_LOADER=y +# CONFIG_EFI_BOOTLOADER_CONTROL is not set +# CONFIG_EFI_CAPSULE_LOADER is not set +# CONFIG_EFI_COCO_SECRET is not set +# CONFIG_EFI_CUSTOM_SSDT_OVERLAYS is not set +# CONFIG_EFI_DISABLE_PCI_DMA is not set +# CONFIG_EFI_DISABLE_RUNTIME is not set +CONFIG_EFI_EARLYCON=y +CONFIG_EFI_ESRT=y +CONFIG_EFI_GENERIC_STUB=y +# CONFIG_EFI_GENERIC_STUB_INITRD_CMDLINE_LOADER is not set +CONFIG_EFI_PARAMS_FROM_FDT=y +CONFIG_EFI_RUNTIME_WRAPPERS=y +CONFIG_EFI_STUB=y +# CONFIG_EFI_TEST is not set +# CONFIG_EFI_ZBOOT is not set +CONFIG_EXT4_FS=y +CONFIG_F2FS_FS=y +CONFIG_FAILOVER=y +CONFIG_FB_EFI=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_FONT_8x16=y +CONFIG_FONT_AUTOSELECT=y +CONFIG_FONT_SUPPORT=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +CONFIG_FRAME_POINTER=y +CONFIG_FS_IOMAP=y +CONFIG_FS_MBCACHE=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_ARCH_TOPOLOGY=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_CPU_VULNERABILITIES=y +CONFIG_GENERIC_CSUM=y +CONFIG_GENERIC_EARLY_IOREMAP=y +CONFIG_GENERIC_FIND_FIRST_BIT=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_MIGRATION=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_GENERIC_MSI_IRQ_DOMAIN=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GPIOLIB_IRQCHIP=y +CONFIG_GPIO_ACPI=y +CONFIG_GPIO_CDEV=y +# CONFIG_GPIO_HISI is not set +CONFIG_GPIO_PL061=y +# CONFIG_GPIO_VF610 is not set +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HID=y +CONFIG_HID_GENERIC=y +CONFIG_HID_SUPPORT=y +CONFIG_HOTPLUG_CPU=y +CONFIG_HOTPLUG_PCI_ACPI=y +CONFIG_HVC_DRIVER=y +CONFIG_HZ_PERIODIC=y +# CONFIG_I2C_AMD_MP2 is not set +CONFIG_I2C_HID_ACPI=y +# CONFIG_I2C_HISI is not set +# CONFIG_I2C_SLAVE_TESTUNIT is not set +CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 +# CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT is not set +CONFIG_INITRAMFS_SOURCE="" +CONFIG_INPUT_KEYBOARD=y +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_WORK=y +# CONFIG_ISCSI_IBFT is not set +CONFIG_JBD2=y +CONFIG_LIBFDT=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_MEMFD_CREATE=y +CONFIG_MEMORY_BALLOON=y +CONFIG_MIGRATION=y +# CONFIG_MLXBF_GIGE is not set +CONFIG_MMC_SDHCI_ACPI=y +CONFIG_MODULES_USE_ELF_RELA=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_MVMDIO=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_SG_DMA_LENGTH=y +CONFIG_NET_9P=y +# CONFIG_NET_9P_DEBUG is not set +# CONFIG_NET_9P_FD is not set +CONFIG_NET_9P_VIRTIO=y +CONFIG_NET_FAILOVER=y +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NLS=y +CONFIG_NR_CPUS=256 +CONFIG_NVMEM=y +CONFIG_NVME_CORE=y +# CONFIG_NVME_MULTIPATH is not set +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_PADATA=y +CONFIG_PAGE_REPORTING=y +CONFIG_PARTITION_PERCPU=y +CONFIG_PCI=y +# CONFIG_PCIE_HISI_ERR is not set +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_DOMAINS_GENERIC=y +CONFIG_PCI_ECAM=y +CONFIG_PCI_HOST_COMMON=y +CONFIG_PCI_HOST_GENERIC=y +CONFIG_PCI_LABEL=y +CONFIG_PCI_MSI=y +CONFIG_PCI_MSI_IRQ_DOMAIN=y +CONFIG_PGTABLE_LEVELS=3 +CONFIG_PHYS_ADDR_T_64BIT=y +# CONFIG_PMIC_OPREGION is not set +CONFIG_PNP=y +CONFIG_PNPACPI=y +CONFIG_PNP_DEBUG_MESSAGES=y +CONFIG_POWER_RESET=y +CONFIG_POWER_SUPPLY=y +CONFIG_PTP_1588_CLOCK_OPTIONAL=y +CONFIG_QUEUED_RWLOCKS=y +CONFIG_QUEUED_SPINLOCKS=y +CONFIG_RATIONAL=y +# CONFIG_RESET_ATTACK_MITIGATION is not set +CONFIG_RFS_ACCEL=y +CONFIG_RODATA_FULL_DEFAULT_ENABLED=y +CONFIG_RPS=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_EFI=y +CONFIG_RTC_DRV_PL031=y +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_SATA_AHCI=y +CONFIG_SATA_AHCI_PLATFORM=y +CONFIG_SATA_HOST=y +CONFIG_SCSI=y +CONFIG_SCSI_COMMON=y +CONFIG_SCSI_VIRTIO=y +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_FSL=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_PNP=y +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIAL_8250_SHARE_IRQ=y +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +CONFIG_SERIAL_EARLYCON=y +CONFIG_SERIAL_MCTRL_GPIO=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SG_POOL=y +CONFIG_SMP=y +CONFIG_SOCK_RX_QUEUE_MAPPING=y +CONFIG_SPARSEMEM=y +CONFIG_SPARSEMEM_EXTREME=y +CONFIG_SPARSEMEM_VMEMMAP=y +CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y +CONFIG_SPARSE_IRQ=y +CONFIG_SRCU=y +# CONFIG_SURFACE_PLATFORMS is not set +CONFIG_SWIOTLB=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +CONFIG_SYSFB=y +# CONFIG_SYSFB_SIMPLEFB is not set +CONFIG_THERMAL=y +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y +CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 +CONFIG_THERMAL_GOV_STEP_WISE=y +CONFIG_THERMAL_OF=y +CONFIG_THREAD_INFO_IN_TASK=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_ACPI=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_TREE_RCU=y +CONFIG_TREE_SRCU=y +# CONFIG_UACCE is not set +CONFIG_UCS2_STRING=y +CONFIG_UNMAP_KERNEL_AT_EL0=y +CONFIG_USB=y +CONFIG_USB_HID=y +CONFIG_USB_HIDDEV=y +CONFIG_USB_PCI=y +CONFIG_USB_STORAGE=y +CONFIG_USB_SUPPORT=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_PCI=y +CONFIG_VIRTIO=y +CONFIG_VIRTIO_BALLOON=y +CONFIG_VIRTIO_BLK=y +CONFIG_VIRTIO_CONSOLE=y +CONFIG_VIRTIO_MMIO=y +CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y +CONFIG_VIRTIO_NET=y +CONFIG_VIRTIO_PCI=y +CONFIG_VIRTIO_PCI_LEGACY=y +CONFIG_VIRTIO_PCI_LIB=y +CONFIG_VMAP_STACK=y +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_WATCHDOG_CORE=y +CONFIG_XPS=y +CONFIG_ZONE_DMA32=y diff --git a/target/linux/armsr/modules.mk b/target/linux/armsr/modules.mk index 7dd3739ffaec9d..d5a5d5c407f86f 100644 --- a/target/linux/armsr/modules.mk +++ b/target/linux/armsr/modules.mk @@ -92,6 +92,7 @@ define KernelPackage/fsl-enetc-net CONFIG_FSL_ENETC_QOS=y FILES:= \ $(LINUX_DIR)/drivers/net/ethernet/freescale/enetc/fsl-enetc.ko \ + $(LINUX_DIR)/drivers/net/ethernet/freescale/enetc/fsl-enetc-core.ko@ge6.3 \ $(LINUX_DIR)/drivers/net/ethernet/freescale/enetc/fsl-enetc-vf.ko \ $(LINUX_DIR)/drivers/net/ethernet/freescale/enetc/fsl-enetc-mdio.ko \ $(LINUX_DIR)/drivers/net/ethernet/freescale/enetc/fsl-enetc-ierb.ko diff --git a/target/linux/armsr/patches-6.6/221-armsr-disable_gc_sections_armv7.patch b/target/linux/armsr/patches-6.6/221-armsr-disable_gc_sections_armv7.patch new file mode 100644 index 00000000000000..c9dbdf25212ff8 --- /dev/null +++ b/target/linux/armsr/patches-6.6/221-armsr-disable_gc_sections_armv7.patch @@ -0,0 +1,23 @@ +From b77c0ecdc7915e5c5c515da1aa6cfaf6f4eb8351 Mon Sep 17 00:00:00 2001 +From: Mathew McBride +Date: Wed, 28 Sep 2022 16:39:31 +1000 +Subject: [PATCH] arm: disable code size reduction measures + (gc-sections,-f*-sections) + +This interferes with the EFI boot stub on armv7l. + +Signed-off-by: Mathew McBride +--- + arch/arm/Kconfig | 1 - + 1 file changed, 1 deletion(-) + +--- a/arch/arm/Kconfig ++++ b/arch/arm/Kconfig +@@ -128,7 +128,6 @@ config ARM + select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU + select IRQ_FORCED_THREADING + select LOCK_MM_AND_FIND_VMA +- select HAVE_LD_DEAD_CODE_DATA_ELIMINATION + select MODULES_USE_ELF_REL + select NEED_DMA_MAP_STATE + select OF_EARLY_FLATTREE if OF diff --git a/target/linux/generic/backport-6.1/301-v6.9-kernel.h-removed-REPEAT_BYTE-from-kernel.h.patch b/target/linux/generic/backport-6.1/301-v6.9-kernel.h-removed-REPEAT_BYTE-from-kernel.h.patch new file mode 100644 index 00000000000000..239adff1af7d4d --- /dev/null +++ b/target/linux/generic/backport-6.1/301-v6.9-kernel.h-removed-REPEAT_BYTE-from-kernel.h.patch @@ -0,0 +1,161 @@ +From 66a5c40f60f5d88ad8d47ba6a4ba05892853fa1f Mon Sep 17 00:00:00 2001 +From: Tanzir Hasan +Date: Tue, 26 Dec 2023 18:00:00 +0000 +Subject: [PATCH] kernel.h: removed REPEAT_BYTE from kernel.h + +This patch creates wordpart.h and includes it in asm/word-at-a-time.h +for all architectures. WORD_AT_A_TIME_CONSTANTS depends on kernel.h +because of REPEAT_BYTE. Moving this to another header and including it +where necessary allows us to not include the bloated kernel.h. Making +this implicit dependency on REPEAT_BYTE explicit allows for later +improvements in the lib/string.c inclusion list. + +Suggested-by: Al Viro +Suggested-by: Andy Shevchenko +Signed-off-by: Tanzir Hasan +Reviewed-by: Andy Shevchenko +Link: https://lore.kernel.org/r/20231226-libstringheader-v6-1-80aa08c7652c@google.com +Signed-off-by: Kees Cook +--- + arch/arm/include/asm/word-at-a-time.h | 3 ++- + arch/arm64/include/asm/word-at-a-time.h | 3 ++- + arch/powerpc/include/asm/word-at-a-time.h | 4 ++-- + arch/riscv/include/asm/word-at-a-time.h | 3 ++- + arch/s390/include/asm/word-at-a-time.h | 3 ++- + arch/sh/include/asm/word-at-a-time.h | 2 ++ + arch/x86/include/asm/word-at-a-time.h | 3 ++- + arch/x86/kvm/mmu/mmu.c | 1 + + fs/namei.c | 2 +- + include/asm-generic/word-at-a-time.h | 3 ++- + include/linux/kernel.h | 8 -------- + include/linux/wordpart.h | 13 +++++++++++++ + 12 files changed, 31 insertions(+), 17 deletions(-) + create mode 100644 include/linux/wordpart.h + +--- a/arch/arm/include/asm/word-at-a-time.h ++++ b/arch/arm/include/asm/word-at-a-time.h +@@ -8,7 +8,8 @@ + * Little-endian word-at-a-time zero byte handling. + * Heavily based on the x86 algorithm. + */ +-#include ++#include ++#include + + struct word_at_a_time { + const unsigned long one_bits, high_bits; +--- a/arch/arm64/include/asm/word-at-a-time.h ++++ b/arch/arm64/include/asm/word-at-a-time.h +@@ -9,7 +9,8 @@ + + #ifndef __AARCH64EB__ + +-#include ++#include ++#include + + struct word_at_a_time { + const unsigned long one_bits, high_bits; +--- a/arch/powerpc/include/asm/word-at-a-time.h ++++ b/arch/powerpc/include/asm/word-at-a-time.h +@@ -4,8 +4,8 @@ + /* + * Word-at-a-time interfaces for PowerPC. + */ +- +-#include ++#include ++#include + #include + #include + +--- a/arch/sh/include/asm/word-at-a-time.h ++++ b/arch/sh/include/asm/word-at-a-time.h +@@ -5,6 +5,8 @@ + #ifdef CONFIG_CPU_BIG_ENDIAN + # include + #else ++#include ++#include + /* + * Little-endian version cribbed from x86. + */ +--- a/arch/x86/include/asm/word-at-a-time.h ++++ b/arch/x86/include/asm/word-at-a-time.h +@@ -2,7 +2,8 @@ + #ifndef _ASM_WORD_AT_A_TIME_H + #define _ASM_WORD_AT_A_TIME_H + +-#include ++#include ++#include + + /* + * This is largely generic for little-endian machines, but the +--- a/arch/x86/kvm/mmu/mmu.c ++++ b/arch/x86/kvm/mmu/mmu.c +@@ -44,6 +44,7 @@ + #include + #include + #include ++#include + + #include + #include +--- a/fs/namei.c ++++ b/fs/namei.c +@@ -17,8 +17,8 @@ + + #include + #include +-#include + #include ++#include + #include + #include + #include +--- a/include/asm-generic/word-at-a-time.h ++++ b/include/asm-generic/word-at-a-time.h +@@ -2,7 +2,8 @@ + #ifndef _ASM_WORD_AT_A_TIME_H + #define _ASM_WORD_AT_A_TIME_H + +-#include ++#include ++#include + #include + + #ifdef __BIG_ENDIAN +--- a/include/linux/kernel.h ++++ b/include/linux/kernel.h +@@ -36,14 +36,6 @@ + + #define STACK_MAGIC 0xdeadbeef + +-/** +- * REPEAT_BYTE - repeat the value @x multiple times as an unsigned long value +- * @x: value to repeat +- * +- * NOTE: @x is not checked for > 0xff; larger values produce odd results. +- */ +-#define REPEAT_BYTE(x) ((~0ul / 0xff) * (x)) +- + /* generic data direction definitions */ + #define READ 0 + #define WRITE 1 +--- /dev/null ++++ b/include/linux/wordpart.h +@@ -0,0 +1,13 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++ ++#ifndef _LINUX_WORDPART_H ++#define _LINUX_WORDPART_H ++/** ++ * REPEAT_BYTE - repeat the value @x multiple times as an unsigned long value ++ * @x: value to repeat ++ * ++ * NOTE: @x is not checked for > 0xff; larger values produce odd results. ++ */ ++#define REPEAT_BYTE(x) ((~0ul / 0xff) * (x)) ++ ++#endif // _LINUX_WORDPART_H diff --git a/target/linux/generic/backport-6.1/302-v6.9-kernel.h-Move-upper_-_bits-and-lower_-_bits-to-wordp.patch b/target/linux/generic/backport-6.1/302-v6.9-kernel.h-Move-upper_-_bits-and-lower_-_bits-to-wordp.patch new file mode 100644 index 00000000000000..9bbd515852d597 --- /dev/null +++ b/target/linux/generic/backport-6.1/302-v6.9-kernel.h-Move-upper_-_bits-and-lower_-_bits-to-wordp.patch @@ -0,0 +1,107 @@ +From adeb04362d74188c1e22ccb824b15a0a7b3de2f4 Mon Sep 17 00:00:00 2001 +From: Andy Shevchenko +Date: Wed, 14 Feb 2024 19:26:32 +0200 +Subject: [PATCH] kernel.h: Move upper_*_bits() and lower_*_bits() to + wordpart.h + +The wordpart.h header is collecting APIs related to the handling +parts of the word (usually in byte granularity). The upper_*_bits() +and lower_*_bits() are good candidates to be moved to there. + +This helps to clean up header dependency hell with regard to kernel.h +as the latter gathers completely unrelated stuff together and slows +down compilation (especially when it's included into other header). + +Signed-off-by: Andy Shevchenko +Link: https://lore.kernel.org/r/20240214172752.3605073-1-andriy.shevchenko@linux.intel.com +Reviewed-by: Randy Dunlap +Signed-off-by: Kees Cook +--- + include/linux/kernel.h | 30 ++---------------------------- + include/linux/wordpart.h | 29 +++++++++++++++++++++++++++++ + 2 files changed, 31 insertions(+), 28 deletions(-) + +--- a/include/linux/kernel.h ++++ b/include/linux/kernel.h +@@ -30,6 +30,8 @@ + #include + #include + #include ++#include ++ + #include + + #include +@@ -55,34 +57,6 @@ + } \ + ) + +-/** +- * upper_32_bits - return bits 32-63 of a number +- * @n: the number we're accessing +- * +- * A basic shift-right of a 64- or 32-bit quantity. Use this to suppress +- * the "right shift count >= width of type" warning when that quantity is +- * 32-bits. +- */ +-#define upper_32_bits(n) ((u32)(((n) >> 16) >> 16)) +- +-/** +- * lower_32_bits - return bits 0-31 of a number +- * @n: the number we're accessing +- */ +-#define lower_32_bits(n) ((u32)((n) & 0xffffffff)) +- +-/** +- * upper_16_bits - return bits 16-31 of a number +- * @n: the number we're accessing +- */ +-#define upper_16_bits(n) ((u16)((n) >> 16)) +- +-/** +- * lower_16_bits - return bits 0-15 of a number +- * @n: the number we're accessing +- */ +-#define lower_16_bits(n) ((u16)((n) & 0xffff)) +- + struct completion; + struct user; + +--- a/include/linux/wordpart.h ++++ b/include/linux/wordpart.h +@@ -2,6 +2,35 @@ + + #ifndef _LINUX_WORDPART_H + #define _LINUX_WORDPART_H ++ ++/** ++ * upper_32_bits - return bits 32-63 of a number ++ * @n: the number we're accessing ++ * ++ * A basic shift-right of a 64- or 32-bit quantity. Use this to suppress ++ * the "right shift count >= width of type" warning when that quantity is ++ * 32-bits. ++ */ ++#define upper_32_bits(n) ((u32)(((n) >> 16) >> 16)) ++ ++/** ++ * lower_32_bits - return bits 0-31 of a number ++ * @n: the number we're accessing ++ */ ++#define lower_32_bits(n) ((u32)((n) & 0xffffffff)) ++ ++/** ++ * upper_16_bits - return bits 16-31 of a number ++ * @n: the number we're accessing ++ */ ++#define upper_16_bits(n) ((u16)((n) >> 16)) ++ ++/** ++ * lower_16_bits - return bits 0-15 of a number ++ * @n: the number we're accessing ++ */ ++#define lower_16_bits(n) ((u16)((n) & 0xffff)) ++ + /** + * REPEAT_BYTE - repeat the value @x multiple times as an unsigned long value + * @x: value to repeat diff --git a/target/linux/generic/backport-6.1/790-69-v6.10-net-dsa-mt7530-do-not-set-MT7530_P5_DIS-when-PHY-.patch b/target/linux/generic/backport-6.1/790-69-v6.10-net-dsa-mt7530-do-not-set-MT7530_P5_DIS-when-PHY-.patch new file mode 100644 index 00000000000000..29079e03c599d0 --- /dev/null +++ b/target/linux/generic/backport-6.1/790-69-v6.10-net-dsa-mt7530-do-not-set-MT7530_P5_DIS-when-PHY-.patch @@ -0,0 +1,45 @@ +From 16e6592cd5c5bd74d8890973489f60176c692614 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= +Date: Sun, 28 Apr 2024 12:19:58 +0300 +Subject: [PATCH] net: dsa: mt7530: do not set MT7530_P5_DIS when PHY muxing is + being used +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +DSA initalises the ds->num_ports amount of ports in +dsa_switch_touch_ports(). When the PHY muxing feature is in use, port 5 +won't be defined in the device tree. Because of this, the type member of +the dsa_port structure for this port will be assigned DSA_PORT_TYPE_UNUSED. +The dsa_port_setup() function calls ds->ops->port_disable() when the port +type is DSA_PORT_TYPE_UNUSED. + +The MT7530_P5_DIS bit is unset in mt7530_setup() when PHY muxing is being +used. mt7530_port_disable() which is assigned to ds->ops->port_disable() is +called afterwards. Currently, mt7530_port_disable() sets MT7530_P5_DIS +which breaks network connectivity when PHY muxing is being used. + +Therefore, do not set MT7530_P5_DIS when PHY muxing is being used. + +Fixes: 377174c5760c ("net: dsa: mt7530: move MT753X_MTRAP operations for MT7530") +Reported-by: Daniel Golle +Signed-off-by: Arınç ÃœNAL +Reviewed-by: Andrew Lunn +Link: https://lore.kernel.org/r/20240428-for-netnext-mt7530-do-not-disable-port5-when-phy-muxing-v2-1-bb7c37d293f8@arinc9.com +Signed-off-by: Paolo Abeni +--- + drivers/net/dsa/mt7530.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/drivers/net/dsa/mt7530.c ++++ b/drivers/net/dsa/mt7530.c +@@ -1227,7 +1227,8 @@ mt7530_port_disable(struct dsa_switch *d + if (priv->id != ID_MT7530 && priv->id != ID_MT7621) + return; + +- if (port == 5) ++ /* Do not set MT7530_P5_DIS when port 5 is being used for PHY muxing. */ ++ if (port == 5 && priv->p5_mode == GMAC5) + mt7530_set(priv, MT753X_MTRAP, MT7530_P5_DIS); + else if (port == 6) + mt7530_set(priv, MT753X_MTRAP, MT7530_P6_DIS); diff --git a/target/linux/generic/backport-6.1/790-70-v6.10-796-net-dsa-mt7530-detect-PHY-muxing-when-PHY-is-defined.patch b/target/linux/generic/backport-6.1/790-70-v6.10-796-net-dsa-mt7530-detect-PHY-muxing-when-PHY-is-defined.patch new file mode 100644 index 00000000000000..69bbb8e22924d0 --- /dev/null +++ b/target/linux/generic/backport-6.1/790-70-v6.10-796-net-dsa-mt7530-detect-PHY-muxing-when-PHY-is-defined.patch @@ -0,0 +1,45 @@ +From d8dcf5bd6d0eace9f7c1daa14b63b3925b09d033 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= +Date: Tue, 30 Apr 2024 08:01:33 +0300 +Subject: [PATCH] net: dsa: mt7530: detect PHY muxing when PHY is defined on + switch MDIO bus +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Currently, the MT7530 DSA subdriver configures the MT7530 switch to provide +direct access to switch PHYs, meaning, the switch PHYs listen on the MDIO +bus the switch listens on. The PHY muxing feature makes use of this. + +This is problematic as the PHY may be attached before the switch is +initialised, in which case, the PHY will fail to be attached. + +Since commit 91374ba537bd ("net: dsa: mt7530: support OF-based registration +of switch MDIO bus"), we can describe the switch PHYs on the MDIO bus of +the switch on the device tree. Extend the check to detect PHY muxing when +the PHY is defined on the MDIO bus of the switch on the device tree. + +When the PHY is described this way, the switch will be initialised first, +then the switch MDIO bus will be registered. Only after these steps, the +PHY will be attached. + +Signed-off-by: Arınç ÃœNAL +Reviewed-by: Daniel Golle +Link: https://lore.kernel.org/r/20240430-b4-for-netnext-mt7530-use-switch-mdio-bus-for-phy-muxing-v2-1-9104d886d0db@arinc9.com +Signed-off-by: Paolo Abeni +--- + drivers/net/dsa/mt7530.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/drivers/net/dsa/mt7530.c ++++ b/drivers/net/dsa/mt7530.c +@@ -2489,7 +2489,8 @@ mt7530_setup(struct dsa_switch *ds) + if (!phy_node) + continue; + +- if (phy_node->parent == priv->dev->of_node->parent) { ++ if (phy_node->parent == priv->dev->of_node->parent || ++ phy_node->parent->parent == priv->dev->of_node) { + ret = of_get_phy_mode(mac_np, &interface); + if (ret && ret != -ENODEV) { + of_node_put(mac_np); diff --git a/target/linux/generic/pending-6.1/750-net-phy-airoha-Add-the-Airoha-EN8811H-PHY-driver.patch b/target/linux/generic/backport-6.1/798-v6.10-net-phy-air_en8811h-Add-the-Airoha-EN8811H-PHY-drive.patch similarity index 61% rename from target/linux/generic/pending-6.1/750-net-phy-airoha-Add-the-Airoha-EN8811H-PHY-driver.patch rename to target/linux/generic/backport-6.1/798-v6.10-net-phy-air_en8811h-Add-the-Airoha-EN8811H-PHY-drive.patch index 1dfa1366ebf248..7f963b3cf66e72 100644 --- a/target/linux/generic/pending-6.1/750-net-phy-airoha-Add-the-Airoha-EN8811H-PHY-driver.patch +++ b/target/linux/generic/backport-6.1/798-v6.10-net-phy-air_en8811h-Add-the-Airoha-EN8811H-PHY-drive.patch @@ -1,88 +1,33 @@ -From patchwork Tue Feb 6 19:47:51 2024 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Eric Woudstra -X-Patchwork-Id: 13547762 -X-Patchwork-Delegate: kuba@kernel.org +From 71e79430117d56c409c5ea485a263bc0d8083390 Mon Sep 17 00:00:00 2001 From: Eric Woudstra -To: "David S. Miller" , - Eric Dumazet , - Jakub Kicinski , - Paolo Abeni , - Rob Herring , - Krzysztof Kozlowski , - Conor Dooley , - Andrew Lunn , - Heiner Kallweit , - Russell King , - Matthias Brugger , - AngeloGioacchino Del Regno , - "Frank Wunderlich" , - Daniel Golle , - Lucien Jheng , - Zhi-Jun You -Cc: netdev@vger.kernel.org, - devicetree@vger.kernel.org, - Eric Woudstra -Subject: [PATCH net-next 2/2] net: phy: air_en8811h: Add the Airoha EN8811H - PHY driver -Date: Tue, 6 Feb 2024 20:47:51 +0100 -Message-ID: <20240206194751.1901802-3-ericwouds@gmail.com> -X-Mailer: git-send-email 2.42.1 -In-Reply-To: <20240206194751.1901802-1-ericwouds@gmail.com> -References: <20240206194751.1901802-1-ericwouds@gmail.com> -Precedence: bulk -X-Mailing-List: netdev@vger.kernel.org -List-Id: -List-Subscribe: -List-Unsubscribe: -MIME-Version: 1.0 -X-Patchwork-Delegate: kuba@kernel.org +Date: Tue, 26 Mar 2024 17:23:05 +0100 +Subject: [PATCH] net: phy: air_en8811h: Add the Airoha EN8811H PHY driver -* Source originated from airoha's en8811h v1.2.1 driver - * Moved air_en8811h.h to air_en8811h.c - * Removed air_pbus_reg_write() as it writes to another device on mdio-bus - * Load firmware from /lib/firmware/airoha/ instead of /lib/firmware/ - * Added .get_rate_matching() - * Use generic phy_read/write() and phy_read/write_mmd() - * Edited .get_features() to use generic C45 functions - * Edited .config_aneg() and .read_status() to use a mix of generic C22/C45 - * Use led handling functions from mediatek-ge-soc.c - * Simplified led handling by storing led rules - * Cleanup macro definitions - * Cleanup code to pass checkpatch.pl - * General code cleanup +Add the driver for the Airoha EN8811H 2.5 Gigabit PHY. The phy supports +100/1000/2500 Mbps with auto negotiation only. -Changes from original RFC patch: +The driver uses two firmware files, for which updated versions are added to +linux-firmware already. - * Use the correct order in Kconfig and Makefile - * Change some register naming to correspond with datasheet - * Use phy_driver .read_page() and .write_page() - * Use module_phy_driver() - * Use get_unaligned_le16() instead of macro - * In .config_aneg() and .read_status() use genphy_xxx() C22 - * Use another vendor register to read real speed - * Load firmware only once and store firmware version - * Apply 2.5G LPA work-around (firmware before 24011202) - * Read 2.5G LPA from vendor register (firmware 24011202 and later) - -Changes to be committed: - modified: drivers/net/phy/Kconfig - modified: drivers/net/phy/Makefile - new file: drivers/net/phy/air_en8811h.c +Note: At phy-address + 8 there is another device on the mdio bus, that +belongs to the EN881H. While the original driver writes to it, Airoha +has confirmed this is not needed. Therefore, communication with this +device is not included in this driver. Signed-off-by: Eric Woudstra +Reviewed-by: Andrew Lunn +Link: https://lore.kernel.org/r/20240326162305.303598-3-ericwouds@gmail.com +Signed-off-by: Jakub Kicinski --- drivers/net/phy/Kconfig | 5 + drivers/net/phy/Makefile | 1 + - drivers/net/phy/air_en8811h.c | 1006 +++++++++++++++++++++++++++++++++ - 3 files changed, 1012 insertions(+) + drivers/net/phy/air_en8811h.c | 1086 +++++++++++++++++++++++++++++++++ + 3 files changed, 1092 insertions(+) create mode 100644 drivers/net/phy/air_en8811h.c --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig -@@ -69,6 +69,11 @@ config SFP +@@ -63,6 +63,11 @@ config SFP comment "MII PHY device drivers" @@ -92,7 +37,7 @@ Signed-off-by: Eric Woudstra + Currently supports the Airoha EN8811H PHY. + config AMD_PHY - tristate "AMD and Altima PHYs" + tristate "AMD PHYs" help --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -106,12 +51,10 @@ Signed-off-by: Eric Woudstra obj-$(CONFIG_AX88796B_PHY) += ax88796b.o --- /dev/null +++ b/drivers/net/phy/air_en8811h.c -@@ -0,0 +1,1006 @@ +@@ -0,0 +1,1086 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* -+ * Driver for Airoha Ethernet PHYs -+ * -+ * Currently supporting the EN8811H. ++ * Driver for the Airoha EN8811H 2.5 Gigabit PHY. + * + * Limitations of the EN8811H: + * - Only full duplex supported @@ -125,6 +68,7 @@ Signed-off-by: Eric Woudstra +#include +#include +#include ++#include +#include + +#define EN8811H_PHY_ID 0x03a2a411 @@ -135,12 +79,8 @@ Signed-off-by: Eric Woudstra +#define AIR_FW_ADDR_DM 0x00000000 +#define AIR_FW_ADDR_DSP 0x00100000 + -+/* u32 (DWORD) component macros */ -+#define LOWORD(d) ((u16)(u32)(d)) -+#define HIWORD(d) ((u16)(((u32)(d)) >> 16)) -+ +/* MII Registers */ -+#define AIR_AUX_CTRL_STATUS 0x1d ++#define AIR_AUX_CTRL_STATUS 0x1d +#define AIR_AUX_CTRL_STATUS_SPEED_MASK GENMASK(4, 2) +#define AIR_AUX_CTRL_STATUS_SPEED_100 0x4 +#define AIR_AUX_CTRL_STATUS_SPEED_1000 0x8 @@ -151,32 +91,32 @@ Signed-off-by: Eric Woudstra +#define AIR_PHY_PAGE_EXTENDED_4 0x0004 + +/* MII Registers Page 4*/ -+#define AIR_PBUS_MODE 0x10 -+#define AIR_PBUS_MODE_ADDR_FIXED 0x0000 -+#define AIR_PBUS_MODE_ADDR_INCR BIT(15) -+#define AIR_PBUS_WR_ADDR_HIGH 0x11 -+#define AIR_PBUS_WR_ADDR_LOW 0x12 -+#define AIR_PBUS_WR_DATA_HIGH 0x13 -+#define AIR_PBUS_WR_DATA_LOW 0x14 -+#define AIR_PBUS_RD_ADDR_HIGH 0x15 -+#define AIR_PBUS_RD_ADDR_LOW 0x16 -+#define AIR_PBUS_RD_DATA_HIGH 0x17 -+#define AIR_PBUS_RD_DATA_LOW 0x18 ++#define AIR_BPBUS_MODE 0x10 ++#define AIR_BPBUS_MODE_ADDR_FIXED 0x0000 ++#define AIR_BPBUS_MODE_ADDR_INCR BIT(15) ++#define AIR_BPBUS_WR_ADDR_HIGH 0x11 ++#define AIR_BPBUS_WR_ADDR_LOW 0x12 ++#define AIR_BPBUS_WR_DATA_HIGH 0x13 ++#define AIR_BPBUS_WR_DATA_LOW 0x14 ++#define AIR_BPBUS_RD_ADDR_HIGH 0x15 ++#define AIR_BPBUS_RD_ADDR_LOW 0x16 ++#define AIR_BPBUS_RD_DATA_HIGH 0x17 ++#define AIR_BPBUS_RD_DATA_LOW 0x18 + +/* Registers on MDIO_MMD_VEND1 */ +#define EN8811H_PHY_FW_STATUS 0x8009 +#define EN8811H_PHY_READY 0x02 + -+#define AIR_PHY_HOST_CMD_1 0x800c -+#define AIR_PHY_HOST_CMD_1_MODE1 0x0 -+#define AIR_PHY_HOST_CMD_2 0x800d -+#define AIR_PHY_HOST_CMD_2_MODE1 0x0 -+#define AIR_PHY_HOST_CMD_3 0x800e -+#define AIR_PHY_HOST_CMD_3_MODE1 0x1101 -+#define AIR_PHY_HOST_CMD_3_DOCMD 0x1100 -+#define AIR_PHY_HOST_CMD_4 0x800f -+#define AIR_PHY_HOST_CMD_4_MODE1 0x0002 -+#define AIR_PHY_HOST_CMD_4_INTCLR 0x00e4 ++#define AIR_PHY_MCU_CMD_1 0x800c ++#define AIR_PHY_MCU_CMD_1_MODE1 0x0 ++#define AIR_PHY_MCU_CMD_2 0x800d ++#define AIR_PHY_MCU_CMD_2_MODE1 0x0 ++#define AIR_PHY_MCU_CMD_3 0x800e ++#define AIR_PHY_MCU_CMD_3_MODE1 0x1101 ++#define AIR_PHY_MCU_CMD_3_DOCMD 0x1100 ++#define AIR_PHY_MCU_CMD_4 0x800f ++#define AIR_PHY_MCU_CMD_4_MODE1 0x0002 ++#define AIR_PHY_MCU_CMD_4_INTCLR 0x00e4 + +/* Registers on MDIO_MMD_VEND2 */ +#define AIR_PHY_LED_BCR 0x021 @@ -235,28 +175,21 @@ Signed-off-by: Eric Woudstra +#define EN8811H_FW_CTRL_2 0x800000 +#define EN8811H_FW_CTRL_2_LOADING BIT(11) + ++/* Led definitions */ +#define EN8811H_LED_COUNT 3 + -+/* GPIO5 <-> BASE_T_LED0 -+ * GPIO4 <-> BASE_T_LED1 -+ * GPIO3 <-> BASE_T_LED2 -+ * -+ * Default setup suitable for 2 leds connected: -+ * 100M link up triggers led0, only led0 blinking on traffic -+ * 1000M link up triggers led1, only led1 blinking on traffic -+ * 2500M link up triggers led0 and led1, both blinking on traffic -+ * Also suitable for 1 led connected: -+ * any link up triggers led2 ++/* Default LED setup: ++ * GPIO5 <-> LED0 On: Link detected, blink Rx/Tx ++ * GPIO4 <-> LED1 On: Link detected at 2500 or 1000 Mbps ++ * GPIO3 <-> LED2 On: Link detected at 2500 or 100 Mbps + */ -+#define AIR_DEFAULT_TRIGGER_LED0 (BIT(TRIGGER_NETDEV_LINK_2500) | \ -+ BIT(TRIGGER_NETDEV_LINK_100) | \ ++#define AIR_DEFAULT_TRIGGER_LED0 (BIT(TRIGGER_NETDEV_LINK) | \ + BIT(TRIGGER_NETDEV_RX) | \ + BIT(TRIGGER_NETDEV_TX)) +#define AIR_DEFAULT_TRIGGER_LED1 (BIT(TRIGGER_NETDEV_LINK_2500) | \ -+ BIT(TRIGGER_NETDEV_LINK_1000) | \ -+ BIT(TRIGGER_NETDEV_RX) | \ -+ BIT(TRIGGER_NETDEV_TX)) -+#define AIR_DEFAULT_TRIGGER_LED2 BIT(TRIGGER_NETDEV_LINK) ++ BIT(TRIGGER_NETDEV_LINK_1000)) ++#define AIR_DEFAULT_TRIGGER_LED2 (BIT(TRIGGER_NETDEV_LINK_2500) | \ ++ BIT(TRIGGER_NETDEV_LINK_100)) + +struct led { + unsigned long rules; @@ -265,6 +198,7 @@ Signed-off-by: Eric Woudstra + +struct en8811h_priv { + u32 firmware_version; ++ bool mcu_needs_restart; + struct led led[EN8811H_LED_COUNT]; +}; + @@ -274,12 +208,12 @@ Signed-off-by: Eric Woudstra +}; + +enum { -+ AIR_PHY_LED_DUR_BLINK_32M, -+ AIR_PHY_LED_DUR_BLINK_64M, -+ AIR_PHY_LED_DUR_BLINK_128M, -+ AIR_PHY_LED_DUR_BLINK_256M, -+ AIR_PHY_LED_DUR_BLINK_512M, -+ AIR_PHY_LED_DUR_BLINK_1024M, ++ AIR_PHY_LED_DUR_BLINK_32MS, ++ AIR_PHY_LED_DUR_BLINK_64MS, ++ AIR_PHY_LED_DUR_BLINK_128MS, ++ AIR_PHY_LED_DUR_BLINK_256MS, ++ AIR_PHY_LED_DUR_BLINK_512MS, ++ AIR_PHY_LED_DUR_BLINK_1024MS, +}; + +enum { @@ -298,16 +232,16 @@ Signed-off-by: Eric Woudstra +}; + +#define AIR_PHY_LED_DUR_UNIT 1024 -+#define AIR_PHY_LED_DUR (AIR_PHY_LED_DUR_UNIT << AIR_PHY_LED_DUR_BLINK_64M) ++#define AIR_PHY_LED_DUR (AIR_PHY_LED_DUR_UNIT << AIR_PHY_LED_DUR_BLINK_64MS) + -+static const unsigned long en8811h_led_trig = (BIT(TRIGGER_NETDEV_FULL_DUPLEX) | -+ BIT(TRIGGER_NETDEV_LINK) | -+ BIT(TRIGGER_NETDEV_LINK_10) | -+ BIT(TRIGGER_NETDEV_LINK_100) | -+ BIT(TRIGGER_NETDEV_LINK_1000) | -+ BIT(TRIGGER_NETDEV_LINK_2500) | -+ BIT(TRIGGER_NETDEV_RX) | -+ BIT(TRIGGER_NETDEV_TX)); ++static const unsigned long en8811h_led_trig = BIT(TRIGGER_NETDEV_FULL_DUPLEX) | ++ BIT(TRIGGER_NETDEV_LINK) | ++ BIT(TRIGGER_NETDEV_LINK_10) | ++ BIT(TRIGGER_NETDEV_LINK_100) | ++ BIT(TRIGGER_NETDEV_LINK_1000) | ++ BIT(TRIGGER_NETDEV_LINK_2500) | ++ BIT(TRIGGER_NETDEV_RX) | ++ BIT(TRIGGER_NETDEV_TX); + +static int air_phy_read_page(struct phy_device *phydev) +{ @@ -324,23 +258,27 @@ Signed-off-by: Eric Woudstra +{ + int ret; + -+ ret = __phy_write(phydev, AIR_PBUS_MODE, AIR_PBUS_MODE_ADDR_FIXED); ++ ret = __phy_write(phydev, AIR_BPBUS_MODE, AIR_BPBUS_MODE_ADDR_FIXED); + if (ret < 0) + return ret; + -+ ret = __phy_write(phydev, AIR_PBUS_WR_ADDR_HIGH, HIWORD(pbus_address)); ++ ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_HIGH, ++ upper_16_bits(pbus_address)); + if (ret < 0) + return ret; + -+ ret = __phy_write(phydev, AIR_PBUS_WR_ADDR_LOW, LOWORD(pbus_address)); ++ ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_LOW, ++ lower_16_bits(pbus_address)); + if (ret < 0) + return ret; + -+ ret = __phy_write(phydev, AIR_PBUS_WR_DATA_HIGH, HIWORD(pbus_data)); ++ ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_HIGH, ++ upper_16_bits(pbus_data)); + if (ret < 0) + return ret; + -+ ret = __phy_write(phydev, AIR_PBUS_WR_DATA_LOW, LOWORD(pbus_data)); ++ ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_LOW, ++ lower_16_bits(pbus_data)); + if (ret < 0) + return ret; + @@ -350,17 +288,20 @@ Signed-off-by: Eric Woudstra +static int air_buckpbus_reg_write(struct phy_device *phydev, + u32 pbus_address, u32 pbus_data) +{ -+ int ret, saved_page; ++ int saved_page; ++ int ret = 0; + + saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4); + -+ ret = __air_buckpbus_reg_write(phydev, pbus_address, pbus_data); -+ if (ret < 0) -+ phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__, -+ pbus_address, ret); ++ if (saved_page >= 0) { ++ ret = __air_buckpbus_reg_write(phydev, pbus_address, ++ pbus_data); ++ if (ret < 0) ++ phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__, ++ pbus_address, ret); ++ } + + return phy_restore_page(phydev, saved_page, ret); -+; +} + +static int __air_buckpbus_reg_read(struct phy_device *phydev, @@ -369,41 +310,122 @@ Signed-off-by: Eric Woudstra + int pbus_data_low, pbus_data_high; + int ret; + -+ ret = __phy_write(phydev, AIR_PBUS_MODE, AIR_PBUS_MODE_ADDR_FIXED); ++ ret = __phy_write(phydev, AIR_BPBUS_MODE, AIR_BPBUS_MODE_ADDR_FIXED); + if (ret < 0) + return ret; + -+ ret = __phy_write(phydev, AIR_PBUS_RD_ADDR_HIGH, HIWORD(pbus_address)); ++ ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_HIGH, ++ upper_16_bits(pbus_address)); + if (ret < 0) + return ret; + -+ ret = __phy_write(phydev, AIR_PBUS_RD_ADDR_LOW, LOWORD(pbus_address)); ++ ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_LOW, ++ lower_16_bits(pbus_address)); + if (ret < 0) + return ret; + -+ pbus_data_high = __phy_read(phydev, AIR_PBUS_RD_DATA_HIGH); ++ pbus_data_high = __phy_read(phydev, AIR_BPBUS_RD_DATA_HIGH); + if (pbus_data_high < 0) + return ret; + -+ pbus_data_low = __phy_read(phydev, AIR_PBUS_RD_DATA_LOW); ++ pbus_data_low = __phy_read(phydev, AIR_BPBUS_RD_DATA_LOW); + if (pbus_data_low < 0) + return ret; + -+ *pbus_data = (u16)pbus_data_low | ((u32)(u16)pbus_data_high << 16); ++ *pbus_data = pbus_data_low | (pbus_data_high << 16); + return 0; +} + +static int air_buckpbus_reg_read(struct phy_device *phydev, + u32 pbus_address, u32 *pbus_data) +{ -+ int ret, saved_page; ++ int saved_page; ++ int ret = 0; + + saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4); + -+ ret = __air_buckpbus_reg_read(phydev, pbus_address, pbus_data); ++ if (saved_page >= 0) { ++ ret = __air_buckpbus_reg_read(phydev, pbus_address, pbus_data); ++ if (ret < 0) ++ phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__, ++ pbus_address, ret); ++ } ++ ++ return phy_restore_page(phydev, saved_page, ret); ++} ++ ++static int __air_buckpbus_reg_modify(struct phy_device *phydev, ++ u32 pbus_address, u32 mask, u32 set) ++{ ++ int pbus_data_low, pbus_data_high; ++ u32 pbus_data_old, pbus_data_new; ++ int ret; ++ ++ ret = __phy_write(phydev, AIR_BPBUS_MODE, AIR_BPBUS_MODE_ADDR_FIXED); ++ if (ret < 0) ++ return ret; ++ ++ ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_HIGH, ++ upper_16_bits(pbus_address)); ++ if (ret < 0) ++ return ret; ++ ++ ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_LOW, ++ lower_16_bits(pbus_address)); ++ if (ret < 0) ++ return ret; ++ ++ pbus_data_high = __phy_read(phydev, AIR_BPBUS_RD_DATA_HIGH); ++ if (pbus_data_high < 0) ++ return ret; ++ ++ pbus_data_low = __phy_read(phydev, AIR_BPBUS_RD_DATA_LOW); ++ if (pbus_data_low < 0) ++ return ret; ++ ++ pbus_data_old = pbus_data_low | (pbus_data_high << 16); ++ pbus_data_new = (pbus_data_old & ~mask) | set; ++ if (pbus_data_new == pbus_data_old) ++ return 0; ++ ++ ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_HIGH, ++ upper_16_bits(pbus_address)); + if (ret < 0) -+ phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__, -+ pbus_address, ret); ++ return ret; ++ ++ ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_LOW, ++ lower_16_bits(pbus_address)); ++ if (ret < 0) ++ return ret; ++ ++ ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_HIGH, ++ upper_16_bits(pbus_data_new)); ++ if (ret < 0) ++ return ret; ++ ++ ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_LOW, ++ lower_16_bits(pbus_data_new)); ++ if (ret < 0) ++ return ret; ++ ++ return 0; ++} ++ ++static int air_buckpbus_reg_modify(struct phy_device *phydev, ++ u32 pbus_address, u32 mask, u32 set) ++{ ++ int saved_page; ++ int ret = 0; ++ ++ saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4); ++ ++ if (saved_page >= 0) { ++ ret = __air_buckpbus_reg_modify(phydev, pbus_address, mask, ++ set); ++ if (ret < 0) ++ phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__, ++ pbus_address, ret); ++ } + + return phy_restore_page(phydev, saved_page, ret); +} @@ -415,26 +437,28 @@ Signed-off-by: Eric Woudstra + int ret; + u16 val; + -+ ret = __phy_write(phydev, AIR_PBUS_MODE, AIR_PBUS_MODE_ADDR_INCR); ++ ret = __phy_write(phydev, AIR_BPBUS_MODE, AIR_BPBUS_MODE_ADDR_INCR); + if (ret < 0) + return ret; + -+ ret = __phy_write(phydev, AIR_PBUS_WR_ADDR_HIGH, HIWORD(address)); ++ ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_HIGH, ++ upper_16_bits(address)); + if (ret < 0) + return ret; + -+ ret = __phy_write(phydev, AIR_PBUS_WR_ADDR_LOW, LOWORD(address)); ++ ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_LOW, ++ lower_16_bits(address)); + if (ret < 0) + return ret; + + for (offset = 0; offset < fw->size; offset += 4) { + val = get_unaligned_le16(&fw->data[offset + 2]); -+ ret = __phy_write(phydev, AIR_PBUS_WR_DATA_HIGH, val); ++ ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_HIGH, val); + if (ret < 0) + return ret; + + val = get_unaligned_le16(&fw->data[offset]); -+ ret = __phy_write(phydev, AIR_PBUS_WR_DATA_LOW, val); ++ ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_LOW, val); + if (ret < 0) + return ret; + } @@ -445,23 +469,43 @@ Signed-off-by: Eric Woudstra +static int air_write_buf(struct phy_device *phydev, u32 address, + const struct firmware *fw) +{ -+ int ret, saved_page; ++ int saved_page; ++ int ret = 0; + + saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4); + -+ ret = __air_write_buf(phydev, address, fw); -+ if (ret < 0) -+ phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__, -+ address, ret); ++ if (saved_page >= 0) { ++ ret = __air_write_buf(phydev, address, fw); ++ if (ret < 0) ++ phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__, ++ address, ret); ++ } + + return phy_restore_page(phydev, saved_page, ret); +} + ++static int en8811h_wait_mcu_ready(struct phy_device *phydev) ++{ ++ int ret, reg_value; ++ ++ /* Because of mdio-lock, may have to wait for multiple loads */ ++ ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, ++ EN8811H_PHY_FW_STATUS, reg_value, ++ reg_value == EN8811H_PHY_READY, ++ 20000, 7500000, true); ++ if (ret) { ++ phydev_err(phydev, "MCU not ready: 0x%x\n", reg_value); ++ return -ENODEV; ++ } ++ ++ return 0; ++} ++ +static int en8811h_load_firmware(struct phy_device *phydev) +{ ++ struct en8811h_priv *priv = phydev->priv; + struct device *dev = &phydev->mdio.dev; + const struct firmware *fw1, *fw2; -+ u32 pbus_value; + int ret; + + ret = request_firmware_direct(&fw1, EN8811H_MD32_DM, dev); @@ -477,11 +521,9 @@ Signed-off-by: Eric Woudstra + if (ret < 0) + goto en8811h_load_firmware_out; + -+ ret = air_buckpbus_reg_read(phydev, EN8811H_FW_CTRL_2, &pbus_value); -+ if (ret < 0) -+ goto en8811h_load_firmware_out; -+ pbus_value |= EN8811H_FW_CTRL_2_LOADING; -+ ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_2, pbus_value); ++ ret = air_buckpbus_reg_modify(phydev, EN8811H_FW_CTRL_2, ++ EN8811H_FW_CTRL_2_LOADING, ++ EN8811H_FW_CTRL_2_LOADING); + if (ret < 0) + goto en8811h_load_firmware_out; + @@ -493,11 +535,8 @@ Signed-off-by: Eric Woudstra + if (ret < 0) + goto en8811h_load_firmware_out; + -+ ret = air_buckpbus_reg_read(phydev, EN8811H_FW_CTRL_2, &pbus_value); -+ if (ret < 0) -+ goto en8811h_load_firmware_out; -+ pbus_value &= ~EN8811H_FW_CTRL_2_LOADING; -+ ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_2, pbus_value); ++ ret = air_buckpbus_reg_modify(phydev, EN8811H_FW_CTRL_2, ++ EN8811H_FW_CTRL_2_LOADING, 0); + if (ret < 0) + goto en8811h_load_firmware_out; + @@ -506,7 +545,12 @@ Signed-off-by: Eric Woudstra + if (ret < 0) + goto en8811h_load_firmware_out; + -+ ret = 0; ++ ret = en8811h_wait_mcu_ready(phydev); ++ ++ air_buckpbus_reg_read(phydev, EN8811H_FW_VERSION, ++ &priv->firmware_version); ++ phydev_info(phydev, "MD32 firmware version: %08x\n", ++ priv->firmware_version); + +en8811h_load_firmware_out: + release_firmware(fw2); @@ -520,7 +564,7 @@ Signed-off-by: Eric Woudstra + return ret; +} + -+static int en8811h_restart_host(struct phy_device *phydev) ++static int en8811h_restart_mcu(struct phy_device *phydev) +{ + int ret; + @@ -529,8 +573,12 @@ Signed-off-by: Eric Woudstra + if (ret < 0) + return ret; + -+ return air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1, ++ ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1, + EN8811H_FW_CTRL_1_FINISH); ++ if (ret < 0) ++ return ret; ++ ++ return en8811h_wait_mcu_ready(phydev); +} + +static int air_hw_led_on_set(struct phy_device *phydev, u8 index, bool on) @@ -664,68 +712,46 @@ Signed-off-by: Eric Woudstra + u16 on = 0, blink = 0; + int ret; + -+ priv->led[index].rules = rules; -+ + if (index >= EN8811H_LED_COUNT) + return -EINVAL; + -+ if (rules & (BIT(TRIGGER_NETDEV_LINK_10) | BIT(TRIGGER_NETDEV_LINK))) { ++ priv->led[index].rules = rules; ++ ++ if (rules & BIT(TRIGGER_NETDEV_FULL_DUPLEX)) ++ on |= AIR_PHY_LED_ON_FDX; ++ ++ if (rules & (BIT(TRIGGER_NETDEV_LINK_10) | BIT(TRIGGER_NETDEV_LINK))) + on |= AIR_PHY_LED_ON_LINK10; -+ if (rules & BIT(TRIGGER_NETDEV_RX)) -+ blink |= AIR_PHY_LED_BLINK_10RX; -+ if (rules & BIT(TRIGGER_NETDEV_TX)) -+ blink |= AIR_PHY_LED_BLINK_10TX; -+ } + -+ if (rules & (BIT(TRIGGER_NETDEV_LINK_100) | BIT(TRIGGER_NETDEV_LINK))) { ++ if (rules & (BIT(TRIGGER_NETDEV_LINK_100) | BIT(TRIGGER_NETDEV_LINK))) + on |= AIR_PHY_LED_ON_LINK100; -+ if (rules & BIT(TRIGGER_NETDEV_RX)) -+ blink |= AIR_PHY_LED_BLINK_100RX; -+ if (rules & BIT(TRIGGER_NETDEV_TX)) -+ blink |= AIR_PHY_LED_BLINK_100TX; -+ } + -+ if (rules & (BIT(TRIGGER_NETDEV_LINK_1000) | BIT(TRIGGER_NETDEV_LINK))) { ++ if (rules & (BIT(TRIGGER_NETDEV_LINK_1000) | BIT(TRIGGER_NETDEV_LINK))) + on |= AIR_PHY_LED_ON_LINK1000; -+ if (rules & BIT(TRIGGER_NETDEV_RX)) -+ blink |= AIR_PHY_LED_BLINK_1000RX; -+ if (rules & BIT(TRIGGER_NETDEV_TX)) -+ blink |= AIR_PHY_LED_BLINK_1000TX; -+ } + -+ if (rules & (BIT(TRIGGER_NETDEV_LINK_2500) | BIT(TRIGGER_NETDEV_LINK))) { ++ if (rules & (BIT(TRIGGER_NETDEV_LINK_2500) | BIT(TRIGGER_NETDEV_LINK))) + on |= AIR_PHY_LED_ON_LINK2500; -+ if (rules & BIT(TRIGGER_NETDEV_RX)) -+ blink |= AIR_PHY_LED_BLINK_2500RX; -+ if (rules & BIT(TRIGGER_NETDEV_TX)) -+ blink |= AIR_PHY_LED_BLINK_2500TX; -+ } + -+ if (on == 0) { -+ if (rules & BIT(TRIGGER_NETDEV_RX)) { -+ blink |= AIR_PHY_LED_BLINK_10RX | -+ AIR_PHY_LED_BLINK_100RX | -+ AIR_PHY_LED_BLINK_1000RX | -+ AIR_PHY_LED_BLINK_2500RX; -+ } -+ if (rules & BIT(TRIGGER_NETDEV_TX)) { -+ blink |= AIR_PHY_LED_BLINK_10TX | -+ AIR_PHY_LED_BLINK_100TX | -+ AIR_PHY_LED_BLINK_1000TX | -+ AIR_PHY_LED_BLINK_2500TX; -+ } ++ if (rules & BIT(TRIGGER_NETDEV_RX)) { ++ blink |= AIR_PHY_LED_BLINK_10RX | ++ AIR_PHY_LED_BLINK_100RX | ++ AIR_PHY_LED_BLINK_1000RX | ++ AIR_PHY_LED_BLINK_2500RX; + } + -+ if (rules & BIT(TRIGGER_NETDEV_FULL_DUPLEX)) -+ on |= AIR_PHY_LED_ON_FDX; -+ -+ if (rules & BIT(TRIGGER_NETDEV_HALF_DUPLEX)) -+ on |= AIR_PHY_LED_ON_HDX; ++ if (rules & BIT(TRIGGER_NETDEV_TX)) { ++ blink |= AIR_PHY_LED_BLINK_10TX | ++ AIR_PHY_LED_BLINK_100TX | ++ AIR_PHY_LED_BLINK_1000TX | ++ AIR_PHY_LED_BLINK_2500TX; ++ } + + if (blink || on) { + /* switch hw-control on, so led-on and led-blink are off */ -+ clear_bit(AIR_PHY_LED_STATE_FORCE_ON, &priv->led[index].state); -+ clear_bit(AIR_PHY_LED_STATE_FORCE_BLINK, &priv->led[index].state); ++ clear_bit(AIR_PHY_LED_STATE_FORCE_ON, ++ &priv->led[index].state); ++ clear_bit(AIR_PHY_LED_STATE_FORCE_BLINK, ++ &priv->led[index].state); + } else { + priv->led[index].rules = 0; + } @@ -742,28 +768,26 @@ Signed-off-by: Eric Woudstra + +static int air_led_init(struct phy_device *phydev, u8 index, u8 state, u8 pol) +{ -+ int cl45_data; ++ int val = 0; + int err; + + if (index >= EN8811H_LED_COUNT) + return -EINVAL; + -+ cl45_data = phy_read_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_ON(index)); -+ if (cl45_data < 0) -+ return cl45_data; -+ + if (state == AIR_LED_ENABLE) -+ cl45_data |= AIR_PHY_LED_ON_ENABLE; ++ val |= AIR_PHY_LED_ON_ENABLE; + else -+ cl45_data &= ~AIR_PHY_LED_ON_ENABLE; ++ val &= ~AIR_PHY_LED_ON_ENABLE; + + if (pol == AIR_ACTIVE_HIGH) -+ cl45_data |= AIR_PHY_LED_ON_POLARITY; ++ val |= AIR_PHY_LED_ON_POLARITY; + else -+ cl45_data &= ~AIR_PHY_LED_ON_POLARITY; ++ val &= ~AIR_PHY_LED_ON_POLARITY; ++ ++ err = phy_modify_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_ON(index), ++ AIR_PHY_LED_ON_ENABLE | ++ AIR_PHY_LED_ON_POLARITY, val); + -+ err = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_ON(index), -+ cl45_data); + if (err < 0) + return err; + @@ -773,42 +797,40 @@ Signed-off-by: Eric Woudstra +static int air_leds_init(struct phy_device *phydev, int num, int dur, int mode) +{ + struct en8811h_priv *priv = phydev->priv; -+ int cl45_data = dur; + int ret, i; + + ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_DUR_BLINK, -+ cl45_data); ++ dur); + if (ret < 0) + return ret; + -+ cl45_data >>= 1; + ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_DUR_ON, -+ cl45_data); ++ dur >> 1); + if (ret < 0) + return ret; + -+ cl45_data = phy_read_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_BCR); -+ if (cl45_data < 0) -+ return cl45_data; -+ + switch (mode) { + case AIR_LED_MODE_DISABLE: -+ cl45_data &= ~AIR_PHY_LED_BCR_EXT_CTRL; -+ cl45_data &= ~AIR_PHY_LED_BCR_MODE_MASK; ++ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_BCR, ++ AIR_PHY_LED_BCR_EXT_CTRL | ++ AIR_PHY_LED_BCR_MODE_MASK, 0); ++ if (ret < 0) ++ return ret; + break; + case AIR_LED_MODE_USER_DEFINE: -+ cl45_data |= AIR_PHY_LED_BCR_EXT_CTRL; -+ cl45_data |= AIR_PHY_LED_BCR_CLK_EN; ++ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_BCR, ++ AIR_PHY_LED_BCR_EXT_CTRL | ++ AIR_PHY_LED_BCR_CLK_EN, ++ AIR_PHY_LED_BCR_EXT_CTRL | ++ AIR_PHY_LED_BCR_CLK_EN); ++ if (ret < 0) ++ return ret; + break; + default: + phydev_err(phydev, "LED mode %d is not supported\n", mode); + return -EINVAL; + } + -+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_BCR, cl45_data); -+ if (ret < 0) -+ return ret; -+ + for (i = 0; i < num; ++i) { + ret = air_led_init(phydev, i, AIR_LED_ENABLE, AIR_ACTIVE_HIGH); + if (ret < 0) { @@ -837,21 +859,42 @@ Signed-off-by: Eric Woudstra +static int en8811h_probe(struct phy_device *phydev) +{ + struct en8811h_priv *priv; ++ int ret; + + priv = devm_kzalloc(&phydev->mdio.dev, sizeof(struct en8811h_priv), + GFP_KERNEL); + if (!priv) + return -ENOMEM; ++ phydev->priv = priv; ++ ++ ret = en8811h_load_firmware(phydev); ++ if (ret < 0) ++ return ret; ++ ++ /* mcu has just restarted after firmware load */ ++ priv->mcu_needs_restart = false; + + priv->led[0].rules = AIR_DEFAULT_TRIGGER_LED0; + priv->led[1].rules = AIR_DEFAULT_TRIGGER_LED1; + priv->led[2].rules = AIR_DEFAULT_TRIGGER_LED2; + -+ phydev->priv = priv; -+ + /* MDIO_DEVS1/2 empty, so set mmds_present bits here */ + phydev->c45_ids.mmds_present |= MDIO_DEVS_PMAPMD | MDIO_DEVS_AN; + ++ ret = air_leds_init(phydev, EN8811H_LED_COUNT, AIR_PHY_LED_DUR, ++ AIR_LED_MODE_DISABLE); ++ if (ret < 0) { ++ phydev_err(phydev, "Failed to disable leds: %d\n", ret); ++ return ret; ++ } ++ ++ /* Configure led gpio pins as output */ ++ ret = air_buckpbus_reg_modify(phydev, EN8811H_GPIO_OUTPUT, ++ EN8811H_GPIO_OUTPUT_345, ++ EN8811H_GPIO_OUTPUT_345); ++ if (ret < 0) ++ return ret; ++ + return 0; +} + @@ -859,58 +902,41 @@ Signed-off-by: Eric Woudstra +{ + struct en8811h_priv *priv = phydev->priv; + struct device *dev = &phydev->mdio.dev; -+ int ret, pollret, reg_value; + u32 pbus_value; ++ int ret; + -+ if (!priv->firmware_version) -+ ret = en8811h_load_firmware(phydev); -+ else -+ ret = en8811h_restart_host(phydev); -+ if (ret < 0) -+ return ret; -+ -+ /* Because of mdio-lock, may have to wait for multiple loads */ -+ pollret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, -+ EN8811H_PHY_FW_STATUS, reg_value, -+ reg_value == EN8811H_PHY_READY, -+ 20000, 7500000, true); -+ -+ ret = air_buckpbus_reg_read(phydev, EN8811H_FW_VERSION, &pbus_value); -+ if (ret < 0) -+ return ret; -+ -+ if (pollret || !pbus_value) { -+ phydev_err(phydev, "Firmware not ready: 0x%x\n", reg_value); -+ return -ENODEV; -+ } -+ -+ if (!priv->firmware_version) { -+ phydev_info(phydev, "MD32 firmware version: %08x\n", pbus_value); -+ priv->firmware_version = pbus_value; ++ /* If restart happened in .probe(), no need to restart now */ ++ if (priv->mcu_needs_restart) { ++ ret = en8811h_restart_mcu(phydev); ++ if (ret < 0) ++ return ret; ++ } else { ++ /* Next calls to .config_init() mcu needs to restart */ ++ priv->mcu_needs_restart = true; + } + -+ /* Select mode 1, the only mode supported */ -+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_HOST_CMD_1, -+ AIR_PHY_HOST_CMD_1_MODE1); ++ /* Select mode 1, the only mode supported. ++ * Configures the SerDes for 2500Base-X with rate adaptation ++ */ ++ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_1, ++ AIR_PHY_MCU_CMD_1_MODE1); + if (ret < 0) + return ret; -+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_HOST_CMD_2, -+ AIR_PHY_HOST_CMD_2_MODE1); ++ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_2, ++ AIR_PHY_MCU_CMD_2_MODE1); + if (ret < 0) + return ret; -+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_HOST_CMD_3, -+ AIR_PHY_HOST_CMD_3_MODE1); ++ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_3, ++ AIR_PHY_MCU_CMD_3_MODE1); + if (ret < 0) + return ret; -+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_HOST_CMD_4, -+ AIR_PHY_HOST_CMD_4_MODE1); ++ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_4, ++ AIR_PHY_MCU_CMD_4_MODE1); + if (ret < 0) + return ret; + + /* Serdes polarity */ -+ ret = air_buckpbus_reg_read(phydev, EN8811H_POLARITY, &pbus_value); -+ if (ret < 0) -+ return ret; ++ pbus_value = 0; + if (device_property_read_bool(dev, "airoha,pnswap-rx")) + pbus_value |= EN8811H_POLARITY_RX_REVERSE; + else @@ -919,7 +945,9 @@ Signed-off-by: Eric Woudstra + pbus_value &= ~EN8811H_POLARITY_TX_NORMAL; + else + pbus_value |= EN8811H_POLARITY_TX_NORMAL; -+ ret = air_buckpbus_reg_write(phydev, EN8811H_POLARITY, pbus_value); ++ ret = air_buckpbus_reg_modify(phydev, EN8811H_POLARITY, ++ EN8811H_POLARITY_RX_REVERSE | ++ EN8811H_POLARITY_TX_NORMAL, pbus_value); + if (ret < 0) + return ret; + @@ -930,14 +958,6 @@ Signed-off-by: Eric Woudstra + return ret; + } + -+ ret = air_buckpbus_reg_read(phydev, EN8811H_GPIO_OUTPUT, &pbus_value); -+ if (ret < 0) -+ return ret; -+ pbus_value |= EN8811H_GPIO_OUTPUT_345; -+ ret = air_buckpbus_reg_write(phydev, EN8811H_GPIO_OUTPUT, pbus_value); -+ if (ret < 0) -+ return ret; -+ + return 0; +} + @@ -959,17 +979,21 @@ Signed-off-by: Eric Woudstra +static int en8811h_config_aneg(struct phy_device *phydev) +{ + bool changed = false; -+ int err, val; -+ -+ val = 0; -+ if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, -+ phydev->advertising)) -+ val |= MDIO_AN_10GBT_CTRL_ADV2_5G; -+ err = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, -+ MDIO_AN_10GBT_CTRL_ADV2_5G, val); -+ if (err < 0) -+ return err; -+ if (err > 0) ++ int ret; ++ u32 adv; ++ ++ if (phydev->autoneg == AUTONEG_DISABLE) { ++ phydev_warn(phydev, "Disabling autoneg is not supported\n"); ++ return -EINVAL; ++ } ++ ++ adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising); ++ ++ ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, ++ MDIO_AN_10GBT_CTRL_ADV2_5G, adv); ++ if (ret < 0) ++ return ret; ++ if (ret > 0) + changed = true; + + return __genphy_config_aneg(phydev, changed); @@ -991,6 +1015,7 @@ Signed-off-by: Eric Woudstra + phydev->duplex = DUPLEX_UNKNOWN; + phydev->pause = 0; + phydev->asym_pause = 0; ++ phydev->rate_matching = RATE_MATCH_PAUSE; + + ret = genphy_read_master_slave(phydev); + if (ret < 0) @@ -1008,7 +1033,7 @@ Signed-off-by: Eric Woudstra + phydev->lp_advertising, + pbus_value & EN8811H_2P5G_LPA_2P5G); + -+ if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) ++ if (phydev->autoneg_complete) + phy_resolve_aneg_pause(phydev); + + if (!phydev->link) @@ -1030,8 +1055,7 @@ Signed-off-by: Eric Woudstra + break; + } + -+ /* BUG in PHY firmware: MDIO_AN_10GBT_STAT_LP2_5G does not get set. -+ * Firmware before version 24011202 has no vendor register 2P5G_LPA. ++ /* Firmware before version 24011202 has no vendor register 2P5G_LPA. + * Assume link partner advertised it if connected at 2500Mbps. + */ + if (priv->firmware_version < 0x24011202) { @@ -1050,13 +1074,13 @@ Signed-off-by: Eric Woudstra +{ + int ret; + -+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_HOST_CMD_3, -+ AIR_PHY_HOST_CMD_3_DOCMD); ++ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_3, ++ AIR_PHY_MCU_CMD_3_DOCMD); + if (ret < 0) + return ret; + -+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_HOST_CMD_4, -+ AIR_PHY_HOST_CMD_4_INTCLR); ++ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_4, ++ AIR_PHY_MCU_CMD_4_INTCLR); + if (ret < 0) + return ret; + @@ -1105,6 +1129,7 @@ Signed-off-by: Eric Woudstra + { PHY_ID_MATCH_MODEL(EN8811H_PHY_ID) }, + { } +}; ++ +MODULE_DEVICE_TABLE(mdio, en8811h_tbl); +MODULE_FIRMWARE(EN8811H_MD32_DM); +MODULE_FIRMWARE(EN8811H_MD32_DSP); diff --git a/target/linux/generic/backport-6.1/799-v6.10-net-phy-air_en8811h-fix-some-error-codes.patch b/target/linux/generic/backport-6.1/799-v6.10-net-phy-air_en8811h-fix-some-error-codes.patch new file mode 100644 index 00000000000000..1bd0eefe77b512 --- /dev/null +++ b/target/linux/generic/backport-6.1/799-v6.10-net-phy-air_en8811h-fix-some-error-codes.patch @@ -0,0 +1,47 @@ +From 87c33315af380ca12a2e59ac94edad4fe0481b4c Mon Sep 17 00:00:00 2001 +From: Dan Carpenter +Date: Fri, 5 Apr 2024 13:08:59 +0300 +Subject: [PATCH] net: phy: air_en8811h: fix some error codes + +These error paths accidentally return "ret" which is zero/success +instead of the correct error code. + +Fixes: 71e79430117d ("net: phy: air_en8811h: Add the Airoha EN8811H PHY driver") +Signed-off-by: Dan Carpenter +Reviewed-by: Simon Horman +Link: https://lore.kernel.org/r/7ef2e230-dfb7-4a77-8973-9e5be1a99fc2@moroto.mountain +Signed-off-by: Jakub Kicinski +--- + drivers/net/phy/air_en8811h.c | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +--- a/drivers/net/phy/air_en8811h.c ++++ b/drivers/net/phy/air_en8811h.c +@@ -272,11 +272,11 @@ static int __air_buckpbus_reg_read(struc + + pbus_data_high = __phy_read(phydev, AIR_BPBUS_RD_DATA_HIGH); + if (pbus_data_high < 0) +- return ret; ++ return pbus_data_high; + + pbus_data_low = __phy_read(phydev, AIR_BPBUS_RD_DATA_LOW); + if (pbus_data_low < 0) +- return ret; ++ return pbus_data_low; + + *pbus_data = pbus_data_low | (pbus_data_high << 16); + return 0; +@@ -323,11 +323,11 @@ static int __air_buckpbus_reg_modify(str + + pbus_data_high = __phy_read(phydev, AIR_BPBUS_RD_DATA_HIGH); + if (pbus_data_high < 0) +- return ret; ++ return pbus_data_high; + + pbus_data_low = __phy_read(phydev, AIR_BPBUS_RD_DATA_LOW); + if (pbus_data_low < 0) +- return ret; ++ return pbus_data_low; + + pbus_data_old = pbus_data_low | (pbus_data_high << 16); + pbus_data_new = (pbus_data_old & ~mask) | set; diff --git a/target/linux/generic/backport-6.1/832-v6.7-net-phy-amd-Support-the-Altima-AMI101L.patch b/target/linux/generic/backport-6.1/832-v6.7-net-phy-amd-Support-the-Altima-AMI101L.patch index 2969462838c684..e8e73c1e5f04ac 100644 --- a/target/linux/generic/backport-6.1/832-v6.7-net-phy-amd-Support-the-Altima-AMI101L.patch +++ b/target/linux/generic/backport-6.1/832-v6.7-net-phy-amd-Support-the-Altima-AMI101L.patch @@ -16,8 +16,8 @@ Signed-off-by: Linus Walleij --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig -@@ -72,9 +72,9 @@ config SFP - comment "MII PHY device drivers" +@@ -77,9 +77,9 @@ config AIR_EN8811H_PHY + Currently supports the Airoha EN8811H PHY. config AMD_PHY - tristate "AMD PHYs" diff --git a/target/linux/generic/backport-6.6/301-v6.9-kernel.h-removed-REPEAT_BYTE-from-kernel.h.patch b/target/linux/generic/backport-6.6/301-v6.9-kernel.h-removed-REPEAT_BYTE-from-kernel.h.patch new file mode 100644 index 00000000000000..adc924c09a6268 --- /dev/null +++ b/target/linux/generic/backport-6.6/301-v6.9-kernel.h-removed-REPEAT_BYTE-from-kernel.h.patch @@ -0,0 +1,161 @@ +From 66a5c40f60f5d88ad8d47ba6a4ba05892853fa1f Mon Sep 17 00:00:00 2001 +From: Tanzir Hasan +Date: Tue, 26 Dec 2023 18:00:00 +0000 +Subject: [PATCH] kernel.h: removed REPEAT_BYTE from kernel.h + +This patch creates wordpart.h and includes it in asm/word-at-a-time.h +for all architectures. WORD_AT_A_TIME_CONSTANTS depends on kernel.h +because of REPEAT_BYTE. Moving this to another header and including it +where necessary allows us to not include the bloated kernel.h. Making +this implicit dependency on REPEAT_BYTE explicit allows for later +improvements in the lib/string.c inclusion list. + +Suggested-by: Al Viro +Suggested-by: Andy Shevchenko +Signed-off-by: Tanzir Hasan +Reviewed-by: Andy Shevchenko +Link: https://lore.kernel.org/r/20231226-libstringheader-v6-1-80aa08c7652c@google.com +Signed-off-by: Kees Cook +--- + arch/arm/include/asm/word-at-a-time.h | 3 ++- + arch/arm64/include/asm/word-at-a-time.h | 3 ++- + arch/powerpc/include/asm/word-at-a-time.h | 4 ++-- + arch/riscv/include/asm/word-at-a-time.h | 3 ++- + arch/s390/include/asm/word-at-a-time.h | 3 ++- + arch/sh/include/asm/word-at-a-time.h | 2 ++ + arch/x86/include/asm/word-at-a-time.h | 3 ++- + arch/x86/kvm/mmu/mmu.c | 1 + + fs/namei.c | 2 +- + include/asm-generic/word-at-a-time.h | 3 ++- + include/linux/kernel.h | 8 -------- + include/linux/wordpart.h | 13 +++++++++++++ + 12 files changed, 31 insertions(+), 17 deletions(-) + create mode 100644 include/linux/wordpart.h + +--- a/arch/arm/include/asm/word-at-a-time.h ++++ b/arch/arm/include/asm/word-at-a-time.h +@@ -8,7 +8,8 @@ + * Little-endian word-at-a-time zero byte handling. + * Heavily based on the x86 algorithm. + */ +-#include ++#include ++#include + + struct word_at_a_time { + const unsigned long one_bits, high_bits; +--- a/arch/arm64/include/asm/word-at-a-time.h ++++ b/arch/arm64/include/asm/word-at-a-time.h +@@ -9,7 +9,8 @@ + + #ifndef __AARCH64EB__ + +-#include ++#include ++#include + + struct word_at_a_time { + const unsigned long one_bits, high_bits; +--- a/arch/powerpc/include/asm/word-at-a-time.h ++++ b/arch/powerpc/include/asm/word-at-a-time.h +@@ -4,8 +4,8 @@ + /* + * Word-at-a-time interfaces for PowerPC. + */ +- +-#include ++#include ++#include + #include + #include + +--- a/arch/sh/include/asm/word-at-a-time.h ++++ b/arch/sh/include/asm/word-at-a-time.h +@@ -5,6 +5,8 @@ + #ifdef CONFIG_CPU_BIG_ENDIAN + # include + #else ++#include ++#include + /* + * Little-endian version cribbed from x86. + */ +--- a/arch/x86/include/asm/word-at-a-time.h ++++ b/arch/x86/include/asm/word-at-a-time.h +@@ -2,7 +2,8 @@ + #ifndef _ASM_WORD_AT_A_TIME_H + #define _ASM_WORD_AT_A_TIME_H + +-#include ++#include ++#include + + /* + * This is largely generic for little-endian machines, but the +--- a/arch/x86/kvm/mmu/mmu.c ++++ b/arch/x86/kvm/mmu/mmu.c +@@ -47,6 +47,7 @@ + #include + #include + #include ++#include + + #include + #include +--- a/fs/namei.c ++++ b/fs/namei.c +@@ -17,8 +17,8 @@ + + #include + #include +-#include + #include ++#include + #include + #include + #include +--- a/include/asm-generic/word-at-a-time.h ++++ b/include/asm-generic/word-at-a-time.h +@@ -2,7 +2,8 @@ + #ifndef _ASM_WORD_AT_A_TIME_H + #define _ASM_WORD_AT_A_TIME_H + +-#include ++#include ++#include + #include + + #ifdef __BIG_ENDIAN +--- a/include/linux/kernel.h ++++ b/include/linux/kernel.h +@@ -38,14 +38,6 @@ + + #define STACK_MAGIC 0xdeadbeef + +-/** +- * REPEAT_BYTE - repeat the value @x multiple times as an unsigned long value +- * @x: value to repeat +- * +- * NOTE: @x is not checked for > 0xff; larger values produce odd results. +- */ +-#define REPEAT_BYTE(x) ((~0ul / 0xff) * (x)) +- + /* generic data direction definitions */ + #define READ 0 + #define WRITE 1 +--- /dev/null ++++ b/include/linux/wordpart.h +@@ -0,0 +1,13 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++ ++#ifndef _LINUX_WORDPART_H ++#define _LINUX_WORDPART_H ++/** ++ * REPEAT_BYTE - repeat the value @x multiple times as an unsigned long value ++ * @x: value to repeat ++ * ++ * NOTE: @x is not checked for > 0xff; larger values produce odd results. ++ */ ++#define REPEAT_BYTE(x) ((~0ul / 0xff) * (x)) ++ ++#endif // _LINUX_WORDPART_H diff --git a/target/linux/generic/backport-6.6/302-v6.9-kernel.h-Move-upper_-_bits-and-lower_-_bits-to-wordp.patch b/target/linux/generic/backport-6.6/302-v6.9-kernel.h-Move-upper_-_bits-and-lower_-_bits-to-wordp.patch new file mode 100644 index 00000000000000..b9c40e6206a8c8 --- /dev/null +++ b/target/linux/generic/backport-6.6/302-v6.9-kernel.h-Move-upper_-_bits-and-lower_-_bits-to-wordp.patch @@ -0,0 +1,107 @@ +From adeb04362d74188c1e22ccb824b15a0a7b3de2f4 Mon Sep 17 00:00:00 2001 +From: Andy Shevchenko +Date: Wed, 14 Feb 2024 19:26:32 +0200 +Subject: [PATCH] kernel.h: Move upper_*_bits() and lower_*_bits() to + wordpart.h + +The wordpart.h header is collecting APIs related to the handling +parts of the word (usually in byte granularity). The upper_*_bits() +and lower_*_bits() are good candidates to be moved to there. + +This helps to clean up header dependency hell with regard to kernel.h +as the latter gathers completely unrelated stuff together and slows +down compilation (especially when it's included into other header). + +Signed-off-by: Andy Shevchenko +Link: https://lore.kernel.org/r/20240214172752.3605073-1-andriy.shevchenko@linux.intel.com +Reviewed-by: Randy Dunlap +Signed-off-by: Kees Cook +--- + include/linux/kernel.h | 30 ++---------------------------- + include/linux/wordpart.h | 29 +++++++++++++++++++++++++++++ + 2 files changed, 31 insertions(+), 28 deletions(-) + +--- a/include/linux/kernel.h ++++ b/include/linux/kernel.h +@@ -32,6 +32,8 @@ + #include + #include + #include ++#include ++ + #include + + #include +@@ -57,34 +59,6 @@ + } \ + ) + +-/** +- * upper_32_bits - return bits 32-63 of a number +- * @n: the number we're accessing +- * +- * A basic shift-right of a 64- or 32-bit quantity. Use this to suppress +- * the "right shift count >= width of type" warning when that quantity is +- * 32-bits. +- */ +-#define upper_32_bits(n) ((u32)(((n) >> 16) >> 16)) +- +-/** +- * lower_32_bits - return bits 0-31 of a number +- * @n: the number we're accessing +- */ +-#define lower_32_bits(n) ((u32)((n) & 0xffffffff)) +- +-/** +- * upper_16_bits - return bits 16-31 of a number +- * @n: the number we're accessing +- */ +-#define upper_16_bits(n) ((u16)((n) >> 16)) +- +-/** +- * lower_16_bits - return bits 0-15 of a number +- * @n: the number we're accessing +- */ +-#define lower_16_bits(n) ((u16)((n) & 0xffff)) +- + struct completion; + struct user; + +--- a/include/linux/wordpart.h ++++ b/include/linux/wordpart.h +@@ -2,6 +2,35 @@ + + #ifndef _LINUX_WORDPART_H + #define _LINUX_WORDPART_H ++ ++/** ++ * upper_32_bits - return bits 32-63 of a number ++ * @n: the number we're accessing ++ * ++ * A basic shift-right of a 64- or 32-bit quantity. Use this to suppress ++ * the "right shift count >= width of type" warning when that quantity is ++ * 32-bits. ++ */ ++#define upper_32_bits(n) ((u32)(((n) >> 16) >> 16)) ++ ++/** ++ * lower_32_bits - return bits 0-31 of a number ++ * @n: the number we're accessing ++ */ ++#define lower_32_bits(n) ((u32)((n) & 0xffffffff)) ++ ++/** ++ * upper_16_bits - return bits 16-31 of a number ++ * @n: the number we're accessing ++ */ ++#define upper_16_bits(n) ((u16)((n) >> 16)) ++ ++/** ++ * lower_16_bits - return bits 0-15 of a number ++ * @n: the number we're accessing ++ */ ++#define lower_16_bits(n) ((u16)((n) & 0xffff)) ++ + /** + * REPEAT_BYTE - repeat the value @x multiple times as an unsigned long value + * @x: value to repeat diff --git a/target/linux/generic/backport-6.6/790-53-v6.10-net-dsa-mt7530-do-not-set-MT7530_P5_DIS-when-PHY-.patch b/target/linux/generic/backport-6.6/790-53-v6.10-net-dsa-mt7530-do-not-set-MT7530_P5_DIS-when-PHY-.patch new file mode 100644 index 00000000000000..cee3d01728bd23 --- /dev/null +++ b/target/linux/generic/backport-6.6/790-53-v6.10-net-dsa-mt7530-do-not-set-MT7530_P5_DIS-when-PHY-.patch @@ -0,0 +1,45 @@ +From 16e6592cd5c5bd74d8890973489f60176c692614 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= +Date: Sun, 28 Apr 2024 12:19:58 +0300 +Subject: [PATCH] net: dsa: mt7530: do not set MT7530_P5_DIS when PHY muxing is + being used +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +DSA initalises the ds->num_ports amount of ports in +dsa_switch_touch_ports(). When the PHY muxing feature is in use, port 5 +won't be defined in the device tree. Because of this, the type member of +the dsa_port structure for this port will be assigned DSA_PORT_TYPE_UNUSED. +The dsa_port_setup() function calls ds->ops->port_disable() when the port +type is DSA_PORT_TYPE_UNUSED. + +The MT7530_P5_DIS bit is unset in mt7530_setup() when PHY muxing is being +used. mt7530_port_disable() which is assigned to ds->ops->port_disable() is +called afterwards. Currently, mt7530_port_disable() sets MT7530_P5_DIS +which breaks network connectivity when PHY muxing is being used. + +Therefore, do not set MT7530_P5_DIS when PHY muxing is being used. + +Fixes: 377174c5760c ("net: dsa: mt7530: move MT753X_MTRAP operations for MT7530") +Reported-by: Daniel Golle +Signed-off-by: Arınç ÃœNAL +Reviewed-by: Andrew Lunn +Link: https://lore.kernel.org/r/20240428-for-netnext-mt7530-do-not-disable-port5-when-phy-muxing-v2-1-bb7c37d293f8@arinc9.com +Signed-off-by: Paolo Abeni +--- + drivers/net/dsa/mt7530.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/drivers/net/dsa/mt7530.c ++++ b/drivers/net/dsa/mt7530.c +@@ -1220,7 +1220,8 @@ mt7530_port_disable(struct dsa_switch *d + if (priv->id != ID_MT7530 && priv->id != ID_MT7621) + return; + +- if (port == 5) ++ /* Do not set MT7530_P5_DIS when port 5 is being used for PHY muxing. */ ++ if (port == 5 && priv->p5_mode == GMAC5) + mt7530_set(priv, MT753X_MTRAP, MT7530_P5_DIS); + else if (port == 6) + mt7530_set(priv, MT753X_MTRAP, MT7530_P6_DIS); diff --git a/target/linux/generic/backport-6.6/790-54-v6.10-796-net-dsa-mt7530-detect-PHY-muxing-when-PHY-is-defined.patch b/target/linux/generic/backport-6.6/790-54-v6.10-796-net-dsa-mt7530-detect-PHY-muxing-when-PHY-is-defined.patch new file mode 100644 index 00000000000000..d369c4e05ec9ad --- /dev/null +++ b/target/linux/generic/backport-6.6/790-54-v6.10-796-net-dsa-mt7530-detect-PHY-muxing-when-PHY-is-defined.patch @@ -0,0 +1,45 @@ +From d8dcf5bd6d0eace9f7c1daa14b63b3925b09d033 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= +Date: Tue, 30 Apr 2024 08:01:33 +0300 +Subject: [PATCH] net: dsa: mt7530: detect PHY muxing when PHY is defined on + switch MDIO bus +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Currently, the MT7530 DSA subdriver configures the MT7530 switch to provide +direct access to switch PHYs, meaning, the switch PHYs listen on the MDIO +bus the switch listens on. The PHY muxing feature makes use of this. + +This is problematic as the PHY may be attached before the switch is +initialised, in which case, the PHY will fail to be attached. + +Since commit 91374ba537bd ("net: dsa: mt7530: support OF-based registration +of switch MDIO bus"), we can describe the switch PHYs on the MDIO bus of +the switch on the device tree. Extend the check to detect PHY muxing when +the PHY is defined on the MDIO bus of the switch on the device tree. + +When the PHY is described this way, the switch will be initialised first, +then the switch MDIO bus will be registered. Only after these steps, the +PHY will be attached. + +Signed-off-by: Arınç ÃœNAL +Reviewed-by: Daniel Golle +Link: https://lore.kernel.org/r/20240430-b4-for-netnext-mt7530-use-switch-mdio-bus-for-phy-muxing-v2-1-9104d886d0db@arinc9.com +Signed-off-by: Paolo Abeni +--- + drivers/net/dsa/mt7530.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/drivers/net/dsa/mt7530.c ++++ b/drivers/net/dsa/mt7530.c +@@ -2484,7 +2484,8 @@ mt7530_setup(struct dsa_switch *ds) + if (!phy_node) + continue; + +- if (phy_node->parent == priv->dev->of_node->parent) { ++ if (phy_node->parent == priv->dev->of_node->parent || ++ phy_node->parent->parent == priv->dev->of_node) { + ret = of_get_phy_mode(mac_np, &interface); + if (ret && ret != -ENODEV) { + of_node_put(mac_np); diff --git a/target/linux/generic/pending-6.6/750-net-phy-airoha-Add-the-Airoha-EN8811H-PHY-driver.patch b/target/linux/generic/backport-6.6/798-v6.10-net-phy-air_en8811h-Add-the-Airoha-EN8811H-PHY-drive.patch similarity index 61% rename from target/linux/generic/pending-6.6/750-net-phy-airoha-Add-the-Airoha-EN8811H-PHY-driver.patch rename to target/linux/generic/backport-6.6/798-v6.10-net-phy-air_en8811h-Add-the-Airoha-EN8811H-PHY-drive.patch index c811e40d49004b..5b627cf44975c2 100644 --- a/target/linux/generic/pending-6.6/750-net-phy-airoha-Add-the-Airoha-EN8811H-PHY-driver.patch +++ b/target/linux/generic/backport-6.6/798-v6.10-net-phy-air_en8811h-Add-the-Airoha-EN8811H-PHY-drive.patch @@ -1,83 +1,28 @@ -From patchwork Tue Feb 6 19:47:51 2024 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Eric Woudstra -X-Patchwork-Id: 13547762 -X-Patchwork-Delegate: kuba@kernel.org +From 71e79430117d56c409c5ea485a263bc0d8083390 Mon Sep 17 00:00:00 2001 From: Eric Woudstra -To: "David S. Miller" , - Eric Dumazet , - Jakub Kicinski , - Paolo Abeni , - Rob Herring , - Krzysztof Kozlowski , - Conor Dooley , - Andrew Lunn , - Heiner Kallweit , - Russell King , - Matthias Brugger , - AngeloGioacchino Del Regno , - "Frank Wunderlich" , - Daniel Golle , - Lucien Jheng , - Zhi-Jun You -Cc: netdev@vger.kernel.org, - devicetree@vger.kernel.org, - Eric Woudstra -Subject: [PATCH net-next 2/2] net: phy: air_en8811h: Add the Airoha EN8811H - PHY driver -Date: Tue, 6 Feb 2024 20:47:51 +0100 -Message-ID: <20240206194751.1901802-3-ericwouds@gmail.com> -X-Mailer: git-send-email 2.42.1 -In-Reply-To: <20240206194751.1901802-1-ericwouds@gmail.com> -References: <20240206194751.1901802-1-ericwouds@gmail.com> -Precedence: bulk -X-Mailing-List: netdev@vger.kernel.org -List-Id: -List-Subscribe: -List-Unsubscribe: -MIME-Version: 1.0 -X-Patchwork-Delegate: kuba@kernel.org +Date: Tue, 26 Mar 2024 17:23:05 +0100 +Subject: [PATCH] net: phy: air_en8811h: Add the Airoha EN8811H PHY driver -* Source originated from airoha's en8811h v1.2.1 driver - * Moved air_en8811h.h to air_en8811h.c - * Removed air_pbus_reg_write() as it writes to another device on mdio-bus - * Load firmware from /lib/firmware/airoha/ instead of /lib/firmware/ - * Added .get_rate_matching() - * Use generic phy_read/write() and phy_read/write_mmd() - * Edited .get_features() to use generic C45 functions - * Edited .config_aneg() and .read_status() to use a mix of generic C22/C45 - * Use led handling functions from mediatek-ge-soc.c - * Simplified led handling by storing led rules - * Cleanup macro definitions - * Cleanup code to pass checkpatch.pl - * General code cleanup +Add the driver for the Airoha EN8811H 2.5 Gigabit PHY. The phy supports +100/1000/2500 Mbps with auto negotiation only. -Changes from original RFC patch: +The driver uses two firmware files, for which updated versions are added to +linux-firmware already. - * Use the correct order in Kconfig and Makefile - * Change some register naming to correspond with datasheet - * Use phy_driver .read_page() and .write_page() - * Use module_phy_driver() - * Use get_unaligned_le16() instead of macro - * In .config_aneg() and .read_status() use genphy_xxx() C22 - * Use another vendor register to read real speed - * Load firmware only once and store firmware version - * Apply 2.5G LPA work-around (firmware before 24011202) - * Read 2.5G LPA from vendor register (firmware 24011202 and later) - -Changes to be committed: - modified: drivers/net/phy/Kconfig - modified: drivers/net/phy/Makefile - new file: drivers/net/phy/air_en8811h.c +Note: At phy-address + 8 there is another device on the mdio bus, that +belongs to the EN881H. While the original driver writes to it, Airoha +has confirmed this is not needed. Therefore, communication with this +device is not included in this driver. Signed-off-by: Eric Woudstra +Reviewed-by: Andrew Lunn +Link: https://lore.kernel.org/r/20240326162305.303598-3-ericwouds@gmail.com +Signed-off-by: Jakub Kicinski --- drivers/net/phy/Kconfig | 5 + drivers/net/phy/Makefile | 1 + - drivers/net/phy/air_en8811h.c | 1006 +++++++++++++++++++++++++++++++++ - 3 files changed, 1012 insertions(+) + drivers/net/phy/air_en8811h.c | 1086 +++++++++++++++++++++++++++++++++ + 3 files changed, 1092 insertions(+) create mode 100644 drivers/net/phy/air_en8811h.c --- a/drivers/net/phy/Kconfig @@ -92,7 +37,7 @@ Signed-off-by: Eric Woudstra + Currently supports the Airoha EN8811H PHY. + config AMD_PHY - tristate "AMD and Altima PHYs" + tristate "AMD PHYs" help --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -106,12 +51,10 @@ Signed-off-by: Eric Woudstra obj-$(CONFIG_AX88796B_PHY) += ax88796b.o --- /dev/null +++ b/drivers/net/phy/air_en8811h.c -@@ -0,0 +1,1006 @@ +@@ -0,0 +1,1086 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* -+ * Driver for Airoha Ethernet PHYs -+ * -+ * Currently supporting the EN8811H. ++ * Driver for the Airoha EN8811H 2.5 Gigabit PHY. + * + * Limitations of the EN8811H: + * - Only full duplex supported @@ -125,6 +68,7 @@ Signed-off-by: Eric Woudstra +#include +#include +#include ++#include +#include + +#define EN8811H_PHY_ID 0x03a2a411 @@ -135,12 +79,8 @@ Signed-off-by: Eric Woudstra +#define AIR_FW_ADDR_DM 0x00000000 +#define AIR_FW_ADDR_DSP 0x00100000 + -+/* u32 (DWORD) component macros */ -+#define LOWORD(d) ((u16)(u32)(d)) -+#define HIWORD(d) ((u16)(((u32)(d)) >> 16)) -+ +/* MII Registers */ -+#define AIR_AUX_CTRL_STATUS 0x1d ++#define AIR_AUX_CTRL_STATUS 0x1d +#define AIR_AUX_CTRL_STATUS_SPEED_MASK GENMASK(4, 2) +#define AIR_AUX_CTRL_STATUS_SPEED_100 0x4 +#define AIR_AUX_CTRL_STATUS_SPEED_1000 0x8 @@ -151,32 +91,32 @@ Signed-off-by: Eric Woudstra +#define AIR_PHY_PAGE_EXTENDED_4 0x0004 + +/* MII Registers Page 4*/ -+#define AIR_PBUS_MODE 0x10 -+#define AIR_PBUS_MODE_ADDR_FIXED 0x0000 -+#define AIR_PBUS_MODE_ADDR_INCR BIT(15) -+#define AIR_PBUS_WR_ADDR_HIGH 0x11 -+#define AIR_PBUS_WR_ADDR_LOW 0x12 -+#define AIR_PBUS_WR_DATA_HIGH 0x13 -+#define AIR_PBUS_WR_DATA_LOW 0x14 -+#define AIR_PBUS_RD_ADDR_HIGH 0x15 -+#define AIR_PBUS_RD_ADDR_LOW 0x16 -+#define AIR_PBUS_RD_DATA_HIGH 0x17 -+#define AIR_PBUS_RD_DATA_LOW 0x18 ++#define AIR_BPBUS_MODE 0x10 ++#define AIR_BPBUS_MODE_ADDR_FIXED 0x0000 ++#define AIR_BPBUS_MODE_ADDR_INCR BIT(15) ++#define AIR_BPBUS_WR_ADDR_HIGH 0x11 ++#define AIR_BPBUS_WR_ADDR_LOW 0x12 ++#define AIR_BPBUS_WR_DATA_HIGH 0x13 ++#define AIR_BPBUS_WR_DATA_LOW 0x14 ++#define AIR_BPBUS_RD_ADDR_HIGH 0x15 ++#define AIR_BPBUS_RD_ADDR_LOW 0x16 ++#define AIR_BPBUS_RD_DATA_HIGH 0x17 ++#define AIR_BPBUS_RD_DATA_LOW 0x18 + +/* Registers on MDIO_MMD_VEND1 */ +#define EN8811H_PHY_FW_STATUS 0x8009 +#define EN8811H_PHY_READY 0x02 + -+#define AIR_PHY_HOST_CMD_1 0x800c -+#define AIR_PHY_HOST_CMD_1_MODE1 0x0 -+#define AIR_PHY_HOST_CMD_2 0x800d -+#define AIR_PHY_HOST_CMD_2_MODE1 0x0 -+#define AIR_PHY_HOST_CMD_3 0x800e -+#define AIR_PHY_HOST_CMD_3_MODE1 0x1101 -+#define AIR_PHY_HOST_CMD_3_DOCMD 0x1100 -+#define AIR_PHY_HOST_CMD_4 0x800f -+#define AIR_PHY_HOST_CMD_4_MODE1 0x0002 -+#define AIR_PHY_HOST_CMD_4_INTCLR 0x00e4 ++#define AIR_PHY_MCU_CMD_1 0x800c ++#define AIR_PHY_MCU_CMD_1_MODE1 0x0 ++#define AIR_PHY_MCU_CMD_2 0x800d ++#define AIR_PHY_MCU_CMD_2_MODE1 0x0 ++#define AIR_PHY_MCU_CMD_3 0x800e ++#define AIR_PHY_MCU_CMD_3_MODE1 0x1101 ++#define AIR_PHY_MCU_CMD_3_DOCMD 0x1100 ++#define AIR_PHY_MCU_CMD_4 0x800f ++#define AIR_PHY_MCU_CMD_4_MODE1 0x0002 ++#define AIR_PHY_MCU_CMD_4_INTCLR 0x00e4 + +/* Registers on MDIO_MMD_VEND2 */ +#define AIR_PHY_LED_BCR 0x021 @@ -235,28 +175,21 @@ Signed-off-by: Eric Woudstra +#define EN8811H_FW_CTRL_2 0x800000 +#define EN8811H_FW_CTRL_2_LOADING BIT(11) + ++/* Led definitions */ +#define EN8811H_LED_COUNT 3 + -+/* GPIO5 <-> BASE_T_LED0 -+ * GPIO4 <-> BASE_T_LED1 -+ * GPIO3 <-> BASE_T_LED2 -+ * -+ * Default setup suitable for 2 leds connected: -+ * 100M link up triggers led0, only led0 blinking on traffic -+ * 1000M link up triggers led1, only led1 blinking on traffic -+ * 2500M link up triggers led0 and led1, both blinking on traffic -+ * Also suitable for 1 led connected: -+ * any link up triggers led2 ++/* Default LED setup: ++ * GPIO5 <-> LED0 On: Link detected, blink Rx/Tx ++ * GPIO4 <-> LED1 On: Link detected at 2500 or 1000 Mbps ++ * GPIO3 <-> LED2 On: Link detected at 2500 or 100 Mbps + */ -+#define AIR_DEFAULT_TRIGGER_LED0 (BIT(TRIGGER_NETDEV_LINK_2500) | \ -+ BIT(TRIGGER_NETDEV_LINK_100) | \ ++#define AIR_DEFAULT_TRIGGER_LED0 (BIT(TRIGGER_NETDEV_LINK) | \ + BIT(TRIGGER_NETDEV_RX) | \ + BIT(TRIGGER_NETDEV_TX)) +#define AIR_DEFAULT_TRIGGER_LED1 (BIT(TRIGGER_NETDEV_LINK_2500) | \ -+ BIT(TRIGGER_NETDEV_LINK_1000) | \ -+ BIT(TRIGGER_NETDEV_RX) | \ -+ BIT(TRIGGER_NETDEV_TX)) -+#define AIR_DEFAULT_TRIGGER_LED2 BIT(TRIGGER_NETDEV_LINK) ++ BIT(TRIGGER_NETDEV_LINK_1000)) ++#define AIR_DEFAULT_TRIGGER_LED2 (BIT(TRIGGER_NETDEV_LINK_2500) | \ ++ BIT(TRIGGER_NETDEV_LINK_100)) + +struct led { + unsigned long rules; @@ -265,6 +198,7 @@ Signed-off-by: Eric Woudstra + +struct en8811h_priv { + u32 firmware_version; ++ bool mcu_needs_restart; + struct led led[EN8811H_LED_COUNT]; +}; + @@ -274,12 +208,12 @@ Signed-off-by: Eric Woudstra +}; + +enum { -+ AIR_PHY_LED_DUR_BLINK_32M, -+ AIR_PHY_LED_DUR_BLINK_64M, -+ AIR_PHY_LED_DUR_BLINK_128M, -+ AIR_PHY_LED_DUR_BLINK_256M, -+ AIR_PHY_LED_DUR_BLINK_512M, -+ AIR_PHY_LED_DUR_BLINK_1024M, ++ AIR_PHY_LED_DUR_BLINK_32MS, ++ AIR_PHY_LED_DUR_BLINK_64MS, ++ AIR_PHY_LED_DUR_BLINK_128MS, ++ AIR_PHY_LED_DUR_BLINK_256MS, ++ AIR_PHY_LED_DUR_BLINK_512MS, ++ AIR_PHY_LED_DUR_BLINK_1024MS, +}; + +enum { @@ -298,16 +232,16 @@ Signed-off-by: Eric Woudstra +}; + +#define AIR_PHY_LED_DUR_UNIT 1024 -+#define AIR_PHY_LED_DUR (AIR_PHY_LED_DUR_UNIT << AIR_PHY_LED_DUR_BLINK_64M) ++#define AIR_PHY_LED_DUR (AIR_PHY_LED_DUR_UNIT << AIR_PHY_LED_DUR_BLINK_64MS) + -+static const unsigned long en8811h_led_trig = (BIT(TRIGGER_NETDEV_FULL_DUPLEX) | -+ BIT(TRIGGER_NETDEV_LINK) | -+ BIT(TRIGGER_NETDEV_LINK_10) | -+ BIT(TRIGGER_NETDEV_LINK_100) | -+ BIT(TRIGGER_NETDEV_LINK_1000) | -+ BIT(TRIGGER_NETDEV_LINK_2500) | -+ BIT(TRIGGER_NETDEV_RX) | -+ BIT(TRIGGER_NETDEV_TX)); ++static const unsigned long en8811h_led_trig = BIT(TRIGGER_NETDEV_FULL_DUPLEX) | ++ BIT(TRIGGER_NETDEV_LINK) | ++ BIT(TRIGGER_NETDEV_LINK_10) | ++ BIT(TRIGGER_NETDEV_LINK_100) | ++ BIT(TRIGGER_NETDEV_LINK_1000) | ++ BIT(TRIGGER_NETDEV_LINK_2500) | ++ BIT(TRIGGER_NETDEV_RX) | ++ BIT(TRIGGER_NETDEV_TX); + +static int air_phy_read_page(struct phy_device *phydev) +{ @@ -324,23 +258,27 @@ Signed-off-by: Eric Woudstra +{ + int ret; + -+ ret = __phy_write(phydev, AIR_PBUS_MODE, AIR_PBUS_MODE_ADDR_FIXED); ++ ret = __phy_write(phydev, AIR_BPBUS_MODE, AIR_BPBUS_MODE_ADDR_FIXED); + if (ret < 0) + return ret; + -+ ret = __phy_write(phydev, AIR_PBUS_WR_ADDR_HIGH, HIWORD(pbus_address)); ++ ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_HIGH, ++ upper_16_bits(pbus_address)); + if (ret < 0) + return ret; + -+ ret = __phy_write(phydev, AIR_PBUS_WR_ADDR_LOW, LOWORD(pbus_address)); ++ ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_LOW, ++ lower_16_bits(pbus_address)); + if (ret < 0) + return ret; + -+ ret = __phy_write(phydev, AIR_PBUS_WR_DATA_HIGH, HIWORD(pbus_data)); ++ ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_HIGH, ++ upper_16_bits(pbus_data)); + if (ret < 0) + return ret; + -+ ret = __phy_write(phydev, AIR_PBUS_WR_DATA_LOW, LOWORD(pbus_data)); ++ ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_LOW, ++ lower_16_bits(pbus_data)); + if (ret < 0) + return ret; + @@ -350,17 +288,20 @@ Signed-off-by: Eric Woudstra +static int air_buckpbus_reg_write(struct phy_device *phydev, + u32 pbus_address, u32 pbus_data) +{ -+ int ret, saved_page; ++ int saved_page; ++ int ret = 0; + + saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4); + -+ ret = __air_buckpbus_reg_write(phydev, pbus_address, pbus_data); -+ if (ret < 0) -+ phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__, -+ pbus_address, ret); ++ if (saved_page >= 0) { ++ ret = __air_buckpbus_reg_write(phydev, pbus_address, ++ pbus_data); ++ if (ret < 0) ++ phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__, ++ pbus_address, ret); ++ } + + return phy_restore_page(phydev, saved_page, ret); -+; +} + +static int __air_buckpbus_reg_read(struct phy_device *phydev, @@ -369,41 +310,122 @@ Signed-off-by: Eric Woudstra + int pbus_data_low, pbus_data_high; + int ret; + -+ ret = __phy_write(phydev, AIR_PBUS_MODE, AIR_PBUS_MODE_ADDR_FIXED); ++ ret = __phy_write(phydev, AIR_BPBUS_MODE, AIR_BPBUS_MODE_ADDR_FIXED); + if (ret < 0) + return ret; + -+ ret = __phy_write(phydev, AIR_PBUS_RD_ADDR_HIGH, HIWORD(pbus_address)); ++ ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_HIGH, ++ upper_16_bits(pbus_address)); + if (ret < 0) + return ret; + -+ ret = __phy_write(phydev, AIR_PBUS_RD_ADDR_LOW, LOWORD(pbus_address)); ++ ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_LOW, ++ lower_16_bits(pbus_address)); + if (ret < 0) + return ret; + -+ pbus_data_high = __phy_read(phydev, AIR_PBUS_RD_DATA_HIGH); ++ pbus_data_high = __phy_read(phydev, AIR_BPBUS_RD_DATA_HIGH); + if (pbus_data_high < 0) + return ret; + -+ pbus_data_low = __phy_read(phydev, AIR_PBUS_RD_DATA_LOW); ++ pbus_data_low = __phy_read(phydev, AIR_BPBUS_RD_DATA_LOW); + if (pbus_data_low < 0) + return ret; + -+ *pbus_data = (u16)pbus_data_low | ((u32)(u16)pbus_data_high << 16); ++ *pbus_data = pbus_data_low | (pbus_data_high << 16); + return 0; +} + +static int air_buckpbus_reg_read(struct phy_device *phydev, + u32 pbus_address, u32 *pbus_data) +{ -+ int ret, saved_page; ++ int saved_page; ++ int ret = 0; + + saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4); + -+ ret = __air_buckpbus_reg_read(phydev, pbus_address, pbus_data); ++ if (saved_page >= 0) { ++ ret = __air_buckpbus_reg_read(phydev, pbus_address, pbus_data); ++ if (ret < 0) ++ phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__, ++ pbus_address, ret); ++ } ++ ++ return phy_restore_page(phydev, saved_page, ret); ++} ++ ++static int __air_buckpbus_reg_modify(struct phy_device *phydev, ++ u32 pbus_address, u32 mask, u32 set) ++{ ++ int pbus_data_low, pbus_data_high; ++ u32 pbus_data_old, pbus_data_new; ++ int ret; ++ ++ ret = __phy_write(phydev, AIR_BPBUS_MODE, AIR_BPBUS_MODE_ADDR_FIXED); ++ if (ret < 0) ++ return ret; ++ ++ ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_HIGH, ++ upper_16_bits(pbus_address)); ++ if (ret < 0) ++ return ret; ++ ++ ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_LOW, ++ lower_16_bits(pbus_address)); ++ if (ret < 0) ++ return ret; ++ ++ pbus_data_high = __phy_read(phydev, AIR_BPBUS_RD_DATA_HIGH); ++ if (pbus_data_high < 0) ++ return ret; ++ ++ pbus_data_low = __phy_read(phydev, AIR_BPBUS_RD_DATA_LOW); ++ if (pbus_data_low < 0) ++ return ret; ++ ++ pbus_data_old = pbus_data_low | (pbus_data_high << 16); ++ pbus_data_new = (pbus_data_old & ~mask) | set; ++ if (pbus_data_new == pbus_data_old) ++ return 0; ++ ++ ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_HIGH, ++ upper_16_bits(pbus_address)); + if (ret < 0) -+ phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__, -+ pbus_address, ret); ++ return ret; ++ ++ ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_LOW, ++ lower_16_bits(pbus_address)); ++ if (ret < 0) ++ return ret; ++ ++ ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_HIGH, ++ upper_16_bits(pbus_data_new)); ++ if (ret < 0) ++ return ret; ++ ++ ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_LOW, ++ lower_16_bits(pbus_data_new)); ++ if (ret < 0) ++ return ret; ++ ++ return 0; ++} ++ ++static int air_buckpbus_reg_modify(struct phy_device *phydev, ++ u32 pbus_address, u32 mask, u32 set) ++{ ++ int saved_page; ++ int ret = 0; ++ ++ saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4); ++ ++ if (saved_page >= 0) { ++ ret = __air_buckpbus_reg_modify(phydev, pbus_address, mask, ++ set); ++ if (ret < 0) ++ phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__, ++ pbus_address, ret); ++ } + + return phy_restore_page(phydev, saved_page, ret); +} @@ -415,26 +437,28 @@ Signed-off-by: Eric Woudstra + int ret; + u16 val; + -+ ret = __phy_write(phydev, AIR_PBUS_MODE, AIR_PBUS_MODE_ADDR_INCR); ++ ret = __phy_write(phydev, AIR_BPBUS_MODE, AIR_BPBUS_MODE_ADDR_INCR); + if (ret < 0) + return ret; + -+ ret = __phy_write(phydev, AIR_PBUS_WR_ADDR_HIGH, HIWORD(address)); ++ ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_HIGH, ++ upper_16_bits(address)); + if (ret < 0) + return ret; + -+ ret = __phy_write(phydev, AIR_PBUS_WR_ADDR_LOW, LOWORD(address)); ++ ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_LOW, ++ lower_16_bits(address)); + if (ret < 0) + return ret; + + for (offset = 0; offset < fw->size; offset += 4) { + val = get_unaligned_le16(&fw->data[offset + 2]); -+ ret = __phy_write(phydev, AIR_PBUS_WR_DATA_HIGH, val); ++ ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_HIGH, val); + if (ret < 0) + return ret; + + val = get_unaligned_le16(&fw->data[offset]); -+ ret = __phy_write(phydev, AIR_PBUS_WR_DATA_LOW, val); ++ ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_LOW, val); + if (ret < 0) + return ret; + } @@ -445,23 +469,43 @@ Signed-off-by: Eric Woudstra +static int air_write_buf(struct phy_device *phydev, u32 address, + const struct firmware *fw) +{ -+ int ret, saved_page; ++ int saved_page; ++ int ret = 0; + + saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4); + -+ ret = __air_write_buf(phydev, address, fw); -+ if (ret < 0) -+ phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__, -+ address, ret); ++ if (saved_page >= 0) { ++ ret = __air_write_buf(phydev, address, fw); ++ if (ret < 0) ++ phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__, ++ address, ret); ++ } + + return phy_restore_page(phydev, saved_page, ret); +} + ++static int en8811h_wait_mcu_ready(struct phy_device *phydev) ++{ ++ int ret, reg_value; ++ ++ /* Because of mdio-lock, may have to wait for multiple loads */ ++ ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, ++ EN8811H_PHY_FW_STATUS, reg_value, ++ reg_value == EN8811H_PHY_READY, ++ 20000, 7500000, true); ++ if (ret) { ++ phydev_err(phydev, "MCU not ready: 0x%x\n", reg_value); ++ return -ENODEV; ++ } ++ ++ return 0; ++} ++ +static int en8811h_load_firmware(struct phy_device *phydev) +{ ++ struct en8811h_priv *priv = phydev->priv; + struct device *dev = &phydev->mdio.dev; + const struct firmware *fw1, *fw2; -+ u32 pbus_value; + int ret; + + ret = request_firmware_direct(&fw1, EN8811H_MD32_DM, dev); @@ -477,11 +521,9 @@ Signed-off-by: Eric Woudstra + if (ret < 0) + goto en8811h_load_firmware_out; + -+ ret = air_buckpbus_reg_read(phydev, EN8811H_FW_CTRL_2, &pbus_value); -+ if (ret < 0) -+ goto en8811h_load_firmware_out; -+ pbus_value |= EN8811H_FW_CTRL_2_LOADING; -+ ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_2, pbus_value); ++ ret = air_buckpbus_reg_modify(phydev, EN8811H_FW_CTRL_2, ++ EN8811H_FW_CTRL_2_LOADING, ++ EN8811H_FW_CTRL_2_LOADING); + if (ret < 0) + goto en8811h_load_firmware_out; + @@ -493,11 +535,8 @@ Signed-off-by: Eric Woudstra + if (ret < 0) + goto en8811h_load_firmware_out; + -+ ret = air_buckpbus_reg_read(phydev, EN8811H_FW_CTRL_2, &pbus_value); -+ if (ret < 0) -+ goto en8811h_load_firmware_out; -+ pbus_value &= ~EN8811H_FW_CTRL_2_LOADING; -+ ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_2, pbus_value); ++ ret = air_buckpbus_reg_modify(phydev, EN8811H_FW_CTRL_2, ++ EN8811H_FW_CTRL_2_LOADING, 0); + if (ret < 0) + goto en8811h_load_firmware_out; + @@ -506,7 +545,12 @@ Signed-off-by: Eric Woudstra + if (ret < 0) + goto en8811h_load_firmware_out; + -+ ret = 0; ++ ret = en8811h_wait_mcu_ready(phydev); ++ ++ air_buckpbus_reg_read(phydev, EN8811H_FW_VERSION, ++ &priv->firmware_version); ++ phydev_info(phydev, "MD32 firmware version: %08x\n", ++ priv->firmware_version); + +en8811h_load_firmware_out: + release_firmware(fw2); @@ -520,7 +564,7 @@ Signed-off-by: Eric Woudstra + return ret; +} + -+static int en8811h_restart_host(struct phy_device *phydev) ++static int en8811h_restart_mcu(struct phy_device *phydev) +{ + int ret; + @@ -529,8 +573,12 @@ Signed-off-by: Eric Woudstra + if (ret < 0) + return ret; + -+ return air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1, ++ ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1, + EN8811H_FW_CTRL_1_FINISH); ++ if (ret < 0) ++ return ret; ++ ++ return en8811h_wait_mcu_ready(phydev); +} + +static int air_hw_led_on_set(struct phy_device *phydev, u8 index, bool on) @@ -664,68 +712,46 @@ Signed-off-by: Eric Woudstra + u16 on = 0, blink = 0; + int ret; + -+ priv->led[index].rules = rules; -+ + if (index >= EN8811H_LED_COUNT) + return -EINVAL; + -+ if (rules & (BIT(TRIGGER_NETDEV_LINK_10) | BIT(TRIGGER_NETDEV_LINK))) { ++ priv->led[index].rules = rules; ++ ++ if (rules & BIT(TRIGGER_NETDEV_FULL_DUPLEX)) ++ on |= AIR_PHY_LED_ON_FDX; ++ ++ if (rules & (BIT(TRIGGER_NETDEV_LINK_10) | BIT(TRIGGER_NETDEV_LINK))) + on |= AIR_PHY_LED_ON_LINK10; -+ if (rules & BIT(TRIGGER_NETDEV_RX)) -+ blink |= AIR_PHY_LED_BLINK_10RX; -+ if (rules & BIT(TRIGGER_NETDEV_TX)) -+ blink |= AIR_PHY_LED_BLINK_10TX; -+ } + -+ if (rules & (BIT(TRIGGER_NETDEV_LINK_100) | BIT(TRIGGER_NETDEV_LINK))) { ++ if (rules & (BIT(TRIGGER_NETDEV_LINK_100) | BIT(TRIGGER_NETDEV_LINK))) + on |= AIR_PHY_LED_ON_LINK100; -+ if (rules & BIT(TRIGGER_NETDEV_RX)) -+ blink |= AIR_PHY_LED_BLINK_100RX; -+ if (rules & BIT(TRIGGER_NETDEV_TX)) -+ blink |= AIR_PHY_LED_BLINK_100TX; -+ } + -+ if (rules & (BIT(TRIGGER_NETDEV_LINK_1000) | BIT(TRIGGER_NETDEV_LINK))) { ++ if (rules & (BIT(TRIGGER_NETDEV_LINK_1000) | BIT(TRIGGER_NETDEV_LINK))) + on |= AIR_PHY_LED_ON_LINK1000; -+ if (rules & BIT(TRIGGER_NETDEV_RX)) -+ blink |= AIR_PHY_LED_BLINK_1000RX; -+ if (rules & BIT(TRIGGER_NETDEV_TX)) -+ blink |= AIR_PHY_LED_BLINK_1000TX; -+ } + -+ if (rules & (BIT(TRIGGER_NETDEV_LINK_2500) | BIT(TRIGGER_NETDEV_LINK))) { ++ if (rules & (BIT(TRIGGER_NETDEV_LINK_2500) | BIT(TRIGGER_NETDEV_LINK))) + on |= AIR_PHY_LED_ON_LINK2500; -+ if (rules & BIT(TRIGGER_NETDEV_RX)) -+ blink |= AIR_PHY_LED_BLINK_2500RX; -+ if (rules & BIT(TRIGGER_NETDEV_TX)) -+ blink |= AIR_PHY_LED_BLINK_2500TX; -+ } + -+ if (on == 0) { -+ if (rules & BIT(TRIGGER_NETDEV_RX)) { -+ blink |= AIR_PHY_LED_BLINK_10RX | -+ AIR_PHY_LED_BLINK_100RX | -+ AIR_PHY_LED_BLINK_1000RX | -+ AIR_PHY_LED_BLINK_2500RX; -+ } -+ if (rules & BIT(TRIGGER_NETDEV_TX)) { -+ blink |= AIR_PHY_LED_BLINK_10TX | -+ AIR_PHY_LED_BLINK_100TX | -+ AIR_PHY_LED_BLINK_1000TX | -+ AIR_PHY_LED_BLINK_2500TX; -+ } ++ if (rules & BIT(TRIGGER_NETDEV_RX)) { ++ blink |= AIR_PHY_LED_BLINK_10RX | ++ AIR_PHY_LED_BLINK_100RX | ++ AIR_PHY_LED_BLINK_1000RX | ++ AIR_PHY_LED_BLINK_2500RX; + } + -+ if (rules & BIT(TRIGGER_NETDEV_FULL_DUPLEX)) -+ on |= AIR_PHY_LED_ON_FDX; -+ -+ if (rules & BIT(TRIGGER_NETDEV_HALF_DUPLEX)) -+ on |= AIR_PHY_LED_ON_HDX; ++ if (rules & BIT(TRIGGER_NETDEV_TX)) { ++ blink |= AIR_PHY_LED_BLINK_10TX | ++ AIR_PHY_LED_BLINK_100TX | ++ AIR_PHY_LED_BLINK_1000TX | ++ AIR_PHY_LED_BLINK_2500TX; ++ } + + if (blink || on) { + /* switch hw-control on, so led-on and led-blink are off */ -+ clear_bit(AIR_PHY_LED_STATE_FORCE_ON, &priv->led[index].state); -+ clear_bit(AIR_PHY_LED_STATE_FORCE_BLINK, &priv->led[index].state); ++ clear_bit(AIR_PHY_LED_STATE_FORCE_ON, ++ &priv->led[index].state); ++ clear_bit(AIR_PHY_LED_STATE_FORCE_BLINK, ++ &priv->led[index].state); + } else { + priv->led[index].rules = 0; + } @@ -742,28 +768,26 @@ Signed-off-by: Eric Woudstra + +static int air_led_init(struct phy_device *phydev, u8 index, u8 state, u8 pol) +{ -+ int cl45_data; ++ int val = 0; + int err; + + if (index >= EN8811H_LED_COUNT) + return -EINVAL; + -+ cl45_data = phy_read_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_ON(index)); -+ if (cl45_data < 0) -+ return cl45_data; -+ + if (state == AIR_LED_ENABLE) -+ cl45_data |= AIR_PHY_LED_ON_ENABLE; ++ val |= AIR_PHY_LED_ON_ENABLE; + else -+ cl45_data &= ~AIR_PHY_LED_ON_ENABLE; ++ val &= ~AIR_PHY_LED_ON_ENABLE; + + if (pol == AIR_ACTIVE_HIGH) -+ cl45_data |= AIR_PHY_LED_ON_POLARITY; ++ val |= AIR_PHY_LED_ON_POLARITY; + else -+ cl45_data &= ~AIR_PHY_LED_ON_POLARITY; ++ val &= ~AIR_PHY_LED_ON_POLARITY; ++ ++ err = phy_modify_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_ON(index), ++ AIR_PHY_LED_ON_ENABLE | ++ AIR_PHY_LED_ON_POLARITY, val); + -+ err = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_ON(index), -+ cl45_data); + if (err < 0) + return err; + @@ -773,42 +797,40 @@ Signed-off-by: Eric Woudstra +static int air_leds_init(struct phy_device *phydev, int num, int dur, int mode) +{ + struct en8811h_priv *priv = phydev->priv; -+ int cl45_data = dur; + int ret, i; + + ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_DUR_BLINK, -+ cl45_data); ++ dur); + if (ret < 0) + return ret; + -+ cl45_data >>= 1; + ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_DUR_ON, -+ cl45_data); ++ dur >> 1); + if (ret < 0) + return ret; + -+ cl45_data = phy_read_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_BCR); -+ if (cl45_data < 0) -+ return cl45_data; -+ + switch (mode) { + case AIR_LED_MODE_DISABLE: -+ cl45_data &= ~AIR_PHY_LED_BCR_EXT_CTRL; -+ cl45_data &= ~AIR_PHY_LED_BCR_MODE_MASK; ++ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_BCR, ++ AIR_PHY_LED_BCR_EXT_CTRL | ++ AIR_PHY_LED_BCR_MODE_MASK, 0); ++ if (ret < 0) ++ return ret; + break; + case AIR_LED_MODE_USER_DEFINE: -+ cl45_data |= AIR_PHY_LED_BCR_EXT_CTRL; -+ cl45_data |= AIR_PHY_LED_BCR_CLK_EN; ++ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_BCR, ++ AIR_PHY_LED_BCR_EXT_CTRL | ++ AIR_PHY_LED_BCR_CLK_EN, ++ AIR_PHY_LED_BCR_EXT_CTRL | ++ AIR_PHY_LED_BCR_CLK_EN); ++ if (ret < 0) ++ return ret; + break; + default: + phydev_err(phydev, "LED mode %d is not supported\n", mode); + return -EINVAL; + } + -+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_BCR, cl45_data); -+ if (ret < 0) -+ return ret; -+ + for (i = 0; i < num; ++i) { + ret = air_led_init(phydev, i, AIR_LED_ENABLE, AIR_ACTIVE_HIGH); + if (ret < 0) { @@ -837,21 +859,42 @@ Signed-off-by: Eric Woudstra +static int en8811h_probe(struct phy_device *phydev) +{ + struct en8811h_priv *priv; ++ int ret; + + priv = devm_kzalloc(&phydev->mdio.dev, sizeof(struct en8811h_priv), + GFP_KERNEL); + if (!priv) + return -ENOMEM; ++ phydev->priv = priv; ++ ++ ret = en8811h_load_firmware(phydev); ++ if (ret < 0) ++ return ret; ++ ++ /* mcu has just restarted after firmware load */ ++ priv->mcu_needs_restart = false; + + priv->led[0].rules = AIR_DEFAULT_TRIGGER_LED0; + priv->led[1].rules = AIR_DEFAULT_TRIGGER_LED1; + priv->led[2].rules = AIR_DEFAULT_TRIGGER_LED2; + -+ phydev->priv = priv; -+ + /* MDIO_DEVS1/2 empty, so set mmds_present bits here */ + phydev->c45_ids.mmds_present |= MDIO_DEVS_PMAPMD | MDIO_DEVS_AN; + ++ ret = air_leds_init(phydev, EN8811H_LED_COUNT, AIR_PHY_LED_DUR, ++ AIR_LED_MODE_DISABLE); ++ if (ret < 0) { ++ phydev_err(phydev, "Failed to disable leds: %d\n", ret); ++ return ret; ++ } ++ ++ /* Configure led gpio pins as output */ ++ ret = air_buckpbus_reg_modify(phydev, EN8811H_GPIO_OUTPUT, ++ EN8811H_GPIO_OUTPUT_345, ++ EN8811H_GPIO_OUTPUT_345); ++ if (ret < 0) ++ return ret; ++ + return 0; +} + @@ -859,58 +902,41 @@ Signed-off-by: Eric Woudstra +{ + struct en8811h_priv *priv = phydev->priv; + struct device *dev = &phydev->mdio.dev; -+ int ret, pollret, reg_value; + u32 pbus_value; ++ int ret; + -+ if (!priv->firmware_version) -+ ret = en8811h_load_firmware(phydev); -+ else -+ ret = en8811h_restart_host(phydev); -+ if (ret < 0) -+ return ret; -+ -+ /* Because of mdio-lock, may have to wait for multiple loads */ -+ pollret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, -+ EN8811H_PHY_FW_STATUS, reg_value, -+ reg_value == EN8811H_PHY_READY, -+ 20000, 7500000, true); -+ -+ ret = air_buckpbus_reg_read(phydev, EN8811H_FW_VERSION, &pbus_value); -+ if (ret < 0) -+ return ret; -+ -+ if (pollret || !pbus_value) { -+ phydev_err(phydev, "Firmware not ready: 0x%x\n", reg_value); -+ return -ENODEV; -+ } -+ -+ if (!priv->firmware_version) { -+ phydev_info(phydev, "MD32 firmware version: %08x\n", pbus_value); -+ priv->firmware_version = pbus_value; ++ /* If restart happened in .probe(), no need to restart now */ ++ if (priv->mcu_needs_restart) { ++ ret = en8811h_restart_mcu(phydev); ++ if (ret < 0) ++ return ret; ++ } else { ++ /* Next calls to .config_init() mcu needs to restart */ ++ priv->mcu_needs_restart = true; + } + -+ /* Select mode 1, the only mode supported */ -+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_HOST_CMD_1, -+ AIR_PHY_HOST_CMD_1_MODE1); ++ /* Select mode 1, the only mode supported. ++ * Configures the SerDes for 2500Base-X with rate adaptation ++ */ ++ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_1, ++ AIR_PHY_MCU_CMD_1_MODE1); + if (ret < 0) + return ret; -+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_HOST_CMD_2, -+ AIR_PHY_HOST_CMD_2_MODE1); ++ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_2, ++ AIR_PHY_MCU_CMD_2_MODE1); + if (ret < 0) + return ret; -+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_HOST_CMD_3, -+ AIR_PHY_HOST_CMD_3_MODE1); ++ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_3, ++ AIR_PHY_MCU_CMD_3_MODE1); + if (ret < 0) + return ret; -+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_HOST_CMD_4, -+ AIR_PHY_HOST_CMD_4_MODE1); ++ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_4, ++ AIR_PHY_MCU_CMD_4_MODE1); + if (ret < 0) + return ret; + + /* Serdes polarity */ -+ ret = air_buckpbus_reg_read(phydev, EN8811H_POLARITY, &pbus_value); -+ if (ret < 0) -+ return ret; ++ pbus_value = 0; + if (device_property_read_bool(dev, "airoha,pnswap-rx")) + pbus_value |= EN8811H_POLARITY_RX_REVERSE; + else @@ -919,7 +945,9 @@ Signed-off-by: Eric Woudstra + pbus_value &= ~EN8811H_POLARITY_TX_NORMAL; + else + pbus_value |= EN8811H_POLARITY_TX_NORMAL; -+ ret = air_buckpbus_reg_write(phydev, EN8811H_POLARITY, pbus_value); ++ ret = air_buckpbus_reg_modify(phydev, EN8811H_POLARITY, ++ EN8811H_POLARITY_RX_REVERSE | ++ EN8811H_POLARITY_TX_NORMAL, pbus_value); + if (ret < 0) + return ret; + @@ -930,14 +958,6 @@ Signed-off-by: Eric Woudstra + return ret; + } + -+ ret = air_buckpbus_reg_read(phydev, EN8811H_GPIO_OUTPUT, &pbus_value); -+ if (ret < 0) -+ return ret; -+ pbus_value |= EN8811H_GPIO_OUTPUT_345; -+ ret = air_buckpbus_reg_write(phydev, EN8811H_GPIO_OUTPUT, pbus_value); -+ if (ret < 0) -+ return ret; -+ + return 0; +} + @@ -959,17 +979,21 @@ Signed-off-by: Eric Woudstra +static int en8811h_config_aneg(struct phy_device *phydev) +{ + bool changed = false; -+ int err, val; -+ -+ val = 0; -+ if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, -+ phydev->advertising)) -+ val |= MDIO_AN_10GBT_CTRL_ADV2_5G; -+ err = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, -+ MDIO_AN_10GBT_CTRL_ADV2_5G, val); -+ if (err < 0) -+ return err; -+ if (err > 0) ++ int ret; ++ u32 adv; ++ ++ if (phydev->autoneg == AUTONEG_DISABLE) { ++ phydev_warn(phydev, "Disabling autoneg is not supported\n"); ++ return -EINVAL; ++ } ++ ++ adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising); ++ ++ ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, ++ MDIO_AN_10GBT_CTRL_ADV2_5G, adv); ++ if (ret < 0) ++ return ret; ++ if (ret > 0) + changed = true; + + return __genphy_config_aneg(phydev, changed); @@ -991,6 +1015,7 @@ Signed-off-by: Eric Woudstra + phydev->duplex = DUPLEX_UNKNOWN; + phydev->pause = 0; + phydev->asym_pause = 0; ++ phydev->rate_matching = RATE_MATCH_PAUSE; + + ret = genphy_read_master_slave(phydev); + if (ret < 0) @@ -1008,7 +1033,7 @@ Signed-off-by: Eric Woudstra + phydev->lp_advertising, + pbus_value & EN8811H_2P5G_LPA_2P5G); + -+ if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) ++ if (phydev->autoneg_complete) + phy_resolve_aneg_pause(phydev); + + if (!phydev->link) @@ -1030,8 +1055,7 @@ Signed-off-by: Eric Woudstra + break; + } + -+ /* BUG in PHY firmware: MDIO_AN_10GBT_STAT_LP2_5G does not get set. -+ * Firmware before version 24011202 has no vendor register 2P5G_LPA. ++ /* Firmware before version 24011202 has no vendor register 2P5G_LPA. + * Assume link partner advertised it if connected at 2500Mbps. + */ + if (priv->firmware_version < 0x24011202) { @@ -1050,13 +1074,13 @@ Signed-off-by: Eric Woudstra +{ + int ret; + -+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_HOST_CMD_3, -+ AIR_PHY_HOST_CMD_3_DOCMD); ++ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_3, ++ AIR_PHY_MCU_CMD_3_DOCMD); + if (ret < 0) + return ret; + -+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_HOST_CMD_4, -+ AIR_PHY_HOST_CMD_4_INTCLR); ++ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_4, ++ AIR_PHY_MCU_CMD_4_INTCLR); + if (ret < 0) + return ret; + @@ -1105,6 +1129,7 @@ Signed-off-by: Eric Woudstra + { PHY_ID_MATCH_MODEL(EN8811H_PHY_ID) }, + { } +}; ++ +MODULE_DEVICE_TABLE(mdio, en8811h_tbl); +MODULE_FIRMWARE(EN8811H_MD32_DM); +MODULE_FIRMWARE(EN8811H_MD32_DSP); diff --git a/target/linux/generic/backport-6.6/799-v6.10-net-phy-air_en8811h-fix-some-error-codes.patch b/target/linux/generic/backport-6.6/799-v6.10-net-phy-air_en8811h-fix-some-error-codes.patch new file mode 100644 index 00000000000000..1bd0eefe77b512 --- /dev/null +++ b/target/linux/generic/backport-6.6/799-v6.10-net-phy-air_en8811h-fix-some-error-codes.patch @@ -0,0 +1,47 @@ +From 87c33315af380ca12a2e59ac94edad4fe0481b4c Mon Sep 17 00:00:00 2001 +From: Dan Carpenter +Date: Fri, 5 Apr 2024 13:08:59 +0300 +Subject: [PATCH] net: phy: air_en8811h: fix some error codes + +These error paths accidentally return "ret" which is zero/success +instead of the correct error code. + +Fixes: 71e79430117d ("net: phy: air_en8811h: Add the Airoha EN8811H PHY driver") +Signed-off-by: Dan Carpenter +Reviewed-by: Simon Horman +Link: https://lore.kernel.org/r/7ef2e230-dfb7-4a77-8973-9e5be1a99fc2@moroto.mountain +Signed-off-by: Jakub Kicinski +--- + drivers/net/phy/air_en8811h.c | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +--- a/drivers/net/phy/air_en8811h.c ++++ b/drivers/net/phy/air_en8811h.c +@@ -272,11 +272,11 @@ static int __air_buckpbus_reg_read(struc + + pbus_data_high = __phy_read(phydev, AIR_BPBUS_RD_DATA_HIGH); + if (pbus_data_high < 0) +- return ret; ++ return pbus_data_high; + + pbus_data_low = __phy_read(phydev, AIR_BPBUS_RD_DATA_LOW); + if (pbus_data_low < 0) +- return ret; ++ return pbus_data_low; + + *pbus_data = pbus_data_low | (pbus_data_high << 16); + return 0; +@@ -323,11 +323,11 @@ static int __air_buckpbus_reg_modify(str + + pbus_data_high = __phy_read(phydev, AIR_BPBUS_RD_DATA_HIGH); + if (pbus_data_high < 0) +- return ret; ++ return pbus_data_high; + + pbus_data_low = __phy_read(phydev, AIR_BPBUS_RD_DATA_LOW); + if (pbus_data_low < 0) +- return ret; ++ return pbus_data_low; + + pbus_data_old = pbus_data_low | (pbus_data_high << 16); + pbus_data_new = (pbus_data_old & ~mask) | set; diff --git a/target/linux/generic/backport-6.6/832-v6.7-net-phy-amd-Support-the-Altima-AMI101L.patch b/target/linux/generic/backport-6.6/832-v6.7-net-phy-amd-Support-the-Altima-AMI101L.patch index fa2056b69a2cb1..07287206f698b3 100644 --- a/target/linux/generic/backport-6.6/832-v6.7-net-phy-amd-Support-the-Altima-AMI101L.patch +++ b/target/linux/generic/backport-6.6/832-v6.7-net-phy-amd-Support-the-Altima-AMI101L.patch @@ -16,8 +16,8 @@ Signed-off-by: Linus Walleij --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig -@@ -69,9 +69,9 @@ config SFP - comment "MII PHY device drivers" +@@ -74,9 +74,9 @@ config AIR_EN8811H_PHY + Currently supports the Airoha EN8811H PHY. config AMD_PHY - tristate "AMD PHYs" diff --git a/target/linux/generic/config-6.6 b/target/linux/generic/config-6.6 index dd274e63d8c0b1..1e9a82e8f0e84b 100644 --- a/target/linux/generic/config-6.6 +++ b/target/linux/generic/config-6.6 @@ -414,6 +414,7 @@ CONFIG_ARM64_SW_TTBR0_PAN=y # CONFIG_ARM_CCI_PMU is not set # CONFIG_ARM_CCN is not set # CONFIG_ARM_CMN is not set +# CONFIG_ARM_CORESIGHT_PMU_ARCH_SYSTEM_PMU is not set # CONFIG_ARM_CPUIDLE is not set CONFIG_ARM_CPU_TOPOLOGY=y # CONFIG_ARM_CRYPTO is not set @@ -465,6 +466,7 @@ CONFIG_ARM_MODULE_PLTS=y # CONFIG_ARM_SDE_INTERFACE is not set # CONFIG_ARM_SMCCC_SOC_ID is not set # CONFIG_ARM_SMC_WATCHDOG is not set +# CONFIG_ARM_SMMU_V3_PMU is not set # CONFIG_ARM_SP805_WATCHDOG is not set # CONFIG_ARM_SPE_PMU is not set # CONFIG_ARM_THUMBEE is not set diff --git a/target/linux/generic/hack-6.6/200-tools_portability.patch b/target/linux/generic/hack-6.6/200-tools_portability.patch new file mode 100644 index 00000000000000..2ea8a685378cdf --- /dev/null +++ b/target/linux/generic/hack-6.6/200-tools_portability.patch @@ -0,0 +1,90 @@ +--- a/tools/scripts/Makefile.include ++++ b/tools/scripts/Makefile.include +@@ -72,8 +72,6 @@ $(call allow-override,CXX,$(CROSS_COMPIL + $(call allow-override,STRIP,$(CROSS_COMPILE)strip) + endif + +-CC_NO_CLANG := $(shell $(CC) -dM -E -x c /dev/null | grep -Fq "__clang__"; echo $$?) +- + ifneq ($(LLVM),) + HOSTAR ?= $(LLVM_PREFIX)llvm-ar$(LLVM_SUFFIX) + HOSTCC ?= $(LLVM_PREFIX)clang$(LLVM_SUFFIX) +@@ -84,6 +82,9 @@ HOSTCC ?= gcc + HOSTLD ?= ld + endif + ++CC_NO_CLANG := $(shell $(CC) -dM -E -x c /dev/null | grep -Fq "__clang__"; echo $$?) ++HOSTCC_NO_CLANG := $(shell $(HOSTCC) -dM -E -x c /dev/null | grep -Fq "__clang__"; echo $$?) ++ + # Some tools require Clang, LLC and/or LLVM utils + CLANG ?= clang + LLC ?= llc +@@ -92,8 +93,9 @@ LLVM_OBJCOPY ?= llvm-objcopy + LLVM_STRIP ?= llvm-strip + + ifeq ($(CC_NO_CLANG), 1) +-EXTRA_WARNINGS += -Wstrict-aliasing=3 +- ++ ifeq ($(HOSTCC_NO_CLANG), 1) ++ EXTRA_WARNINGS += -Wstrict-aliasing=3 ++ endif + else ifneq ($(CROSS_COMPILE),) + # Allow userspace to override CLANG_CROSS_FLAGS to specify their own + # sysroots and flags or to avoid the GCC call in pure Clang builds. +--- a/tools/include/linux/types.h ++++ b/tools/include/linux/types.h +@@ -56,6 +56,7 @@ typedef __s8 s8; + #define __user + #endif + #define __must_check ++#undef __cold + #define __cold + + typedef __u16 __bitwise __le16; +--- a/tools/objtool/include/objtool/objtool.h ++++ b/tools/objtool/include/objtool/objtool.h +@@ -12,6 +12,7 @@ + + #include + ++#undef __weak + #define __weak __attribute__((weak)) + + struct pv_state { +--- a/tools/include/asm-generic/bitops/fls.h ++++ b/tools/include/asm-generic/bitops/fls.h +@@ -2,6 +2,8 @@ + #ifndef _ASM_GENERIC_BITOPS_FLS_H_ + #define _ASM_GENERIC_BITOPS_FLS_H_ + ++#include ++ + /** + * fls - find last (most-significant) bit set + * @x: the word to search +@@ -10,6 +12,7 @@ + * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32. + */ + ++#define fls __linux_fls + static __always_inline int fls(unsigned int x) + { + int r = 32; +--- a/tools/lib/string.c ++++ b/tools/lib/string.c +@@ -96,6 +96,7 @@ int strtobool(const char *s, bool *res) + * If libc has strlcpy() then that version will override this + * implementation: + */ ++#ifndef __APPLE__ + #ifdef __clang__ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wignored-attributes" +@@ -114,6 +115,7 @@ size_t __weak strlcpy(char *dest, const + #ifdef __clang__ + #pragma clang diagnostic pop + #endif ++#endif + + /** + * skip_spaces - Removes leading whitespace from @str. diff --git a/target/linux/generic/pending-6.1/742-net-phy-air_en8811h-reset-netdev-rules-when-LED-is-s.patch b/target/linux/generic/pending-6.1/742-net-phy-air_en8811h-reset-netdev-rules-when-LED-is-s.patch new file mode 100644 index 00000000000000..500567b4ed05b7 --- /dev/null +++ b/target/linux/generic/pending-6.1/742-net-phy-air_en8811h-reset-netdev-rules-when-LED-is-s.patch @@ -0,0 +1,45 @@ +From 9be9a00adfac8118b6d685e71696f83187308c66 Mon Sep 17 00:00:00 2001 +Message-ID: <9be9a00adfac8118b6d685e71696f83187308c66.1715125851.git.daniel@makrotopia.org> +From: Daniel Golle +Date: Tue, 7 May 2024 22:43:30 +0100 +Subject: [PATCH net] net: phy: air_en8811h: reset netdev rules when LED is set + manually +To: Andrew Lunn , + Heiner Kallweit , + Russell King , + David S. Miller , + Eric Dumazet , + Jakub Kicinski , + Paolo Abeni , + SkyLake Huang , + Eric Woudstra , + netdev@vger.kernel.org, + linux-kernel@vger.kernel.org + +Setting LED_OFF via the brightness_set should deactivate hw control, +so make sure netdev trigger rules also get cleared in that case. + +Fixes: 71e79430117d ("net: phy: air_en8811h: Add the Airoha EN8811H PHY driver") +Signed-off-by: Daniel Golle +--- +This is basically a stop-gap measure until unified LED handling has +been implemented accross all MediaTek and Airoha PHYs. +See also +https://patchwork.kernel.org/project/netdevbpf/patch/20240425023325.15586-3-SkyLake.Huang@mediatek.com/ + + drivers/net/phy/air_en8811h.c | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/drivers/net/phy/air_en8811h.c ++++ b/drivers/net/phy/air_en8811h.c +@@ -544,6 +544,10 @@ static int air_hw_led_on_set(struct phy_ + + changed |= (priv->led[index].rules != 0); + ++ /* clear netdev trigger rules in case LED_OFF has been set */ ++ if (!on) ++ priv->led[index].rules = 0; ++ + if (changed) + return phy_modify_mmd(phydev, MDIO_MMD_VEND2, + AIR_PHY_LED_ON(index), diff --git a/target/linux/generic/pending-6.1/795-01-net-dsa-mt7530-do-not-set-MT7530_P5_DIS-when-PHY-.patch b/target/linux/generic/pending-6.1/795-01-net-dsa-mt7530-do-not-set-MT7530_P5_DIS-when-PHY-.patch deleted file mode 100644 index 04d8c8760fcc61..00000000000000 --- a/target/linux/generic/pending-6.1/795-01-net-dsa-mt7530-do-not-set-MT7530_P5_DIS-when-PHY-.patch +++ /dev/null @@ -1,79 +0,0 @@ -From patchwork Sat Apr 27 11:24:42 2024 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 8bit -X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTCB2aWEgQjQgUmVsYXk=?= - -X-Patchwork-Id: 13645655 -From: =?utf-8?b?QXLEsW7DpyDDnE5BTCB2aWEgQjQgUmVsYXk=?= - -Date: Sat, 27 Apr 2024 14:24:42 +0300 -Subject: [PATCH net-next] net: dsa: mt7530: do not set MT7530_P5_DIS when - PHY muxing is being used -Precedence: bulk -X-Mailing-List: netdev@vger.kernel.org -List-Id: -List-Subscribe: -List-Unsubscribe: -MIME-Version: 1.0 -Message-Id: - <20240427-for-netnext-mt7530-do-not-disable-port5-when-phy-muxing-v1-1-793cdf9d7707@arinc9.com> -To: Daniel Golle , DENG Qingfang , - Sean Wang , Andrew Lunn , - Florian Fainelli , - Vladimir Oltean , - "David S. Miller" , Eric Dumazet , - Jakub Kicinski , Paolo Abeni , - Matthias Brugger , - AngeloGioacchino Del Regno -Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, - linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, - =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= -X-Mailer: b4 0.13.0 -X-Patchwork-Delegate: kuba@kernel.org - -From: Arınç ÃœNAL - -When the PHY muxing feature is in use, port 5 won't be defined in the -device tree. Because of this, the type member of the dsa_port structure for -this port will be assigned DSA_PORT_TYPE_UNUSED. The dsa_port_setup() -function calls ds->ops->port_disable() when the port type is -DSA_PORT_TYPE_UNUSED. - -The MT7530_P5_DIS bit is unset when PHY muxing is being used. -mt7530_port_disable() which is assigned to ds->ops->port_disable() is -called afterwards. Currently, mt7530_port_disable() sets MT7530_P5_DIS -which breaks network connectivity when PHY muxing is being used. - -Therefore, do not set MT7530_P5_DIS when PHY muxing is being used. - -Fixes: 377174c5760c ("net: dsa: mt7530: move MT753X_MTRAP operations for MT7530") -Reported-by: Daniel Golle -Signed-off-by: Arınç ÃœNAL ---- -Hello. - -I've sent this to net-next as the patch it fixes is on the current -development cycle. ---- - drivers/net/dsa/mt7530.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - - ---- -base-commit: 5c4c0edca68a5841a8d53ccd49596fe199c8334c -change-id: 20240427-for-netnext-mt7530-do-not-disable-port5-when-phy-muxing-7ff5fd0995d7 - -Best regards, - ---- a/drivers/net/dsa/mt7530.c -+++ b/drivers/net/dsa/mt7530.c -@@ -1227,7 +1227,7 @@ mt7530_port_disable(struct dsa_switch *d - if (priv->id != ID_MT7530 && priv->id != ID_MT7621) - return; - -- if (port == 5) -+ if (port == 5 && priv->p5_mode == GMAC5) - mt7530_set(priv, MT753X_MTRAP, MT7530_P5_DIS); - else if (port == 6) - mt7530_set(priv, MT753X_MTRAP, MT7530_P6_DIS); diff --git a/target/linux/generic/pending-6.1/796-net-dsa-mt7530-detect-PHY-muxing-when-PHY-is-defined-on-switch-MDIO-bus.patch b/target/linux/generic/pending-6.1/796-net-dsa-mt7530-detect-PHY-muxing-when-PHY-is-defined-on-switch-MDIO-bus.patch deleted file mode 100644 index 5db834e23f31fd..00000000000000 --- a/target/linux/generic/pending-6.1/796-net-dsa-mt7530-detect-PHY-muxing-when-PHY-is-defined-on-switch-MDIO-bus.patch +++ /dev/null @@ -1,136 +0,0 @@ -From patchwork Tue Apr 30 05:01:33 2024 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 8bit -X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTCB2aWEgQjQgUmVsYXk=?= - -X-Patchwork-Id: 13648264 -X-Patchwork-Delegate: kuba@kernel.org -Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org - [10.30.226.201]) - (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) - (No client certificate requested) - by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4C9C114A89; - Tue, 30 Apr 2024 05:01:39 +0000 (UTC) -Authentication-Results: smtp.subspace.kernel.org; - arc=none smtp.client-ip=10.30.226.201 -ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; - t=1714453299; cv=none; - b=gV4Z0elIASLrrICjPPmDeR0kBaXtdjeqbz/cnj3/0V74cRGmjd5sMQ4PtMYq5iPdJkWbhn4mzf/WX9xcqituDcVV7Vj68zrsE5d6NavvrMK9kf7Ef3Yyr8gEbekALfL9fKuF6ul7TeVFQiFoGQyAJNFzB9YAiQGJlWzw98bldMQ= -ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; - s=arc-20240116; t=1714453299; c=relaxed/simple; - bh=GGkybB3RbZ4yacytPZCe3ceKcaWca6ygWTw/PJtmpsk=; - h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:To:Cc; - b=QRWD6k4Qg1t5nZj6oj2xdwWDCGHQWHG2xj0lkYcEMm3dMkvPpLbCIOptpZBJtSq06TMxRjVJhgVJ9ATDTIYGKwCHJTx3JTxspI+YkxLsXsfnz9jNxMyQ/+CO3xzRjTuKg0mGP3fl1Q1xznm/8cenWMDUOrv/p1Wlg1XZ8s01edY= -ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; - dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org - header.b=LTwGL2cB; arc=none smtp.client-ip=10.30.226.201 -Authentication-Results: smtp.subspace.kernel.org; - dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org - header.b="LTwGL2cB" -Received: by smtp.kernel.org (Postfix) with ESMTPS id 1A3AEC2BBFC; - Tue, 30 Apr 2024 05:01:39 +0000 (UTC) -DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; - s=k20201202; t=1714453299; - bh=GGkybB3RbZ4yacytPZCe3ceKcaWca6ygWTw/PJtmpsk=; - h=From:Date:Subject:To:Cc:Reply-To:From; - b=LTwGL2cBtvmG8vpW/5yPEkA2A4EWbBIHkpxGRp6NhmQcwKx6T+Q4Gt/MKTUdGZ6pp - FHxkNOtF/KeqTZc814r9H7gtR+6rzRBCcQfWYl2TIdj+1edX/UrwUARQa8CQYwWK3V - jqfD9pCOCm+hptOHs6o0+j5FaW5TtN6QJTG/1GpftEfJkQYpsp/jEL28MY35u99DBK - yZErlS77MlNQEMScOR7McNtMj0pYnTvgrZLefdORzeWQhX6REODGKFL2xoSWjtg9jw - QeQUp07wKwtuwHpKI07IBsFwIsclZYD3/oXrjBSSZmvwHCCvAYT+PXRiH0moLzHERn - aa8XczXBSlBVw== -Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org - (localhost.localdomain [127.0.0.1]) - by smtp.lore.kernel.org (Postfix) with ESMTP id 04CA2C25B10; - Tue, 30 Apr 2024 05:01:39 +0000 (UTC) -From: =?utf-8?b?QXLEsW7DpyDDnE5BTCB2aWEgQjQgUmVsYXk=?= - -Date: Tue, 30 Apr 2024 08:01:33 +0300 -Subject: [PATCH net-next v2] net: dsa: mt7530: detect PHY muxing when PHY - is defined on switch MDIO bus -Precedence: bulk -X-Mailing-List: netdev@vger.kernel.org -List-Id: -List-Subscribe: -List-Unsubscribe: -MIME-Version: 1.0 -Message-Id: - <20240430-b4-for-netnext-mt7530-use-switch-mdio-bus-for-phy-muxing-v2-1-9104d886d0db@arinc9.com> -X-B4-Tracking: v=1; b=H4sIACx7MGYC/6WOSw6DMBBDr1LNulNBIHy66j0qFhAGmAUJSgIFI - e7eNFeovLJsPfsER5bJwfN2gqWNHRsdjLjfQE2tHgm5Dx5EIvIkFzV2OQ7Goiavafc4+1JmCa6 - O0H3Yqwnnng12q4u1ZTpwXnfWI8qqEEWdlamSEgJ+sTTwHqffEHD440ETkomdN/aIn7Y05v/Pb - ykGDWUp6yqjVMpXa1mr+qHMDM11XV8dryM7CwEAAA== -To: Daniel Golle , DENG Qingfang , - Sean Wang , Andrew Lunn , - Florian Fainelli , - Vladimir Oltean , - "David S. Miller" , Eric Dumazet , - Jakub Kicinski , Paolo Abeni , - Matthias Brugger , - AngeloGioacchino Del Regno -Cc: Bartel Eerdekens , - mithat.guner@xeront.com, erkin.bozoglu@xeront.com, netdev@vger.kernel.org, - linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, - linux-mediatek@lists.infradead.org, - =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= -X-Mailer: b4 0.13.0 -X-Developer-Signature: v=1; a=ed25519-sha256; t=1714453297; l=1949; - i=arinc.unal@arinc9.com; s=arinc9-PC; h=from:subject:message-id; - bh=c3IRARdnxa6x5otHszH4xrnla2RxJAal1114ej/d2wE=; - b=FL4WEHh4zYu1gBE7wbaN+X2OMCOIMJVsYBkXurHM0IC3CnI6XfpKE1V5QLUSXby75WZfvQ0se - lrMQos/eOAaCNbkyxUkmwb3opbC915iywMECA0lv/g0IAo6snRYzMae -X-Developer-Key: i=arinc.unal@arinc9.com; a=ed25519; - pk=Bd1s2kQtNfZAWyeLHg39jaWBDqt8Ud1WJXLFh7gxl20= -X-Endpoint-Received: by B4 Relay for arinc.unal@arinc9.com/arinc9-PC with - auth_id=158 -X-Original-From: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= -Reply-To: arinc.unal@arinc9.com -X-Patchwork-Delegate: kuba@kernel.org - -From: Arınç ÃœNAL - -Currently, the MT7530 DSA subdriver configures the MT7530 switch to provide -direct access to switch PHYs, meaning, the switch PHYs listen on the MDIO -bus the switch listens on. The PHY muxing feature makes use of this. - -This is problematic as the PHY may be attached before the switch is -initialised, in which case, the PHY will fail to be attached. - -Since commit 91374ba537bd ("net: dsa: mt7530: support OF-based registration -of switch MDIO bus"), we can describe the switch PHYs on the MDIO bus of -the switch on the device tree. Extend the check to detect PHY muxing when -the PHY is defined on the MDIO bus of the switch on the device tree. - -When the PHY is described this way, the switch will be initialised first, -then the switch MDIO bus will be registered. Only after these steps, the -PHY will be attached. - -Signed-off-by: Arınç ÃœNAL ---- -Changes in v2: -- Address the terminology on the patch log. -- Link to v1: https://lore.kernel.org/r/20240429-b4-for-netnext-mt7530-use-switch-mdio-bus-for-phy-muxing-v1-1-1f775983e155@arinc9.com ---- - drivers/net/dsa/mt7530.c | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - - ---- -base-commit: 5c4c0edca68a5841a8d53ccd49596fe199c8334c -change-id: 20240429-b4-for-netnext-mt7530-use-switch-mdio-bus-for-phy-muxing-586269371c55 - -Best regards, - ---- a/drivers/net/dsa/mt7530.c -+++ b/drivers/net/dsa/mt7530.c -@@ -2488,7 +2488,8 @@ mt7530_setup(struct dsa_switch *ds) - if (!phy_node) - continue; - -- if (phy_node->parent == priv->dev->of_node->parent) { -+ if (phy_node->parent == priv->dev->of_node->parent || -+ phy_node->parent->parent == priv->dev->of_node) { - ret = of_get_phy_mode(mac_np, &interface); - if (ret && ret != -ENODEV) { - of_node_put(mac_np); diff --git a/target/linux/generic/pending-6.6/360-selftests-bpf-portability-of-unprivileged-tests.patch b/target/linux/generic/pending-6.6/360-selftests-bpf-portability-of-unprivileged-tests.patch new file mode 100644 index 00000000000000..0f28834d48c0f3 --- /dev/null +++ b/target/linux/generic/pending-6.6/360-selftests-bpf-portability-of-unprivileged-tests.patch @@ -0,0 +1,26 @@ +From ecb8f9a7d69698ce20fc6f4d107718d56fa861df Mon Sep 17 00:00:00 2001 +From: Tony Ambardar +Date: Sat, 9 Mar 2024 16:44:53 -0800 +Subject: [PATCH] selftests/bpf: Improve portability of unprivileged tests + +The addition of general support for unprivileged tests in test_loader.c +breaks building test_verifier on non-glibc (e.g. musl) systems, due to the +inclusion of glibc extension '' in 'unpriv_helpers.c'. However, +the header is actually not needed, so remove it to restore building. + +Fixes: 1d56ade032a4 ("selftests/bpf: Unprivileged tests for test_loader.c") +Signed-off-by: Tony Ambardar +--- + tools/testing/selftests/bpf/unpriv_helpers.c | 1 - + 1 file changed, 1 deletion(-) + +--- a/tools/testing/selftests/bpf/unpriv_helpers.c ++++ b/tools/testing/selftests/bpf/unpriv_helpers.c +@@ -2,7 +2,6 @@ + + #include + #include +-#include + #include + + #include "unpriv_helpers.h" diff --git a/target/linux/generic/pending-6.6/742-net-phy-air_en8811h-reset-netdev-rules-when-LED-is-s.patch b/target/linux/generic/pending-6.6/742-net-phy-air_en8811h-reset-netdev-rules-when-LED-is-s.patch new file mode 100644 index 00000000000000..500567b4ed05b7 --- /dev/null +++ b/target/linux/generic/pending-6.6/742-net-phy-air_en8811h-reset-netdev-rules-when-LED-is-s.patch @@ -0,0 +1,45 @@ +From 9be9a00adfac8118b6d685e71696f83187308c66 Mon Sep 17 00:00:00 2001 +Message-ID: <9be9a00adfac8118b6d685e71696f83187308c66.1715125851.git.daniel@makrotopia.org> +From: Daniel Golle +Date: Tue, 7 May 2024 22:43:30 +0100 +Subject: [PATCH net] net: phy: air_en8811h: reset netdev rules when LED is set + manually +To: Andrew Lunn , + Heiner Kallweit , + Russell King , + David S. Miller , + Eric Dumazet , + Jakub Kicinski , + Paolo Abeni , + SkyLake Huang , + Eric Woudstra , + netdev@vger.kernel.org, + linux-kernel@vger.kernel.org + +Setting LED_OFF via the brightness_set should deactivate hw control, +so make sure netdev trigger rules also get cleared in that case. + +Fixes: 71e79430117d ("net: phy: air_en8811h: Add the Airoha EN8811H PHY driver") +Signed-off-by: Daniel Golle +--- +This is basically a stop-gap measure until unified LED handling has +been implemented accross all MediaTek and Airoha PHYs. +See also +https://patchwork.kernel.org/project/netdevbpf/patch/20240425023325.15586-3-SkyLake.Huang@mediatek.com/ + + drivers/net/phy/air_en8811h.c | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/drivers/net/phy/air_en8811h.c ++++ b/drivers/net/phy/air_en8811h.c +@@ -544,6 +544,10 @@ static int air_hw_led_on_set(struct phy_ + + changed |= (priv->led[index].rules != 0); + ++ /* clear netdev trigger rules in case LED_OFF has been set */ ++ if (!on) ++ priv->led[index].rules = 0; ++ + if (changed) + return phy_modify_mmd(phydev, MDIO_MMD_VEND2, + AIR_PHY_LED_ON(index), diff --git a/target/linux/generic/pending-6.6/795-01-net-dsa-mt7530-do-not-set-MT7530_P5_DIS-when-PHY-.patch b/target/linux/generic/pending-6.6/795-01-net-dsa-mt7530-do-not-set-MT7530_P5_DIS-when-PHY-.patch deleted file mode 100644 index 286c96e43bc0c7..00000000000000 --- a/target/linux/generic/pending-6.6/795-01-net-dsa-mt7530-do-not-set-MT7530_P5_DIS-when-PHY-.patch +++ /dev/null @@ -1,79 +0,0 @@ -From patchwork Sat Apr 27 11:24:42 2024 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 8bit -X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTCB2aWEgQjQgUmVsYXk=?= - -X-Patchwork-Id: 13645655 -From: =?utf-8?b?QXLEsW7DpyDDnE5BTCB2aWEgQjQgUmVsYXk=?= - -Date: Sat, 27 Apr 2024 14:24:42 +0300 -Subject: [PATCH net-next] net: dsa: mt7530: do not set MT7530_P5_DIS when - PHY muxing is being used -Precedence: bulk -X-Mailing-List: netdev@vger.kernel.org -List-Id: -List-Subscribe: -List-Unsubscribe: -MIME-Version: 1.0 -Message-Id: - <20240427-for-netnext-mt7530-do-not-disable-port5-when-phy-muxing-v1-1-793cdf9d7707@arinc9.com> -To: Daniel Golle , DENG Qingfang , - Sean Wang , Andrew Lunn , - Florian Fainelli , - Vladimir Oltean , - "David S. Miller" , Eric Dumazet , - Jakub Kicinski , Paolo Abeni , - Matthias Brugger , - AngeloGioacchino Del Regno -Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, - linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, - =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= -X-Mailer: b4 0.13.0 -X-Patchwork-Delegate: kuba@kernel.org - -From: Arınç ÃœNAL - -When the PHY muxing feature is in use, port 5 won't be defined in the -device tree. Because of this, the type member of the dsa_port structure for -this port will be assigned DSA_PORT_TYPE_UNUSED. The dsa_port_setup() -function calls ds->ops->port_disable() when the port type is -DSA_PORT_TYPE_UNUSED. - -The MT7530_P5_DIS bit is unset when PHY muxing is being used. -mt7530_port_disable() which is assigned to ds->ops->port_disable() is -called afterwards. Currently, mt7530_port_disable() sets MT7530_P5_DIS -which breaks network connectivity when PHY muxing is being used. - -Therefore, do not set MT7530_P5_DIS when PHY muxing is being used. - -Fixes: 377174c5760c ("net: dsa: mt7530: move MT753X_MTRAP operations for MT7530") -Reported-by: Daniel Golle -Signed-off-by: Arınç ÃœNAL ---- -Hello. - -I've sent this to net-next as the patch it fixes is on the current -development cycle. ---- - drivers/net/dsa/mt7530.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - - ---- -base-commit: 5c4c0edca68a5841a8d53ccd49596fe199c8334c -change-id: 20240427-for-netnext-mt7530-do-not-disable-port5-when-phy-muxing-7ff5fd0995d7 - -Best regards, - ---- a/drivers/net/dsa/mt7530.c -+++ b/drivers/net/dsa/mt7530.c -@@ -1220,7 +1220,7 @@ mt7530_port_disable(struct dsa_switch *d - if (priv->id != ID_MT7530 && priv->id != ID_MT7621) - return; - -- if (port == 5) -+ if (port == 5 && priv->p5_mode == GMAC5) - mt7530_set(priv, MT753X_MTRAP, MT7530_P5_DIS); - else if (port == 6) - mt7530_set(priv, MT753X_MTRAP, MT7530_P6_DIS); diff --git a/target/linux/generic/pending-6.6/796-net-dsa-mt7530-detect-PHY-muxing-when-PHY-is-defined-on-switch-MDIO-bus.patch b/target/linux/generic/pending-6.6/796-net-dsa-mt7530-detect-PHY-muxing-when-PHY-is-defined-on-switch-MDIO-bus.patch deleted file mode 100644 index f181be933a02d4..00000000000000 --- a/target/linux/generic/pending-6.6/796-net-dsa-mt7530-detect-PHY-muxing-when-PHY-is-defined-on-switch-MDIO-bus.patch +++ /dev/null @@ -1,136 +0,0 @@ -From patchwork Tue Apr 30 05:01:33 2024 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 8bit -X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTCB2aWEgQjQgUmVsYXk=?= - -X-Patchwork-Id: 13648264 -X-Patchwork-Delegate: kuba@kernel.org -Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org - [10.30.226.201]) - (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) - (No client certificate requested) - by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4C9C114A89; - Tue, 30 Apr 2024 05:01:39 +0000 (UTC) -Authentication-Results: smtp.subspace.kernel.org; - arc=none smtp.client-ip=10.30.226.201 -ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; - t=1714453299; cv=none; - b=gV4Z0elIASLrrICjPPmDeR0kBaXtdjeqbz/cnj3/0V74cRGmjd5sMQ4PtMYq5iPdJkWbhn4mzf/WX9xcqituDcVV7Vj68zrsE5d6NavvrMK9kf7Ef3Yyr8gEbekALfL9fKuF6ul7TeVFQiFoGQyAJNFzB9YAiQGJlWzw98bldMQ= -ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; - s=arc-20240116; t=1714453299; c=relaxed/simple; - bh=GGkybB3RbZ4yacytPZCe3ceKcaWca6ygWTw/PJtmpsk=; - h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:To:Cc; - b=QRWD6k4Qg1t5nZj6oj2xdwWDCGHQWHG2xj0lkYcEMm3dMkvPpLbCIOptpZBJtSq06TMxRjVJhgVJ9ATDTIYGKwCHJTx3JTxspI+YkxLsXsfnz9jNxMyQ/+CO3xzRjTuKg0mGP3fl1Q1xznm/8cenWMDUOrv/p1Wlg1XZ8s01edY= -ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; - dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org - header.b=LTwGL2cB; arc=none smtp.client-ip=10.30.226.201 -Authentication-Results: smtp.subspace.kernel.org; - dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org - header.b="LTwGL2cB" -Received: by smtp.kernel.org (Postfix) with ESMTPS id 1A3AEC2BBFC; - Tue, 30 Apr 2024 05:01:39 +0000 (UTC) -DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; - s=k20201202; t=1714453299; - bh=GGkybB3RbZ4yacytPZCe3ceKcaWca6ygWTw/PJtmpsk=; - h=From:Date:Subject:To:Cc:Reply-To:From; - b=LTwGL2cBtvmG8vpW/5yPEkA2A4EWbBIHkpxGRp6NhmQcwKx6T+Q4Gt/MKTUdGZ6pp - FHxkNOtF/KeqTZc814r9H7gtR+6rzRBCcQfWYl2TIdj+1edX/UrwUARQa8CQYwWK3V - jqfD9pCOCm+hptOHs6o0+j5FaW5TtN6QJTG/1GpftEfJkQYpsp/jEL28MY35u99DBK - yZErlS77MlNQEMScOR7McNtMj0pYnTvgrZLefdORzeWQhX6REODGKFL2xoSWjtg9jw - QeQUp07wKwtuwHpKI07IBsFwIsclZYD3/oXrjBSSZmvwHCCvAYT+PXRiH0moLzHERn - aa8XczXBSlBVw== -Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org - (localhost.localdomain [127.0.0.1]) - by smtp.lore.kernel.org (Postfix) with ESMTP id 04CA2C25B10; - Tue, 30 Apr 2024 05:01:39 +0000 (UTC) -From: =?utf-8?b?QXLEsW7DpyDDnE5BTCB2aWEgQjQgUmVsYXk=?= - -Date: Tue, 30 Apr 2024 08:01:33 +0300 -Subject: [PATCH net-next v2] net: dsa: mt7530: detect PHY muxing when PHY - is defined on switch MDIO bus -Precedence: bulk -X-Mailing-List: netdev@vger.kernel.org -List-Id: -List-Subscribe: -List-Unsubscribe: -MIME-Version: 1.0 -Message-Id: - <20240430-b4-for-netnext-mt7530-use-switch-mdio-bus-for-phy-muxing-v2-1-9104d886d0db@arinc9.com> -X-B4-Tracking: v=1; b=H4sIACx7MGYC/6WOSw6DMBBDr1LNulNBIHy66j0qFhAGmAUJSgIFI - e7eNFeovLJsPfsER5bJwfN2gqWNHRsdjLjfQE2tHgm5Dx5EIvIkFzV2OQ7Goiavafc4+1JmCa6 - O0H3Yqwnnng12q4u1ZTpwXnfWI8qqEEWdlamSEgJ+sTTwHqffEHD440ETkomdN/aIn7Y05v/Pb - ykGDWUp6yqjVMpXa1mr+qHMDM11XV8dryM7CwEAAA== -To: Daniel Golle , DENG Qingfang , - Sean Wang , Andrew Lunn , - Florian Fainelli , - Vladimir Oltean , - "David S. Miller" , Eric Dumazet , - Jakub Kicinski , Paolo Abeni , - Matthias Brugger , - AngeloGioacchino Del Regno -Cc: Bartel Eerdekens , - mithat.guner@xeront.com, erkin.bozoglu@xeront.com, netdev@vger.kernel.org, - linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, - linux-mediatek@lists.infradead.org, - =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= -X-Mailer: b4 0.13.0 -X-Developer-Signature: v=1; a=ed25519-sha256; t=1714453297; l=1949; - i=arinc.unal@arinc9.com; s=arinc9-PC; h=from:subject:message-id; - bh=c3IRARdnxa6x5otHszH4xrnla2RxJAal1114ej/d2wE=; - b=FL4WEHh4zYu1gBE7wbaN+X2OMCOIMJVsYBkXurHM0IC3CnI6XfpKE1V5QLUSXby75WZfvQ0se - lrMQos/eOAaCNbkyxUkmwb3opbC915iywMECA0lv/g0IAo6snRYzMae -X-Developer-Key: i=arinc.unal@arinc9.com; a=ed25519; - pk=Bd1s2kQtNfZAWyeLHg39jaWBDqt8Ud1WJXLFh7gxl20= -X-Endpoint-Received: by B4 Relay for arinc.unal@arinc9.com/arinc9-PC with - auth_id=158 -X-Original-From: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= -Reply-To: arinc.unal@arinc9.com -X-Patchwork-Delegate: kuba@kernel.org - -From: Arınç ÃœNAL - -Currently, the MT7530 DSA subdriver configures the MT7530 switch to provide -direct access to switch PHYs, meaning, the switch PHYs listen on the MDIO -bus the switch listens on. The PHY muxing feature makes use of this. - -This is problematic as the PHY may be attached before the switch is -initialised, in which case, the PHY will fail to be attached. - -Since commit 91374ba537bd ("net: dsa: mt7530: support OF-based registration -of switch MDIO bus"), we can describe the switch PHYs on the MDIO bus of -the switch on the device tree. Extend the check to detect PHY muxing when -the PHY is defined on the MDIO bus of the switch on the device tree. - -When the PHY is described this way, the switch will be initialised first, -then the switch MDIO bus will be registered. Only after these steps, the -PHY will be attached. - -Signed-off-by: Arınç ÃœNAL ---- -Changes in v2: -- Address the terminology on the patch log. -- Link to v1: https://lore.kernel.org/r/20240429-b4-for-netnext-mt7530-use-switch-mdio-bus-for-phy-muxing-v1-1-1f775983e155@arinc9.com ---- - drivers/net/dsa/mt7530.c | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - - ---- -base-commit: 5c4c0edca68a5841a8d53ccd49596fe199c8334c -change-id: 20240429-b4-for-netnext-mt7530-use-switch-mdio-bus-for-phy-muxing-586269371c55 - -Best regards, - ---- a/drivers/net/dsa/mt7530.c -+++ b/drivers/net/dsa/mt7530.c -@@ -2483,7 +2483,8 @@ mt7530_setup(struct dsa_switch *ds) - if (!phy_node) - continue; - -- if (phy_node->parent == priv->dev->of_node->parent) { -+ if (phy_node->parent == priv->dev->of_node->parent || -+ phy_node->parent->parent == priv->dev->of_node) { - ret = of_get_phy_mode(mac_np, &interface); - if (ret && ret != -ENODEV) { - of_node_put(mac_np); diff --git a/target/linux/ipq40xx/base-files/etc/board.d/02_network b/target/linux/ipq40xx/base-files/etc/board.d/02_network index e86d24fab5b587..df0fca754424d6 100644 --- a/target/linux/ipq40xx/base-files/etc/board.d/02_network +++ b/target/linux/ipq40xx/base-files/etc/board.d/02_network @@ -52,6 +52,7 @@ ipq40xx_setup_interfaces() aruba,ap-365|\ avm,fritzrepeater-1200|\ dlink,dap-2610|\ + engenius,eap1300|\ extreme-networks,ws-ap3915i|\ meraki,mr33|\ meraki,mr74|\ diff --git a/target/linux/ipq40xx/config-6.6 b/target/linux/ipq40xx/config-6.6 index 22101d7df0ecc5..52ac1a585e0eb7 100644 --- a/target/linux/ipq40xx/config-6.6 +++ b/target/linux/ipq40xx/config-6.6 @@ -330,6 +330,7 @@ CONFIG_NVMEM=y CONFIG_NVMEM_QCOM_QFPROM=y # CONFIG_NVMEM_QCOM_SEC_QFPROM is not set # CONFIG_NVMEM_SPMI_SDAM is not set +CONFIG_NVMEM_U_BOOT_ENV=y CONFIG_NVMEM_SYSFS=y CONFIG_OF=y CONFIG_OF_ADDRESS=y diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac.dts index ceaa1edd45972b..07262f9ed5c586 100644 --- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac.dts +++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac.dts @@ -98,19 +98,6 @@ qcom,wifi_noc_memtype_m0_m2 = ; }; - usb2@60f8800 { - status = "okay"; - }; - - usb3@8af8800 { - status = "okay"; - - dwc3@8a00000 { - phys = <&usb3_hs_phy>; - phy-names = "usb2-phy"; - }; - }; - crypto@8e3a000 { status = "okay"; }; @@ -323,10 +310,23 @@ status = "okay"; }; +&usb2 { + status = "okay"; +}; + &usb3_hs_phy { status = "okay"; }; +&usb3 { + status = "okay"; +}; + +&usb3_dwc { + phys = <&usb3_hs_phy>; + phy-names = "usb2-phy"; +}; + &gmac { status = "okay"; }; diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-ea6350v3.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-ea6350v3.dts index 50e7f3d4e0c8b6..396d4e5fea49ae 100644 --- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-ea6350v3.dts +++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-ea6350v3.dts @@ -50,14 +50,6 @@ qcom,wifi_noc_memtype_m0_m2 = ; }; - usb2@60f8800 { - status = "okay"; - }; - - usb3@8af8800 { - status = "okay"; - }; - crypto@8e3a000 { status = "okay"; }; @@ -307,6 +299,14 @@ status = "okay"; }; +&usb3 { + status = "okay"; +}; + &usb2_hs_phy { status = "okay"; }; + +&usb2 { + status = "okay"; +}; diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-eap1300.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-eap1300.dts index e9d4775fd87ad4..bfbed30b90d4e5 100644 --- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-eap1300.dts +++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-eap1300.dts @@ -200,8 +200,13 @@ reg = <0x190000 0x1dc0000>; }; partition9@1f50000 { + compatible = "u-boot,env"; label = "u-boot-env"; reg = <0x01f50000 0x00010000>; + + macaddr_ubootenv_ethaddr: ethaddr { + #nvmem-cell-cells = <1>; + }; }; partition10@1f60000 { label = "userconfig"; @@ -221,16 +226,35 @@ status = "okay"; }; +&switch { + status = "okay"; +}; + +&swport5 { + status = "okay"; + label = "lan"; + nvmem-cell-names = "mac-address"; + nvmem-cells = <&macaddr_ubootenv_ethaddr 0>; +}; + +&gmac { + status = "okay"; +}; + +&mdio { + status = "okay"; +}; + &wifi0 { status = "okay"; - nvmem-cell-names = "pre-calibration"; - nvmem-cells = <&precal_art_1000>; + nvmem-cell-names = "pre-calibration", "mac-address"; + nvmem-cells = <&precal_art_1000>, <&macaddr_ubootenv_ethaddr 1>; qcom,ath10k-calibration-variant = "EnGenius-EAP1300"; }; &wifi1 { status = "okay"; - nvmem-cell-names = "pre-calibration"; - nvmem-cells = <&precal_art_5000>; + nvmem-cell-names = "pre-calibration", "mac-address"; + nvmem-cells = <&precal_art_5000>, <&macaddr_ubootenv_ethaddr 2>; qcom,ath10k-calibration-variant = "EnGenius-EAP1300"; }; diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-ecw5211.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-ecw5211.dts index e74d110b3df38e..4f3d00c6788588 100644 --- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-ecw5211.dts +++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-ecw5211.dts @@ -89,19 +89,6 @@ qcom,wifi_noc_memtype_m0_m2 = ; }; - usb2@60f8800 { - status = "okay"; - }; - - usb3@8af8800 { - status = "okay"; - - dwc3@8a00000 { - phys = <&usb3_hs_phy>; - phy-names = "usb2-phy"; - }; - }; - crypto@8e3a000 { status = "okay"; }; @@ -325,10 +312,23 @@ qcom,ath10k-calibration-variant = "ALFA-Network-AP120C-AC"; }; +&usb2_hs_phy { + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; + &usb3_hs_phy { status = "okay"; }; -&usb2_hs_phy { +&usb3 { status = "okay"; }; + +&usb3_dwc { + phys = <&usb3_hs_phy>; + phy-names = "usb2-phy"; +}; diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-emr3500.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-emr3500.dts index 701dc936f14b20..8f108a3f9f6902 100644 --- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-emr3500.dts +++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-emr3500.dts @@ -37,10 +37,6 @@ qcom,wifi_noc_memtype_m0_m2 = ; }; - usb2_hs_phy: hsphy@a8000 { - status = "okay"; - }; - crypto@8e3a000 { status = "okay"; }; diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-fritzbox-4040.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-fritzbox-4040.dts index 524bcbcb2b2a26..572e6545c48f36 100644 --- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-fritzbox-4040.dts +++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-fritzbox-4040.dts @@ -51,14 +51,6 @@ qcom,wifi_noc_memtype_m0_m2 = ; }; - usb2@60f8800 { - status = "okay"; - }; - - usb3@8af8800 { - status = "okay"; - }; - crypto@8e3a000 { status = "okay"; }; @@ -315,10 +307,18 @@ status = "okay"; }; +&usb3 { + status = "okay"; +}; + &usb2_hs_phy { status = "okay"; }; +&usb2 { + status = "okay"; +}; + &wifi0 { status = "okay"; qcom,ath10k-calibration-variant = "AVM-FRITZBox-4040"; diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-gl-ap1300.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-gl-ap1300.dts index 5fc97d7bb2b6e9..fb0175aecab9da 100644 --- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-gl-ap1300.dts +++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-gl-ap1300.dts @@ -61,14 +61,6 @@ qcom,wifi_noc_memtype_m0_m2 = ; }; - usb2@60f8800 { - status = "okay"; - }; - - usb3@8af8800 { - status = "okay"; - }; - crypto@8e3a000 { status = "okay"; }; @@ -261,6 +253,10 @@ status = "okay"; }; +&usb2 { + status = "okay"; +}; + &usb3_hs_phy { status = "okay"; }; @@ -269,6 +265,10 @@ status = "okay"; }; +&usb3 { + status = "okay"; +}; + &gmac { status = "okay"; }; diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-hap-ac2.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-hap-ac2.dts index fa3ed8b054455a..deee82b1a68ca0 100644 --- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-hap-ac2.dts +++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-hap-ac2.dts @@ -63,15 +63,6 @@ qcom,wifi_noc_memtype_m0_m2 = ; }; - usb3@8af8800 { - status = "okay"; - - dwc3@8a00000 { - phys = <&usb3_hs_phy>; - phy-names = "usb2-phy"; - }; - }; - crypto@8e3a000 { status = "okay"; }; @@ -219,6 +210,15 @@ status = "okay"; }; +&usb3 { + status = "okay"; +}; + +&usb3_dwc { + phys = <&usb3_hs_phy>; + phy-names = "usb2-phy"; +}; + &mdio { status = "okay"; }; diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-nbg6617.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-nbg6617.dts index a9e96835920757..cb40b87e56e416 100644 --- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-nbg6617.dts +++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-nbg6617.dts @@ -60,39 +60,6 @@ qcom,wifi_noc_memtype_m0_m2 = ; }; - usb2@60f8800 { - status = "okay"; - - dwc3@6000000 { - #address-cells = <1>; - #size-cells = <0>; - - usb2_port1: port@1 { - reg = <1>; - #trigger-source-cells = <0>; - }; - }; - }; - - usb3@8af8800 { - status = "okay"; - - dwc3@8a00000 { - #address-cells = <1>; - #size-cells = <0>; - - usb3_port1: port@1 { - reg = <1>; - #trigger-source-cells = <0>; - }; - - usb3_port2: port@2 { - reg = <2>; - #trigger-source-cells = <0>; - }; - }; - }; - crypto@8e3a000 { status = "okay"; }; @@ -360,6 +327,39 @@ status = "okay"; }; +&usb3 { + status = "okay"; +}; + +&usb3_dwc { + #address-cells = <1>; + #size-cells = <0>; + + usb3_port1: port@1 { + reg = <1>; + #trigger-source-cells = <0>; + }; + + usb3_port2: port@2 { + reg = <2>; + #trigger-source-cells = <0>; + }; +}; + &usb2_hs_phy { status = "okay"; }; + +&usb2 { + status = "okay"; + + usb@6000000 { + #address-cells = <1>; + #size-cells = <0>; + + usb2_port1: port@1 { + reg = <1>; + #trigger-source-cells = <0>; + }; + }; +}; diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-rt-ac58u.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-rt-ac58u.dts index 38158fbfa70e1c..ecf652368c9fca 100644 --- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-rt-ac58u.dts +++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-rt-ac58u.dts @@ -55,25 +55,6 @@ qcom,wifi_noc_memtype_m0_m2 = ; }; - usb3@8af8800 { - status = "okay"; - - dwc3@8a00000 { - #address-cells = <1>; - #size-cells = <0>; - - usb3_port1: port@1 { - reg = <1>; - #trigger-source-cells = <0>; - }; - - usb3_port2: port@2 { - reg = <2>; - #trigger-source-cells = <0>; - }; - }; - }; - crypto@8e3a000 { status = "okay"; }; @@ -291,6 +272,25 @@ status = "okay"; }; +&usb3 { + status = "okay"; +}; + +&usb3_dwc { + #address-cells = <1>; + #size-cells = <0>; + + usb3_port1: port@1 { + reg = <1>; + #trigger-source-cells = <0>; + }; + + usb3_port2: port@2 { + reg = <2>; + #trigger-source-cells = <0>; + }; +}; + &gmac { status = "okay"; }; diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-wap-ac-lte.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-wap-ac-lte.dts index 8ff18d92b77d8d..5cb103b32148cf 100644 --- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-wap-ac-lte.dts +++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-wap-ac-lte.dts @@ -15,15 +15,6 @@ qcom,usb-hsphy-mode-select = ; status = "okay"; }; - - usb3@8af8800 { - status = "okay"; - - dwc3@8a00000 { - phys = <&usb3_hs_phy>; - phy-names = "usb2-phy"; - }; - }; }; }; @@ -43,3 +34,8 @@ &usb3 { status = "okay"; }; + +&usb3_dwc { + phys = <&usb3_hs_phy>; + phy-names = "usb2-phy"; +}; diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-wap-r-ac.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-wap-r-ac.dts index e7f28f23cf494a..bf50ebfc544e40 100644 --- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-wap-r-ac.dts +++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-wap-r-ac.dts @@ -15,15 +15,6 @@ qcom,usb-hsphy-mode-select = ; status = "okay"; }; - - usb3@8af8800 { - status = "okay"; - - dwc3@8a00000 { - phys = <&usb3_hs_phy>; - phy-names = "usb2-phy"; - }; - }; }; }; @@ -43,3 +34,8 @@ &usb3 { status = "okay"; }; + +&usb3_dwc { + phys = <&usb3_hs_phy>; + phy-names = "usb2-phy"; +}; diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-wrtq-329acn.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-wrtq-329acn.dts index f3c6f34bf4f550..26c8c0244a734c 100644 --- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-wrtq-329acn.dts +++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-wrtq-329acn.dts @@ -69,14 +69,6 @@ qcom,wifi_noc_memtype_m0_m2 = ; }; - usb2@60f8800 { - status = "okay"; - }; - - usb3@8af8800 { - status = "okay"; - }; - crypto@8e3a000 { status = "okay"; }; @@ -282,6 +274,10 @@ status = "okay"; }; +&usb2 { + status = "okay"; +}; + &usb3_hs_phy { status = "okay"; }; @@ -290,6 +286,10 @@ status = "okay"; }; +&usb3 { + status = "okay"; +}; + &wifi0 { status = "okay"; nvmem-cell-names = "pre-calibration"; diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-cm520-79f.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-cm520-79f.dts index d1c8d798f9f425..b4f536fdb8e02f 100644 --- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-cm520-79f.dts +++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-cm520-79f.dts @@ -54,39 +54,6 @@ qcom,wifi_noc_memtype_m0_m2 = ; }; - usb2@60f8800 { - status = "okay"; - - dwc3@6000000 { - #address-cells = <1>; - #size-cells = <0>; - - usb2_port1: port@1 { - reg = <1>; - #trigger-source-cells = <0>; - }; - }; - }; - - usb3@8af8800 { - status = "okay"; - - dwc3@8a00000 { - #address-cells = <1>; - #size-cells = <0>; - - usb3_port1: port@1 { - reg = <1>; - #trigger-source-cells = <0>; - }; - - usb3_port2: port@2 { - reg = <2>; - #trigger-source-cells = <0>; - }; - }; - }; - crypto@8e3a000 { status = "okay"; }; @@ -344,10 +311,43 @@ status = "okay"; }; +&usb3 { + status = "okay"; +}; + +&usb3_dwc { + #address-cells = <1>; + #size-cells = <0>; + + usb3_port1: port@1 { + reg = <1>; + #trigger-source-cells = <0>; + }; + + usb3_port2: port@2 { + reg = <2>; + #trigger-source-cells = <0>; + }; +}; + &usb2_hs_phy { status = "okay"; }; +&usb2 { + status = "okay"; + + usb@6000000 { + #address-cells = <1>; + #size-cells = <0>; + + usb2_port1: port@1 { + reg = <1>; + #trigger-source-cells = <0>; + }; + }; +}; + &gmac { status = "okay"; diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-e2600ac.dtsi b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-e2600ac.dtsi index 9216a7c9f8beb0..6ea0eb2b55bf99 100644 --- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-e2600ac.dtsi +++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-e2600ac.dtsi @@ -202,20 +202,20 @@ &usb3 { status = "okay"; +}; - dwc3@8a00000 { - #address-cells = <1>; - #size-cells = <0>; +&usb3_dwc { + #address-cells = <1>; + #size-cells = <0>; - usb3_port1: port@1 { - reg = <1>; - #trigger-source-cells = <0>; - }; + usb3_port1: port@1 { + reg = <1>; + #trigger-source-cells = <0>; + }; - usb3_port2: port@2 { - reg = <2>; - #trigger-source-cells = <0>; - }; + usb3_port2: port@2 { + reg = <2>; + #trigger-source-cells = <0>; }; }; @@ -230,7 +230,7 @@ &usb2 { status = "okay"; - dwc3@6000000 { + usb@6000000 { #address-cells = <1>; #size-cells = <0>; diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-fritzbox-7530.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-fritzbox-7530.dts index a118bdf26bd6ca..2c86cd57bc950c 100644 --- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-fritzbox-7530.dts +++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-fritzbox-7530.dts @@ -54,10 +54,6 @@ qcom,wifi_noc_memtype_m0_m2 = ; }; - usb3@8af8800 { - status = "okay"; - }; - crypto@8e3a000 { status = "okay"; }; @@ -266,6 +262,10 @@ status = "okay"; }; +&usb3 { + status = "okay"; +}; + &qpic_bam { status = "okay"; }; diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-le1.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-le1.dts index c4e7d0b2075a81..1577ed58bba46c 100644 --- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-le1.dts +++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-le1.dts @@ -269,7 +269,7 @@ &usb2 { status = "okay"; - dwc3@6000000 { + usb@6000000 { #address-cells = <1>; #size-cells = <0>; @@ -286,20 +286,20 @@ &usb3 { status = "okay"; +}; - dwc3@8a00000 { - #address-cells = <1>; - #size-cells = <0>; +&usb3_dwc { + #address-cells = <1>; + #size-cells = <0>; - usb3_port1: port@1 { - reg = <1>; - #trigger-source-cells = <0>; - }; + usb3_port1: port@1 { + reg = <1>; + #trigger-source-cells = <0>; + }; - usb3_port2: port@2 { - reg = <2>; - #trigger-source-cells = <0>; - }; + usb3_port2: port@2 { + reg = <2>; + #trigger-source-cells = <0>; }; }; diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-map-ac2200.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-map-ac2200.dts index 32f0473fb169ae..30101b0c3a36f8 100644 --- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-map-ac2200.dts +++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-map-ac2200.dts @@ -45,10 +45,6 @@ qcom,wifi_noc_memtype_m0_m2 = ; }; - usb2@60f8800 { - status = "okay"; - }; - crypto@8e3a000 { status = "okay"; }; @@ -233,6 +229,10 @@ status = "okay"; }; +&usb2 { + status = "okay"; +}; + &blsp1_i2c3 { pinctrl-0 = <&i2c_0_pins>; pinctrl-names = "default"; diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-mf18a.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-mf18a.dts index 6987515720408f..9bc12be8efe6ff 100644 --- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-mf18a.dts +++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-mf18a.dts @@ -135,14 +135,6 @@ qcom,wifi_noc_memtype_m0_m2 = ; }; - usb2@60f8800 { - status = "okay"; - }; - - usb3@8af8800 { - status = "okay"; - }; - crypto@8e3a000 { status = "okay"; }; @@ -449,6 +441,10 @@ status = "okay"; }; +&usb2 { + status = "okay"; +}; + &usb3_ss_phy { status = "okay"; }; @@ -457,6 +453,10 @@ status = "okay"; }; +&usb3 { + status = "okay"; +}; + &wifi0 { status = "okay"; nvmem-cell-names = "pre-calibration", "mac-address"; diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-mf282plus.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-mf282plus.dts index 54353cac58e7d7..ede92f7e22a9f4 100644 --- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-mf282plus.dts +++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-mf282plus.dts @@ -118,14 +118,6 @@ qcom,wifi_noc_memtype_m0_m2 = ; }; - usb2@60f8800 { - status = "okay"; - }; - - usb3@8af8800 { - status = "okay"; - }; - crypto@8e3a000 { status = "okay"; }; @@ -423,6 +415,10 @@ status = "okay"; }; +&usb2 { + status = "okay"; +}; + &usb3_ss_phy { status = "okay"; }; @@ -431,6 +427,10 @@ status = "okay"; }; +&usb3 { + status = "okay"; +}; + /* * The MD5 sum of the board file of the MF286D is identical to the board * file in the OEM firmware diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-mf286d.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-mf286d.dts index 61cbdba0d12a8b..cd1c3c732f4808 100644 --- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-mf286d.dts +++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-mf286d.dts @@ -111,14 +111,6 @@ qcom,wifi_noc_memtype_m0_m2 = ; }; - usb2@60f8800 { - status = "okay"; - }; - - usb3@8af8800 { - status = "okay"; - }; - crypto@8e3a000 { status = "okay"; }; @@ -430,6 +422,10 @@ status = "okay"; }; +&usb2 { + status = "okay"; +}; + &usb3_ss_phy { status = "okay"; }; @@ -438,6 +434,10 @@ status = "okay"; }; +&usb3 { + status = "okay"; +}; + &wifi0 { status = "okay"; nvmem-cell-names = "pre-calibration", "mac-address"; diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-ncp-hg100-cellular.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-ncp-hg100-cellular.dts index ea27defea3de85..a23654e4c816ff 100644 --- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-ncp-hg100-cellular.dts +++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-ncp-hg100-cellular.dts @@ -582,15 +582,15 @@ pinctrl-0 = <&usb3_pins>, <<e_pins>; pinctrl-names = "default"; +}; - dwc3@8a00000 { - #address-cells = <1>; - #size-cells = <0>; +&usb3_dwc { + #address-cells = <1>; + #size-cells = <0>; - device@1 { - compatible = "usb1bc7,1900"; - reg = <1>; - }; + device@1 { + compatible = "usb1bc7,1900"; + reg = <1>; }; }; diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-oap100.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-oap100.dts index 2080a34e2f864d..f3f9395b411e3a 100644 --- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-oap100.dts +++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-oap100.dts @@ -53,39 +53,6 @@ status = "okay"; }; - usb2@60f8800 { - status = "okay"; - - dwc3@6000000 { - #address-cells = <1>; - #size-cells = <0>; - - usb2_port1: port@1 { - reg = <1>; - #trigger-source-cells = <0>; - }; - }; - }; - - usb3@8af8800 { - status = "okay"; - - dwc3@8a00000 { - #address-cells = <1>; - #size-cells = <0>; - - usb3_port1: port@1 { - reg = <1>; - #trigger-source-cells = <0>; - }; - - usb3_port2: port@2 { - reg = <2>; - #trigger-source-cells = <0>; - }; - }; - }; - crypto@8e3a000 { status = "okay"; }; @@ -337,6 +304,40 @@ status = "okay"; }; +&usb3 { + status = "okay"; +}; + +&usb3_dwc { + #address-cells = <1>; + #size-cells = <0>; + + usb3_port1: port@1 { + reg = <1>; + #trigger-source-cells = <0>; + }; + + usb3_port2: port@2 { + reg = <2>; + #trigger-source-cells = <0>; + }; +}; + + &usb2_hs_phy { status = "okay"; }; + +&usb2 { + status = "okay"; + + usb@6000000 { + #address-cells = <1>; + #size-cells = <0>; + + usb2_port1: port@1 { + reg = <1>; + #trigger-source-cells = <0>; + }; + }; +}; diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-r619ac.dtsi b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-r619ac.dtsi index 90e5455b25a969..0abc3aff55817f 100644 --- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-r619ac.dtsi +++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-r619ac.dtsi @@ -53,14 +53,6 @@ qcom,wifi_noc_memtype_m0_m2 = ; }; - usb2@60f8800 { - status = "okay"; - }; - - usb3@8af8800 { - status = "okay"; - }; - crypto@8e3a000 { status = "okay"; }; @@ -364,10 +356,18 @@ status = "okay"; }; +&usb3 { + status = "okay"; +}; + &usb2_hs_phy { status = "okay"; }; +&usb2 { + status = "okay"; +}; + &vqmmc { status = "okay"; }; diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-rbr50.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-rbr50.dts index a803999804a51e..f83f75b46438ea 100644 --- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-rbr50.dts +++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-rbr50.dts @@ -9,22 +9,20 @@ chosen { bootargs = "root=/dev/mmcblk0p20 blkdevparts=mmcblk0:512K@17K(0:SBL1)ro,512K(0:BOOTCONFIG)ro,512K(0:QSEE)ro,512K(0:QSEE_ALT)ro,256K(0:CDT)ro,256K(0:CDT_ALT)ro,256K(0:DDRPARAMS)ro,256K(0:APPSBLENV)ro,1M(0:APPSBL)ro,1M(0:APPSBL_ALT)ro,256K(0:ART)ro,256K(ARTMTD)ro,2M(language)ro,256K(config)ro,256K(pot)ro,256K(traffic_meter)ro,256K(pot_bak)ro,256K(traffic_meter.bak)ro,3840K(kernel),31488K(rootfs),35328K@9233K(firmware),256K(mtdoops)ro,1457651200(reserved)ro,-(unallocated) rootfstype=squashfs,ext4 rootwait"; }; - - soc { - usb2@60f8800 { - status = "okay"; - }; - - usb3@8af8800 { - status = "okay"; - }; - }; }; &usb3_hs_phy { status = "okay"; }; +&usb3 { + status = "okay"; +}; + &usb2_hs_phy { status = "okay"; }; + +&usb2 { + status = "okay"; +}; diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-rbs50.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-rbs50.dts index 4d0a9132c6ab8f..9151c5d33c59be 100644 --- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-rbs50.dts +++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-rbs50.dts @@ -9,22 +9,20 @@ chosen { bootargs = "root=/dev/mmcblk0p20 blkdevparts=mmcblk0:512K@17K(0:SBL1)ro,512K(0:BOOTCONFIG)ro,512K(0:QSEE)ro,512K(0:QSEE_ALT)ro,256K(0:CDT)ro,256K(0:CDT_ALT)ro,256K(0:DDRPARAMS)ro,256K(0:APPSBLENV)ro,1M(0:APPSBL)ro,1M(0:APPSBL_ALT)ro,256K(0:ART)ro,256K(ARTMTD)ro,2M(language)ro,256K(config)ro,256K(pot)ro,256K(traffic_meter)ro,256K(pot_bak)ro,256K(traffic_meter.bak)ro,3840K(kernel),31488K(rootfs),35328K@9233K(firmware),256K(mtdoops)ro,1457651200(reserved)ro,-(unallocated) rootfstype=squashfs,ext4 rootwait"; }; - - soc { - usb2@60f8800 { - status = "okay"; - }; - - usb3@8af8800 { - status = "okay"; - }; - }; }; &usb3_hs_phy { status = "okay"; }; +&usb3 { + status = "okay"; +}; + &usb2_hs_phy { status = "okay"; }; + +&usb2 { + status = "okay"; +}; diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-rt-ac42u.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-rt-ac42u.dts index 70849d71d67fab..2854809bfe42bc 100644 --- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-rt-ac42u.dts +++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-rt-ac42u.dts @@ -55,25 +55,6 @@ qcom,wifi_noc_memtype_m0_m2 = ; }; - usb3@8af8800 { - status = "okay"; - - dwc3@8a00000 { - #address-cells = <1>; - #size-cells = <0>; - - usb3_port1: port@1 { - reg = <1>; - #trigger-source-cells = <0>; - }; - - usb3_port2: port@2 { - reg = <2>; - #trigger-source-cells = <0>; - }; - }; - }; - crypto@8e3a000 { status = "okay"; }; @@ -269,6 +250,25 @@ status = "okay"; }; +&usb3 { + status = "okay"; +}; + +&usb3_dwc { + #address-cells = <1>; + #size-cells = <0>; + + usb3_port1: port@1 { + reg = <1>; + #trigger-source-cells = <0>; + }; + + usb3_port2: port@2 { + reg = <2>; + #trigger-source-cells = <0>; + }; +}; + &gmac { status = "okay"; }; diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-rtl30vw.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-rtl30vw.dts index e2df1d1997609d..e2d435133b7edf 100644 --- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-rtl30vw.dts +++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-rtl30vw.dts @@ -172,14 +172,6 @@ qcom,wifi_noc_memtype_m0_m2 = ; }; - usb2@60f8800 { - status = "okay"; - }; - - usb3@8af8800 { - status = "okay"; - }; - crypto@8e3a000 { status = "okay"; }; @@ -358,6 +350,10 @@ status = "okay"; }; +&usb2 { + status = "okay"; +}; + &usb3_ss_phy { status = "okay"; }; @@ -366,6 +362,10 @@ status = "okay"; }; +&usb3 { + status = "okay"; +}; + &wifi0 { status = "okay"; qcom,ath10k-calibration-variant = "cellc,rtl30vw"; diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-u4019.dtsi b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-u4019.dtsi index c7439b87ec968f..e31f10f9d30f98 100644 --- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-u4019.dtsi +++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-u4019.dtsi @@ -46,39 +46,6 @@ qcom,wifi_noc_memtype_m0_m2 = ; }; - usb2@60f8800 { - status = "okay"; - - dwc3@6000000 { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - #trigger-source-cells = <0>; - }; - }; - }; - - usb3@8af8800 { - status = "okay"; - - dwc3@8a00000 { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - #trigger-source-cells = <0>; - }; - - port@2 { - reg = <2>; - #trigger-source-cells = <0>; - }; - }; - }; - watchdog@b017000 { status = "okay"; }; @@ -199,10 +166,44 @@ status = "okay"; }; +&usb3 { + status = "okay"; +}; + +&usb3_dwc { + #address-cells = <1>; + #size-cells = <0>; + + usb3_port1: port@1 { + reg = <1>; + #trigger-source-cells = <0>; + }; + + usb3_port2: port@2 { + reg = <2>; + #trigger-source-cells = <0>; + }; +}; + + &usb2_hs_phy { status = "okay"; }; +&usb2 { + status = "okay"; + + usb@6000000 { + #address-cells = <1>; + #size-cells = <0>; + + usb2_port1: port@1 { + reg = <1>; + #trigger-source-cells = <0>; + }; + }; +}; + &wifi0 { status = "okay"; nvmem-cell-names = "pre-calibration"; diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-wpj419.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-wpj419.dts index 2dc4544433474b..d99cbdb608d740 100644 --- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-wpj419.dts +++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-wpj419.dts @@ -300,26 +300,6 @@ status = "okay"; }; - usb3_ss_phy: ssphy@9a000 { - status = "okay"; - }; - - usb3_hs_phy: hsphy@a6000 { - status = "okay"; - }; - - usb3: usb3@8af8800 { - status = "okay"; - }; - - usb2_hs_phy: hsphy@a8000 { - status = "okay"; - }; - - usb2: usb2@60f8800 { - status = "okay"; - }; - cryptobam: dma@8e04000 { status = "okay"; }; @@ -354,6 +334,26 @@ }; }; +&usb3_ss_phy { + status = "okay"; +}; + +&usb3_hs_phy { + status = "okay"; +}; + +&usb3 { + status = "okay"; +}; + +&usb2_hs_phy { + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; + &nand { pinctrl-0 = <&nand_pins>; pinctrl-names = "default"; diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-wtr-m2133hp.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-wtr-m2133hp.dts index 00b5897b7dbac1..37383b015d426a 100644 --- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-wtr-m2133hp.dts +++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-wtr-m2133hp.dts @@ -72,10 +72,6 @@ watchdog@b017000 { status = "okay"; }; - - usb3@8af8800 { - status = "okay"; - }; }; leds { @@ -470,3 +466,7 @@ &usb3_hs_phy { status = "okay"; }; + +&usb3 { + status = "okay"; +}; diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-x1pro.dtsi b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-x1pro.dtsi index fe3650ca580771..8f0fd9a89f1203 100644 --- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-x1pro.dtsi +++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-x1pro.dtsi @@ -56,39 +56,6 @@ qcom,wifi_noc_memtype_m0_m2 = ; }; - usb2@60f8800 { - status = "okay"; - - dwc3@6000000 { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - #trigger-source-cells = <0>; - }; - }; - }; - - usb3@8af8800 { - status = "okay"; - - dwc3@8a00000 { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - #trigger-source-cells = <0>; - }; - - port@2 { - reg = <2>; - #trigger-source-cells = <0>; - }; - }; - }; - watchdog@b017000 { status = "okay"; }; @@ -201,10 +168,43 @@ status = "okay"; }; +&usb3 { + status = "okay"; +}; + +&usb3_dwc { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + #trigger-source-cells = <0>; + }; + + port@2 { + reg = <2>; + #trigger-source-cells = <0>; + }; +}; + &usb2_hs_phy { status = "okay"; }; +&usb2 { + status = "okay"; + + usb@6000000 { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + #trigger-source-cells = <0>; + }; + }; +}; + &wifi0 { status = "okay"; nvmem-cell-names = "pre-calibration"; diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-xx8300.dtsi b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-xx8300.dtsi index 141ea604425a5e..83574f89c769a0 100644 --- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-xx8300.dtsi +++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-xx8300.dtsi @@ -59,39 +59,6 @@ qcom,wifi_noc_memtype_m0_m2 = ; }; - usb2@60f8800 { - status = "okay"; - - dwc3@6000000 { - #address-cells = <1>; - #size-cells = <0>; - - usb2_port1: port@1 { - reg = <1>; - #trigger-source-cells = <0>; - }; - }; - }; - - usb3@8af8800 { - status = "okay"; - - dwc3@8a00000 { - #address-cells = <1>; - #size-cells = <0>; - - usb3_port1: port@1 { - reg = <1>; - #trigger-source-cells = <0>; - }; - - usb3_port2: port@2 { - reg = <2>; - #trigger-source-cells = <0>; - }; - }; - }; - crypto@8e3a000 { status = "okay"; }; @@ -289,6 +256,20 @@ status = "okay"; }; +&usb2 { + status = "okay"; + + usb@6000000 { + #address-cells = <1>; + #size-cells = <0>; + + usb2_port1: port@1 { + reg = <1>; + #trigger-source-cells = <0>; + }; + }; +}; + &usb3_hs_phy { status = "okay"; }; @@ -297,6 +278,25 @@ status = "okay"; }; +&usb3 { + status = "okay"; +}; + +&usb3_dwc { + #address-cells = <1>; + #size-cells = <0>; + + usb3_port1: port@1 { + reg = <1>; + #trigger-source-cells = <0>; + }; + + usb3_port2: port@2 { + reg = <2>; + #trigger-source-cells = <0>; + }; +}; + &gmac { status = "okay"; }; diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4029-gl-b1300.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4029-gl-b1300.dts index 13ed26d5d6082e..e424a021b78bfd 100644 --- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4029-gl-b1300.dts +++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4029-gl-b1300.dts @@ -72,14 +72,6 @@ qcom,wifi_noc_memtype_m0_m2 = ; }; - usb2@60f8800 { - status = "okay"; - }; - - usb3@8af8800 { - status = "okay"; - }; - crypto@8e3a000 { status = "okay"; }; @@ -275,6 +267,10 @@ status = "okay"; }; +&usb2 { + status = "okay"; +}; + &usb3_hs_phy { status = "okay"; }; @@ -283,6 +279,10 @@ status = "okay"; }; +&usb3 { + status = "okay"; +}; + &gmac { status = "okay"; }; diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4029-gl-s1300.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4029-gl-s1300.dts index e7236824aa0fee..b7ff970b25e896 100644 --- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4029-gl-s1300.dts +++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4029-gl-s1300.dts @@ -57,14 +57,6 @@ qcom,wifi_noc_memtype_m0_m2 = ; }; - usb2@60f8800 { - status = "okay"; - }; - - usb3@8af8800 { - status = "okay"; - }; - crypto@8e3a000 { status = "okay"; }; @@ -340,6 +332,10 @@ status = "okay"; }; +&usb2 { + status = "okay"; +}; + &usb3_hs_phy { status = "okay"; }; @@ -348,6 +344,10 @@ status = "okay"; }; +&usb3 { + status = "okay"; +}; + &wifi0 { status = "okay"; nvmem-cell-names = "pre-calibration"; diff --git a/target/linux/ipq40xx/image/generic.mk b/target/linux/ipq40xx/image/generic.mk index 7af777248d4904..444035ffe5104e 100644 --- a/target/linux/ipq40xx/image/generic.mk +++ b/target/linux/ipq40xx/image/generic.mk @@ -454,8 +454,7 @@ define Device/engenius_eap1300 IMAGE_SIZE := 25344k IMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | append-metadata endef -# Missing DSA Setup -#TARGET_DEVICES += engenius_eap1300 +TARGET_DEVICES += engenius_eap1300 define Device/engenius_eap2200 $(call Device/FitImage) diff --git a/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8068-mr52.dts b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8068-mr52.dts index 7512bfb74f1c2d..0d3230e6de9922 100644 --- a/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8068-mr52.dts +++ b/target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8068-mr52.dts @@ -46,13 +46,13 @@ gpios = <&qcom_pinmux 19 GPIO_ACTIVE_HIGH>; }; - lan2_green { - label = "green:lan2"; + lan1_green { + label = "green:lan1"; gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>; }; - lan1_green { - label = "green:lan1"; + lan2_green { + label = "green:lan2"; gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>; }; @@ -61,13 +61,13 @@ gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>; }; - lan2_orange { - label = "orange:lan2"; + lan1_orange { + label = "orange:lan1"; gpios = <&qcom_pinmux 60 GPIO_ACTIVE_HIGH>; }; - lan1_orange { - label = "orange:lan1"; + lan2_orange { + label = "orange:lan2"; gpios = <&qcom_pinmux 62 GPIO_ACTIVE_HIGH>; }; }; diff --git a/target/linux/mediatek/base-files/etc/uci-defaults/99_fwenv-store-ethaddr.sh b/target/linux/mediatek/base-files/etc/uci-defaults/99_fwenv-store-ethaddr.sh index 0afb434c97d748..e9cb4f921d9aed 100644 --- a/target/linux/mediatek/base-files/etc/uci-defaults/99_fwenv-store-ethaddr.sh +++ b/target/linux/mediatek/base-files/etc/uci-defaults/99_fwenv-store-ethaddr.sh @@ -11,7 +11,8 @@ unielec,u7623-02) ;; bananapi,bpi-r3|\ bananapi,bpi-r3-mini|\ -bananapi,bpi-4) +bananapi,bpi-r4|\ +bananapi,bpi-r4-poe) [ -z "$(fw_printenv -n ethaddr 2>/dev/null)" ] && fw_setenv ethaddr "$(cat /sys/class/net/eth0/address)" [ -z "$(fw_printenv -n eth1addr 2>/dev/null)" ] && diff --git a/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-poe.dts b/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-poe.dts new file mode 100644 index 00000000000000..efcf0ec35851cc --- /dev/null +++ b/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-poe.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2022 MediaTek Inc. + * Author: Sam.Shih + */ + +#include "mt7988a-bananapi-bpi-r4.dtsi" + +/ { + model = "Bananapi BPI-R4 2.5GE PoE"; + compatible = "bananapi,bpi-r4-poe", + "mediatek,mt7988a"; +}; + +&gmac1 { + phy-mode = "internal"; + phy-connection-type = "internal"; + phy = <&int_2p5g_phy>; + status = "okay"; +}; + +&int_2p5g_phy { + pinctrl-names = "i2p5gbe-led"; + pinctrl-0 = <&i2p5gbe_led0_pins>; +}; diff --git a/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts b/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts index d72051d187aa01..d2c223b4efaaa4 100644 --- a/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts +++ b/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts @@ -4,48 +4,13 @@ * Author: Sam.Shih */ -/dts-v1/; -#include "mt7988a.dtsi" -#include -#include -#include -#include +#include "mt7988a-bananapi-bpi-r4.dtsi" / { model = "Bananapi BPI-R4"; compatible = "bananapi,bpi-r4", "mediatek,mt7988a"; - aliases { - serial0 = &uart0; - led-boot = &led_green; - led-failsafe = &led_green; - led-running = &led_green; - led-upgrade = &led_green; - }; - - chosen { - stdout-path = &uart0; - bootargs = "console=ttyS0,115200n1 loglevel=8 pci=pcie_bus_perf ubi.block=0,fit root=/dev/fit0"; - rootdisk-spim-nand = <&ubi_rootfs>; - }; - - memory { - reg = <0x00 0x40000000 0x00 0x10000000>; - }; - - /* SFP1 cage (WAN) */ - sfp1: sfp1 { - compatible = "sff,sfp"; - i2c-bus = <&i2c_sfp1>; - los-gpios = <&pio 54 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&pio 82 GPIO_ACTIVE_LOW>; - tx-disable-gpios = <&pio 70 GPIO_ACTIVE_HIGH>; - tx-fault-gpios = <&pio 69 GPIO_ACTIVE_HIGH>; - rate-select0-gpios = <&pio 21 GPIO_ACTIVE_LOW>; - maximum-power-milliwatt = <3000>; - }; - /* SFP2 cage (LAN) */ sfp2: sfp2 { compatible = "sff,sfp"; @@ -57,42 +22,6 @@ rate-select0-gpios = <&pio 3 GPIO_ACTIVE_LOW>; maximum-power-milliwatt = <3000>; }; - - gpio-keys { - compatible = "gpio-keys"; - - wps { - label = "WPS"; - linux,code = ; - gpios = <&pio 14 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - led_green: led-green { - function = LED_FUNCTION_STATUS; - color = ; - gpios = <&pio 79 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - led_blue: led-blue { - function = LED_FUNCTION_WPS; - color = ; - gpios = <&pio 63 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; -}; - -ð { - status = "okay"; -}; - -&gmac0 { - status = "okay"; }; &gmac1 { @@ -102,306 +31,10 @@ status = "okay"; }; -&gmac2 { - sfp = <&sfp1>; - managed = "in-band-status"; - phy-mode = "usxgmii"; - status = "okay"; -}; - -&switch { - status = "okay"; -}; - -&gsw_phy0 { - pinctrl-names = "gbe-led"; - pinctrl-0 = <&gbe0_led0_pins>; -}; - -&gsw_port0 { - label = "wan"; -}; - -&gsw_phy0_led0 { - status = "okay"; - color = ; -}; - -&gsw_phy1 { - pinctrl-names = "gbe-led"; - pinctrl-0 = <&gbe1_led0_pins>; -}; - -&gsw_phy1_led0 { - status = "okay"; - color = ; -}; - -&gsw_phy2 { - pinctrl-names = "gbe-led"; - pinctrl-0 = <&gbe2_led0_pins>; -}; - -&gsw_phy2_led0 { - status = "okay"; - color = ; -}; - -&gsw_phy3 { - pinctrl-names = "gbe-led"; - pinctrl-0 = <&gbe3_led0_pins>; -}; - -&gsw_phy3_led0 { - status = "okay"; - color = ; -}; - -&cpu0 { - proc-supply = <&rt5190_buck3>; -}; - -&cpu1 { - proc-supply = <&rt5190_buck3>; -}; - -&cpu2 { - proc-supply = <&rt5190_buck3>; -}; - -&cpu3 { - proc-supply = <&rt5190_buck3>; -}; - -&cci { - proc-supply = <&rt5190_buck3>; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "okay"; - - rt5190a_64: rt5190a@64 { - compatible = "richtek,rt5190a"; - reg = <0x64>; - vin2-supply = <&rt5190_buck1>; - vin3-supply = <&rt5190_buck1>; - vin4-supply = <&rt5190_buck1>; - - regulators { - rt5190_buck1: buck1 { - regulator-name = "rt5190a-buck1"; - regulator-min-microvolt = <5090000>; - regulator-max-microvolt = <5090000>; - regulator-allowed-modes = - ; - regulator-boot-on; - regulator-always-on; - }; - buck2 { - regulator-name = "vcore"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1400000>; - regulator-boot-on; - regulator-always-on; - }; - rt5190_buck3: buck3 { - regulator-name = "vproc"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1400000>; - regulator-boot-on; - }; - buck4 { - regulator-name = "rt5190a-buck4"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - regulator-allowed-modes = - ; - regulator-boot-on; - regulator-always-on; - }; - ldo { - regulator-name = "rt5190a-ldo"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_1_pins>; - status = "okay"; - - pca9545: i2c-switch@70 { - reg = <0x70>; - compatible = "nxp,pca9545"; - reset-gpios = <&pio 5 GPIO_ACTIVE_LOW>; +&pca9545 { + i2c_sfp2: i2c@2 { #address-cells = <1>; #size-cells = <0>; - - i2c_rtc: i2c@0 { //eeprom,rtc,ngff - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - address-bits = <8>; - page-size = <8>; - size = <256>; - }; - - eeprom@57 { - compatible = "atmel,24c02"; - reg = <0x57>; - address-bits = <8>; - page-size = <8>; - size = <256>; - }; - - pcf8563: rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - status = "disabled"; - }; - }; - - i2c_sfp1: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - i2c_sfp2: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - i2c_wifi: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - }; -}; - -/* mPCIe SIM2 */ -&pcie0 { - pinctrl-names = "default"; - pinctrl-0 = <&pcie0_pins>; - status = "okay"; -}; - -/* mPCIe SIM3 */ -&pcie1 { - pinctrl-names = "default"; - pinctrl-0 = <&pcie1_pins>; - status = "okay"; -}; - -/* M.2 key-B SIM1 */ -&pcie2 { - pinctrl-names = "default"; - pinctrl-0 = <&pcie2_pins>; - status = "okay"; -}; - -/* M.2 key-M SSD */ -&pcie3 { - pinctrl-names = "default"; - pinctrl-0 = <&pcie3_pins>; - status = "okay"; -}; - -&ssusb1 { - status = "okay"; -}; - -&tphy { - status = "okay"; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_flash_pins>; - status = "okay"; - - spi_nand: spi_nand@0 { - compatible = "spi-nand"; - reg = <0>; - spi-max-frequency = <52000000>; - spi-tx-buswidth = <4>; - spi-rx-buswidth = <4>; - }; -}; - -&spi_nand { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "bl2"; - reg = <0x0 0x200000>; - read-only; - }; - - partition@200000 { - label = "ubi"; - reg = <0x200000 0x7e00000>; - compatible = "linux,ubi"; - - volumes { - ubi-volume-ubootenv { - volname = "ubootenv"; - nvmem-layout { - compatible = "u-boot,env-redundant-bool-layout"; - }; - }; - - ubi-volume-ubootenv2 { - volname = "ubootenv2"; - nvmem-layout { - compatible = "u-boot,env-redundant-bool-layout"; - }; - }; - - ubi_rootfs: ubi-volume-fit { - volname = "fit"; - }; - }; - }; + reg = <2>; }; }; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_2_lite_pins>; -}; - -&uart2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_3_pins>; -}; - -&watchdog { - status = "okay"; -}; - -&xphy { - status = "okay"; -}; diff --git a/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi b/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi new file mode 100644 index 00000000000000..c4c05fd419f254 --- /dev/null +++ b/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi @@ -0,0 +1,384 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2022 MediaTek Inc. + * Author: Sam.Shih + */ + +/dts-v1/; +#include "mt7988a.dtsi" +#include +#include +#include +#include + +/ { + model = "Bananapi BPI-R4"; + compatible = "bananapi,bpi-r4", + "mediatek,mt7988a"; + + aliases { + ethernet0 = &gmac0; + ethernet1 = &gmac1; + led-boot = &led_green; + led-failsafe = &led_green; + led-running = &led_green; + led-upgrade = &led_green; + serial0 = &uart0; + }; + + chosen { + stdout-path = &uart0; + bootargs = "console=ttyS0,115200n1 loglevel=8 pci=pcie_bus_perf ubi.block=0,fit root=/dev/fit0 rootwait"; + rootdisk-spim-nand = <&ubi_rootfs>; + }; + + memory { + reg = <0x00 0x40000000 0x00 0x10000000>; + }; + + /* SFP1 cage (WAN) */ + sfp1: sfp1 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp1>; + los-gpios = <&pio 54 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&pio 82 GPIO_ACTIVE_LOW>; + tx-disable-gpios = <&pio 70 GPIO_ACTIVE_HIGH>; + tx-fault-gpios = <&pio 69 GPIO_ACTIVE_HIGH>; + rate-select0-gpios = <&pio 21 GPIO_ACTIVE_LOW>; + maximum-power-milliwatt = <3000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + wps { + label = "WPS"; + linux,code = ; + gpios = <&pio 14 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led_green: led-green { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&pio 79 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + led_blue: led-blue { + function = LED_FUNCTION_WPS; + color = ; + gpios = <&pio 63 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; +}; + +ð { + status = "okay"; +}; + +&gmac0 { + status = "okay"; +}; + +&gmac2 { + sfp = <&sfp1>; + managed = "in-band-status"; + phy-mode = "usxgmii"; + status = "okay"; +}; + +&switch { + status = "okay"; +}; + +&gsw_phy0 { + pinctrl-names = "gbe-led"; + pinctrl-0 = <&gbe0_led0_pins>; +}; + +&gsw_port0 { + label = "wan"; +}; + +&gsw_phy0_led0 { + status = "okay"; + color = ; +}; + +&gsw_phy1 { + pinctrl-names = "gbe-led"; + pinctrl-0 = <&gbe1_led0_pins>; +}; + +&gsw_phy1_led0 { + status = "okay"; + color = ; +}; + +&gsw_phy2 { + pinctrl-names = "gbe-led"; + pinctrl-0 = <&gbe2_led0_pins>; +}; + +&gsw_phy2_led0 { + status = "okay"; + color = ; +}; + +&gsw_phy3 { + pinctrl-names = "gbe-led"; + pinctrl-0 = <&gbe3_led0_pins>; +}; + +&gsw_phy3_led0 { + status = "okay"; + color = ; +}; + +&cpu0 { + proc-supply = <&rt5190_buck3>; +}; + +&cpu1 { + proc-supply = <&rt5190_buck3>; +}; + +&cpu2 { + proc-supply = <&rt5190_buck3>; +}; + +&cpu3 { + proc-supply = <&rt5190_buck3>; +}; + +&cci { + proc-supply = <&rt5190_buck3>; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "okay"; + + rt5190a_64: rt5190a@64 { + compatible = "richtek,rt5190a"; + reg = <0x64>; + vin2-supply = <&rt5190_buck1>; + vin3-supply = <&rt5190_buck1>; + vin4-supply = <&rt5190_buck1>; + + regulators { + rt5190_buck1: buck1 { + regulator-name = "rt5190a-buck1"; + regulator-min-microvolt = <5090000>; + regulator-max-microvolt = <5090000>; + regulator-allowed-modes = + ; + regulator-boot-on; + regulator-always-on; + }; + buck2 { + regulator-name = "vcore"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1400000>; + regulator-boot-on; + regulator-always-on; + }; + rt5190_buck3: buck3 { + regulator-name = "vproc"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1400000>; + regulator-boot-on; + }; + buck4 { + regulator-name = "rt5190a-buck4"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-allowed-modes = + ; + regulator-boot-on; + regulator-always-on; + }; + ldo { + regulator-name = "rt5190a-ldo"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_1_pins>; + status = "okay"; + + pca9545: i2c-switch@70 { + reg = <0x70>; + compatible = "nxp,pca9545"; + reset-gpios = <&pio 5 GPIO_ACTIVE_LOW>; + #address-cells = <1>; + #size-cells = <0>; + + i2c_rtc: i2c@0 { //eeprom,rtc,ngff + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + address-bits = <8>; + page-size = <8>; + size = <256>; + }; + + eeprom@57 { + compatible = "atmel,24c02"; + reg = <0x57>; + address-bits = <8>; + page-size = <8>; + size = <256>; + }; + + pcf8563: rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + status = "disabled"; + }; + }; + + i2c_sfp1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + i2c_wifi: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; +}; + +/* mPCIe SIM2 */ +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_pins>; + status = "okay"; +}; + +/* mPCIe SIM3 */ +&pcie1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_pins>; + status = "okay"; +}; + +/* M.2 key-B SIM1 */ +&pcie2 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_pins>; + status = "okay"; +}; + +/* M.2 key-M SSD */ +&pcie3 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie3_pins>; + status = "okay"; +}; + +&ssusb1 { + status = "okay"; +}; + +&tphy { + status = "okay"; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_flash_pins>; + status = "okay"; + + spi_nand: spi_nand@0 { + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <52000000>; + spi-tx-buswidth = <4>; + spi-rx-buswidth = <4>; + }; +}; + +&spi_nand { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "bl2"; + reg = <0x0 0x200000>; + read-only; + }; + + partition@200000 { + label = "ubi"; + reg = <0x200000 0x7e00000>; + compatible = "linux,ubi"; + + volumes { + ubi-volume-ubootenv { + volname = "ubootenv"; + nvmem-layout { + compatible = "u-boot,env-redundant-bool-layout"; + }; + }; + + ubi-volume-ubootenv2 { + volname = "ubootenv2"; + nvmem-layout { + compatible = "u-boot,env-redundant-bool-layout"; + }; + }; + + ubi_rootfs: ubi-volume-fit { + volname = "fit"; + }; + }; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_2_lite_pins>; +}; + +&uart2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_3_pins>; +}; + +&watchdog { + status = "okay"; +}; + +&xphy { + status = "okay"; +}; diff --git a/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a.dtsi index caad6e5577e7f1..db2b85c1818dff 100644 --- a/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -159,7 +159,7 @@ pmu { compatible = "arm,cortex-a73-pmu"; interrupt-parent = <&gic>; - interrupt = ; + interrupts = ; }; psci { diff --git a/target/linux/mediatek/files-6.6/drivers/net/phy/mediatek-2p5ge.c b/target/linux/mediatek/files-6.6/drivers/net/phy/mediatek-2p5ge.c index e2e06d1ecac8cf..d1d01190ede2b2 100644 --- a/target/linux/mediatek/files-6.6/drivers/net/phy/mediatek-2p5ge.c +++ b/target/linux/mediatek/files-6.6/drivers/net/phy/mediatek-2p5ge.c @@ -137,6 +137,11 @@ static int mt7988_2p5ge_phy_config_init(struct phy_device *phydev) } /* Setup LED */ + + /* Set polarity of led0 to active-high for BPI-R4 */ + phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL, + MTK_PHY_LED0_POLARITY); + phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL, MTK_PHY_LED0_ON_LINK10 | MTK_PHY_LED0_ON_LINK100 | diff --git a/target/linux/mediatek/filogic/base-files/etc/board.d/01_leds b/target/linux/mediatek/filogic/base-files/etc/board.d/01_leds index 7f75de8b3b961c..b5a25546717acd 100644 --- a/target/linux/mediatek/filogic/base-files/etc/board.d/01_leds +++ b/target/linux/mediatek/filogic/base-files/etc/board.d/01_leds @@ -20,7 +20,8 @@ bananapi,bpi-r3-mini) ucidef_set_led_netdev "wlan2g" "WLAN2G" "blue:wlan-1" "phy0-ap0" ucidef_set_led_netdev "wlan5g" "WLAN5G" "blue:wlan-2" "phy1-ap0" ;; -bananapi,bpi-r4) +bananapi,bpi-r4|\ +bananapi,bpi-r4-poe) ucidef_set_led_netdev "wan" "wan" "mt7530-0:00:green:lan" "wan" "link tx rx" ucidef_set_led_netdev "lan1" "lan1" "mt7530-0:01:green:lan" "lan1" "link tx rx" ucidef_set_led_netdev "lan2" "lan2" "mt7530-0:02:green:lan" "lan2" "link tx rx" diff --git a/target/linux/mediatek/filogic/base-files/etc/board.d/02_network b/target/linux/mediatek/filogic/base-files/etc/board.d/02_network index c9fd8d96e69a1f..a161a864627923 100644 --- a/target/linux/mediatek/filogic/base-files/etc/board.d/02_network +++ b/target/linux/mediatek/filogic/base-files/etc/board.d/02_network @@ -41,7 +41,8 @@ mediatek_setup_interfaces() edgecore,eap111) ucidef_set_interfaces_lan_wan eth0 eth1 ;; - bananapi,bpi-r4) + bananapi,bpi-r4|\ + bananapi,bpi-r4-poe) ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 eth1" "wan eth2" ;; cmcc,rax3000m|\ diff --git a/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac b/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac index 62860390ebb2e6..0c5f66c02910c3 100644 --- a/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac +++ b/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac @@ -42,7 +42,8 @@ case "$board" in [ "$PHYNBR" = "0" ] && macaddr_add $addr 2 > /sys${DEVPATH}/macaddress [ "$PHYNBR" = "1" ] && macaddr_add $addr 3 > /sys${DEVPATH}/macaddress ;; - bananapi,bpi-r4) + bananapi,bpi-r4|\ + bananapi,bpi-r4-poe) addr=$(cat /sys/class/net/eth0/address) [ "$PHYNBR" = "0" ] && macaddr_add $addr 2 > /sys${DEVPATH}/macaddress [ "$PHYNBR" = "1" ] && macaddr_add $addr 3 > /sys${DEVPATH}/macaddress diff --git a/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh b/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh index ee0e8b62d752db..ff791a600a3442 100755 --- a/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh +++ b/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh @@ -83,6 +83,7 @@ platform_do_upgrade() { bananapi,bpi-r3|\ bananapi,bpi-r3-mini|\ bananapi,bpi-r4|\ + bananapi,bpi-r4-poe|\ jdcloud,re-cp-03|\ tplink,tl-xdr4288|\ tplink,tl-xdr6086|\ @@ -196,6 +197,7 @@ platform_check_image() { case "$board" in bananapi,bpi-r3|\ bananapi,bpi-r4|\ + bananapi,bpi-r4-poe|\ cmcc,rax3000m) [ "$magic" != "d00dfeed" ] && { echo "Invalid image type." @@ -223,7 +225,8 @@ platform_copy_config() { ;; bananapi,bpi-r3|\ bananapi,bpi-r3-mini|\ - bananapi,bpi-r4) + bananapi,bpi-r4|\ + bananapi,bpi-r4-poe) case "$(fitblk_get_bootdev)" in mmcblk*) emmc_copy_config diff --git a/target/linux/mediatek/image/filogic.mk b/target/linux/mediatek/image/filogic.mk index f99a73ac74c887..13426f4f3acace 100644 --- a/target/linux/mediatek/image/filogic.mk +++ b/target/linux/mediatek/image/filogic.mk @@ -318,11 +318,8 @@ endif endef TARGET_DEVICES += bananapi_bpi-r3-mini -define Device/bananapi_bpi-r4 +define Device/bananapi_bpi-r4-common DEVICE_VENDOR := Bananapi - DEVICE_MODEL := BPi-R4 - DEVICE_DTS := mt7988a-bananapi-bpi-r4 - DEVICE_DTS_CONFIG := config-mt7988a-bananapi-bpi-r4 DEVICE_DTS_DIR := $(DTS_DIR)/ DEVICE_DTS_LOADADDR := 0x45f00000 DEVICE_DTS_OVERLAY:= mt7988a-bananapi-bpi-r4-emmc mt7988a-bananapi-bpi-r4-rtc mt7988a-bananapi-bpi-r4-sd mt7988a-bananapi-bpi-r4-wifi-mt7996a @@ -337,19 +334,19 @@ define Device/bananapi_bpi-r4 sdcard.img.gz \ snand-preloader.bin snand-bl31-uboot.fip ARTIFACT/emmc-preloader.bin := mt7988-bl2 emmc-comb - ARTIFACT/emmc-bl31-uboot.fip := mt7988-bl31-uboot bananapi_bpi-r4-emmc + ARTIFACT/emmc-bl31-uboot.fip := mt7988-bl31-uboot $$(DEVICE_NAME)-emmc ARTIFACT/snand-preloader.bin := mt7988-bl2 spim-nand-ubi-comb - ARTIFACT/snand-bl31-uboot.fip := mt7988-bl31-uboot bananapi_bpi-r4-snand + ARTIFACT/snand-bl31-uboot.fip := mt7988-bl31-uboot $$(DEVICE_NAME)-snand ARTIFACT/sdcard.img.gz := mt798x-gpt sdmmc |\ pad-to 17k | mt7988-bl2 sdmmc-comb |\ - pad-to 6656k | mt7988-bl31-uboot bananapi_bpi-r4-sdmmc |\ + pad-to 6656k | mt7988-bl31-uboot $$(DEVICE_NAME)-sdmmc |\ $(if $(CONFIG_TARGET_ROOTFS_INITRAMFS),\ pad-to 12M | append-image-stage initramfs-recovery.itb | check-size 44m |\ ) \ pad-to 44M | mt7988-bl2 spim-nand-ubi-comb |\ - pad-to 45M | mt7988-bl31-uboot bananapi_bpi-r4-snand |\ + pad-to 45M | mt7988-bl31-uboot $$(DEVICE_NAME)-snand |\ pad-to 51M | mt7988-bl2 emmc-comb |\ - pad-to 52M | mt7988-bl31-uboot bananapi_bpi-r4-emmc |\ + pad-to 52M | mt7988-bl31-uboot $$(DEVICE_NAME)-emmc |\ pad-to 56M | mt798x-gpt emmc |\ $(if $(CONFIG_TARGET_ROOTFS_SQUASHFS),\ pad-to 64M | append-image squashfs-sysupgrade.itb | check-size |\ @@ -361,8 +358,24 @@ define Device/bananapi_bpi-r4 fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k IMAGE/sysupgrade.itb := append-kernel | fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-with-rootfs | pad-rootfs | append-metadata endef + +define Device/bananapi_bpi-r4 + DEVICE_MODEL := BPi-R4 + DEVICE_DTS := mt7988a-bananapi-bpi-r4 + DEVICE_DTS_CONFIG := config-mt7988a-bananapi-bpi-r4 + $(call Device/bananapi_bpi-r4-common) +endef TARGET_DEVICES += bananapi_bpi-r4 +define Device/bananapi_bpi-r4-poe + DEVICE_MODEL := BPi-R4 2.5GE + DEVICE_DTS := mt7988a-bananapi-bpi-r4-poe + DEVICE_DTS_CONFIG := config-mt7988a-bananapi-bpi-r4-poe + $(call Device/bananapi_bpi-r4-common) + DEVICE_PACKAGES += mt7988-2p5g-phy-firmware +endef +TARGET_DEVICES += bananapi_bpi-r4-poe + define Device/cetron_ct3003 DEVICE_VENDOR := Cetron DEVICE_MODEL := CT3003 diff --git a/target/linux/mediatek/patches-6.6/164-dts-mt7623-bpi-r2-rootdisk-for-fitblk.patch b/target/linux/mediatek/patches-6.6/164-dts-mt7623-bpi-r2-rootdisk-for-fitblk.patch index f1a182b04441f0..fac14b4d82c727 100644 --- a/target/linux/mediatek/patches-6.6/164-dts-mt7623-bpi-r2-rootdisk-for-fitblk.patch +++ b/target/linux/mediatek/patches-6.6/164-dts-mt7623-bpi-r2-rootdisk-for-fitblk.patch @@ -5,7 +5,7 @@ chosen { stdout-path = "serial2:115200n8"; - bootargs = "earlycon=uart8250,mmio32,0x11004000 console=ttyS2,115200n8 console=tty1"; -+ bootargs = "root=/dev/fit0 earlycon=uart8250,mmio32,0x11004000 console=ttyS2,115200n8 console=tty1"; ++ bootargs = "root=/dev/fit0 rootwait earlycon=uart8250,mmio32,0x11004000 console=ttyS2,115200n8 console=tty1"; + rootdisk-emmc = <&emmc_rootdisk>; + rootdisk-sd = <&sd_rootdisk>; }; diff --git a/target/linux/mediatek/patches-6.6/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch b/target/linux/mediatek/patches-6.6/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch index a3247f1779ac9f..917a458d308003 100644 --- a/target/linux/mediatek/patches-6.6/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch +++ b/target/linux/mediatek/patches-6.6/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch @@ -30,6 +30,15 @@ Signed-off-by: Felix Fietkau #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; +@@ -937,7 +943,7 @@ + }; + + hifsys: clock-controller@1af00000 { +- compatible = "mediatek,mt7622-hifsys"; ++ compatible = "mediatek,mt7622-hifsys", "syscon"; + reg = <0 0x1af00000 0 0x70>; + #clock-cells = <1>; + }; --- a/drivers/pci/controller/pcie-mediatek.c +++ b/drivers/pci/controller/pcie-mediatek.c @@ -20,6 +20,7 @@ diff --git a/target/linux/realtek/files-5.15/drivers/net/ethernet/rtl838x_eth.c b/target/linux/realtek/files-5.15/drivers/net/ethernet/rtl838x_eth.c index 54e592aeaafa59..71e7937336157c 100644 --- a/target/linux/realtek/files-5.15/drivers/net/ethernet/rtl838x_eth.c +++ b/target/linux/realtek/files-5.15/drivers/net/ethernet/rtl838x_eth.c @@ -1658,7 +1658,7 @@ static int rtl839x_mdio_read_paged(struct mii_bus *bus, int mii_id, u16 page, in int err; struct rtl838x_eth_priv *priv = bus->priv; - if (mii_id >= 48 && mii_id <= 49 && priv->id == 0x8393) + if (priv->phy_is_internal[mii_id]) return rtl839x_read_sds_phy(mii_id, regnum); if (regnum & (MII_ADDR_C45 | MII_ADDR_C22_MMD)) { @@ -1797,7 +1797,7 @@ static int rtl839x_mdio_write_paged(struct mii_bus *bus, int mii_id, u16 page, struct rtl838x_eth_priv *priv = bus->priv; int err; - if (mii_id >= 48 && mii_id <= 49 && priv->id == 0x8393) + if (priv->phy_is_internal[mii_id]) return rtl839x_write_sds_phy(mii_id, regnum, value); if (regnum & (MII_ADDR_C45 | MII_ADDR_C22_MMD)) { diff --git a/target/linux/realtek/files-5.15/drivers/net/phy/rtl83xx-phy.c b/target/linux/realtek/files-5.15/drivers/net/phy/rtl83xx-phy.c index 56e8a7f49d3128..490020989f6eae 100644 --- a/target/linux/realtek/files-5.15/drivers/net/phy/rtl83xx-phy.c +++ b/target/linux/realtek/files-5.15/drivers/net/phy/rtl83xx-phy.c @@ -46,6 +46,8 @@ extern struct mutex smi_lock; /* external RTL821X PHY uses register 0x1e to select media page */ #define RTL821XEXT_MEDIA_PAGE_SELECT 0x1e +#define RTL821X_CHIP_ID 0x6276 + #define RTL821X_MEDIA_PAGE_AUTO 0 #define RTL821X_MEDIA_PAGE_COPPER 1 #define RTL821X_MEDIA_PAGE_FIBRE 3 @@ -834,7 +836,7 @@ static int rtl8380_configure_ext_rtl8218b(struct phy_device *phydev) /* Read internal PHY ID */ phy_write_paged(phydev, 31, 27, 0x0002); val = phy_read_paged(phydev, 31, 28); - if (val != 0x6276) { + if (val != RTL821X_CHIP_ID) { phydev_err(phydev, "Expected external RTL8218B, found PHY-ID %x\n", val); return -1; } @@ -1331,7 +1333,7 @@ static int rtl8380_configure_rtl8214fc(struct phy_device *phydev) phy_write_paged(phydev, 0, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER); phy_write_paged(phydev, 0x1f, 0x1b, 0x0002); val = phy_read_paged(phydev, 0x1f, 0x1c); - if (val != 0x6276) { + if (val != RTL821X_CHIP_ID) { phydev_err(phydev, "Expected external RTL8214FC, found PHY-ID %x\n", val); return -1; } diff --git a/target/linux/rockchip/Makefile b/target/linux/rockchip/Makefile index f0e2de612efad1..f49b1d78bdb7d0 100644 --- a/target/linux/rockchip/Makefile +++ b/target/linux/rockchip/Makefile @@ -8,6 +8,7 @@ FEATURES:=ext4 audio usb usbgadget display gpio fpu pci pcie rootfs-part boot-pa SUBTARGETS:=armv8 KERNEL_PATCHVER:=6.1 +KERNEL_TESTING_PATCHVER:=6.6 define Target/Description Build firmware image for Rockchip SoC devices. diff --git a/target/linux/rockchip/armv8/config-6.6 b/target/linux/rockchip/armv8/config-6.6 new file mode 100644 index 00000000000000..fb57fc62604f1d --- /dev/null +++ b/target/linux/rockchip/armv8/config-6.6 @@ -0,0 +1,729 @@ +CONFIG_64BIT=y +CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y +CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y +CONFIG_ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG=y +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_ARCH_FORCE_MAX_ORDER=10 +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_KEEP_MEMBLOCK=y +CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y +CONFIG_ARCH_MMAP_RND_BITS=18 +CONFIG_ARCH_MMAP_RND_BITS_MAX=33 +CONFIG_ARCH_MMAP_RND_BITS_MIN=18 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 +CONFIG_ARCH_PROC_KCORE_TEXT=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_ARCH_SELECTS_KEXEC_FILE=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_STACKWALK=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_WANTS_NO_INSTR=y +CONFIG_ARCH_WANTS_THP_SWAP=y +CONFIG_ARC_EMAC_CORE=y +CONFIG_ARM64=y +CONFIG_ARM64_4K_PAGES=y +CONFIG_ARM64_CNP=y +CONFIG_ARM64_EPAN=y +CONFIG_ARM64_ERRATUM_2051678=y +CONFIG_ARM64_ERRATUM_2054223=y +CONFIG_ARM64_ERRATUM_2067961=y +CONFIG_ARM64_ERRATUM_2077057=y +CONFIG_ARM64_ERRATUM_2658417=y +CONFIG_ARM64_ERRATUM_819472=y +CONFIG_ARM64_ERRATUM_824069=y +CONFIG_ARM64_ERRATUM_826319=y +CONFIG_ARM64_ERRATUM_827319=y +CONFIG_ARM64_ERRATUM_832075=y +CONFIG_ARM64_ERRATUM_843419=y +CONFIG_ARM64_ERRATUM_858921=y +CONFIG_ARM64_HW_AFDBM=y +CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y +CONFIG_ARM64_PAGE_SHIFT=12 +CONFIG_ARM64_PAN=y +CONFIG_ARM64_PA_BITS=48 +CONFIG_ARM64_PA_BITS_48=y +CONFIG_ARM64_PTR_AUTH=y +CONFIG_ARM64_PTR_AUTH_KERNEL=y +CONFIG_ARM64_RAS_EXTN=y +CONFIG_ARM64_SME=y +CONFIG_ARM64_SVE=y +CONFIG_ARM64_TAGGED_ADDR_ABI=y +CONFIG_ARM64_VA_BITS=48 +# CONFIG_ARM64_VA_BITS_39 is not set +CONFIG_ARM64_VA_BITS_48=y +CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y +CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE=y +CONFIG_ARM_AMBA=y +CONFIG_ARM_ARCH_TIMER=y +CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y +CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y +CONFIG_ARM_GIC=y +CONFIG_ARM_GIC_V2M=y +CONFIG_ARM_GIC_V3=y +CONFIG_ARM_GIC_V3_ITS=y +CONFIG_ARM_GIC_V3_ITS_PCI=y +CONFIG_ARM_MHU=y +CONFIG_ARM_MHU_V2=y +CONFIG_ARM_PSCI_CPUIDLE=y +CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y +CONFIG_ARM_PSCI_FW=y +# CONFIG_ARM_RK3399_DMC_DEVFREQ is not set +CONFIG_ARM_SCMI_CPUFREQ=y +CONFIG_ARM_SCMI_HAVE_SHMEM=y +CONFIG_ARM_SCMI_HAVE_TRANSPORT=y +CONFIG_ARM_SCMI_POWER_CONTROL=y +CONFIG_ARM_SCMI_POWER_DOMAIN=y +CONFIG_ARM_SCMI_PROTOCOL=y +# CONFIG_ARM_SCMI_RAW_MODE_SUPPORT is not set +CONFIG_ARM_SCMI_TRANSPORT_MAILBOX=y +CONFIG_ARM_SCMI_TRANSPORT_SMC=y +CONFIG_ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE=y +CONFIG_ARM_SCPI_CPUFREQ=y +CONFIG_ARM_SCPI_POWER_DOMAIN=y +CONFIG_ARM_SCPI_PROTOCOL=y +CONFIG_ARM_SMMU=y +CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y +# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set +CONFIG_ARM_SMMU_V3=y +# CONFIG_ARM_SMMU_V3_SVA is not set +CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_GPIO=y +CONFIG_BACKLIGHT_PWM=y +CONFIG_BLK_DEV_BSG=y +CONFIG_BLK_DEV_BSGLIB=y +CONFIG_BLK_DEV_BSG_COMMON=y +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_BLK_DEV_INTEGRITY=y +CONFIG_BLK_DEV_INTEGRITY_T10=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_NVME=y +CONFIG_BLK_DEV_PCIESSD_MTIP32XX=y +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_MQ_PCI=y +CONFIG_BLK_PM=y +CONFIG_BRCMSTB_GISB_ARB=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_BUFFER_HEAD=y +CONFIG_BUILTIN_RETURN_ADDRESS_STRIPS_PAC=y +CONFIG_CC_HAVE_SHADOW_CALL_STACK=y +CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y +CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" +CONFIG_CC_NO_ARRAY_BOUNDS=y +CONFIG_CHARGER_GPIO=y +# CONFIG_CHARGER_RK817 is not set +CONFIG_CLKSRC_MMIO=y +CONFIG_CLK_PX30=y +CONFIG_CLK_RK3308=y +CONFIG_CLK_RK3328=y +CONFIG_CLK_RK3368=y +CONFIG_CLK_RK3399=y +CONFIG_CLK_RK3568=y +CONFIG_CLK_RK3588=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_CMA=y +CONFIG_CMA_ALIGNMENT=8 +CONFIG_CMA_AREAS=7 +# CONFIG_CMA_DEBUG is not set +# CONFIG_CMA_DEBUGFS is not set +CONFIG_CMA_SIZE_MBYTES=16 +# CONFIG_CMA_SIZE_SEL_MAX is not set +CONFIG_CMA_SIZE_SEL_MBYTES=y +# CONFIG_CMA_SIZE_SEL_MIN is not set +# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set +# CONFIG_CMA_SYSFS is not set +CONFIG_COMMON_CLK=y +CONFIG_COMMON_CLK_RK808=y +CONFIG_COMMON_CLK_ROCKCHIP=y +CONFIG_COMMON_CLK_SCMI=y +CONFIG_COMMON_CLK_SCPI=y +CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_CONFIGFS_FS=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_CONTEXT_TRACKING=y +CONFIG_CONTEXT_TRACKING_IDLE=y +CONFIG_CONTIG_ALLOC=y +CONFIG_CPUFREQ_DT=y +CONFIG_CPUFREQ_DT_PLATDEV=y +CONFIG_CPU_FREQ=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y +CONFIG_CPU_FREQ_GOV_ATTR_SET=y +# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set +# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y +# CONFIG_CPU_FREQ_GOV_USERSPACE is not set +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_MENU=y +CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y +CONFIG_CPU_ISOLATION=y +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_CPU_PM=y +CONFIG_CPU_RMAP=y +CONFIG_CPU_THERMAL=y +CONFIG_CRASH_CORE=y +CONFIG_CRASH_DUMP=y +CONFIG_CRC16=y +# CONFIG_CRC32_SARWATE is not set +CONFIG_CRC32_SLICEBY8=y +CONFIG_CRC64=y +CONFIG_CRC64_ROCKSOFT=y +CONFIG_CRC_T10DIF=y +CONFIG_CROSS_MEMORY_ATTACH=y +CONFIG_CRYPTO_AES_ARM64=y +CONFIG_CRYPTO_AES_ARM64_CE=y +CONFIG_CRYPTO_AES_ARM64_CE_BLK=y +CONFIG_CRYPTO_AES_ARM64_CE_CCM=y +CONFIG_CRYPTO_CRC32=y +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_CRC64_ROCKSOFT=y +CONFIG_CRYPTO_CRCT10DIF=y +CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y +CONFIG_CRYPTO_CRYPTD=y +# CONFIG_CRYPTO_DEV_ROCKCHIP is not set +CONFIG_CRYPTO_GHASH_ARM64_CE=y +CONFIG_CRYPTO_HW=y +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_LIB_GF128MUL=y +CONFIG_CRYPTO_LIB_SHA1=y +CONFIG_CRYPTO_LIB_SHA256=y +CONFIG_CRYPTO_LIB_UTILS=y +CONFIG_CRYPTO_POLYVAL=y +CONFIG_CRYPTO_POLYVAL_ARM64_CE=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SM3=y +CONFIG_CRYPTO_SM3_NEON=y +CONFIG_CRYPTO_SM4=y +CONFIG_CRYPTO_SM4_ARM64_CE_BLK=y +CONFIG_CRYPTO_SM4_ARM64_NEON_BLK=y +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_INFO=y +# CONFIG_DEVFREQ_GOV_PASSIVE is not set +CONFIG_DEVFREQ_GOV_PERFORMANCE=y +CONFIG_DEVFREQ_GOV_POWERSAVE=y +CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y +CONFIG_DEVFREQ_GOV_USERSPACE=y +# CONFIG_DEVFREQ_THERMAL is not set +CONFIG_DEVMEM=y +# CONFIG_DEVPORT is not set +CONFIG_DMADEVICES=y +CONFIG_DMA_BOUNCE_UNALIGNED_KMALLOC=y +CONFIG_DMA_CMA=y +CONFIG_DMA_DIRECT_REMAP=y +CONFIG_DMA_ENGINE=y +CONFIG_DMA_OF=y +CONFIG_DMA_OPS=y +CONFIG_DMA_SHARED_BUFFER=y +CONFIG_DNOTIFY=y +CONFIG_DTC=y +CONFIG_DT_IDLE_GENPD=y +CONFIG_DT_IDLE_STATES=y +CONFIG_DUMMY_CONSOLE=y +CONFIG_DWMAC_DWC_QOS_ETH=y +CONFIG_DWMAC_GENERIC=y +CONFIG_DWMAC_ROCKCHIP=y +CONFIG_DW_WATCHDOG=y +CONFIG_EDAC_SUPPORT=y +CONFIG_EEPROM_AT24=y +CONFIG_EMAC_ROCKCHIP=y +CONFIG_ENERGY_MODEL=y +CONFIG_EXCLUSIVE_SYSTEM_RAM=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXTCON=y +CONFIG_F2FS_FS=y +CONFIG_FANOTIFY=y +CONFIG_FHANDLE=y +CONFIG_FIXED_PHY=y +CONFIG_FIX_EARLYCON_MEM=y +# CONFIG_FORTIFY_SOURCE is not set +CONFIG_FRAME_POINTER=y +CONFIG_FS_IOMAP=y +CONFIG_FS_MBCACHE=y +CONFIG_FS_POSIX_ACL=y +CONFIG_FUNCTION_ALIGNMENT=4 +CONFIG_FUNCTION_ALIGNMENT_4B=y +CONFIG_FWNODE_MDIO=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_FW_LOADER_SYSFS=y +CONFIG_GCC10_NO_ARRAY_BOUNDS=y +CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND=y +CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_ARCH_TOPOLOGY=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_CPU_VULNERABILITIES=y +CONFIG_GENERIC_CSUM=y +CONFIG_GENERIC_EARLY_IOREMAP=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IOREMAP=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_MIGRATION=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_PINCONF=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GPIOLIB_IRQCHIP=y +CONFIG_GPIO_CDEV=y +CONFIG_GPIO_DWAPB=y +CONFIG_GPIO_GENERIC=y +CONFIG_GPIO_GENERIC_PLATFORM=y +CONFIG_GPIO_ROCKCHIP=y +CONFIG_GPIO_SYSCON=y +CONFIG_GRO_CELLS=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HOTPLUG_CORE_SYNC=y +CONFIG_HOTPLUG_CORE_SYNC_DEAD=y +CONFIG_HOTPLUG_CPU=y +CONFIG_HOTPLUG_PCI=y +# CONFIG_HOTPLUG_PCI_CPCI is not set +# CONFIG_HOTPLUG_PCI_PCIE is not set +# CONFIG_HOTPLUG_PCI_SHPC is not set +CONFIG_HUGETLBFS=y +CONFIG_HUGETLB_PAGE=y +CONFIG_HWMON=y +CONFIG_HWSPINLOCK=y +CONFIG_HW_CONSOLE=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_ROCKCHIP=y +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_RK3X=y +CONFIG_IIO=y +# CONFIG_IIO_SCMI is not set +CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 +CONFIG_INDIRECT_PIO=y +CONFIG_INPUT=y +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_FF_MEMLESS=y +CONFIG_INPUT_KEYBOARD=y +CONFIG_INPUT_LEDS=y +CONFIG_INPUT_MATRIXKMAP=y +CONFIG_INPUT_RK805_PWRKEY=y +# CONFIG_IOMMUFD is not set +CONFIG_IOMMU_API=y +# CONFIG_IOMMU_DEBUGFS is not set +# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set +# CONFIG_IOMMU_DEFAULT_DMA_STRICT is not set +CONFIG_IOMMU_DEFAULT_PASSTHROUGH=y +CONFIG_IOMMU_DMA=y +CONFIG_IOMMU_IOVA=y +CONFIG_IOMMU_IO_PGTABLE=y +# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set +# CONFIG_IOMMU_IO_PGTABLE_DART is not set +CONFIG_IOMMU_IO_PGTABLE_LPAE=y +# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set +CONFIG_IOMMU_SUPPORT=y +# CONFIG_IO_STRICT_DEVMEM is not set +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_MSI_IOMMU=y +CONFIG_IRQ_TIME_ACCOUNTING=y +CONFIG_IRQ_WORK=y +CONFIG_JBD2=y +CONFIG_JFFS2_ZLIB=y +CONFIG_JUMP_LABEL=y +CONFIG_KALLSYMS=y +CONFIG_KCMP=y +CONFIG_KEXEC_CORE=y +CONFIG_KEXEC_FILE=y +CONFIG_KSM=y +# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_PWM=y +CONFIG_LEDS_SYSCON=y +CONFIG_LEDS_TRIGGER_CPU=y +CONFIG_LEDS_TRIGGER_PANIC=y +CONFIG_LIBCRC32C=y +CONFIG_LIBFDT=y +CONFIG_LOCALVERSION_AUTO=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_LOG_BUF_SHIFT=19 +CONFIG_MAGIC_SYSRQ=y +CONFIG_MAGIC_SYSRQ_SERIAL=y +CONFIG_MAILBOX=y +# CONFIG_MAILBOX_TEST is not set +CONFIG_MDIO_BUS=y +CONFIG_MDIO_BUS_MUX=y +CONFIG_MDIO_BUS_MUX_GPIO=y +CONFIG_MDIO_BUS_MUX_MMIOREG=y +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_DEVRES=y +CONFIG_MEDIATEK_GE_PHY=y +# CONFIG_MEDIATEK_GE_SOC_PHY is not set +CONFIG_MEMORY_ISOLATION=y +CONFIG_MFD_CORE=y +# CONFIG_MFD_KHADAS_MCU is not set +CONFIG_MFD_RK8XX=y +CONFIG_MFD_RK8XX_I2C=y +CONFIG_MFD_RK8XX_SPI=y +CONFIG_MFD_SYSCON=y +CONFIG_MIGRATION=y +CONFIG_MMC=y +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_MINORS=32 +CONFIG_MMC_CQHCI=y +CONFIG_MMC_DW=y +# CONFIG_MMC_DW_BLUEFIELD is not set +# CONFIG_MMC_DW_EXYNOS is not set +# CONFIG_MMC_DW_HI3798CV200 is not set +# CONFIG_MMC_DW_K3 is not set +# CONFIG_MMC_DW_PCI is not set +CONFIG_MMC_DW_PLTFM=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_OF_ARASAN=y +CONFIG_MMC_SDHCI_OF_DWCMSHC=y +# CONFIG_MMC_SDHCI_PCI is not set +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMU_LAZY_TLB_REFCOUNT=y +CONFIG_MODULES_USE_ELF_RELA=y +CONFIG_MOTORCOMM_PHY=y +CONFIG_MQ_IOSCHED_DEADLINE=y +# CONFIG_MTD_CFI is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y +CONFIG_MTD_SPLIT_FIRMWARE=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_SG_DMA_FLAGS=y +CONFIG_NEED_SG_DMA_LENGTH=y +CONFIG_NET_DEVLINK=y +CONFIG_NET_DSA=y +CONFIG_NET_DSA_MT7530=y +CONFIG_NET_DSA_MT7530_MDIO=y +CONFIG_NET_DSA_MT7530_MMIO=y +CONFIG_NET_DSA_TAG_MTK=y +CONFIG_NET_EGRESS=y +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NET_INGRESS=y +CONFIG_NET_PTP_CLASSIFY=y +CONFIG_NET_SELFTESTS=y +CONFIG_NET_SWITCHDEV=y +CONFIG_NET_XGRESS=y +CONFIG_NLS=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NOP_USB_XCEIV=y +CONFIG_NO_HZ_COMMON=y +CONFIG_NO_HZ_IDLE=y +CONFIG_NR_CPUS=256 +CONFIG_NVMEM=y +CONFIG_NVMEM_LAYOUTS=y +CONFIG_NVMEM_ROCKCHIP_EFUSE=y +# CONFIG_NVMEM_ROCKCHIP_OTP is not set +CONFIG_NVMEM_SYSFS=y +CONFIG_NVME_CORE=y +# CONFIG_NVME_HWMON is not set +# CONFIG_NVME_MULTIPATH is not set +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_DYNAMIC=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IOMMU=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_MDIO=y +CONFIG_OF_OVERLAY=y +CONFIG_OF_RESOLVE=y +# CONFIG_OVERLAY_FS_XINO_AUTO is not set +CONFIG_PADATA=y +CONFIG_PAGE_POOL=y +CONFIG_PAGE_SIZE_LESS_THAN_256KB=y +CONFIG_PAGE_SIZE_LESS_THAN_64KB=y +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 +CONFIG_PANIC_TIMEOUT=0 +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_PARTITION_PERCPU=y +CONFIG_PCI=y +CONFIG_PCIEAER=y +CONFIG_PCIEASPM=y +CONFIG_PCIEASPM_DEFAULT=y +# CONFIG_PCIEASPM_PERFORMANCE is not set +# CONFIG_PCIEASPM_POWERSAVE is not set +# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set +CONFIG_PCIEPORTBUS=y +CONFIG_PCIE_DW=y +CONFIG_PCIE_DW_HOST=y +CONFIG_PCIE_PME=y +CONFIG_PCIE_ROCKCHIP=y +CONFIG_PCIE_ROCKCHIP_DW_HOST=y +CONFIG_PCIE_ROCKCHIP_HOST=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_DOMAINS_GENERIC=y +CONFIG_PCI_MSI=y +CONFIG_PCI_STUB=y +CONFIG_PCS_MTK_LYNXI=y +CONFIG_PCS_XPCS=y +CONFIG_PER_VMA_LOCK=y +CONFIG_PGTABLE_LEVELS=4 +CONFIG_PHYLIB=y +CONFIG_PHYLIB_LEDS=y +CONFIG_PHYLINK=y +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_PHY_ROCKCHIP_DP=y +# CONFIG_PHY_ROCKCHIP_DPHY_RX0 is not set +CONFIG_PHY_ROCKCHIP_EMMC=y +# CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY is not set +# CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY is not set +# CONFIG_PHY_ROCKCHIP_INNO_HDMI is not set +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=y +CONFIG_PHY_ROCKCHIP_PCIE=y +CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y +CONFIG_PHY_ROCKCHIP_TYPEC=y +CONFIG_PHY_ROCKCHIP_USB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_RK805=y +CONFIG_PINCTRL_ROCKCHIP=y +# CONFIG_PINCTRL_SINGLE is not set +CONFIG_PL330_DMA=y +CONFIG_PLATFORM_MHU=y +CONFIG_PM=y +CONFIG_PM_CLK=y +CONFIG_PM_DEVFREQ=y +# CONFIG_PM_DEVFREQ_EVENT is not set +CONFIG_PM_GENERIC_DOMAINS=y +CONFIG_PM_GENERIC_DOMAINS_OF=y +CONFIG_PM_OPP=y +CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y +CONFIG_POWER_RESET=y +CONFIG_POWER_SUPPLY=y +CONFIG_POWER_SUPPLY_HWMON=y +CONFIG_PPS=y +CONFIG_PREEMPT=y +CONFIG_PREEMPTION=y +CONFIG_PREEMPT_BUILD=y +CONFIG_PREEMPT_COUNT=y +# CONFIG_PREEMPT_NONE is not set +CONFIG_PREEMPT_RCU=y +CONFIG_PRINTK_TIME=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_PROC_VMCORE=y +CONFIG_PTP_1588_CLOCK=y +CONFIG_PTP_1588_CLOCK_OPTIONAL=y +CONFIG_PWM=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_PWM_SYSFS=y +# CONFIG_QFMT_V2 is not set +CONFIG_QUEUED_RWLOCKS=y +CONFIG_QUEUED_SPINLOCKS=y +CONFIG_QUOTA=y +CONFIG_QUOTACTL=y +CONFIG_RAID_ATTRS=y +CONFIG_RANDSTRUCT_NONE=y +CONFIG_RAS=y +CONFIG_RATIONAL=y +# CONFIG_RAVE_SP_CORE is not set +CONFIG_RCU_TRACE=y +CONFIG_REALTEK_PHY=y +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_IRQ=y +CONFIG_REGMAP_MMIO=y +CONFIG_REGMAP_SPI=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_ARM_SCMI=y +CONFIG_REGULATOR_FAN53555=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_GPIO=y +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_RK808=y +CONFIG_RELOCATABLE=y +CONFIG_RESET_CONTROLLER=y +CONFIG_RESET_SCMI=y +CONFIG_RFS_ACCEL=y +CONFIG_ROCKCHIP_GRF=y +CONFIG_ROCKCHIP_IODOMAIN=y +CONFIG_ROCKCHIP_IOMMU=y +CONFIG_ROCKCHIP_MBOX=y +CONFIG_ROCKCHIP_PHY=y +CONFIG_ROCKCHIP_PM_DOMAINS=y +# CONFIG_ROCKCHIP_SARADC is not set +CONFIG_ROCKCHIP_THERMAL=y +CONFIG_ROCKCHIP_TIMER=y +CONFIG_RODATA_FULL_DEFAULT_ENABLED=y +CONFIG_RPS=y +CONFIG_RSEQ=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_HYM8563=y +CONFIG_RTC_DRV_RK808=y +CONFIG_RTC_I2C_AND_SPI=y +CONFIG_RTC_NVMEM=y +# CONFIG_RUNTIME_TESTING_MENU is not set +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_SCHED_MC=y +CONFIG_SCSI=y +CONFIG_SCSI_COMMON=y +# CONFIG_SCSI_LOWLEVEL is not set +# CONFIG_SCSI_PROC_FS is not set +CONFIG_SCSI_SAS_ATTRS=y +CONFIG_SCSI_SAS_HOST_SMP=y +CONFIG_SCSI_SAS_LIBSAS=y +# CONFIG_SECURITY_DMESG_RESTRICT is not set +CONFIG_SENSORS_ARM_SCMI=y +CONFIG_SENSORS_ARM_SCPI=y +CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y +CONFIG_SERIAL_8250_DW=y +CONFIG_SERIAL_8250_DWLIB=y +CONFIG_SERIAL_8250_EXAR=y +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_FSL=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_PCILIB=y +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIAL_8250_SHARE_IRQ=y +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +CONFIG_SERIAL_DEV_BUS=y +CONFIG_SERIAL_DEV_CTRL_TTYPORT=y +CONFIG_SERIAL_MCTRL_GPIO=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SERIO=y +CONFIG_SERIO_AMBAKMI=y +CONFIG_SERIO_LIBPS2=y +CONFIG_SG_POOL=y +CONFIG_SMP=y +CONFIG_SOCK_RX_QUEUE_MAPPING=y +CONFIG_SOFTIRQ_ON_OWN_STACK=y +CONFIG_SPARSEMEM=y +CONFIG_SPARSEMEM_EXTREME=y +CONFIG_SPARSEMEM_VMEMMAP=y +CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y +CONFIG_SPARSE_IRQ=y +CONFIG_SPI=y +CONFIG_SPI_BITBANG=y +CONFIG_SPI_DYNAMIC=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y +CONFIG_SPI_ROCKCHIP=y +CONFIG_SPI_ROCKCHIP_SFC=y +CONFIG_SPI_SPIDEV=y +CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y +# CONFIG_SQUASHFS_EMBEDDED is not set +CONFIG_SQUASHFS_FILE_CACHE=y +# CONFIG_SQUASHFS_FILE_DIRECT is not set +CONFIG_SRAM=y +CONFIG_STACKPROTECTOR=y +CONFIG_STACKPROTECTOR_PER_TASK=y +CONFIG_STACKPROTECTOR_STRONG=y +CONFIG_STACKTRACE=y +CONFIG_STMMAC_ETH=y +CONFIG_STMMAC_PLATFORM=y +CONFIG_STRICT_DEVMEM=y +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_SWAP is not set +CONFIG_SWIOTLB=y +CONFIG_SWPHY=y +CONFIG_SYNC_FILE=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +CONFIG_SYSFS_SYSCALL=y +# CONFIG_TEXTSEARCH is not set +CONFIG_THERMAL=y +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y +CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 +CONFIG_THERMAL_EMULATION=y +CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y +CONFIG_THERMAL_GOV_STEP_WISE=y +CONFIG_THERMAL_HWMON=y +CONFIG_THERMAL_OF=y +CONFIG_THREAD_INFO_IN_TASK=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_TRACE_CLOCK=y +CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y +CONFIG_TRANSPARENT_HUGEPAGE=y +CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y +# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set +CONFIG_TRANS_TABLE=y +CONFIG_TREE_RCU=y +CONFIG_TREE_SRCU=y +CONFIG_TYPEC=y +# CONFIG_TYPEC_ANX7411 is not set +CONFIG_TYPEC_FUSB302=y +# CONFIG_TYPEC_HD3SS3220 is not set +# CONFIG_TYPEC_MUX_FSA4480 is not set +# CONFIG_TYPEC_MUX_GPIO_SBU is not set +# CONFIG_TYPEC_MUX_NB7VPQ904M is not set +# CONFIG_TYPEC_MUX_PI3USB30532 is not set +# CONFIG_TYPEC_RT1719 is not set +# CONFIG_TYPEC_STUSB160X is not set +# CONFIG_TYPEC_TCPCI is not set +CONFIG_TYPEC_TCPM=y +# CONFIG_TYPEC_TPS6598X is not set +# CONFIG_TYPEC_WUSB3801 is not set +# CONFIG_UCLAMP_TASK is not set +# CONFIG_UEVENT_HELPER is not set +CONFIG_UNINLINE_SPIN_UNLOCK=y +CONFIG_UNMAP_KERNEL_AT_EL0=y +CONFIG_USB=y +CONFIG_USB_COMMON=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_HOST=y +CONFIG_USB_DWC3_OF_SIMPLE=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_HCD_PLATFORM=y +# CONFIG_USB_EHCI_ROOT_HUB_TT is not set +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_HCD_PLATFORM=y +CONFIG_USB_PHY=y +CONFIG_USB_ROLE_SWITCH=y +CONFIG_USB_STORAGE=y +CONFIG_USB_SUPPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_ULPI_BUS=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_PLATFORM=y +# CONFIG_VIRTIO_MENU is not set +CONFIG_VMAP_STACK=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_WATCHDOG_CORE=y +CONFIG_XARRAY_MULTI=y +CONFIG_XPS=y +CONFIG_XXHASH=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_ARMTHUMB=y +CONFIG_XZ_DEC_BCJ=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZONE_DMA32=y diff --git a/target/linux/rockchip/patches-6.6/023-v6.8-arm64-dts-rockchip-Add-ethernet0-alias-to-the-dts-for-RK3566-boards.patch b/target/linux/rockchip/patches-6.6/023-v6.8-arm64-dts-rockchip-Add-ethernet0-alias-to-the-dts-for-RK3566-boards.patch new file mode 100644 index 00000000000000..fb5015cf6e0fe4 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/023-v6.8-arm64-dts-rockchip-Add-ethernet0-alias-to-the-dts-for-RK3566-boards.patch @@ -0,0 +1,28 @@ +From 36d9b3ae708e865cdab95692db5a24c5d975383d Mon Sep 17 00:00:00 2001 +From: Dragan Simic +Date: Tue, 12 Dec 2023 09:01:39 +0100 +Subject: [PATCH] arm64: dts: rockchip: Add ethernet0 alias to the dts for + RK3566 boards + +Add ethernet0 alias to the board dts files for a few supported RK3566 boards +that had it missing. Also, remove the ethernet0 alias from one RK3566 SoM +dtsi file, which doesn't enable the GMAC, and add the ethernet0 alias back to +the dependent board dts files, which actually enable the GMAC. + +Signed-off-by: Dragan Simic +Link: https://lore.kernel.org/r/d2a272e0ae0fff0adfab8bb0238243b11d348799.1702368023.git.dsimic@manjaro.org +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts | 1 + + 1 files changed, 1 insertions(+), 0 deletion(-) + +--- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts +@@ -14,6 +14,7 @@ + compatible = "radxa,cm3-io", "radxa,cm3", "rockchip,rk3566"; + + aliases { ++ ethernet0 = &gmac1; + mmc1 = &sdmmc0; + }; + diff --git a/target/linux/rockchip/patches-6.6/030-v6.9-arm64-dts-rockchip-adjust-vendor-on-Banana-Pi-R2-Pro.patch b/target/linux/rockchip/patches-6.6/030-v6.9-arm64-dts-rockchip-adjust-vendor-on-Banana-Pi-R2-Pro.patch new file mode 100644 index 00000000000000..9be609f6616aa0 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/030-v6.9-arm64-dts-rockchip-adjust-vendor-on-Banana-Pi-R2-Pro.patch @@ -0,0 +1,27 @@ +From 437644753208092f642b7669c69da606aa07dfb4 Mon Sep 17 00:00:00 2001 +From: Tim Lunn +Date: Wed, 14 Feb 2024 15:07:30 +1100 +Subject: [PATCH] arm64: dts: rockchip: adjust vendor on Banana Pi R2 Pro board + +Adjust compatible string to match the board vendor of Sinovoip + +Signed-off-by: Tim Lunn +Reviewed-by: Dragan Simic +Acked-by: Conor Dooley +Link: https://lore.kernel.org/r/20240214040731.3069111-4-tim@feathertop.org +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts +@@ -13,7 +13,7 @@ + + / { + model = "Bananapi-R2 Pro (RK3568) DDR4 Board"; +- compatible = "rockchip,rk3568-bpi-r2pro", "rockchip,rk3568"; ++ compatible = "sinovoip,rk3568-bpi-r2pro", "rockchip,rk3568"; + + aliases { + ethernet0 = &gmac0; diff --git a/target/linux/rockchip/patches-6.6/100-rockchip-use-system-LED-for-OpenWrt.patch b/target/linux/rockchip/patches-6.6/100-rockchip-use-system-LED-for-OpenWrt.patch new file mode 100644 index 00000000000000..683e5347f75b01 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/100-rockchip-use-system-LED-for-OpenWrt.patch @@ -0,0 +1,77 @@ +From 6731d2c9039fbe1ecf21915eab3acee0a999508a Mon Sep 17 00:00:00 2001 +From: David Bauer +Date: Fri, 10 Jul 2020 21:38:20 +0200 +Subject: [PATCH] rockchip: use system LED for OpenWrt + +Use the SYS LED on the casing for showing system status. + +This patch is kept separate from the NanoPi R2S support patch, as i plan +on submitting the device support upstream. + +Signed-off-by: David Bauer +--- + arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 9 ++++++++- + 1 file changed, 8 insertions(+), 1 deletion(-) + +--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts +@@ -6,6 +6,7 @@ + /dts-v1/; + + #include ++#include + #include + #include "rk3328.dtsi" + +@@ -16,6 +17,11 @@ + aliases { + ethernet1 = &rtl8153; + mmc0 = &sdmmc; ++ ++ led-boot = &sys_led; ++ led-failsafe = &sys_led; ++ led-running = &sys_led; ++ led-upgrade = &sys_led; + }; + + chosen { +@@ -48,19 +54,22 @@ + pinctrl-names = "default"; + + lan_led: led-0 { ++ color = ; ++ function = LED_FUNCTION_LAN; + gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; +- label = "nanopi-r2s:green:lan"; + }; + + sys_led: led-1 { ++ color = ; ++ function = LED_FUNCTION_STATUS; + gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; +- label = "nanopi-r2s:red:sys"; + default-state = "on"; + }; + + wan_led: led-2 { ++ color = ; ++ function = LED_FUNCTION_WAN; + gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>; +- label = "nanopi-r2s:green:wan"; + }; + }; + +--- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts +@@ -13,6 +13,11 @@ + aliases { + mmc0 = &sdmmc; + mmc1 = &emmc; ++ ++ led-boot = &power_led; ++ led-failsafe = &power_led; ++ led-running = &power_led; ++ led-upgrade = &power_led; + }; + + chosen { diff --git a/target/linux/rockchip/patches-6.6/103-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch b/target/linux/rockchip/patches-6.6/103-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch new file mode 100644 index 00000000000000..eeef0df014f2d0 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/103-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch @@ -0,0 +1,24 @@ +From 2795c8b31a686bdb8338f9404d18ef7a154f0d75 Mon Sep 17 00:00:00 2001 +From: David Bauer +Date: Sun, 26 Jul 2020 13:32:59 +0200 +Subject: [PATCH] arm64: rockchip: add OF node for USB eth on NanoPi R2S + +This adds the OF node for the USB3 ethernet adapter on the FriendlyARM +NanoPi R2S. Add the correct value for the RTL8153 LED configuration +register to match the blink behavior of the other port on the device. + +Signed-off-by: David Bauer +--- + arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 7 +++++++ + 1 file changed, 1 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts +@@ -406,6 +406,7 @@ + rtl8153: device@2 { + compatible = "usbbda,8153"; + reg = <2>; ++ realtek,led-data = <0x87>; + }; + }; + diff --git a/target/linux/rockchip/patches-6.6/105-nanopi-r4s-sd-signalling.patch b/target/linux/rockchip/patches-6.6/105-nanopi-r4s-sd-signalling.patch new file mode 100644 index 00000000000000..b3c941821aaaf8 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/105-nanopi-r4s-sd-signalling.patch @@ -0,0 +1,36 @@ +From: David Bauer +Subject: arm64: dts: rockchip: disable UHS modes for NanoPi R4S + +The NanoPi R4S leaves the SD card in 1.8V signalling when rebooting +while U-Boot requires the card to be in 3.3V mode. + +Remove UHS support from the SD controller so the card remains in 3.3V +mode. This reduces transfer speeds but ensures a reboot whether from +userspace or following a kernel panic is always working. + +Signed-off-by: David Bauer + +--- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts +@@ -335,7 +335,6 @@ + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; +- sd-uhs-sdr104; + vmmc-supply = <&vcc_sd>; + vqmmc-supply = <&vcc_sdio>; + status = "okay"; +--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts +@@ -112,6 +112,11 @@ + status = "disabled"; + }; + ++&sdmmc { ++ /delete-property/ sd-uhs-sdr104; ++ cap-sd-highspeed; ++}; ++ + &u2phy0_host { + phy-supply = <&vdd_5v>; + }; diff --git a/target/linux/rockchip/patches-6.6/106-r4s-openwrt-leds.patch b/target/linux/rockchip/patches-6.6/106-r4s-openwrt-leds.patch new file mode 100644 index 00000000000000..d7579d61e90ce3 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/106-r4s-openwrt-leds.patch @@ -0,0 +1,16 @@ +--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts +@@ -19,6 +19,13 @@ + model = "FriendlyElec NanoPi R4S"; + compatible = "friendlyarm,nanopi-r4s", "rockchip,rk3399"; + ++ aliases { ++ led-boot = &sys_led; ++ led-failsafe = &sys_led; ++ led-running = &sys_led; ++ led-upgrade = &sys_led; ++ }; ++ + /delete-node/ display-subsystem; + + gpio-leds { diff --git a/target/linux/rockchip/patches-6.6/107-arm64-dts-rockchip-Update-LED-properties-for-Orange-.patch b/target/linux/rockchip/patches-6.6/107-arm64-dts-rockchip-Update-LED-properties-for-Orange-.patch new file mode 100644 index 00000000000000..3aff37d0969b01 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/107-arm64-dts-rockchip-Update-LED-properties-for-Orange-.patch @@ -0,0 +1,40 @@ +From d2166e3b3680bd2b206aebf1e1ce4c0d346f3c50 Mon Sep 17 00:00:00 2001 +From: Tianling Shen +Date: Fri, 19 May 2023 12:10:52 +0800 +Subject: [PATCH] arm64: dts: rockchip: Update LED properties for Orange Pi R1 + Plus + +Add OpenWrt's LED aliases for showing system status. + +Signed-off-by: Tianling Shen +--- + .../dts/rockchip/rk3328-orangepi-r1-plus.dts | 17 +++++++++-------- + 1 file changed, 9 insertions(+), 8 deletions(-) + +--- a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts +@@ -17,6 +17,11 @@ + aliases { + ethernet1 = &rtl8153; + mmc0 = &sdmmc; ++ ++ led-boot = &status_led; ++ led-failsafe = &status_led; ++ led-running = &status_led; ++ led-upgrade = &status_led; + }; + + chosen { +@@ -41,11 +46,10 @@ + gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; + }; + +- led-1 { ++ status_led: led-1 { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; +- linux,default-trigger = "heartbeat"; + }; + + led-2 { diff --git a/target/linux/rockchip/patches-6.6/108-arm64-dts-rockchip-add-LED-configuration-to-Orange-P.patch b/target/linux/rockchip/patches-6.6/108-arm64-dts-rockchip-add-LED-configuration-to-Orange-P.patch new file mode 100644 index 00000000000000..af8f8b16bada0a --- /dev/null +++ b/target/linux/rockchip/patches-6.6/108-arm64-dts-rockchip-add-LED-configuration-to-Orange-P.patch @@ -0,0 +1,24 @@ +From b46a530d12ada422b9d5b2b97059e0d3ed950b40 Mon Sep 17 00:00:00 2001 +From: Tianling Shen +Date: Fri, 19 May 2023 12:38:04 +0800 +Subject: [PATCH] arm64: dts: rockchip: add LED configuration to Orange Pi R1 + Plus + +Add the correct value for the RTL8153 LED configuration register to +match the blink behavior of the other port on the device. + +Signed-off-by: Tianling Shen +--- + arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts | 1 + + 1 file changed, 1 insertion(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts +@@ -365,6 +365,7 @@ + rtl8153: device@2 { + compatible = "usbbda,8153"; + reg = <2>; ++ realtek,led-data = <0x87>; + }; + }; + diff --git a/target/linux/rockchip/patches-6.6/109-nanopc-t4-add-led-aliases.patch b/target/linux/rockchip/patches-6.6/109-nanopc-t4-add-led-aliases.patch new file mode 100644 index 00000000000000..1a80dadd48b93b --- /dev/null +++ b/target/linux/rockchip/patches-6.6/109-nanopc-t4-add-led-aliases.patch @@ -0,0 +1,16 @@ +--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts +@@ -15,6 +15,13 @@ + model = "FriendlyElec NanoPC-T4"; + compatible = "friendlyarm,nanopc-t4", "rockchip,rk3399"; + ++ aliases { ++ led-boot = &status_led; ++ led-failsafe = &status_led; ++ led-running = &status_led; ++ led-upgrade = &status_led; ++ }; ++ + vcc12v0_sys: vcc12v0-sys { + compatible = "regulator-fixed"; + regulator-always-on; diff --git a/target/linux/rockchip/patches-6.6/110-arm64-dts-rockchip-Update-LED-properties-for-NanoPi-.patch b/target/linux/rockchip/patches-6.6/110-arm64-dts-rockchip-Update-LED-properties-for-NanoPi-.patch new file mode 100644 index 00000000000000..c22fdd52b8a789 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/110-arm64-dts-rockchip-Update-LED-properties-for-NanoPi-.patch @@ -0,0 +1,45 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Tianling Shen +Date: Tue Jun 20 16:45:27 2023 +0800 +Subject: [PATCH] arm64: dts: rockchip: Update LED properties for NanoPi R5 + series + +Add OpenWrt's LED aliases for showing system status. + +Signed-off-by: Tianling Shen +--- + +--- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts +@@ -40,7 +40,6 @@ + power_led: led-power { + color = ; + function = LED_FUNCTION_POWER; +- linux,default-trigger = "heartbeat"; + gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>; + }; + +--- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts +@@ -39,7 +39,6 @@ + power_led: led-power { + color = ; + function = LED_FUNCTION_POWER; +- linux,default-trigger = "heartbeat"; + gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; + }; + +--- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi +@@ -18,6 +18,11 @@ + aliases { + mmc0 = &sdmmc0; + mmc1 = &sdhci; ++ ++ led-boot = &power_led; ++ led-failsafe = &power_led; ++ led-running = &power_led; ++ led-upgrade = &power_led; + }; + + chosen: chosen { diff --git a/target/linux/rockchip/patches-6.6/111-radxa-cm3-io-add-led-aliases.patch b/target/linux/rockchip/patches-6.6/111-radxa-cm3-io-add-led-aliases.patch new file mode 100644 index 00000000000000..c8183a2b8ae9b6 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/111-radxa-cm3-io-add-led-aliases.patch @@ -0,0 +1,36 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Marius Durbaca +Date: Tue Feb 20 15:05:27 2024 +0200 +Subject: [PATCH] arm64: dts: rockchip: Update LED properties for Radxa +CM3 IO board + +Add OpenWrt's LED aliases for showing system status. + +Suggested-by: Tianling Shen +Signed-off-by: Marius Durbaca +--- + +--- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts +@@ -16,6 +16,10 @@ + aliases { + ethernet0 = &gmac1; + mmc1 = &sdmmc0; ++ led-boot = &status_led; ++ led-failsafe = &status_led; ++ led-running = &status_led; ++ led-upgrade = &status_led; + }; + + chosen: chosen { +--- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi +@@ -17,7 +17,7 @@ + leds { + compatible = "gpio-leds"; + +- led-0 { ++ status_led: led-0 { + gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_STATUS; diff --git a/target/linux/rockchip/patches-6.6/112-radxa-e25-add-led-aliases.patch b/target/linux/rockchip/patches-6.6/112-radxa-e25-add-led-aliases.patch new file mode 100644 index 00000000000000..75038c7f39f4a6 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/112-radxa-e25-add-led-aliases.patch @@ -0,0 +1,24 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Marius Durbaca +Date: Tue Feb 27 16:25:27 2024 +0200 +Subject: [PATCH] arm64: dts: rockchip: Update LED properties for Radxa +E25 + +Add OpenWrt's LED aliases for showing system status. + +Signed-off-by: Marius Durbaca +--- + +--- a/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts +@@ -9,6 +9,10 @@ + + aliases { + mmc1 = &sdmmc0; ++ led-boot = &led_user; ++ led-failsafe = &led_user; ++ led-running = &led_user; ++ led-upgrade = &led_user; + }; + + pwm-leds { diff --git a/target/linux/rockchip/patches-6.6/300-hwrng-add-Rockchip-SoC-hwrng-driver.patch b/target/linux/rockchip/patches-6.6/300-hwrng-add-Rockchip-SoC-hwrng-driver.patch new file mode 100644 index 00000000000000..0be9a7300b0bf5 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/300-hwrng-add-Rockchip-SoC-hwrng-driver.patch @@ -0,0 +1,340 @@ +From patchwork Sat Nov 12 14:10:58 2022 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Aurelien Jarno +X-Patchwork-Id: 13041222 +Return-Path: + +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +From: Aurelien Jarno +To: Olivia Mackall , + Herbert Xu , + Rob Herring , + Krzysztof Kozlowski , + Heiko Stuebner , + Philipp Zabel , + Lin Jinhan +Cc: linux-crypto@vger.kernel.org (open list:HARDWARE RANDOM NUMBER GENERATOR + CORE), + devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE + BINDINGS), + linux-arm-kernel@lists.infradead.org (moderated list:ARM/Rockchip SoC + support), + linux-rockchip@lists.infradead.org (open list:ARM/Rockchip SoC support), + linux-kernel@vger.kernel.org (open list), + Aurelien Jarno +Subject: [PATCH v1 2/3] hwrng: add Rockchip SoC hwrng driver +Date: Sat, 12 Nov 2022 15:10:58 +0100 +Message-Id: <20221112141059.3802506-3-aurelien@aurel32.net> +In-Reply-To: <20221112141059.3802506-1-aurelien@aurel32.net> +References: <20221112141059.3802506-1-aurelien@aurel32.net> +MIME-Version: 1.0 +List-Id: + +Rockchip SoCs used to have a random number generator as part of their +crypto device, and support for it has to be added to the corresponding +driver. However newer Rockchip SoCs like the RK356x have an independent +True Random Number Generator device. This patch adds a driver for it, +greatly inspired from the downstream driver. + +The TRNG device does not seem to have a signal conditionner and the FIPS +140-2 test returns a lot of failures. They can be reduced by increasing +RK_RNG_SAMPLE_CNT, in a tradeoff between quality and speed. This value +has been adjusted to get ~90% of successes and the quality value has +been set accordingly. + +Signed-off-by: Aurelien Jarno +--- + drivers/char/hw_random/Kconfig | 14 ++ + drivers/char/hw_random/Makefile | 1 + + drivers/char/hw_random/rockchip-rng.c | 251 ++++++++++++++++++++++++++ + 3 files changed, 266 insertions(+) + create mode 100644 drivers/char/hw_random/rockchip-rng.c + +--- a/drivers/char/hw_random/Kconfig ++++ b/drivers/char/hw_random/Kconfig +@@ -573,6 +573,20 @@ config HW_RANDOM_JH7110 + To compile this driver as a module, choose M here. + The module will be called jh7110-trng. + ++config HW_RANDOM_ROCKCHIP ++ tristate "Rockchip True Random Number Generator" ++ depends on HW_RANDOM && (ARCH_ROCKCHIP || COMPILE_TEST) ++ depends on HAS_IOMEM ++ default HW_RANDOM ++ help ++ This driver provides kernel-side support for the True Random Number ++ Generator hardware found on some Rockchip SoC like RK3566 or RK3568. ++ ++ To compile this driver as a module, choose M here: the ++ module will be called rockchip-rng. ++ ++ If unsure, say Y. ++ + endif # HW_RANDOM + + config UML_RANDOM +--- a/drivers/char/hw_random/Makefile ++++ b/drivers/char/hw_random/Makefile +@@ -48,4 +48,5 @@ obj-$(CONFIG_HW_RANDOM_XIPHERA) += xiphe + obj-$(CONFIG_HW_RANDOM_ARM_SMCCC_TRNG) += arm_smccc_trng.o + obj-$(CONFIG_HW_RANDOM_CN10K) += cn10k-rng.o + obj-$(CONFIG_HW_RANDOM_POLARFIRE_SOC) += mpfs-rng.o ++obj-$(CONFIG_HW_RANDOM_ROCKCHIP) += rockchip-rng.o + obj-$(CONFIG_HW_RANDOM_JH7110) += jh7110-trng.o +--- /dev/null ++++ b/drivers/char/hw_random/rockchip-rng.c +@@ -0,0 +1,251 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * rockchip-rng.c True Random Number Generator driver for Rockchip SoCs ++ * ++ * Copyright (c) 2018, Fuzhou Rockchip Electronics Co., Ltd. ++ * Copyright (c) 2022, Aurelien Jarno ++ * Authors: ++ * Lin Jinhan ++ * Aurelien Jarno ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define RK_RNG_AUTOSUSPEND_DELAY 100 ++#define RK_RNG_MAX_BYTE 32 ++#define RK_RNG_POLL_PERIOD_US 100 ++#define RK_RNG_POLL_TIMEOUT_US 10000 ++ ++/* ++ * TRNG collects osc ring output bit every RK_RNG_SAMPLE_CNT time. The value is ++ * a tradeoff between speed and quality and has been adjusted to get a quality ++ * of ~900 (~90% of FIPS 140-2 successes). ++ */ ++#define RK_RNG_SAMPLE_CNT 1000 ++ ++/* TRNG registers from RK3568 TRM-Part2, section 5.4.1 */ ++#define TRNG_RST_CTL 0x0004 ++#define TRNG_RNG_CTL 0x0400 ++#define TRNG_RNG_CTL_LEN_64_BIT (0x00 << 4) ++#define TRNG_RNG_CTL_LEN_128_BIT (0x01 << 4) ++#define TRNG_RNG_CTL_LEN_192_BIT (0x02 << 4) ++#define TRNG_RNG_CTL_LEN_256_BIT (0x03 << 4) ++#define TRNG_RNG_CTL_OSC_RING_SPEED_0 (0x00 << 2) ++#define TRNG_RNG_CTL_OSC_RING_SPEED_1 (0x01 << 2) ++#define TRNG_RNG_CTL_OSC_RING_SPEED_2 (0x02 << 2) ++#define TRNG_RNG_CTL_OSC_RING_SPEED_3 (0x03 << 2) ++#define TRNG_RNG_CTL_ENABLE BIT(1) ++#define TRNG_RNG_CTL_START BIT(0) ++#define TRNG_RNG_SAMPLE_CNT 0x0404 ++#define TRNG_RNG_DOUT_0 0x0410 ++#define TRNG_RNG_DOUT_1 0x0414 ++#define TRNG_RNG_DOUT_2 0x0418 ++#define TRNG_RNG_DOUT_3 0x041c ++#define TRNG_RNG_DOUT_4 0x0420 ++#define TRNG_RNG_DOUT_5 0x0424 ++#define TRNG_RNG_DOUT_6 0x0428 ++#define TRNG_RNG_DOUT_7 0x042c ++ ++struct rk_rng { ++ struct hwrng rng; ++ void __iomem *base; ++ struct reset_control *rst; ++ int clk_num; ++ struct clk_bulk_data *clk_bulks; ++}; ++ ++/* The mask determine the bits that are updated */ ++static void rk_rng_write_ctl(struct rk_rng *rng, u32 val, u32 mask) ++{ ++ writel_relaxed((mask << 16) | val, rng->base + TRNG_RNG_CTL); ++} ++ ++static int rk_rng_init(struct hwrng *rng) ++{ ++ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); ++ u32 reg; ++ int ret; ++ ++ /* start clocks */ ++ ret = clk_bulk_prepare_enable(rk_rng->clk_num, rk_rng->clk_bulks); ++ if (ret < 0) { ++ dev_err((struct device *) rk_rng->rng.priv, ++ "Failed to enable clks %d\n", ret); ++ return ret; ++ } ++ ++ /* set the sample period */ ++ writel(RK_RNG_SAMPLE_CNT, rk_rng->base + TRNG_RNG_SAMPLE_CNT); ++ ++ /* set osc ring speed and enable it */ ++ reg = TRNG_RNG_CTL_LEN_256_BIT | ++ TRNG_RNG_CTL_OSC_RING_SPEED_0 | ++ TRNG_RNG_CTL_ENABLE; ++ rk_rng_write_ctl(rk_rng, reg, 0xffff); ++ ++ return 0; ++} ++ ++static void rk_rng_cleanup(struct hwrng *rng) ++{ ++ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); ++ u32 reg; ++ ++ /* stop TRNG */ ++ reg = 0; ++ rk_rng_write_ctl(rk_rng, reg, 0xffff); ++ ++ /* stop clocks */ ++ clk_bulk_disable_unprepare(rk_rng->clk_num, rk_rng->clk_bulks); ++} ++ ++static int rk_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait) ++{ ++ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); ++ u32 reg; ++ int ret = 0; ++ int i; ++ ++ pm_runtime_get_sync((struct device *) rk_rng->rng.priv); ++ ++ /* Start collecting random data */ ++ reg = TRNG_RNG_CTL_START; ++ rk_rng_write_ctl(rk_rng, reg, reg); ++ ++ ret = readl_poll_timeout(rk_rng->base + TRNG_RNG_CTL, reg, ++ !(reg & TRNG_RNG_CTL_START), ++ RK_RNG_POLL_PERIOD_US, ++ RK_RNG_POLL_TIMEOUT_US); ++ if (ret < 0) ++ goto out; ++ ++ /* Read random data stored in big endian in the registers */ ++ ret = min_t(size_t, max, RK_RNG_MAX_BYTE); ++ for (i = 0; i < ret; i += 4) { ++ reg = readl_relaxed(rk_rng->base + TRNG_RNG_DOUT_0 + i); ++ *(u32 *)(buf + i) = be32_to_cpu(reg); ++ } ++ ++out: ++ pm_runtime_mark_last_busy((struct device *) rk_rng->rng.priv); ++ pm_runtime_put_sync_autosuspend((struct device *) rk_rng->rng.priv); ++ ++ return ret; ++} ++ ++static int rk_rng_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct rk_rng *rk_rng; ++ int ret; ++ ++ rk_rng = devm_kzalloc(dev, sizeof(struct rk_rng), GFP_KERNEL); ++ if (!rk_rng) ++ return -ENOMEM; ++ ++ rk_rng->base = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(rk_rng->base)) ++ return PTR_ERR(rk_rng->base); ++ ++ rk_rng->clk_num = devm_clk_bulk_get_all(dev, &rk_rng->clk_bulks); ++ if (rk_rng->clk_num < 0) ++ return dev_err_probe(dev, rk_rng->clk_num, ++ "Failed to get clks property\n"); ++ ++ rk_rng->rst = devm_reset_control_array_get(&pdev->dev, false, false); ++ if (IS_ERR(rk_rng->rst)) ++ return dev_err_probe(dev, PTR_ERR(rk_rng->rst), ++ "Failed to get reset property\n"); ++ ++ reset_control_assert(rk_rng->rst); ++ udelay(2); ++ reset_control_deassert(rk_rng->rst); ++ ++ platform_set_drvdata(pdev, rk_rng); ++ ++ rk_rng->rng.name = dev_driver_string(dev); ++#ifndef CONFIG_PM ++ rk_rng->rng.init = rk_rng_init; ++ rk_rng->rng.cleanup = rk_rng_cleanup; ++#endif ++ rk_rng->rng.read = rk_rng_read; ++ rk_rng->rng.priv = (unsigned long) dev; ++ rk_rng->rng.quality = 900; ++ ++ pm_runtime_set_autosuspend_delay(dev, RK_RNG_AUTOSUSPEND_DELAY); ++ pm_runtime_use_autosuspend(dev); ++ pm_runtime_enable(dev); ++ ++ ret = devm_hwrng_register(dev, &rk_rng->rng); ++ if (ret) ++ return dev_err_probe(&pdev->dev, ret, "Failed to register Rockchip hwrng\n"); ++ ++ dev_info(&pdev->dev, "Registered Rockchip hwrng\n"); ++ ++ return 0; ++} ++ ++static int rk_rng_remove(struct platform_device *pdev) ++{ ++ pm_runtime_disable(&pdev->dev); ++ ++ return 0; ++} ++ ++#ifdef CONFIG_PM ++static int rk_rng_runtime_suspend(struct device *dev) ++{ ++ struct rk_rng *rk_rng = dev_get_drvdata(dev); ++ ++ rk_rng_cleanup(&rk_rng->rng); ++ ++ return 0; ++} ++ ++static int rk_rng_runtime_resume(struct device *dev) ++{ ++ struct rk_rng *rk_rng = dev_get_drvdata(dev); ++ ++ return rk_rng_init(&rk_rng->rng); ++} ++#endif ++ ++static const struct dev_pm_ops rk_rng_pm_ops = { ++ SET_RUNTIME_PM_OPS(rk_rng_runtime_suspend, ++ rk_rng_runtime_resume, NULL) ++ SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, ++ pm_runtime_force_resume) ++}; ++ ++static const struct of_device_id rk_rng_dt_match[] = { ++ { ++ .compatible = "rockchip,rk3568-rng", ++ }, ++ {}, ++}; ++ ++MODULE_DEVICE_TABLE(of, rk_rng_dt_match); ++ ++static struct platform_driver rk_rng_driver = { ++ .driver = { ++ .name = "rockchip-rng", ++ .pm = &rk_rng_pm_ops, ++ .of_match_table = rk_rng_dt_match, ++ }, ++ .probe = rk_rng_probe, ++ .remove = rk_rng_remove, ++}; ++ ++module_platform_driver(rk_rng_driver); ++ ++MODULE_DESCRIPTION("Rockchip True Random Number Generator driver"); ++MODULE_AUTHOR("Lin Jinhan , Aurelien Jarno "); ++MODULE_LICENSE("GPL v2"); diff --git a/target/linux/rockchip/patches-6.6/301-arm64-dts-rockchip-add-DT-entry-for-RNG-to-RK356x.patch b/target/linux/rockchip/patches-6.6/301-arm64-dts-rockchip-add-DT-entry-for-RNG-to-RK356x.patch new file mode 100644 index 00000000000000..577aa6c9d25655 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/301-arm64-dts-rockchip-add-DT-entry-for-RNG-to-RK356x.patch @@ -0,0 +1,56 @@ +From patchwork Sat Nov 12 14:10:59 2022 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Aurelien Jarno +X-Patchwork-Id: 13041221 +From: Aurelien Jarno +To: Olivia Mackall , + Herbert Xu , + Rob Herring , + Krzysztof Kozlowski , + Heiko Stuebner , + Philipp Zabel , + Lin Jinhan +Cc: linux-crypto@vger.kernel.org (open list:HARDWARE RANDOM NUMBER GENERATOR + CORE), + devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE + BINDINGS), + linux-arm-kernel@lists.infradead.org (moderated list:ARM/Rockchip SoC + support), + linux-rockchip@lists.infradead.org (open list:ARM/Rockchip SoC support), + linux-kernel@vger.kernel.org (open list), + Aurelien Jarno +Subject: [PATCH v1 3/3] arm64: dts: rockchip: add DT entry for RNG to RK356x +Date: Sat, 12 Nov 2022 15:10:59 +0100 +Message-Id: <20221112141059.3802506-4-aurelien@aurel32.net> +In-Reply-To: <20221112141059.3802506-1-aurelien@aurel32.net> +References: <20221112141059.3802506-1-aurelien@aurel32.net> +MIME-Version: 1.0 +List-Id: + +Enable the just added Rockchip RNG driver for RK356x SoCs. + +Signed-off-by: Aurelien Jarno +--- + arch/arm64/boot/dts/rockchip/rk356x.dtsi | 9 +++++++++ + 1 file changed, 9 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi +@@ -1807,6 +1807,15 @@ + }; + }; + ++ rng: rng@fe388000 { ++ compatible = "rockchip,rk3568-rng"; ++ reg = <0x0 0xfe388000 0x0 0x4000>; ++ clocks = <&cru CLK_TRNG_NS>, <&cru HCLK_TRNG_NS>; ++ clock-names = "trng_clk", "trng_hclk"; ++ resets = <&cru SRST_TRNG_NS>; ++ reset-names = "reset"; ++ }; ++ + pinctrl: pinctrl { + compatible = "rockchip,rk3568-pinctrl"; + rockchip,grf = <&grf>; diff --git a/tools/include/asm/bitsperlong.h b/tools/include/asm/bitsperlong.h new file mode 100644 index 00000000000000..75f320fa91e54e --- /dev/null +++ b/tools/include/asm/bitsperlong.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ +#ifndef __ASM_GENERIC_BITS_PER_LONG +#define __ASM_GENERIC_BITS_PER_LONG + +#ifndef __BITS_PER_LONG +/* + * In order to keep safe and avoid regression, only unify uapi + * bitsperlong.h for some archs which are using newer toolchains + * that have the definitions of __CHAR_BIT__ and __SIZEOF_LONG__. + * See the following link for more info: + * https://lore.kernel.org/linux-arch/b9624545-2c80-49a1-ac3c-39264a591f7b@app.fastmail.com/ + */ +#if defined(__CHAR_BIT__) && defined(__SIZEOF_LONG__) +#define __BITS_PER_LONG (__CHAR_BIT__ * __SIZEOF_LONG__) +#else +/* + * There seems to be no way of detecting this automatically from user + * space, so 64 bit architectures should override this in their + * bitsperlong.h. In particular, an architecture that supports + * both 32 and 64 bit user space must not rely on CONFIG_64BIT + * to decide it, but rather check a compiler provided macro. + */ +#define __BITS_PER_LONG 32 +#endif +#endif + +#endif /* __ASM_GENERIC_BITS_PER_LONG */ diff --git a/tools/include/asm/byteorder.h b/tools/include/asm/byteorder.h new file mode 100644 index 00000000000000..8e7d779d7dd015 --- /dev/null +++ b/tools/include/asm/byteorder.h @@ -0,0 +1,12 @@ +#ifndef __ASM_BYTEORDER_H +#define __ASM_BYTEORDER_H + +#include + +#if __BYTE_ORDER == __LITTLE_ENDIAN +#include +#else +#include +#endif + +#endif diff --git a/tools/include/asm/errno-base.h b/tools/include/asm/errno-base.h new file mode 100644 index 00000000000000..9653140bff92dd --- /dev/null +++ b/tools/include/asm/errno-base.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ +#ifndef _ASM_GENERIC_ERRNO_BASE_H +#define _ASM_GENERIC_ERRNO_BASE_H + +#define EPERM 1 /* Operation not permitted */ +#define ENOENT 2 /* No such file or directory */ +#define ESRCH 3 /* No such process */ +#define EINTR 4 /* Interrupted system call */ +#define EIO 5 /* I/O error */ +#define ENXIO 6 /* No such device or address */ +#define E2BIG 7 /* Argument list too long */ +#define ENOEXEC 8 /* Exec format error */ +#define EBADF 9 /* Bad file number */ +#define ECHILD 10 /* No child processes */ +#define EAGAIN 11 /* Try again */ +#define ENOMEM 12 /* Out of memory */ +#define EACCES 13 /* Permission denied */ +#define EFAULT 14 /* Bad address */ +#define ENOTBLK 15 /* Block device required */ +#define EBUSY 16 /* Device or resource busy */ +#define EEXIST 17 /* File exists */ +#define EXDEV 18 /* Cross-device link */ +#define ENODEV 19 /* No such device */ +#define ENOTDIR 20 /* Not a directory */ +#define EISDIR 21 /* Is a directory */ +#define EINVAL 22 /* Invalid argument */ +#define ENFILE 23 /* File table overflow */ +#define EMFILE 24 /* Too many open files */ +#define ENOTTY 25 /* Not a typewriter */ +#define ETXTBSY 26 /* Text file busy */ +#define EFBIG 27 /* File too large */ +#define ENOSPC 28 /* No space left on device */ +#define ESPIPE 29 /* Illegal seek */ +#define EROFS 30 /* Read-only file system */ +#define EMLINK 31 /* Too many links */ +#define EPIPE 32 /* Broken pipe */ +#define EDOM 33 /* Math argument out of domain of func */ +#define ERANGE 34 /* Math result not representable */ + +#endif diff --git a/tools/include/asm/errno.h b/tools/include/asm/errno.h new file mode 100644 index 00000000000000..a96d52533013a6 --- /dev/null +++ b/tools/include/asm/errno.h @@ -0,0 +1,123 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ +#ifndef _ASM_GENERIC_ERRNO_H +#define _ASM_GENERIC_ERRNO_H + +#include + +#define EDEADLK 35 /* Resource deadlock would occur */ +#define ENAMETOOLONG 36 /* File name too long */ +#define ENOLCK 37 /* No record locks available */ + +/* + * This error code is special: arch syscall entry code will return + * -ENOSYS if users try to call a syscall that doesn't exist. To keep + * failures of syscalls that really do exist distinguishable from + * failures due to attempts to use a nonexistent syscall, syscall + * implementations should refrain from returning -ENOSYS. + */ +#define ENOSYS 38 /* Invalid system call number */ + +#define ENOTEMPTY 39 /* Directory not empty */ +#define ELOOP 40 /* Too many symbolic links encountered */ +#define EWOULDBLOCK EAGAIN /* Operation would block */ +#define ENOMSG 42 /* No message of desired type */ +#define EIDRM 43 /* Identifier removed */ +#define ECHRNG 44 /* Channel number out of range */ +#define EL2NSYNC 45 /* Level 2 not synchronized */ +#define EL3HLT 46 /* Level 3 halted */ +#define EL3RST 47 /* Level 3 reset */ +#define ELNRNG 48 /* Link number out of range */ +#define EUNATCH 49 /* Protocol driver not attached */ +#define ENOCSI 50 /* No CSI structure available */ +#define EL2HLT 51 /* Level 2 halted */ +#define EBADE 52 /* Invalid exchange */ +#define EBADR 53 /* Invalid request descriptor */ +#define EXFULL 54 /* Exchange full */ +#define ENOANO 55 /* No anode */ +#define EBADRQC 56 /* Invalid request code */ +#define EBADSLT 57 /* Invalid slot */ + +#define EDEADLOCK EDEADLK + +#define EBFONT 59 /* Bad font file format */ +#define ENOSTR 60 /* Device not a stream */ +#define ENODATA 61 /* No data available */ +#define ETIME 62 /* Timer expired */ +#define ENOSR 63 /* Out of streams resources */ +#define ENONET 64 /* Machine is not on the network */ +#define ENOPKG 65 /* Package not installed */ +#define EREMOTE 66 /* Object is remote */ +#define ENOLINK 67 /* Link has been severed */ +#define EADV 68 /* Advertise error */ +#define ESRMNT 69 /* Srmount error */ +#define ECOMM 70 /* Communication error on send */ +#define EPROTO 71 /* Protocol error */ +#define EMULTIHOP 72 /* Multihop attempted */ +#define EDOTDOT 73 /* RFS specific error */ +#define EBADMSG 74 /* Not a data message */ +#define EOVERFLOW 75 /* Value too large for defined data type */ +#define ENOTUNIQ 76 /* Name not unique on network */ +#define EBADFD 77 /* File descriptor in bad state */ +#define EREMCHG 78 /* Remote address changed */ +#define ELIBACC 79 /* Can not access a needed shared library */ +#define ELIBBAD 80 /* Accessing a corrupted shared library */ +#define ELIBSCN 81 /* .lib section in a.out corrupted */ +#define ELIBMAX 82 /* Attempting to link in too many shared libraries */ +#define ELIBEXEC 83 /* Cannot exec a shared library directly */ +#define EILSEQ 84 /* Illegal byte sequence */ +#define ERESTART 85 /* Interrupted system call should be restarted */ +#define ESTRPIPE 86 /* Streams pipe error */ +#define EUSERS 87 /* Too many users */ +#define ENOTSOCK 88 /* Socket operation on non-socket */ +#define EDESTADDRREQ 89 /* Destination address required */ +#define EMSGSIZE 90 /* Message too long */ +#define EPROTOTYPE 91 /* Protocol wrong type for socket */ +#define ENOPROTOOPT 92 /* Protocol not available */ +#define EPROTONOSUPPORT 93 /* Protocol not supported */ +#define ESOCKTNOSUPPORT 94 /* Socket type not supported */ +#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */ +#define EPFNOSUPPORT 96 /* Protocol family not supported */ +#define EAFNOSUPPORT 97 /* Address family not supported by protocol */ +#define EADDRINUSE 98 /* Address already in use */ +#define EADDRNOTAVAIL 99 /* Cannot assign requested address */ +#define ENETDOWN 100 /* Network is down */ +#define ENETUNREACH 101 /* Network is unreachable */ +#define ENETRESET 102 /* Network dropped connection because of reset */ +#define ECONNABORTED 103 /* Software caused connection abort */ +#define ECONNRESET 104 /* Connection reset by peer */ +#define ENOBUFS 105 /* No buffer space available */ +#define EISCONN 106 /* Transport endpoint is already connected */ +#define ENOTCONN 107 /* Transport endpoint is not connected */ +#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */ +#define ETOOMANYREFS 109 /* Too many references: cannot splice */ +#define ETIMEDOUT 110 /* Connection timed out */ +#define ECONNREFUSED 111 /* Connection refused */ +#define EHOSTDOWN 112 /* Host is down */ +#define EHOSTUNREACH 113 /* No route to host */ +#define EALREADY 114 /* Operation already in progress */ +#define EINPROGRESS 115 /* Operation now in progress */ +#define ESTALE 116 /* Stale file handle */ +#define EUCLEAN 117 /* Structure needs cleaning */ +#define ENOTNAM 118 /* Not a XENIX named type file */ +#define ENAVAIL 119 /* No XENIX semaphores available */ +#define EISNAM 120 /* Is a named type file */ +#define EREMOTEIO 121 /* Remote I/O error */ +#define EDQUOT 122 /* Quota exceeded */ + +#define ENOMEDIUM 123 /* No medium found */ +#define EMEDIUMTYPE 124 /* Wrong medium type */ +#define ECANCELED 125 /* Operation Canceled */ +#define ENOKEY 126 /* Required key not available */ +#define EKEYEXPIRED 127 /* Key has expired */ +#define EKEYREVOKED 128 /* Key has been revoked */ +#define EKEYREJECTED 129 /* Key was rejected by service */ + +/* for robust mutexes */ +#define EOWNERDEAD 130 /* Owner died */ +#define ENOTRECOVERABLE 131 /* State not recoverable */ + +#define ERFKILL 132 /* Operation not possible due to RF-kill */ + +#define EHWPOISON 133 /* Memory page has hardware error */ + +#endif diff --git a/tools/include/asm/posix_types.h b/tools/include/asm/posix_types.h new file mode 100644 index 00000000000000..10f5e6ef4ab57c --- /dev/null +++ b/tools/include/asm/posix_types.h @@ -0,0 +1,100 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ +#ifndef __ASM_GENERIC_POSIX_TYPES_H +#define __ASM_GENERIC_POSIX_TYPES_H + +#include + +/* + * This file is generally used by user-level software, so you need to + * be a little careful about namespace pollution etc. + * + * First the types that are often defined in different ways across + * architectures, so that you can override them. + */ + +#ifndef __kernel_long_t +typedef long __kernel_long_t; +typedef unsigned long __kernel_ulong_t; +#endif + +#ifndef __kernel_ino_t +typedef __kernel_ulong_t __kernel_ino_t; +#endif + +#ifndef __kernel_mode_t +typedef unsigned int __kernel_mode_t; +#endif + +#ifndef __kernel_pid_t +typedef int __kernel_pid_t; +#endif + +#ifndef __kernel_ipc_pid_t +typedef int __kernel_ipc_pid_t; +#endif + +#ifndef __kernel_uid_t +typedef unsigned int __kernel_uid_t; +typedef unsigned int __kernel_gid_t; +#endif + +#ifndef __kernel_suseconds_t +typedef __kernel_long_t __kernel_suseconds_t; +#endif + +#ifndef __kernel_daddr_t +typedef int __kernel_daddr_t; +#endif + +#ifndef __kernel_uid32_t +typedef unsigned int __kernel_uid32_t; +typedef unsigned int __kernel_gid32_t; +#endif + +#ifndef __kernel_old_uid_t +typedef __kernel_uid_t __kernel_old_uid_t; +typedef __kernel_gid_t __kernel_old_gid_t; +#endif + +#ifndef __kernel_old_dev_t +typedef unsigned int __kernel_old_dev_t; +#endif + +/* + * Most 32 bit architectures use "unsigned int" size_t, + * and all 64 bit architectures use "unsigned long" size_t. + */ +#ifndef __kernel_size_t +#if __BITS_PER_LONG != 64 +typedef unsigned int __kernel_size_t; +typedef int __kernel_ssize_t; +typedef int __kernel_ptrdiff_t; +#else +typedef __kernel_ulong_t __kernel_size_t; +typedef __kernel_long_t __kernel_ssize_t; +typedef __kernel_long_t __kernel_ptrdiff_t; +#endif +#endif + +#ifndef __kernel_fsid_t +typedef struct { + int val[2]; +} __kernel_fsid_t; +#endif + +/* + * anything below here should be completely generic + */ +typedef __kernel_long_t __kernel_off_t; +typedef long long __kernel_loff_t; +typedef __kernel_long_t __kernel_old_time_t; +typedef __kernel_long_t __kernel_time_t; +typedef long long __kernel_time64_t; +typedef __kernel_long_t __kernel_clock_t; +typedef int __kernel_timer_t; +typedef int __kernel_clockid_t; +typedef char * __kernel_caddr_t; +typedef unsigned short __kernel_uid16_t; +typedef unsigned short __kernel_gid16_t; + +#endif /* __ASM_GENERIC_POSIX_TYPES_H */ diff --git a/tools/include/asm/swab.h b/tools/include/asm/swab.h new file mode 100644 index 00000000000000..f2da4e4fd4d129 --- /dev/null +++ b/tools/include/asm/swab.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ +#ifndef _ASM_GENERIC_SWAB_H +#define _ASM_GENERIC_SWAB_H + +#include + +/* + * 32 bit architectures typically (but not always) want to + * set __SWAB_64_THRU_32__. In user space, this is only + * valid if the compiler supports 64 bit data types. + */ + +#if __BITS_PER_LONG == 32 +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) || defined(__KERNEL__) +#define __SWAB_64_THRU_32__ +#endif +#endif + +#endif /* _ASM_GENERIC_SWAB_H */ diff --git a/tools/include/linux/big_endian.h b/tools/include/linux/big_endian.h new file mode 100644 index 00000000000000..3bb87c573cd60e --- /dev/null +++ b/tools/include/linux/big_endian.h @@ -0,0 +1,107 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ +#ifndef _LINUX_BYTEORDER_BIG_ENDIAN_H +#define _LINUX_BYTEORDER_BIG_ENDIAN_H + +#ifndef __BIG_ENDIAN +#define __BIG_ENDIAN 4321 +#endif +#ifndef __BIG_ENDIAN_BITFIELD +#define __BIG_ENDIAN_BITFIELD +#endif + +#include +#include +#include + +#define __constant_htonl(x) ((__be32)(__u32)(x)) +#define __constant_ntohl(x) ((__u32)(__be32)(x)) +#define __constant_htons(x) ((__be16)(__u16)(x)) +#define __constant_ntohs(x) ((__u16)(__be16)(x)) +#define __constant_cpu_to_le64(x) ((__le64)___constant_swab64((x))) +#define __constant_le64_to_cpu(x) ___constant_swab64((__u64)(__le64)(x)) +#define __constant_cpu_to_le32(x) ((__le32)___constant_swab32((x))) +#define __constant_le32_to_cpu(x) ___constant_swab32((__u32)(__le32)(x)) +#define __constant_cpu_to_le16(x) ((__le16)___constant_swab16((x))) +#define __constant_le16_to_cpu(x) ___constant_swab16((__u16)(__le16)(x)) +#define __constant_cpu_to_be64(x) ((__be64)(__u64)(x)) +#define __constant_be64_to_cpu(x) ((__u64)(__be64)(x)) +#define __constant_cpu_to_be32(x) ((__be32)(__u32)(x)) +#define __constant_be32_to_cpu(x) ((__u32)(__be32)(x)) +#define __constant_cpu_to_be16(x) ((__be16)(__u16)(x)) +#define __constant_be16_to_cpu(x) ((__u16)(__be16)(x)) +#define __cpu_to_le64(x) ((__le64)__swab64((x))) +#define __le64_to_cpu(x) __swab64((__u64)(__le64)(x)) +#define __cpu_to_le32(x) ((__le32)__swab32((x))) +#define __le32_to_cpu(x) __swab32((__u32)(__le32)(x)) +#define __cpu_to_le16(x) ((__le16)__swab16((x))) +#define __le16_to_cpu(x) __swab16((__u16)(__le16)(x)) +#define __cpu_to_be64(x) ((__be64)(__u64)(x)) +#define __be64_to_cpu(x) ((__u64)(__be64)(x)) +#define __cpu_to_be32(x) ((__be32)(__u32)(x)) +#define __be32_to_cpu(x) ((__u32)(__be32)(x)) +#define __cpu_to_be16(x) ((__be16)(__u16)(x)) +#define __be16_to_cpu(x) ((__u16)(__be16)(x)) + +static __always_inline __le64 __cpu_to_le64p(const __u64 *p) +{ + return (__le64)__swab64p(p); +} +static __always_inline __u64 __le64_to_cpup(const __le64 *p) +{ + return __swab64p((__u64 *)p); +} +static __always_inline __le32 __cpu_to_le32p(const __u32 *p) +{ + return (__le32)__swab32p(p); +} +static __always_inline __u32 __le32_to_cpup(const __le32 *p) +{ + return __swab32p((__u32 *)p); +} +static __always_inline __le16 __cpu_to_le16p(const __u16 *p) +{ + return (__le16)__swab16p(p); +} +static __always_inline __u16 __le16_to_cpup(const __le16 *p) +{ + return __swab16p((__u16 *)p); +} +static __always_inline __be64 __cpu_to_be64p(const __u64 *p) +{ + return (__be64)*p; +} +static __always_inline __u64 __be64_to_cpup(const __be64 *p) +{ + return (__u64)*p; +} +static __always_inline __be32 __cpu_to_be32p(const __u32 *p) +{ + return (__be32)*p; +} +static __always_inline __u32 __be32_to_cpup(const __be32 *p) +{ + return (__u32)*p; +} +static __always_inline __be16 __cpu_to_be16p(const __u16 *p) +{ + return (__be16)*p; +} +static __always_inline __u16 __be16_to_cpup(const __be16 *p) +{ + return (__u16)*p; +} +#define __cpu_to_le64s(x) __swab64s((x)) +#define __le64_to_cpus(x) __swab64s((x)) +#define __cpu_to_le32s(x) __swab32s((x)) +#define __le32_to_cpus(x) __swab32s((x)) +#define __cpu_to_le16s(x) __swab16s((x)) +#define __le16_to_cpus(x) __swab16s((x)) +#define __cpu_to_be64s(x) do { (void)(x); } while (0) +#define __be64_to_cpus(x) do { (void)(x); } while (0) +#define __cpu_to_be32s(x) do { (void)(x); } while (0) +#define __be32_to_cpus(x) do { (void)(x); } while (0) +#define __cpu_to_be16s(x) do { (void)(x); } while (0) +#define __be16_to_cpus(x) do { (void)(x); } while (0) + + +#endif /* _LINUX_BYTEORDER_BIG_ENDIAN_H */ diff --git a/tools/include/linux/errno.h b/tools/include/linux/errno.h new file mode 100644 index 00000000000000..70f2bd34e3354b --- /dev/null +++ b/tools/include/linux/errno.h @@ -0,0 +1 @@ +#include diff --git a/tools/include/linux/little_endian.h b/tools/include/linux/little_endian.h new file mode 100644 index 00000000000000..ba6c199c9b6f3e --- /dev/null +++ b/tools/include/linux/little_endian.h @@ -0,0 +1,107 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ +#ifndef _LINUX_BYTEORDER_LITTLE_ENDIAN_H +#define _LINUX_BYTEORDER_LITTLE_ENDIAN_H + +#ifndef __LITTLE_ENDIAN +#define __LITTLE_ENDIAN 1234 +#endif +#ifndef __LITTLE_ENDIAN_BITFIELD +#define __LITTLE_ENDIAN_BITFIELD +#endif + +#include +#include +#include + +#define __constant_htonl(x) ((__be32)___constant_swab32((x))) +#define __constant_ntohl(x) ___constant_swab32((__be32)(x)) +#define __constant_htons(x) ((__be16)___constant_swab16((x))) +#define __constant_ntohs(x) ___constant_swab16((__be16)(x)) +#define __constant_cpu_to_le64(x) ((__le64)(__u64)(x)) +#define __constant_le64_to_cpu(x) ((__u64)(__le64)(x)) +#define __constant_cpu_to_le32(x) ((__le32)(__u32)(x)) +#define __constant_le32_to_cpu(x) ((__u32)(__le32)(x)) +#define __constant_cpu_to_le16(x) ((__le16)(__u16)(x)) +#define __constant_le16_to_cpu(x) ((__u16)(__le16)(x)) +#define __constant_cpu_to_be64(x) ((__be64)___constant_swab64((x))) +#define __constant_be64_to_cpu(x) ___constant_swab64((__u64)(__be64)(x)) +#define __constant_cpu_to_be32(x) ((__be32)___constant_swab32((x))) +#define __constant_be32_to_cpu(x) ___constant_swab32((__u32)(__be32)(x)) +#define __constant_cpu_to_be16(x) ((__be16)___constant_swab16((x))) +#define __constant_be16_to_cpu(x) ___constant_swab16((__u16)(__be16)(x)) +#define __cpu_to_le64(x) ((__le64)(__u64)(x)) +#define __le64_to_cpu(x) ((__u64)(__le64)(x)) +#define __cpu_to_le32(x) ((__le32)(__u32)(x)) +#define __le32_to_cpu(x) ((__u32)(__le32)(x)) +#define __cpu_to_le16(x) ((__le16)(__u16)(x)) +#define __le16_to_cpu(x) ((__u16)(__le16)(x)) +#define __cpu_to_be64(x) ((__be64)__swab64((x))) +#define __be64_to_cpu(x) __swab64((__u64)(__be64)(x)) +#define __cpu_to_be32(x) ((__be32)__swab32((x))) +#define __be32_to_cpu(x) __swab32((__u32)(__be32)(x)) +#define __cpu_to_be16(x) ((__be16)__swab16((x))) +#define __be16_to_cpu(x) __swab16((__u16)(__be16)(x)) + +static __always_inline __le64 __cpu_to_le64p(const __u64 *p) +{ + return (__le64)*p; +} +static __always_inline __u64 __le64_to_cpup(const __le64 *p) +{ + return (__u64)*p; +} +static __always_inline __le32 __cpu_to_le32p(const __u32 *p) +{ + return (__le32)*p; +} +static __always_inline __u32 __le32_to_cpup(const __le32 *p) +{ + return (__u32)*p; +} +static __always_inline __le16 __cpu_to_le16p(const __u16 *p) +{ + return (__le16)*p; +} +static __always_inline __u16 __le16_to_cpup(const __le16 *p) +{ + return (__u16)*p; +} +static __always_inline __be64 __cpu_to_be64p(const __u64 *p) +{ + return (__be64)__swab64p(p); +} +static __always_inline __u64 __be64_to_cpup(const __be64 *p) +{ + return __swab64p((__u64 *)p); +} +static __always_inline __be32 __cpu_to_be32p(const __u32 *p) +{ + return (__be32)__swab32p(p); +} +static __always_inline __u32 __be32_to_cpup(const __be32 *p) +{ + return __swab32p((__u32 *)p); +} +static __always_inline __be16 __cpu_to_be16p(const __u16 *p) +{ + return (__be16)__swab16p(p); +} +static __always_inline __u16 __be16_to_cpup(const __be16 *p) +{ + return __swab16p((__u16 *)p); +} +#define __cpu_to_le64s(x) do { (void)(x); } while (0) +#define __le64_to_cpus(x) do { (void)(x); } while (0) +#define __cpu_to_le32s(x) do { (void)(x); } while (0) +#define __le32_to_cpus(x) do { (void)(x); } while (0) +#define __cpu_to_le16s(x) do { (void)(x); } while (0) +#define __le16_to_cpus(x) do { (void)(x); } while (0) +#define __cpu_to_be64s(x) __swab64s((x)) +#define __be64_to_cpus(x) __swab64s((x)) +#define __cpu_to_be32s(x) __swab32s((x)) +#define __be32_to_cpus(x) __swab32s((x)) +#define __cpu_to_be16s(x) __swab16s((x)) +#define __be16_to_cpus(x) __swab16s((x)) + + +#endif /* _LINUX_BYTEORDER_LITTLE_ENDIAN_H */ diff --git a/tools/include/linux/stddef.h b/tools/include/linux/stddef.h new file mode 100644 index 00000000000000..e3d20e76b1e6e2 --- /dev/null +++ b/tools/include/linux/stddef.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ +#ifndef _UAPI_LINUX_STDDEF_H +#define _UAPI_LINUX_STDDEF_H + +#ifndef __always_inline +#define __always_inline inline +#endif + +/** + * __struct_group() - Create a mirrored named and anonyomous struct + * + * @TAG: The tag name for the named sub-struct (usually empty) + * @NAME: The identifier name of the mirrored sub-struct + * @ATTRS: Any struct attributes (usually empty) + * @MEMBERS: The member declarations for the mirrored structs + * + * Used to create an anonymous union of two structs with identical layout + * and size: one anonymous and one named. The former's members can be used + * normally without sub-struct naming, and the latter can be used to + * reason about the start, end, and size of the group of struct members. + * The named struct can also be explicitly tagged for layer reuse, as well + * as both having struct attributes appended. + */ +#define __struct_group(TAG, NAME, ATTRS, MEMBERS...) \ + union { \ + struct { MEMBERS } ATTRS; \ + struct TAG { MEMBERS } ATTRS NAME; \ + } ATTRS + +#ifdef __cplusplus +/* sizeof(struct{}) is 1 in C++, not 0, can't use C version of the macro. */ +#define __DECLARE_FLEX_ARRAY(T, member) \ + T member[0] +#else +/** + * __DECLARE_FLEX_ARRAY() - Declare a flexible array usable in a union + * + * @TYPE: The type of each flexible array element + * @NAME: The name of the flexible array member + * + * In order to have a flexible array member in a union or alone in a + * struct, it needs to be wrapped in an anonymous struct with at least 1 + * named member, but that member can be empty. + */ +#define __DECLARE_FLEX_ARRAY(TYPE, NAME) \ + struct { \ + struct { } __empty_ ## NAME; \ + TYPE NAME[]; \ + } +#endif + +#ifndef __counted_by +#define __counted_by(m) +#endif + +#endif /* _UAPI_LINUX_STDDEF_H */ diff --git a/tools/include/linux/swab.h b/tools/include/linux/swab.h new file mode 100644 index 00000000000000..7e3bad56cf8d76 --- /dev/null +++ b/tools/include/linux/swab.h @@ -0,0 +1,305 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ +#ifndef _LINUX_SWAB_H +#define _LINUX_SWAB_H + +#include +#include +#include +#include + +/* + * casts are necessary for constants, because we never know how for sure + * how U/UL/ULL map to __u16, __u32, __u64. At least not in a portable way. + */ +#define ___constant_swab16(x) ((__u16)( \ + (((__u16)(x) & (__u16)0x00ffU) << 8) | \ + (((__u16)(x) & (__u16)0xff00U) >> 8))) + +#define ___constant_swab32(x) ((__u32)( \ + (((__u32)(x) & (__u32)0x000000ffUL) << 24) | \ + (((__u32)(x) & (__u32)0x0000ff00UL) << 8) | \ + (((__u32)(x) & (__u32)0x00ff0000UL) >> 8) | \ + (((__u32)(x) & (__u32)0xff000000UL) >> 24))) + +#define ___constant_swab64(x) ((__u64)( \ + (((__u64)(x) & (__u64)0x00000000000000ffULL) << 56) | \ + (((__u64)(x) & (__u64)0x000000000000ff00ULL) << 40) | \ + (((__u64)(x) & (__u64)0x0000000000ff0000ULL) << 24) | \ + (((__u64)(x) & (__u64)0x00000000ff000000ULL) << 8) | \ + (((__u64)(x) & (__u64)0x000000ff00000000ULL) >> 8) | \ + (((__u64)(x) & (__u64)0x0000ff0000000000ULL) >> 24) | \ + (((__u64)(x) & (__u64)0x00ff000000000000ULL) >> 40) | \ + (((__u64)(x) & (__u64)0xff00000000000000ULL) >> 56))) + +#define ___constant_swahw32(x) ((__u32)( \ + (((__u32)(x) & (__u32)0x0000ffffUL) << 16) | \ + (((__u32)(x) & (__u32)0xffff0000UL) >> 16))) + +#define ___constant_swahb32(x) ((__u32)( \ + (((__u32)(x) & (__u32)0x00ff00ffUL) << 8) | \ + (((__u32)(x) & (__u32)0xff00ff00UL) >> 8))) + +/* + * Implement the following as inlines, but define the interface using + * macros to allow constant folding when possible: + * ___swab16, ___swab32, ___swab64, ___swahw32, ___swahb32 + */ + +static __inline__ __u16 __fswab16(__u16 val) +{ +#if defined (__arch_swab16) + return __arch_swab16(val); +#else + return ___constant_swab16(val); +#endif +} + +static __inline__ __u32 __fswab32(__u32 val) +{ +#if defined(__arch_swab32) + return __arch_swab32(val); +#else + return ___constant_swab32(val); +#endif +} + +static __inline__ __u64 __fswab64(__u64 val) +{ +#if defined (__arch_swab64) + return __arch_swab64(val); +#elif defined(__SWAB_64_THRU_32__) + __u32 h = val >> 32; + __u32 l = val & ((1ULL << 32) - 1); + return (((__u64)__fswab32(l)) << 32) | ((__u64)(__fswab32(h))); +#else + return ___constant_swab64(val); +#endif +} + +static __inline__ __u32 __fswahw32(__u32 val) +{ +#ifdef __arch_swahw32 + return __arch_swahw32(val); +#else + return ___constant_swahw32(val); +#endif +} + +static __inline__ __u32 __fswahb32(__u32 val) +{ +#ifdef __arch_swahb32 + return __arch_swahb32(val); +#else + return ___constant_swahb32(val); +#endif +} + +/** + * __swab16 - return a byteswapped 16-bit value + * @x: value to byteswap + */ +#ifdef __HAVE_BUILTIN_BSWAP16__ +#define __swab16(x) (__u16)__builtin_bswap16((__u16)(x)) +#else +#define __swab16(x) \ + (__u16)(__builtin_constant_p(x) ? \ + ___constant_swab16(x) : \ + __fswab16(x)) +#endif + +/** + * __swab32 - return a byteswapped 32-bit value + * @x: value to byteswap + */ +#ifdef __HAVE_BUILTIN_BSWAP32__ +#define __swab32(x) (__u32)__builtin_bswap32((__u32)(x)) +#else +#define __swab32(x) \ + (__u32)(__builtin_constant_p(x) ? \ + ___constant_swab32(x) : \ + __fswab32(x)) +#endif + +/** + * __swab64 - return a byteswapped 64-bit value + * @x: value to byteswap + */ +#ifdef __HAVE_BUILTIN_BSWAP64__ +#define __swab64(x) (__u64)__builtin_bswap64((__u64)(x)) +#else +#define __swab64(x) \ + (__u64)(__builtin_constant_p(x) ? \ + ___constant_swab64(x) : \ + __fswab64(x)) +#endif + +static __always_inline unsigned long __swab(const unsigned long y) +{ +#if __BITS_PER_LONG == 64 + return __swab64(y); +#else /* __BITS_PER_LONG == 32 */ + return __swab32(y); +#endif +} + +/** + * __swahw32 - return a word-swapped 32-bit value + * @x: value to wordswap + * + * __swahw32(0x12340000) is 0x00001234 + */ +#define __swahw32(x) \ + (__builtin_constant_p((__u32)(x)) ? \ + ___constant_swahw32(x) : \ + __fswahw32(x)) + +/** + * __swahb32 - return a high and low byte-swapped 32-bit value + * @x: value to byteswap + * + * __swahb32(0x12345678) is 0x34127856 + */ +#define __swahb32(x) \ + (__builtin_constant_p((__u32)(x)) ? \ + ___constant_swahb32(x) : \ + __fswahb32(x)) + +/** + * __swab16p - return a byteswapped 16-bit value from a pointer + * @p: pointer to a naturally-aligned 16-bit value + */ +static __always_inline __u16 __swab16p(const __u16 *p) +{ +#ifdef __arch_swab16p + return __arch_swab16p(p); +#else + return __swab16(*p); +#endif +} + +/** + * __swab32p - return a byteswapped 32-bit value from a pointer + * @p: pointer to a naturally-aligned 32-bit value + */ +static __always_inline __u32 __swab32p(const __u32 *p) +{ +#ifdef __arch_swab32p + return __arch_swab32p(p); +#else + return __swab32(*p); +#endif +} + +/** + * __swab64p - return a byteswapped 64-bit value from a pointer + * @p: pointer to a naturally-aligned 64-bit value + */ +static __always_inline __u64 __swab64p(const __u64 *p) +{ +#ifdef __arch_swab64p + return __arch_swab64p(p); +#else + return __swab64(*p); +#endif +} + +/** + * __swahw32p - return a wordswapped 32-bit value from a pointer + * @p: pointer to a naturally-aligned 32-bit value + * + * See __swahw32() for details of wordswapping. + */ +static __inline__ __u32 __swahw32p(const __u32 *p) +{ +#ifdef __arch_swahw32p + return __arch_swahw32p(p); +#else + return __swahw32(*p); +#endif +} + +/** + * __swahb32p - return a high and low byteswapped 32-bit value from a pointer + * @p: pointer to a naturally-aligned 32-bit value + * + * See __swahb32() for details of high/low byteswapping. + */ +static __inline__ __u32 __swahb32p(const __u32 *p) +{ +#ifdef __arch_swahb32p + return __arch_swahb32p(p); +#else + return __swahb32(*p); +#endif +} + +/** + * __swab16s - byteswap a 16-bit value in-place + * @p: pointer to a naturally-aligned 16-bit value + */ +static __inline__ void __swab16s(__u16 *p) +{ +#ifdef __arch_swab16s + __arch_swab16s(p); +#else + *p = __swab16p(p); +#endif +} +/** + * __swab32s - byteswap a 32-bit value in-place + * @p: pointer to a naturally-aligned 32-bit value + */ +static __always_inline void __swab32s(__u32 *p) +{ +#ifdef __arch_swab32s + __arch_swab32s(p); +#else + *p = __swab32p(p); +#endif +} + +/** + * __swab64s - byteswap a 64-bit value in-place + * @p: pointer to a naturally-aligned 64-bit value + */ +static __always_inline void __swab64s(__u64 *p) +{ +#ifdef __arch_swab64s + __arch_swab64s(p); +#else + *p = __swab64p(p); +#endif +} + +/** + * __swahw32s - wordswap a 32-bit value in-place + * @p: pointer to a naturally-aligned 32-bit value + * + * See __swahw32() for details of wordswapping + */ +static __inline__ void __swahw32s(__u32 *p) +{ +#ifdef __arch_swahw32s + __arch_swahw32s(p); +#else + *p = __swahw32p(p); +#endif +} + +/** + * __swahb32s - high and low byteswap a 32-bit value in-place + * @p: pointer to a naturally-aligned 32-bit value + * + * See __swahb32() for details of high and low byte swapping + */ +static __inline__ void __swahb32s(__u32 *p) +{ +#ifdef __arch_swahb32s + __arch_swahb32s(p); +#else + *p = __swahb32p(p); +#endif +} + + +#endif /* _LINUX_SWAB_H */