From 6831bd55164457fd198107c6690a541399592056 Mon Sep 17 00:00:00 2001
From: Andrew Goessling <agoessling@gmail.com>
Date: Sun, 22 Nov 2020 11:19:09 -0800
Subject: [PATCH] Add support for `verilog_module` from `rules_verilog`. (#9)

`verilog_module` provides a concise way to provide
`verilator_cc_library` the verilog sources, dependencies, and top
module name of a verilog module.
---
 README.md                  | 17 +++++++++++------
 test/alu/BUILD             | 19 +++++++++++++++++++
 verilator/defs.bzl         | 24 +++++++++++++++++-------
 verilator/repositories.bzl |  7 +++++++
 4 files changed, 54 insertions(+), 13 deletions(-)

diff --git a/README.md b/README.md
index a2b9e53..f5b0c80 100644
--- a/README.md
+++ b/README.md
@@ -56,23 +56,28 @@ cc_binary(
 )
 ```
 
-Verilog libraries can also be specifed as dependencies
+The details of a verilog module (sources, top name, etc.) can also be specified by a `verilog_module`
+which can be reused in other rules.
 
 ```python
-load("@rules_verilator//verilator:defs.bzl", "sv_library", "verilator_cc_library")
+load("@rules_verilog//verilog:defs.bzl", "verilog_module")
 
-sv_library(
-    name = "alu_lib",
+load("@rules_verilator//verilator:defs.bzl", "verilator_cc_library")
+
+verilog_module(
+    name = "alu_module",
+    top = "alu",
     srcs = ["alu.sv"],
 )
 
 verilator_cc_library(
     name = "alu",
-    mtop = "alu",
-    deps = [":alu_lib"],
+    module = ":alu_module",
 )
 ```
 
+See [test/alu/BUILD](test/alu/BUILD) for working examples.
+
 ## License
 
 Released under Apache 2.0.
diff --git a/test/alu/BUILD b/test/alu/BUILD
index e956697..1774016 100644
--- a/test/alu/BUILD
+++ b/test/alu/BUILD
@@ -1,3 +1,5 @@
+load("@rules_verilog//verilog:defs.bzl", "verilog_module")
+
 load("@rules_verilator//verilator:defs.bzl", "sv_library", "verilator_cc_library")
 
 sv_library(
@@ -16,3 +18,20 @@ cc_binary(
     srcs = ["alu.cpp"],
     deps = [":alu"],
 )
+
+verilog_module(
+    name = "alu_module",
+    top = "alu",
+    srcs = ["alu.sv"],
+)
+
+verilator_cc_library(
+    name = "alu_with_module",
+    module = ":alu_module",
+)
+
+cc_binary(
+    name = "alu_bin_with_module",
+    srcs = ["alu.cpp"],
+    deps = [":alu_with_module"],
+)
diff --git a/verilator/defs.bzl b/verilator/defs.bzl
index 7c7f371..7de461e 100644
--- a/verilator/defs.bzl
+++ b/verilator/defs.bzl
@@ -1,3 +1,5 @@
+load("@rules_verilog//verilog:defs.bzl", "VerilogModuleInfo")
+
 load(
     "@rules_verilator//verilator/internal:cc_actions.bzl",
     "cc_compile_and_link_static_library",
@@ -80,14 +82,18 @@ def _verilator_cc_library(ctx):
     verilator_toolchain = ctx.toolchains[_TOOLCHAIN_TYPE].verilator_toolchain
 
     # Gather all the Verilog source files, including transitive dependencies
+    module_srcs = ctx.attr.module[VerilogModuleInfo].files.to_list() if ctx.attr.module else []
     srcs = get_transitive_sources(
-        ctx.files.srcs + ctx.files.hdrs,
+        ctx.files.srcs + ctx.files.hdrs + module_srcs,
         ctx.attr.deps,
     )
 
     # Default Verilator output prefix (e.g. "Vtop")
-    mtop = ctx.label.name if not ctx.attr.mtop else ctx.attr.mtop
-    prefix = ctx.attr.prefix + ctx.attr.mtop
+    if ctx.attr.module:
+      mtop = ctx.attr.module[VerilogModuleInfo].top
+    else:
+      mtop = ctx.label.name if not ctx.attr.mtop else ctx.attr.mtop
+    prefix = ctx.attr.prefix + mtop
 
     # Output directories/files
     verilator_output = ctx.actions.declare_directory(ctx.label.name + "-gen")
@@ -155,21 +161,25 @@ verilator_cc_library = rule(
     _verilator_cc_library,
     attrs = {
         "srcs": attr.label_list(
-            doc = "List of verilog source files",
+            doc = "[Deprecated] List of verilog source files",
             mandatory = False,
             allow_files = [".v", ".sv"],
         ),
         "hdrs": attr.label_list(
-            doc = "List of verilog header files",
+            doc = "[Deprecated] List of verilog header files",
             allow_files = [".v", ".sv", ".vh", ".svh"],
         ),
         "deps": attr.label_list(
-            doc = "List of verilog and C++ dependencies",
+            doc = "[Deprectated] List of verilog dependencies",
         ),
         "mtop": attr.string(
-            doc = "Top level module. Defaults to the rule name if not specified",
+            doc = "[Deprecated] Top level module. Defaults to the rule name if not specified",
             mandatory = False,
         ),
+        "module": attr.label(
+            doc = "Label of verilog_module to verilate",
+            providers = [VerilogModuleInfo],
+        ),
         "trace": attr.bool(
             doc = "Enable tracing for Verilator",
             default = False,
diff --git a/verilator/repositories.bzl b/verilator/repositories.bzl
index 9d00ef9..785c7cc 100644
--- a/verilator/repositories.bzl
+++ b/verilator/repositories.bzl
@@ -62,6 +62,13 @@ def rules_verilator_dependencies(version = _DEFAULT_VERSION):
         urls = ["https://github.com/jmillikin/rules_bison/releases/download/v0.1/rules_bison-v0.1.tar.xz"],
         sha256 = "5c57552a129b0d8eeb9252341ee975ec2720c35baf2f0d154756310c1ff572a0",
     )
+    _maybe(
+        http_archive,
+        name = "rules_verilog",
+        urls = ["https://github.com/agoessling/rules_verilog/archive/v0.1.0.zip"],
+        strip_prefix = "rules_verilog-0.1.0",
+        sha256 = "401b3f591f296f6fd2f6656f01afc1f93111e10b81b9a9d291f9c04b3e4a3e8b",
+    )
 
 def rules_verilator_toolchains(version = _DEFAULT_VERSION):
     repo_name = "verilator_v{version}".format(version = version)