diff --git a/devices/common/patches/MediaTek-ethernet-phy.patch b/devices/common/patches/MediaTek-ethernet-phy.patch new file mode 100644 index 000000000000..a34dca81d063 --- /dev/null +++ b/devices/common/patches/MediaTek-ethernet-phy.patch @@ -0,0 +1,675 @@ +From 529f60c8ca3d6e0168d24ee2671f257384877430 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Tue, 8 Oct 2024 19:33:49 +0100 +Subject: [PATCH] mediatek: update MediaTek PHY patchset + +The previous iteration of MediaTek's PHY patches caused various weird bugs. +Drop culprit patch 733-10-net-phy-mediatek-Extend-1G-TX-RX-link-pulse-time.patch +and use the most recent iteration of the patchset which has been posted to the +netdev mailing list. + +Link: https://patchwork.kernel.org/project/netdevbpf/list/?series=895513&state=* +Fixes: #16448 +Signed-off-by: Daniel Golle +--- + ...-Re-organize-MediaTek-ethernet-phy-d.patch | 13 +- + ...-Fix-spelling-errors-and-rearrange-v.patch | 6 +- + ...-Move-LED-helper-functions-into-mtk-.patch | 8 +- + ...-Improve-readability-of-mtk-phy-lib..patch | 6 +- + ...-Integrate-read-write-page-helper-fu.patch | 6 +- + ...-Hook-LED-helper-functions-in-mtk-ge.patch | 23 +- + ...ek-add-MT7530-MT7531-s-PHY-ID-macros.patch | 6 +- + ...ek-Change-mtk-ge-soc.c-line-wrapping.patch | 6 +- + ...-Add-token-ring-access-helper-functi.patch | 6 +- + ...atek-Extend-1G-TX-RX-link-pulse-time.patch | 219 ------------------ + ...er-for-built-in-2.5G-ethernet-PHY-on.patch | 6 +- + ...-Fix-alignment-in-callback-functions.patch | 130 ----------- + ...-Remove-unnecessary-outer-parens-of-.patch | 65 ------ + 13 files changed, 45 insertions(+), 455 deletions(-) + delete mode 100644 target/linux/mediatek/patches-6.6/733-10-net-phy-mediatek-Extend-1G-TX-RX-link-pulse-time.patch + delete mode 100644 target/linux/mediatek/patches-6.6/733-12-net-phy-mediatek-Fix-alignment-in-callback-functions.patch + delete mode 100644 target/linux/mediatek/patches-6.6/733-13-net-phy-mediatek-Remove-unnecessary-outer-parens-of-.patch + +diff --git a/target/linux/mediatek/patches-6.6/733-01-net-phy-mediatek-Re-organize-MediaTek-ethernet-phy-d.patch b/target/linux/mediatek/patches-6.6/733-01-net-phy-mediatek-Re-organize-MediaTek-ethernet-phy-d.patch +index 3ec756bb4b0ace..cf8e5cd38a9192 100644 +--- a/target/linux/mediatek/patches-6.6/733-01-net-phy-mediatek-Re-organize-MediaTek-ethernet-phy-d.patch ++++ b/target/linux/mediatek/patches-6.6/733-01-net-phy-mediatek-Re-organize-MediaTek-ethernet-phy-d.patch +@@ -1,14 +1,15 @@ +-From c14e7c954fd752fbb3da17a8bcf65cd9dbf41186 Mon Sep 17 00:00:00 2001 ++From 656f5fdeb6ee6fa95c28cab3b535e2e09ef59c57 Mon Sep 17 00:00:00 2001 + From: "SkyLake.Huang" +-Date: Mon, 1 Jul 2024 18:54:05 +0800 +-Subject: [PATCH 01/13] net: phy: mediatek: Re-organize MediaTek ethernet phy ++Date: Fri, 4 Oct 2024 18:24:05 +0800 ++Subject: [PATCH 1/9] net: phy: mediatek: Re-organize MediaTek ethernet phy + drivers + + Re-organize MediaTek ethernet phy driver files and get ready to integrate +-some common functions and add new 2.5G phy driver. ++some common functions (and add new 2.5G phy driver). + mtk-ge.c: MT7530 Gphy on MT7621 & MT7531 Gphy + mtk-ge-soc.c: Built-in Gphy on MT7981 & Built-in switch Gphy on MT7988 +-mtk-2p5ge.c: Planned for built-in 2.5G phy on MT7988 ++(mtk-2p5ge.c: Planned for built-in 2.5G phy on MT7988 ++ --> in another patchset) + + Signed-off-by: SkyLake.Huang + --- +@@ -18,7 +19,7 @@ Signed-off-by: SkyLake.Huang + drivers/net/phy/mediatek/Makefile | 3 +++ + .../mtk-ge-soc.c} | 0 + .../phy/{mediatek-ge.c => mediatek/mtk-ge.c} | 0 +- 7 files changed, 29 insertions(+), 20 deletions(-) ++ 6 files changed, 27 insertions(+), 18 deletions(-) + create mode 100644 drivers/net/phy/mediatek/Kconfig + create mode 100644 drivers/net/phy/mediatek/Makefile + rename drivers/net/phy/{mediatek-ge-soc.c => mediatek/mtk-ge-soc.c} (100%) +diff --git a/target/linux/mediatek/patches-6.6/733-02-net-phy-mediatek-Fix-spelling-errors-and-rearrange-v.patch b/target/linux/mediatek/patches-6.6/733-02-net-phy-mediatek-Fix-spelling-errors-and-rearrange-v.patch +index 901949fe9f2ff0..ed68e97dbbef57 100644 +--- a/target/linux/mediatek/patches-6.6/733-02-net-phy-mediatek-Fix-spelling-errors-and-rearrange-v.patch ++++ b/target/linux/mediatek/patches-6.6/733-02-net-phy-mediatek-Fix-spelling-errors-and-rearrange-v.patch +@@ -1,7 +1,7 @@ +-From 12054d38fc55adbfa2b40299ad8af3449d882ee2 Mon Sep 17 00:00:00 2001 ++From 61bcabdb69418215ea05bdc48cb88459d757f505 Mon Sep 17 00:00:00 2001 + From: "SkyLake.Huang" +-Date: Mon, 1 Jul 2024 18:54:06 +0800 +-Subject: [PATCH 02/13] net: phy: mediatek: Fix spelling errors and rearrange ++Date: Fri, 4 Oct 2024 18:24:06 +0800 ++Subject: [PATCH 2/9] net: phy: mediatek: Fix spelling errors and rearrange + variables + + This patch fixes spelling errors which comes from mediatek-ge-soc.c and +diff --git a/target/linux/mediatek/patches-6.6/733-03-net-phy-mediatek-Move-LED-helper-functions-into-mtk-.patch b/target/linux/mediatek/patches-6.6/733-03-net-phy-mediatek-Move-LED-helper-functions-into-mtk-.patch +index 9e6ae4b1360baf..61bde761f0ed0c 100644 +--- a/target/linux/mediatek/patches-6.6/733-03-net-phy-mediatek-Move-LED-helper-functions-into-mtk-.patch ++++ b/target/linux/mediatek/patches-6.6/733-03-net-phy-mediatek-Move-LED-helper-functions-into-mtk-.patch +@@ -1,7 +1,7 @@ +-From 434e41555c45ec10b19320024163bb009da168bc Mon Sep 17 00:00:00 2001 ++From 16bbd4ecb67ec1899ad8aa1eb1219a6d576cbaaf Mon Sep 17 00:00:00 2001 + From: "SkyLake.Huang" +-Date: Mon, 1 Jul 2024 18:54:07 +0800 +-Subject: [PATCH 03/13] net: phy: mediatek: Move LED helper functions into mtk ++Date: Fri, 4 Oct 2024 18:24:07 +0800 ++Subject: [PATCH 3/9] net: phy: mediatek: Move LED helper functions into mtk + phy lib + + This patch creates mtk-phy-lib.c & mtk-phy.h and integrates mtk-ge-soc.c's +@@ -15,7 +15,7 @@ Signed-off-by: SkyLake.Huang + drivers/net/phy/mediatek/mtk-ge-soc.c | 262 +++---------------------- + drivers/net/phy/mediatek/mtk-phy-lib.c | 251 +++++++++++++++++++++++ + drivers/net/phy/mediatek/mtk.h | 82 ++++++++ +- 6 files changed, 368 insertions(+), 235 deletions(-) ++ 5 files changed, 366 insertions(+), 235 deletions(-) + create mode 100644 drivers/net/phy/mediatek/mtk-phy-lib.c + create mode 100644 drivers/net/phy/mediatek/mtk.h + +diff --git a/target/linux/mediatek/patches-6.6/733-04-net-phy-mediatek-Improve-readability-of-mtk-phy-lib..patch b/target/linux/mediatek/patches-6.6/733-04-net-phy-mediatek-Improve-readability-of-mtk-phy-lib..patch +index 717dc890e3fa1e..78413d28ead78f 100644 +--- a/target/linux/mediatek/patches-6.6/733-04-net-phy-mediatek-Improve-readability-of-mtk-phy-lib..patch ++++ b/target/linux/mediatek/patches-6.6/733-04-net-phy-mediatek-Improve-readability-of-mtk-phy-lib..patch +@@ -1,7 +1,7 @@ +-From 2783929879854d5750ba82e2e203663313362abb Mon Sep 17 00:00:00 2001 ++From 2b118202583eb05a1799d435d2dce974dc3f5b16 Mon Sep 17 00:00:00 2001 + From: "SkyLake.Huang" +-Date: Mon, 1 Jul 2024 18:54:08 +0800 +-Subject: [PATCH 04/13] net: phy: mediatek: Improve readability of ++Date: Fri, 4 Oct 2024 18:24:08 +0800 ++Subject: [PATCH 4/9] net: phy: mediatek: Improve readability of + mtk-phy-lib.c's mtk_phy_led_hw_ctrl_set() + + This patch removes parens around TRIGGER_NETDEV_RX/TRIGGER_NETDEV_TX in +diff --git a/target/linux/mediatek/patches-6.6/733-05-net-phy-mediatek-Integrate-read-write-page-helper-fu.patch b/target/linux/mediatek/patches-6.6/733-05-net-phy-mediatek-Integrate-read-write-page-helper-fu.patch +index 4a112a202c99aa..9dd9f7d99dade4 100644 +--- a/target/linux/mediatek/patches-6.6/733-05-net-phy-mediatek-Integrate-read-write-page-helper-fu.patch ++++ b/target/linux/mediatek/patches-6.6/733-05-net-phy-mediatek-Integrate-read-write-page-helper-fu.patch +@@ -1,7 +1,7 @@ +-From 58c1270423ab48464cdc31ef71ffe7f5b2441961 Mon Sep 17 00:00:00 2001 ++From 59e7082cb8c8e89bceb44cc60df156d818c8da96 Mon Sep 17 00:00:00 2001 + From: "SkyLake.Huang" +-Date: Mon, 1 Jul 2024 18:54:09 +0800 +-Subject: [PATCH 05/13] net: phy: mediatek: Integrate read/write page helper ++Date: Fri, 4 Oct 2024 18:24:09 +0800 ++Subject: [PATCH 5/9] net: phy: mediatek: Integrate read/write page helper + functions + + This patch integrates read/write page helper functions as MTK phy lib. +diff --git a/target/linux/mediatek/patches-6.6/733-06-net-phy-mediatek-Hook-LED-helper-functions-in-mtk-ge.patch b/target/linux/mediatek/patches-6.6/733-06-net-phy-mediatek-Hook-LED-helper-functions-in-mtk-ge.patch +index 485e2621340a05..9f6dac9431b363 100644 +--- a/target/linux/mediatek/patches-6.6/733-06-net-phy-mediatek-Hook-LED-helper-functions-in-mtk-ge.patch ++++ b/target/linux/mediatek/patches-6.6/733-06-net-phy-mediatek-Hook-LED-helper-functions-in-mtk-ge.patch +@@ -1,8 +1,7 @@ +-From 9403f1d54598ae56386a8bf47a5b6b34c884e4f5 Mon Sep 17 00:00:00 2001 ++From 5b605457b93d0979ab623ef2aa6eb456c46e511c Mon Sep 17 00:00:00 2001 + From: "SkyLake.Huang" +-Date: Mon, 1 Jul 2024 18:54:10 +0800 +-Subject: [PATCH 06/13] net: phy: mediatek: Hook LED helper functions in +- mtk-ge.c ++Date: Fri, 4 Oct 2024 18:24:10 +0800 ++Subject: [PATCH 6/9] net: phy: mediatek: Hook LED helper functions in mtk-ge.c + + We have mtk-phy-lib.c now so that we can use LED helper functions in + mtk-ge.c(mt7531 part). It also means that mt7531/mt7981/mt7988's +@@ -83,14 +82,14 @@ Signed-off-by: SkyLake.Huang + +} + + + +static const unsigned long supported_triggers = +-+ (BIT(TRIGGER_NETDEV_FULL_DUPLEX) | +-+ BIT(TRIGGER_NETDEV_HALF_DUPLEX) | +-+ BIT(TRIGGER_NETDEV_LINK) | +-+ BIT(TRIGGER_NETDEV_LINK_10) | +-+ BIT(TRIGGER_NETDEV_LINK_100) | +-+ BIT(TRIGGER_NETDEV_LINK_1000) | +-+ BIT(TRIGGER_NETDEV_RX) | +-+ BIT(TRIGGER_NETDEV_TX)); +++ BIT(TRIGGER_NETDEV_FULL_DUPLEX) | +++ BIT(TRIGGER_NETDEV_HALF_DUPLEX) | +++ BIT(TRIGGER_NETDEV_LINK) | +++ BIT(TRIGGER_NETDEV_LINK_10) | +++ BIT(TRIGGER_NETDEV_LINK_100) | +++ BIT(TRIGGER_NETDEV_LINK_1000) | +++ BIT(TRIGGER_NETDEV_RX) | +++ BIT(TRIGGER_NETDEV_TX); + + + +static int mt753x_phy_led_hw_is_supported(struct phy_device *phydev, u8 index, + + unsigned long rules) +diff --git a/target/linux/mediatek/patches-6.6/733-07-net-phy-mediatek-add-MT7530-MT7531-s-PHY-ID-macros.patch b/target/linux/mediatek/patches-6.6/733-07-net-phy-mediatek-add-MT7530-MT7531-s-PHY-ID-macros.patch +index bfdf864f8d5cc5..7ea81612e3c869 100644 +--- a/target/linux/mediatek/patches-6.6/733-07-net-phy-mediatek-add-MT7530-MT7531-s-PHY-ID-macros.patch ++++ b/target/linux/mediatek/patches-6.6/733-07-net-phy-mediatek-add-MT7530-MT7531-s-PHY-ID-macros.patch +@@ -1,7 +1,7 @@ +-From 51ee83602dbb84716180d9b6e43f6bebb0c2d7bd Mon Sep 17 00:00:00 2001 ++From c5ff7bece642dbba601be89e70f78ff037ca084f Mon Sep 17 00:00:00 2001 + From: "SkyLake.Huang" +-Date: Mon, 1 Jul 2024 18:54:11 +0800 +-Subject: [PATCH 07/13] net: phy: mediatek: add MT7530 & MT7531's PHY ID macros ++Date: Fri, 4 Oct 2024 18:24:11 +0800 ++Subject: [PATCH 7/9] net: phy: mediatek: add MT7530 & MT7531's PHY ID macros + + This patch adds MT7530 & MT7531's PHY ID macros in mtk-ge.c so that + it follows the same rule of mtk-ge-soc.c. +diff --git a/target/linux/mediatek/patches-6.6/733-08-net-phy-mediatek-Change-mtk-ge-soc.c-line-wrapping.patch b/target/linux/mediatek/patches-6.6/733-08-net-phy-mediatek-Change-mtk-ge-soc.c-line-wrapping.patch +index ca155e50127c89..8cb2b549e5b56e 100644 +--- a/target/linux/mediatek/patches-6.6/733-08-net-phy-mediatek-Change-mtk-ge-soc.c-line-wrapping.patch ++++ b/target/linux/mediatek/patches-6.6/733-08-net-phy-mediatek-Change-mtk-ge-soc.c-line-wrapping.patch +@@ -1,7 +1,7 @@ +-From e73df692396b0d6bdcb2317299fa1e8e547f3446 Mon Sep 17 00:00:00 2001 ++From dbe70a9353b5095a90af61a051486484765ada6f Mon Sep 17 00:00:00 2001 + From: "SkyLake.Huang" +-Date: Mon, 1 Jul 2024 18:54:12 +0800 +-Subject: [PATCH 08/13] net: phy: mediatek: Change mtk-ge-soc.c line wrapping ++Date: Fri, 4 Oct 2024 18:24:12 +0800 ++Subject: [PATCH 8/9] net: phy: mediatek: Change mtk-ge-soc.c line wrapping + + This patch shrinks mtk-ge-soc.c line wrapping to 80 characters. + +diff --git a/target/linux/mediatek/patches-6.6/733-09-net-phy-mediatek-Add-token-ring-access-helper-functi.patch b/target/linux/mediatek/patches-6.6/733-09-net-phy-mediatek-Add-token-ring-access-helper-functi.patch +index 49e4c2057fc95b..62c063462b90c1 100644 +--- a/target/linux/mediatek/patches-6.6/733-09-net-phy-mediatek-Add-token-ring-access-helper-functi.patch ++++ b/target/linux/mediatek/patches-6.6/733-09-net-phy-mediatek-Add-token-ring-access-helper-functi.patch +@@ -1,7 +1,7 @@ +-From 60228de48d8bfde62b4db5945314e6a62079f091 Mon Sep 17 00:00:00 2001 ++From ca024bc7267a8c0439325d352f9b8818ba0f2cf0 Mon Sep 17 00:00:00 2001 + From: "SkyLake.Huang" +-Date: Mon, 1 Jul 2024 18:54:13 +0800 +-Subject: [PATCH 09/13] net: phy: mediatek: Add token ring access helper ++Date: Fri, 4 Oct 2024 18:24:13 +0800 ++Subject: [PATCH 9/9] net: phy: mediatek: Add token ring access helper + functions in mtk-phy-lib + + This patch adds TR(token ring) manipulations and adds correct +diff --git a/target/linux/mediatek/patches-6.6/733-10-net-phy-mediatek-Extend-1G-TX-RX-link-pulse-time.patch b/target/linux/mediatek/patches-6.6/733-10-net-phy-mediatek-Extend-1G-TX-RX-link-pulse-time.patch +deleted file mode 100644 +index 2fc1adb5ec1229..00000000000000 +--- a/target/linux/mediatek/patches-6.6/733-10-net-phy-mediatek-Extend-1G-TX-RX-link-pulse-time.patch ++++ /dev/null +@@ -1,219 +0,0 @@ +-From 3c05195fc2c232cd853fc8cebf55310c4605111d Mon Sep 17 00:00:00 2001 +-From: "SkyLake.Huang" +-Date: Mon, 1 Jul 2024 18:54:14 +0800 +-Subject: [PATCH 10/13] net: phy: mediatek: Extend 1G TX/RX link pulse time +- +-We observe that some 10G devices' (mostly Marvell's chips inside) 1G +-training time violates specification, which may last 2230ms and affect +-later TX/RX link pulse time. This will invalidate MediaTek series +-gigabit Ethernet PHYs' hardware auto downshift mechanism. +- +-Without this patch, if someone is trying to use "4-wire" cable to +-connect above devices, MediaTek' gigabit Ethernet PHYs may fail +-to downshift to 100Mbps. (If partner 10G devices' downshift mechanism +-stops at 1G) +- +-This patch extends our 1G TX/RX link pulse time so that we can still +-link up with those 10G devices. +- +-Tested device: +-- Netgear GS110EMX's 10G port (Marvell 88X3340P) +-- QNAP QSW-M408-4C +- +-Signed-off-by: SkyLake.Huang +---- +- drivers/net/phy/mediatek/mtk-ge-soc.c | 2 + +- drivers/net/phy/mediatek/mtk-ge.c | 5 +- +- drivers/net/phy/mediatek/mtk-phy-lib.c | 92 ++++++++++++++++++++++++++ +- drivers/net/phy/mediatek/mtk.h | 21 ++++++ +- 4 files changed, 116 insertions(+), 4 deletions(-) +- +---- a/drivers/net/phy/mediatek/mtk-ge-soc.c +-+++ b/drivers/net/phy/mediatek/mtk-ge-soc.c +-@@ -1396,6 +1396,7 @@ static struct phy_driver mtk_socphy_driv +- PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981), +- .name = "MediaTek MT7981 PHY", +- .config_init = mt798x_phy_config_init, +-+ .read_status = mtk_gphy_cl22_read_status, +- .config_intr = genphy_no_config_intr, +- .handle_interrupt = genphy_handle_interrupt_no_ack, +- .probe = mt7981_phy_probe, +-@@ -1413,6 +1414,7 @@ static struct phy_driver mtk_socphy_driv +- PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988), +- .name = "MediaTek MT7988 PHY", +- .config_init = mt798x_phy_config_init, +-+ .read_status = mtk_gphy_cl22_read_status, +- .config_intr = genphy_no_config_intr, +- .handle_interrupt = genphy_handle_interrupt_no_ack, +- .probe = mt7988_phy_probe, +---- a/drivers/net/phy/mediatek/mtk-ge.c +-+++ b/drivers/net/phy/mediatek/mtk-ge.c +-@@ -9,10 +9,6 @@ +- #define MTK_GPHY_ID_MT7530 0x03a29412 +- #define MTK_GPHY_ID_MT7531 0x03a29441 +- +--#define MTK_PHY_PAGE_EXTENDED_1 0x0001 +--#define MTK_PHY_AUX_CTRL_AND_STATUS 0x14 +--#define MTK_PHY_ENABLE_DOWNSHIFT BIT(4) +-- +- #define MTK_PHY_PAGE_EXTENDED_2 0x0002 +- #define MTK_PHY_PAGE_EXTENDED_3 0x0003 +- #define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG11 0x11 +-@@ -251,6 +247,7 @@ static struct phy_driver mtk_gephy_drive +- .name = "MediaTek MT7531 PHY", +- .probe = mt7531_phy_probe, +- .config_init = mt7531_phy_config_init, +-+ .read_status = mtk_gphy_cl22_read_status, +- /* Interrupts are handled by the switch, not the PHY +- * itself. +- */ +---- a/drivers/net/phy/mediatek/mtk-phy-lib.c +-+++ b/drivers/net/phy/mediatek/mtk-phy-lib.c +-@@ -109,6 +109,108 @@ int mtk_phy_write_page(struct phy_device +- } +- EXPORT_SYMBOL_GPL(mtk_phy_write_page); +- +-+/* This function deals with the case that 1G AN starts but isn't completed. We +-+ * set AN_NEW_LP_CNT_LIMIT with different values time after time to let our +-+ * 1G->100Mbps hardware automatic downshift to fit more partner devices. +-+ */ +-+static int extend_an_new_lp_cnt_limit(struct phy_device *phydev) +-+{ +-+ int ret; +-+ u32 reg_val; +-+ int timeout; +-+ +-+ /* According to table 28-9 & Figure 28-18 in IEEE 802.3, +-+ * link_fail_inhibit_timer of 10/100/1000 Mbps devices ranges from 750 +-+ * to "1000ms". Once MTK_PHY_FINAL_SPEED_1000 is set, it means that we +-+ * enter "FLP LINK GOOD CHECK" state, link_fail_inhibit_timer starts and +-+ * this PHY's 1G training starts. If 1G training never starts, we do +-+ * nothing but leave. +-+ */ +-+ timeout = read_poll_timeout(ret = phy_read_mmd, reg_val, +-+ (ret < 0) || +-+ reg_val & MTK_PHY_FINAL_SPEED_1000, +-+ 10000, 500000, false, phydev, +-+ MDIO_MMD_VEND1, MTK_PHY_LINK_STATUS_MISC); +-+ phydev_dbg(phydev, "%s: Training Indicator: 0x%x\n", __func__, reg_val); +-+ if (ret < 0) +-+ return ret; +-+ +-+ if (!timeout) { +-+ /* Once we found MTK_PHY_FINAL_SPEED_1000 is set, no matter 1G +-+ * AN is completed or not, we'll set AN_NEW_LP_CNT_LIMIT again +-+ * and again. +-+ */ +-+ mtk_tr_modify(phydev, 0x0, 0xf, 0x3c, AN_NEW_LP_CNT_LIMIT_MASK, +-+ FIELD_PREP(AN_NEW_LP_CNT_LIMIT_MASK, 0xf)); +-+ msleep(1500); +-+ +-+ /* Read phy status again to make sure the following step won't +-+ * affect normal devices. +-+ */ +-+ ret = genphy_read_status(phydev); +-+ if (ret) +-+ return ret; +-+ if (phydev->link) +-+ return 0; +-+ +-+ timeout = read_poll_timeout(mtk_tr_read, reg_val, +-+ (reg_val & AN_STATE_MASK) != +-+ (AN_STATE_TX_DISABLE << +-+ AN_STATE_SHIFT), +-+ 10000, 1000000, false, phydev, +-+ 0x0, 0xf, 0x2); +-+ phydev_dbg(phydev, "%s: AN State: 0x%x\n", __func__, reg_val); +-+ if (!timeout) { +-+ msleep(625); +-+ mtk_tr_modify(phydev, 0x0, 0xf, 0x3c, +-+ AN_NEW_LP_CNT_LIMIT_MASK, +-+ FIELD_PREP(AN_NEW_LP_CNT_LIMIT_MASK, +-+ 0x8)); +-+ msleep(500); +-+ mtk_tr_modify(phydev, 0x0, 0xf, 0x3c, +-+ AN_NEW_LP_CNT_LIMIT_MASK, +-+ FIELD_PREP(AN_NEW_LP_CNT_LIMIT_MASK, +-+ 0xf)); +-+ } +-+ } +-+ +-+ return 0; +-+} +-+ +-+int mtk_gphy_cl22_read_status(struct phy_device *phydev) +-+{ +-+ int ret; +-+ +-+ ret = genphy_read_status(phydev); +-+ if (ret) +-+ return ret; +-+ +-+ if (phydev->autoneg == AUTONEG_ENABLE && !phydev->autoneg_complete) { +-+ ret = phy_read_paged(phydev, MTK_PHY_PAGE_EXTENDED_1, +-+ MTK_PHY_AUX_CTRL_AND_STATUS); +-+ if (ret < 0) +-+ return ret; +-+ +-+ /* Once LP_DETECTED is set, it means that"ability_match" in +-+ * IEEE 802.3 Figure 28-18 is set. This happens after we plug in +-+ * cable. Also, LP_DETECTED will be cleared after AN complete. +-+ */ +-+ if (!FIELD_GET(MTK_PHY_LP_DETECTED_MASK, ret)) +-+ return 0; +-+ +-+ ret = phy_read(phydev, MII_CTRL1000); +-+ if (ret & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) { +-+ ret = extend_an_new_lp_cnt_limit(phydev); +-+ phydev_dbg(phydev, "%s: counter limit ret: %d\n", __func__, ret); +-+ if (ret < 0) +-+ return ret; +-+ } +-+ } +-+ +-+ return 0; +-+} +-+EXPORT_SYMBOL_GPL(mtk_gphy_cl22_read_status); +-+ +- int mtk_phy_led_hw_is_supported(struct phy_device *phydev, u8 index, +- unsigned long rules, +- unsigned long supported_triggers) +---- a/drivers/net/phy/mediatek/mtk.h +-+++ b/drivers/net/phy/mediatek/mtk.h +-@@ -10,8 +10,28 @@ +- +- #define MTK_EXT_PAGE_ACCESS 0x1f +- #define MTK_PHY_PAGE_STANDARD 0x0000 +-+#define MTK_PHY_PAGE_EXTENDED_1 0x0001 +-+#define MTK_PHY_AUX_CTRL_AND_STATUS 0x14 +-+/* suprv_media_select_RefClk */ +-+#define MTK_PHY_LP_DETECTED_MASK GENMASK(7, 6) +-+#define MTK_PHY_ENABLE_DOWNSHIFT BIT(4) +-+ +- #define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5 +- +-+/* Registers on Token Ring debug nodes */ +-+/* ch_addr = 0x0, node_addr = 0xf, data_addr = 0x2 */ +-+#define AN_STATE_MASK GENMASK(22, 19) +-+#define AN_STATE_SHIFT 19 +-+#define AN_STATE_TX_DISABLE 1 +-+ +-+/* ch_addr = 0x0, node_addr = 0xf, data_addr = 0x3c */ +-+#define AN_NEW_LP_CNT_LIMIT_MASK GENMASK(23, 20) +-+#define AUTO_NP_10XEN BIT(6) +-+ +-+/* Registers on MDIO_MMD_VEND1 */ +-+#define MTK_PHY_LINK_STATUS_MISC (0xa2) +-+#define MTK_PHY_FINAL_SPEED_1000 BIT(3) +-+ +- /* Registers on MDIO_MMD_VEND2 */ +- #define MTK_PHY_LED0_ON_CTRL 0x24 +- #define MTK_PHY_LED1_ON_CTRL 0x26 +-@@ -78,6 +98,7 @@ void __mtk_tr_clr_bits(struct phy_device +- int mtk_phy_read_page(struct phy_device *phydev); +- int mtk_phy_write_page(struct phy_device *phydev, int page); +- +-+int mtk_gphy_cl22_read_status(struct phy_device *phydev); +- int mtk_phy_led_hw_is_supported(struct phy_device *phydev, u8 index, +- unsigned long rules, +- unsigned long supported_triggers); +diff --git a/target/linux/mediatek/patches-6.6/733-11-net-phy-add-driver-for-built-in-2.5G-ethernet-PHY-on.patch b/target/linux/mediatek/patches-6.6/733-11-net-phy-add-driver-for-built-in-2.5G-ethernet-PHY-on.patch +index a9595157ffbd82..2548e789f065f4 100644 +--- a/target/linux/mediatek/patches-6.6/733-11-net-phy-add-driver-for-built-in-2.5G-ethernet-PHY-on.patch ++++ b/target/linux/mediatek/patches-6.6/733-11-net-phy-add-driver-for-built-in-2.5G-ethernet-PHY-on.patch +@@ -42,7 +42,7 @@ Signed-off-by: SkyLake.Huang + +obj-$(CONFIG_MEDIATEK_2P5GE_PHY) += mtk-2p5ge.o + --- /dev/null + +++ b/drivers/net/phy/mediatek/mtk-2p5ge.c +-@@ -0,0 +1,432 @@ ++@@ -0,0 +1,436 @@ + +// SPDX-License-Identifier: GPL-2.0+ + +#include + +#include +@@ -59,6 +59,10 @@ Signed-off-by: SkyLake.Huang + + + +#define MTK_2P5GPHY_ID_MT7988 (0x00339c11) + + +++#define MTK_PHY_PAGE_EXTENDED_1 0x0001 +++#define MTK_PHY_AUX_CTRL_AND_STATUS 0x14 +++#define MTK_PHY_ENABLE_DOWNSHIFT BIT(4) +++ + +#define MT7988_2P5GE_PMB_FW "mediatek/mt7988/i2p5ge-phy-pmb.bin" + +#define MT7988_2P5GE_PMB_FW_SIZE (0x20000) + +#define MT7988_2P5GE_PMB_FW_BASE (0x0f100000) +diff --git a/target/linux/mediatek/patches-6.6/733-12-net-phy-mediatek-Fix-alignment-in-callback-functions.patch b/target/linux/mediatek/patches-6.6/733-12-net-phy-mediatek-Fix-alignment-in-callback-functions.patch +deleted file mode 100644 +index 8657886138eca3..00000000000000 +--- a/target/linux/mediatek/patches-6.6/733-12-net-phy-mediatek-Fix-alignment-in-callback-functions.patch ++++ /dev/null +@@ -1,130 +0,0 @@ +-From 07e90eb1819319a0c34b0cf3a57a4a3878e96e4d Mon Sep 17 00:00:00 2001 +-From: "SkyLake.Huang" +-Date: Mon, 1 Jul 2024 18:54:16 +0800 +-Subject: [PATCH 12/13] net: phy: mediatek: Fix alignment in callback +- functions' hook +- +-Align declarations in mtk_gephy_driver(mtk-ge.c) and +-mtk_socphy_driver(mtk-ge-soc.c). At first, some of them are +-".foo= method_foo", and others are ".bar= method_bar". +-Use space instead for all of them here in case line is longer than +-80 chars. +- +-Signed-off-by: SkyLake.Huang +---- +- drivers/net/phy/mediatek/mtk-ge-soc.c | 40 +++++++++++++-------------- +- drivers/net/phy/mediatek/mtk-ge.c | 34 +++++++++++------------ +- 2 files changed, 37 insertions(+), 37 deletions(-) +- +---- a/drivers/net/phy/mediatek/mtk-ge-soc.c +-+++ b/drivers/net/phy/mediatek/mtk-ge-soc.c +-@@ -1394,17 +1394,17 @@ static int mt7981_phy_probe(struct phy_d +- static struct phy_driver mtk_socphy_driver[] = { +- { +- PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981), +-- .name = "MediaTek MT7981 PHY", +-- .config_init = mt798x_phy_config_init, +-- .read_status = mtk_gphy_cl22_read_status, +-- .config_intr = genphy_no_config_intr, +-+ .name = "MediaTek MT7981 PHY", +-+ .config_init = mt798x_phy_config_init, +-+ .read_status = mtk_gphy_cl22_read_status, +-+ .config_intr = genphy_no_config_intr, +- .handle_interrupt = genphy_handle_interrupt_no_ack, +-- .probe = mt7981_phy_probe, +-- .suspend = genphy_suspend, +-- .resume = genphy_resume, +-- .read_page = mtk_phy_read_page, +-- .write_page = mtk_phy_write_page, +-- .led_blink_set = mt798x_phy_led_blink_set, +-+ .probe = mt7981_phy_probe, +-+ .suspend = genphy_suspend, +-+ .resume = genphy_resume, +-+ .read_page = mtk_phy_read_page, +-+ .write_page = mtk_phy_write_page, +-+ .led_blink_set = mt798x_phy_led_blink_set, +- .led_brightness_set = mt798x_phy_led_brightness_set, +- .led_hw_is_supported = mt798x_phy_led_hw_is_supported, +- .led_hw_control_set = mt798x_phy_led_hw_control_set, +-@@ -1412,17 +1412,17 @@ static struct phy_driver mtk_socphy_driv +- }, +- { +- PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988), +-- .name = "MediaTek MT7988 PHY", +-- .config_init = mt798x_phy_config_init, +-- .read_status = mtk_gphy_cl22_read_status, +-- .config_intr = genphy_no_config_intr, +-+ .name = "MediaTek MT7988 PHY", +-+ .config_init = mt798x_phy_config_init, +-+ .read_status = mtk_gphy_cl22_read_status, +-+ .config_intr = genphy_no_config_intr, +- .handle_interrupt = genphy_handle_interrupt_no_ack, +-- .probe = mt7988_phy_probe, +-- .suspend = genphy_suspend, +-- .resume = genphy_resume, +-- .read_page = mtk_phy_read_page, +-- .write_page = mtk_phy_write_page, +-- .led_blink_set = mt798x_phy_led_blink_set, +-+ .probe = mt7988_phy_probe, +-+ .suspend = genphy_suspend, +-+ .resume = genphy_resume, +-+ .read_page = mtk_phy_read_page, +-+ .write_page = mtk_phy_write_page, +-+ .led_blink_set = mt798x_phy_led_blink_set, +- .led_brightness_set = mt798x_phy_led_brightness_set, +- .led_hw_is_supported = mt798x_phy_led_hw_is_supported, +- .led_hw_control_set = mt798x_phy_led_hw_control_set, +---- a/drivers/net/phy/mediatek/mtk-ge.c +-+++ b/drivers/net/phy/mediatek/mtk-ge.c +-@@ -230,34 +230,34 @@ static int mt753x_phy_led_hw_control_set +- static struct phy_driver mtk_gephy_driver[] = { +- { +- PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7530), +-- .name = "MediaTek MT7530 PHY", +-- .config_init = mt7530_phy_config_init, +-+ .name = "MediaTek MT7530 PHY", +-+ .config_init = mt7530_phy_config_init, +- /* Interrupts are handled by the switch, not the PHY +- * itself. +- */ +-- .config_intr = genphy_no_config_intr, +-+ .config_intr = genphy_no_config_intr, +- .handle_interrupt = genphy_handle_interrupt_no_ack, +-- .suspend = genphy_suspend, +-- .resume = genphy_resume, +-- .read_page = mtk_phy_read_page, +-- .write_page = mtk_phy_write_page, +-+ .suspend = genphy_suspend, +-+ .resume = genphy_resume, +-+ .read_page = mtk_phy_read_page, +-+ .write_page = mtk_phy_write_page, +- }, +- { +- PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7531), +-- .name = "MediaTek MT7531 PHY", +-- .probe = mt7531_phy_probe, +-- .config_init = mt7531_phy_config_init, +-- .read_status = mtk_gphy_cl22_read_status, +-+ .name = "MediaTek MT7531 PHY", +-+ .probe = mt7531_phy_probe, +-+ .config_init = mt7531_phy_config_init, +-+ .read_status = mtk_gphy_cl22_read_status, +- /* Interrupts are handled by the switch, not the PHY +- * itself. +- */ +-- .config_intr = genphy_no_config_intr, +-+ .config_intr = genphy_no_config_intr, +- .handle_interrupt = genphy_handle_interrupt_no_ack, +-- .suspend = genphy_suspend, +-- .resume = genphy_resume, +-- .read_page = mtk_phy_read_page, +-- .write_page = mtk_phy_write_page, +-- .led_blink_set = mt753x_phy_led_blink_set, +-+ .suspend = genphy_suspend, +-+ .resume = genphy_resume, +-+ .read_page = mtk_phy_read_page, +-+ .write_page = mtk_phy_write_page, +-+ .led_blink_set = mt753x_phy_led_blink_set, +- .led_brightness_set = mt753x_phy_led_brightness_set, +- .led_hw_is_supported = mt753x_phy_led_hw_is_supported, +- .led_hw_control_set = mt753x_phy_led_hw_control_set, +diff --git a/target/linux/mediatek/patches-6.6/733-13-net-phy-mediatek-Remove-unnecessary-outer-parens-of-.patch b/target/linux/mediatek/patches-6.6/733-13-net-phy-mediatek-Remove-unnecessary-outer-parens-of-.patch +deleted file mode 100644 +index dd99bbba9a09ec..00000000000000 +--- a/target/linux/mediatek/patches-6.6/733-13-net-phy-mediatek-Remove-unnecessary-outer-parens-of-.patch ++++ /dev/null +@@ -1,65 +0,0 @@ +-From e59883b637ae317c2ac275b542e8a50670d76e7c Mon Sep 17 00:00:00 2001 +-From: "SkyLake.Huang" +-Date: Mon, 1 Jul 2024 18:54:17 +0800 +-Subject: [PATCH 13/13] net: phy: mediatek: Remove unnecessary outer parens of +- "supported_triggers" var +- +-This patch removes unnecessary outer parens of "supported_triggers" vars +-in mtk-ge.c & mtk-ge-soc.c to improve readability. +- +-Signed-off-by: SkyLake.Huang +---- +- drivers/net/phy/mediatek/mtk-ge-soc.c | 16 ++++++++-------- +- drivers/net/phy/mediatek/mtk-ge.c | 16 ++++++++-------- +- 2 files changed, 16 insertions(+), 16 deletions(-) +- +---- a/drivers/net/phy/mediatek/mtk-ge-soc.c +-+++ b/drivers/net/phy/mediatek/mtk-ge-soc.c +-@@ -1224,14 +1224,14 @@ static int mt798x_phy_led_brightness_set +- } +- +- static const unsigned long supported_triggers = +-- (BIT(TRIGGER_NETDEV_FULL_DUPLEX) | +-- BIT(TRIGGER_NETDEV_HALF_DUPLEX) | +-- BIT(TRIGGER_NETDEV_LINK) | +-- BIT(TRIGGER_NETDEV_LINK_10) | +-- BIT(TRIGGER_NETDEV_LINK_100) | +-- BIT(TRIGGER_NETDEV_LINK_1000) | +-- BIT(TRIGGER_NETDEV_RX) | +-- BIT(TRIGGER_NETDEV_TX)); +-+ BIT(TRIGGER_NETDEV_FULL_DUPLEX) | +-+ BIT(TRIGGER_NETDEV_HALF_DUPLEX) | +-+ BIT(TRIGGER_NETDEV_LINK) | +-+ BIT(TRIGGER_NETDEV_LINK_10) | +-+ BIT(TRIGGER_NETDEV_LINK_100) | +-+ BIT(TRIGGER_NETDEV_LINK_1000) | +-+ BIT(TRIGGER_NETDEV_RX) | +-+ BIT(TRIGGER_NETDEV_TX); +- +- static int mt798x_phy_led_hw_is_supported(struct phy_device *phydev, u8 index, +- unsigned long rules) +---- a/drivers/net/phy/mediatek/mtk-ge.c +-+++ b/drivers/net/phy/mediatek/mtk-ge.c +-@@ -189,14 +189,14 @@ static int mt753x_phy_led_brightness_set +- } +- +- static const unsigned long supported_triggers = +-- (BIT(TRIGGER_NETDEV_FULL_DUPLEX) | +-- BIT(TRIGGER_NETDEV_HALF_DUPLEX) | +-- BIT(TRIGGER_NETDEV_LINK) | +-- BIT(TRIGGER_NETDEV_LINK_10) | +-- BIT(TRIGGER_NETDEV_LINK_100) | +-- BIT(TRIGGER_NETDEV_LINK_1000) | +-- BIT(TRIGGER_NETDEV_RX) | +-- BIT(TRIGGER_NETDEV_TX)); +-+ BIT(TRIGGER_NETDEV_FULL_DUPLEX) | +-+ BIT(TRIGGER_NETDEV_HALF_DUPLEX) | +-+ BIT(TRIGGER_NETDEV_LINK) | +-+ BIT(TRIGGER_NETDEV_LINK_10) | +-+ BIT(TRIGGER_NETDEV_LINK_100) | +-+ BIT(TRIGGER_NETDEV_LINK_1000) | +-+ BIT(TRIGGER_NETDEV_RX) | +-+ BIT(TRIGGER_NETDEV_TX); +- +- static int mt753x_phy_led_hw_is_supported(struct phy_device *phydev, u8 index, +- unsigned long rules)