diff --git a/.github/CODE_OF_CONDUCT.md b/.github/CODE_OF_CONDUCT.md new file mode 100644 index 0000000..18c9147 --- /dev/null +++ b/.github/CODE_OF_CONDUCT.md @@ -0,0 +1,128 @@ +# Contributor Covenant Code of Conduct + +## Our Pledge + +We as members, contributors, and leaders pledge to make participation in our +community a harassment-free experience for everyone, regardless of age, body +size, visible or invisible disability, ethnicity, sex characteristics, gender +identity and expression, level of experience, education, socio-economic status, +nationality, personal appearance, race, religion, or sexual identity +and orientation. + +We pledge to act and interact in ways that contribute to an open, welcoming, +diverse, inclusive, and healthy community. + +## Our Standards + +Examples of behavior that contributes to a positive environment for our +community include: + +* Demonstrating empathy and kindness toward other people +* Being respectful of differing opinions, viewpoints, and experiences +* Giving and gracefully accepting constructive feedback +* Accepting responsibility and apologizing to those affected by our mistakes, + and learning from the experience +* Focusing on what is best not just for us as individuals, but for the + overall community + +Examples of unacceptable behavior include: + +* The use of sexualized language or imagery, and sexual attention or + advances of any kind +* Trolling, insulting or derogatory comments, and personal or political attacks +* Public or private harassment +* Publishing others' private information, such as a physical or email + address, without their explicit permission +* Other conduct which could reasonably be considered inappropriate in a + professional setting + +## Enforcement Responsibilities + +Community leaders are responsible for clarifying and enforcing our standards of +acceptable behavior and will take appropriate and fair corrective action in +response to any behavior that they deem inappropriate, threatening, offensive, +or harmful. + +Community leaders have the right and responsibility to remove, edit, or reject +comments, commits, code, wiki edits, issues, and other contributions that are +not aligned to this Code of Conduct, and will communicate reasons for moderation +decisions when appropriate. + +## Scope + +This Code of Conduct applies within all community spaces, and also applies when +an individual is officially representing the community in public spaces. +Examples of representing our community include using an official e-mail address, +posting via an official social media account, or acting as an appointed +representative at an online or offline event. + +## Enforcement + +Instances of abusive, harassing, or otherwise unacceptable behavior may be +reported to the community leaders responsible for enforcement at +. +All complaints will be reviewed and investigated promptly and fairly. + +All community leaders are obligated to respect the privacy and security of the +reporter of any incident. + +## Enforcement Guidelines + +Community leaders will follow these Community Impact Guidelines in determining +the consequences for any action they deem in violation of this Code of Conduct: + +### 1. Correction + +**Community Impact**: Use of inappropriate language or other behavior deemed +unprofessional or unwelcome in the community. + +**Consequence**: A private, written warning from community leaders, providing +clarity around the nature of the violation and an explanation of why the +behavior was inappropriate. A public apology may be requested. + +### 2. Warning + +**Community Impact**: A violation through a single incident or series +of actions. + +**Consequence**: A warning with consequences for continued behavior. No +interaction with the people involved, including unsolicited interaction with +those enforcing the Code of Conduct, for a specified period of time. This +includes avoiding interactions in community spaces as well as external channels +like social media. Violating these terms may lead to a temporary or +permanent ban. + +### 3. Temporary Ban + +**Community Impact**: A serious violation of community standards, including +sustained inappropriate behavior. + +**Consequence**: A temporary ban from any sort of interaction or public +communication with the community for a specified period of time. No public or +private interaction with the people involved, including unsolicited interaction +with those enforcing the Code of Conduct, is allowed during this period. +Violating these terms may lead to a permanent ban. + +### 4. Permanent Ban + +**Community Impact**: Demonstrating a pattern of violation of community +standards, including sustained inappropriate behavior, harassment of an +individual, or aggression toward or disparagement of classes of individuals. + +**Consequence**: A permanent ban from any sort of public interaction within +the community. + +## Attribution + +This Code of Conduct is adapted from the [Contributor Covenant][homepage], +version 2.0, available at +https://www.contributor-covenant.org/version/2/0/code_of_conduct.html. + +Community Impact Guidelines were inspired by [Mozilla's code of conduct +enforcement ladder](https://github.com/mozilla/diversity). + +[homepage]: https://www.contributor-covenant.org + +For answers to common questions about this code of conduct, see the FAQ at +https://www.contributor-covenant.org/faq. Translations are available at +https://www.contributor-covenant.org/translations. diff --git a/.github/CONTRIBUTING.md b/.github/CONTRIBUTING.md new file mode 100644 index 0000000..bd316c5 --- /dev/null +++ b/.github/CONTRIBUTING.md @@ -0,0 +1,34 @@ +# 贡献指南 + +首先感谢您参与本开源项目,在您提交issue和pull request之前请认真阅读本指南 + +在提交pull request时一定要关联相应的issue,如果没有相应issue,请先创建issue +关于pull request关联issue,GitHub支持自动和手动关联,具体操作请参考[Link PR to issue](https://docs.github.com/en/issues/tracking-your-work-with-issues/linking-a-pull-request-to-an-issue) + +issue和pull request填写时都支持Markdown,关于GitHub的Markdown语法和扩展请参考[GitHub Flavored Markdown](https://docs.github.com/en/get-started/writing-on-github) + +## 提交issue + +1. 打开issue界面 [isuue](https://github.com/kendryte/k230_docs/issues) +2. 查看issue列表中是否已经存在相似issue,如果没有请点击`New issue`按钮 +3. 根据您的问题类型,选择不同的issue模板 +4. 填写必须项后(带红色\*标记),点击`Submit new issue`按钮完成提交 + +## 提交pull request + +1. Fork本仓库到您的github +2. Clone仓库到您本地 +3. 您可以基于`main`分支创建新分支并添加更改`git checkout -b newbranch -l main` +4. 提交您的更改到您的github +5. 进入您的github仓库点击`Pull request`按钮后点击`New pull request`按钮 +6. 选择`base repository`为`kendryte/k230_docs`,选择`base`为`main`,选择`head repository`为`yourname/k230_docs`,选择`compare`为`newbranch` +7. 根据pull request模板要求填写您的描述 +8. 点击`Create pull request`完成提交 + +> 如果您对以上流程还有不清楚的地方请参考[GitHub PR Flow](https://docs.github.com/en/pull-requests/collaborating-with-pull-requests/proposing-changes-to-your-work-with-pull-requests) + +## Markdown检查 + +本项目会对上传的Markdown文件进行格式化检查和内部引用链接检查,如果不符合格式要求或存在不能访问的链接,导致PR不能被merge,因此提交PR前请确保您已在本地进行过检查 +格式检查工具使用的是`markdownlint`,规则配置文件是[markdownlint.json](../.markdownlint.json)。本地可使用`vscode`安装`markdownlint`来进行在线检查和格式化 +您也可以在提交PR之前,先push到您GitHub仓库的`check`分支进行CI检查,避免重复修改PR diff --git a/.github/ISSUE_TEMPLATE/config.yml b/.github/ISSUE_TEMPLATE/config.yml new file mode 100644 index 0000000..574f8de --- /dev/null +++ b/.github/ISSUE_TEMPLATE/config.yml @@ -0,0 +1,5 @@ +blank_issues_enabled: false +contact_links: + - name: kendryte Community + about: kendryte 开发者社区 + url: https://developer.canaan-creative.com/ diff --git a/.github/ISSUE_TEMPLATE/errata.yml b/.github/ISSUE_TEMPLATE/errata.yml new file mode 100644 index 0000000..ac4c470 --- /dev/null +++ b/.github/ISSUE_TEMPLATE/errata.yml @@ -0,0 +1,15 @@ +name: Errata +description: 向我们反馈错误 +title: "[Errata]: " +labels: ["errata"] +body: + - type: textarea + id: errata + attributes: + label: Errata + description: 勘误 + placeholder: | + Please describe the wrong document and location. (请您描述一下错误的文档及位置) + Tip: You can attach images or files by clicking this area to highlight it and then dragging files in. (您能点击这个区域然后拖动文件来添加图片或文件) + validations: + required: true diff --git a/.github/ISSUE_TEMPLATE/improvement.yml b/.github/ISSUE_TEMPLATE/improvement.yml new file mode 100644 index 0000000..4db5410 --- /dev/null +++ b/.github/ISSUE_TEMPLATE/improvement.yml @@ -0,0 +1,15 @@ +name: Improvement +description: 向我们提出改进 +title: "[Improvement]: " +labels: ["improvement"] +body: + - type: textarea + id: improvement + attributes: + label: Improvement + description: 改进 + placeholder: | + You can suggest to us to add some content or modify the typography. (您可以向我们建议新增某些内容或修改排版) + Tip: You can attach images or files by clicking this area to highlight it and then dragging files in. (您能点击这个区域然后拖动文件来添加图片或文件) + validations: + required: true diff --git a/.github/ISSUE_TEMPLATE/other.yml b/.github/ISSUE_TEMPLATE/other.yml new file mode 100644 index 0000000..1d82b18 --- /dev/null +++ b/.github/ISSUE_TEMPLATE/other.yml @@ -0,0 +1,15 @@ +name: Other +description: 其它问题 +title: "[other]: " +labels: [] +body: + - type: textarea + id: other + attributes: + label: Other + description: 其它问题 + placeholder: | + If you have any other questions you can describe them here. (如果您有任何其它问题可以在这里描述) + Tip: You can attach images or files by clicking this area to highlight it and then dragging files in. (您能点击这个区域然后拖动文件来添加图片或文件) + validations: + required: true diff --git a/.github/pull_request_template.md b/.github/pull_request_template.md new file mode 100644 index 0000000..a98a60a --- /dev/null +++ b/.github/pull_request_template.md @@ -0,0 +1,14 @@ + + +## PR描述: + + +## 关联issue: + + diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..eed118e --- /dev/null +++ b/.gitignore @@ -0,0 +1,3 @@ +*.pdf +.DS_Store +**/.DS_Store diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml new file mode 100755 index 0000000..a505c31 --- /dev/null +++ b/.gitlab-ci.yml @@ -0,0 +1,24 @@ +# docker image from https://github.com/DavidAnson/markdownlint-cli2 +# vscode markdownlint https://marketplace.visualstudio.com/items?itemName=DavidAnson.vscode-markdownlint +# markdownlint-cli2: https://github.com/DavidAnson/markdownlint-cli2 +# markdownlint rules: https://github.com/DavidAnson/markdownlint/blob/main/doc/Rules.md +# + +markdownlint: + rules: + # MR job + - if: $CI_PIPELINE_SOURCE == "merge_request_event" && $CI_MERGE_REQUEST_TARGET_BRANCH_NAME == "dev" + - if: $CI_PIPELINE_SOURCE == "merge_request_event" && $CI_MERGE_REQUEST_TARGET_BRANCH_NAME == "main" + # release job + - if: $CI_PIPELINE_SOURCE == "push" && $CI_COMMIT_TAG =~ /^v\d+\.\d+.*$/ + # pre-release job + - if: '$CI_PIPELINE_SOURCE == "web"' + when: always + stage: test + timeout: 10m + image: registry.gitlab.com/pipeline-components/markdownlint-cli2:latest + tags: + - k230 + script: + - markdownlint-cli2 *.md **/*.md **/**/*.md **/**/**/*.md **/**/**/**/*.md + diff --git a/.gitlab/merge_request_templates/doc.md b/.gitlab/merge_request_templates/doc.md new file mode 100644 index 0000000..5cb8cec --- /dev/null +++ b/.gitlab/merge_request_templates/doc.md @@ -0,0 +1,11 @@ +# Merge Request + + +## 1. Doc概述 + + +## 2. 详细说明 + + +## 3. JIRA BUG Link + diff --git a/.markdownlint.json b/.markdownlint.json new file mode 100644 index 0000000..bab771d --- /dev/null +++ b/.markdownlint.json @@ -0,0 +1,104 @@ +{ + // MD003 + "heading-style": { + "style": "atx" + }, + // MD004 + "ul-style": { + "style": "consistent" + }, + // MD007 + "ul-indent": { + "indent": 2 + }, + // MD009 + "no-trailing-spaces": { + "br_spaces": 2, + "list_item_empty_lines": false, + "strict": false + }, + // MD010 + "no-hard-tabs": { + "code_blocks": true, + "ignore_code_languages": ["Makefile","makefile"], + "spaces_per_tab": 1 + }, + // MD011 + "no-multiple-blanks": { + "maximum": 1 + }, + // MD013 + "line-length": { + "strict": false, + "line_length": 2000, + "code_blocks": false + }, + // MD022 + "blanks-around-headers": { + "lines_above": 1, + "lines_below": 1 + }, + // MD025 + "single-title": { + "level": 1 + }, + // MD024 + "no-duplicate-heading": { + "allow_different_nesting": false, + "siblings_only": false + }, + // MD029 + "ol-prefix": { + //"style": "one_or_ordered" + "style": "one" + }, + // MD030 + "list-marker-space": { + "ol_multi": 1, + "ol_single": 1, + "ul_multi": 1, + "ul_single": 1 + }, + // MD031 + "blanks-around-fences": { + "list_items": true + }, + // MD033 + "no-inline-html": { + "allowed_elements": ["div"] + }, + // MD035 + "hr-style": { + "style": "---" + }, + // MD040 + "fenced-code-language": { + "allowed_languages": [], + "language_only": false + }, + // MD041 + "first-line-heading": { + "level": 1 + }, + // MD044 + "proper-names": { + "code_blocks": true, + "names": [] + }, + // MD046 + "code-block-style": { + "style": "fenced" + }, + // MD048 + "code-fence-style": { + "style": "backtick" + }, + // MD049 + "emphasis-style": { + "style": "asterisk" + }, + // MD050 + "strong-style": { + "style": "asterisk" + } +} diff --git a/LICENSE b/LICENSE new file mode 100644 index 0000000..f00ebf0 --- /dev/null +++ b/LICENSE @@ -0,0 +1,25 @@ +Copyright (c) 2023, Canaan Bright Sight Co., Ltd + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright +notice, this list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright +notice, this list of conditions and the following disclaimer in the +documentation and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND +CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR +CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/README.md b/README.md new file mode 100644 index 0000000..dd51e09 --- /dev/null +++ b/README.md @@ -0,0 +1,162 @@ +# 嘉楠勘智K230文档 + +[![Github repository](https://img.shields.io/badge/github-repository-blue?logo=github&style=plastic)](https://github.com/kendryte/k230_docs) +[![Gitee repository](https://img.shields.io/badge/gitee-repository-blue?logo=gitee&style=plastic)](https://gitee.com/kendryte/k230_docs) +[![GitHub release](https://img.shields.io/github/v/release/kendryte/k230_docs?color=brightgreen&display_name=tag&logo=github&style=plastic)](https://github.com/kendryte/k230_docs/releases) + +[TOC] + +## K230相关链接 + +| 链接 | 说明 | +| ------ | ---- | +| [K230 SDK](https://github.com/kendryte/k230_sdk) | Kendryte K230 SDK Github Repo | +|[K230 Docs](https://github.com/kendryte/k230_docs)| Kendryte K230 Docs Github Repo | +| [K230 SDK Gitee mirror](https://gitee.com/kendryte/k230_sdk) | Kendryte K230 SDK Gitee mirror Repo | +|[K230 Docs Gitee mirror](https://gitee.com/kendryte/k230_docs)| Kendryte K230 Docs Gitee mirror Repo | +|[K230 SDK Release mirror](https://kendryte-download.canaan-creative.com/k230/release/sdk/k230_sdk.tar.gz)| 嘉楠勘智K230 SDK release k230_sdk.tar.gz下载 | +|[Canaan Kendryte Forum](https://developer.canaan-creative.com/)| 嘉楠勘智开发者论坛 | + +## K230硬件文档 + +| 文档名称 | 文档概要 | +| --- | --- | +| [K230_DEMO_BOARD资源使用指南.md](zh/00_hardware/K230_DEMO_BOARD资源使用指南.md) | K230 Demo Board 硬件资源使用说明文档 | +| [K230_硬件设计指南.md](zh/00_hardware/K230_硬件设计指南.md) | K230 硬件设计指南文档 | +| [K230_PINOUT_V1.0_20230524](zh/00_hardware/K230_PINOUT_V1.0_20230524.xlsx) | K230 芯片引脚定义 | +| [K230_datasheet.md](zh/00_hardware/K230_datasheet.md) | K230 Datasheet | + +### K230工程设计文件 + +| 文档名称 | 文档概要 | +| --- | --- | +| [K230_DEMO_BOARD-20230427-DXF](zh/00_hardware/K230/K230_DEMO_BOARD-20230427-DXF.zip) | K230 Demo Board DXF 文件| +| [K230_DEMO_BOARD-20230427-GERBER](zh/00_hardware/K230/K230_DEMO_BOARD-20230427-GERBER.zip) | K230 Demo Board制板用GERBER文件 | +| [K230_DEMO_BOARD-20230427-PCB](zh/00_hardware/K230/K230_DEMO_BOARD-20230427-PCB.zip) | K230 Demo Board PCB Cadence 设计文件| +| [K230_DEMO_BOARD-20230427-SMT](zh/00_hardware/K230/K230_DEMO_BOARD-20230427-SMT.zip) | K230 Demo Board SMT 焊接排布与钻孔文件| +| [K230-DEMO-BOARD-BOM-20230510](zh/00_hardware/K230/K230-DEMO-BOARD-BOM-20230510.xlsx) | K230 Demo Board所用器件BOM | +| [K230-DEMO-BOARD-SCH.DSN](zh/00_hardware/K230/K230-DEMO-BOARD-SCH.DSN) | K230 Demo Board 原理图Cadence CIS Capture文件 | +| [K230-DEMO-BOARD-SCH.pdf](zh/00_hardware/K230/K230-DEMO-BOARD-SCH.pdf) | K230 Demo Board 原理图 pdf文件 | + +### K230D工程设计文件 + +| 文档名称 | 文档概要 | +| --- | --- | +| [K230-SIP-EVB-V1_0-A_1-20230322-DXF](zh/00_hardware/K230D/K230-SIP-EVB-V1_0-A_1-20230322-DXF.zip) | K230D Demo Board DXF 文件| +| [K230-SIP-EVB-V1_0-A_1-20230322-GERBER](zh/00_hardware/K230D/K230-SIP-EVB-V1_0-A_1-20230322-GERBER.zip) | K230D Demo Board制板用GERBER文件 | +| [K230-SIP-EVB-V1_0-A_1-20230322-PCB](zh/00_hardware/K230D/K230-SIP-EVB-V1_0-A_1-20230322-PCB.zip) | K230D Demo Board PCB Cadence 设计文件| +| [K230-SIP-EVB-V1_0-A_1-20230322-SMT](zh/00_hardware/K230D/K230-SIP-EVB-V1_0-A_1-20230322-SMT.zip) | K230D Demo Board SMT 焊接排布与钻孔文件| +| [K230-SIP-EVB-V1_0-A_1_20230316-BOM](zh/00_hardware/K230D/K230-SIP-EVB-V1_0-A_1_20230316-BOM.xlsx) | K230D Demo Board所用器件BOM | +| [K230-SIP-EVB-V1_0-A_1-20230316.DSN](zh/00_hardware/K230D/K230-SIP-EVB-V1_0-A_1-20230316.DSN) | K230D Demo Board 原理图Cadence CIS Capture文件 | +| [K230-SIP-EVB-V1.0-A.1-20230317.pdf](zh/00_hardware/K230D/K230-SIP-EVB-V1.0-A.1-20230317.pdf) | K230D Demo Board 原理图 pdf文件 | + +## K230 SDK 软件文档 + +### K230 EVB 软件文档 + +| 文档名称 | 文档概要 | +| --- | --- | +| [K230_SDK_使用说明.md](zh/01_software/board/K230_SDK_使用说明.md) | K230 SDK 使用说明| + +#### K230 SDK nncase 文档 + +| 文档名称 | 文档概要 | +| --- | --- | +| [K230_nncase_开发指南.md](zh/01_software/board/ai/K230_nncase_开发指南.md) | K230 nncase 开发指南| + +#### K230 sdk cdk 文档 + +| 文档名称 | 文档概要 | +| --- | --- | +| [K230_核间通讯_API参考.md](zh/01_software/board/cdk/K230_核间通讯_API参考.md) | K230 核间通讯 API参考| +| [K230_系统控制_MAPI参考.md](zh/01_software/board/cdk/K230_系统控制_MAPI参考.md) | K230 系统控制 MAPI参考| + +#### K230 sdk demo 文档 + +| 文档名称 | 文档概要 | +| --- | --- | +| [K230_SDK_Demo使用指南.md](zh/01_software/board/examples/K230_SDK_Demo使用指南.md) | K230 SDK Demo使用指南| + +#### K230 sdk middleware 文档 + +| 文档名称 | 文档概要 | +| --- | --- | +| [K230_openblas_开发使用指南.md](zh/01_software/board/middleware/K230_openblas_开发使用指南.md) | K230 OpenBLAS 开发使用指南| +| [K230_opencv_开发使用指南.md](zh/01_software/board/middleware/K230_opencv_开发使用指南.md) | K230 OpenCV 开发使用指南| + +#### K230 sdk mpp 文档 + +| 文档名称 | 文档概要 | +| --- | --- | +| [K230_Camera_Sensor适配指南.md](zh/01_software/board/mpp/K230_Camera_Sensor适配指南.md) | K230 Camera Sensor适配指南| +| [K230_DMA_API参考.md](zh/01_software/board/mpp/K230_DMA_API参考.md) | K230 DMA API参考| +| [K230_DPU_API参考.md](zh/01_software/board/mpp/K230_DPU_API参考.md) | K230 DPU API参考| +| [K230_GPU_API参考.md](zh/01_software/board/mpp/K230_GPU_API参考.md) | K230 GPU API参考| +| [K230_SHA256_API参考.md](zh/01_software/board/mpp/K230_SHA256_API参考.md) | K230 SHA256 API参考| +| [K230_VICAP_API参考.md](zh/01_software/board/mpp/K230_VICAP_API参考.md) | K230 VICAP API参考| +| [K230_系统控制_API参考.md](zh/01_software/board/mpp/K230_系统控制_API参考.md) | K230 系统控制 API参考| +| [K230_视频编解码_API参考.md](zh/01_software/board/mpp/K230_视频编解码_API参考.md) | K230 视频编解码 API参考| +| [K230_视频输出_API参考.md](zh/01_software/board/mpp/K230_视频输出_API参考.md) | K230 视频输出 API参考| +| [K230_音频_API参考.md](zh/01_software/board/mpp/K230_音频_API参考.md) | K230 音频 API参考| + +#### K230 sdk osdrv 文档 + +| 文档名称 | 文档概要 | +| --- | --- | +| [K230_DRM_API参考.md](zh/01_software/board/osdrv/K230_DRM_API参考.md) | K230 DRM API参考| +| [K230_PMU_使用指南.md](zh/01_software/board/osdrv/K230_PMU_使用指南.md) | K230 PMU 使用指南| +| [K230_SDK_IoT_WiFi_AiW4211LV10_使用指南.md](zh/01_software/board/osdrv/K230_SDK_IoT_WiFi_AiW4211LV10_使用指南.md) | K230 SDK IoT WiFi AiW4211LV10_使用指南| +| [K230_SDK_IoT_WiFi_AiW4211LV10_驱动开发指南.md](zh/01_software/board/osdrv/K230_SDK_IoT_WiFi_AiW4211LV10_驱动开发指南.md) | K230 SDK IoT WiFi AiW4211LV10 驱动开发指南| +| [K230_大核低速驱动_API参考.md](zh/01_software/board/osdrv/K230_大核低速驱动_API参考.md) | K230 大核低速驱动 API参考| +| [K230_小核Linux驱动_API参考.md](zh/01_software/board/osdrv/K230_小核Linux驱动_API参考.md) | K230 小核Linux驱动 API参考| + +### K230 PC 软件文档 + +| 文档名称 | 文档概要 | +| --- | --- | +| [K230_SDK_Tuning_Tool使用指南.md](zh/01_software/pc/pqtools/K230_SDK_Tuning_Tool使用指南.md) | K230 SDK Tuning Tool 使用指南| +| [K230_SDK_Dewarp使用指南.md](zh/01_software/pc/dewarp/K230_SDK_Dewarp使用指南.md) | K230 SDK Dewarp 使用指南 | + +## K230 SDK 使用教程 + +### K230 SDK 基础教程 + +| 文档名称 | 文档概要 | +| --- | --- | +| [K230_实战基础篇_hello_world.md](zh/02_applications/tutorials/K230_实战基础篇_hello_world.md) | K230 实战基础篇 hello_world| +| [K230_大小核通讯_sharefs用法介绍.md](zh/02_applications/tutorials/K230_大小核通讯_sharefs用法介绍.md) | K230 大小核通讯 sharefs用法介绍| +| [K230_GPU应用实战.md](zh/02_applications/tutorials/K230_GPU应用实战.md) | K230 GPU应用实战| +| [K230_GUI实战_LVGL移植教程.md](zh/02_applications/tutorials/K230_GUI实战_LVGL移植教程.md) | K230 GUI实战 LVGL移植教程| +| [K230_RVV实战.md](zh/02_applications/tutorials/K230_RVV实战.md) | K230 RVV实战| +| [K230_USB应用实战_UVC传输YUV及编码码流.md](zh/02_applications/tutorials/K230_USB应用实战_UVC传输YUV及编码码流.md) | K230 USB应用实战 UVC传输YUV及编码码流| +| [K230_图像实战_开机视频和开机logo.md](zh/02_applications/tutorials/K230_图像实战_开机视频和开机logo.md) | K230 图像实战 开机视频和开机logo| +| [K230_图像采集实战_如何支持一款新sensor.md](zh/02_applications/tutorials/K230_图像采集实战_如何支持一款新sensor.md) | K230 图像采集实战 如何支持一款新sensor| +| [K230_音频实战_音频采集_播放和编解码.md](zh/02_applications/tutorials/K230_音频实战_音频采集_播放和编解码.md) | K230 实战基础篇 音频采集、播放和编解码| +| [K230_编码实战_rtsp_server搭建和推流.md](zh/02_applications/tutorials/K230_编码实战_rtsp_server搭建和推流.md) | K230 编码实战 rtsp server 搭建和推流| +| [K230_AI实战_HHB神经网络模型部署工具.md](zh/02_applications/tutorials/K230_AI实战_HHB神经网络模型部署工具.md) | K230 AI实战 HHB神经网络模型部署工具| + +### K230 SDK 商业应用 + +| 文档名称 | 文档概要 | +| --- | --- | +| [K230_场景实战_智能门锁.md](zh/02_applications/business_poc/K230_场景实战_智能门锁.md) | K230 场景实战 智能门锁| + +### K230 SDK AI教程 + +## K230 SDK 其它文档 + +| 文档名称 | 文档概要 | +| --- | --- | +| [K230_SDK_版本说明.md](zh/03_other/K230_SDK_版本说明.md) | K230 SDK 版本说明| + +## 贡献指南 + +如果您对本项目感兴趣,想要反馈问题或提交文档,请参考[CONTRIBUTING](/.github/CONTRIBUTING.md) + +## 联系我们 + +北京嘉楠捷思信息技术有限公司 + +网址:[canaan-creative.com](https://www.canaan-creative.com/) + +商务垂询:[salesAI@canaan-creative.com](mailto:salesAI@canaan-creative.com) diff --git a/en/K230_brief_datasheet.md b/en/K230_brief_datasheet.md new file mode 100755 index 0000000..fea5e38 --- /dev/null +++ b/en/K230_brief_datasheet.md @@ -0,0 +1,221 @@ +# K230 Product Brief + +![cover](images/canaan-cover.png) + +Document version: V1.0 +Release date: 2023-6-10 + +
+ +## Disclaimer + +The products, services or features you purchase shall be subject to the commercial contracts and terms of Canaan Creative CO., LTD. (the "Company") and its affiliates, and all or part of the products, services or features described in this document may not be within the scope of your purchase or use. Unless otherwise agreed in the contract, the Company does not provide any express or implied representations or warranties as to the correctness, reliability, completeness, merchantability, fitness for a particular purpose and non-aggression of any statements, information, or content in this document.Unless otherwise agreed, this document is intended as a guide for use only. + +Due to product version upgrades or other reasons, the content of this document may be updated or modified from time to time without any notice. + +## Trademark Notice + +![logo](images/logo.png) +"Canaan" and other Canaan trademarks are trademarks of Canaan Creative CO., LTD. and its affiliates. All other trademarks or registered trademarks that may be mentioned in this document are owned by their respective owners. + +Copyright©2023 Canaan Creative CO., LTD. +This document is only suitable for the development and design of K230 platform, without the written permission of the company, any unit or individual shall not disseminate part or all of the content of this document in any form. + +Canaan Creative CO., LTD. +Website:canaan-creative.com +Business Email: + +
+ +## Menu + +[TOC] + +## Preface + +### Purpose + +This document is intended to provide a general overview of the K230 platform and its features. + +### Intended Audience + +The main people to whom this document (this guide) applies: + +- Design and maintenance personnel for electronic products +- Sales personnel for electronic products +- Technical support personnel + +### Terms + +### Revision history + +| Version Number | Modified by | Revision Date | Revision Notes | +|----------------|----------------|--------------|-------------------------------------------------------------------| +| V1.0 | Zhenming Huang | 2023-6-10 | Re-format to markdown document based on K230 Brief Datasheet_Complete_Apr_2023_v1 | +| | | | | + +## Overview + +The K230 chip is the latest generation SoC product in Canaan Technology's (NASDAQ: CAN) Kendryte® series of AIOT chips. The chip adopts a brand-new multi-heterogeneous unit acceleration computing architecture, integrates two RISC-V C908 computing cores, and has a built-in new generation KPU (Knowledge Process Unit) intelligent computing unit. Multi-precision AI computing power with INT8 and INT16. Supports general AI computing framework. The chip also has a variety of peripheral interfaces, as well as multiple scalar, vector, graphics, and other dedicated hardware acceleration units such as image 2D engine, AI 2D engine, 2.5D GPU, and 3D depth engine. K230 provides full-process computing acceleration for various computing tasks such as images, videos, audio, AI, etc. The chip has many features such as low latency, high performance, low power consumption, fast startup, and high security. +K230 can be used in various smart hardware products, such as smart door locks, home smart security cameras, dictionary pens, payment recognition, 3D structured light vision modules, drones, interactive robots, smart home appliances, smart toys, and smart manufacturing, intelligent vehicle cockpit and many other fields. + +## General Specifications + +### CPU + +- CPU 1: 64bit, RISC-V processor, 1.6GHz, supports RISC-V Vector Extension 1.0 specification, with floating-point units (FPUs), 128bits vector-process-unit, runs RTOS system + +- CPU 0: 64bit, RISC-V processor, 800MHz, supports RISC-V 64GCB instruction set, runs LINUX system + +### KPU + +- Support INT8 and INT16 + +- Support weight sparse compression +- Typical network performance: + - Resnet 50 ≥ 85fps @INT8 + - Mobilenet_v2 ≥ 670fps @INT8 + - YoloV5S ≥ 38fps @INT8 +- Support TVM / TensorFlow / Pytorch / ONNX +- Support quantitative tool chain and profiling tools +- Loss of quantization accuracy <1% + +### 2D Engine + +- 2D(GDMA) Engine: + - OSD/CSC/X-Mirror/Y-Mirror/Rotation(90/180/270) + - Typical image rotation capability: + - 2 x 1080\*1280 YUV400 @15fps + 1 x 1080\*1920 YUV420 @30fps + +- Independent AI 2D Engine: + - Affine/Crop/Resize/Padding/Shift + +### DPU (Depth Computing Unit) + +- Using 3D structured light depth calculation + +- Support multiple operators, including Img_check / LCN / SAD / Post_proc / Align +/ Disptodepth +- The maximum resolution of the landscape image is 1920\*1080, and the maximum resolution of the portrait image is 1080\*1440 +- Typical performance is 1280\*800@30fps, 1280\*1080@15fps,1920\*1080@9fps + +### Memory + +- DRAM: DDR3L / LPDDR4 with 16/32bit, +LPDDR3 with 32bit + +- DRAM frequency: + - DDR3L@1600Mbps / LPDDR3@2133Mbps + - LPDDR4@2667Mbps +- Maximum capacity: 2GB +- SIP mode: 128MB 16bit LPDDR4@3200Mbps +- SRAM:2MB+2MB (default for KPU) + +### Video Input + +- 3 x MIPI CSI + +- (1 x 4lane+1 x 2lane) or 3 x 2lane + +### ISP + +- Total throughput:8MP@30fps + +- Image 3A / 2DNR / 3DNR / WDR / HDR +- Local Tone Mapping +- Sharpen / BLS / LSC / De-warping +- RGB-IR 4x4 pattern + +### Video Output + +- 1 x MIPI DSI, 1 x 4 lane or 1 x 2 lane + +- Resolution: 2MP@60fps + +### Video Codec + +- Video encoding + - H.264 Baseline / Main Profile / High Profile + - H.265 Main Profile + - JPEG / MJPEG + - Maximum encoding performance: + - 8MP@20fps + - CBR / VBR / CQP / ROI encoding + +- Video decoding + - H.264 Baseline, Main Profile, High Profile + - H.265 Main Profile + - JPEG / MJPEG + - Maximum decoding performance: + - 8MP@40fps + +### 2.5D GPU + +- Highly optimized Tessellation Engine, cooperates with the VGlite driver to provide vector graphics drawing functions + +- Support rotation, scaling, translation, and format conversion of the input image +- The drawn picture can perform operations such as blending, compression, etc., with the picture in video memory + +### Audio + +- 2 x DAC: 8-192Khz + +- 2 x ADC: 8-192Khz +- Support ALC +- Maximum 8 x PDM DMIC inputs +- I2S interface supports 2x2 expansion + +### Peripherals + +- Low-speed interface + - 5 x UART / 5 x I2C / 6 x PWM + - GPIO (multiplexed with function pins): + - 64 x GPIO + 8 x PMU GPIO + - 50 x GPIO + 6 x PMU GPIO(SIP) + +- High-speed interface + - 2 x USB 2.0 OTG + - 2 x SDxC: SD3.01, eMMC 5.0 + - 3 x SPI: 1 x OSPI + 2 x QSPI +- WDT / RTC / Timer + +### Security + +- PUF / OTP / TRNG + +- Support AES, SHA, RSA, SM2/3/4, ECC + +### PMU + +- Ultra-low power consumption: in deep sleep mode, standby power consumption ≤ 20uW +- Support RTC function in 32KHz +- Support long and short press detection as system shutdown or wakeup signal +- Support IO edge and level detection to generate interrupts +- Support two output IOs to control PMIC and system reset +- Support 512 bits system log when shutdown + +### Other Features + +- Decompression module: + - decompression bandwidth ≥ 400MB/s, GZIP format + +- 4096-point FFT / IFFT unit +- Fastboot: 3A first picture ≤ 400ms +- Working environment temperature: -40 ~ 85°C +- Package:BGA, 0.65mm pitch + - 13 x 13mm + - 11 x 11mm (SIP 128MB 16bit LPDDR4) + +## Block Diagram + +![K230_block_diagram.png](images/K230_block_diagram.png) + +## Typical Applications   + +- 3D Face Lock Integrated Application Solution   + +![K230_application_1.png](images/K230_application_1.png) + +- Smart Dictionary Pen Application Solution   + +![K230_application_2.png](images/K230_application_2.png) diff --git a/en/images/K230_application_1.png b/en/images/K230_application_1.png new file mode 100755 index 0000000..8b5d1b5 Binary files /dev/null and b/en/images/K230_application_1.png differ diff --git a/en/images/K230_application_2.png b/en/images/K230_application_2.png new file mode 100755 index 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"a/zh/00_hardware/K230_DEMO_BOARD\350\265\204\346\272\220\344\275\277\347\224\250\346\214\207\345\215\227.md" "b/zh/00_hardware/K230_DEMO_BOARD\350\265\204\346\272\220\344\275\277\347\224\250\346\214\207\345\215\227.md" new file mode 100755 index 0000000..46cf566 --- /dev/null +++ "b/zh/00_hardware/K230_DEMO_BOARD\350\265\204\346\272\220\344\275\277\347\224\250\346\214\207\345\215\227.md" @@ -0,0 +1,263 @@ +# K230 DEMO BOARD 资源使用说明 + +![cover](images/HDG/canaan-cover.png) + +
+ +## 免责声明 + +您购买的产品、服务或特性等应受北京嘉楠捷思信息技术有限公司(“本公司”,下同)及其关联公司的商业合同和条款的约束,本文档中描述的全部或部分产品、服务或特性可能不在您的购买或使用范围之内。除非合同另有约定,本公司不对本文档的任何陈述、信息、内容的正确性、可靠性、完整性、适销性、符合特定目的和不侵权提供任何明示或默示的声明或保证。除非另有约定,本文档仅作为使用指导参考。 + +由于产品版本升级或其他原因,本文档内容将可能在未经任何通知的情况下,不定期进行更新或修改。 + +## 商标声明 + +![logo](./images/K230_DEMO_BOARD_USAGE_GUIDE/image3.png)、“嘉楠”和其他嘉楠商标均为北京嘉楠捷思信息技术有限公司及其关联公司的商标。本文档可能提及的其他所有商标或注册商标,由各自的所有人拥有。 + +**版权所有 © 2023北京嘉楠捷思信息技术有限公司。保留一切权利。** +非经本公司书面许可,任何单位和个人不得擅自摘抄、复制本文档内容的部分或全部,并不得以任何形式传播。 + +
+ +## 目录 + +[TOC] + +## 前言 + +### 概述 + +本文档主要介绍了K230 DEMO BOARD的使用说明。 + +### 读者对象 + +本文档(本指南)主要适用于以下人员: + +- 技术支持工程师 +- 软件开发工程师 + +### 缩略词定义 + +| 简称 | 说明 | +|------|------| +| | | +| | | + +### 修订记录 + +| 文档版本号 | 修改说明 | 修改者 | 日期 | +|------------|---------------------------------|--------|------------| +| V1.0 | 初版 | 杜瓴一 | 2023-03-10 | +| V1.1 | 改为对应EVB V1.1的说明 | 杜瓴一 | 2023-05-05 | +| V1.2 | 更新了J5,USB OTG的排针使用方法 | 杜瓴一 | 2023-05-10 | +| V1.3 | 将内容从EVB更改为K230 DEMO BOARD|杜瓴一|2023-06-07| + +## 开发板概述 + +### K230 DEMO BOARD概要 + +K230 DEMO BOARD是加装了摄像头子板和屏幕的完整开发测试板,已处于Plug-and-play状态,上电即可开始进行针对K230的后续开发工作。K230 DEMO BOARD会以一主板组装多子板的形式交付。本文档将通过主板上的各个接口,简要概述K230 DEMO BOARD各项配套的组件子板以及使用流程。 + +### K230 DEMO BOARD主板示意图 + +![K230 DEMO BOARD 样例](./images/K230_DEMO_BOARD_USAGE_GUIDE/image4.png) +(**图1.2.1**:K230 DEMO BOARD样品示例,子板未组装) + +### K230 DEMO BOARD配套组装子板 + +为确保验证灵活性,K230 DEMO BOARD配有多种接口,具备与不同种类的子卡连通的能力从而更为全面的开发芯片功能。主板所能搭载的子板种类如下: + +- Flash模组子卡(使用详情参阅**章节2.2**) + +- DSI屏幕与转接板(使用详情参阅**章节2.4**) + +- IMX335模组Sensor板(使用详情参阅**章节2.4**) + +- WIFI子卡(使用详情参阅**章节2.6**) + +- I2S/PDM接口数字音频子卡(使用详情参阅**章节2.7**) + +接口与子卡的使用方式将在**章节2**中介绍该子卡对应的接口时进行详细说明。以上子卡中,Flash模组子卡,DSI屏幕与转接板,IMX335模组Sensor板将被组装在K230 DEMO BOARD主板上交付,其余子卡默认**不包含**在K230 DEMO BOARD的交付清单中,在此列出仅用于辅助说明相关的接口功能及用法。 + +此外,以下使用K230 DEMO BOARD交付时会包含以下开发用线缆: + +- USB Type C 线缆2根 + +- OTG转接线,Type C公头转USB-A母头1根 + +- Type C公头转网口线缆1根 + +组装完整的DEMO板请参考**图1.3.1**。 + +![K230 DEMO BOARD样品示例,完整组装](./images/K230_DEMO_BOARD_USAGE_GUIDE/image5.png) +(**图1.3.1**:K230 DEMO BOARD样品示例,完整组装) + +## DEMO BOARD硬件功能说明 + +### K230 DEMO BOARD主板功能模块与全部接口 + +![K230 DEMO BOARD功能区域划分](./images/K230_DEMO_BOARD_USAGE_GUIDE/image6.png) +![所支持的所有接口与其在DEMO BOARD上对应的位置](./images/K230_DEMO_BOARD_USAGE_GUIDE/image7.png) +(**图2.1.1**:上图为K230 DEMO BOARD功能区域划分,下图为所支持的所有接口与其在DEMO BOARD上对应的位置) + +K230 DEMO BOARD可以按照**图2.1.1**中左图所示大致划分为6个区域,按所标序号顺序依次为: + +1. (蓝色)核心区 -即主芯片K230及其存储DDR,flash,eMMC,以及系统主时钟的所在位置。 + +1. (红色)电源区 - 即DEMO BOARD主板上全部电源,电源控制器件的所在位置。 + +1. (绿色)视频输入输出 - 即摄像头与屏幕与主板连接的位置。 + +1. (橙色)音频输入输出 - 即麦克风与耳机的所在位置。 + +1. (紫色)通用接口 -- 与其他设备进行数据交换的接口区域。 + +1. (黄色)排针接口 -- 此区域包含DEMO BOARD上关键信号的对应排针,可以被作为测试点或者与外接信号,扩展子卡等连接点。 + +左图中的每个区域包含数个右图中所列出的器件/接口。在本章节接下来的部分中,会按照上述顺序依次陈列每个区域中所覆盖的器件/接口。如有需要,会在陈列对应器件/接口时进行额外的信息补充或者使用方法说明。 + +**在本章节出现了原理图的场合中,如无特殊说明,则默认DEMO BOARD上器件封装的引脚与原理图上的封装引脚完全一致(指单双排,引脚出线顺序)。另外提到的所有引脚编号,器件编号均在K230 DEMO BOARD上通过白字丝印留有注明,请结合DEMO BOARD实物确认。** + +### 核心区(基本参数) + +本部分为DEMO BOARD的核心处理与存储区,包含**图2.1.1**右图中所罗列的如下5个接口/器件: + +1. **K230-USIP(DEMO BOARD上器件编号:U1)** + +1. **LPDDR3(DEMO BOARD上器件编号:U5)** +选型为NT6CL128M32DM-H0,南亚32bits - 4Gbits的LPDDR3,上限速率为2133Mbps + +1. **eMMC(DEMO BOARD上器件编号:U30)** +选型为KLM4G1FETE-B041,三星8bits - 4GBytes的eMMC,兼容至Ver. +5.1,时钟速率200MHz + +1. **Flash扩展(DEMO BOARD上器件编号:J9)** + +![flash模组子卡的实例图](./images/K230_DEMO_BOARD_USAGE_GUIDE/image8.png) +![Flash扩展-J9的原理图](./images/K230_DEMO_BOARD_USAGE_GUIDE/image9.png) +(**图2.2.1**:上图为flash模组子卡的实例图,左上白点处为引脚1,下图为Flash扩展-J9的原理图) + +DEMO板的FLASH的扩展处已焊好验证后的flash模组,无需进一步的改动。选型为NOR +OSPI(GD25LX256E,厂商:Giga Device,256Mbits) + +### 电源区(开机上电方式) + +![主要器件位置](./images/K230_DEMO_BOARD_USAGE_GUIDE/image10.png) + +(**图2.3.1**:电源区域主要器件位置,图示为通过开关上电的模式) + +这个区域产生DEMO BOARD上所需的所有电源。全部与DEMO BOARD电源控制相关的交互器件皆位于此区域,并有2种上电开机模式可以选择(后续会说明选择方法)。**图2.3.1**中编号对应如下6个主要接口/器件(名称与**图2.1.1**中右图的列表一致): + +1. **启动方式选择开关(DEMO BOARD上器件编号:SW1)** +K230支持从四种不同的地方加载启动文件,通过四种高低电平状态来选择K230启动位置的拨码开关。四种状态分别对应的启动位置与SW1的原理图请参考下方**图2.3.2**。 +![W1原理图](./images/K230_DEMO_BOARD_USAGE_GUIDE/image11.png) +(**图2.3.2**:SW1原理图) +其中,开关1,2分别对应BOOT0,BOOT1。将开关拨至引脚1,2对应高电平逻辑1(DEMO BOARD上标注的H侧),拨至引脚3,4对应低电平逻辑0(DEMO BOARD上标注的L侧)。以上编号均在DEMO BOARD板面上通过丝印注明。 + +1. **系统复位按键(DEMO BOARD上器件编号:K2)** +低有效按键复位。按下时拉低复位,松开时常态为高电平。可通过检测引脚2的电压判断当前的复位状况。 + +1. **开关机拨动开关(DEMO BOARD上器件编号:K3)** + +1. **中断信号按键(DEMO BOARD上器件编号:K1)** +用于手动产生中断信号的测试用按键。 + +1. **电源入口 DC 5V:2A(DEMO BOARD上器件编号:J2)** + +1. **PMU扩展(DEMO BOARD上器件编号:J1)** +电源测试时所用的排针扩展,在使用DEMO板时不需要。 +![PMU扩展J1原理图](./images/K230_DEMO_BOARD_USAGE_GUIDE/image12.png) +(**图2.3.3**:PMU扩展J1原理图) + +1. **红色LED电源指示灯(DEMO BOARD上器件编号:LED1)** + +**正常开机流程如下:** + +- 将SW1拨至所需的BOOT位置 + +- 将5V电压通过Type-C电源线接入电源入口-J2。 + +- 拨动K3至ON位置开机。若电源成功接通,则**图2.3.1**中的红色LED指示灯会亮起 + +- 在电源正常的情况下,可以通过查看复位状态是否为高平以确保K230成功启动。 + +- 若开机时电源指示灯不亮,请确认PMU扩展(J6)的15,16引脚处(即**图2.3.1**标号为6的方框中额外标示出的位置)的跳线帽是否被正确的插接。 + +### 视频输入输出(摄像头子板与屏幕子板) + +![视频区域主要器件位置](./images/K230_DEMO_BOARD_USAGE_GUIDE/image13.png) +(**图2.4.1**:视频区域主要器件位置) + +随DEMO BOARD一起交付的摄像头与屏幕子卡的连接处。**图2.4.1**中编号对应如下2个主要接口/器件(名称与**图2.1.1**中右图的列表一致)。 + +1. **显示屏扩展(DEMO BOARD上器件编号:J4)** +MIPI DSI的接口,是通过FPC连接线传输从MIPI发往(transmit to)显示屏的视频信号,亦称作MIPI TX接口。此处为**章节1.3**所述清单中的**DSI触摸屏幕转接板**的连接处,直接通过30Pin宽的FPC连接线接通J4与转接板即可。J4的引脚定义原理图如**图2.4.2**所示。 +![显示屏扩展引脚定义原理图](./images/K230_DEMO_BOARD_USAGE_GUIDE/image14.png) +(**图2.4.2:**显示屏扩展引脚定义原理图,图中引脚31,32为固定引脚不是信号引脚,可忽略) + +1. **Sensor扩展(DEMO BOARD上器件编号:J3)** + MIPI CSI的接口,是通过板对板连接器传输MIPI从摄像头处收到(receive from)的视频信号,亦称作MIPI RX接口。此处为**章节1.3**所述清单中的**IMX335模组Sensor板**的连接处。**J3**的引脚定义原理图如**图2.4.3**所示。 + +![ Sensor扩展引脚定义原理图](./images/K230_DEMO_BOARD_USAGE_GUIDE/image15.png) +(**图2.4.3**: Sensor扩展引脚定义原理图) + +在交付时全部模组子板已组装完毕,如**图1.3.1**所示。 + +### 音频输入输出 + +![耳机与麦克风](./images/K230_DEMO_BOARD_USAGE_GUIDE/image17.png) + +(**图2.5.1**:耳机与麦克风在DEMO BOARD上的位置) + +外接音频设备的区域,在此区域内的声音信号处理已全部在K230中完成,可直接接入耳机输出模拟信号,不需要进行改动。这个区块仅有模拟信号可用,另有数字声音信号从排针引出,通过I2S/PDM接口数字音频转接板在外部进行数模转化,这部分将在**章节2.7**中另行介绍。**图2.5.1**中编号对应如下2个主要接口/器件(名称与**图2.1.1**中右图的列表一致): + +1. **耳机(DEMO BOARD上器件编号:J7)** + +1. **麦克风(DEMO BOARD上器件编号:U29)** + +### 通用接口(常规开发方法) + +![数据接口](./images/K230_DEMO_BOARD_USAGE_GUIDE/image18.png) +(**图2.6.1**:数据接口在DEMO BOARD上的位置) + +与外部计算机/信息源的连接口集中处。**图2.6.1**中编号对应如下3个主要接口/器件(名称与**图2.1.1**中右图的列表一致): + +1. **USB 2.0(DEMO BOARD上器件编号:J11,J13)** +共计两路支持OTG的USB 2.0接口,直接与K230交互。J11对应USB0,J13对应USB1。 + +1. **TF卡槽/WIFI扩展(DEMO BOARD上器件编号:U4)** +K230支持从TF卡槽启动,此处是装载K230启动程序TF卡的位置。选择从TF卡启动的方式在**章节2.3**中已描述。此外,该卡槽可另接**章节1.3**清单中所述**WIFI子卡**,二者为复用关系。**WIFI子卡**用于为板面添加WIFI模块验证联网功能。该子卡具有TF卡槽金手指,直接嵌入TF卡槽即可正常使用。 + +1. **串口调试(DEMO BOARD上器件编号:J6)** +使用Type C数据线进行UART串口调试,串口速率默认为115200。 + +### 排针接口 + +![排针](./images/K230_DEMO_BOARD_USAGE_GUIDE/image19.png) +(**图2.7.1**:排针在DEMO BOARD上的位置,各排针的引脚1已圈出) + +板面上的电源以及部分来自K230 GPIO的信号通过这里的排针接出。**图2.7.1**中编号对应如下3个主要接口/器件(名称与**图2.1.1**中右图的列表一致): + +1. **电源监测扩展(DEMO BOARD上器件编号:J10)** +系研发时内部的测试用接口,在使用K230做产品开发时不需要使用。 + +1. **SDIO/I2S/PDM/IOMUX扩展(DEMO BOARD上器件编号:J8)** +接往K230上GPIO26-37的排针,对应的IO电平电压为1.8V。前文**章节2.5**中有提到,**章节1.3**所述的子卡清单中的**I2S/PDM接口数字音频转接板**应被放置于此处,用于将K230产生的数字音频从外部进行数模转换。将子板的排母与此处的排针引脚1对齐扣上即可使用。引脚定义详见其原理图。 +![SDIO/I2S/PDM/IOMUX扩展](./images/K230_DEMO_BOARD_USAGE_GUIDE/image21.png) +(**图2.7.2**:SDIO/I2S/PDM/IOMUX扩展-J8的原理图) + +1. **JTAG扩展(DEMO BOARD上器件编号:J12)** +连接JTAG调试器的端口。使用时用杜邦线将JTAG扩展上的引脚与相应的JTAG调试器端口相连。其引脚定义见**图2.7.4。** +![JTAG扩展](./images/K230_DEMO_BOARD_USAGE_GUIDE/image22.png) +(**图2.7.3**:JTAG扩展的引脚定义原理图,数据线通过10K电阻上拉至1.8V) + +1. **IOMUX/电源扩展(DEMO BOARD上器件编号:J5)** +USB与串口的控制排针,通过短接J5部分引脚的方可以改变**章节2.6**提到的两个USB接口的模式。J5的引脚定义见**图2.7.5。** +若需要USB0作为HOST使用,或者用于转以太网口时,则需使用跳线帽短接J5的引脚1,2,作为DEVICE时则保持引脚1,2开路。(交付时默认已短接) +相应的,USB1作为HOST使用,或者用于转以太网口时,在J5的引脚3,4上添加跳帽。(交付时默认未短接) +此外,引脚8,10可分别以UART_RX和UART_TX作为额外的一路调试串口使用**。** +![IOMUX/电源扩展](./images/K230_DEMO_BOARD_USAGE_GUIDE/image23.png) +(**图2.7.4**:IOMUX/电源扩展-J5的原理图) + +1. **ADC扩展(DEMO BOARD上器件编号:J15)** +K230有共计6个ADC输入口引出至J15处可以根据使用需求,收集传感器数据或者反馈信号。ADC的输入位置位于MIPI CSI接口旁边。其中ADC5(**图2.7.1**最右侧下数第二孔)与耳机复用,在未接入耳机时,该ADC输入将始终接地无法正常使用,请注意。若ADC5无读数,将耳机接入耳机孔即可。 diff --git a/zh/00_hardware/K230_PINOUT_V1.0_20230524.xlsx b/zh/00_hardware/K230_PINOUT_V1.0_20230524.xlsx new file mode 100755 index 0000000..8573188 Binary files /dev/null and b/zh/00_hardware/K230_PINOUT_V1.0_20230524.xlsx differ diff --git a/zh/00_hardware/K230_datasheet.md b/zh/00_hardware/K230_datasheet.md new file mode 100755 index 0000000..a1e7f58 --- /dev/null +++ b/zh/00_hardware/K230_datasheet.md @@ -0,0 +1,1254 @@ +# K230 Product Full Datasheet + +![cover](images/canaan-cover.png) + +Document version: V1.0 +Release date: 2023-7-6 + +
+ +## Disclaimer + +The products, services or features you purchase shall be subject to the commercial contracts and terms of Canaan Creative CO., LTD. (the "Company") and its affiliates, and all or part of the products, services or features described in this document may not be within the scope of your purchase or use. Unless otherwise agreed in the contract, the Company does not provide any express or implied representations or warranties as to the correctness, reliability, completeness, merchantability, fitness for a particular purpose and non-aggression of any statements, information, or content in this document.Unless otherwise agreed, this document is intended as a guide for use only. + +Due to product version upgrades or other reasons, the content of this document may be updated or modified from time to time without any notice. + +## Trademark Notice + +![logo](images/logo.png) +"Canaan" and other Canaan trademarks are trademarks of Canaan Creative CO., LTD. and its affiliates. All other trademarks or registered trademarks that may be mentioned in this document are owned by their respective owners. + +Copyright©2023 Canaan Creative CO., LTD. +This document is only suitable for the development and design of K230 platform, without the written permission of the company, any unit or individual shall not disseminate part or all of the content of this document in any form. + +Canaan Creative CO., LTD. +Website:canaan-creative.com +Business Email: + +
+ +## Preface + +### Purpose + +This document is intended to provide a full description of the K230 platform and its features. + +### Intended Audience + +The main people to whom this document (this guide) applies: + +- Design and maintenance personnel for electronic products +- Sales personnel for electronic products +- Technical support personnel + +### Terms + +### Revision history + +| Version Number | Modified by | Revision Date | Revision Notes | +| -------------- | -------------- | ------------- | --------------------------------------------------------------------------------- | +| V1.0 | Ruizheng Li,Heng Wen | 2023-7-6 | Revised version | +| | | | | + +
+ +## Index + +[TOC] + +
+ +## Chapter 1 Introduction + +### 1.1 Overview + +The K230 chip is the latest generation SoC product in Canaan Technology's (NASDAQ: CAN) Kendryte® series of AIOT chips. The chip adopts a brand-new multi-heterogeneous unit acceleration computing architecture, integrates two RISC-V C908 computing cores, and has a built-in new generation KPU (Knowledge Process Unit) intelligent computing unit. Multi-precision AI computing power with INT8 and INT16. Supports general AI computing framework. The chip also has a variety of peripheral interfaces, as well as multiple scalar, vector, graphics, and other dedicated hardware acceleration units such as image 2D engine, AI 2D engine, 2.5D GPU, and 3D depth engine. K230 provides full-process computing acceleration for various computing tasks such as images, videos, audio, AI, etc. The chip has many features such as low latency, high performance, low power consumption, fast startup, and high security. +K230 can be used in various smart hardware products, such as smart door locks, home smart security cameras, dictionary pens, payment recognition, 3D structured light vision modules, drones, interactive robots, smart home appliances, smart toys, and smart manufacturing, intelligent vehicle cockpit and many other fields. + +### 1.2 Feature + +#### 1.2.1 CPU subsystem + +- CPU0 subsystem + + - 64bit RISC-V processor + - Supports maximum 800 MHz working frequency + - Supports RISC-V 64GCB instruction set + - Cpu contains floating-point units (FPUs) + - L1 cache contains 32 KB instruction cache (I-cache) and 32 KB data cache (D-cache) + - Integrates with 128 KB L2 cache + - Supports memory management unit (MMU) + - Integrates with the interrupt controller (PLIC), which can process 208 interrupt external sources + - Supports the Joint Test Action Group (JTAG) debugging interface + - Supports WFI + +- CPU1 subsystem + + - 64bit RISC-V processor + - Supports maximum 1.6 GHz working frequency + - Supports RISC-V Vector Extension 1.0 specification + - Cpu contains floating-point units (FPUs) + - 128bits vector-process-unit + - L1 cache contains 32 KB instruction cache (I-cache) and 32 KB data cache (D-cache) + - Integrates with 256 KB L2 cache + - Supports memory management unit (MMU) + - Integrates with the interrupt controller (PLIC), which can process 208 interrupt external sources + - Supports the Joint Test Action Group (JTAG) debugging interface + - Supports WFI + +#### 1.2.2 KPU subsystem + +- Support INT8 and INT16 +- Support weight sparse compression +- Typical network performance: + - Resnet 50 ≥ 85fps @INT8 + - Mobilenet_v2 ≥ 670fps @INT8 + - YoloV5S ≥ 38fps @INT8 +- Support TensorFlow / PyTorch / TFLite / PaddlePaddle / ONNX +- Support quantization toolchain and profiling tools +- Loss of quantization accuracy <1% +- Support Abs, Acos, Acosh, And, ArgMax, ArgMin, Asin, Asinh, Add, AveragePool, BatchNormalization, Cast, Ceil, Celu, Clip, Concat, Constant, ConstantOfShape, Conv, ConvTranspose, Cos, Cosh, CumSum, DepthToSpace, DequantizeLinear, Div, Dropout, Elu, Equal, Exp, Erf, Expand, Flatten, Floor, Gather, GatherElements, GatherND, Gemm, GlobalAveragePool, GlobalMaxPool, Greater, GreaterOrEqual, Hardmax, HardSigmoid, HardSwish, Identity, InstanceNormalization, LpNormalization, LeakyRelu, Less, LessOrEqual, Log, LogSoftmax, LRN, LSTM, MatMul, MaxPool, Max, Min, Mod, Mul, Neg, Not, OneHot, Pad, Pow, PRelu, QuantizeLinear, QLinearConv, QLinearMatmul, RandomNormal, RandomNormalLike, RandomUniform, RandomUniformLike, Range, ReduceL1, ReduceL2, ReduceLogSum, ReduceLogSumExp, ReduceMax, ReduceMean, ReduceMin, ReduceProd, ReduceSum, ReduceSumSquare, Relu, Reshape, Resize, ReverseSequence, Round, ScatterND, Selu, Shape, Sin, Sinh, Sigmoid, Sign, Size, Slice, Softmax, Softplus, Softsign, SpaceToDepth, Split, Sqrt, Squeeze, Sub, Sum, Tanh, Tile, TopK, Transpose, Upsample, Unsqueeze, Where + +#### 1.2.3 2D Engine + +- 2D GDMA Engine + + - X-Mirror/Y-Mirror/Rotation(90/180/270) + - Typical image rotation capability: + - 2 x 1080\*1280 YUV400 @15fps + 1 x 1080\*1920 YUV420 @30fps + - Provides one physical DMA channel + - The axi data width is 64-bit + - Supports configurable axi transaction outstanding numbers: the max outstanding number is 8 + - Supports data transfer with the linked list + - Supports configurable weight-based channel priority arbitration + - Supports lowpower mode:each channel supports auto clock gate + - Supports configurable image row stride + - The maximum image resolution supports 64Kx64K + - The data width of the image pixel supports 8/16/24/32bits + - Max Burst length can be set to 8 or 4 for non-24bit width pixel, and 12 for 24bit pixel + +- Non AI 2D + - Support OSD mode + - Support CSC mode + - Support draw border mode + - Support corp operation + +- Independent AI 2D Engine + - Affine/Crop/Resize/Padding/Shift + - Resize + - Crop + - Affine + - The calculation of resize and affine coordinates supports opencv's round, as well as ceil and floor + - Pad + - Support four edge parts to complement constant pads, the pad value can be specified, and the maximum number of pads on a single side is 1023 + - CSC + - Both input and output images support the following formats + - YUV420_NV12 + - YUV420_NV12 + - YUV420_I420 + - YUV400 + - RGB_packed + - NCHW + + - Shift + + - RAW16 input -> shift to RAW8 output + + - Support CPU to read internal registers + + - The accelerator can access the system SRAM(2MB). + + - Support software reset through configuration register + + - Support clk gating + + **NOTE** + + - Note1: The highest source image resolution supports 4K + + - Note2: All configured ddr addresses follow 16B align, which is friendly to performance + + - Note3: A configuration register cannot exceed 1KB + + - Note4: When configuring cpu, configure 32bit each time, and configure 4 times for each 128bit, and must configure 4 times, the order is from low to high; when configuring GNNE, configure 128bit at a time + +#### 1.2.4 DPU (Depth Processing Unit) + +- Using 3D structured light depth calculation +- The maximum resolution of the landscape image is 1920\*1080, and the maximum resolution of the portrait image is 1080\*1440 +- Typical performance is 1280\*800@30fps, 1280\*1080@15fps,1920\*1080@9fps +- Both read and write AXI bus support crop +- Support standard axi-4 protocol, data bit width 64bit, address bit width 32bit, burst_length up to 16, read and write outstanding up to 8 +- Support standard apb3.0 protocol, data bit width 32bit, address bit width 32bit +- Img_check: The precision of the input speckle image is int8, the precision of the output calculation result is int1, and it supports output after downsampling +- LCN: The precision of the input speckle image is int8, and the precision of the output calculation result is int12, which supports normalized calculation of the source image +- SAD: Input the normalized speckle image/reference image, the accuracy is int12, the output row and column parallax accuracy is int16, support Init_SAD single/double layer enable, support SAD double layer enable, and support the first layer input of Init_SAD/SAD is involved in the calculation after 1/2 downsampling +- Post_proc: The precision of the input column parallax is int16, the precision of the output calculation result is int1, supports Post_proc enable, and supports Post_proc inner mask denoising enable +- Align: The precision of input column parallax is int16, the precision of mask is int1, the precision of output depth/disparity map is int16, the precision of input/output infrared map is int8, supports height block processing parallax/infrared alignment, supports parallax/infrared Alignment enable, support Align inner parallax denoising enable, support parallax/infrared up and down sampling enable, support Disp2depth enable +- Support normal calculation end interrupt, timeout interrupt, instruction exception interrupt, configuration instruction overflow interrupt, AXI write response exception interrupt +- Support independent soft reset, interrupt clear operation + +#### 1.2.5 Memory + +- DDR + + - 16-bit per channel LPDDR4, two channels, the max speed is 3200Mbps + - 32-bit LPDDR3 supported,the max speed is 2133Mbps + - Maximum capacity: 2GB + - Scalable 1:1/1:2 frequency ratio architecture. We setting 1:2 frequency ratio + - For LPDDR3 configurations, direct software request control or programmable internal control for ZQ short calibration cycles + - For LPDDR3 configurations, support for ZQ long calibration after self-refresh exit + - For LPDDR4 configurations, direct software request control or programmable internal control for ZQ calibration cycles + - For LPDDR4 configurations, support for ZQ calibration after SR-Powerdown exit + - Dynamic scheduling to optimize bandwidth and latency + - For maximum SDRAM efficiency, commands are executed out-of-order + - Hardware configurable and software programmable Quality of Service (QoS) support + - Programmable support for all of the following SDRAM data-bus widths: Full data-bus width or Half of the full data-bus width + - Supports max to 2 ranks + - Control options to avoid starvation of lower priorities + - Guaranteed coherency for write-after-read (WAR) and read-after-write (RAW) hazards (always on the HIF interface and on the AXI interface only if appropriate hardware configuration parameter and software register are set) + - Write combine to allow multiple writes to the same address to be combined into a single write to SDRAM; supported for same starting address + - Supports automatic SDRAM power-down entry and exit caused by lack of transaction arrival for a programmable time + - Supports automatic Clock Stop (LPDDR3/LPDDR4) entry and exit caused by lack transaction arrival + - Supports automatic low power mode operation caused by lack of transaction arrival for a rogrammable time through the Hardware Low Power Interface + - Flexible address mapper logic to allow application specific mapping of row, column, bank, and rank bits + - Leverages out of order requests with CAM to maximize throughput + - APB interface for the software accessible registers + - 5 host ports using AMBA AXI + - Automatic periodic retraining through PHY MASTER Interface + - Support for: + 1. (LPDDR3, LPDDR4) Command Bus eye training relative to CK + 1. Write Leveling to compensate for CK-DQS timing skew + 1. Write Training: DQS to DQ + Two modes of training are available in LPDDR4: + - Command-based FIFO WR/RD with user patterns + - An internal DQS clock tree oscillator, to determine the need for, and the magnitude of, required periodic training + 1. Data bus VREFDQ training + 1. Read training( DQ bit deskew training using DRAM mode registers and DQS to DQ eye centering training using DRAM array) + - LVSTL IO calibration and ODT calibration + - Support for a SW controllable DQ bit and AC bit swizzling + - Firmware-based 2D eye mapping diagnostic tool allows measuring 2D eye for every bit of the bus at both DRAM and host receivers + - Direct override programming available for all VREF, ODT, drive strength, and timing delays to facilitate debug and characterization + +- SRAM + - SRAM:2MB (shared sram)+2MB (default for KPU) + - The shared 2MB sram provides access to CPU/KPU/decompression and other modules + - The shared 2MB sram has two independent 128bit AXI4 Slave buses. Burst supports incremental, fixed, and wrap. The maximum burst length is 16. Exclusive transmission is not supported. The maximum outstanding read and write are 16 respectively + - The shared 2MB sram is divided into two groups. The first group is shared by KPU port0, axi slave0, axi slave1, and decompression module. When decompression does not work, KPU port0 has the highest priority, followed by axi slave0/axi slave1. The other group of KPU port1, axi slave 0, and axi slave 1 are shared. KPU port1 has the highest priority + - The decompression module shares 768KB SRAM to cache the decompression process data + +- Flash + + - Supports the SPI NOR flash and SPI NAND flash + - Supports the read and write operations in internal DMA mode for the SPI NAND flash and the SPI NOR flash. + - Support Enhanced (Dual/Quad/Octal) SPI features: + - Programmble address,instruction,wait cycles,and data frame size + - Dual Data Rate(DDR) support + - Read Data Strobe support for DDR transfer + - Data item size(4 to 32bits)-Item size of each data transfer under control of the programmer + - Execute In Place(XIP) mode support: + - AHB address is mapped to SPI NOR flash address directly + - Read and write SPI NOR flash directly + - Read and write SPI NAND flash need to operate according to the NAND flash operation requirement + - Except XIP mode, all operations need to operate according to the flash operation requirement + - Programmable delay on the sample time of received serial data bit(rxd) + - Programmable clock bit rate + - The latency of strb can be adjusted + + **Note:** + + If data frame size is set to 8bit and DDR mode is selected, one clock pulse corresponds to two byte data. So total data length must be set to an even number. + +#### 1.2.6 system component + +- RMU + + - Reset management module (RMU) is responable for power on reset deglitch, manage wdt reset,chip soft reset and generate sub-module reset + - Reset glitch length less than 8ms will be filtered + - Manage two watchdog reset and generate soc reset + - Manage software soc reset request and generate soc reset + - Manage sub-module software reset request and generate sub-module reset + +- CMU + + - Clock management module (CMU) is designed to manage generation of sub-module and system clock、clock division、clock switch and clock gating + - The clock source include external 24MHz OSC and four internal PLLs + - CPU1 and KPU module support DVFS. Their frequency should meet current voltage + - When CPU1 and KPU use the same clock source, their frequency can be changed synchronously + - When CPU1 and KPU use different clock source, their frequency can be changed independently + +- PWR + + - Power control module (PWR) is used for power control of SOC and sub-module + - There are five power mode : Power on, sleep0, sleep1, standby, powerdown + - There are three kinds of wakeup source : GPIO, PMU and timer + - Each power domain can be controlled to power down、power up 、clock gating according to defferent application + +- Interrupt + + - K230 supports 208 interrupt sources + +- PDMA + + - PDMA (Peripheral Direct Memory Access) supports the data transfer between peripheral ports and DDR/SRAM + - PDMA provides 8 channels to transfer different transactions, with 64-byte data buffer per channel + - It supports up to 35 peripheral ports through channel configuration + - Low power IDLE state of each channel can be set by shutting down corresponding clock + - A 64-bit AXI4 master is used to transfer different channel transactions + - The priority of each transaction is configured with each channel. Transactions with high priority gets high chance to be transferred + - Peripheral data address can only be accessed in 4 bytes aligned with strobe signal to indicate the lower 1/2/4 byte(s) are used, and only fixed address is supported + +- SDMA + + - Provides four DMA channels:ch0,ch1,ch2 and ch3 + - The axi data width is 64-bit + - The max axi burst length is 16 + - Supports configurable axi transaction outstanding numbers: the max outstanding number of ch0,ch2,ch3 is 2, the max outstanding number of ch1 is 16 + - Supports configurable data endian + - Supports data transfer with the linked list + - Supports configurable weight-based channel priority arbitration + - Supports lowpower mode:each channel supports auto clock gate + - Supports specified data transfer for decompression module using ch0 and ch1 + +- General-puspose timers + + - APB interface supports APB3 + - Up to six programmable timers + - Configurable timer width: 8 to 32 bits + - Support for two operation modes: free-running and user-defined count + - Support for independent clocking of timers + - Configurable polarity for each individual interrupt + - Configurable option for a single or combined interrupt output flag + - Configurable option to have read/write coherency registers for each timer + - connfigurable option to include timer toggle output, which toggles whenever timer counter reloads + - Configurable option to enable programmable pulse-width modulation of timer toggle outputs + - Configurable option to include pulse width modulation of timer toggle output with 0% and 100% + duty cycle. + - Can be used to count external input signal with frequency less than 1MHz and ducy cycle from 0~100% + +- Stc timer + + - 64 bit timer width + - 3 configurable timescale : 27MHz, 1MHz, 90KHz + - Configurable enable、load、clear control register + - Apb 3.0 interface + - One timer can be used for video-input/video-output and audio synchronization. + - One timer is used for cpu0 and one timer is used for cpu1. + - Timer used for video/audio synchronization provides two sets of timer value, one is old value and the other is latest value + +- Watchdog + + - APB3 interface support + - Watchdog counter width of 32 bits + - Counter counts down from a preset value to 0 to indicate the occurrence of a timeout + - If a timeout occurs the watchdog can perform one of the following operations: + - Generate a system reset + - First generate an interrupt and even if it is cleared (or not) by the service routine by the time a second timeout occurs then generate a system reset + - Programmable reset pulse length + +- RTC + + - Typical working frequency: external clock source 32768 Hz + - Involved in the work mode: normal working mode, independent power supply working mode + - Interface type: APB3.0 interface + - Support calendar initial value configuration, configuration items including year, month, day, week, when, minutes and seconds + - Can read less than 1 second counter count, and the initial values can be configured, minimum scale unit for each calibration cycle of the crystals + - Support disruption: a timer interrupt (configurable project includes year, month, day, week,, minutes and seconds), the interrupt for level interrupts, need to register to clear; Periodic interruption (including annual, monthly, daily, weekly, every hour, every minute, every second, every 1/8 of a second, 1/64 of a second trigger interrupt) the interrupts for pulse, pulse width is two 32768 hz clock cycles + - Typical application scenario: calendar, timing interrupt trigger interrupt trigger, cycle + - Other features: a regular in the system domain, need external power supply; A low speed clock of 32768Hz is required + +- Mailbox + + - Bus interface: Mailbox with APB 3.0 interface + - Data bit width: 32bit, configurable via APB bus + - Configuring the clock: configuring the clock to be the pclk clock + - Support for hardware locks + - Support for cpu0_sys and cpu1_sys to send interrupts to each other + - Support for register configuration and status reading of submodules + +- Temperature Sensor + + - ±3°C Accuracy Without Trimming + - Supply voltages: VDD 0.72-0.88V, VDDA 1.62-1.98V + - Temperature Measurement Range: -40 ~ 125℃ + +#### 1.2.6 Video input + +- Compatible with MIPI 1.2 RX protocol, max up to three 2lane sensors or one 4lane sensor and one 2lane sensor +- 3 x MIPI CSI +- Support sensor slave mode +- Support flash trigger mode which support both follow-strobe mode and pwm mode +- Support structured light sensor and can separate the IR data and speckle data to different DVP interface. +- Support timestamp +- Support HDR sensor +- Support hardware discard frame +- 8/10/12/16 Bit Bayer RAW + +#### 1.2.7 ISP + +- Total throughput:8MP@30fps +- Auto Focus measurement (AF) +- Auto White Balance measurement (AWB) +- Auto Exposure measurement (AE) +- Advanced 2DNR spatial noise reduction +- Advanced 3DNR: spatial and temporal noise reduction +- WDR in single wide dynamic frame +- Multi-exposure HDR (Native/Built-in HDR interface, 12~16-bit HDR input). The performance is up to 2960x1666@60fps for DOL2 and 1920x1080@90fps for DOL3 HDR. +- CPD, compand function to support native HDR sensor which performs HDR merging in sensor +- Variable sensor interface for RGB-Bayer Sensors, DOL or stagger HDR sensors +- 20-bit HDR Processing, includes multi exposure stitching and local tone mapping +- Test Pattern Generator (TPG) +- Black level Compensation +- Sensor Linear Correction +- Defect Pixel Cluster Correction (DPCC) +- Green Equalization +- Lens Shade Correction (De-Vignetting) +- De-warping, including fisheye correction, wide field of view (FOV) correction, keystone correction and scaling and 4PTZ view +- Digital Gain +- 2-Stage Adaptive Noise Filter (Noise reduction, Sharpness, Blurring) +- Enhanced Color Interpolation (Bayer De-mosaic filter) +- Chromatic Aberration Correction (CAC) +- Color Correction (Xtalk) Matrix (CCM) +- Color Space Conversion (CSC) +- Programmable gamma correction for sensor adaptation and display correction +- Histogram Calculation +- Anti-flicker +- Cropping of the output picture (to crop interpolation artifacts), also used for windowing +- Color Processing: Contrast, Saturation, Brightness, Hue (CPROC) +- Sharpen/Blur Filter +- Flash light control +- Mechanical shutter control +- Image size: horizontal size multiple of 8 and vertical size multiple of 4 +- Enhanced Chroma Noise Reduction (CNR) +- Video Stabilization (VSM) +- Multi-Context Management to support three sensors within a single ISP Core (MCM). In MCM mode, only DVP0 supports HDR + +#### 1.2.8 Video output + +- 1 x MIPI DSI, 1 x 4 lane or 1 x 2 lane +- Resolution: 2MP@60fps +- Support up to 13 layers, including 4 video layers, 8 OSD layers and 1 background layer. +- Support all common output picture formats: UXVGA (1600x1200), SXVGA (1280x1024), 1080p, 720p +- Video Layer 0: + - support scaling up and scaling down function + - support 2-plane, YUV420 data format input + - support configurable start pixel & start line input + - Support 90 °, 180 °, 270 ° rotation + - Support x-mirror/y-mirror function. +- Video Layer 1: + - support 2-plane, YUV420 data format input + - support configurable start pixel & start line input + - support 90 °, 180 °, 270 ° rotation + - Support x-mirror/y-mirror function. +- Video Layer 2 & Layer 3: + - Support 2-plane, YUV420 & YUV422 data format input + - Support configurable start pixel & start line input + - Do not support scaling function +- 8 OSD layers support 1 or 2 plane ARGB formats: + - RGB888 with separate alpha channel + - RGB565 with separate alpha channel + - ARGB8888 + - ARGB4444 + - ARGB1555 + - Monochrome(8-bit) +- Display mix: + - OSD layer support configurable global alpha blending or pixel by pixel alpha mode + - Video layer only support configurable global alpha + - Configurable output size and position for each layer +- Support vsync interrupt, DPI interface underrun interrupt and configurable output line number interrupt +- Support configurable color space conversion, yuv2rgb or rgb2yuv +- Support gamma correction on RGB data before output +- Support dither function + + **Note** +- When not using scaling, it is recommended to use layer1 (supports rotation but not scaling)/layer2 (does not support rotation and scaling)/layer3 (does not support rotation and scaling). The video layer can only use three layers +- When scaling is necessary and layer0 is required, the maximum frame rate at 1080p is 20fps, and 30 frames can be supported at 720p + +#### 1.2.9 video codec + + **video encoding** + General encoding features + +- Maximum encoding performance up to 8MP@20fps +- Stride support. +- Horizontal and vertical mirroring. +- CBR / VBR / CQP / ROI encoding +- Support for optional rotation of the source frame in 90 degree steps before encoding. Note If YUV422 is rotated by 90 degrees or 270 degrees and not converted to YUV420, the result is encoded as YUV440. + +The video processor supports encoding the following source-frame input formats: + +- 1-plane YUV422, scan-line format, interleaved in YUYV or UYVY order. Note YUV422 inputs can be converted to YUV420 format. +- 1-plane RGB, 8-bit, byte address order RGBA, BGRA, ARGB, or ABGR. +- 2-plane YUV420, scan-line format, chroma interleaved in UV or VU order. +- 3-plane YUV420, scan-line format. +- 3-plane YUV420 10-in-16 bit scan line format. Note Support for 3-plane formats is included to help you with testing. Do not use these for maximum performance. +- YUV420 10-bit, P010, little endian, MSB aligned. +- YUV420 10-bit, 2 × 2 tile format. + +Supported codecs + +The following codec standards are supported for encoding: + +- HEVC (H.265) Main. +- HEVC (H.265) Main 10 Profile. +- H.264 Baseline Profile (BP). +- H.264 Main Profile (MP). +- H.264 High Profile (HP). +- H.264 High 10 Profile. +- JPEG, baseline sequential, YUV420 and YUV422. Note Only the JPEG codec can encode YUV422. +- MJPEG + +HEVC (H.265) encoding features + +- The encoded bitstream complies with the HEVC (H.265) Main Profile. +- Maximum frame width of 4,096 pixels. +- Maximum frame height of 4,096 pixels. +- 8-bit or 10-bit sample depth with I and P frames. +- Progressive encoding with 64 × 64 CTU size. +- Tiled mode, up to four tiles, horizontal splits only. +- Wavefront parallel encoding. +- The Motion Estimation (ME) search window is ±128 pixels horizontally, ±64 pixels vertically. - ME search down to Quarter Picture ELement (QPEL) resolution. +- 8 × 8, 16 × 16, and 32 × 32 luma intra-modes. +- 4 × 4, 8 × 8, and 16 × 16 chroma intra-modes. +- 8 × 8, 16 × 16, and 32 × 32 inter-modes. +- 8 × 8, 16 × 16, and 32 × 32 transform size for luma. +- 4 × 4, 8 × 8, and 16 × 16 transform size for chromas. +- Skipped CUs, Merge modes. +- Deblocking. +- Sample Adaptive Offset (SAO). +- Constrained intra-prediction selectable. +- Fixed Quantization Parameters (QP) operation or rate-controlled operation. +- Rate controlled based on bitrate and buffer size settings. This is also known as leaky bucket. +- Long term reference frame. +- Selectable intra-frame refresh interval. +- Encoders do not prevent the output from exceeding the maximum number of bits per CTU. + +H.264 encoding features + +- The encoded bitstream complies with the Baseline, Main, High, and High 10 Profiles. +- Maximum frame width of 4,096 pixels. +- Maximum frame height of 4,096 pixels. +- I and P frames. +- Progressive encoding. +- Context Adaptive Binary Arithmetic Coding (CABAC) or Context Adaptive Variable Length Coding (CAVLC) entropy coding. Note B frames are not supported with CAVLC entropy coding. +- The Motion Estimation (ME) search window is ±128 pixels horizontally, ±64 pixels vertically. +- ME search down to Quarter Picture Element (QPEL) resolution. +- All 4 × 4, 8 × 8, 16 × 16 luma, and 8 × 8 chroma intra-modes evaluated. +- 8 × 8, and 16 × 16 inter-modes. +- 4 × 4 and 8 × 8 transform. +- Skipped macroblocks. +- Deblocking. +- Constrained intra-prediction selectable. +- Fixed QP operation or rate-controlled operation. +- Rate controlled based on bitrate and buffer size settings. This is also known as leaky bucket. +- Long term reference frame. +- Selectable intra-frame refresh interval. +- Escaping to prevent Network Abstraction Layer (NAL) unit start code emulation. This is always enabled and is independent of the NAL packet format setting. For more information, see ITU-T H.264 Annex B. Note Encoders do not prevent the output from exceeding the maximum number of bits per macroblock. + + **video decoding** + General decoding features + +- Maximum decoding performance up to 8MP@40fps +- Supported source frame output formats are: + - 2 plane YUV420 scan line format, chroma interleaved in UV or VU order. + - 3 plane YUV420 scan line format. Note Support for 3-plane formats is included to help you with testing. Do not use these for maximum performance. + - YUV420 10 bit, P010, little endian, MSB aligned. + - YUV420 10 bit, 2 × 2 tile format. Note The YUV buffer and stride must have correct alignment for maximum performance. +- Stride support for scan-line formats only. +- Support for rotation of the decoded frame in 90 degree steps before output. +- Support for downscaling the decoded frame horizontally and vertically by a factor of 2 or 4. +- Support for downscaling the decoded frame horizontally and vertically by any factor individually. The smallest resolution can be 2 x 2 pixels. +- Support for output of average frame luminance and chrominance for each 32 x 32 pixel block, for every output display frame. + +Supported codecs + +The following codec standards are supported for decoding: + +- HEVC (H.265) Main/Main10. +- H.264 Baseline, Main, High, and High10 Progressive Profile. +- JPEG, baseline sequential, YUV420 and YUV422. Note Only the JPEG codec can decode YUV422. + +HEVC (H.265) decoding features + +- The decoder is fully compliant to the Main and Main10 Profiles. +- Maximum frame width is 4,096 pixels. +- Maximum frame height is 4,096 pixels. +- Error concealment is performed in case of bit errors. +- Stream parameter information is output. + +H.264 decoding features + +- Baseline, Main, High, and High 10 progressive Profiles. +- For progressive streams + - Average bitrates up to 100MBit/s. + - Maximum frame width is 4,096 pixels. + - Maximum frame height is 4,096 pixels. +- For interlaced streams + - Average bitrates up to 50MBit/s. + - A maximum frame width of 2,048 pixels. + - A maximum frame height of 4,096 pixels. +- Error concealment is performed in case of bit errors. +- Stream parameter information is output. Escaping to prevent NAL unit start code emulation is always expected. This is independent of the NAL packet format setting. For more information, see ITU T H.264 Annex B. + +JPEG decoding features + +- Average bitrates up to 20MBit/s. +- Support for 4:2:0 output by the video encoder, baseline sequential YYYYCbCr interleaved MCU format only. +- Support for 4:2:2 output by the video encoder, baseline sequential YYCbCr interleaved MCU format only. +- Maximum frame width is 8,192 pixels. +- Maximum frame height is 8,192 pixels. +- Error concealment is performed in case of bit errors. + +#### 1.2.10 2.5D GPU + +- Support following Hardware Components + - Command list based DMAs, Fire and Forgot Control mechanism to minimize CPU overhead + - Primitive Rasterizer, 16x Anti-aliasing without performance drop. + - Texture Mapping Unit, 4 Texel/cycle in Bi-linear filter + - Hardware composition, Frame buffer compression + - Tessellation, No CPU Involved in Bezier Curve generation + - Alpha blending +- Support Image Transformation + - Texture mapping, Point sampling, Bilinear filtering + - Blit support, Stretch (independently on x and y axis) + - Rotation any angle, Mirroring, FP24 coordinate precision, no precision difference in any degree rotation + - 2.5D Perspective Correct Projections + - Configurable Coordinate Systems and Transformations (3x3 matrix) + - Scissoring and viewport clipping, Mage Interpolation, Paint + - Odd/even and non-zero fill rules +- Support draw engine + - Pixel / Line drawing with any degree + - Gradient Filled rectangles + - Triangles, Polygon + - Path Generation + - Linear gradient paint paths +- Support following Color Formats + - 32-bit RGBA8888 / BGRA8888 / ABGR8888 + - 16-bit RGBA5551 / RGB565 + - 8-bit Α8 / L8 / RGB332, 4-bit A4 / L4 & 2-bit A2 / L2 & 1-bit A1 / L1 + - 1/2/4/8-bit index format +- Support Antialiasing + - 16x MSAA(4x4), no quality difference betwwen horizon and vertical direction + - 8x MSAA(4x2), low cost version, horizon quality is better than veritical directon + +#### 1.2.11 Audio + +K230 audio supports the following features: + +- Audio codec inside +- 2 DAC channels for stereo playback with sample rate 8-192Khz +- 2 ADC channels for stereo recording from microphone with sample rate 8-192Khz +- Audio codec support Automatic Level Control (ALC) function to adjust the signal level,which is input into ADC +- Maximum 8 x PDM DMIC inputs +- I2S interface supports 2x2 expansion +- Support master mode, which means clock(pdm_clk and i2s_sclk) and ws(only I2S) are output from audio. +- I2S input, pdm input and I2s output audio modes can work simultaneously +- APB2.0 interface is used to configure registers, and read/write PCM data. The default frequency of configurable APB working clock PCLK is 100MHz, and the data interface is 32 bits +- PCM data can be transferred by PDMA. Burst length in PDMA is configurable +- The audio module can start working again after being disabled and re-enabled +- The audio module can start working again after asserting reset and de-asserting reset +- PDM audio + - PDM audio input with data sampling rate of 2.048/2.8224 MHz, 1-bit data width, sampling clock rate of 0.256MHz/0.384MHz/0.512MHz/0.768MHz/1.024MHz/1.4112MHz/1.536MHz/2.048MHz/2.8224MHz/3.072MHz/4.096MHz/5.6448MHz/6.144MHz/12.288MHz/24.576MHz, corresponding PCM sampling rate of 8kHz/12kHz/16kHz/24kHz/32kHz/44.1kHz/48kHz/96kHz/192kHz + - Oversampling rate is configurable with x128, x64 and x32 + - 1-4 IOs are used for input PDM audio + - The input can be configured with 1-8 PDM channels. It supports left/right mono mode and dual mode of PDM. All IO channel modes are unified. The maximum number of IO in dual mode is 4 + - The serial numbers of enabled channels are from small to big. Random enabling of each channel is not supported + - The skew between PDM input data and pdm_clk is up to 18 PCLK cycles + - Conversion from input PDM audio data to PCM audio data +- I2S audio + - PCM audio in I2S Phillips, left-aligned and right-aligned format + - I2S audio input/output with data sampling rate of 8kHz/12kHz/16kHz/24kHz/32kHz/44.1kHz/48kHz/96kHz/192kHz, and data width of 32 bits. The valid data width(32/24/20/16/12bits) needs to be customized. The sampling clock rate supports 2×32(data width)×data sampling rate + - 1-2 IO to input, and 1-2 IO to output I2S audio data. The full-duplex mode is supported + - Connect to on-chip or off-chip i2s codec to input and output audio data + - Each RX/TX channel FIFO depth is 8. FIFO threshold can be configured + - DMA mode enable and disable + - IO number and left/right channel flag can be fetched from higher bits of data when valid data width is less than 32bits in DMA mode + +#### 1.2.12 peripheral + +- UART + - Support 5 UART interface + - 9-bit serial data support + - False start bit detection + - Programmable fractional baud rate support + - APB data bus widths of 32 + - Additional DMA interface signals for compatibility with DMA interface, DMA interface signal active low + - Transmit and receive FIFO depths of 32, Supports 32x32-bit transmit first-in, first-out (FIFO) and 32x32-bit RX FIFO, Internal FIFO (RAM) + - Busy functionality + - Functionality based on the 16550 industry standard + - Programmable character properties, such as: + - Number of data bits per character (5-8) + - Optional parity bit (with odd, even select or Stick Parity) + - Number of stop bits (1, 1.5 or 2) + - Line break generation and detection + - DMA signaling with two programmable modes + - Prioritized interrupt identification + - Programmable FIFO enable/disable + - Separate system resets for each clock domain to prevent metastability + +- I2C + - Support 5 I2C interface + - Two-wire I2C serial interface–consists of a serial data line (SDA) and a serial clock (SCL) + - Three speeds: + - Standard mode (0 to 100 Kb/s) + - Fast mode (≤400 Kb/s) or fast mode plus (≤1000 Κb/s) + - High-speed mode (≤3.4 Mb/s) + - Clock synchronization + - Master I2C + - 7- or 10-bit addressing + - 7- or 10-bit combined format transfers + - Bulk transmit mode + - Transmit and receive buffers + - 32x32 bits TX FIFOs and 64x8 bits RX FIFOs + - Interrupt or polled-mode operation + - Handles Bit and Byte waiting at all bus speeds + - DMA operation. + - Programmable SDA hold time (tHD;DAT) + - Bus clear feature + - Device ID feature + - Support for APB data bus widths of 32 bits + +- PWM + + - Support 6 channel + - Interface of APB 3.0, width 32 bit data; Slave Error response is not supported + - Support arbitrary duty ratio + - Support programmable output waveform (support two adjacent channel output waveform and even) + - Support produce periodic pulse signal of pulse signal and one-time + - Precise interruption generator can be used as a cycle + - Support output burr elimination + +- GPIO (multiplexed with function pins): + - 64 x GPIO + 8 x PMU GPIO + - 50 x GPIO + 6 x PMU GPIO(SIP) + - Separate data registers and data direction registers for each signal + - Configurable hardware and software control for each signal, or for each bit of each signal Separate auxiliary data input, data output, and data control for each I/O in Hardware Control mode. As output, each GPIO can be set to 0 or 1 separately. + - Independently controllable signal bits + - Configurable interrupt mode for GPIO group0 and GPIO group1. As input, each GPIO pin can act as an interrupt source. IO both edge interrupts. + - Configurable debounce logic with an external slow clock to debounce interrupts + - Option to generate single or multiple interrupts + - Configurable reset values on output signals + - Configurable synchronization of interrupt signals + - 32-bit APB width + +- USB + + - Support 2 USB 2.0 OTG + - Support for the following speeds:High-Speed (HS, 480-Mbps),Full-Speed (FS, 12-Mbps) and Low-Speed (LS, 1.5-Mbps) modes + - Multiple options available for low power operations + - DMA mode access support on the application side + - Supports up to 6 bidirectional endpoints, including control endpoint 0 + - Supports the Keep-Alive in Low-Speed mode and SOFs in High/Full-Speed modes + - The USB 2.0 modules supports the following transfer types:Control transfer,Bulk transfer,Interrupt transfer,isochronous transfer + - Internal DMA mode has two modes of operation: Buffer DMA mode and Scatter/Gather DMA mode + - Total Data FIFO RAM Depth is 3072 + - Not support ADP/HNP/SRP/Battery Charger + +- SD/EMMC + - Support 2 SDxC: SD3.01, eMMC 5.0 + - The eMMC/SD/SDIO controller features as below. + + - Supports SD memory and SD Input/Output (SDIO) digital interface protocol, and compliant with SD HCI specification + - Uses the same SD-HCI register set for eMMC transfers + - Supports eMMC protocols including eMMC 5.1 + - Supports SD-HCI Host version 3 mode or less + - Supports the following data transfer types for SD, eMMC modes: + - CPU + - SDMA + - ADMA2 + - ADMA3 + - Supports independent controller, AMBA Slave interface and Master Interface clocks + - Supports gating of controller base clock if Host Controller is inactive + - Support context aware functional clock gates + - Applications can gate the slave interface clock if Host Controller is inactive + - Supports interrupt enabling and masking + - Supports Command Queuing Engine (CQE) and compliant with eMMC CQ HCI + - Programmable scheduler algorithm selection of task execution + - Supports data prefetch for back-to-back WRITE operations + - Supports auto-tuning + - Support clock gating + + - Support features for interfaces + + - SD + - Supports 4-bit interface + - Supports UHS-I mode + - Supports Default Speed (DS), high-speed (HS), SDR12, SDR25, SDR50 and SDR104 speed modes + - Supports SDIO read wait + - Supports SDIO card interrupts in both 1-bit and 4-bit modes + - Wake up on card interrupt + - eMMC + - Supports 4-bit/8-bit interface + - Supports legacy, high-speed SDR, high-speed DDR, HS200, and HS400 speed modes + - Supports boot operation and alternative boot operation + +- SPI + - Support 3 SPI interface : 1 x OSPI + 2 x QSPI + - Supports AHB Slave Interface for software programming(AMBA 3) + - Supports AXI Master Interface for Internal DMA transfers + - AMBA 3 AXI + - AXI data width : 64 + - AXI address width : 32 + - Supports two separate FIFOs. One acts as an RX FIFO and the other one acts as a TX FIFO. Each of them is 256-location deep + - Enhanced SPI features (Dual/Quad/Octal for OSPI, Dual/Quad for QSPI) + - Programmble address,instruction,wait cycles,and data frame size + - Supports programmable serial data frame length: 4 bits to 32 bits + - Programmable delay on the sample time of received serial data bit(rxd) + - Programmable clock bit rate + +#### 1.2.13 security + +- Support PUF / OTP / TRNG +- Support following symmetric algorithm + - AES128/192/256 + - CMAC128/192/256 + - SM4-128 + +- Support following asymmetric algorithm + - RSA-1024/2048/3072/4096 + - RSA encrypt/decrypt/signature/verify + - ECC-163/233/283/409/571/192/224/256/384/521 + - ECDSA-233/283/409/571/224/256/384/521 + - ECC CDH-163/233/283/409/571/192/224/256/384/521 + - SM2 encrypt/decrypt/signature/verify + +- Support following hash algorithm + - HMAC + - SHA224/256/384/512, SHA_512/224, SHA_512/256 + - SM3 + +- TRNG + - 160Mbps@20Mhz + - Stabilization time minimum than 50us + +- OTP program region has raw OTP density 32Kbits, with security protection +- Support security boot with signature + +#### 1.2.14 PMU + +- Support RTC function in 32Khz +- Support the default 6 inputs and 2 outputs +- Support IO configurable, reusable as GPIOs, the highest rate of up to 25 MHZ +- Support a set of long and short press detection function which can be used as system shutdown or wakeup signal +- Support a set of edge number counter which can be regularly cleared +- Support two sets of edge and level detection with debounce function +- Support four groups of edge and level detection +- Support configurable interrupt operation +- Support 512 bits system log when it is been shutdown +- Support two sets of output IOs with configurable delay time + +#### 1.2.15 Others + +- decompression + + - Decompression accelerator is mainly used to implement hardware GZIP decompression function. + - Decompression bandwidth ≥ 400MB/s + - Support GZIP file format version 4.3 + - Support DEFLATE compressed file version 1.3 + - The maximum dictionary size is 32KB + - Support the minimum word matching length of 3Byte and the maximum word matching length of 258Byte + - Only dynamic huffman compression mode is supported + - Support data stream CRC32 verification + - Support hardware to automatically generate dynamic huffman tree + - The APB3 register interface is used to configure the startup decompression accelerator + - Request the DMA controller to transfer large blocks through hardware, and request to transfer 32Kbyte at most once + +- FFT/IFFT + + - Support maximum 4096 point fft, ifft calculation + - Support int16 calculation accuracy, the real and imaginary parts of input and output are both in int16 format + - Support the standard axi4 slave interface, which is used for parameter configuration and data transfer. + - The input supports RIRI...., RRRR.... (singal real part), RRRR...IIII... format arrangement, and the output supports RIRI...., RRRR...IIII... format arrangement + - It adopts the calculation method of base 2-time decimation, and there is only one butterfly operator inside + - A single clock domain design is adopted, and the bus clock is also used as the operation clock + - The calculation time of 4096-point fft/ifft is controlled within 1ms, including the total overhead of data movement, calculation, and interrupt interaction + - Support interrupt mask, original interrupt query + +- Fastboot: 3A first picture ≤ 400ms +- Working environment temperature: -40 ~ 85°C + +### 1.3 Block Diagram + +
Figure 1-3-1 K230 block diagram
+ +![K230_block_diagram.png](images/K230_block_diagram.png) + +## Chapter 2 Package Information + +K230 have two types of package, one is K230 that has a single die, the other is K230D that merges a 1Gb LPDDR4. + +## 2.1 K230 + +
Figure 2-1-1 K230 Package
+ +![K230_package](./images/K230_package.png) + +### 2.2 K230D + +
Figure 2-2-1 K230D Package
+ +![K230_package](./images/K230D_package.png) + +### 2.3 Pin information description + +This part please refer to《K230_PINOUT_V1.0_20230524》document. + +## chapter 3 Electrical Specification + +### 3.1 Absolute Max Rating + +
Table 3-1-1 Absolute Max Rating
+ +| | Power Parameter | Min | Max | Units | +| ------------ |:--------------- | ---- | --------------- | ----- | +| PMU | AVDD1P8_RTC | -0.1 | 1.98 | V | +| PMU | AVDD1P8_LDO | -0.1 | 1.98 | V | +| CORE | VDD0P8_CORE | -0.1 | 0.88 | V | +| CPU | VDD0P8_CPU | -0.1 | 0.88 | V | +| KPU | VDD0P8_KPU | -0.1 | 0.88 | V | +| DDR | VDD0P8_DDR_CORE | -0.1 | 0.88 | V | +| DDR | VDD1P1_DDR_IO | -0.1 | 1.21/1.32/1.485 | V | +| DDR | VAA_DDR | -0.1 | 1.98 | V | +| IO | VDDIO3P3_0 | -0.1 | 1.98/3.63 | V | +| IO | VDDIO3P3_1 | -0.1 | 1.98/3.63 | V | +| IO | VDDIO3P3_2 | -0.1 | 1.98/3.63 | V | +| IO | VDDIO3P3_3 | -0.1 | 1.98/3.63 | V | +| IO | VDDIO3P3_4 | -0.1 | 1.98/3.63 | V | +| IO | VDDIO3P3_5 | -0.1 | 1.98/3.63 | V | +| USB | AVDD3P3_USB | -0.1 | 3.63 | V | +| USB | AVDD1P8_USB | -0.1 | 1.98 | V | +| PLL | AVDD0P8_PLL | -0.1 | 0.88 | V | +| MIPI | AVDD0P8_MIPI | -0.1 | 0.88 | V | +| MIPI | AVDD1P8_MIPI | -0.1 | 1.98 | V | +| ADC | AVDD1P8_ADC | -0.1 | 1.98 | V | +| AUDIO CODEC | AVDD1P8_CODEC | -0.1 | 1.98 | V | +| MMC | VDD3P3_SD | -0.1 | 3.63 | V | +| SYSTEM | VDD1P8 | -0.1 | 1.98 | V | +| K230D LPDDR4 | VDD1P8_DDR_VDD1 | -0.1 | 1.98 | V | +| K230D LPDDR4 | VDD1P1_DDR_VDD2 | -0.1 | 1.21 | V | +| K230D LPDDR4 | VDD1P1_DDR_VDDQ | -0.1 | 1.21 | V | + +### 3.2 Recommended Operating Condition + +
Table 3-2-1 Recommended operating conditions for power supplies
+ +| Module | Parameter | Min | Typical | Max | Units | +| ------------ |:--------------- | --------------- | ------------ | --------------- | ----- | +| PMU | AVDD1P8_RTC | 1.674 | 1.8 | 1.98 | V | +| PMU | AVDD1P8_LDO | 1.674 | 1.8 | 1.98 | V | +| CORE | VDD0P8_CORE | 0.72 | 0.8 | 0.88 | V | +| CPU | VDD0P8_CPU | 0.72 | 0.8 | 0.88 | V | +| KPU | VDD0P8_KPU | 0.72 | 0.8 | 0.88 | V | +| DDR | VDD0P8_DDR_CORE | 0.744 | 0.8 | 0.88 | V | +| DDR | VDD1P1_DDR_IO | 1.06/1.14/1.283 | 1.1/1.2/1.35 | 1.21/1.32/1.485 | V | +| DDR | VAA_DDR | 1.674 | 1.8 | 1.98 | V | +| IO | VDDIO3P3_0 | 1.62/2.97 | 1.8/3.3 | 1.98/3.63 | V | +| IO | VDDIO3P3_1 | 1.62/2.97 | 1.8/3.3 | 1.98/3.63 | V | +| IO | VDDIO3P3_2 | 1.62/2.97 | 1.8/3.3 | 1.98/3.63 | V | +| IO | VDDIO3P3_3 | 1.62/2.97 | 1.8/3.3 | 1.98/3.63 | V | +| IO | VDDIO3P3_4 | 1.62/2.97 | 1.8/3.3 | 1.98/3.63 | V | +| IO | VDDIO3P3_5 | 1.62/2.97 | 1.8/3.3 | 1.98/3.63 | V | +| USB | AVDD3P3_USB | 3.07 | 3.3 | 3.63 | V | +| USB | AVDD1P8_USB | 1.674 | 1.8 | 1.98 | V | +| PLL | AVDD0P8_PLL | 0.72 | 0.8 | 0.88 | V | +| MIPI | AVDD0P8_MIPI | 0.744 | 0.8 | 0.88 | V | +| MIPI | AVDD1P8_MIPI | 1.674 | 1.8 | 1.98 | V | +| ADC | AVDD1P8_ADC | 1.62 | 1.8 | 1.98 | V | +| AUDIO CODEC | AVDD1P8_CODEC | 1.62 | 1.8 | 1.98 | V | +| MMC | VDD3P3_SD | 2.7 | 3.3 | 3.63 | V | +| SYSTEM | VDD1P8 | 1.62 | 1.8 | 1.98 | V | +| K230D LPDDR4 | VDD1P8_DDR_VDD1 | 1.7 | 1.8 | 1.98 | V | +| K230D LPDDR4 | VDD1P1_DDR_VDD2 | 1.06 | 1.1 | 1.21 | V | +| K230D LPDDR4 | VDD1P1_DDR_VDDQ | 1.06 | 1.1 | 1.21 | V | + +### 3.3 DC Characteristics + +#### 3.3.1 Electrical Characteristics for General IO + +
Table 3-3-1 Electrical Characteristics for General IO
+ +![GPIO_ecectric](./images/GPIO_electric.png) + +#### 3.3.2 Electrical Characteristics for PLL + +
Table 3-3-2 Electrical Characteristics for PLL
+ +| Parameter | Description | Min | Type | Max | Units | +| --------- | --------------------------------- | ---- | ---- | --- | ------------------------- | +| Fref | Divided reference frequency range | 488K | | 4G | Hz | +| Fout | Total output frequency range | 50M | NA | 4G | Hz | +| Fvco | VCO frequency range | 800M | NA | 4G | Hz | +| Tlt | Lock time | 500 | | | div referency clock cycle | +| Ijitter | input jitter | | 2% | | div referency clock cycle | + +### 3.3.3 Electrical Characteristics for DDR + +
Table 3-3-3 common DC input conditions
+ +| Parameter | Symbol | Unit | Minimum | Typical | Maximum | +| ------------------------------------------------- | ------ | ---- | --------- | ------- | --------- | +| Vref input leakage current | IIZ | uA | | | 50 | +| BP_DAT input leakage current | IIZ | uA | | | 50 | +| Input high voltage for BP_DAT* | VIH-DC | V | Vref+0.02 | | | +| Input low voltage for BP_DAT* | VIL-DC | V | | | Vref-0.02 | +| Differential input voltage for abs(DQS_t – DQS_c) | VID-DC | V | 0.1 | | | +| | | | | | | +| Note: | | | | | | + +1. BP_DAT *represent the DDR_DQ* Pins +1. BP_A *represent the DDR_CA* Pins + +
Table 3-3-4 common AC input conditions
+ +| Parameter | Symbol | Unit | Minimum | Typical | Maximum | +| ----------------------------- | ------- | ---- | ------- | ------- | ------- | +| Input capacitance DQ | CpadDQ | pF | 1.54 | 1.62 | 1.76 | +| Input capacitance DQS | CpadDQS | pF | 1.44 | 1.56 | 1.66 | +| Input capacitance,address/cmd | CpadAC | pF | 1.71 | 1.81 | 1.94 | +| | | | | | | +| Note: | | | | | | + +1. This is specified at the top level of the DBYTE and ACX4 blocks. It does not include any customer-supplied routing between these blocks and the C4 bump. +1. Effective parallel capacitance when ODT of 60ohm is enabled。 + +
Table 3-3-5 common input conditions
+ +| Parameter | Symbol | Unit | Minimum | Maximum | +| -------------------------------------------- | -------------- | ---- | ------- | ------- | +| M_DQ edge arrival relative to M_DQS,800MT/s | tDQSDQRead800 | UI | -0.39 | 0.39 | +| M_DQ edge arrival relative to M_DQS,1066MT/s | tDQSDQRead1066 | UI | -0.38 | 0.38 | +| M_DQ edge arrival relative to M_DQS,1333MT/s | tDQSDQRead1333 | UI | -0.37 | 0.37 | +| M_DQ edge arrival relative to M_DQS,1600MT/s | tDQSDQRead1600 | UI | -0.36 | 0.36 | +| M_DQ edge arrival relative to M_DQS,1866MT/s | tDQSDQRead1866 | UI | -0.35 | 0.35 | +| M_DQ edge arrival relative to M_DQS,2133MT/s | tDQSDQRead2133 | UI | -0.34 | 0.34 | +| M_DQ edge arrival relative to M_DQS,2400MT/s | tDQSDQRead2400 | UI | -0.33 | 0.33 | +| M_DQ edge arrival relative to M_DQS,2667MT/s | tDQSDQRead2667 | UI | -0.32 | 0.32 | +| M_DQ edge arrival relative to M_DQS,3200MT/s | tDQSDQRead3200 | UI | -0.31 | 0.31 | + +Note: + +1. This timing parameter applies to all BP_DAT DQ bits within a related DQ byte +1. A larger range implies more margin for channel and DRAM timing effects +1. Per lane deskew training can correct for static skew, up to deskew limits +1. Refer to the receiver timing budget in the Signal and Power Integrity Application Note for more information + +
Table 3-3-6 LPDDR3 DC input conditions
+ +| Parameter | Symbol | Unit | Minimum | Typical | Maximum | +| ------------------------------------------------- | ---------- | ---- | ---------------------------- | -------- | ------- | +| Reference voltage | Vref | V | | Variable | | +| DC reference voltage error | VrefDC-err | VDDQ | -0.75% | | 0.75% | +| On-die termination (ODT) programmable resistances | RTT | ohm | open, 240,120, 80, 60,48, 40 | | | +| ODT low-level (0.5*VDDQ) largesignal resistance | RODT-L/RTT | | 0.9 | 1.0 | 1.1 | +| ODT mid-level (0.8*VDDQ) largesignal resistance | RODT-M/RTT | | 0.8 | | 1.05 | +| ODT high-level (1.1*VDDQ) largesignal resistance | RODT-H/RTT | | 0.75 | | 1.05 | + +
Table 3-3-7 LPDDR3 AC input conditions
+ +| Parameter | Symbol | Unit | Minimum | Typical | Maximum | +| ---------------------------------------------------- | ------------- | ---- | ------------ | ------- | ------------ | +| Reference voltage | VrefAC-err | VDDQ | -0.25% | | 0.25% | +| Low-speed Input high voltage for BP_DAT (logic 1) | VIH-ACLS | V | Vref + 0.070 | | VDDQ +0.15 | +| Low-speed Input low voltage for BP_DAT (logic 0) | VIL-ACLS | V | -0.15 | | Vref - 0.070 | +| High-speed input high voltage for BP_DAT (logic 1) | VIH-ACHS | V | Vref + 0.070 | | Vref + 0.440 | +| High-speed input low voltage for BP_DAT (logic 0) | VIL-ACHS | V | Vref - 0.440 | | Vref - 0.070 | +| ODT low-level (0.5*VDDQ) smallsignal resistance | RODTss-M /RTT | | 0.95 | | 1.75 | +| ODT mid-level (0.8*VDDQ) smallsignal resistance | RODTss-M /RTT | | 0.85 | | 1.05 | +| ODT high-level (1.1*VDDQ) smallsignal resistance | RODTss-H /RTT | | 0.75 | | 1.05 | +| Input crossing voltage for differential signals DQS* | VIX | mV | VDQSavg-75 | VDQSavg | VDQSavg +75 | + +
Table 3-3-8 LPDDR4 DC input conditions
+ +| Parameter | Symbol | Unit | Minimum | Typical | Maximum | +| ------------------------------------------------- | ---------- | ---- | ---------------------------- | -------- | ------- | +| Reference voltage | Vref | V | | Variable | | +| DC reference voltage error | VrefDC-err | VDDQ | -0.75% | | 0.75% | +| On-die termination (ODT) programmable resistances | RTT | ohm | open, 240,120, 80, 60,48, 40 | | | +| ODT mid-level (0.25*VDDQ) largesignal resistance | RODT-M/RTT | | 0.8 | | 1.1 | +| ODT high-level (0.5*VDDQ) largesignal resistance | RODT-H/RTT | | 0.9 | 1.0 | 1.1 | + +
Table 3-3-9 LPDDR4 AC input conditions
+ +| Parameter | Symbol | Unit | Minimum | Typical | Maximum | +| ---------------------------------------------------- | ------------- | ---- | ------------ | ------- | ------------ | +| Reference voltage | VrefAC-err | VDDQ | -0.25% | | 0.25% | +| Low-speed Input high voltage for BP_DAT (logic 1) | VIH-ACLS | V | Vref + 0.070 | | VDDQ +0.15 | +| Low-speed Input low voltage for BP_DAT (logic 0) | VIL-ACLS | V | -0.15 | | Vref - 0.070 | +| High-speed input high voltage for BP_DAT (logic 1) | VIH-ACHS | V | Vref + 0.070 | | Vref + 0.440 | +| High-speed input low voltage for BP_DAT (logic 0) | VIL-ACHS | V | Vref - 0.440 | | Vref - 0.070 | +| ODT mid-level (0.25*VDDQ) smallsignal resistance | RODTss-M /RTT | | 0.9 | | 1.1 | +| ODT high-level (0.5*VDDQ) smallsignal resistance | RODTss-H /RTT | | 0.95 | | 1.75 | +| Input crossing voltage for differential signals DQS* | VIX | mV | VDQSavg-75 | VDQSavg | VDQSavg +75 | + +#### 3.3.4 Electrical Characteristics for MIPI DSI + +
Table 3-3-10 Supply Requirements
+ +| Symbol | Parameter | Condition | Minimum | Typical | Maximum | Unit | +| ------ | ------------------ | --------- | ------- | ------- | ------- | ---- | +| Vslew | Supplies slew rate | | | | 0.1 | V/μs | + +
Table 3-3-11 Input DC Specifications
+ +| Symbol | Parameter | Condition | Minimum | Typical | Maximum | Unit | +| ---------------------------------- | ---------------------------------------- | --------------------------------------------------------------------------- | ------- | ------- | ------- | ---- | +| Apply to CLKP/N and DATAP/N Inputs | | | | | | | +| VI | Input signal voltage range | | -50 | | 1350 | mV | +| ILEAK | Input leakage current | VGNDSH(min) ≤ VI ≤ VGNDSH(max) + VOH(absmax) Lane module in LP receive mode | -10 | | 10 | μA | +| VGNDSH | Ground shift | | -50 | | 50 | mV | +| VOH(absmax) | Maximum transient output voltage level | | -0.15 | | 1.45 | V | +| tVOH(absmax) | Maximum transient time above VOH(absmax) | | | | 20 | ns | + +
Table 3-3-12 HS Line Drivers DC Specifications
+ +| Symbol | Parameter | Condition | Minimum | Typical | Maximum | Unit | +| ---------------- | ----------------------------------------------------------------------- | -------------------------------------------------------------------------------------------------- | ------- | ------- | ------- | ---- | +| |VOD| | HS Transmit Differential output voltage magnitude | 80 Ω ≤ RL ≤ 125 Ω Note: can be programmed using test control register 0x24(cb_sel_v400_prog[2:0]). | 140 | 200 | 270 | mV | +| ∆|VOD| | Change in Differential output voltage magnitude between logic states | 80 Ω ≤ RL ≤ 125 Ω | | | 14 | mV | +| VCMTX | Steady-state common-mode output voltage | 80 Ω ≤ RL ≤ 125 Ω | 150 | 200 | 250 | mV | +| ∆VCMTX(1,0) | Changes in steady-state common-mode output voltage between logic states | 80 Ω ≤ RL ≤ 125 Ω | | | 5 | mV | +| VOHHS | HS output high voltage | 80 Ω ≤ RL ≤ 125 Ω | | | 360 | mV | +| ZOS | Single-ended output impedance | | 40 | 50 | 62.5 | Ω | +| ∆ZOS | Single-ended output impedance mismatch | | | | 10 | % | + +
Table 3-3-13 LP Line Drivers DC Specifications
+ +| Symbol | Parameter | Minimum | Typical | Maximum | Unit | +| ------------ | ------------------------------------------------------------- | ------- | ------- | ------- | ---- | +| VOL | Output low-level SE voltage | -50 | | 50 | mV | +| VOH | Output high-level SE voltage | 1.1 | 1.2 | 1.3 | V | +| ZOLP | Single-ended output impedance | 110 | | | Ω | +| ∆ZOLP(01,10) | Single-ended output impedance mismatch driving opposite level | | | 20 | % | +| ∆ZOLP(00,11) | Single-ended output impedance mismatch driving same level | | | 5 | % | + +
Table 3-3-14 LP Line Receiver DC Specifications
+ +| Symbol | Parameter | Minimum | Typical | Maximum | Unit | +| -------- | ------------------------------ | ------- | ------- | ------- | ---- | +| VIL | Input low voltage, not in ULPS | | | 550 | mV | +| VIL-ULPS | Logic 0 input voltage, ULPS | | | 300 | mV | +| VIH | Input high voltage | 740 | | | mV | +| VHYST | Input hysteresis | 25 | | | mV | + +
Table 3-3-15 Contention Line Receiver DC Specifications
+ +| Symbol | Parameter | Minimum | Typical | Maximum | Unit | +| ------ | -------------------------- | ------- | ------- | ------- | ---- | +| VILF | Input low fault threshold | | | 200 | mV | +| VIHF | Input high fault threshold | 450 | | | mV | + +#### 3.3.5 Electrical Characteristics for MIPI CSI + +
Table 3-3-16 Supply Requirements
+ +| Symbol | Parameter | Condition | Minimum | Typical | Maximum | Unit | +| ------ | ------------------ | --------- | ------- | ------- | ------- | ---- | +| Vslew | Supplies slew rate | -- | -- | -- | 0.1 | V/μs | + +
Table 3-3-17 Input DC Specifications
+ +| Symbol | Parameter | Minimum | Typical | Maximum | Unit | Notes | +| ---------------------------------- | ---------------------------------------- | ------- | ------- | ------- | ---- | ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | +| Apply to CLKP/N and DATAP/N Inputs | | | | | | | +| VPIN | Pin signal voltage range | -50 | | 1350 | mV | | +| ILEAK | Pin leakage current | -10 | | 10 | µA | VGNDSH(min) ≤ VPIN ≤ VGNDSH(max) + VOH(absmax) Lane module in LP receive mode | +| VGNDSH | Ground shift | -50 | | 50 | mV | | +| VPIN(absmax) | Maximum transient output voltage level | -0.15 | | 1.45 | V | | +| VPIN(absmax) | Maximum transient time above VOH(absmax) | | | 20 | ns | The voltage overshoot and undershoot beyond the VPIN is only allowed during a single 20ns window after any LP-0 to LP-1 transition or vice versa. For all other situations the voltage overshoot and undershoot must stay within the VPIN range. | + +
Table 3-3-18 HS Line Receiver DC Specifications
+ +| Symbol | Parameter | Minimum | Typical | Maximum | Unit | Notes | +| ------- | ----------------------------------------- | ------- | ------- | ------- | ---- | ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | +| VIDTH | Differential input high voltage threshold | | | 70 | mV | D-PHY spec 1.1 compatibility mode (<=1.5Gbps) | +| VIDTH | Differential input high voltage threshold | | | 40 | mV | In case of High-Speed deskew calibration (>1.5Gbps) | +| VIDTL | Differential input low voltage threshold | -70 | | | mV | D-PHY spec 1.1 compatibility mode (<=1.5Gbps) | +| VIDTL | Differential input low voltage threshold | -40 | | | mV | In case of High-Speed deskew calibration (>1.5Gbps) | +| VIHHS | Single ended input high voltage | | | 460 | mV | Excluding possible additional RF interference of 100mV peak sine wave beyond 450MHz | +| VILHS | Single ended input low voltage | -40 | | | mV | Excluding possible additional RF interference of 100mV peak sine wave beyond 450MHz | +| VCMRXDC | Input common mode voltage | 70 | | 330 | mV | Excluding possible additional RF interference of 100mV peak sine wave beyond 450MHz. This table value includes a ground difference of 50mV between the transmitter and the receiver, the static common-mode level tolerance and variations below 450MHz | +| ZID | Differential input impedance | 80 | 100 | 125 | Ω | | + +
Table 3-3-19 LP Line Drivers DC Specifications
+ +| Symbol | Parameter | Minimum | Typical | Maximum | Unit | +| ------------ | ------------------------------------------------------------- | ------- | ------- | ------- | ---- | +| VOL | Output low-level SE voltage | -50 | | 50 | mV | +| VOH | Output high-level SE voltage | 1.1 | 1.2 | 1.3 | V | +| ZOLP | Single-ended output impedance | 110 | | | Ω | +| ∆ZOLP(01,10) | Single-ended output impedance mismatch driving opposite level | | | 20 | % | +| ∆ZOLP(00,11) | Single-ended output impedance mismatch driving same level | | | 5 | % | + +
Table 3-3-20 LP Line Receiver DC Specifications
+ +| Symbol | Parameter | Minimum | Typical | Maximum | Unit | +| -------- | --------------------------- | ------- | ------- | ------- | ---- | +| VIL | Input low voltage | | | 550 | mV | +| VIH | Input high voltage | 740 | | | mV | +| VIL-ULPS | Logic 0 input voltage, ULPS | | | 300 | mV | +| VHYST | Input hysteresis | 25 | | | mV | + +
Table 3-3-21 Contention Line Receiver DC Specifications
+ +| Symbol | Parameter | Minimum | Typical | Maximum | Unit | +| ------ | -------------------------- | ------- | ------- | ------- | ---- | +| VILF | Input low fault threshold | | | 200 | mV | +| VIHF | Input high fault threshold | 450 | | | mV | + +### 3.3.6 Electrical Characteristics for USB + +
Table 3-3-22 Electrical Characteristics for USB
+ +| Parameter | Symbol | Test Condition | Min | Max | Unit | +| ---------------------------------------------------------------------------- | ------- | ----------------------------------------------------- | --------- | ----- | ---- | +| High-power Port | VBUS | | 4.75 | 5.25 | V | +| Low-power Port | VBUS | | 4.4 | 5.25 | V | +| High-power Hub Port (out) | ICCPRT | | 500 | | mA | +| Low-power Hub Port (out) | ICCUPT | | 100 | | mA | +| High-power Function (in) | ICCHPF | | | 500 | mA | +| Low-power Function (in) | ICCLPF | | | 100 | mA | +| Unconfigured Function/Hub (in) | ICCINIT | | | 100 | mA | +| Suspended High-power Device | ICCSH | | | 2.5 | mA | +| Suspended Low-power Device | ICCSL | | | 500 | uA | +| High (driven) | VIH | | 2 | | V | +| High (floating) | VIHZ | | 2.7 | 3.6 | V | +| Low | VIL | | 0.8 | | V | +| Differential Input Sensitivity | VDI | | (D+)-(D-) | | 0.2 | +| Differential Common Mode Range | VCM | Includes VDI range; | 0.8 | 2.5 | V | +| High-speed squelch detection threshold (differential signal amplitude) | VHSSQ | specification refers to differential signal amplitude | 100 | 150 | mV | +| High speed disconnect detection threshold (differential signal amplitude) | VHSDSC | specification refers to differential signal amplitude | 525 | 625 | mV | +| High-speed differential input signaling levels | | Specified by eye pattern templates | | | | +| High-speed data signaling common mode voltage range (guideline for receiver) | VHSCM | | -50 | 500 | mV | +| Low | VOL | | 0 | 0.3 | V | +| High (Driven) | VOH | | 2.8 | 3.6 | V | +| SE1 | VOSE1 | | 0.8 | | V | +| Output Signal Crossover Voltage | VCRS | | 1.3 | 2 | V | +| High-speed idle level | VHSOI | | -10 | 10 | mV | +| High-speed data signaling high | VHSOH | | 360 | 440 | mV | +| High-speed data signaling low | VHSOL | | -10 | 10 | mV | +| Chirp J level (differential voltage) | VCHIRPJ | | 700 | 1100 | mV | +| Chirp K level (differential voltage) | VCHIRPK | | -900 | -500 | mV | +| Downstream Facing Port Bypass Capacitance (per hub) | CHPB | VBUS to GND, | 120 | | uF | +| Upstream Facing Port Bypass Capacitance | CRPB | VBUS to GND | 1 | 10 | uF | +| Downstream Facing Port | CIND | | 150 | | pF | +| Upstream Facing Port (w/o cable) | CINUB | | 100 | | pF | +| Transceiver edge rate control capacitance | CEDGE | | 75 | | pF | +| TDR spec for high-speed termination | | | | | | +| Bus Pull-up Resistor on Upstream Facing Port | RPU | 1.5 kΩ ±5% | 1.425 | 1.575 | kΩ | +| Bus Pull-down Resistor on Downstream Facing Port | RPD | 15 kΩ±5% | 14.25 | 15.75 | kΩ | +| Input impedance exclusive of pullup/pulldown (for low-/full speed) | ZINP | | 300 | | kΩ | +| Termination voltage for upstream facing port pullup (RPU) | VTERM | | 3 | 3.6 | V | +| Termination voltage in high speed | VHSTERM | | -10 | 10 | mV | + +#### 3.3.7 Electrical Characteristics for SD/eMMC + +
Table 3-3-23 SD/eMMC electrical specifications
+ +| Parameter | Test conditions | Min | Max | Units | +| ---------------------------- | --------------- | ------------ | ------------- | ----- | +| MMC0_* signals | Relative to VSS | -0.3 | 3.63 | V | +| Input High Voltage(ViH) | Relative to VSS | 1.68 | - | V | +| Input Low Voltage(ViL) | Relative to VSS | - | 0.9 | V | +| VOH | Relative to VSS | 0.75*VDDIO33 | - | V | +| VOL | Relative to VSS | - | 0.125*VDDIO33 | V | +| Operating temprature rang TJ | - | -40 | 125 | C | diff --git "a/zh/00_hardware/K230_\347\241\254\344\273\266\350\256\276\350\256\241\346\214\207\345\215\227.md" "b/zh/00_hardware/K230_\347\241\254\344\273\266\350\256\276\350\256\241\346\214\207\345\215\227.md" new file mode 100755 index 0000000..90ac806 --- /dev/null +++ "b/zh/00_hardware/K230_\347\241\254\344\273\266\350\256\276\350\256\241\346\214\207\345\215\227.md" @@ -0,0 +1,885 @@ +# K230 硬件设计指南 + +![cover](images/HDG/canaan-cover.png) + +版权所有©2023北京嘉楠捷思信息技术有限公司 + +
+ +## 免责声明 + +您购买的产品、服务或特性等应受北京嘉楠捷思信息技术有限公司(“本公司”,下同)及其关联公司的商业合同和条款的约束,本文档中描述的全部或部分产品、服务或特性可能不在您的购买或使用范围之内。除非合同另有约定,本公司不对本文档的任何陈述、信息、内容的正确性、可靠性、完整性、适销性、符合特定目的和不侵权提供任何明示或默示的声明或保证。除非另有约定,本文档仅作为使用指导参考。 + +由于产品版本升级或其他原因,本文档内容将可能在未经任何通知的情况下,不定期进行更新或修改。 + +## 商标声明 + +![logo](images/HDG/logo.png)、“嘉楠”和其他嘉楠商标均为北京嘉楠捷思信息技术有限公司及其关联公司的商标。本文档可能提及的其他所有商标或注册商标,由各自的所有人拥有。 + +**版权所有 © 2023北京嘉楠捷思信息技术有限公司。保留一切权利。** +非经本公司书面许可,任何单位和个人不得擅自摘抄、复制本文档内容的部分或全部,并不得以任何形式传播。 + +
+ +## 目录 + +[toc] + +## 前言 + +### 概述 + +本文档主要介绍K230处理器硬件设计的要点及注意事项,旨在帮助客户缩短产品的设计周期、提高产品的设计稳定性及降低故障率。请客户参考本指南的要求进行硬件设计,同时尽量使用K230发布的相关核心模板。如因特殊原因需要更改的,请严格按照高速数字电路设计要求进行。 + +### 读者对象 + +本文档(本指南)主要适用于以下人员: + +- 硬件开发工程师 +- 技术支持工程师 +- 测试工程师 + +### 术语表 + +| 简称 | 说明 | +| ----- | ---------------------------------------- | +| DDR | Double Data Rate | +| SDRAM | Synchronous Dynamic Random Access Memory | +| LPDDR | low power double data rate | +| MIPI | Mobile Industry Processor Interface | +| OTG | On the Go | +| APB | Advanced Peripheral Bus | +| SPI | Serial Peripheral Interface | +| DMA | Direct Memory Access | +| AHB | Advanced High Performance Bus | +| PCM | Pulse Code Modulation | +| PDM | Pulse Density Modulation | +| PCLK | Peripheral High-speed Clock | +| CLK | Clock | +| DQS | Bi-directional Data Strobe | +| GPIO | General-purpose Input/Output | +| eMMC | Embedded Multi-media Card | +| SIP | System In a Package | +| PMU | Power Management Unit | + +### 修订记录 + +| 文档版本号 | 修改说明 | 修改者 | 日期 | +| ---------- | -------- | ------ | ---------- | +| V1.0 | 初版 | 赵瑞昕 | 2023-06-14 | + +## 1. 芯片概述 + +### 1.1 芯片框图 + +![图1-1 K230框图](images/HDG/image002.jpg) +图1-1 K230框图 + +### 1.2 应用框图 + +图1-2为K230门锁应用框图 +![图1-2 K230门锁方案应用框图](images/HDG/image003.jpg) +图1-2 K230门锁方案应用框图 +图1-3为词典笔方案应用框图 +![图1-3 K230词典笔方案应用框图](images/HDG/image004.jpg) +图1-3 K230词典笔方案应用框图 + +## 2. 封装与管脚 + +### 2.1 封装 + +#### 2.1.1 信息 + +K230的封装信息如下表2-1所示: + +| 器件 | 封装 | 大小 | Pitch | +| ----- | -------- | ----------- | ----- | +| K230 | VFBGA390 | 13mm x 13mm | 0.65 | +| K230D | LFBGA256 | 11mm x 11mm | 0.65 | + +#### 2.1.2 封装尺寸 + +##### K230尺寸 + +![图2-1](images/HDG/image005.png) +图2-1 +![图2-2](images/HDG/image006.png) +图2-2 +![图2-3](images/HDG/image007.png) +图2-3 + +球形防焊开口:0.270mm + +主要基准C和底面是锡球 + +尺寸b是测量最大锡球直径,平行于主要基准C + +##### K230D尺寸 + +![图2-4](images/HDG/image008.png) +图2-4 +![图2-5](images/HDG/image009.png) +图2-5 + +球形防焊开口:0.270mm + +主要基准C和底面是锡球 + +尺寸b是测量最大锡球直径,平行于主要基准C + +#### 2.1.3 引脚定义图 + +K230引脚分布图如下: +![图2-6 K230封装管脚分布](images/HDG/image010.png) +图2-6 K230封装管脚分布 +![图2-7 K230D封装管脚分布](images/HDG/image011.png) +图2-7 K230D封装管脚分布 +引脚详情见表“K230_PINOUT_V1.0_20230524.xlsx”[K230_PINOUT_V1.0_20230524.xlsx](/K230_PINOUT_V1.0_20230524.xlsx)。 + +## 3. 原理图设计建议 + +### 3.1. 最小系统设计 + +#### 3.1.1 时钟要求 + +K230的主系统需要24MHz的高速时钟,PMU子系统的RTC需要32.768kHz的低速时钟。 + +表3-1是K230允许的时钟源参数。 + +| 频点 | 精度 | 电平 | +| --------- | ----- | ---- | +| 32.768KHz | 20ppm | 1.8V | +| 24MHz | 20ppm | 1.8V | + +建议使用20ppm或精度更高的时钟源提供时钟。 + +##### 高速电路 + +推荐的无源晶体连接方式如图3-1所示。 +![图3-1 K230晶体电路](images/HDG/image012.png) +图3-1 K230晶体电路 +注意: + +- 选用的电容需要与晶振的负载电容匹配,材质建议采用NPO 。 +- 建议选用 4Pin 贴片晶振,2个GND管脚与地充分连接,增强系统时钟抗 ESD 干扰能力。 +- 如若需要提高起振速度,可在IN管脚和OUT管脚间添加1MΩ电阻。 + +推荐的有源晶振连接方式如图3-2所示。 +![图3-2 K230有源晶振电路](images/HDG/image013.png) +图3-2 K230有源晶振电路 +工作时,晶振输出接到K230的CLK24M_XIN 脚,CLK24M_XOUT脚悬空。 + +##### 低速时钟 + +K230芯片内置了PMU电路,单板需要给PMU电路提供时钟。推荐的电路如图3-3所示。 +![图3-3 K230 RTC时钟无源晶体电路](images/HDG/image014.png) +图3-3 K230 RTC时钟无源晶体电路 +推荐的有源晶振连接方式如图3-4所示。 +![图3-4 K230 RTC时钟有源晶振电路](images/HDG/image015.png) +图3-4 K230 RTC时钟有源晶振电路 + +工作时,晶振输出接到K230的CLK32K768_XIN脚,CLK32K768_XOUT脚悬空。 +注意: + +- 在使用有源晶振时,以上各有源晶振电路图中NC处需用0Ω电阻连接。 + +#### 3.1.2 复位电路 + +K230的硬件复位通过引脚RSTN来实现,低电平有效。 +如果使用按键复位,建议复位信号引脚增加100nF电容,用来消除复位信号的抖动,增强抗干扰能力,防止误触发导致的系统异常复位。 +复位电路示意图如图3-5。 +![图3-5 K230 复位电路](images/HDG/image016.png) +图3-5 K230 复位电路 + +#### 3.1.3 系统启动引导顺序 + +K230芯片提供4种启动方式,可以通过BOOT0和BOOT1引脚来进行相关的配置。 +表3-2为不同配置下K230的启动方式。 + +| BOOT0 | BOOT1 | K230 | K230D | +| ----- | ----- | ---------- | ---------- | +| 0 | 0 | NOR FLASH | NOR FLASH | +| 1 | 0 | NAND FLASH | NAND FLASH | +| 0 | 1 | MMC0 | MMC1 | +| 1 | 1 | MMC1 | MMC0 | + +表3-2 启动方式说明 + +注意: + +- 四种启动方式都失效时,会跳转到USB UART启动。 + +图3-6为推荐的BOOT电路 +![图3-6 K230 BOOT电路](images/HDG/image017.png) +图3-6 K230 BOOT电路 + +#### 3.1.4 JTAG Debug电路 + +K230芯片推荐的JTAG接口电路如图3-7。 +![图3-7 K230 JTAG下载电路](images/HDG/image018.png) +[图3-7 K230 JTAG下载电路 +其中,JTAG_TCK、JTAG_TDI、JTAG_TMS和JTAG_RST建议用10kΩ上拉,JTAG_TDO悬空。 +K230必须采用平头哥半导体有限公司提供的CKLink系列调试器,否则芯片无法进行调试。 + +#### 3.1.5 DDR控制器 + +K230芯片有K230和K230D两个版本,K230版本需单独设计DDR电路。K230D版本将DDR Die一并进行了封装,无需设计外部DDR电路。 +K230 DDR控制器有以下特点: + +- 支持LPDDR3/LPDDR4 +- 支持2 rank +- 支持16位、32位DDR数据总线位宽 +- 已验证型号:| 协议 | 型号 | 生产厂商 | 容量 | + | ------ | ---------------- | -------- | ---- | + | LPDDR3 | NT6CL128M32DM-H0 | 南亚 | 4Gb | + | LPDDR4 | W66AP6NBUAF/G/HI | 华邦 | 4Gb | + +K230 DDR PHY和各个DRAM颗粒的原理图必须和参考原理图一致,包括电源去耦电容。 + +##### LPDDR3 + +LPDDR3的电路设计参考图3-8、图3-9、图3-10和图3-11。 +![图3-8 K230 LPDDR3电路](images/HDG/image019.png) +图3-8 K230 LPDDR3电路 +![图3-9 K230 LPDDR3电源电路](images/HDG/image020.png) +图3-9 K230 LPDDR3电源电路 +![图3-10 LPDDR3颗粒电源电路](images/HDG/image021.png) +图3-10 LPDDR3颗粒电源电路 +![图3-11 LPDDR3颗粒电路](images/HDG/image022.png) +图3-11 LPDDR3颗粒电路 + +在使用LPDDR3时: + +- DDR PHY和各DRAM颗粒原理图需要和参考设计图一致,包含电源去耦电容 +- DDR_ZN管脚需要接240Ω(1%)的校准电阻到地 +- DDR_RESET管脚悬空 +- 芯片已内置DDR控制器的VREF电路,故DDR_VREF管脚需悬空 +- LP3颗粒的LP3_VREFDQ电压为0.8V,建议使用100Ω和200Ω (1%)的电阻进行分压得出 +- LP3_VREFCA电压为0.6V,建议使用1kΩ(1%)的电阻分压得出 +- LP3的CA、CS、CKE、CLK和ODT引脚均需使用100Ω电阻上下拉到DDR_VDDQ_1V2和地 + +##### LPDDR4 + +LPDDR4的电路设计参考图3-12、图3-13、图3-14、图3-15和图3-16。 +![图3-12 K230 LPDDR4电路](images/HDG/image023.png) +图3-12 K230 LPDDR4电路 +![图3-13 K230 LPDDR4电源电路](images/HDG/image024.png) +K230 LPDDR4电源电路 +![图3-14 K230 LPDDR4参考电压电路](images/HDG/image025.png) +图3-14 K230 LPDDR4参考电压电路 LPDDR4颗粒电路](images/HDG/image026.png) +![图3-16 LPDDR4颗粒电源电路](images/HDG/image027.png) +图3-16 LPDDR4颗粒电源电路 + +在使用LPDDR4时,注意: + +- DDR PHY和各DRAM颗粒原理图需要和参考设计图一致,包含电源去耦电容 +- DDR_ZN管脚需要接240Ω(1%)的校准电阻到地 +- RESRT_N管脚直连到颗粒对应管脚 +- K230使用LPDDR4颗粒时,VREF电压为0.6V,建议使用1kΩ(1%)电阻分压 + +##### K230D DDR模块 + +K230D已内置DDR Die,因此连接参考电压和校准电阻即可。 +参考电路如图3-17和图3-18 + +![图3-17 K230D DDR外围电路](images/HDG/image028.png) +图3-17 K230D DDR外围电路 +![图3-18 K230D DDR参考电压](images/HDG/image029.png) +图3-18 K230D DDR参考电压 + +在使用K230D的DDR模块时,注意: + +- VREF电压为0.55V,建议使用100Ω(1%)电阻分压 +- 校准电阻选用240Ω(1%) + +#### 3.1.6 FLASH + +K230带有OSPI/QSPI控制器,可用来连接FLASH存储芯片,其有以下特点: + +- OSPI支持4/8bit模式的 SPI NOR FLASH +- OSPI最高支持DDR200,SDR166的NOR FLASH +- QSPI支持1/2/4 bit模式的SPI NAND&NOR FLASH +- 最高支持SDR100的NOR FLASH + +##### OSPI + +OSPI参考原理图如图3-19和图3-20 +![图3-19 K230 OSPI电路](images/HDG/image030.png) +图3-19 K230 OSPI电路 +![图3-20 OSPI FLASH电路](images/HDG/image031.png) +图3-20 OSPI FLASH电路 + +请根据FLASH芯片的要求放置上拉电阻。 + +##### QSPI NOR + +QSPI信号中,CS、CLK、D0、D1、D2和D3信号的管脚与OSPI对应信号的管脚复用,如表3-3 + +| QSPI管脚 | OSPI管脚 | +| -------- | -------- | +| QSPI_CS | OSPI_CS | +| QSPI_CLK | OSPI_CLK | +| QSPI_D0 | OSPI_D0 | +| QSPI_D1 | OSPI_D1 | +| QSPI_D2 | OSPI_D2 | +| QSPI_D3 | OSPI_D3 | + +表3-3 QSPI与OSPI对应管脚 + +参考电路如图3-21 +![图3-21 QSPI NOR FLASH芯片电路](images/HDG/image032.png) +图3-21 QSPI NOR FLASH芯片电路 +请根据FLASH芯片的要求放置上拉电阻。 + +##### QSPI NAND + +QSPI NAND的参考电路如图3-22。 +![图3-22 QSPI NAND FLASH芯片电路](images/HDG/image033.png) +图3-22 QSPI NAND FLASH芯片电路 +请根据FLASH芯片的要求放置上拉电阻。 + +### 3.2. MMC电路 + +K230 eMMC 控制电路拥有两个控制器MMC0和MMC1。 + +#### MMC0 + +MMC0控制器有以下特点: + +- 支持SDIO3.0,工作于4/1-bits mode,最高支持SDR104 +- 支持eMMC5.0工作于8/4/1-bits mode,支持HS200 +- 支持SD卡所需3.3V和1.8V电压的转换 + +MMC0功能较全,一般用于控制eMMC电路。 +eMMC推荐参考电路如图3-23和图3-24。 + +![图3-23 K230 eMMC电路](images/HDG/image034.png) +图3-23 K230 eMMC电路 +![图3-24 eMMC颗粒电路](images/HDG/image035.png) +图3-24 eMMC颗粒电路 + +请按照eMMC厂家要求连接对应管脚。如无特殊要求,直连对应管脚即可。 + +#### MMC1 + +MMC1控制器有以下特点: + +- 支持SDIO3.0,工作于4/1-bits mode,最高支持SDR104 +- 支持SD卡所需3.3V和1.8V电压的转换 + +MMC1性能和管脚数量无法满足控制eMMC电路的要求,只能用于控制SD/TF卡电路。 +参考原理图如图3-25、图3-26和图3-27。 + +![图3-25 K230 SD卡接口电路](images/HDG/image036.png) +图3-25 K230 SD卡接口电路 +![图3-26 SD卡上拉电路](images/HDG/image037.png) +图3-26 SD卡上拉电路 +![图3-27 SD卡卡座电路](images/HDG/image038.png) +图3-27 SD卡卡座电路 + +SD卡电路设计时需注意: + +- SD卡引脚的电压去耦电容不得删减,要靠近卡座放置 +- 各信号在SD卡座附近均需放置ESD器件 +- 各信号均需上拉电阻 +- 推荐根据参考电路进行设计 + +### 3.3. USB电路 + +K230芯片内置两个USB2.0 OTG控制器,控制器有以下特点: + +- 支持USB2.0协议,向下兼容USB 1.1 协议 +- 支持Host模式或者Device模式,可选支持动态切换 +- Host模式支持480Mbps,12Mbps,1.5Mbps 传输速率 +- Device模式支持480Mbps,12Mbps传输模式 + +USB电路参考原理图如图3-28和图3-29. + +![图3-28 K230 USB电路](images/HDG/image039.png) +图3-28 K230 USB电路 +![图3-29 USB接口电路](images/HDG/image040.png) +图3-29 USB接口电路 + +注意: + +- 各信号在USB座附近均需放置ESD器件 +- K230的USB_VBUS电源,必须串联30kΩ(1%)电阻到5V电源,不能直接连接电源 +- 为保证信号质量,K230的USB_TXRTUNE管脚必须接200Ω(1%)电阻到地 +- USB_ID可用于OTG设备的身份识别,其接地时,K230作为HOST端,其浮空或拉高时,K230作SLAVE端 + +### 3.4. 音频相关电路 + +#### 3.4.1 I2S + +K230芯片有一个I2S控制器,其有以下特点: + +- 拥有两路输入和输出 +- 支持PHILIP I2S标准 +- 支持左右、PCM格式 +- 同步工作模式 +- 主或从模式可选 +- 可调接口电压 +- 采样速率8k到384kHz + +K230的I2S拥有3个引脚分别是I2S_CLK、I2S_WS和I2S_SD。 +I2S_CK是串行时钟信号,I2S_WS是数据帧控制信号, I2S_SD是串行数据信号。 +I2S接口通常用于连接解码器等音频外设。 +图3-30和图3-31为K230 I2S接口电路和部分外设电路。 +![图3-30 K230 I2S接口电路](images/HDG/image041.png) +图3-30 K230 I2S接口电路 +![图3-31 K230 I2S参考外设](images/HDG/image042.png) +图3-31 K230 I2S参考外设 + +#### 3.4.2 PDM + +K230支持4路PDM信号输入。采样速率从8k到384kHz。 +PDM接口通常用于接入数字麦克风等具有PDM接口的音频设备。 +图3-32为K230的PDM外设电路。 +![图3-32 K230 PDM外设电路](images/HDG/image043.png) +图3-32 K230 PDM外设电路 + +#### 3.4.3 模拟音频接口 + +K230芯片的模拟音频部分有以下特点: + +- 支持2路DAC和2路ADC +- DAC支持差分输出和单端输出,ADC支持差分输入和单端输入 +- 支持低噪声模拟麦克风偏置输出 + +模拟音频的参考电路如图3-33和图3-34 +![图3-33 K230 模拟音频接口电路](images/HDG/image044.png) +图3-33 K230 模拟音频接口电路 +![图3-34 音频接口电路](images/HDG/image045.png) +图3-34 音频接口电路 + +注意,为获得更好的音质,建议考虑使用以下措施: + +- 电源引脚同时使用大容量和小容量的低ESR陶瓷电容 +- MICBIAS管脚需要放置大容量低ESR电容 +- 音频输入的隔直电容靠近K230芯片放置 +- 输出管脚需要放置滤波电路或隔直电容 + +### 3.5. 视频电路 + +#### 3.5.1 MIPI DSI + +K230的MIPI DSI控制器有以下特点: + +- 支持1路信号输出 +- 支持1/2/4lane 模式 +- 最高速率可达1.5Gbps + +MIPI DSI各信号均直连。 +参考硬件设计如图3-35和图3-36 + +![图3-35 K230 MIPI DSI接口电路](images/HDG/image046.png) +![图3-35 K230 MIPI DSI接口电路](images/HDG/image047.png) +图3-35 K230 MIPI DSI接口电路 +![图3-36 屏幕接口电路](images/HDG/image048.png) +图3-36 屏幕接口电路 +注意: + +- MIPI_ATB引脚必须浮空 +- MIPI_REXT引脚必须接200Ω(1%)电阻到地 +- 该连接器电路各引脚仅适配今朝辉屏幕,请根据自有屏幕模组设计电路 + +### 3.6. 摄像头电路 + +#### 3.6.1 MIPI CSI + +K230的MIPI CSI控制器有以下特点: + +- 最高支持3路MIPI信号输入,支持1/2/4lane 模式 +- 最高可配置为3路2lane信号输入或1路4lane、1路2lane信号输入 +- 最高速率可达1.5Gbps + +MIPI CSI信号推荐直连。 +参考硬件设计如图3-37和图3-38 +![图3-37 K230 MIPI CSI接口电路](images/HDG/image049.png) +图3-37 K230 MIPI CSI接口电路 +![图3-38 摄像头连接器电路](images/HDG/image050.png) +图3-38 摄像头连接器电路 +注意: + +- 该连接器电路仅供内部测试使用,实际使用请根据需要自行设计电路 + +### 3.7. 低速子系统电路 + +#### 3.7.1 I2C电路 + +K230芯片支持5路I2C接口,具有以下功能: + +- 支持I2C总线主模式 +- 支持7/10 bit地址 +- 支持I2C速率最高到3.4Mbit/s + +在使用I2C外设时,需要注意对应电源域供电,必须保持一致。 +I2C信号的SCL和SDA需要外接上拉电阻,根据总线负载和总线速率的不同,选择不同阻值的电阻。 + +- 在不大于400kb/s的系统中,推荐阻值为4.7kΩ; +- 在大于400kb/s小于3.4Mb/s的系统中,推荐上拉电阻为2.2 kΩ。 + +#### 3.7.2 UART电路 + +K230支持5路UART信号,其具有以下特点: + +- 支持2线UART和4线UART +- 支持RS485接口 +- 支持波特率最高可达3.125M +- 支持软硬件流控,符合16750标准 +- 支持IrDA 1.0 SIR接收 + +在使用UART外设时,需要注意对应电源域供电,必须保持一致。 + +#### 3.7.3 PWM电路 + +K230支持6路PWM信号,其有以下特点: + +- 支持任意占空比 +- 支持输出波形可编程 +- 支持产生周期性的脉冲信号和一次性的脉冲信号 +- 可作为周期精确的中断发生器 +- 支持输出毛刺消除 + +#### 3.7.4 MCLK电路 + +K230支持输出3路MCLK信号。该信号可作为摄像头的驱动时钟。 +支持输出时钟频率如表3-4: + +| | | | | | | | | +| :----: | :----: | :---: | :---: | :---: | :---: | :---: | :---: | +| 792 | 132 | 66.67 | 46.59 | 36 | 28.57 | 23.76 | 18.56 | +| 594 | 118.8 | 66 | 45.69 | 34.94 | 28.29 | 23.53 | 18.18 | +| 400 | 113.14 | 66 | 44.44 | 34.43 | 28.29 | 22.85 | 17.39 | +| 396 | 100 | 60.92 | 44 | 33.33 | 27.31 | 22.22 | 16.67 | +| 297 | 99 | 59.4 | 42.43 | 33 | 27 | 22 | 16 | +| 264 | 99 | 57.14 | 41.68 | 33 | 26.67 | 21.21 | 15.38 | +| 200 | 88 | 56.57 | 40 | 31.68 | 26.4 | 21.05 | 14.81 | +| 198 | 84.86 | 54 | 39.6 | 31.26 | 25.83 | 20.48 | 14.29 | +| 198 | 80 | 52.8 | 39.6 | 30.77 | 25.55 | 20 | 13.79 | +| 158.4 | 79.2 | 50 | 37.71 | 30.46 | 25 | 19.8 | 13.33 | +| 148.5 | 74.25 | 49.5 | 37.13 | 29.7 | 24.75 | 19.16 | 12.9 | +| 133.33 | 72 | 49.5 | 36.36 | 29.33 | 24.75 | 19.05 | 12.5 | + +表3-4 MCLK输出时钟频率(单位:MHz) + +#### 3.7.5 ADC电路 + +K230集成了一个分辨率为11bit(有效分辨率)的SARADC,最高采样率不小于1MHz。 +其有以下特点: + +- 信号输入范围:0-1.8V +- 支持6个通道输入 +- 支持单次采样和连续采样 +- 内部集成信号调理电路,截止频率在1/2带宽处。ADC可直接进行信号采样,或按需进行外围电路设计 + +#### 3.7.6 PMU电路 + +K230的PMU模块用于控制管理芯片内部和外部电源。 +其内置RTC电路,支持6路输入。其功能如表: + +| 中断源 | 沿触发 | 电平触发 | 去抖动 | 边沿数量检测 | 长短按检测 | +| :----: | :----: | :------: | :----: | :----------: | :--------: | +| INT_0 | 支持 | 支持 | 支持 | - | 支持 | +| INT_1 | 支持 | 支持 | 支持 | 支持 | - | +| INT_2 | 支持 | 支持 | - | - | - | +| INT_3 | 支持 | 支持 | - | - | - | +| INT_4 | - | 支持 | - | - | - | +| INT_5 | - | 支持 | - | - | - | + +支持两路输出OUT0和OUT1,可用于使能电源。 +在冷启动状态,PMU仅使能了INT0的长按中断和INT4的高电平输入中断,作为PMU模块启动的触发源。OUT0和OUT1默认输出低电平,初始下拉电阻约为40Ω。 +在收到以上两种中断之一时,OUT0拉高,OUT1约50ms后拉高。 +OUT0和OUT1可用于控制外部PMIC的使能管脚或用于其他用途。 + +### 3.8. 电源设计 + +#### 3.8.1 K230电源需求 + +| 模块 | 电源管脚 | 描述 | +| ------------- | --------------- | ------------------------------------------------------- | +| CORE | VDD0P8_CORE | CPU0和其他单元电源 | +| CPU | VDD0P8_CPU | CPU1电源 | +| KPU | VDD0P8_KPU | KPU电源 | +| DDR控制器 | VDD0P8_DDR_CORE | DDR的数字CORE电源,可掉电 | +| | VDD1P1_DDR_IO | DDR的IO电源 | +| | VAA_DDR | DDR锁相环电源 | +| USB | AVDD3P3_USB | USB PHY使用的3.3V电源,不使用时可不上电 | +| | AVDD1P8_USB | USB PHY使用的1.8V电源,不使用时可不上电 | +| PLL | AVDD0P8_PLL | PLL电源 | +| MIPI | AVDD0P8_MIPI | MIPI 0.8V电源,不使用时可不上电 | +| | AVDD1P8_MIPI | MIPI 1.8V电源,不使用时可不上电 | +| VDD1P8 | VDD1P8 | 1.8V模块电源 | +| ADC | AVDD1P8_ADC | ADC电源,不使用时可不上电 | +| CODEC | AVDD1P8_CODEC | CODEC电源,不使用时可不上电 | +| PMU | AVDD1P8_RTC | PMU内置RTC电源,不使用时可不上电 | +| | AVDD1P8_LDO | PMU内置LDO电源,不使用时可不上电 | +| MMC | VDD3P3_SD | 3.3V输出buffer和pre-buffer I/O电源,不使用时可不上电 | +| IO | VDDIO3P3_0 | IO_2-IO_13电源,电压可选择1.8V或3.3V,不使用时可不上电 | +| | VDDIO3P3_1 | IO_14-IO_25电源,电压可选择1.8V或3.3V,不使用时可不上电 | +| | VDDIO3P3_2 | IO_26-IO_37电源,电压可选择1.8V或3.3V,不使用时可不上电 | +| | VDDIO3P3_3 | IO_38-IO_49电源,电压可选择1.8V或3.3V,不使用时可不上电 | +| | VDDIO3P3_4 | IO_50-IO_61电源,电压可选择1.8V或3.3V,不使用时可不上电 | +| | VDDIO3P3_5 | IO_62-IO_63电源,电压可选择1.8V或3.3V,不使用时可不上电 | +| K230D DDR部分 | VDD1P8_DDR_VDD1 | K230D中DDR颗粒电源,K230没有此管脚 | +| | VDD1P1_DDR_VDD2 | K230D中DDR颗粒电源,K230没有此管脚,不可掉电 | +| | VDD1P1_DDR_VDDQ | K230D中DDR颗粒电源,K230没有此管脚,可掉电 | + +表3-6 K230电源需求表 + +#### 3.8.2 上电时序 + +VDD0P8_CORE上电必须早于VDD1P8、VDDIO3P3_0到VDDIO3P3_5的IO接口上电,AVDD0P8_MIPI上电必须早于AVDD1P8_MIPI,AVDD1P8_RTC不晚于AVDD1P8_LDO,其余顺序无要求。 + +#### 3.8.3 电源设计建议 + +##### PMU + +| 模块名称 | 管脚 | 最小电压(V) | 典型电压 (V) | 最大电压(V) | 电流 (mA) | 注意事项 | +| -------- | ----------- | ----------- | ------------ | ----------- | --------- | --------------- | +| PMU | AVDD1P8_RTC | 1.674 | 1.8 | 1.98 | 10 | 建议使用LDO供电 | +| | AVDD1P8_LDO | 1.674 | 1.8 | 1.98 | 10 | 建议使用LDO供电 | + +##### 核心模块 + +| 模块名称 | 管脚 | 最小电压(V) | 典型电压 (V) | 最大电压(V) | 电流 (mA) | 注意事项 | +| -------- | ----------- | ----------- | ------------ | ----------- | --------- | --------------------------------------------- | +| CORE | VDD0P8_CORE | 0.72 | 0.8 | 0.88 | 2250 | 建议使用供电能力不小于3A,纹波噪声较低的DC/DC | +| CPU | VDD0P8_CPU | 0.72 | 0.8 | 0.88 | 1000 | 建议使用供电能力不小于2A,纹波噪声较低的DC/DC | +| KPU | VDD0P8_KPU | 0.72 | 0.8 | 0.88 | 3000 | 建议使用供电能力不小于4A,纹波噪声较低的DC/DC | + +##### DDR + +| 模块名称 | 管脚 | 最小电压(V) | 典型电压 (V) | 最大电压(V) | 电流 (mA) | 注意事项 | +| -------- | --------------------- | ----------- | ------------ | ----------- | --------- | ----------------------------------------------------- | +| DDR | VDD0P8_DDR_CORE | 0.744 | 0.8 | 0.88 | 400 | 电源纹波要求在4%以内,建议使用可输出大电流的低噪声LDO | +| | VDD1P1_DDR_IO(LPDDR4) | 1.06 | 1.1 | 1.17 | 800 | LP4纹波要求5%以内,建议使用可输出大电流的低噪声LDO | +| | VDD1P1_DDR_IO(LPDDR3) | 1.14 | 1.2 | 1.3 | 800 | LP3纹波要求10%以内,建议使用可输出大电流的低噪声LDO | +| | VAA_DDR | 1.674 | 1.8 | 1.98 | 10 | 纹波要求在典型电压5%以内 | + +##### K230D DDR Die + +| 模块名称 | 管脚 | 最小电压(V) | 典型电压 (V) | 最大电压(V) | 电流 (mA) | 注意事项 | +| ------------- | --------------- | ----------- | ------------ | ----------- | --------- | ------------------------------------------------------- | +| K230D DDR die | VDD1P8_DDR_VDD1 | 1.7 | 1.8 | 1.95 | 75 | 纹波要求在典型电压5%以内,与DDR控制器电源在同一电源网络 | +| | VDD1P1_DDR_VDD2 | 1.06 | 1.1 | 1.17 | 450 | 与VDD1P1_DDR_IO在同一电源网络 | +| | VDD1P1_DDR_VDDQ | 1.06 | 1.1 | 1.17 | 300 | 建议使用可输出大电流的低噪声LDO | + +##### I/O + +| 模块名称 | 管脚 | 最小电压(V) | 典型电压 (V) | 最大电压(V) | 电流 (mA) | 注意事项 | +| -------- | ---------- | ----------- | ------------ | ----------- | --------- | ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ | +| IO | VDDIO3P3_0 | 1.62/2.97 | 1.8/3.3 | 1.98/3.63 | 50 | IO单元共有5组电压,均可配置为1.8V或3.3V,每组电压控制了该组I/O口的输出电压和输入电压,也控制I/O复用后功能的输出电压和输入电压。IO电压请与所需连接的外设保持一致,如不一致则需进行电平转换。 | +| | VDDIO3P3_1 | 1.62/2.97 | 1.8/3.3 | 1.98/3.63 | 50 | | +| | VDDIO3P3_2 | 1.62/2.97 | 1.8/3.3 | 1.98/3.63 | 50 | | +| | VDDIO3P3_3 | 1.62/2.97 | 1.8/3.3 | 1.98/3.63 | 50 | | +| | VDDIO3P3_4 | 1.62/2.97 | 1.8/3.3 | 1.98/3.63 | 50 | | +| | VDDIO3P3_5 | 1.62/2.97 | 1.8/3.3 | 1.98/3.63 | 50 | | + +##### USB + +| 模块名称 | 管脚 | 最小电压(V) | 典型电压 (V) | 最大电压(V) | 电流 (mA) | 注意事项 | +| -------- | ----------- | ----------- | ------------ | ----------- | --------- | ------------------- | +| USB | AVDD3P3_USB | 3.07 | 3.3 | 3.63 | 50 | 建议使用LDO进行供电 | +| | AVDD1P8_USB | 1.674 | 1.8 | 1.98 | 60 | 建议使用LDO进行供电 | + +##### PLL + +| 模块名称 | 管脚 | 最小电压(V) | 典型电压 (V) | 最大电压(V) | 电流 (mA) | 注意事项 | +| -------- | ----------- | ----------- | ------------ | ----------- | --------- | ------------------------- | +| PLL | AVDD0P8_PLL | 0.72 | 0.8 | 0.88 | 120 | 建议使用高精度LDO进行供电 | + +##### MIPI + +| 模块名称 | 管脚 | 最小电压(V) | 典型电压 (V) | 最大电压(V) | 电流 (mA) | 注意事项 | +| -------- | ------------ | ----------- | ------------ | ----------- | --------- | ------------------- | +| MIPI | AVDD0P8_MIPI | 0.744 | 0.8 | 0.88 | 100 | 建议使用LDO进行供电 | +| | AVDD1P8_MIPI | 1.674 | 1.8 | 1.98 | 30 | 建议使用LDO进行供电 | + +##### ADC + +| 模块名称 | 管脚 | 最小电压(V) | 典型电压 (V) | 最大电压(V) | 电流 (mA) | 注意事项 | +| -------- | ----------- | ----------- | ------------ | ----------- | --------- | ------------------------- | +| ADC | AVDD1P8_ADC | 1.62 | 1.8 | 1.98 | 10 | 建议使用高精度LDO进行供电 | + +##### CODEC + +| 模块名称 | 管脚 | 最小电压(V) | 典型电压 (V) | 最大电压(V) | 电流 (mA) | 注意事项 | +| -------- | ------------- | ----------- | ------------ | ----------- | --------- | ------------------------- | +| CODEC | AVDD1P8_CODEC | 1.62 | 1.8 | 1.98 | 100 | 建议使用高精度LDO进行供电 | + +##### 其他 + +| 模块名称 | 管脚 | 最小电压(V) | 典型电压 (V) | 最大电压(V) | 电流 (mA) | 注意事项 | +| -------- | --------- | ----------- | ------------ | ----------- | --------- | -------- | +| 其他 | VDD3P3_SD | 2.7 | 3.3 | 3.63 | 50 | | +| | VDD1P8 | 1.62 | 1.8 | 1.98 | 500 | | + +注意: + +- 对于K230需要使用的DDR颗粒,电源需与主芯片电源在同一电源网络。 +- 在满足电压精度要求和电流要求的情况下,电压要求相同的模块可使用同一电压源。对于精度要求不高的场合,ADC等模拟模块也可在隔离后接入数字模块所使用的的电源。 +- K230内部集成DDR_Vref电源给芯片DDR控制器,对于外部颗粒,LPDDR3的VREF电源参考设计如图3-39 + +![图3-39 LPDDR3颗粒Vref电路](images/HDG/image051.png) +图3-39 LPDDR3颗粒Vref电路 + +分压电阻建议使用精度为±1%的电阻。 +LPDDR4的外部颗粒VREF电源参考设计如图3-40。 + +![图3-40 LPDDR4颗粒Vref电路](images/HDG/image052.png) +图3-40 LPDDR4颗粒Vref电路 + +K230D的DDR模块VREF电源参考设计如图3-41 + +![图3-41 K230D版本DDR Vref电路](images/HDG/image053.png) +图3-41 K230D版本DDR Vref电路 + +#### 3.8.4 动态调压 + +K230的CPU和KPU电源支持动态调压,以确保同时满足高性能和低功耗的需求。 +CPU的可调电压节点如表3-7 + +| 电压节点 | 电压(V) | +| ----------- | ------- | +| V_typical | 0.8 | +| V_high | 0.9 | +| V_ultrahigh | 1.0 | +| V_low | 0.7 | +| V_retention | 0.48 | + +表3-8 CPU可调电压节点 + +其中,V_retention是针对DDR retention功能的电压节点。 +KPU的可调电压节点如表3-8 + +| 电压节点 | 电压(V) | +| ----------- | ------- | +| V_typical | 0.8 | +| V_high | 0.9 | +| V_ultrahigh | 1.0 | +| V_low | 0.7 | + +表3-9 KPU可调电压节点 + +## 4. PCB设计建议 + +### 4.1高速PCB设计建议 + +#### 4.1.1 DDR设计 + +阻抗控制:DDR单线60Ω,差分(时钟clk,数据dqs)120Ω; +串扰要求:遵循3W原则 +等长要求:同类型信号线经过过孔数量保持一致; +芯片内部DDR走线长度如表4-1,在PCB走线时务必考虑,保证内外走线之和满足等长要求。 +PCB设计强烈建议参考K230 EVB的设计,包括走线和电容的选型及摆放。 + +| 管脚编号 | 管脚名称 | 长度(μm) | 长度(mil) | +| -------- | ---------------- | --------- | --------- | +| N17 | DDR_CKE0_CKEA0 | 3725.8 | 146.8 | +| P18 | DDR_CKE1_CKEA1 | 4338.56 | 170.94 | +| T20 | DDR_CS0_CSA0 | 5839.03 | 230.06 | +| T19 | DDR_CS1_CSA1 | 5528.07 | 217.81 | +| R19 | DDR_CKP_CKAP | 6252.24 | 246.34 | +| R20 | DDR_CKN_CKAN | 6050.13 | 238.38 | +| N18 | DDR_NC_NC | 3937.42 | 155.13 | +| M17 | DDR_NC_NC | 1925.8 | 75.88 | +| P19 | DDR_CA9_CAA5 | 5809.3 | 228.89 | +| M18 | DDR_CA8_CAA4 | 4033.87 | 158.93 | +| N20 | DDR_CA7_CAA3 | 4888.23 | 192.6 | +| N19 | DDR_CA6_CAA2 | 4415.08 | 173.95 | +| L16 | DDR_CA5_CAA1 | 2171.4 | 85.55 | +| M19 | DDR_CA4_CAA0 | 4599.65 | 181.23 | +| L17 | DDR_CA3_NC | 2258.98 | 89 | +| M20 | DDR_CA2_NA | 4190.42 | 165.1 | +| L20 | DDR_CA1_NC | 5108.55 | 201.28 | +| K20 | DDR_CA0_NC | 4832.33 | 190.39 | +| L18 | DDR_ODT_NC | 3849.11 | 151.65 | +| J18 | DDR_NC_CKEB0 | 2599.43 | 102.42 | +| J17 | DDR_NC_CKEB1 | 2792.84 | 110.04 | +| J19 | DDR_NC_CSB1 | 4018.49 | 158.33 | +| J20 | DDR_NC_CSB0 | 4941.35 | 194.69 | +| G20 | DDR_NC_CKBP | 5403.63 | 212.9 | +| F20 | DDR_NC_CKBN | 5418.33 | 213.48 | +| H18 | DDR_NC_NC | 4350.39 | 171.41 | +| H19 | DDR_NC_NC | 4900.25 | 193.07 | +| E20 | DDR_NC_CAB0 | 5468.25 | 215.45 | +| G19 | DDR_NC_CAB1 | 4067.91 | 160.28 | +| G18 | DDR_NC_CAB2 | 3807.29 | 150.01 | +| H17 | DDR_NC_CAB3 | 3113.45 | 122.67 | +| F17 | DDR_NC_CAB4 | 2757.73 | 108.65 | +| F19 | DDR_NC_CAB5 | 4558.27 | 179.6 | +| D20 | DDR_NC_NC | 6535.69 | 257.51 | +| G17 | DDR_NC_NC | 3477.72 | 137.02 | +| D19 | DDR_NC_NC | 5257.59 | 207.15 | +| F18 | DDR_NC_NC | 4584.72 | 180.64 | +| C20 | DDR_NC_NC | 6979.27 | 274.98 | +| U17 | DDR_DQ29_DQA7 | 4829.45 | 190.28 | +| Y18 | DDR_DQ28_DQA6 | 6467.43 | 254.82 | +| V18 | DDR_DQ25_DQA5 | 5047.5 | 198.87 | +| W18 | DDR_DQ24_DQA4 | 5267.44 | 207.54 | +| Y16 | DDR_DQ27_DQA3 | 5846.86 | 230.37 | +| V16 | DDR_DQ26_DQA2 | 4311.64 | 169.88 | +| T16 | DDR_DQ30_DQA1 | 3576.39 | 140.91 | +| U16 | DDR_DQ31_DQA0 | 3132.83 | 123.43 | +| V17 | DDR_DM3_DMIA0 | 4110.44 | 161.95 | +| W17 | DDR_DQS3P_DQSA0P | 6342.48 | 249.89 | +| Y17 | DDR_DQS3N_DQSA0N | 6135.17 | 241.73 | +| R17 | DDR_DQ10_DQA8 | 4018.24 | 158.32 | +| T18 | DDR_DQ12_DQA9 | 5760.1 | 226.95 | +| R18 | DDR_DQ8_DQA10 | 4540.62 | 178.9 | +| U20 | DDR_DQ13_DQA11 | 5625.11 | 221.63 | +| W19 | DDR_DQ11_DQA12 | 6897.92 | 271.78 | +| U18 | DDR_DQ14_DQA13 | 4908.14 | 193.38 | +| P16 | DDR_DQ9_DQA14 | 2036.92 | 80.25 | +| T17 | DDR_DQ15_DQA15 | 4492.07 | 176.99 | +| P17 | DDR_DM1_DMIA1 | 4129.14 | 162.69 | +| V20 | DDR_DQS1P_DQSA1P | 7005.11 | 276 | +| V19 | DDR_DQS1N_DQSA1N | 6768.98 | 266.7 | +| C17 | DDR_DQ0_DQB4 | 4038.16 | 159.1 | +| D16 | DDR_DQ1_DQB1 | 3663.33 | 144.34 | +| D17 | DDR_DQ2_DQB0 | 4242.29 | 167.15 | +| C18 | DDR_DQ3_DQB5 | 5598.19 | 220.57 | +| E18 | DDR_DQ4_DQB2 | 3830.51 | 150.92 | +| E17 | DDR_DQ5_DQB3 | 4273.06 | 168.36 | +| B19 | DDR_DQ6_DQB7 | 6879.01 | 271.03 | +| C19 | DDR_DQ7_DQB6 | 6640.84 | 261.65 | +| D18 | DDR_DM0_DMIB0 | 5275.38 | 207.85 | +| B18 | DDR_DQS0P_DQSB0P | 6516.79 | 256.76 | +| A18 | DDR_DQS0N_DQSB0N | 6628.66 | 261.17 | +| C14 | DDR_DQ16_DQB11 | 2966.98 | 116.9 | +| D14 | DDR_DQ20_DQB8 | 2708.03 | 106.7 | +| B14 | DDR_DQ17_DQB10 | 4486.79 | 176.78 | +| A14 | DDR_DQ21_DQB9 | 5608.52 | 220.98 | +| A17 | DDR_DQ19_DQB14 | 5037.71 | 198.49 | +| B16 | DDR_DQ23_DQB15 | 4419.48 | 174.13 | +| C16 | DDR_DQ18_DQB13 | 4381.95 | 172.65 | +| B17 | DDR_DQ22_DQB12 | 5515.88 | 217.33 | +| C15 | DDR_DM2_DMIB1 | 4509.87 | 177.69 | +| B15 | DDR_DQS2P_DQSB1P | 4623.9 | 182.18 | +| A15 | DDR_DQS2N_DQSB1N | 4942.59 | 194.74 | + +表4-1 芯片内部DDR走线长度 + +##### LPDDR3部分 + +- 数据线内部等长要求:(DQ to DQS domain)DQS_P/N and DQ[7:0] & DM for each byte lane, the length of DQ = DQS +/- 10ps +- 地址线内部等长要求:(CS, ODT, CKE, Cmd, Add to CK/CK#) +- When routing CK_P/N and CA signals for the memory interface, the length of the CA = CK +/- 10ps +- DQS与CK之间的等长要求:(DQS to CK domain)When routing DQS for each byte lane, the length of each DQS pair must be (CK – 85ps) <= DQS <= CK + +##### LPDDR4部分 + +- 数据线内部等长要求:DQS_P/N and DQ[7:0] & DM for each byte lane, the length of DQ = DQS +/- 10ps +- 地址线内部等长要求:(CS, ODT, CKE, Cmd, Add to CK/CK#)When routing CK_P/N and CA signals for the memory interface, the length of the CA = CK +/- 10ps +- DQS与CK之间的等长要求:When routing DQS for each byte lane, the length of each DQS pair must be (CK – 60ps) <= DQS <= CK + +#### 4.1.2 USB2.0设计 + +- 阻抗控制:差分90Ω。 +- 差分对内skew不超过4ps,最大允许过孔数量不超过6个。 + +#### 4.1.3 MIPI设计 + +- 阻抗控制:MIPI_DSI差分100Ω,MIPI_CSI差分100Ω +- 线对之内等长控制在0.3mm。 diff --git a/zh/00_hardware/README.md b/zh/00_hardware/README.md new file mode 100755 index 0000000..f5d89b4 --- /dev/null +++ b/zh/00_hardware/README.md @@ -0,0 +1,49 @@ +# K230 SDK Hardware Docs + +## K230 硬件相关文档 + +| 文档名称 | 文档概要 | +| --- | --- | +| [K230_DEMO_BOARD资源使用指南.md](K230_DEMO_BOARD资源使用指南.md) | K230 Demo Board 硬件资源使用说明文档 | +| [K230_硬件设计指南.md](K230_硬件设计指南.md) | K230 硬件设计指南文档 | +| [K230_PINOUT_V1.0_20230524](K230_PINOUT_V1.0_20230524.xlsx) | K230 芯片引脚定义 | +| [K230_datasheet.md](K230_datasheet.md) | K230 Datasheet | + +## K230 工程设计文件 + +| 文档名称 | 文档概要 | +| --- | --- | +| [K230_DEMO_BOARD-20230427-DXF](K230/K230_DEMO_BOARD-20230427-DXF.zip) | K230 Demo Board DXF 文件| +| [K230_DEMO_BOARD-20230427-GERBER](K230/K230_DEMO_BOARD-20230427-GERBER.zip) | K230 Demo Board制板用GERBER文件 | +| [K230_DEMO_BOARD-20230427-PCB](K230/K230_DEMO_BOARD-20230427-PCB.zip) | K230 Demo Board PCB Cadence 设计文件| +| [K230_DEMO_BOARD-20230427-SMT](K230/K230_DEMO_BOARD-20230427-SMT.zip) | K230 Demo Board SMT 焊接排布与钻孔文件| +| [K230-DEMO-BOARD-BOM-20230510](K230/K230-DEMO-BOARD-BOM-20230510.xlsx) | K230 Demo Board所用器件BOM | +| [K230-DEMO-BOARD-SCH.DSN](K230/K230-DEMO-BOARD-SCH.DSN) | K230 Demo Board 原理图Cadence CIS Capture文件 | +| [K230-DEMO-BOARD-SCH.pdf](K230/K230-DEMO-BOARD-SCH.pdf) | K230 Demo Board 原理图 pdf文件 | + +## K230D 工程设计文件 + +| 文档名称 | 文档概要 | +| --- | --- | +| [K230-SIP-EVB-V1_0-A_1-20230322-DXF](K230D/K230-SIP-EVB-V1_0-A_1-20230322-DXF.zip) | K230D Demo Board DXF 文件| +| [K230-SIP-EVB-V1_0-A_1-20230322-GERBER](K230D/K230-SIP-EVB-V1_0-A_1-20230322-GERBER.zip) | K230D Demo Board制板用GERBER文件 | +| [K230-SIP-EVB-V1_0-A_1-20230322-PCB](K230D/K230-SIP-EVB-V1_0-A_1-20230322-PCB.zip) | K230D Demo Board PCB Cadence 设计文件| +| [K230-SIP-EVB-V1_0-A_1-20230322-SMT](K230D/K230-SIP-EVB-V1_0-A_1-20230322-SMT.zip) | K230D Demo Board SMT 焊接排布与钻孔文件| +| [K230-SIP-EVB-V1_0-A_1_20230316-BOM](K230D/K230-SIP-EVB-V1_0-A_1_20230316-BOM.xlsx) | K230D Demo Board所用器件BOM | +| [K230-SIP-EVB-V1_0-A_1-20230316.DSN](K230D/K230-SIP-EVB-V1_0-A_1-20230316.DSN) | K230D Demo Board 原理图Cadence CIS Capture文件 | +| [K230-SIP-EVB-V1.0-A.1-20230317.pdf](K230D/K230-SIP-EVB-V1.0-A.1-20230317.pdf) | K230D Demo Board 原理图 pdf文件 | + +## 贡献指南 + +如果您对本项目感兴趣,想要反馈问题或提交文档,请参考[CONTRIBUTING](/.github/CONTRIBUTING.md) + +## 联系我们 + +北京嘉楠捷思信息技术有限公司 +网址:[canaan-creative.com](https://www.canaan-creative.com/) +商务垂询:[salesAI@canaan-creative.com](mailto:salesAI@canaan-creative.com) + +**翻译免责声明** +为方便客户,Canaan 使用 AI 翻译程序将文本翻译为多种语言,它可能包含错误。我们不保证提供的译文的准确性、可靠性或时效性。对于因依赖已翻译信息的准确性或可靠性而造成的任何损失或损害,Canaan 概不负责。如果不同语言翻译之间存在内容差异,以简体中文版本为准。 + +如果您要报告翻译错误或不准确的问题,欢迎通过邮件与我们联系。 diff --git a/zh/00_hardware/images/GPIO_electric.png b/zh/00_hardware/images/GPIO_electric.png new file mode 100755 index 0000000..d3e42e4 Binary files /dev/null and b/zh/00_hardware/images/GPIO_electric.png differ diff --git a/zh/00_hardware/images/HDG/canaan-cover.png b/zh/00_hardware/images/HDG/canaan-cover.png new file mode 100755 index 0000000..0319765 Binary files /dev/null and b/zh/00_hardware/images/HDG/canaan-cover.png differ diff --git a/zh/00_hardware/images/HDG/figure1_1.jpg b/zh/00_hardware/images/HDG/figure1_1.jpg new file mode 100755 index 0000000..499ef98 Binary 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a/zh/00_hardware/images/logo.png b/zh/00_hardware/images/logo.png new file mode 100755 index 0000000..aa48558 Binary files /dev/null and b/zh/00_hardware/images/logo.png differ diff --git "a/zh/01_software/board/K230_SDK_\344\275\277\347\224\250\350\257\264\346\230\216.md" "b/zh/01_software/board/K230_SDK_\344\275\277\347\224\250\350\257\264\346\230\216.md" new file mode 100755 index 0000000..92586a3 --- /dev/null +++ "b/zh/01_software/board/K230_SDK_\344\275\277\347\224\250\350\257\264\346\230\216.md" @@ -0,0 +1,712 @@ +# K230 SDK使用说明 + +![cover](images/canaan-cover.png) + +版权所有©2023北京嘉楠捷思信息技术有限公司 + +
+ +## 免责声明 + +您购买的产品、服务或特性等应受北京嘉楠捷思信息技术有限公司(“本公司”,下同)及其关联公司的商业合同和条款的约束,本文档中描述的全部或部分产品、服务或特性可能不在您的购买或使用范围之内。除非合同另有约定,本公司不对本文档的任何陈述、信息、内容的正确性、可靠性、完整性、适销性、符合特定目的和不侵权提供任何明示或默示的声明或保证。除非另有约定,本文档仅作为使用指导参考。 + +由于产品版本升级或其他原因,本文档内容将可能在未经任何通知的情况下,不定期进行更新或修改。 + +## 商标声明 + +![logo](images/logo.png)、“嘉楠”和其他嘉楠商标均为北京嘉楠捷思信息技术有限公司及其关联公司的商标。本文档可能提及的其他所有商标或注册商标,由各自的所有人拥有。 + +**版权所有 © 2023北京嘉楠捷思信息技术有限公司。保留一切权利。** +非经本公司书面许可,任何单位和个人不得擅自摘抄、复制本文档内容的部分或全部,并不得以任何形式传播。 + +
+ +## 目录 + +[TOC] + +## 前言 + +### 概述 + +本文档主要介绍K230 SDK 的安装和使用。 + +### 读者对象 + +本文档(本指南)主要适用于以下人员: + +- 技术支持工程师 +- 软件开发工程师 + +### 缩略词定义 + +| 简称 | 说明 | +|------|------| +| | | + +### 修订记录 + +| 文档版本号 | 修改说明 | 修改者 | 日期 | +| ---------- | -------------------------- | ------ | ---------- | +| V1.0 | 初版 | 杨光 | 2023-03-10 | +| V1.1 | 新增安全镜像及emmc烧录说明 | 王建新 | 2023-04-07 | +| V1.2 | 新增spinor镜像烧录说明 | 王建新 | 2023-05-05 | +| V1.3 | 快起和安全镜像说明 | 王建新 | 2023-05-29 | +| V1.4 | 大核自启动程序说明 | 郝海波 | 2023-06-1 | +| v1.5 | usip lp4 | 王建新 | 2023-06-12 | +| V1.6 | 修改大核自启动程序说明 | 赵忠祥 | 2023-06-28 | +| v1.7 | 增加启动介质分区章节,镜像烧录章节调整, | 王建新 | 2023-07-05 | + +## 1. 概述 + +### 1.1 SDK软件架构概述 + +K230 SDK 是面向K230 开发板的软件开发包,包含了基于Linux&RT-smart 双核异构系统开发需要用到的源代码,工具链和其他相关资源。 + +K230 SDK 软件架构层次如图 1-1 所示: + +![logo](images/cee49715351f6dd3496baf19af1262ed.png) + +图1-1 K230 SDK 软件架构图 + +## 2. 开发环境搭建 + +### 2.1 支持的硬件 + +K230-USIP-LP3-EVB:具体硬件信息参考 《K230-USIP-LP3-EVB-硬件使用说明》 + +K230-USIP-LP4-EVB:具体硬件信息参考 《K230-USIP-LP4-EVB-硬件使用说明》 + +### 2.2 开发环境搭建 + +#### 2.2.1 编译环境 + +| 主机环境 | 描述 | +|-----------------------------|------------------------------------------------------| +| Docker编译环境 | SDK提供了dockerfile,可以生成docker镜像,用于编译SDK | +| Ubuntu 20.04.4 LTS (x86_64) | SDK可以在ubuntu 20.04环境下编译 | + +K230 SDK需要在linux环境下编译,SDK支持docker环境编译,SDK开发包中发布了docker file(`tools/docker/Dockerfile`),可以生成docker镜像。具体dockerfile使用和编译步骤,详见4.3.1章节。 + +SDK使用的Docker 镜像以ubuntu 20.04 为基础,如果不使用docker编译环境,可以在ubuntu 20.04 主机环境下参考dockerfile的内容,安装相关HOST package和工具链后,编译SDK。 + +K230 SDK没有在其他Linux版本的主机环境下验证过,不保证SDK可以在其他环境下编译通过。 + +#### 2.2.2 SDK开发包 + +K230 SDK以压缩包的形式发布,或者自己使用`git clone https://github.com/kendryte/k230_sdk`命令下载。 + +### 2.3 单板准备 + +本章节以K230-USIP-LP3-EVB为例 + +请准备如下硬件: + +- K230-USIP-LP3-EVB +- Typec USB线 至少2根 +- TypeC USB 转以太网转换器(可选) +- 网线一根(可选) +- SD卡(可选) + +说明:TypeC USB 转以太网推荐型号是 + +参考《K230-USIP-LP3-EVB-硬件使用说明》准备开发板。 + +K230 EVB通过USB提供两路调试串口,windows下使用调试串口,需要安装USB转串口驱动程序,驱动下载链接如下: + + + +安装了驱动后,板子上电,PC使用type C数据线连接EVB的调试串口后,可以发现两个USB串口设备,如下图所示: + +![图形用户界面, 文本, 应用程序 描述已自动生成](images/bcb6636268b91758f87ff54523251eeb.png) + +图2-1 USB串口设备 + +以上图为例,`COM47`为小核的调试串口,`COM48`为大核的调试串口。 + +串口波特率设置: `115200 8N1` + +## 3. SDK 安装准备工作 + +### 3.1 安装SDK + +K230 SDK开发包采用压缩包的方式发布,在linux环境下使用。 + +### 3.2 SDK 目录结构 + +K230 SDK目录结构如下图所示: + +```shell +k230_sdk +├── configs +│   ├── k230_evb_defconfig +│   └── k230_evb_usiplpddr4_defconfig +├── Kconfig +├── LICENSE +├── Makefile +├── parse.mak +├── README.md +├── repo.mak +├── src +│   ├── big +│   │   ├── mpp +│   │   ├── rt-smart +│   │   └── unittest +│   ├── common +│   │   ├── cdk +│   │   └── opensbi +│   ├── little +│   │   ├── buildroot-ext +│   │   ├── linux +│   │   └── uboot +│   └── reference +│   ├── ai_poc +│   ├── business_poc +│   └── fancy_poc +└── tools + ├── docker + │   └── Dockerfile + ├── doxygen + ├── firmware_gen.py + ├── gen_image_cfg + ├── gen_image.sh + ├── get_download_url.sh + └── post_copy_rootfs +``` + +各个目录用途描述如下: + +- `configs`: 存放SDK的板级默认配置,主要包含如下信息:参考板类型,toolchain路径, + + 内存布局规划,存储规划配置等 + +- `src`:源代码目录,分为 大核代码(`big`),公共组件(`common`),小核代码(`little`)三个目录。 + + 大核代码包含:`rt-smart`操作系统代码,`mpp`代码,`unittest`代码 + + 公共组件包含:`cdk`代码和`opensbi`代码 + + 小核代码包含:`linux`内核代码,`buildroot`代码,`uboot`代码 + +- `tools`:存放各种工具,脚本等。例如`kconfig`,`doxygen`,`dockerfile`等 + +## 4. SDK 编译 + +### 4.1 SDK 编译介绍 + +K230 SDK支持一键编译大小核操作系统和公共组件,生成可以烧写的镜像文件,用于部署到开发板启动运行。设备上linux系统的用户名是root无密码; + +### 4.2 SDK 配置 + +K230 SDK采用Kconfig作为SDK配置接口,默认支持的板级配置放在configs目录下。 + +#### 4.2.1 配置文件说明 + +`k230_evb_defconfig` :基于K230 USIP LP3 EVB的默认SDK配置文件 +`k230_evb_usiplpddr4_defconfig` :基于K230 USIP LP4 EVB的默认SDK配置文件 + +### 4.3 编译 SDK + +#### 4.3.1 编译步骤 + +说明:本章节命令仅供参考,文件名请根据实际情况进行替换。 +Setp 1:下载代码 + +`git clone https://github.com/kendryte/k230_sdk` + +Step 2:进入SDK根目录 + +`cd k230_sdk` + +Step 3:下载toolchain + +```shell +source tools/get_download_url.sh && make prepare_sourcecode +``` + +>`make prepare_sourcecode` will download both Linux and RT-Smart toolchain, buildroot package and AI package from Microsoft Azure cloud server with CDN, the download cost time may based on your network connection speed. + +Step 4:生成docker镜像(第一次编译需要,已经生成docker镜像后跳过此步骤) + +`docker build -f tools/docker/Dockerfile -t k230_docker tools/docker` + +Step 5: 进入docker环境, + +`docker run -u root -it -v $(pwd):$(pwd) -v $(pwd)/toolchain:/opt/toolchain -w $(pwd) k230_docker /bin/bash` + +Step 6: Docker环境下执行下面命令进行编译SDK + +```bash +make CONF=k230_evb_defconfig #编译K230-USIP-LP4-EVB板子镜像 +#make CONF=k230_evb_usiplpddr4_defconfig #编译K230-USIP-LP4-EVB板子镜像 +``` + +> 编译K230-USIP-LP4-EVB板子镜像使用`make CONF=k230_evb_usiplpddr4_defconfig`命令 +> 编译K230-USIP-LP3-EVB板子镜像使用`make CONF=k230_evb_defconfig` 命令。 + +特别的: +如果需要nand镜像,先做以下修改,然后重新进行步骤'Step 5',进行编译。 +1)小核uboot下,修改k230_sdk\src\little\uboot\arch\riscv\dts\k230_evb.dts 中spi0节点的配置,即测试nandflash时,编译前将compatible 设置为 "spi-nand";测试norflash时,将compatible设为"jedec,spi-nor", +&spi0 { + spi-flash@0 { + //compatible = "spi-nand"; + compatible = "jedec,spi-nor"; + reg = <0>; + +2)小核linux下,修改k230_sdk\src\little\linux\arch\riscv\boot\dts\kendryte\k230_evb.dtsi 中spi0节点的配置,将k230_evb_nand.dtsi内容覆盖到k230_evb.dtsi,以修改SPI0节点的内容。(两个dtsi仅SPI0节点内容不同) +3)k230_sdk下,修改k230_sdk\parse.mak,禁用:'$(K230_SDK_ROOT)/tools/menuconfig_to_code.sh' + +#### 4.3.2 编译输出产物 + +编译完成后,在`output/xx_defconfig/images`目录下可以看到编译输出产物。 + +![文本 描述已自动生成](images/da6d48091ee0af8107a63cde01a2b75b.png) + +图4-1 编译产物 + +`images`目录下镜像文件说明如下: + +`sysimage-sdcard.img` -------------是sd和emmc的非安全启动镜像; + +`sysimage-sdcard.img.gz` --------是SD和emmc的非安全启动镜像压缩包(sysimage-sdcard.img文件的gzip压缩包),烧录时需要先解压缩。 + +`sysimage-sdcard_aes.img.gz`是SD和emmc的aes安全启动镜像压缩包,烧录时需要先解压缩。 + +`sysimage-sdcard_sm.img.gz`是SD和emmc的sm安全启动镜像压缩包,烧录时需要先解压缩。 + +安全镜像默认不会产生,如果需要安全镜像请参考4.3.4使能安全镜像。 + +大核系统的编译产物放在`images/big-core`目录下。 + +小核系统的编译产物放在`images/little-core`目录下。 + +#### 4.3.3 非快起镜像 + +sdk默认编译的是快起镜像(uboot直接启动系统,不会进入uboot命令行),如果需要进入uboot命令行,请参考下面取消`CONFIG_QUICK_BOOT`配置: + +在sdk主目录 执行 `make menuconfig` ,选择`board configuration`,取消`quick boot` 配置选项。 + +#### 4.3.4 安全镜像 + +sdk默认不产生安全镜像,如果需要安全镜像,请参考下面增加CONFIG_GEN_SECURITY_IMG配置: + +在sdk主目录 执行`make menuconfig` ,选择`board configuration`,配上`create security image` 选项。 + +## 5. SDK 镜像烧写 + +### 5.1 sd卡镜像烧录 + +#### 5.1.1 ubuntu下烧录 + +在sd卡插到宿主机之前,输入: + +`ls -l /dev/sd\*` + +查看当前的存储设备。 + +将sd卡插入宿主机后,再次输入: + +`ls -l /dev/sd\*` + +查看此时的存储设备,新增加的就是 sd 卡设备节点。 + +假设/dev/sdc 就是 sd卡设备节点,执行如下命令烧录SD卡: + +`sudo dd if=sysimage-sdcard.img of=/dev/sdc bs=1M oflag=sync` + +说明:`sysimage-sdcard.img`可以是`images`目录下的`sysimage-sdcard.img`文件,或者`sysimage-sdcard_aes.img.gz`、`sysimage-sdcard.img.gz`、`sysimage-sdcard_sm.img.gz`文件解压缩后的文件。 + +#### 5.1.2 Windows下烧录 + +Windows下可通过balena Etcher工具对sd卡进行烧录(balena Etcher工具下载地址)。 + +1)将TF卡插入PC,然后启动balena Etcher工具,点击工具界面的"Flash from file”按钮,选择待烧写的固件,如下图。 + +![图形用户界面, 应用程序 描述已自动生成](images/3e2358e04601c3e03bf233c84f8b3ec4.png) + +图5-1 选择固件 + +2)点击工具界面的“Select target”按钮,选择目标sdcard卡。 + +![图形用户界面, 文本, 应用程序 描述已自动生成](images/4d9f7101ce0225108752d4cae16c9663.png) + +图5-2 选择SD卡 + +3)点击“Flash”按钮开始烧写,烧写过程有进度条展示,烧写结束后会提示Flash Finish。 + +4)当烧录完成后,将SD卡插入开发板卡槽,选择 BOOT为从SD启动,最后开发板上电即可从SD卡启动。 + +![手机屏幕的截图 描述已自动生成](images/84c28ea8eb1de88fe5b4a1b2c122767d.jpg) + +图5-3 开始烧录 + +![图形用户界面, 应用程序 描述已自动生成](images/578b62c404f1f18af8c6aa342e5830b5.jpg) + +图5-4 烧录完成 + +说明:使用`sysimage-sdcard_aes.img.gz`、`sysimage-sdcard.img.gz`、`sysimage-sdcard_sm.img.gz`文件时需要先解压缩,烧录解压缩后的文件。 + +### 5.2 Emmc镜像烧写参考 + +#### 5.2.1 Linux下烧写参考 + +1)把镜像的压缩包下载到sd卡 + +从sd卡启动linux,在linux下可以参考如下命令把镜像的压缩包下载到sd卡 + +```shell +ifconfig eth0 up;udhcpc;mount /dev/mmcblk1p4 /mnt;cd /mnt/; + +scp wangjianxin@10.10.1.94:/home/wangjianxin/k230_sdk/output/k230_evb_defconfig/images/sysimage-sdcard.img.gz . +``` + +2)把压缩包解压缩到emmc + +`gunzip sysimage-sdcard.img.gz -c >/dev/mmcblk0` + +3)切成emmc启动,重启板子 + +### 5.3 Spinor镜像烧写参考 + +#### 5.3.1 Uboot下烧写参考 + +1)把sysimage-spinor32m.img镜像下载到内存。 + +`usb start; dhcp; tftp 0x9000000 10.10.1.94:wjx/sysimage-spinor32m.img;` + +2)把镜像写到spi nor flash + +`sf probe 0:0;sf erase 0 0x2000000;sf write 0x$fileaddr 0 0x$filesize; sf remove;` + +3)重启板子 + +#### 5.3.2 linux烧写spinor + +1)把spinor镜像sysimage-spinor32m.img下载到sd卡 + +从sd卡启动linux,在linux下可以参考如下命令把镜像到sd卡 + +```bash +ifconfig eth0 up; udhcpc; mount /dev/mmcblk1p4 /mnt;cd /mnt/; +scp wangjianxin@10.10.1.94:/home/wangjianxin/k230_sdk/output/k230_evb_defconfig/images/sysimage-spinor32m.img . +``` + +2)参考下面命令把镜像写入spi nor flash + +```bash +[root@canaan /mnt ]#flashcp -v sysimage-spinor32m.img /dev/mtd9 +Erasing blocks: 508/508 (100%) +Writing data: 32512k/32512k (100%) +Verifying data: 32512k/32512k (100%) +[root@canaan /mnt ]# +``` + +3)切成spi nor启动,重启板子 + +#### 5.3.3 Spinor镜像说明 + +由于spinor flash比较小, linux删掉了ko、rtt删掉了部分demo程序。 + +### 5.4. Spinand镜像烧写参考 + +#### 5.4.1 Uboot下烧写参考 + +1)把sysimage-spinand32m.img镜像下载到内存。 + +`usb start; dhcp; tftp 0x9000000 10.10.1.94:wjx/sysimage-spinand32m.img;` + +2)把镜像写到spi nand flash + +`mtd erase spi-nand0 0 0x2000000;mtd write spi-nand0 0x$fileaddr 0 0x$filesize;` + +3)重启板子 + +## 6. sdk启动介质分区及修改 + +### 6.1 spi nor + +#### 6.1.1 spi nor默认分区 + +![image-spi_nor_default_part](images/image-spi_nor_default_part.png) + +| spinor分区 | | | | | +| ------------- | --------- | -------- | ------ | ------- | +| 内容 | 开始地址 | 大小 | 大小MB | 大小 | +| 一级uboot | 0x0 | 512KB | 0.5 | 512KB | +| 二级uboot | 0x80000 | 0x160000 | 1.375 | 1.375MB | +| uboot环境变量 | 0x1e0000 | 128KB | 0.125 | 128KB | +| 快起参数 | 0x200000 | 512KB | 0.5 | 512KB | +| 人脸特性 | 0x280000 | 512kB | 0.5 | 512kB | +| 标定参数 | 0x300000 | 256KB | 0.25 | 256KB | +| ai模型 | 0x340000 | 3MB | 3 | 3MB | +| 散斑 | 0x640000 | 2MB | 2 | 2MB | +| rtt | 0x840000 | 0x1c0000 | 1.75 | 1.75MB | +| rtapp | 0xa00000 | 0x5c0000 | 5.75 | 3.75MB | +| linux | 0xfc0000 | 0x700000 | 7 | 7MB | +| rootfs | 0x16c0000 | 0xb00000 | 13 | 13MB | + +#### 6.1.2 分区修改及实现说明 + +在sdk主目录执行 make menuconfig --->storage configurations--->spi nor partion config 进行分区修改(界面如下);修改完后执行下make build-image; + +![image-image-menuconfig_spi_nor_part](images/image-menuconfig_spi_nor_part.png) + +通过menuconfig修改分区详细实现说明: + +make menuconfig配置完后会生成.config(部分内容如下) + +```bash +CONFIG_SPI_NOR_SENSOR_CFG_CFG_BASE=0x300000 +CONFIG_SPI_NOR_SENSOR_CFG_CFG_SIZE=0x40000 +CONFIG_SPI_NOR_AI_MODE_CFG_BASE=0x340000 +CONFIG_SPI_NOR_AI_MODE_CFG_SIZE=0x300000 +CONFIG_SPI_NOR_SPECKLE_CFG_BASE=0x640000 +CONFIG_SPI_NOR_SPECKLE_CFG_SIZE=0x200000 +CONFIG_SPI_NOR_RTTK_BASE=0x840000 +CONFIG_SPI_NOR_RTTK_SIZE=0x1c0000 +CONFIG_SPI_NOR_RTT_APP_BASE=0xa00000 +CONFIG_SPI_NOR_RTT_APP_SIZE=0x5c0000 +CONFIG_SPI_NOR_LK_BASE=0xfc0000 +CONFIG_SPI_NOR_LK_SIZE=0x700000 +CONFIG_SPI_NOR_LR_BASE=0x16c0000 +CONFIG_SPI_NOR_LR_SIZE=0x900000 +``` + +tools/menuconfig_to_code.sh 脚本会根据这些定义动态(关键脚本如下)修改linux设备树和tools/gen_image_cfg/genimage-spinor.cfg文件; + +```bash +image sysimage-spinor32m.img { + flash {} + flashtype = "spinor-32M-gd25lx256e" + ..... + partition quick_boot_cfg { + offset = ${CONFIG_SPI_NOR_QUICK_BOOT_CFG_BASE} + image = "${quick_boot_cfg_data_file}" + size = ${CONFIG_SPI_NOR_QUICK_BOOT_CFG_SIZE} + } + + partition face_db { + offset = ${CONFIG_SPI_NOR_FACE_DB_CFG_BASE} + image = "${face_database_data_file}" + size = ${CONFIG_SPI_NOR_FACE_DB_CFG_SIZE} + } + + partition sensor_cfg { + offset = ${CONFIG_SPI_NOR_SENSOR_CFG_CFG_BASE} + image = "${sensor_cfg_data_file}" + size = ${CONFIG_SPI_NOR_SENSOR_CFG_CFG_SIZE} + } + + partition ai_mode { + offset = ${CONFIG_SPI_NOR_AI_MODE_CFG_BASE} + image = "${ai_mode_data_file}" + size = ${CONFIG_SPI_NOR_AI_MODE_CFG_SIZE} + } + + partition speckle_cfg { + offset = ${CONFIG_SPI_NOR_SPECKLE_CFG_BASE} + image = "${speckle_data_file}" + size = ${CONFIG_SPI_NOR_SPECKLE_CFG_SIZE} + } + + partition rtt { + offset = ${CONFIG_SPI_NOR_RTTK_BASE} + image = "big-core/rtt_system.bin" + size = ${CONFIG_SPI_NOR_RTTK_SIZE} + } + partition rtt_app { + offset = ${CONFIG_SPI_NOR_RTT_APP_BASE} + image = "${rtapp_data_file}" + size = ${CONFIG_SPI_NOR_RTT_APP_SIZE} + } + + partition linux { + offset = ${CONFIG_SPI_NOR_LK_BASE} + image = "little-core/linux_system.bin" + size = ${CONFIG_SPI_NOR_LK_SIZE} + } + partition rootfs_ubi { + offset = ${CONFIG_SPI_NOR_LR_BASE} + image = "rootfs.ubi" + size = ${CONFIG_SPI_NOR_LR_SIZE} + } +} +``` + +最后genimage 会解析tools/gen_image_cfg/genimage-spinor.cfg 文件并生成正确的镜像。 + +```bash +genimage --rootpath little-core/rootfs/ --tmppath genimage.tmp --inputpath images --outputpath images +--config tools/gen_image_cfg/genimage-spinor.cfg +``` + +#### 6.1.3分区数据格式及生成过程 + +目前快起参数、人脸特性、标定参数、ai模型、散斑、rtt、rtapp等参数分区的数据均不加密,其格式及生成过程如下: + +![image-20230705151949318](images/image-non_crypt.png) + +主要生成脚本如下: + +```bsh +#更详细的生成细节请阅读 tools/gen_image.sh 脚本的gen_cfg_part_bin函数 +${k230_gzip} -f -k ${filename} #gzip +sed -i -e "1s/\x08/\x09/" ${filename}.gz +#add uboot head +${mkimage} -A riscv -O linux -T firmware -C gzip -a ${add} -e ${add} -n ${name} -d ${filename}.gz ${filename}.gzu; +python3 ${firmware_gen} -i ${filename}.gzu -o fh_${filename} ${arg}; #add k230 firmware head + +对应执行过程打印如下: +## + k230_priv_gzip -n8 -f -k speckle.bin +## + sed -i -e '1s/\x08/\x09/' speckle.bin.gz +## + mkimage -A riscv -O linux -T firmware -C gzip -a 0x14040000 -e 0x14040000 -n speckle -d speckle.bin.gz speckle.bin.gzu +## Image Name: speckle +## Created: Wed Jul 5 15:37:49 2023 +## Image Type: RISC-V Linux Firmware (gzip compressed) +## Data Size: 45 Bytes = 0.04 KiB = 0.00 MiB +## Load Address: 14040000 +## Entry Point: 14040000 +## + python3 /home/wangjianxin/k230_sdk/tools/firmware_gen.py -i speckle.bin.gzu -o fh_speckle.bin -n +## the magic is: b'K230' +## ----- NO ENCRYPTION + HASH-256 ----- +## the encryption type: 0 +## mesg_hash: b'3543e2038aedad88a29f8ee98983064367cc79f6e709ed7571df9b391884b8b1' +``` + +uboot启动的时候会解析校验参数分区(快起参数、人脸特性、标定参数、ai模型、散斑、rtt、rtapp)数据,并把解析后的原始数据读到内存的正确位置。 + +各个参数分区在内存的位置可以通过make menuconfig--Memory configuration进行配置(参考界面如下) + +![image-20230705153242437](images/image-memconfig_part.png) + +#### 6.1.4 rtapp和ai mode分区特殊说明 + +rtapp分区的app不能重复执行,设计这个分区的目的是节省内存,这个分区的app执行一遍后内存可能会被释放掉,不能重复执行; + +编译的时候会把大核romfs文件系统里面模型文件的指针修改到ai模型区域(见下面脚本),使用方法和普通文件一样使用就行。 + +```bash +#详见tools/gen_image.sh 文件 +for f in ${all_kmode}; + do + eval fstart="\${${f%%\.*}_start}" + eval fsize="\${${f%%\.*}_size}" + fstart=$(printf "0x%x" $((${fstart} + ${CONFIG_MEM_AI_MODEL_BASE}))) + fsize=$(printf "0x%x" ${fsize}) + sed -i "s/_bin_$f,/(char*)${fstart},/g" ${RTSMART_SRC_DIR}/kernel/bsp/maix3/applications/romfs.c + sed -i "s/sizeof(_bin_$f)/${fsize}/g" ${RTSMART_SRC_DIR}/kernel/bsp/maix3/applications/romfs.c + done +``` + +#### 6.1.5 spi nor验证过的型号 + +gd25lx256e + +### 6.2 sd和emmc + +#### 6.2.1 sd和emmc默认分区 + +![image-20230705100321637](images/sd_emmc默认分区.png) + +| SD、emmc卡默认分区 | | | | | +| ------------------ | --------- | ---------- | ------ | ----- | +| 内容 | 开始地址 | 大小值 | 大小MB | 大小 | +| mbr分区表 | 0x0 | 0x100000 | 1 | 1MB | +| 一级uboot | 0x100000 | 0x80000 | 0.5 | 512KB | +| 备用一级boot | 0x180000 | 0x60000 | 0.375 | 384KB | +| uboot环境变量 | 0x1e0000 | 0x20000 | 0.125 | 128KB | +| 二级uboot | 0x200000 | 0x800000 | 0.5 | 8MB | +| rtt | 0xa00000 | 0x1400000 | 20 | 20MB | +| linux | 0x1e00000 | 0x6200000 | 98 | 98MB | +| rootfs | 0x8000000 | 0x5000000 | 80 | 80MB | +| 测试分区 | 0xd000000 | 0x10000000 | 256 | 256MB | + +#### 6.2.2 sd和emmc分区修改 + +如果需要分区请修改tools/gen_image_cfg/genimage-sdcard.cfg 文件,修改完后执行下make build-image + +### 6.3 spi nand + +#### 6.3 spi nand默认分区 + +![image-20230705111015174](images/image-spi_nand_part.png) + +| spinand分区 | | | | | | +| ------------- | --------- | -------- | --------- | ------ | ------- | +| 内容 | 开始地址 | 大小 | 开始地址 | 大小MB | 大小 | +| 一级uboot | 0x0 | 512KB | 0x0 | 0.5 | 512KB | +| 二级uboot | 0x80000 | 0x160000 | 0x80000 | 1.375 | 1.375MB | +| uboot环境变量 | 0x1e0000 | 128KB | 0x1e0000 | 0.125 | 128KB | +| rtt | 0x200000 | 0x800000 | 0x200000 | 8 | 8MB | +| linux | 0xa00000 | 0x700000 | 0xa00000 | 7 | 7MB | +| rootfs | 0x1100000 | 0xf00000 | 0x1100000 | 15 | 15MB | + +#### 6.3.2 spi nand分区修改 + +如果需要分区请修改tools/gen_image_cfg/genimage-spinand.cfg 文件,修改完后执行下make build-image + +#### 6.3.4 spi nand验证过的型号 + +w25n01gw + +## 7. SDK内存配置 + +在k230_sdk下运行`make menuconfig->Memory configuration`可以配置各个区域使用的内存空间,也可以直接编译configs/k230_evb_defconfig修改,各区域说明如下 + +``` shell +CONFIG_MEM_TOTAL_SIZE="0x20000000" #内存总体容量 不支持配置 +CONFIG_MEM_PARAM_BASE="0x00000000" #参数分区起始地址 不支持配置 +CONFIG_MEM_PARAM_SIZE="0x00100000" #参数分区大小 不支持配置 +CONFIG_MEM_IPCM_BASE="0x00100000" #核间通讯起始地址 不支持配置 +CONFIG_MEM_IPCM_SIZE="0x00100000" #核间通讯共享内存大小 不支持配置 +CONFIG_MEM_RTT_SYS_BASE="0x00200000" #大核RTT起始地址 支持配置 +CONFIG_MEM_RTT_SYS_SIZE="0x07E00000" #大核RTT使用的地址范围 支持配置 +CONFIG_MEM_AI_MODEL_BASE="0x1FC00000" #AI模型加载起始地址 支持配置 +CONFIG_MEM_AI_MODEL_SIZE="0x00400000" #AI模型加载地址区域 支持配置 +CONFIG_MEM_LINUX_SYS_BASE="0x08000000" #小核linux起始地址 支持配置 +CONFIG_MEM_LINUX_SYS_SIZE="0x08000000" #小核linux地址区域 支持配置 +CONFIG_MEM_MMZ_BASE="0x10000000" #mmz共享内存其实地址 支持配置 +CONFIG_MEM_MMZ_SIZE="0x0FC00000" #mmz 共享内存区域 支持配置 +CONFIG_MEM_BOUNDARY_RESERVED_SIZE="0x00001000" #隔离区 不支持配置 +``` + +## 8. SDK单板调试 + +### 8.1 调试前准备 + +1.从 T-Head 公 司 的 OCC 平 台下载`T-Head-DebugServer`软件和《DebugServer User Guide v5.6》,并参考《DebugServer User Guide v5.6》在pc电脑上安装`T-Head-DebugServer`软件; + +![图形用户界面, 文本, 应用程序 描述已自动生成](images/830f7333997768ba1fa01e69aedeeb88.png) + +![图形用户界面, 文本, 应用程序, 电子邮件 描述已自动生成](images/a3ee5b66a56b295c092465fec74ed086.png) + +2.准备下图所示平头哥 cklink、usb线、k230 evb板 + +![图片包含 游戏机, 电缆, 电路 描述已自动生成](images/8e91f1cc85daee080e3de5f875542bc8.png) + +### 8.2 调试 + +1.参考下图把cklink 、k230 evb板子、pc电脑 连接起来,随后给evb上电。 + +![电子仪器被放在电脑旁边 中度可信度描述已自动生成](images/cc18bccbf8054dde022db7f9c07df307.png) + +2.电脑上打开第1步安装的T-HeadDebugServer软件,看到类似如下图打印说明连接成功,如果连接失败请参考《DebugServer User Guide v5.6》排查失败原因。 + +![文本 描述已自动生成](images/33d48fa7906e4bf8a0aed4aad7c28178.png) + +3.在编译代码的服务器上启动riscv64-unknown-linux-gnu-gdb执行target remote xx.xx.xx.xx1025 命令连接板子,连接成功后进行gdb调试。 + +![文本 描述已自动生成](images/2fed09a9dbe48eeeb639b6f977861c77.png) + +## 9. SDK启动 + +当前版本默认编译生成的镜像,烧录到板子上后,大核会自动运行一个程序。 + +SDK V0.7版本的自启动程序为基于OV9732摄像头的人脸检测程序,启动后可以在大核的控制台端输入'q'退出该程序。 + +若使用的EVB板没有连接OV9732,则该自启动程序会报错,同样在大核的控制台端输入'q'退出该程序。 +若需要取消大核的自启动功能,需将 `k230_sdk/src/big/rt-smart/init.sh` 中的内容注释掉。 + +SDK V0.8版本的自启动程序是基于IMX335摄像头(板载晶振)的人脸检测程序,启动后在大核的控制台输入'q'可以退出程序。 + +同样的,如果没有连接IMX335,则自启动程序报错,程序自动退出。按回车即可回到控制台。 diff --git "a/zh/01_software/board/ai/K230_nncase_\345\274\200\345\217\221\346\214\207\345\215\227.md" "b/zh/01_software/board/ai/K230_nncase_\345\274\200\345\217\221\346\214\207\345\215\227.md" new file mode 100644 index 0000000..15269bc --- /dev/null +++ "b/zh/01_software/board/ai/K230_nncase_\345\274\200\345\217\221\346\214\207\345\215\227.md" @@ -0,0 +1,2454 @@ +# K230 nncase开发指南 + +![cover](images/canaan-cover.png) + +版权所有©2023北京嘉楠捷思信息技术有限公司 + +
+ +## 免责声明 + +您购买的产品、服务或特性等应受北京嘉楠捷思信息技术有限公司(“本公司”,下同)及其关联公司的商业合同和条款的约束,本文档中描述的全部或部分产品、服务或特性可能不在您的购买或使用范围之内。除非合同另有约定,本公司不对本文档的任何陈述、信息、内容的正确性、可靠性、完整性、适销性、符合特定目的和不侵权提供任何明示或默示的声明或保证。除非另有约定,本文档仅作为使用指导参考。 + +由于产品版本升级或其他原因,本文档内容将可能在未经任何通知的情况下,不定期进行更新或修改。 + +## 商标声明 + +![logo](images/logo.png)、“嘉楠”和其他嘉楠商标均为北京嘉楠捷思信息技术有限公司及其关联公司的商标。本文档可能提及的其他所有商标或注册商标,由各自的所有人拥有。 + +**版权所有 © 2023北京嘉楠捷思信息技术有限公司。保留一切权利。** +非经本公司书面许可,任何单位和个人不得擅自摘抄、复制本文档内容的部分或全部,并不得以任何形式传播。 + +
+ +## 目录 + +[TOC] + +## 前言 + +### 概述 + +本文档为K230 nncase的使用说明文档,提供给用户如何安装nncase, 如何调用compiler APIs编译神经网络模型和runtime APIs编写AI推理程序. + +### 读者对象 + +本文档(本指南)主要适用于以下人员: + +- 技术支持工程师 +- 软件开发工程师 + +### 缩略词定义 + +| 简称 | 说明 | +| ---- | -------------------------------------- | +| PTQ | Post-training quantization, 训练后量化 | +| MSE | mean-square error, 均方误差 | + +### 修订记录 + +| 文档版本号 | 修改说明 | 修改者 | 日期 | +| ---------- | --------------------------------------------------- | ------------------ | -------- | +| V1.0 | 文档初版 | 张扬/霍成海 | 2023/4/7 | +| V1.1 | 统一改成word格式, 完善ai2d | 张扬/霍成海 | 2023/5/5 | +| V1.2 | nncase v2新架构 | 张扬/郑启航/霍成海 | 2023/6/2 | +| V1.3 | nncase_k230_v2.1.0, ai2d/runtime_tensor支持物理地址 | 张扬 | 2023/7/3 | + +## 1. 概述 + +### 1.1 什么是nncase + +nncase是一个为 AI 加速器设计的神经网络编译器, 目前支持的 target有cpu/K210/K510/K230等. + +nncase提供的功能 + +- 支持多输入多输出网络,支持多分支结构 +- 静态内存分配,不需要堆内存 +- 算子合并和优化 +- 支持 float 和uint8/int8量化推理 +- 支持训练后量化,使用浮点模型和量化校准集 +- 平坦模型,支持零拷贝加载 + +nncase支持的神经网络模型格式 + +- tflite +- onnx + +### 1.2 nncase架构 + +![nncase架构](images/185762ac17039d6c4961faa2fba0d66e.png) + +nncase软件栈包括compiler和runtime两部分。 + +Compiler: 用于在PC上编译神经网络模型,最终生成kmodel文件。主要包括importer, IR, Evaluator, Quantize, Transform优化, Tiling, Partition, Schedule, Codegen等模块。 + +- Importer: 将其它神经网络框架的模型导入到nncase中 +- IR: 中间表示, 分为importer导入的Neutral IR(设备无关)和Neutral IR经lowering转换生成的Target IR(设备相关) +- Evaluator: Evaluator提供IR的解释执行能力,常被用于Constant Folding/PTQ Calibration等场景 +- Transform: 用于IR转换和图的遍历优化等 +- Quantize: 训练后量化, 对要量化的tensor加入量化标记, 根据输入的校正集, 调用 Evaluator进行解释执行, 收集tensor的数据范围, 插入量化/反量化结点, 最后优化消除不必要的量化/反量化结点等 +- Tiling: 受限于NPU较低的存储器容量,需要将大块计算进行拆分. 另外, 计算存在大量数据复用时选择Tiling参数会对时延和带宽产生影响 +- Partition: 将图按ModuleType进行切分, 切分后的每个子图会对应RuntimeModule, 不同类型的RuntimeModule对应不同的Device(cpu/K230) +- Schedule: 根据优化后图中的数据依赖关系生成计算顺序并分配Buffer +- Codegen: 对每个子图分别调用ModuleType对应的codegen,生成RuntimeModule + +Runtime: 集成于用户App, 提供加载kmodel/设置输入数据/KPU执行/获取输出数据等功能. + +### 1.3 开发环境 + +#### 1.3.1 操作系统 + +支持的操作系统包括Ubuntu 18.04/Ubuntu 20.04 + +#### 1.3.2 软件环境 + +| 序号 | 软件 | 版本号 | +| ---- | --------------- | -------------------- | +| 1 | python | 3.6/3.7/3.8/3.9/3.10 | +| 2 | pip | \>=20.3 | +| 3 | numpy | 1.19.5 | +| 4 | onnx | 1.9.0 | +| 5 | onnx-simplifier | 0.3.6 | +| 6 | Onnxoptimizer | 0.2.6 | +| 7 | Onnxruntime | 1.8.0 | +| 8 | dotnet-runtime | 7.0 | + +#### 1.3.3 硬件环境 + +K230 evb + +## 2. 编译模型APIs(Python) + +nncase提供了Python APIs, 用于在PC上编译神经网络模型 + +### 2.1 支持的算子 + +#### 2.1.1 tflite算子 + +| Operator | Is Supported | +| ----------------------- | ------------ | +| ABS | Yes | +| ADD | Yes | +| ARG_MAX | Yes | +| ARG_MIN | Yes | +| AVERAGE_POOL_2D | Yes | +| BATCH_MATMUL | Yes | +| CAST | Yes | +| CEIL | Yes | +| CONCATENATION | Yes | +| CONV_2D | Yes | +| COS | Yes | +| CUSTOM | Yes | +| DEPTHWISE_CONV_2D | Yes | +| DIV | Yes | +| EQUAL | Yes | +| EXP | Yes | +| EXPAND_DIMS | Yes | +| FLOOR | Yes | +| FLOOR_DIV | Yes | +| FLOOR_MOD | Yes | +| FULLY_CONNECTED | Yes | +| GREATER | Yes | +| GREATER_EQUAL | Yes | +| L2_NORMALIZATION | Yes | +| LEAKY_RELU | Yes | +| LESS | Yes | +| LESS_EQUAL | Yes | +| LOG | Yes | +| LOGISTIC | Yes | +| MAX_POOL_2D | Yes | +| MAXIMUM | Yes | +| MEAN | Yes | +| MINIMUM | Yes | +| MUL | Yes | +| NEG | Yes | +| NOT_EQUAL | Yes | +| PAD | Yes | +| PADV2 | Yes | +| MIRROR_PAD | Yes | +| PACK | Yes | +| POW | Yes | +| REDUCE_MAX | Yes | +| REDUCE_MIN | Yes | +| REDUCE_PROD | Yes | +| RELU | Yes | +| PRELU | Yes | +| RELU6 | Yes | +| RESHAPE | Yes | +| RESIZE_BILINEAR | Yes | +| RESIZE_NEAREST_NEIGHBOR | Yes | +| ROUND | Yes | +| RSQRT | Yes | +| SHAPE | Yes | +| SIN | Yes | +| SLICE | Yes | +| SOFTMAX | Yes | +| SPACE_TO_BATCH_ND | Yes | +| SQUEEZE | Yes | +| BATCH_TO_SPACE_ND | Yes | +| STRIDED_SLICE | Yes | +| SQRT | Yes | +| SQUARE | Yes | +| SUB | Yes | +| SUM | Yes | +| TANH | Yes | +| TILE | Yes | +| TRANSPOSE | Yes | +| TRANSPOSE_CONV | Yes | +| QUANTIZE | Yes | +| FAKE_QUANT | Yes | +| DEQUANTIZE | Yes | +| GATHER | Yes | +| GATHER_ND | Yes | +| ONE_HOT | Yes | +| SQUARED_DIFFERENCE | Yes | +| LOG_SOFTMAX | Yes | +| SPLIT | Yes | +| HARD_SWISH | Yes | + +#### 2.1.2 onnx算子 + +| Operator | Is Supported | +| --------------------- | ------------ | +| Abs | Yes | +| Acos | Yes | +| Acosh | Yes | +| And | Yes | +| ArgMax | Yes | +| ArgMin | Yes | +| Asin | Yes | +| Asinh | Yes | +| Add | Yes | +| AveragePool | Yes | +| BatchNormalization | Yes | +| Cast | Yes | +| Ceil | Yes | +| Celu | Yes | +| Clip | Yes | +| Compress | Yes | +| Concat | Yes | +| Constant | Yes | +| ConstantOfShape | Yes | +| Conv | Yes | +| ConvTranspose | Yes | +| Cos | Yes | +| Cosh | Yes | +| CumSum | Yes | +| DepthToSpace | Yes | +| DequantizeLinear | Yes | +| Div | Yes | +| Dropout | Yes | +| Elu | Yes | +| Exp | Yes | +| Expand | Yes | +| Equal | Yes | +| Erf | Yes | +| Flatten | Yes | +| Floor | Yes | +| Gather | Yes | +| GatherElements | Yes | +| GatherND | Yes | +| Gemm | Yes | +| GlobalAveragePool | Yes | +| GlobalMaxPool | Yes | +| Greater | Yes | +| GreaterOrEqual | Yes | +| GRU | Yes | +| Hardmax | Yes | +| HardSigmoid | Yes | +| HardSwish | Yes | +| Identity | Yes | +| InstanceNormalization | Yes | +| LayerNormalization | Yes | +| LpNormalization | Yes | +| LeakyRelu | Yes | +| Less | Yes | +| LessOrEqual | Yes | +| Log | Yes | +| LogSoftmax | Yes | +| LRN | Yes | +| LSTM | Yes | +| MatMul | Yes | +| MaxPool | Yes | +| Max | Yes | +| Min | Yes | +| Mul | Yes | +| Neg | Yes | +| Not | Yes | +| OneHot | Yes | +| Pad | Yes | +| Pow | Yes | +| PRelu | Yes | +| QuantizeLinear | Yes | +| RandomNormal | Yes | +| RandomNormalLike | Yes | +| RandomUniform | Yes | +| RandomUniformLike | Yes | +| ReduceL1 | Yes | +| ReduceL2 | Yes | +| ReduceLogSum | Yes | +| ReduceLogSumExp | Yes | +| ReduceMax | Yes | +| ReduceMean | Yes | +| ReduceMin | Yes | +| ReduceProd | Yes | +| ReduceSum | Yes | +| ReduceSumSquare | Yes | +| Relu | Yes | +| Reshape | Yes | +| Resize | Yes | +| ReverseSequence | Yes | +| RoiAlign | Yes | +| Round | Yes | +| Rsqrt | Yes | +| Selu | Yes | +| Shape | Yes | +| Sign | Yes | +| Sin | Yes | +| Sinh | Yes | +| Sigmoid | Yes | +| Size | Yes | +| Slice | Yes | +| Softmax | Yes | +| Softplus | Yes | +| Softsign | Yes | +| SpaceToDepth | Yes | +| Split | Yes | +| Sqrt | Yes | +| Squeeze | Yes | +| Sub | Yes | +| Sum | Yes | +| Tanh | Yes | +| Tile | Yes | +| TopK | Yes | +| Transpose | Yes | +| Trilu | Yes | +| ThresholdedRelu | Yes | +| Upsample | Yes | +| Unsqueeze | Yes | +| Where | Yes | + +### 2.2 APIs + +目前编译模型APIs支持tflite/onnx/caffe等格式的深度学习模型。 + +#### 2.2.1 CompileOptions + +【描述】 + +CompileOptions类, 用于配置nncase编译选项 + +【定义】 + +```python +class CompileOptions: + benchmark_only: bool + dump_asm: bool + dump_dir: str + dump_ir: bool + swapRB: bool + input_range: List[float] + input_shape: List[int] + input_type: str + is_fpga: bool + mean: List[float] + std: List[float] + output_type: str + preprocess: bool + quant_type: str + target: str + w_quant_type: str + use_mse_quant_w: bool + input_layout: str + output_layout: str + letterbox_value: float + tcu_num: int + + def __init__(self) -> None: + self.benchmark_only = False + self.dump_asm = True + self.dump_dir = "tmp" + self.dump_ir = False + self.is_fpga = False + self.quant_type = "uint8" + self.target = "cpu" + self.w_quant_type = "uint8" + self.use_mse_quant_w = True + self.tcu_num = 0 + + self.preprocess = False + self.swapRB = False + self.input_range = [] + self.input_shape = [] + self.input_type = "float32" + self.mean = [0, 0, 0] + self.std = [1, 1, 1] + self.input_layout = "" + self.output_layout = "" + self.letterbox_value = 0 +``` + +【属性】 + +| 名称 | 类型 | 描述 | +| --------------- | ------ | ------------------------------------------------------------ | +| dump_asm | bool | 指定是否dump asm汇编文件, 默认为True | +| dump_dir | bool | 前面指定dump_ir等开关后, 这里指定dump的目录, 默认为"tmp" | +| dump_ir | bool | 指定是否dump IR, 默认为False | +| swapRB | bool | 是否交换RGB输入数据的红和蓝两个通道(RGB--\>BGR或者BGR--\>RGB),默认为False | +| input_range | list | 输入数据反量化后对应浮点数的范围,默认为`[0,1]` | +| input_shape | list | 指定输入数据的shape,input_shape的layout需要与input layout保持一致,输入数据的input_shape与模型的input shape不一致时会进行letterbox操作(resize/pad等) | +| input_type | string | 指定输入数据的类型, 默认为'float32' | +| mean | list | 前处理标准化参数均值,默认为`[0, 0, 0]` | +| std | list | 前处理标准化参数方差,默认为`[1, 1, 1]` | +| output_type | string | 指定输出数据的类型, 如'float32', 'uint8'(仅用于指定量化情况下) | +| preprocess | bool | 是否开启前处理,默认为False | +| target | string | 指定编译目标, 如'k210', 'k510', ‘k230’ | +| letterbox_value | float | 指定前处理letterbox的填充值 | +| input_layout | string | 指定输入数据的layout, 如'NCHW', 'NHWC'. 若输入数据layout与模型本身layout不同, nncase会插入transpose进行转换 | +| output_layout | string | 指定输出数据的layout, 如'NCHW', 'NHWC'. 若输出数据layout与模型本身layout不同, nncase会插入transpose进行转换. | + +【注意】 + +1. input range为浮点数的范围,即如果输入数据类型为uint8,则input range为反量化到浮点之后的范围(可以不为0\~1),可以自由指定. +1. input_shape需要按照input_layout进行指定,以`[1,224,224,3]`为例,如果input_layout为NCHW,则input_shape需指定为`[1,3,224,224]`;input_layout为NHWC,则input_shape需指定为`[1,224,224,3]`. +1. mean和std为浮点数进行normalize的参数,用户可以自由指定. +1. 使用letterbox功能时,需要限制输入size在1.5MB内,单channel的size在0.75MB内. + +例如: + +1. 输入数据类型设定为uint8,input_range设定为`[0,255]`,则反量化的作用只是进行类型转化,将uint8的数据转化为float32,mean和std参数仍然可以按照0\~255的数据进行指定. +1. 输入数据类型设定为uint8,input_range设定为`[0,1]`,则会将定点数反量化为范围为`[0,1]`的浮点数, mean 和std需要按照新的浮点数范围进行指定。 + +前处理流程如下(图中绿色节点皆为可选): + +![前处理流程](images/540e27e83677e9457077ad1d45bc1980.png) + +【示例】 + +实例化CompileOptions, 配置各属性的值 + +```python +# compile_options +compile_options = nncase.CompileOptions() +compile_options.target = args.target +compile_options.preprocess = True +compile_options.swapRB = False +compile_options.input_shape = input_shape +compile_options.input_type = 'uint8' +compile_options.input_range = [0, 255] +compile_options.mean = [127.5, 127.5, 127.5] +compile_options.std = [127.5, 127.5, 127.5] +compile_options.input_layout = 'NCHW' +compile_options.dump_ir = True +compile_options.dump_asm = True +compile_options.dump_dir = dump_dir +``` + +#### 2.2.2 ImportOptions + +【描述】 + +ImportOptions类, 用于配置nncase导入选项 + +【定义】 + +```python +class ImportOptions: + def __init__(self) -> None: + pass +``` + +【示例】 + +实例化ImportOptions, 配置各属性的值 + +```python +#import_options +import_options = nncase.ImportOptions() +``` + +#### 2.2.3 PTQTensorOptions + +【描述】 + +PTQTensorOptions类, 用于配置nncase PTQ选项 + +【定义】 + +```python +class PTQTensorOptions: + calibrate_method: str + input_mean: float + input_std: float + samples_count: int + quant_type: str + w_quant_type: str + finetune_weights_method: str + use_mix_quant: bool + quant_scheme: str + export_quant_scheme: bool + export_weight_range_by_channel: bool + cali_data: List[RuntimeTensor] + + def __init__(self) -> None: + self.calibrate_method: str = "Kld" + self.input_mean: float = 0.5 + self.input_std: float = 0.5 + self.samples_count: int = 5 + self.quant_type: str = "uint8" + self.w_quant_type: str = "uint8" + self.finetune_weights_method: str = "NoFineTuneWeights" + self.use_mix_quant: bool = False + self.quant_scheme: str = "" + self.export_quant_scheme: bool = False + self.export_weight_range_by_channel: bool = False + self.cali_data: List[RuntimeTensor] = [] + + def set_tensor_data(self, data: List[List[np.ndarray]]) -> None: + reshape_data = list(map(list, zip(*data))) + self.cali_data = [RuntimeTensor.from_numpy( + d) for d in itertools.chain.from_iterable(reshape_data)] +``` + +【属性】 + +| 名称 | 类型 | 描述 | +| ----------------------- | ------ | ------------------------------------------------------------ | +| calibrate_method | string | 校准方法 , 支持'NoClip', 'Kld', 默认值为'Kld' | +| input_mean | float | 用户指定输入的均值,默认值为0.5 | +| input_std | float | 用户指定输入的方差,默认值为0.5 | +| samples_count | Int | 样本个数 | +| quant_type | string | 指定数据量化类型, 如'uint8', 'int8', 默认值为'uint8' | +| w_quant_type | string | 指定权重量化类型, 如'uint8', 'int8', 默认值为’uint8’ | +| finetune_weights_method | string | 调整权重方法,有'NoFineTuneWeights', 'UseSquant',默认值为'NoFineTuneWeights' | +| use_mix_quant | bool | 是否使用混合量化,默认值为False | + +【示例】 + +```python +# ptq_options +ptq_options = nncase.PTQTensorOptions() +ptq_options.samples_count = 6 +ptq_options.set_tensor_data(generate_data(input_shape, ptq_options.samples_count, args.dataset)) +compiler.use_ptq(ptq_options) +``` + +#### 2.2.4 set_tensor_data + +【描述】 + +设置tensor数据 + +【定义】 + +```python + def set_tensor_data(self, data: List[List[np.ndarray]]) -> None: + reshape_data = list(map(list, zip(*data))) + self.cali_data = [RuntimeTensor.from_numpy( + d) for d in itertools.chain.from_iterable(reshape_data)] +``` + +【参数】 + +| 名称 | 类型 | 描述 | +| ---------- | ------ | -------------- | +| data | List[List[np.ndarray] | 读取的校准数据 | + +【返回值】 + +无 + +【示例】 + +```shell +# ptq_options +ptq_options = nncase.PTQTensorOptions() +ptq_options.samples_count = 6 +ptq_options.set_tensor_data(generate_data(input_shape, ptq_options.samples_count, args.dataset)) +compiler.use_ptq(ptq_options) +``` + +#### 2.2.5 Compiler + +【描述】 + +Compiler类, 用于编译神经网络模型 + +【定义】 + +```python +class Compiler: + _target: _nncase.Target + _session: _nncase.CompileSession + _compiler: _nncase.Compiler + _compile_options: _nncase.CompileOptions + _quantize_options: _nncase.QuantizeOptions + _module: IRModule +``` + +#### 2.2.6 import_tflite + +【描述】 + +导入tflite模型 + +【定义】 + +```python +def import_tflite(self, model_content: bytes, options: ImportOptions) -> None: + self._compile_options.input_format = "tflite" + self._import_module(model_content) +``` + +【参数】 + +| 名称 | 类型 | 描述 | +| -------------- | ------------- | -------------- | +| model_content | byte\[\] | 读取的模型内容 | +| import_options | ImportOptions | 导入选项 | + +【返回值】 + +无 + +【示例】 + +```python +model_content = read_model_file(model) +compiler.import_tflite(model_content, import_options) +``` + +#### 2.2.7 import_onnx + +【描述】 + +导入onnx模型 + +【定义】 + +```python +def import_onnx(self, model_content: bytes, options: ImportOptions) -> None: + self._compile_options.input_format = "onnx" + self._import_module(model_content) +``` + +【参数】 + +| 名称 | 类型 | 描述 | +| -------------- | ------------- | -------------- | +| model_content | byte\[\] | 读取的模型内容 | +| import_options | ImportOptions | 导入选项 | + +【返回值】 + +无 + +【示例】 + +```python +model_content = read_model_file(model) +compiler.import_onnx(model_content, import_options) +``` + +#### 2.2.8 use_ptq + +【描述】 + +设置PTQ配置选项. + +- K230默认必须使用量化。 + +【定义】 + +`use_ptq(ptq_options)` + +【参数】 + +| 名称 | 类型 | 描述 | +| ----------- | ---------------- | ----------- | +| ptq_options | PTQTensorOptions | PTQ配置选项 | + +【返回值】 + +无 + +【示例】 + +`compiler.use_ptq(ptq_options)` + +#### 2.2.9 compile + +【描述】 + +编译神经网络模型 + +【定义】 + +`compile()` + +【参数】 + +无 + +【返回值】 + +无 + +【示例】 + +`compiler.compile()` + +#### 2.2.10 gencode_tobytes + +【描述】 + +生成kmodel字节流 + +【定义】 + +`gencode_tobytes()` + +【参数】 + +无 + +【返回值】 + +`bytes[]` + +【示例】 + +```python +kmodel = compiler.gencode_tobytes() +with open(os.path.join(infer_dir, 'test.kmodel'), 'wb') as f: + f.write(kmodel) +``` + +### 2.3 示例 + +下面示例中使用到的模型和python编译脚本 + +- 原始模型文件位于/path/to/k230_sdk/src/big/nncase/examples/models目录 +- python编译脚本位于/path/to/k230_sdk/src/big/nncase/examples/scripts目录 + +#### 2.3.1 编译tflite模型 + +mbv2_tflite.py脚本如下 + +```python +import os +import argparse +import numpy as np +from PIL import Image +import nncase + +def read_model_file(model_file): + with open(model_file, 'rb') as f: + model_content = f.read() + return model_content + +def generate_data(shape, batch, calib_dir): + img_paths = [os.path.join(calib_dir, p) for p in os.listdir(calib_dir)] + data = [] + for i in range(batch): + assert i < len(img_paths), "calibration images not enough." + img_data = Image.open(img_paths[i]).convert('RGB') + img_data = img_data.resize((shape[3], shape[2]), Image.BILINEAR) + img_data = np.asarray(img_data, dtype=np.uint8) + img_data = np.transpose(img_data, (2, 0, 1)) + data.append([img_data[np.newaxis, ...]]) + return data + +def main(): + parser = argparse.ArgumentParser(prog="nncase") + parser.add_argument("--target", type=str, help='target to run') + parser.add_argument("--model", type=str, help='model file') + parser.add_argument("--dataset", type=str, help='calibration_dataset') + args = parser.parse_args() + + input_shape = [1, 3, 224, 224] + dump_dir = 'tmp/mbv2_tflite' + + # compile_options + compile_options = nncase.CompileOptions() + compile_options.target = args.target + compile_options.preprocess = True + compile_options.swapRB = False + compile_options.input_shape = input_shape + compile_options.input_type = 'uint8' + compile_options.input_range = [0, 255] + compile_options.mean = [127.5, 127.5, 127.5] + compile_options.std = [127.5, 127.5, 127.5] + compile_options.input_layout = 'NCHW' + compile_options.dump_ir = True + compile_options.dump_asm = True + compile_options.dump_dir = dump_dir + + # compiler + compiler = nncase.Compiler(compile_options) + + # import + model_content = read_model_file(args.model) + import_options = nncase.ImportOptions() + compiler.import_tflite(model_content, import_options) + + # ptq_options + ptq_options = nncase.PTQTensorOptions() + ptq_options.samples_count = 6 + ptq_options.set_tensor_data(generate_data(input_shape, ptq_options.samples_count, args.dataset)) + compiler.use_ptq(ptq_options) + + # compile + compiler.compile() + + # kmodel + kmodel = compiler.gencode_tobytes() + with open(os.path.join(dump_dir, 'test.kmodel'), 'wb') as f: + f.write(kmodel) + +if __name__ == '__main__': + main() +``` + +执行如下命令即可编译mobilenetv2的tflite模型, target为k230 + +```sh +root@c285a41a7243:/mnt/# cd src/big/nncase/examples +root@c285a41a7243:/mnt/src/big/nncase/examples# python3 ./scripts/mbv2_tflite.py --target k230 --model models/mbv2.tflite --dataset calibration_dataset +``` + +#### 2.3.2 编译onnx模型 + +针对onnx模型, 建议先使用[ONNX Simplifier](https://github.com/daquexian/onnx-simplifier)进行简化, 然后再使用nncase编译. + +yolov5s_onnx.py 脚本如下 + +```python +import os +import argparse +import numpy as np +from PIL import Image +import onnxsim +import onnx +import nncase + +def parse_model_input_output(model_file): + onnx_model = onnx.load(model_file) + input_all = [node.name for node in onnx_model.graph.input] + input_initializer = [node.name for node in onnx_model.graph.initializer] + input_names = list(set(input_all) - set(input_initializer)) + input_tensors = [ + node for node in onnx_model.graph.input if node.name in input_names] + + # input + inputs = [] + for _, e in enumerate(input_tensors): + onnx_type = e.type.tensor_type + input_dict = {} + input_dict['name'] = e.name + input_dict['dtype'] = onnx.mapping.TENSOR_TYPE_TO_NP_TYPE[onnx_type.elem_type] + input_dict['shape'] = [(i.dim_value if i.dim_value != 0 else d) for i, d in zip( + onnx_type.shape.dim, [1, 3, 224, 224])] + inputs.append(input_dict) + + return onnx_model, inputs + + +def onnx_simplify(model_file, dump_dir): + onnx_model, inputs = parse_model_input_output(model_file) + onnx_model = onnx.shape_inference.infer_shapes(onnx_model) + input_shapes = {} + for input in inputs: + input_shapes[input['name']] = input['shape'] + + onnx_model, check = onnxsim.simplify(onnx_model, input_shapes=input_shapes) + assert check, "Simplified ONNX model could not be validated" + + model_file = os.path.join(dump_dir, 'simplified.onnx') + onnx.save_model(onnx_model, model_file) + return model_file + + +def read_model_file(model_file): + with open(model_file, 'rb') as f: + model_content = f.read() + return model_content + +def generate_data_ramdom(shape, batch): + data = [] + for i in range(batch): + data.append([np.random.randint(0, 256, shape).astype(np.uint8)]) + return data + + +def generate_data(shape, batch, calib_dir): + img_paths = [os.path.join(calib_dir, p) for p in os.listdir(calib_dir)] + data = [] + for i in range(batch): + assert i < len(img_paths), "calibration images not enough." + img_data = Image.open(img_paths[i]).convert('RGB') + img_data = img_data.resize((shape[3], shape[2]), Image.BILINEAR) + img_data = np.asarray(img_data, dtype=np.uint8) + img_data = np.transpose(img_data, (2, 0, 1)) + data.append([img_data[np.newaxis, ...]]) + return data + +def main(): + parser = argparse.ArgumentParser(prog="nncase") + parser.add_argument("--target", type=str, help='target to run') + parser.add_argument("--model", type=str, help='model file') + parser.add_argument("--dataset", type=str, help='calibration_dataset') + + args = parser.parse_args() + + input_shape = [1, 3, 320, 320] + + dump_dir = 'tmp/yolov5s_onnx' + if not os.path.exists(dump_dir): + os.makedirs(dump_dir) + + # onnx simplify + model_file = onnx_simplify(args.model, dump_dir) + + # compile_options + compile_options = nncase.CompileOptions() + compile_options.target = args.target + compile_options.preprocess = True + compile_options.swapRB = False + compile_options.input_shape = input_shape + compile_options.input_type = 'uint8' + compile_options.input_range = [0, 255] + compile_options.mean = [0, 0, 0] + compile_options.std = [255, 255, 255] + compile_options.input_layout = 'NCHW' + compile_options.output_layout = 'NCHW' + compile_options.dump_ir = True + compile_options.dump_asm = True + compile_options.dump_dir = dump_dir + + # compiler + compiler = nncase.Compiler(compile_options) + + # import + model_content = read_model_file(model_file) + import_options = nncase.ImportOptions() + compiler.import_onnx(model_content, import_options) + + # ptq_options + ptq_options = nncase.PTQTensorOptions() + ptq_options.samples_count = 6 + ptq_options.set_tensor_data(generate_data(input_shape, ptq_options.samples_count, args.dataset)) + compiler.use_ptq(ptq_options) + + # compile + compiler.compile() + + # kmodel + kmodel = compiler.gencode_tobytes() + with open(os.path.join(dump_dir, 'test.kmodel'), 'wb') as f: + f.write(kmodel) + +if __name__ == '__main__': + main() +``` + +执行如下命令即可编译onnx模型, target为k230 + +```sh +root@c285a41a7243:/mnt/# cd src/big/nncase/examples +root@c285a41a7243: /mnt/src/big/nncase/examples # python3 ./scripts/yolov5s_onnx.py --target k230 --model models/yolov5s.onnx --dataset calibration_dataset +``` + +## 3. 模拟器APIs(Python) + +除了编译模型APIs, nncase还提供了推理模型的APIs, 在PC上可推理编译模型生成的kmodel, 用来验证nncase推理结果和相应深度学习框架的runtime的结果是否一致等. + +### 3.1 APIs + +#### 3.1.1 MemoryRange + +【描述】 + +MemoryRange类, 用于表示内存范围 + +【定义】 + +```python +py::class_(m, "MemoryRange") + .def_readwrite("location", &memory_range::memory_location) + .def_property( + "dtype", [](const memory_range &range) { return to_dtype(range.datatype); }, + [](memory_range &range, py::object dtype) { range.datatype = from_dtype(py::dtype::from_args(dtype)); }) + .def_readwrite("start", &memory_range::start) + .def_readwrite("size", &memory_range::size); +``` + +【属性】 + +| 名称 | 类型 | 描述 | +| -------- | -------------- | -------------------------------------------------------------------------- | +| location | int | 内存位置, 0表示input, 1表示output, 2表示rdata, 3表示data, 4表示shared_data | +| dtype | python数据类型 | 数据类型 | +| start | int | 内存起始地址 | +| Size | int | 内存大小 | + +【示例】 + +`mr = nncase.MemoryRange()` + +#### 3.1.2 RuntimeTensor + +【描述】 + +RuntimeTensor类, 用于表示运行时tensor + +【定义】 + +```python +py::class_(m, "RuntimeTensor") + .def_static("from_numpy", [](py::array arr) { + auto src_buffer = arr.request(); + auto datatype = from_dtype(arr.dtype()); + auto tensor = host_runtime_tensor::create( + datatype, + to_rt_shape(src_buffer.shape), + to_rt_strides(src_buffer.itemsize, src_buffer.strides), + gsl::make_span(reinterpret_cast(src_buffer.ptr), src_buffer.size * src_buffer.itemsize), + [=](gsl::byte *) { arr.dec_ref(); }) + .unwrap_or_throw(); + arr.inc_ref(); + return tensor; + }) + .def("copy_to", [](runtime_tensor &from, runtime_tensor &to) { + from.copy_to(to).unwrap_or_throw(); + }) + .def("to_numpy", [](runtime_tensor &tensor) { + auto host = tensor.as_host().unwrap_or_throw(); + auto src_map = std::move(hrt::map(host, hrt::map_read).unwrap_or_throw()); + auto src_buffer = src_map.buffer(); + return py::array( + to_dtype(tensor.datatype()), + tensor.shape(), + to_py_strides(runtime::get_bytes(tensor.datatype()), tensor.strides()), + src_buffer.data()); + }) + .def_property_readonly("dtype", [](runtime_tensor &tensor) { + return to_dtype(tensor.datatype()); + }) + .def_property_readonly("shape", [](runtime_tensor &tensor) { + return to_py_shape(tensor.shape()); + }); +``` + +【属性】 + +| 名称 | 类型 | 描述 | +| ----- | -------------- | ---------------- | +| dtype | python数据类型 | Tensor的数据类型 | +| shape | list | tensor的形状 | + +#### 3.1.3 from_numpy + +【描述】 + +从numpy.ndarray构造RuntimeTensor对象 + +【定义】 + +`from_numpy(py::array arr)` + +【参数】 + +| 名称 | 类型 | 描述 | +| ---- | ------------- | ----------------- | +| Arr | numpy.ndarray | numpy.ndarray对象 | + +【返回值】 + +RuntimeTensor + +【示例】 + +`tensor = nncase.RuntimeTensor.from_numpy(self.inputs[i]['data'])` + +#### 3.1.4 copy_to + +【描述】 + +拷贝RuntimeTensor + +【定义】 + +`copy_to(RuntimeTensor to)` + +【参数】 + +| 名称 | 类型 | 描述 | +| ---- | ------------- | ----------------- | +| to | RuntimeTensor | RuntimeTensor对象 | + +【返回值】 + +无 + +【示例】 + +`sim.get_output_tensor(i).copy_to(to)` + +#### 3.1.5 to_numpy + +【描述】 + +将RuntimeTensor转换为numpy.ndarray对象 + +【定义】 + +`to_numpy()` + +【参数】 + +无 + +【返回值】 + +numpy.ndarray对象 + +【示例】 + +`arr = sim.get_output_tensor(i).to_numpy()` + +#### 3.1.6 Simulator + +【描述】 + +Simulator类, 用于在PC上推理kmodel + +【定义】 + +```python +py::class_(m, "Simulator") + .def(py::init()) + .def("load_model", [](interpreter &interp, gsl::span buffer) { interp.load_model(buffer).unwrap_or_throw(); }) + .def_property_readonly("inputs_size", &interpreter::inputs_size) + .def_property_readonly("outputs_size", &interpreter::outputs_size) + .def("get_input_desc", &interpreter::input_desc) + .def("get_output_desc", &interpreter::output_desc) + .def("get_input_tensor", [](interpreter &interp, size_t index) { return interp.input_tensor(index).unwrap_or_throw(); }) + .def("set_input_tensor", [](interpreter &interp, size_t index, runtime_tensor tensor) { return interp.input_tensor(index, tensor).unwrap_or_throw(); }) + .def("get_output_tensor", [](interpreter &interp, size_t index) { return interp.output_tensor(index).unwrap_or_throw(); }) + .def("set_output_tensor", [](interpreter &interp, size_t index, runtime_tensor tensor) { return interp.output_tensor(index, tensor).unwrap_or_throw(); }) + .def("run", [](interpreter &interp) { interp.run().unwrap_or_throw(); }); +``` + +【属性】 + +| 名称 | 类型 | 描述 | +| ------------ | ---- | -------- | +| inputs_size | int | 输入个数 | +| outputs_size | int | 输出个数 | + +【示例】 + +`sim = nncase.Simulator()` + +#### 3.1.7 load_model + +【描述】 + +加载kmodel + +【定义】 + +`load_model(model_content)` + +【参数】 + +| 名称 | 类型 | 描述 | +| ------------- | ------ | ------------ | +| model_content | byte\[\] | kmodel字节流 | + +【返回值】 + +无 + +【示例】 + +`sim.load_model(kmodel)` + +#### 3.1.8 get_input_desc + +【描述】 + +获取指定索引的输入的描述信息 + +【定义】 + +`get_input_desc(index)` + +【参数】 + +| 名称 | 类型 | 描述 | +| ----- | ---- | ---------- | +| index | int | 输入的索引 | + +【返回值】 + +MemoryRange + +【示例】 + +`input_desc_0 = sim.get_input_desc(0)` + +#### 3.1.9 get_output_desc + +【描述】 + +获取指定索引的输出的描述信息 + +【定义】 + +`get_output_desc(index)` + +【参数】 + +| 名称 | 类型 | 描述 | +| ----- | ---- | ---------- | +| index | int | 输出的索引 | + +【返回值】 + +MemoryRange + +【示例】 + +`output_desc_0 = sim.get_output_desc(0)` + +#### 3.1.10 get_input_tensor + +【描述】 + +获取指定索引的输入的RuntimeTensor + +【定义】 + +`get_input_tensor(index)` + +【参数】 + +| 名称 | 类型 | 描述 | +| ----- | ---- | ---------------- | +| index | int | 输入tensor的索引 | + +【返回值】 + +RuntimeTensor + +【示例】 + +`input_tensor_0 = sim.get_input_tensor(0)` + +#### 3.1.11 set_input_tensor + +【描述】 + +设置指定索引的输入的RuntimeTensor + +【定义】 + +`set_input_tensor(index, tensor)` + +【参数】 + +| 名称 | 类型 | 描述 | +| ------ | ------------- | ---------------- | +| index | int | 输入tensor的索引 | +| tensor | RuntimeTensor | 输入tensor | + +【返回值】 + +无 + +【示例】 + +`sim.set_input_tensor(0, nncase.RuntimeTensor.from_numpy(self.inputs[0]['data']))` + +#### 3.1.12 get_output_tensor + +【描述】 + +获取指定索引的输出的RuntimeTensor + +【定义】 + +`get_output_tensor(index)` + +【参数】 + +| 名称 | 类型 | 描述 | +| ----- | ---- | ---------------- | +| index | int | 输出tensor的索引 | + +【返回值】 + +RuntimeTensor + +【示例】 + +`output_arr_0 = sim.get_output_tensor(0).to_numpy()` + +#### 3.1.13 set_output_tensor + +【描述】 + +设置指定索引的输出的RuntimeTensor + +【定义】 + +`set_output_tensor(index, tensor)` + +【参数】 + +| 名称 | 类型 | 描述 | +| ------ | ------------- | ---------------- | +| index | int | 输出tensor的索引 | +| tensor | RuntimeTensor | 输出tensor | + +【返回值】 + +无 + +【示例】 + +`sim.set_output_tensor(0, tensor)` + +#### 3.1.14 run + +【描述】 + +运行kmodel推理 + +【定义】 + +`run()` + +【参数】 + +无 + +【返回值】 + +无 + +【示例】 + +`sim.run()` + +### 3.2 示例 + +**前置条件**: yolov5s_onnx.py脚本已编译过yolov5s.onnx模型 + +yolov5s_onnx_simu.py位于/path/to/k230_sdk/src/big/nncase/examples/scripts子目录, 内容如下 + +```python +import os +import copy +import argparse +import numpy as np +import onnx +import onnxruntime as ort +import nncase + +def read_model_file(model_file): + with open(model_file, 'rb') as f: + model_content = f.read() + return model_content + +def cosine(gt, pred): + return (gt @ pred) / (np.linalg.norm(gt, 2) * np.linalg.norm(pred, 2)) + +def main(): + parser = argparse.ArgumentParser(prog="nncase") + parser.add_argument("--model", type=str, help='original model file') + parser.add_argument("--model_input", type=str, help='input bin file for original model') + parser.add_argument("--kmodel", type=str, help='kmodel file') + parser.add_argument("--kmodel_input", type=str, help='input bin file for kmodel') + args = parser.parse_args() + + # cpu inference + ort_session = ort.InferenceSession(args.model) + output_names = [] + model_outputs = ort_session.get_outputs() + for i in range(len(model_outputs)): + output_names.append(model_outputs[i].name) + model_input = ort_session.get_inputs()[0] + model_input_name = model_input.name + model_input_type = np.float32 + model_input_shape = model_input.shape + model_input_data = np.fromfile(args.model_input, model_input_type).reshape(model_input_shape) + cpu_results = [] + cpu_results = ort_session.run(output_names, { model_input_name : model_input_data }) + + # create simulator + sim = nncase.Simulator() + + # read kmodel + kmodel = read_model_file(args.kmodel) + + # load kmodel + sim.load_model(kmodel) + + # read input.bin + # input_tensor=sim.get_input_tensor(0).to_numpy() + dtype = sim.get_input_desc(0).dtype + input = np.fromfile(args.kmodel_input, dtype).reshape([1, 3, 320, 320]) + + # set input for simulator + sim.set_input_tensor(0, nncase.RuntimeTensor.from_numpy(input)) + + # simulator inference + nncase_results = [] + sim.run() + for i in range(sim.outputs_size): + nncase_result = sim.get_output_tensor(i).to_numpy() + nncase_results.append(copy.deepcopy(nncase_result)) + + # compare + for i in range(sim.outputs_size): + cos = cosine(np.reshape(nncase_results[i], (-1)), np.reshape(cpu_results[i], (-1))) + print('output {0} cosine similarity : {1}'.format(i, cos)) + +if __name__ == '__main__': + main() +``` + +执行推理脚本 + +```shell +root@5f718e19f8a7:/mnt/# cd src/big/nncase/examples +root@5f718e19f8a7:/mnt/src/big/nncase/examples # export PATH=$PATH:/usr/local/lib/python3.8/dist-packages/ +root@5f718e19f8a7:/mnt/src/big/nncase/examples # python3 scripts/yolov5s_onnx_simu.py --model models/yolov5s.onnx --model_input object_detect/data/input_fp32.bin --kmodel tmp/yolov5s_onnx/test.kmodel --kmodel_input object_detect/data/input_uint8.bin +``` + +nncase simulator和cpu推理结果对比如下 + +```sh +output 0 cosine similarity : 0.9997244477272034 +output 1 cosine similarity : 0.999757707118988 +output 2 cosine similarity : 0.9997308850288391 +``` + +## 4. KPU运行时APIs(C++) + +### 4.1 简介 + +KPU运行时APIs用于在AI设备加载kmodel,设置输入数据,执行kpu/cpu计算, 获取输出数据等. + +目前只提供C++ APIs, 相关的头文件和静态库在/path/to/k230_sdk/src/big/nncase/riscv64目录下. + +```shell +$ tree -L 3 riscv64/ +riscv64/ +├── gsl +│   └── gsl-lite.hpp +├── nncase +│   ├── include +│   │   └── nncase +│   └── lib +│   ├── cmake +│   ├── libfunctional_k230.a +│   ├── libnncase.rt_modules.k230.a +│   └── libNncase.Runtime.Native.a +└── rvvlib + ├── include + │   ├── k230_math.h + │   ├── nms.h + │   └── rvv_math.h + └── librvv.a + +8 directories, 8 files +``` + +### 4.2 APIs + +#### 4.2.1 hrt::create + +【描述】 + +创建runtime_tensor + +【定义】 + +```cpp +(1) NNCASE_API result create(typecode_t datatype, dims_t shape, memory_pool_t pool = pool_shared_first) noexcept; +(2) NNCASE_API result create(typecode_t datatype, dims_t shape, gsl::span data, bool copy, + memory_pool_t pool = pool_shared_first) noexcept; +(3)NNCASE_API resultcreate(typecode_t datatype, dims_t shape, strides_t strides, gsl::span data, bool copy, memory_pool_t pool = pool_shared_first, uintptr_t physical_address = 0) noexcept; +``` + +【参数】 + +| 名称 | 类型 | 描述 | +| ---------------- | ---------------------- | ------------------------------------- | +| datatype | typecode_t | 数据类型, 如dt_float32, dt_uint8等 | +| shape | dims_t | tensor的形状 | +| data | gsl::span\ | 用户态数据buffer | +| copy | bool | 是否拷贝 | +| pool | memory_pool_t | 内存池类型, 默认值为pool_shared_first | +| physical_address | uintptr_t | 用户指定buffer的物理地址 | + +【返回值】 + +`result` + +【示例】 + +```cpp +// create input tensor +auto input_desc = interp.input_desc(0); +auto input_shape = interp.input_shape(0); +auto input_tensor = host_runtime_tensor::create(input_desc.datatype, input_shape, hrt::pool_shared).expect("cannot create input tensor"); +``` + +#### 4.2.2 hrt::sync + +【描述】 + +同步tensor的cache。 + +- 对用户的输入数据, 需要调用 此接口的sync_write_back确保数据已刷入ddr. +- 对gnne/ai2d计算后输出数据,默认gnne/ai2d runtime已做了sync_invalidate处理。 + +【定义】 + +`NNCASE_API result sync(runtime_tensor &tensor, sync_op_t op, bool force = false) noexcept;` + +【参数】 + +| 名称 | 类型 | 描述 | +| ------ | -------------- | ------------------------------------------------------------ | +| tensor | runtime_tensor | 要操作的tensor | +| op | sync_op_t | sync_invalidate(将tensor的cache invalidate)或sync_write_back(将tensor的cache写入ddr) | +| force | bool | 是否强制执行 | + +【返回值】 + +`result` + +【示例】 + +```cpp +hrt::sync(input_tensor, sync_op_t::sync_write_back, true).expect("sync write_back failed"); +``` + +#### 4.2.3 interpreter::load_model + +【描述】 + +加载kmodel模型 + +【定义】 + +`NNCASE_NODISCARD result load_model(gsl::span buffer) noexcept;` + +【参数】 + +| 名称 | 类型 | 描述 | +| ------ | ----------------------------- | ------------- | +| buffer | gsl::span \ | kmodel buffer | + +【返回值】 + +`result` + +【示例】 + +```cpp +interpreter interp; +auto model = read_binary_file(kmodel); +interp.load_model({(const gsl::byte *)model.data(), model.size()}).expect("cannot load model."); +``` + +#### 4.2.4 interpreter::inputs_size + +【描述】 + +获取模型输入的个数 + +【定义】 + +`size_t inputs_size() const noexcept;` + +【参数】 + +无 + +【返回值】 + +`size_t` + +【示例】 + +`auto inputs_size = interp.inputs_size();` + +#### 4.2.5 interpreter::outputs_size + +【描述】 + +获取模型输出的个数 + +【定义】 + +`size_t outputs_size() const noexcept;` + +【参数】 + +无 + +【返回值】 + +`size_t` + +【示例】 + +`auto outputs_size = interp.outputs_size();` + +#### 4.2.6 interpreter:: input_shape + +【描述】 + +获取模型指定输入的形状 + +【定义】 + +`const runtime_shape_t &input_shape(size_t index) const noexcept;` + +【参数】 + +| 名称 | 类型 | 描述 | +| ----- | ------ | ---------- | +| index | size_t | 输入的索引 | + +【返回值】 + +`runtime_shape_t` + +【示例】 + +`auto shape = interp.input_shape(0);` + +#### 4.2.7 interpreter:: output_shape + +【描述】 + +获取模型指定输出的形状 + +【定义】 + +`const runtime_shape_t &output_shape(size_t index) const noexcept;` + +【参数】 + +| 名称 | 类型 | 描述 | +| ----- | ------ | ---------- | +| index | size_t | 输出的索引 | + +【返回值】 + +`runtime_shape_t` + +【示例】 + +`auto shape = interp.output_shape(0);` + +#### 4.2.8 interpreter:: input_tensor + +【描述】 + +获取/设置指定索引的输入 tensor + +【定义】 + +```cpp +(1) result input_tensor(size_t index) noexcept; +(2) result input_tensor(size_t index, runtime_tensor tensor) noexcept; +``` + +【参数】 + +| 名称 | 类型 | 描述 | +| ------ | -------------- | ------------------------ | +| index | size_t | 输入的索引 | +| tensor | runtime_tensor | 输入对应的runtime tensor | + +【返回值】 + +```cpp +(1) result +(2) result +​```cpp + +【示例】 + +​```cpp +// set input +interp.input_tensor(0, input_tensor).expect("cannot set input tensor"); +``` + +#### 4.2.9 interpreter:: output_tensor + +【描述】 + +获取/设置指定索引的输出tensor + +【定义】 + +```cpp +(1) result output_tensor(size_t index) noexcept; +(2) result output_tensor(size_t index, runtime_tensor tensor) noexcept; +``` + +【参数】 + +| 名称 | 类型 | 描述 | +| ------ | -------------- | ------------------------ | +| index | size_t | 输出的索引 | +| tensor | runtime_tensor | 输出对应的runtime tensor | + +【返回值】 + +```cpp +(1) result +(2) result +``` + +【示例】 + +```cpp +// get output +auto output_tensor = interp.output_tensor(0).expect("cannot get output tensor"); +``` + +#### 4.2.10 interpreter:: run + +【描述】 + +执行kpu计算 + +【定义】 + +`result run() noexcept;` + +【参数】 + +无 + +【返回值】 + +返回result \ + +【示例】 + +```cpp +// run +interp.run().expect("error occurred in running model"); +``` + +### 4.3 示例 + +```cpp +#include +#include +#include +#include +#include + +#define USE_OPENCV 1 +#define preprocess 1 + +#if USE_OPENCV +#include +#include +#include +#endif + +using namespace nncase; +using namespace nncase::runtime; +using namespace nncase::runtime::detail; + +#define INTPUT_HEIGHT 224 +#define INTPUT_WIDTH 224 +#define INTPUT_CHANNELS 3 + +template +std::vector read_binary_file(const std::string &file_name) +{ + std::ifstream ifs(file_name, std::ios::binary); + ifs.seekg(0, ifs.end); + size_t len = ifs.tellg(); + std::vector vec(len / sizeof(T), 0); + ifs.seekg(0, ifs.beg); + ifs.read(reinterpret_cast(vec.data()), len); + ifs.close(); + return vec; +} + +void read_binary_file(const char *file_name, char *buffer) +{ + std::ifstream ifs(file_name, std::ios::binary); + ifs.seekg(0, ifs.end); + size_t len = ifs.tellg(); + ifs.seekg(0, ifs.beg); + ifs.read(buffer, len); + ifs.close(); +} + +static std::vector read_txt_file(const char *file_name) +{ + std::vector vec; + vec.reserve(1024); + + std::ifstream fp(file_name); + std::string label; + + while (getline(fp, label)) + { + vec.push_back(label); + } + + return vec; +} + +template +static int softmax(const T* src, T* dst, int length) +{ + const T alpha = *std::max_element(src, src + length); + T denominator{ 0 }; + + for (int i = 0; i < length; ++i) { + dst[i] = std::exp(src[i] - alpha); + denominator += dst[i]; + } + + for (int i = 0; i < length; ++i) { + dst[i] /= denominator; + } + + return 0; +} + +#if USE_OPENCV +std::vector hwc2chw(cv::Mat &img) +{ + std::vector vec; + std::vector rgbChannels(3); + cv::split(img, rgbChannels); + for (auto i = 0; i < rgbChannels.size(); i++) + { + std::vector data = std::vector(rgbChannels[i].reshape(1, 1)); + vec.insert(vec.end(), data.begin(), data.end()); + } + + return vec; +} +#endif + +static int inference(const char *kmodel_file, const char *image_file, const char *label_file) +{ + // load kmodel + interpreter interp; + auto kmodel = read_binary_file(kmodel_file); + interp.load_model({ (const gsl::byte *)kmodel.data(), kmodel.size() }).expect("cannot load model."); + + // create input tensor + auto input_desc = interp.input_desc(0); + auto input_shape = interp.input_shape(0); + auto input_tensor = host_runtime_tensor::create(input_desc.datatype, input_shape, hrt::pool_shared).expect("cannot create input tensor"); + interp.input_tensor(0, input_tensor).expect("cannot set input tensor"); + + // create output tensor + // auto output_desc = interp.output_desc(0); + // auto output_shape = interp.output_shape(0); + // auto output_tensor = host_runtime_tensor::create(output_desc.datatype, output_shape, hrt::pool_shared).expect("cannot create output tensor"); + // interp.output_tensor(0, output_tensor).expect("cannot set output tensor"); + + // set input data + auto dst = input_tensor.impl()->to_host().unwrap()->buffer().as_host().unwrap().map(map_access_::map_write).unwrap().buffer(); +#if USE_OPENCV + cv::Mat img = cv::imread(image_file); + cv::resize(img, img, cv::Size(INTPUT_WIDTH, INTPUT_HEIGHT), cv::INTER_NEAREST); + auto input_vec = hwc2chw(img); + memcpy(reinterpret_cast(dst.data()), input_vec.data(), input_vec.size()); +#else + read_binary_file(image_file, reinterpret_cast(dst.data())); +#endif + hrt::sync(input_tensor, sync_op_t::sync_write_back, true).expect("sync write_back failed"); + + // run + size_t counter = 1; + auto start = std::chrono::steady_clock::now(); + for (size_t c = 0; c < counter; c++) + { + interp.run().expect("error occurred in running model"); + } + auto stop = std::chrono::steady_clock::now(); + double duration = std::chrono::duration(stop - start).count(); + std::cout << "interp.run() took: " << duration / counter << " ms" << std::endl; + + // get output data + auto output_tensor = interp.output_tensor(0).expect("cannot set output tensor"); + dst = output_tensor.impl()->to_host().unwrap()->buffer().as_host().unwrap().map(map_access_::map_read).unwrap().buffer(); + float *output_data = reinterpret_cast(dst.data()); + auto out_shape = interp.output_shape(0); + auto size = compute_size(out_shape); + + // postprogress softmax by cpu + std::vector softmax_vec(size, 0); + auto buf = softmax_vec.data(); + softmax(output_data, buf, size); + auto it = std::max_element(buf, buf + size); + size_t idx = it - buf; + + // load label + auto labels = read_txt_file(label_file); + std::cout << "image classify result: " << labels[idx] << "(" << *it << ")" << std::endl; + + return 0; +} + +int main(int argc, char *argv[]) +{ + std::cout << "case " << argv[0] << " built at " << __DATE__ << " " << __TIME__ << std::endl; + if (argc != 4) + { + std::cerr << "Usage: " << argv[0] << "