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The current implementation uses the single byte of CPU ID information in EBX from CPUID with EAX=1 to play nicely with CPUs that do not support x2APIC (such as AMDs and older Intels). However, this limits the number of processors to 256. CPUID also supports giving x2APIC IDs using EAX=0xb and reading the 4 bytes in EDX. cpu_amd64.s should use this feature if the CPU supports it.
A patch to correctly use the x2APIC CPUID instruction is given below:
diff --git a/cpu_amd64.s b/cpu_amd64.s
index b485f31..354f8f9 100644
--- a/cpu_amd64.s+++ b/cpu_amd64.s@@ -2,14 +2,12 @@
// func cpu() uint64
TEXT ·cpu(SB),NOSPLIT,$0-8
- MOVL $0x01, AX // version information+ MOVL $0x0b, AX // version information
MOVL $0x00, BX // any leaf will do
MOVL $0x00, CX // any subleaf will do
// call CPUID
BYTE $0x0f
BYTE $0xa2
-- SHRQ $24, BX // logical cpu id is put in EBX[31-24]- MOVQ BX, ret+0(FP)+ MOVQ DX, ret+0(FP) // logical cpu id is put in EDX
RET
The text was updated successfully, but these errors were encountered:
The current implementation uses the single byte of CPU ID information in
EBX
fromCPUID
withEAX=1
to play nicely with CPUs that do not support x2APIC (such as AMDs and older Intels). However, this limits the number of processors to 256.CPUID
also supports giving x2APIC IDs usingEAX=0xb
and reading the 4 bytes inEDX
.cpu_amd64.s
should use this feature if the CPU supports it.A patch to correctly use the x2APIC CPUID instruction is given below:
The text was updated successfully, but these errors were encountered: