Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

No support for >256 CPUs. #2

Open
jonhoo opened this issue May 7, 2015 · 0 comments
Open

No support for >256 CPUs. #2

jonhoo opened this issue May 7, 2015 · 0 comments

Comments

@jonhoo
Copy link
Owner

jonhoo commented May 7, 2015

The current implementation uses the single byte of CPU ID information in EBX from CPUID with EAX=1 to play nicely with CPUs that do not support x2APIC (such as AMDs and older Intels). However, this limits the number of processors to 256. CPUID also supports giving x2APIC IDs using EAX=0xb and reading the 4 bytes in EDX. cpu_amd64.s should use this feature if the CPU supports it.

A patch to correctly use the x2APIC CPUID instruction is given below:

diff --git a/cpu_amd64.s b/cpu_amd64.s
index b485f31..354f8f9 100644
--- a/cpu_amd64.s
+++ b/cpu_amd64.s
@@ -2,14 +2,12 @@

 // func cpu() uint64
 TEXT ·cpu(SB),NOSPLIT,$0-8
-       MOVL    $0x01, AX // version information
+       MOVL    $0x0b, AX // version information
        MOVL    $0x00, BX // any leaf will do
        MOVL    $0x00, CX // any subleaf will do

        // call CPUID
        BYTE $0x0f
        BYTE $0xa2
-
-       SHRQ    $24, BX // logical cpu id is put in EBX[31-24]
-       MOVQ    BX, ret+0(FP)
+       MOVQ    DX, ret+0(FP) // logical cpu id is put in EDX
        RET
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

No branches or pull requests

1 participant