Fix the behavior of non-combin memory

[hnpl]

Leaving the Pipe.io.valid signal on [1] in every cycle results in the Pipe keeps on pipelining [2] (unsurprisingly) the request from the input. Effectively, this looks like we are queue-ing the request, while the reason we use pipe is to simulate the latency.

I'm pretty sure if leaving the Pipe.io.valid affects the correctness of the simulation, but it's definitely something we don't want to simulate.

[1] https://github.com/jlpteaching/dinocpu/blob/main/src/main/scala/memory/memory-noncombin.scala#L70
[2] https://github.com/chipsalliance/chisel3/blob/v3.3.3/src/main/scala/chisel3/util/Valid.scala#L119

Desired behavior,

latency = 5
Request Pipe
t = 0 [  Req1 | Empty | Empty | Empty | Empty ]
t = 1 [ Empty |  Req1 | Empty | Empty | Empty ]
t = 2 [ Empty | Empty |  Req1 | Empty | Empty ]
t = 3 [ Empty | Empty | Empty |  Req1 | Empty ]
t = 4 [ Empty | Empty | Empty | Empty |  Req1 ]
t = 5 [  Req2 | Empty | Empty | Empty | Empty ]

Current behavior,

latency = 5
Request Pipe
t = 0 [  Req1 | Empty | Empty | Empty | Empty ]
t = 1 [  Req1 |  Req1 | Empty | Empty | Empty ]
t = 2 [  Req1 |  Req1 |  Req1 | Empty | Empty ]
t = 3 [  Req1 |  Req1 |  Req1 |  Req1 | Empty ]
t = 4 [  Req1 |  Req1 |  Req1 |  Req1 |  Req1 ]
t = 5 [  Req2 |  Req1 |  Req1 |  Req1 |  Req1 ]