From b44429b35cacbf5825bc4c298e37d5acc85b66f9 Mon Sep 17 00:00:00 2001
From: Jared Barocsi <deyahruhd@gmail.com>
Date: Fri, 26 Jul 2019 04:16:39 -0700
Subject: [PATCH] Small changes to pipelined CPUs for combin mem to work

---
 src/main/scala/pipelined/cpu-bp.scala |  9 +++++++++
 src/main/scala/pipelined/cpu.scala    | 11 +++++++++++
 2 files changed, 20 insertions(+)

diff --git a/src/main/scala/pipelined/cpu-bp.scala b/src/main/scala/pipelined/cpu-bp.scala
index 43d219af..24f835ea 100644
--- a/src/main/scala/pipelined/cpu-bp.scala
+++ b/src/main/scala/pipelined/cpu-bp.scala
@@ -152,6 +152,9 @@ class PipelinedCPUBP(implicit val conf: CPUConfig) extends BaseCPU {
     if_id.instruction := io.imem.instruction
     if_id.pc          := pc
     if_id.pcplusfour  := pcPlusFour.io.result
+    io.imem.valid := true.B
+  } .otherwise {
+    io.imem.valid := false.B
   }
 
   // Flush IF/ID when required
@@ -368,6 +371,9 @@ class PipelinedCPUBP(implicit val conf: CPUConfig) extends BaseCPU {
   io.dmem.maskmode  := ex_mem.mcontrol.maskmode
   io.dmem.sext      := ex_mem.mcontrol.sext
 
+  // Set dmem request as valid when a write or read is being requested
+  io.dmem.valid := (io.dmem.memread || io.dmem.memwrite)
+
   // Send next_pc back to the fetch stage
   mem_next_pc := ex_mem.nextpc
 
@@ -385,6 +391,9 @@ class PipelinedCPUBP(implicit val conf: CPUConfig) extends BaseCPU {
   mem_wb.readdata   := io.dmem.readdata
   mem_wb.wbcontrol  := ex_mem.wbcontrol
 
+  // Stall pipeline if neither instruction nor data memory are ready
+  val memStall = ~(io.imem.good && io.dmem.good)
+
   if (conf.debug) { printf(p"MEM/WB: $mem_wb\n") }
 
   /////////////////////////////////////////////////////////////////////////////
diff --git a/src/main/scala/pipelined/cpu.scala b/src/main/scala/pipelined/cpu.scala
index f2e06441..1f1d0d98 100644
--- a/src/main/scala/pipelined/cpu.scala
+++ b/src/main/scala/pipelined/cpu.scala
@@ -138,6 +138,10 @@ class PipelinedCPU(implicit val conf: CPUConfig) extends BaseCPU {
     if_id.instruction := io.imem.instruction
     if_id.pc          := pc
     if_id.pcplusfour  := pcPlusFour.io.result
+
+    io.imem.valid := true.B
+  } .otherwise {
+    io.imem.valid := false.B
   }
 
   // Flush IF/ID when required
@@ -312,6 +316,10 @@ class PipelinedCPU(implicit val conf: CPUConfig) extends BaseCPU {
   io.dmem.maskmode  := ex_mem.mcontrol.maskmode
   io.dmem.sext      := ex_mem.mcontrol.sext
 
+  // Set dmem request as valid when a write or read is being requested
+  io.dmem.valid := (io.dmem.memread || io.dmem.memwrite)
+
+
   // Send next_pc back to the fetch stage
   next_pc := ex_mem.nextpc
 
@@ -329,6 +337,9 @@ class PipelinedCPU(implicit val conf: CPUConfig) extends BaseCPU {
   mem_wb.readdata   := io.dmem.readdata
   mem_wb.wbcontrol  := ex_mem.wbcontrol
 
+  // Stall pipeline if neither instruction nor data memory are ready
+  val memStall = ~(io.imem.good && io.dmem.good)
+
   if (conf.debug) { printf(p"MEM/WB: $mem_wb\n") }
 
   /////////////////////////////////////////////////////////////////////////////