From 5c0ca651932764b25f482e860f3376c45294ea7f Mon Sep 17 00:00:00 2001 From: Jerome Coutant Date: Fri, 20 Aug 2021 09:31:42 +0200 Subject: [PATCH] Remove IAR patches from #14900 --- .../TOOLCHAIN_IAR/TARGET_CORTEX_A/irq_ca.S | 21 +- .../Source/TOOLCHAIN_IAR/TARGET_M0/irq_cm0.S | 57 +--- .../Source/TOOLCHAIN_IAR/TARGET_M0P/irq_cm0.S | 57 +--- .../TARGET_M23/irq_armv8mbl_common.S | 238 +++++++++------- .../Source/TOOLCHAIN_IAR/TARGET_M3/irq_cm3.S | 113 +------- .../TARGET_M33/irq_armv8mml_common.S | 256 +++++++++--------- .../TARGET_RTOS_M4_M7/irq_cm4f.S | 130 +++------ 7 files changed, 361 insertions(+), 511 deletions(-) diff --git a/cmsis/CMSIS_5/CMSIS/RTOS2/RTX/Source/TOOLCHAIN_IAR/TARGET_CORTEX_A/irq_ca.S b/cmsis/CMSIS_5/CMSIS/RTOS2/RTX/Source/TOOLCHAIN_IAR/TARGET_CORTEX_A/irq_ca.S index 9e27930a0e75..975b30dcd674 100644 --- a/cmsis/CMSIS_5/CMSIS/RTOS2/RTX/Source/TOOLCHAIN_IAR/TARGET_CORTEX_A/irq_ca.S +++ b/cmsis/CMSIS_5/CMSIS/RTOS2/RTX/Source/TOOLCHAIN_IAR/TARGET_CORTEX_A/irq_ca.S @@ -1,5 +1,5 @@ ;/* -; * Copyright (c) 2013-2021 Arm Limited. All rights reserved. +; * Copyright (c) 2013-2018 Arm Limited. All rights reserved. ; * ; * SPDX-License-Identifier: Apache-2.0 ; * @@ -18,13 +18,12 @@ ; * ----------------------------------------------------------------------------- ; * ; * Project: CMSIS-RTOS RTX -; * Title: ARMv7-A Exception handlers +; * Title: Cortex-A Exception handlers ; * ; * ----------------------------------------------------------------------------- ; */ - NAME irq_armv7a.s - + NAME irq_ca.s MODE_FIQ EQU 0x11 MODE_IRQ EQU 0x12 @@ -353,16 +352,16 @@ osRtxContextSave STMDB R1!, {R2,R12} ; Push FPSCR, maintain 8-byte alignment VSTMDB R1!, {D0-D15} ; Save D0-D15 - #ifdef __ARM_ADVANCED_SIMD__ + #ifdef __ARM_ADVANCED_SIMD__ VSTMDB R1!, {D16-D31} ; Save D16-D31 - #endif + #endif LDRB R2, [LR, #TCB_SP_FRAME] ; Load osRtxInfo.thread.run.curr frame info - #ifdef __ARM_ADVANCED_SIMD__ + #ifdef __ARM_ADVANCED_SIMD__ ORR R2, R2, #4 ; NEON state - #else + #else ORR R2, R2, #2 ; VFP state - #endif + #endif STRB R2, [LR, #TCB_SP_FRAME] ; Store VFP/NEON state osRtxContextSave1 @@ -414,9 +413,9 @@ osRtxContextRestore MCR p15, 0, R2, c1, c0, 2 ; Write CPACR BEQ osRtxContextRestore1 ; No VFP ISB ; Sync if VFP was enabled - #ifdef __ARM_ADVANCED_SIMD__ + #ifdef __ARM_ADVANCED_SIMD__ VLDMIA LR!, {D16-D31} ; Restore D16-D31 - #endif + #endif VLDMIA LR!, {D0-D15} ; Restore D0-D15 LDR R2, [LR] VMSR FPSCR, R2 ; Restore FPSCR diff --git a/cmsis/CMSIS_5/CMSIS/RTOS2/RTX/Source/TOOLCHAIN_IAR/TARGET_M0/irq_cm0.S b/cmsis/CMSIS_5/CMSIS/RTOS2/RTX/Source/TOOLCHAIN_IAR/TARGET_M0/irq_cm0.S index 29b8bb027436..3ca51f670125 100644 --- a/cmsis/CMSIS_5/CMSIS/RTOS2/RTX/Source/TOOLCHAIN_IAR/TARGET_M0/irq_cm0.S +++ b/cmsis/CMSIS_5/CMSIS/RTOS2/RTX/Source/TOOLCHAIN_IAR/TARGET_M0/irq_cm0.S @@ -1,5 +1,5 @@ ;/* -; * Copyright (c) 2013-2021 Arm Limited. All rights reserved. +; * Copyright (c) 2013-2018 Arm Limited. All rights reserved. ; * ; * SPDX-License-Identifier: Apache-2.0 ; * @@ -18,23 +18,18 @@ ; * ----------------------------------------------------------------------------- ; * ; * Project: CMSIS-RTOS RTX -; * Title: ARMv6-M Exception handlers +; * Title: Cortex-M0 Exception handlers ; * ; * ----------------------------------------------------------------------------- ; */ - NAME irq_armv6m.s + NAME irq_cm0.s - #include "rtx_def.h" - I_T_RUN_OFS EQU 20 ; osRtxInfo.thread.run offset TCB_SP_OFS EQU 56 ; TCB.SP offset -osRtxErrorStackOverflow\ - EQU 1 ; Stack overflow - PRESERVE8 SECTION .rodata:DATA:NOROOT(2) @@ -52,10 +47,6 @@ SVC_Handler EXPORT SVC_Handler IMPORT osRtxUserSVC IMPORT osRtxInfo - #ifdef RTX_STACK_CHECK - IMPORT osRtxThreadStackCheck - IMPORT osRtxKernelErrorNotify - #endif MOV R0,LR LSRS R0,R0,#3 ; Determine return stack from EXC_RETURN bit 2 @@ -66,7 +57,7 @@ SVC_Number LDR R1,[R0,#24] ; Load saved PC from stack SUBS R1,R1,#2 ; Point to SVC instruction LDRB R1,[R1] ; Load SVC number - CMP R1,#0 ; Check SVC number + CMP R1,#0 BNE SVC_User ; Branch if not SVC 0 PUSH {R0,LR} ; Save SP and EXC_RETURN @@ -77,42 +68,18 @@ SVC_Number MOV LR,R3 ; Set EXC_RETURN SVC_Context - LDR R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.thread.run + LDR R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run LDMIA R3!,{R1,R2} ; Load osRtxInfo.thread.run: curr & next CMP R1,R2 ; Check if thread switch is required BEQ SVC_Exit ; Branch when threads are the same - SUBS R3,R3,#8 ; Adjust address - STR R2,[R3] ; osRtxInfo.thread.run: curr = next CMP R1,#0 - BEQ SVC_ContextRestore ; Branch if running thread is deleted + BEQ SVC_ContextSwitch ; Branch if running thread is deleted SVC_ContextSave MRS R0,PSP ; Get PSP - SUBS R0,R0,#32 ; Calculate SP: space for R4..R11 + SUBS R0,R0,#32 ; Calculate SP STR R0,[R1,#TCB_SP_OFS] ; Store SP - - #ifdef RTX_STACK_CHECK - - PUSH {R1,R2} ; Save osRtxInfo.thread.run: curr & next - MOV R0,R1 ; Parameter: osRtxInfo.thread.run.curr - BL osRtxThreadStackCheck ; Check if thread stack is overrun - POP {R1,R2} ; Restore osRtxInfo.thread.run: curr & next - CMP R0,#0 - BNE SVC_ContextSaveRegs ; Branch when stack check is ok - - MOVS R0,#osRtxErrorStackOverflow ; Parameter: r0=code, r1=object_id - BL osRtxKernelErrorNotify ; Call osRtxKernelErrorNotify - LDR R3,=osRtxInfo+I_T_RUN_OFS ; Load address of osRtxInfo.thread.run - LDR R2,[R3,#4] ; Load osRtxInfo.thread.run: next - STR R2,[R3] ; osRtxInfo.thread.run: curr = next - B SVC_ContextRestore ; Branch to context restore handling - -SVC_ContextSaveRegs - LDR R0,[R1,#TCB_SP_OFS] ; Load SP - - #endif - STMIA R0!,{R4-R7} ; Save R4..R7 MOV R4,R8 MOV R5,R9 @@ -120,6 +87,10 @@ SVC_ContextSaveRegs MOV R7,R11 STMIA R0!,{R4-R7} ; Save R8..R11 +SVC_ContextSwitch + SUBS R3,R3,#8 ; Adjust address + STR R2,[R3] ; osRtxInfo.thread.run: curr = next + SVC_ContextRestore LDR R0,[R2,#TCB_SP_OFS] ; Load SP ADDS R0,R0,#16 ; Adjust address @@ -132,7 +103,7 @@ SVC_ContextRestore SUBS R0,R0,#32 ; Adjust address LDMIA R0!,{R4-R7} ; Restore R4..R7 - MOVS R0,#2 ; Binary complement of 0xFFFFFFFD + MOVS R0,#~0xFFFFFFFD MVNS R0,R0 ; Set EXC_RETURN value BX R0 ; Exit from handler @@ -170,7 +141,7 @@ PendSV_Handler BL osRtxPendSV_Handler ; Call osRtxPendSV_Handler POP {R0,R1} ; Restore EXC_RETURN MOV LR,R1 ; Set EXC_RETURN - B SVC_Context ; Branch to context handling + B SVC_Context SysTick_Handler @@ -181,7 +152,7 @@ SysTick_Handler BL osRtxTick_Handler ; Call osRtxTick_Handler POP {R0,R1} ; Restore EXC_RETURN MOV LR,R1 ; Set EXC_RETURN - B SVC_Context ; Branch to context handling + B SVC_Context END diff --git a/cmsis/CMSIS_5/CMSIS/RTOS2/RTX/Source/TOOLCHAIN_IAR/TARGET_M0P/irq_cm0.S b/cmsis/CMSIS_5/CMSIS/RTOS2/RTX/Source/TOOLCHAIN_IAR/TARGET_M0P/irq_cm0.S index 29b8bb027436..3ca51f670125 100644 --- a/cmsis/CMSIS_5/CMSIS/RTOS2/RTX/Source/TOOLCHAIN_IAR/TARGET_M0P/irq_cm0.S +++ b/cmsis/CMSIS_5/CMSIS/RTOS2/RTX/Source/TOOLCHAIN_IAR/TARGET_M0P/irq_cm0.S @@ -1,5 +1,5 @@ ;/* -; * Copyright (c) 2013-2021 Arm Limited. All rights reserved. +; * Copyright (c) 2013-2018 Arm Limited. All rights reserved. ; * ; * SPDX-License-Identifier: Apache-2.0 ; * @@ -18,23 +18,18 @@ ; * ----------------------------------------------------------------------------- ; * ; * Project: CMSIS-RTOS RTX -; * Title: ARMv6-M Exception handlers +; * Title: Cortex-M0 Exception handlers ; * ; * ----------------------------------------------------------------------------- ; */ - NAME irq_armv6m.s + NAME irq_cm0.s - #include "rtx_def.h" - I_T_RUN_OFS EQU 20 ; osRtxInfo.thread.run offset TCB_SP_OFS EQU 56 ; TCB.SP offset -osRtxErrorStackOverflow\ - EQU 1 ; Stack overflow - PRESERVE8 SECTION .rodata:DATA:NOROOT(2) @@ -52,10 +47,6 @@ SVC_Handler EXPORT SVC_Handler IMPORT osRtxUserSVC IMPORT osRtxInfo - #ifdef RTX_STACK_CHECK - IMPORT osRtxThreadStackCheck - IMPORT osRtxKernelErrorNotify - #endif MOV R0,LR LSRS R0,R0,#3 ; Determine return stack from EXC_RETURN bit 2 @@ -66,7 +57,7 @@ SVC_Number LDR R1,[R0,#24] ; Load saved PC from stack SUBS R1,R1,#2 ; Point to SVC instruction LDRB R1,[R1] ; Load SVC number - CMP R1,#0 ; Check SVC number + CMP R1,#0 BNE SVC_User ; Branch if not SVC 0 PUSH {R0,LR} ; Save SP and EXC_RETURN @@ -77,42 +68,18 @@ SVC_Number MOV LR,R3 ; Set EXC_RETURN SVC_Context - LDR R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.thread.run + LDR R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run LDMIA R3!,{R1,R2} ; Load osRtxInfo.thread.run: curr & next CMP R1,R2 ; Check if thread switch is required BEQ SVC_Exit ; Branch when threads are the same - SUBS R3,R3,#8 ; Adjust address - STR R2,[R3] ; osRtxInfo.thread.run: curr = next CMP R1,#0 - BEQ SVC_ContextRestore ; Branch if running thread is deleted + BEQ SVC_ContextSwitch ; Branch if running thread is deleted SVC_ContextSave MRS R0,PSP ; Get PSP - SUBS R0,R0,#32 ; Calculate SP: space for R4..R11 + SUBS R0,R0,#32 ; Calculate SP STR R0,[R1,#TCB_SP_OFS] ; Store SP - - #ifdef RTX_STACK_CHECK - - PUSH {R1,R2} ; Save osRtxInfo.thread.run: curr & next - MOV R0,R1 ; Parameter: osRtxInfo.thread.run.curr - BL osRtxThreadStackCheck ; Check if thread stack is overrun - POP {R1,R2} ; Restore osRtxInfo.thread.run: curr & next - CMP R0,#0 - BNE SVC_ContextSaveRegs ; Branch when stack check is ok - - MOVS R0,#osRtxErrorStackOverflow ; Parameter: r0=code, r1=object_id - BL osRtxKernelErrorNotify ; Call osRtxKernelErrorNotify - LDR R3,=osRtxInfo+I_T_RUN_OFS ; Load address of osRtxInfo.thread.run - LDR R2,[R3,#4] ; Load osRtxInfo.thread.run: next - STR R2,[R3] ; osRtxInfo.thread.run: curr = next - B SVC_ContextRestore ; Branch to context restore handling - -SVC_ContextSaveRegs - LDR R0,[R1,#TCB_SP_OFS] ; Load SP - - #endif - STMIA R0!,{R4-R7} ; Save R4..R7 MOV R4,R8 MOV R5,R9 @@ -120,6 +87,10 @@ SVC_ContextSaveRegs MOV R7,R11 STMIA R0!,{R4-R7} ; Save R8..R11 +SVC_ContextSwitch + SUBS R3,R3,#8 ; Adjust address + STR R2,[R3] ; osRtxInfo.thread.run: curr = next + SVC_ContextRestore LDR R0,[R2,#TCB_SP_OFS] ; Load SP ADDS R0,R0,#16 ; Adjust address @@ -132,7 +103,7 @@ SVC_ContextRestore SUBS R0,R0,#32 ; Adjust address LDMIA R0!,{R4-R7} ; Restore R4..R7 - MOVS R0,#2 ; Binary complement of 0xFFFFFFFD + MOVS R0,#~0xFFFFFFFD MVNS R0,R0 ; Set EXC_RETURN value BX R0 ; Exit from handler @@ -170,7 +141,7 @@ PendSV_Handler BL osRtxPendSV_Handler ; Call osRtxPendSV_Handler POP {R0,R1} ; Restore EXC_RETURN MOV LR,R1 ; Set EXC_RETURN - B SVC_Context ; Branch to context handling + B SVC_Context SysTick_Handler @@ -181,7 +152,7 @@ SysTick_Handler BL osRtxTick_Handler ; Call osRtxTick_Handler POP {R0,R1} ; Restore EXC_RETURN MOV LR,R1 ; Set EXC_RETURN - B SVC_Context ; Branch to context handling + B SVC_Context END diff --git a/cmsis/CMSIS_5/CMSIS/RTOS2/RTX/Source/TOOLCHAIN_IAR/TARGET_M23/irq_armv8mbl_common.S b/cmsis/CMSIS_5/CMSIS/RTOS2/RTX/Source/TOOLCHAIN_IAR/TARGET_M23/irq_armv8mbl_common.S index 9f0bf8effa04..a0e6918fb7f5 100644 --- a/cmsis/CMSIS_5/CMSIS/RTOS2/RTX/Source/TOOLCHAIN_IAR/TARGET_M23/irq_armv8mbl_common.S +++ b/cmsis/CMSIS_5/CMSIS/RTOS2/RTX/Source/TOOLCHAIN_IAR/TARGET_M23/irq_armv8mbl_common.S @@ -1,5 +1,5 @@ ;/* -; * Copyright (c) 2016-2021 Arm Limited. All rights reserved. +; * Copyright (c) 2016-2020 Arm Limited. All rights reserved. ; * ; * SPDX-License-Identifier: Apache-2.0 ; * @@ -18,17 +18,12 @@ ; * ----------------------------------------------------------------------------- ; * ; * Project: CMSIS-RTOS RTX -; * Title: ARMv8-M Baseline Exception handlers +; * Title: ARMv8M Baseline Exception handlers ; * ; * ----------------------------------------------------------------------------- ; */ - NAME irq_armv8mbl.s - - - #include "rtx_def.h" - #ifndef DOMAIN_NS #define DOMAIN_NS 0 #endif @@ -39,9 +34,6 @@ TCB_SP_OFS EQU 56 ; TCB.SP offset TCB_SF_OFS EQU 34 ; TCB.stack_frame offset TCB_TZM_OFS EQU 64 ; TCB.tz_memory offset -osRtxErrorStackOverflow\ - EQU 1 ; Stack overflow - PRESERVE8 @@ -59,14 +51,10 @@ SVC_Handler EXPORT SVC_Handler IMPORT osRtxUserSVC IMPORT osRtxInfo - #ifdef RTX_STACK_CHECK - IMPORT osRtxThreadStackCheck - IMPORT osRtxKernelErrorNotify - #endif - #if (DOMAIN_NS != 0) + #if (DOMAIN_NS == 1) IMPORT TZ_LoadContext_S IMPORT TZ_StoreContext_S - #endif + #endif MOV R0,LR LSRS R0,R0,#3 ; Determine return stack from EXC_RETURN bit 2 @@ -77,136 +65,95 @@ SVC_Number LDR R1,[R0,#24] ; Load saved PC from stack SUBS R1,R1,#2 ; Point to SVC instruction LDRB R1,[R1] ; Load SVC number - CMP R1,#0 ; Check SVC number + CMP R1,#0 BNE SVC_User ; Branch if not SVC 0 PUSH {R0,LR} ; Save SP and EXC_RETURN - LDMIA R0,{R0-R3} ; Load function parameters from stack + LDM R0,{R0-R3} ; Load function parameters from stack BLX R7 ; Call service function POP {R2,R3} ; Restore SP and EXC_RETURN STMIA R2!,{R0-R1} ; Store function return values MOV LR,R3 ; Set EXC_RETURN SVC_Context - LDR R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.thread.run + LDR R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run LDMIA R3!,{R1,R2} ; Load osRtxInfo.thread.run: curr & next CMP R1,R2 ; Check if thread switch is required BEQ SVC_Exit ; Branch when threads are the same - SUBS R3,R3,#8 ; Adjust address - STR R2,[R3] ; osRtxInfo.thread.run: curr = next - CBZ R1,SVC_ContextRestore ; Branch if running thread is deleted + CBZ R1,SVC_ContextSwitch ; Branch if running thread is deleted SVC_ContextSave - #if (DOMAIN_NS != 0) + #if (DOMAIN_NS == 1) LDR R0,[R1,#TCB_TZM_OFS] ; Load TrustZone memory identifier - CBZ R0,SVC_ContextSave_NS ; Branch if there is no secure context + CBZ R0,SVC_ContextSave1 ; Branch if there is no secure context PUSH {R1,R2,R3,R7} ; Save registers MOV R7,LR ; Get EXC_RETURN BL TZ_StoreContext_S ; Store secure context MOV LR,R7 ; Set EXC_RETURN POP {R1,R2,R3,R7} ; Restore registers - #endif + #endif -SVC_ContextSave_NS +SVC_ContextSave1 MRS R0,PSP ; Get PSP - #if (DOMAIN_NS != 0) - MOV R3,LR ; Get EXC_RETURN - LSLS R3,R3,#25 ; Check domain of interrupted thread - BMI SVC_ContextSaveSP ; Branch if secure - #endif - - #ifdef RTX_STACK_CHECK - SUBS R0,R0,#32 ; Calculate SP: space for R4..R11 - -SVC_ContextSaveSP + SUBS R0,R0,#32 ; Calculate SP STR R0,[R1,#TCB_SP_OFS] ; Store SP - MOV R3,LR ; Get EXC_RETURN - MOV R0,R1 ; osRtxInfo.thread.run.curr - ADDS R0,R0,#TCB_SF_OFS ; Adjust address - STRB R3,[R0] ; Store stack frame information - - PUSH {R1,R2} ; Save osRtxInfo.thread.run: curr & next - MOV R0,R1 ; Parameter: osRtxInfo.thread.run.curr - BL osRtxThreadStackCheck ; Check if thread stack is overrun - POP {R1,R2} ; Restore osRtxInfo.thread.run: curr & next - CMP R0,#0 - BNE SVC_ContextSaveRegs ; Branch when stack check is ok - - MOVS R0,#osRtxErrorStackOverflow ; Parameter: r0=code, r1=object_id - BL osRtxKernelErrorNotify ; Call osRtxKernelErrorNotify - LDR R3,=osRtxInfo+I_T_RUN_OFS ; Load address of osRtxInfo.thread.run - LDR R2,[R3,#4] ; Load osRtxInfo.thread.run: next - STR R2,[R3] ; osRtxInfo.thread.run: curr = next - B SVC_ContextRestore ; Branch to context restore handling - -SVC_ContextSaveRegs - #if (DOMAIN_NS != 0) - MOV R0,R1 ; osRtxInfo.thread.run.curr - ADDS R0,R0,#TCB_SF_OFS ; Adjust address - LDRB R3,[R0] ; Load stack frame information - LSLS R3,R3,#25 ; Check domain of interrupted thread - BMI SVC_ContextRestore ; Branch if secure - #endif - LDR R0,[R1,#TCB_SP_OFS] ; Load SP STMIA R0!,{R4-R7} ; Save R4..R7 MOV R4,R8 MOV R5,R9 MOV R6,R10 MOV R7,R11 STMIA R0!,{R4-R7} ; Save R8..R11 - #else - SUBS R0,R0,#32 ; Calculate SP: space for R4..R11 - STMIA R0!,{R4-R7} ; Save R4..R7 - MOV R4,R8 - MOV R5,R9 - MOV R6,R10 - MOV R7,R11 - STMIA R0!,{R4-R7} ; Save R8..R11 - SUBS R0,R0,#32 ; Adjust address -SVC_ContextSaveSP - STR R0,[R1,#TCB_SP_OFS] ; Store SP + +SVC_ContextSave2 MOV R0,LR ; Get EXC_RETURN ADDS R1,R1,#TCB_SF_OFS ; Adjust address STRB R0,[R1] ; Store stack frame information - #endif + +SVC_ContextSwitch + SUBS R3,R3,#8 ; Adjust address + STR R2,[R3] ; osRtxInfo.thread.run: curr = next SVC_ContextRestore - #if (DOMAIN_NS != 0) + #if (DOMAIN_NS == 1) LDR R0,[R2,#TCB_TZM_OFS] ; Load TrustZone memory identifier - CBZ R0,SVC_ContextRestore_NS ; Branch if there is no secure context + CBZ R0,SVC_ContextRestore1 ; Branch if there is no secure context PUSH {R2,R3} ; Save registers BL TZ_LoadContext_S ; Load secure context POP {R2,R3} ; Restore registers - #endif + #endif -SVC_ContextRestore_NS +SVC_ContextRestore1 + MOV R1,R2 + ADDS R1,R1,#TCB_SF_OFS ; Adjust address + LDRB R0,[R1] ; Load stack frame information + MOVS R1,#0xFF + MVNS R1,R1 ; R1=0xFFFFFF00 + ORRS R0,R1 + MOV LR,R0 ; Set EXC_RETURN + + #if (DOMAIN_NS == 1) + LSLS R0,R0,#25 ; Check domain of interrupted thread + BPL SVC_ContextRestore2 ; Branch if non-secure + LDR R0,[R2,#TCB_SP_OFS] ; Load SP + MSR PSP,R0 ; Set PSP + BX LR ; Exit from handler + #else LDR R0,[R2,#TCB_SM_OFS] ; Load stack memory base MSR PSPLIM,R0 ; Set PSPLIM - MOV R0,R2 ; osRtxInfo.thread.run.next - ADDS R0,R0,#TCB_SF_OFS ; Adjust address - LDRB R3,[R0] ; Load stack frame information - MOVS R0,#0xFF - MVNS R0,R0 ; R0=0xFFFFFF00 - ORRS R3,R3,R0 - MOV LR,R3 ; Set EXC_RETURN + #endif + +SVC_ContextRestore2 LDR R0,[R2,#TCB_SP_OFS] ; Load SP - #if (DOMAIN_NS != 0) - LSLS R3,R3,#25 ; Check domain of interrupted thread - BMI SVC_ContextRestoreSP ; Branch if secure - #endif ADDS R0,R0,#16 ; Adjust address LDMIA R0!,{R4-R7} ; Restore R8..R11 MOV R8,R4 MOV R9,R5 MOV R10,R6 MOV R11,R7 + MSR PSP,R0 ; Set PSP SUBS R0,R0,#32 ; Adjust address LDMIA R0!,{R4-R7} ; Restore R4..R7 - ADDS R0,R0,#16 ; Adjust address - -SVC_ContextRestoreSP - MSR PSP,R0 ; Set PSP SVC_Exit BX LR ; Exit from handler @@ -242,7 +189,7 @@ PendSV_Handler BL osRtxPendSV_Handler ; Call osRtxPendSV_Handler POP {R0,R1} ; Restore EXC_RETURN MOV LR,R1 ; Set EXC_RETURN - B SVC_Context ; Branch to context handling + B Sys_Context SysTick_Handler @@ -253,7 +200,104 @@ SysTick_Handler BL osRtxTick_Handler ; Call osRtxTick_Handler POP {R0,R1} ; Restore EXC_RETURN MOV LR,R1 ; Set EXC_RETURN - B SVC_Context ; Branch to context handling + B Sys_Context + + +Sys_Context + EXPORT Sys_Context + IMPORT osRtxInfo + #if (DOMAIN_NS == 1) + IMPORT TZ_LoadContext_S + IMPORT TZ_StoreContext_S + #endif + + LDR R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run + LDM R3!,{R1,R2} ; Load osRtxInfo.thread.run: curr & next + CMP R1,R2 ; Check if thread switch is required + BEQ Sys_ContextExit ; Branch when threads are the same + +Sys_ContextSave + #if (DOMAIN_NS == 1) + LDR R0,[R1,#TCB_TZM_OFS] ; Load TrustZone memory identifier + CBZ R0,Sys_ContextSave1 ; Branch if there is no secure context + PUSH {R1,R2,R3,R7} ; Save registers + MOV R7,LR ; Get EXC_RETURN + BL TZ_StoreContext_S ; Store secure context + MOV LR,R7 ; Set EXC_RETURN + POP {R1,R2,R3,R7} ; Restore registers + +Sys_ContextSave1 + MOV R0,LR ; Get EXC_RETURN + LSLS R0,R0,#25 ; Check domain of interrupted thread + BPL Sys_ContextSave2 ; Branch if non-secure + MRS R0,PSP ; Get PSP + STR R0,[R1,#TCB_SP_OFS] ; Store SP + B Sys_ContextSave3 + #endif + +Sys_ContextSave2 + MRS R0,PSP ; Get PSP + SUBS R0,R0,#32 ; Adjust address + STR R0,[R1,#TCB_SP_OFS] ; Store SP + STMIA R0!,{R4-R7} ; Save R4..R7 + MOV R4,R8 + MOV R5,R9 + MOV R6,R10 + MOV R7,R11 + STMIA R0!,{R4-R7} ; Save R8..R11 + +Sys_ContextSave3 + MOV R0,LR ; Get EXC_RETURN + ADDS R1,R1,#TCB_SF_OFS ; Adjust address + STRB R0,[R1] ; Store stack frame information + +Sys_ContextSwitch + SUBS R3,R3,#8 ; Adjust address + STR R2,[R3] ; osRtxInfo.run: curr = next + +Sys_ContextRestore + #if (DOMAIN_NS == 1) + LDR R0,[R2,#TCB_TZM_OFS] ; Load TrustZone memory identifier + CBZ R0,Sys_ContextRestore1 ; Branch if there is no secure context + PUSH {R2,R3} ; Save registers + BL TZ_LoadContext_S ; Load secure context + POP {R2,R3} ; Restore registers + #endif + +Sys_ContextRestore1 + MOV R1,R2 + ADDS R1,R1,#TCB_SF_OFS ; Adjust offset + LDRB R0,[R1] ; Load stack frame information + MOVS R1,#0xFF + MVNS R1,R1 ; R1=0xFFFFFF00 + ORRS R0,R1 + MOV LR,R0 ; Set EXC_RETURN + + #if (DOMAIN_NS == 1) + LSLS R0,R0,#25 ; Check domain of interrupted thread + BPL Sys_ContextRestore2 ; Branch if non-secure + LDR R0,[R2,#TCB_SP_OFS] ; Load SP + MSR PSP,R0 ; Set PSP + BX LR ; Exit from handler + #else + LDR R0,[R2,#TCB_SM_OFS] ; Load stack memory base + MSR PSPLIM,R0 ; Set PSPLIM + #endif + +Sys_ContextRestore2 + LDR R0,[R2,#TCB_SP_OFS] ; Load SP + ADDS R0,R0,#16 ; Adjust address + LDMIA R0!,{R4-R7} ; Restore R8..R11 + MOV R8,R4 + MOV R9,R5 + MOV R10,R6 + MOV R11,R7 + MSR PSP,R0 ; Set PSP + SUBS R0,R0,#32 ; Adjust address + LDMIA R0!,{R4-R7} ; Restore R4..R7 + +Sys_ContextExit + BX LR ; Exit from handler END diff --git a/cmsis/CMSIS_5/CMSIS/RTOS2/RTX/Source/TOOLCHAIN_IAR/TARGET_M3/irq_cm3.S b/cmsis/CMSIS_5/CMSIS/RTOS2/RTX/Source/TOOLCHAIN_IAR/TARGET_M3/irq_cm3.S index 3b6f9cf1d337..29fe1b727e6e 100644 --- a/cmsis/CMSIS_5/CMSIS/RTOS2/RTX/Source/TOOLCHAIN_IAR/TARGET_M3/irq_cm3.S +++ b/cmsis/CMSIS_5/CMSIS/RTOS2/RTX/Source/TOOLCHAIN_IAR/TARGET_M3/irq_cm3.S @@ -1,5 +1,5 @@ ;/* -; * Copyright (c) 2013-2021 Arm Limited. All rights reserved. +; * Copyright (c) 2013-2018 Arm Limited. All rights reserved. ; * ; * SPDX-License-Identifier: Apache-2.0 ; * @@ -18,31 +18,17 @@ ; * ----------------------------------------------------------------------------- ; * ; * Project: CMSIS-RTOS RTX -; * Title: ARMv7-M Exception handlers +; * Title: Cortex-M3 Exception handlers ; * ; * ----------------------------------------------------------------------------- ; */ - NAME irq_armv7m.s + NAME irq_cm3.s - #include "rtx_def.h" - -#ifdef __ARMVFP__ -FPU_USED EQU 1 -#else -FPU_USED EQU 0 -#endif - I_T_RUN_OFS EQU 20 ; osRtxInfo.thread.run offset TCB_SP_OFS EQU 56 ; TCB.SP offset -TCB_SF_OFS EQU 34 ; TCB.stack_frame offset - -FPCCR EQU 0xE000EF34 ; FPCCR Address - -osRtxErrorStackOverflow\ - EQU 1 ; Stack overflow PRESERVE8 @@ -61,10 +47,6 @@ SVC_Handler EXPORT SVC_Handler IMPORT osRtxUserSVC IMPORT osRtxInfo - #ifdef RTX_STACK_CHECK - IMPORT osRtxThreadStackCheck - IMPORT osRtxKernelErrorNotify - #endif TST LR,#0x04 ; Determine return stack from EXC_RETURN bit 2 ITE EQ @@ -73,8 +55,7 @@ SVC_Handler LDR R1,[R0,#24] ; Load saved PC from stack LDRB R1,[R1,#-2] ; Load SVC number - CMP R1,#0 ; Check SVC number - BNE SVC_User ; Branch if not SVC 0 + CBNZ R1,SVC_User ; Branch if not SVC 0 PUSH {R0,LR} ; Save SP and EXC_RETURN LDM R0,{R0-R3,R12} ; Load function parameters and address from stack @@ -83,94 +64,28 @@ SVC_Handler STM R12,{R0-R1} ; Store function return values SVC_Context - LDR R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.thread.run + LDR R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run LDM R3,{R1,R2} ; Load osRtxInfo.thread.run: curr & next CMP R1,R2 ; Check if thread switch is required IT EQ BXEQ LR ; Exit when threads are the same - STR R2,[R3] ; osRtxInfo.thread.run: curr = next - - #if (FPU_USED != 0) - CBNZ R1,SVC_ContextSave ; Branch if running thread is not deleted -SVC_FP_LazyState - TST LR,#0x10 ; Determine stack frame from EXC_RETURN bit 4 - BNE SVC_ContextRestore ; Branch if not extended stack frame - LDR R3,=FPCCR ; FPCCR Address - LDR R0,[R3] ; Load FPCCR - BIC R0,R0,#1 ; Clear LSPACT (Lazy state preservation) - STR R0,[R3] ; Store FPCCR - B SVC_ContextRestore ; Branch to context restore handling - #else - CBZ R1,SVC_ContextRestore ; Branch if running thread is deleted - #endif + CBZ R1,SVC_ContextSwitch ; Branch if running thread is deleted SVC_ContextSave - #ifdef RTX_STACK_CHECK - SUB R12,R12,#32 ; Calculate SP: space for R4..R11 - #if (FPU_USED != 0) - TST LR,#0x10 ; Determine stack frame from EXC_RETURN bit 4 - IT EQ ; If extended stack frame - SUBEQ R12,R12,#64 ; Additional space for S16..S31 - STRB LR, [R1,#TCB_SF_OFS] ; Store stack frame information - #endif + STMDB R12!,{R4-R11} ; Save R4..R11 STR R12,[R1,#TCB_SP_OFS] ; Store SP - PUSH {R1,R2} ; Save osRtxInfo.thread.run: curr & next - MOV R0,R1 ; Parameter: osRtxInfo.thread.run.curr - BL osRtxThreadStackCheck ; Check if thread stack is overrun - POP {R1,R2} ; Restore osRtxInfo.thread.run: curr & next - CBNZ R0,SVC_ContextSaveRegs ; Branch when stack check is ok - - #if (FPU_USED != 0) - MOV R4,R1 ; Save osRtxInfo.thread.run.curr - #endif - MOV R0,#osRtxErrorStackOverflow ; Parameter: r0=code, r1=object_id - BL osRtxKernelErrorNotify ; Call osRtxKernelErrorNotify - LDR R3,=osRtxInfo+I_T_RUN_OFS ; Load address of osRtxInfo.thread.run - LDR R2,[R3,#4] ; Load osRtxInfo.thread.run: next +SVC_ContextSwitch STR R2,[R3] ; osRtxInfo.thread.run: curr = next - #if (FPU_USED != 0) - LDRB LR,[R4,#TCB_SF_OFS] ; Load stack frame information - B SVC_FP_LazyState ; Branch to FP lazy state handling - #else - B SVC_ContextRestore ; Branch to context restore handling - #endif - -SVC_ContextSaveRegs - LDR R12,[R1,#TCB_SP_OFS] ; Load SP - #if (FPU_USED != 0) - LDRB LR, [R1,#TCB_SF_OFS] ; Load stack frame information - TST LR,#0x10 ; Determine stack frame from EXC_RETURN bit 4 - IT EQ ; If extended stack frame - VSTMIAEQ R12!,{S16-S31} ; Save VFP S16..S31 - #endif - STM R12,{R4-R11} ; Save R4..R11 - #else - STMDB R12!,{R4-R11} ; Save R4..R11 - #if (FPU_USED != 0) - TST LR,#0x10 ; Determine stack frame from EXC_RETURN bit 4 - IT EQ ; If extended stack frame - VSTMDBEQ R12!,{S16-S31} ; Save VFP S16.S31 - STRB LR, [R1,#TCB_SF_OFS] ; Store stack frame information - #endif - STR R12,[R1,#TCB_SP_OFS] ; Store SP - #endif SVC_ContextRestore LDR R0,[R2,#TCB_SP_OFS] ; Load SP - #if (FPU_USED != 0) - LDRB R1,[R2,#TCB_SF_OFS] ; Load stack frame information - ORN LR,R1,#0xFF ; Set EXC_RETURN - TST LR,#0x10 ; Determine stack frame from EXC_RETURN bit 4 - IT EQ ; If extended stack frame - VLDMIAEQ R0!,{S16-S31} ; Restore VFP S16..S31 - #else - MVN LR,#~0xFFFFFFFD ; Set EXC_RETURN value - #endif LDMIA R0!,{R4-R11} ; Restore R4..R11 MSR PSP,R0 ; Set PSP + MVN LR,#~0xFFFFFFFD ; Set EXC_RETURN value + SVC_Exit BX LR ; Exit from handler @@ -197,8 +112,8 @@ PendSV_Handler PUSH {R0,LR} ; Save EXC_RETURN BL osRtxPendSV_Handler ; Call osRtxPendSV_Handler POP {R0,LR} ; Restore EXC_RETURN - MRS R12,PSP ; Save PSP to R12 - B SVC_Context ; Branch to context handling + MRS R12,PSP + B SVC_Context SysTick_Handler @@ -208,8 +123,8 @@ SysTick_Handler PUSH {R0,LR} ; Save EXC_RETURN BL osRtxTick_Handler ; Call osRtxTick_Handler POP {R0,LR} ; Restore EXC_RETURN - MRS R12,PSP ; Save PSP to R12 - B SVC_Context ; Branch to context handling + MRS R12,PSP + B SVC_Context END diff --git a/cmsis/CMSIS_5/CMSIS/RTOS2/RTX/Source/TOOLCHAIN_IAR/TARGET_M33/irq_armv8mml_common.S b/cmsis/CMSIS_5/CMSIS/RTOS2/RTX/Source/TOOLCHAIN_IAR/TARGET_M33/irq_armv8mml_common.S index 00a84225cc5a..aa1cbc218fb1 100644 --- a/cmsis/CMSIS_5/CMSIS/RTOS2/RTX/Source/TOOLCHAIN_IAR/TARGET_M33/irq_armv8mml_common.S +++ b/cmsis/CMSIS_5/CMSIS/RTOS2/RTX/Source/TOOLCHAIN_IAR/TARGET_M33/irq_armv8mml_common.S @@ -1,5 +1,5 @@ ;/* -; * Copyright (c) 2016-2021 Arm Limited. All rights reserved. +; * Copyright (c) 2016-2020 Arm Limited. All rights reserved. ; * ; * SPDX-License-Identifier: Apache-2.0 ; * @@ -18,17 +18,12 @@ ; * ----------------------------------------------------------------------------- ; * ; * Project: CMSIS-RTOS RTX -; * Title: ARMv8-M Mainline Exception handlers +; * Title: ARMv8M Mainline Exception handlers ; * ; * ----------------------------------------------------------------------------- ; */ - NAME irq_armv8mml.s - - - #include "rtx_def.h" - #ifndef DOMAIN_NS #define DOMAIN_NS 0 #endif @@ -51,11 +46,6 @@ TCB_SP_OFS EQU 56 ; TCB.SP offset TCB_SF_OFS EQU 34 ; TCB.stack_frame offset TCB_TZM_OFS EQU 64 ; TCB.tz_memory offset -FPCCR EQU 0xE000EF34 ; FPCCR Address - -osRtxErrorStackOverflow\ - EQU 1 ; Stack overflow - PRESERVE8 @@ -73,14 +63,10 @@ SVC_Handler EXPORT SVC_Handler IMPORT osRtxUserSVC IMPORT osRtxInfo - #ifdef RTX_STACK_CHECK - IMPORT osRtxThreadStackCheck - IMPORT osRtxKernelErrorNotify - #endif - #if (DOMAIN_NS != 0) + #if (DOMAIN_NS == 1) IMPORT TZ_LoadContext_S IMPORT TZ_StoreContext_S - #endif + #endif TST LR,#0x04 ; Determine return stack from EXC_RETURN bit 2 ITE EQ @@ -89,7 +75,7 @@ SVC_Handler LDR R1,[R0,#24] ; Load saved PC from stack LDRB R1,[R1,#-2] ; Load SVC number - CMP R1,#0 ; Check SVC number + CMP R1,#0 BNE SVC_User ; Branch if not SVC 0 PUSH {R0,LR} ; Save SP and EXC_RETURN @@ -99,131 +85,79 @@ SVC_Handler STM R12,{R0-R1} ; Store function return values SVC_Context - LDR R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.thread.run + LDR R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run LDM R3,{R1,R2} ; Load osRtxInfo.thread.run: curr & next CMP R1,R2 ; Check if thread switch is required IT EQ BXEQ LR ; Exit when threads are the same - STR R2,[R3] ; osRtxInfo.thread.run: curr = next - - #if ((FPU_USED != 0) || (MVE_USED != 0)) + #if ((FPU_USED == 1) || (MVE_USED == 1)) CBNZ R1,SVC_ContextSave ; Branch if running thread is not deleted -SVC_FP_LazyState - TST LR,#0x10 ; Determine stack frame from EXC_RETURN bit 4 - BNE SVC_ContextRestore ; Branch if not extended stack frame - LDR R3,=FPCCR ; FPCCR Address - LDR R0,[R3] ; Load FPCCR - BIC R0,R0,#1 ; Clear LSPACT (Lazy state preservation) - STR R0,[R3] ; Store FPCCR - B SVC_ContextRestore ; Branch to context restore handling - #else - CBZ R1,SVC_ContextRestore ; Branch if running thread is deleted - #endif + TST LR,#0x10 ; Check if extended stack frame + BNE SVC_ContextSwitch + LDR R1,=0xE000EF34 ; FPCCR Address + LDR R0,[R1] ; Load FPCCR + BIC R0,R0,#1 ; Clear LSPACT (Lazy state) + STR R0,[R1] ; Store FPCCR + B SVC_ContextSwitch + #else + CBZ R1,SVC_ContextSwitch ; Branch if running thread is deleted + #endif SVC_ContextSave - #if (DOMAIN_NS != 0) + #if (DOMAIN_NS == 1) LDR R0,[R1,#TCB_TZM_OFS] ; Load TrustZone memory identifier - CBZ R0,SVC_ContextSave_NS ; Branch if there is no secure context - PUSH {R1,R2,R12,LR} ; Save registers and EXC_RETURN + CBZ R0,SVC_ContextSave1 ; Branch if there is no secure context + PUSH {R1,R2,R3,LR} ; Save registers and EXC_RETURN BL TZ_StoreContext_S ; Store secure context - POP {R1,R2,R12,LR} ; Restore registers and EXC_RETURN - #endif + POP {R1,R2,R3,LR} ; Restore registers and EXC_RETURN + #endif + +SVC_ContextSave1 + MRS R0,PSP ; Get PSP + STMDB R0!,{R4-R11} ; Save R4..R11 + #if ((FPU_USED == 1) || (MVE_USED == 1)) + TST LR,#0x10 ; Check if extended stack frame + IT EQ + VSTMDBEQ R0!,{S16-S31} ; Save VFP S16.S31 + #endif -SVC_ContextSave_NS - #if (DOMAIN_NS != 0) - TST LR,#0x40 ; Check domain of interrupted thread - BNE SVC_ContextSaveSP ; Branch if secure - #endif - - #ifdef RTX_STACK_CHECK - SUB R12,R12,#32 ; Calculate SP: space for R4..R11 - #if ((FPU_USED != 0) || (MVE_USED != 0)) - TST LR,#0x10 ; Determine stack frame from EXC_RETURN bit 4 - IT EQ ; If extended stack frame - SUBEQ R12,R12,#64 ; Additional space for S16..S31 - #endif - -SVC_ContextSaveSP - STR R12,[R1,#TCB_SP_OFS] ; Store SP - STRB LR, [R1,#TCB_SF_OFS] ; Store stack frame information - - PUSH {R1,R2} ; Save osRtxInfo.thread.run: curr & next - MOV R0,R1 ; Parameter: osRtxInfo.thread.run.curr - BL osRtxThreadStackCheck ; Check if thread stack is overrun - POP {R1,R2} ; Restore osRtxInfo.thread.run: curr & next - CBNZ R0,SVC_ContextSaveRegs ; Branch when stack check is ok - - #if ((FPU_USED != 0) || (MVE_USED != 0)) - MOV R4,R1 ; Save osRtxInfo.thread.run.curr - #endif - MOV R0,#osRtxErrorStackOverflow ; Parameter: r0=code, r1=object_id - BL osRtxKernelErrorNotify ; Call osRtxKernelErrorNotify - LDR R3,=osRtxInfo+I_T_RUN_OFS ; Load address of osRtxInfo.thread.run - LDR R2,[R3,#4] ; Load osRtxInfo.thread.run: next +SVC_ContextSave2 + STR R0,[R1,#TCB_SP_OFS] ; Store SP + STRB LR,[R1,#TCB_SF_OFS] ; Store stack frame information + +SVC_ContextSwitch STR R2,[R3] ; osRtxInfo.thread.run: curr = next - #if ((FPU_USED != 0) || (MVE_USED != 0)) - LDRB LR,[R4,#TCB_SF_OFS] ; Load stack frame information - B SVC_FP_LazyState ; Branch to FP lazy state handling - #else - B SVC_ContextRestore ; Branch to context restore handling - #endif - -SVC_ContextSaveRegs - LDRB LR,[R1,#TCB_SF_OFS] ; Load stack frame information - #if (DOMAIN_NS != 0) - TST LR,#0x40 ; Check domain of interrupted thread - BNE SVC_ContextRestore ; Branch if secure - #endif - LDR R12,[R1,#TCB_SP_OFS] ; Load SP - #if ((FPU_USED != 0) || (MVE_USED != 0)) - TST LR,#0x10 ; Determine stack frame from EXC_RETURN bit 4 - IT EQ ; If extended stack frame - VSTMIAEQ R12!,{S16-S31} ; Save VFP S16..S31 - #endif - STM R12,{R4-R11} ; Save R4..R11 - #else - STMDB R12!,{R4-R11} ; Save R4..R11 - #if ((FPU_USED != 0) || (MVE_USED != 0)) - TST LR,#0x10 ; Determine stack frame from EXC_RETURN bit 4 - IT EQ ; If extended stack frame - VSTMDBEQ R12!,{S16-S31} ; Save VFP S16.S31 - #endif - -SVC_ContextSaveSP - STR R12,[R1,#TCB_SP_OFS] ; Store SP - STRB LR, [R1,#TCB_SF_OFS] ; Store stack frame information - #endif SVC_ContextRestore - #if (DOMAIN_NS != 0) + #if (DOMAIN_NS == 1) LDR R0,[R2,#TCB_TZM_OFS] ; Load TrustZone memory identifier - CBZ R0,SVC_ContextRestore_NS; Branch if there is no secure context + CBZ R0,SVC_ContextRestore1 ; Branch if there is no secure context PUSH {R2,R3} ; Save registers BL TZ_LoadContext_S ; Load secure context POP {R2,R3} ; Restore registers - #endif + #endif -SVC_ContextRestore_NS - LDR R0,[R2,#TCB_SP_OFS] ; Load SP - LDR R1,[R2,#TCB_SM_OFS] ; Load stack memory base - MSR PSPLIM,R1 ; Set PSPLIM +SVC_ContextRestore1 + LDR R0,[R2,#TCB_SM_OFS] ; Load stack memory base LDRB R1,[R2,#TCB_SF_OFS] ; Load stack frame information - ORN LR,R1,#0xFF ; Set EXC_RETURN + MSR PSPLIM,R0 ; Set PSPLIM + LDR R0,[R2,#TCB_SP_OFS] ; Load SP + ORR LR,R1,#0xFFFFFF00 ; Set EXC_RETURN - #if (DOMAIN_NS != 0) + #if (DOMAIN_NS == 1) TST LR,#0x40 ; Check domain of interrupted thread - BNE SVC_ContextRestoreSP ; Branch if secure - #endif + BNE SVC_ContextRestore2 ; Branch if secure + #endif - #if ((FPU_USED != 0) || (MVE_USED != 0)) - TST LR,#0x10 ; Determine stack frame from EXC_RETURN bit 4 - IT EQ ; If extended stack frame + #if ((FPU_USED == 1) || (MVE_USED == 1)) + TST LR,#0x10 ; Check if extended stack frame + IT EQ VLDMIAEQ R0!,{S16-S31} ; Restore VFP S16..S31 - #endif + #endif LDMIA R0!,{R4-R11} ; Restore R4..R11 -SVC_ContextRestoreSP +SVC_ContextRestore2 MSR PSP,R0 ; Set PSP SVC_Exit @@ -252,8 +186,7 @@ PendSV_Handler PUSH {R0,LR} ; Save EXC_RETURN BL osRtxPendSV_Handler ; Call osRtxPendSV_Handler POP {R0,LR} ; Restore EXC_RETURN - MRS R12,PSP ; Save PSP to R12 - B SVC_Context ; Branch to context handling + B Sys_Context SysTick_Handler @@ -263,8 +196,87 @@ SysTick_Handler PUSH {R0,LR} ; Save EXC_RETURN BL osRtxTick_Handler ; Call osRtxTick_Handler POP {R0,LR} ; Restore EXC_RETURN - MRS R12,PSP ; Save PSP to R12 - B SVC_Context ; Branch to context handling + B Sys_Context + + + +Sys_Context + EXPORT Sys_Context + IMPORT osRtxInfo + #if (DOMAIN_NS == 1) + IMPORT TZ_LoadContext_S + IMPORT TZ_StoreContext_S + #endif + + LDR R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run + LDM R3,{R1,R2} ; Load osRtxInfo.thread.run: curr & next + CMP R1,R2 ; Check if thread switch is required + IT EQ + BXEQ LR ; Exit when threads are the same +Sys_ContextSave + #if (DOMAIN_NS == 1) + LDR R0,[R1,#TCB_TZM_OFS] ; Load TrustZone memory identifier + CBZ R0,Sys_ContextSave1 ; Branch if there is no secure context + PUSH {R1,R2,R3,LR} ; Save registers and EXC_RETURN + BL TZ_StoreContext_S ; Store secure context + POP {R1,R2,R3,LR} ; Restore registers and EXC_RETURN + +Sys_ContextSave1 + TST LR,#0x40 ; Check domain of interrupted thread + IT NE + MRSNE R0,PSP ; Get PSP + BNE Sys_ContextSave3 ; Branch if secure + #endif + +Sys_ContextSave2 + MRS R0,PSP ; Get PSP + STMDB R0!,{R4-R11} ; Save R4..R11 + #if ((FPU_USED == 1) || (MVE_USED == 1)) + TST LR,#0x10 ; Check if extended stack frame + IT EQ + VSTMDBEQ R0!,{S16-S31} ; Save VFP S16.S31 + #endif + +Sys_ContextSave3 + STR R0,[R1,#TCB_SP_OFS] ; Store SP + STRB LR,[R1,#TCB_SF_OFS] ; Store stack frame information + +Sys_ContextSwitch + STR R2,[R3] ; osRtxInfo.run: curr = next + +Sys_ContextRestore + #if (DOMAIN_NS == 1) + LDR R0,[R2,#TCB_TZM_OFS] ; Load TrustZone memory identifier + CBZ R0,Sys_ContextRestore1 ; Branch if there is no secure context + PUSH {R2,R3} ; Save registers + BL TZ_LoadContext_S ; Load secure context + POP {R2,R3} ; Restore registers + #endif + +Sys_ContextRestore1 + LDR R0,[R2,#TCB_SM_OFS] ; Load stack memory base + LDRB R1,[R2,#TCB_SF_OFS] ; Load stack frame information + MSR PSPLIM,R0 ; Set PSPLIM + LDR R0,[R2,#TCB_SP_OFS] ; Load SP + ORR LR,R1,#0xFFFFFF00 ; Set EXC_RETURN + + #if (DOMAIN_NS == 1) + TST LR,#0x40 ; Check domain of interrupted thread + BNE Sys_ContextRestore2 ; Branch if secure + #endif + + #if ((FPU_USED == 1) || (MVE_USED == 1)) + TST LR,#0x10 ; Check if extended stack frame + IT EQ + VLDMIAEQ R0!,{S16-S31} ; Restore VFP S16..S31 + #endif + LDMIA R0!,{R4-R11} ; Restore R4..R11 + +Sys_ContextRestore2 + MSR PSP,R0 ; Set PSP + +Sys_ContextExit + BX LR ; Exit from handler END diff --git a/cmsis/CMSIS_5/CMSIS/RTOS2/RTX/Source/TOOLCHAIN_IAR/TARGET_RTOS_M4_M7/irq_cm4f.S b/cmsis/CMSIS_5/CMSIS/RTOS2/RTX/Source/TOOLCHAIN_IAR/TARGET_RTOS_M4_M7/irq_cm4f.S index 3b6f9cf1d337..4f8f3d4c8f55 100644 --- a/cmsis/CMSIS_5/CMSIS/RTOS2/RTX/Source/TOOLCHAIN_IAR/TARGET_RTOS_M4_M7/irq_cm4f.S +++ b/cmsis/CMSIS_5/CMSIS/RTOS2/RTX/Source/TOOLCHAIN_IAR/TARGET_RTOS_M4_M7/irq_cm4f.S @@ -1,5 +1,5 @@ ;/* -; * Copyright (c) 2013-2021 Arm Limited. All rights reserved. +; * Copyright (c) 2013-2018 Arm Limited. All rights reserved. ; * ; * SPDX-License-Identifier: Apache-2.0 ; * @@ -18,32 +18,19 @@ ; * ----------------------------------------------------------------------------- ; * ; * Project: CMSIS-RTOS RTX -; * Title: ARMv7-M Exception handlers +; * Title: Cortex-M4F Exception handlers ; * ; * ----------------------------------------------------------------------------- ; */ - NAME irq_armv7m.s + NAME irq_cm4f.s - #include "rtx_def.h" - -#ifdef __ARMVFP__ -FPU_USED EQU 1 -#else -FPU_USED EQU 0 -#endif - I_T_RUN_OFS EQU 20 ; osRtxInfo.thread.run offset TCB_SP_OFS EQU 56 ; TCB.SP offset TCB_SF_OFS EQU 34 ; TCB.stack_frame offset -FPCCR EQU 0xE000EF34 ; FPCCR Address - -osRtxErrorStackOverflow\ - EQU 1 ; Stack overflow - PRESERVE8 SECTION .rodata:DATA:NOROOT(2) @@ -61,10 +48,6 @@ SVC_Handler EXPORT SVC_Handler IMPORT osRtxUserSVC IMPORT osRtxInfo - #ifdef RTX_STACK_CHECK - IMPORT osRtxThreadStackCheck - IMPORT osRtxKernelErrorNotify - #endif TST LR,#0x04 ; Determine return stack from EXC_RETURN bit 2 ITE EQ @@ -73,8 +56,7 @@ SVC_Handler LDR R1,[R0,#24] ; Load saved PC from stack LDRB R1,[R1,#-2] ; Load SVC number - CMP R1,#0 ; Check SVC number - BNE SVC_User ; Branch if not SVC 0 + CBNZ R1,SVC_User ; Branch if not SVC 0 PUSH {R0,LR} ; Save SP and EXC_RETURN LDM R0,{R0-R3,R12} ; Load function parameters and address from stack @@ -83,91 +65,47 @@ SVC_Handler STM R12,{R0-R1} ; Store function return values SVC_Context - LDR R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.thread.run + LDR R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run LDM R3,{R1,R2} ; Load osRtxInfo.thread.run: curr & next CMP R1,R2 ; Check if thread switch is required IT EQ BXEQ LR ; Exit when threads are the same - STR R2,[R3] ; osRtxInfo.thread.run: curr = next - - #if (FPU_USED != 0) CBNZ R1,SVC_ContextSave ; Branch if running thread is not deleted -SVC_FP_LazyState - TST LR,#0x10 ; Determine stack frame from EXC_RETURN bit 4 - BNE SVC_ContextRestore ; Branch if not extended stack frame - LDR R3,=FPCCR ; FPCCR Address - LDR R0,[R3] ; Load FPCCR - BIC R0,R0,#1 ; Clear LSPACT (Lazy state preservation) - STR R0,[R3] ; Store FPCCR - B SVC_ContextRestore ; Branch to context restore handling - #else - CBZ R1,SVC_ContextRestore ; Branch if running thread is deleted - #endif + TST LR,#0x10 ; Check if extended stack frame + BNE SVC_ContextSwitch +#ifdef __FPU_PRESENT + LDR R1,=0xE000EF34 ; FPCCR Address + LDR R0,[R1] ; Load FPCCR + BIC R0,R0,#1 ; Clear LSPACT (Lazy state) + STR R0,[R1] ; Store FPCCR + B SVC_ContextSwitch +#endif SVC_ContextSave - #ifdef RTX_STACK_CHECK - SUB R12,R12,#32 ; Calculate SP: space for R4..R11 - #if (FPU_USED != 0) - TST LR,#0x10 ; Determine stack frame from EXC_RETURN bit 4 - IT EQ ; If extended stack frame - SUBEQ R12,R12,#64 ; Additional space for S16..S31 - STRB LR, [R1,#TCB_SF_OFS] ; Store stack frame information - #endif - STR R12,[R1,#TCB_SP_OFS] ; Store SP - - PUSH {R1,R2} ; Save osRtxInfo.thread.run: curr & next - MOV R0,R1 ; Parameter: osRtxInfo.thread.run.curr - BL osRtxThreadStackCheck ; Check if thread stack is overrun - POP {R1,R2} ; Restore osRtxInfo.thread.run: curr & next - CBNZ R0,SVC_ContextSaveRegs ; Branch when stack check is ok - - #if (FPU_USED != 0) - MOV R4,R1 ; Save osRtxInfo.thread.run.curr - #endif - MOV R0,#osRtxErrorStackOverflow ; Parameter: r0=code, r1=object_id - BL osRtxKernelErrorNotify ; Call osRtxKernelErrorNotify - LDR R3,=osRtxInfo+I_T_RUN_OFS ; Load address of osRtxInfo.thread.run - LDR R2,[R3,#4] ; Load osRtxInfo.thread.run: next - STR R2,[R3] ; osRtxInfo.thread.run: curr = next - #if (FPU_USED != 0) - LDRB LR,[R4,#TCB_SF_OFS] ; Load stack frame information - B SVC_FP_LazyState ; Branch to FP lazy state handling - #else - B SVC_ContextRestore ; Branch to context restore handling - #endif - -SVC_ContextSaveRegs - LDR R12,[R1,#TCB_SP_OFS] ; Load SP - #if (FPU_USED != 0) - LDRB LR, [R1,#TCB_SF_OFS] ; Load stack frame information - TST LR,#0x10 ; Determine stack frame from EXC_RETURN bit 4 - IT EQ ; If extended stack frame - VSTMIAEQ R12!,{S16-S31} ; Save VFP S16..S31 - #endif - STM R12,{R4-R11} ; Save R4..R11 - #else STMDB R12!,{R4-R11} ; Save R4..R11 - #if (FPU_USED != 0) - TST LR,#0x10 ; Determine stack frame from EXC_RETURN bit 4 - IT EQ ; If extended stack frame +#ifdef __FPU_PRESENT + TST LR,#0x10 ; Check if extended stack frame + IT EQ VSTMDBEQ R12!,{S16-S31} ; Save VFP S16.S31 - STRB LR, [R1,#TCB_SF_OFS] ; Store stack frame information - #endif +#endif + STR R12,[R1,#TCB_SP_OFS] ; Store SP - #endif + STRB LR, [R1,#TCB_SF_OFS] ; Store stack frame information + +SVC_ContextSwitch + STR R2,[R3] ; osRtxInfo.thread.run: curr = next SVC_ContextRestore - LDR R0,[R2,#TCB_SP_OFS] ; Load SP - #if (FPU_USED != 0) LDRB R1,[R2,#TCB_SF_OFS] ; Load stack frame information - ORN LR,R1,#0xFF ; Set EXC_RETURN - TST LR,#0x10 ; Determine stack frame from EXC_RETURN bit 4 - IT EQ ; If extended stack frame + LDR R0,[R2,#TCB_SP_OFS] ; Load SP + ORR LR,R1,#0xFFFFFF00 ; Set EXC_RETURN + +#ifdef __FPU_PRESENT + TST LR,#0x10 ; Check if extended stack frame + IT EQ VLDMIAEQ R0!,{S16-S31} ; Restore VFP S16..S31 - #else - MVN LR,#~0xFFFFFFFD ; Set EXC_RETURN value - #endif +#endif LDMIA R0!,{R4-R11} ; Restore R4..R11 MSR PSP,R0 ; Set PSP @@ -197,8 +135,8 @@ PendSV_Handler PUSH {R0,LR} ; Save EXC_RETURN BL osRtxPendSV_Handler ; Call osRtxPendSV_Handler POP {R0,LR} ; Restore EXC_RETURN - MRS R12,PSP ; Save PSP to R12 - B SVC_Context ; Branch to context handling + MRS R12,PSP + B SVC_Context SysTick_Handler @@ -208,8 +146,8 @@ SysTick_Handler PUSH {R0,LR} ; Save EXC_RETURN BL osRtxTick_Handler ; Call osRtxTick_Handler POP {R0,LR} ; Restore EXC_RETURN - MRS R12,PSP ; Save PSP to R12 - B SVC_Context ; Branch to context handling + MRS R12,PSP + B SVC_Context END