FPGA+SIM: updated Vivado project to compile RISC-V simulation, access… #201
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| # This is a basic workflow to help you get started with Actions | |
| name: riscv-arch-test | |
| # Controls when the workflow will run | |
| on: | |
| # Triggers the workflow on push or pull request events but only for the master branch | |
| push: | |
| branches: [ master ] | |
| pull_request: | |
| branches: [ master ] | |
| # Allows you to run this workflow manually from the Actions tab | |
| workflow_dispatch: | |
| env: | |
| # variables used by Verilator build scripts | |
| CI_OS_NAME: linux | |
| CI_BUILD_STAGE_NAME: build | |
| # Ccache variables | |
| CCACHE_COMPRESS: 1 | |
| CCACHE_DIR: ${{ github.workspace }}/.ccache | |
| CCACHE_LIMIT_MULTIPLE: 0.95 | |
| # A workflow run is made up of one or more jobs that can run sequentially or in parallel | |
| jobs: | |
| # This workflow contains a single job called "build" | |
| build: | |
| # The type of runner that the job will run on | |
| runs-on: ubuntu-22.04 | |
| strategy: | |
| fail-fast: false | |
| matrix: | |
| xlen: | |
| - 32 | |
| # - 64 | |
| device: | |
| - I | |
| - C | |
| # - M | |
| # - privilege | |
| # - Zifencei | |
| name: "RISC-V Compatibility Check" | |
| env: | |
| # variables used by Verilator build scripts | |
| CI_BUILD_STAGE_NAME: build | |
| CI_RUNS_ON: ubuntu-22.04 | |
| CI_M32: 0 | |
| # Ccache variables | |
| CACHE_BASE_KEY: test-${{ matrix.xlen }}-${{ matrix.device }} | |
| CCACHE_MAXSIZE: 64M # Per build matrix entry (2160M in total) | |
| # Steps represent a sequence of tasks that will be executed as part of the job | |
| steps: | |
| # Checks-out your repository under $GITHUB_WORKSPACE, so your job can access it | |
| - name: "repository checkout" | |
| uses: actions/checkout@v3 | |
| with: | |
| submodules: recursive | |
| - name: Cache $CCACHE_DIR | |
| uses: actions/cache@v2 | |
| env: | |
| CACHE_KEY: ${{ env.CACHE_BASE_KEY }}-ccache | |
| with: | |
| path: ${{ env.CCACHE_DIR }} | |
| key: ${{ env.CACHE_KEY }}-${{ github.sha }} | |
| restore-keys: | | |
| ${{ env.CACHE_KEY }}- | |
| - name: "Setup RISC-V GCC" | |
| run: | | |
| wget https://github.com/riscv-collab/riscv-gnu-toolchain/releases/download/2022.06.10/riscv32-elf-ubuntu-20.04-nightly-2022.06.10-nightly.tar.gz | |
| tar -xzf riscv32-elf-ubuntu-20.04-nightly-2022.06.10-nightly.tar.gz | |
| ls -la riscv | |
| - name: Install dependencies and build Verilator | |
| run: | | |
| cd submodules/verilator | |
| ./ci/ci-install.bash | |
| ./ci/ci-script.bash | |
| # - name: "Install SystemC and Verilator" | |
| # run: | | |
| # sudo apt install libsystemc | |
| # | |
| # - name: 'Add Verilator docker image' | |
| # uses: docker://iztokjeras/verilator:latest | |
| # | |
| # - name: "Setup Verilator" | |
| # run: | | |
| # sudo apt install libsystemc | |
| # wget https://github.com/sifive/verilator/releases/download/4.204-0sifive3/verilator_4.204-0sifive3_amd64.deb | |
| # sudo dpkg -i verilator_4.204-0sifive3_amd64.deb | |
| - name: 'Run RISC-V Architecture Tests' | |
| env: | |
| RISCV_TARGET: r5p | |
| XLEN: ${{ matrix.xlen }} | |
| RISCV_DEVICE: ${{ matrix.device }} | |
| run: | | |
| export PATH=`pwd`/riscv/bin/:$PATH | |
| source sim/verilator/settings.sh | |
| cd test | |
| TARGETDIR=`pwd` WORK=`pwd`/work make -C ../submodules/riscv-arch-test verify |