Pinned Loading

1. rp32 rp32 Public

   RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).

   SystemVerilog 12 3

2. TCB TCB Public

   Tightly Coupled Bus, low complexity, high performance system bus.

   SystemVerilog 1

3. fri-magisterij fri-magisterij Public

   Forked from mitar/fri-latex-templates

   LaTeX templates for theses written at Faculty of Computer and Information Science, University of Ljubljana.

   PostScript

4. preimages-2D preimages-2D Public

   2D cellular automata preimages count&list algorithm

   C 3

5. sockit_cdc sockit_cdc Public

   clock domain crossing FIFO

   Verilog 6 2

6. sockit_owm sockit_owm Public

   SocKit 1-wire (onewire) master

   C 19 6