diff --git a/Makefile b/Makefile index 673e6812c..6bdba3733 100644 --- a/Makefile +++ b/Makefile @@ -1,4 +1,4 @@ -BOARDS ?= QUARTZ64 SOQUARTZ ROC-RK3566-PC ROC-RK3568-PC ORANGEPI3B PINETAB2 +BOARDS ?= QUARTZ64 SOQUARTZ ROC-RK3566-PC ROC-RK3568-PC ORANGEPI3B PINETAB2 NANOPI-R5S TARGET ?= RELEASE .PHONY: all diff --git a/build.sh b/build.sh index 0940b364a..56f41cf38 100755 --- a/build.sh +++ b/build.sh @@ -110,6 +110,10 @@ for board in ${RKUEFIBOARDS}; do build_uefi Pine64 PineTab2 build_fit PineTab2 rk3566-pinetab2 ;; + NANOPI-R5S) + build_uefi FriendlyElec NanoPi-R5S + build_fit NanoPi-R5S rk3568-nanopi-r5s + ;; *) echo "Unknown board ${board}" exit 1 diff --git a/dtb/rk3568-nanopi-r5s.dtb b/dtb/rk3568-nanopi-r5s.dtb new file mode 100644 index 000000000..be803b812 Binary files /dev/null and b/dtb/rk3568-nanopi-r5s.dtb differ diff --git a/edk2-rockchip/Platform/FriendlyElec/NanoPi-R5S/Drivers/BoardInitDxe/BoardInitDxe.c b/edk2-rockchip/Platform/FriendlyElec/NanoPi-R5S/Drivers/BoardInitDxe/BoardInitDxe.c new file mode 100644 index 000000000..eb841ffbd --- /dev/null +++ b/edk2-rockchip/Platform/FriendlyElec/NanoPi-R5S/Drivers/BoardInitDxe/BoardInitDxe.c @@ -0,0 +1,347 @@ +/** @file + * + * Board init for the FriendlyELEC NanoPi-R5S board + * + * Copyright (c) 2021-2023, Jared McNeill + * Copyright (c) 2022-2023, Sergey Tyuryukanov + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "EthernetPhy.h" + +/* + * GMAC registers + */ +#define GMAC0_MAC_ADDRESS0_LOW (GMAC0_BASE + 0x0304) +#define GMAC0_MAC_ADDRESS0_HIGH (GMAC0_BASE + 0x0300) + +#define GRF_MAC0_CON0 (SYS_GRF + 0x0380) +#define CLK_RX_DL_CFG_SHIFT 8 +#define CLK_TX_DL_CFG_SHIFT 0 +#define GRF_MAC0_CON1 (SYS_GRF + 0x0384) +#define PHY_INTF_SEL_SHIFT 4 +#define PHY_INTF_SEL_MASK (0x7U << PHY_INTF_SEL_SHIFT) +#define PHY_INTF_SEL_RGMII (1U << PHY_INTF_SEL_SHIFT) +#define FLOWCTRL BIT3 +#define MAC_SPEED BIT2 +#define RXCLK_DLY_ENA BIT1 +#define TXCLK_DLY_ENA BIT0 + +#define TX_DELAY_GMAC0 0x3C +#define RX_DELAY_GMAC0 0x2F + +/* + * PMIC registers +*/ +#define PMIC_I2C_ADDR 0x20 + +#define PMIC_CHIP_NAME 0xed +#define PMIC_CHIP_VER 0xee +#define PMIC_POWER_EN1 0xb2 +#define PMIC_POWER_EN2 0xb3 +#define PMIC_POWER_EN3 0xb4 +#define PMIC_LDO1_ON_VSEL 0xcc +#define PMIC_LDO2_ON_VSEL 0xce +#define PMIC_LDO3_ON_VSEL 0xd0 +#define PMIC_LDO4_ON_VSEL 0xd2 +#define PMIC_LDO6_ON_VSEL 0xd6 +#define PMIC_LDO7_ON_VSEL 0xd8 +#define PMIC_LDO8_ON_VSEL 0xda +#define PMIC_LDO9_ON_VSEL 0xdc + +/* + * CPU_GRF registers +*/ +#define GRF_CPU_COREPVTPLL_CON0 (CPU_GRF + 0x0010) +#define CORE_PVTPLL_RING_LENGTH_SEL_SHIFT 3 +#define CORE_PVTPLL_RING_LENGTH_SEL_MASK (0x1FU << CORE_PVTPLL_RING_LENGTH_SEL_SHIFT) +#define CORE_PVTPLL_OSC_EN BIT1 +#define CORE_PVTPLL_START BIT0 + + /* + * SYS_GRF registers + */ +#define GRF_IOFUNC_SEL5 (SYS_GRF + 0x0314) +#define PCIE20X1_IOMUX_SEL_MASK (BIT3|BIT2) +#define PCIE20X1_IOMUX_SEL_M1 BIT2 +#define PCIE20X1_IOMUX_SEL_M2 BIT3 +#define PCIE30X1_IOMUX_SEL_MASK (BIT5|BIT4) +#define PCIE30X1_IOMUX_SEL_M1 BIT4 +#define PCIE30X1_IOMUX_SEL_M2 BIT5 +#define PCIE30X2_IOMUX_SEL_MASK (BIT7|BIT6) +#define PCIE30X2_IOMUX_SEL_M1 BIT6 +#define PCIE30X2_IOMUX_SEL_M2 BIT7 + +/* + * PMU registers + */ +#define PMU_NOC_AUTO_CON0 (PMU_BASE + 0x0070) +#define PMU_NOC_AUTO_CON1 (PMU_BASE + 0x0074) + +STATIC CONST GPIO_IOMUX_CONFIG mGmac0IomuxConfig[] = { + { "gmac0_mdcm", 2, GPIO_PIN_PC3, 2, GPIO_PIN_PULL_NONE, GPIO_PIN_DRIVE_DEFAULT }, + { "gmac0_mdio", 2, GPIO_PIN_PC4, 2, GPIO_PIN_PULL_NONE, GPIO_PIN_DRIVE_DEFAULT }, + { "gmac0_txd0", 2, GPIO_PIN_PB3, 1, GPIO_PIN_PULL_NONE, GPIO_PIN_DRIVE_2 }, + { "gmac0_txd1", 2, GPIO_PIN_PB4, 1, GPIO_PIN_PULL_NONE, GPIO_PIN_DRIVE_2 }, + { "gmac0_txen", 2, GPIO_PIN_PB5, 1, GPIO_PIN_PULL_NONE, GPIO_PIN_DRIVE_DEFAULT }, + { "gmac0_rxd0", 2, GPIO_PIN_PB6, 1, GPIO_PIN_PULL_NONE, GPIO_PIN_DRIVE_DEFAULT }, + { "gmac0_rxd1", 2, GPIO_PIN_PB7, 2, GPIO_PIN_PULL_NONE, GPIO_PIN_DRIVE_DEFAULT }, + { "gmac0_rxdvcrs", 2, GPIO_PIN_PC0, 2, GPIO_PIN_PULL_NONE, GPIO_PIN_DRIVE_DEFAULT }, + { "gmac0_rxclk", 2, GPIO_PIN_PA5, 2, GPIO_PIN_PULL_NONE, GPIO_PIN_DRIVE_DEFAULT }, + { "gmac0_txclk", 2, GPIO_PIN_PB0, 2, GPIO_PIN_PULL_NONE, GPIO_PIN_DRIVE_1 }, + { "gmac0_mclkinout", 2, GPIO_PIN_PC2, 2, GPIO_PIN_PULL_NONE, GPIO_PIN_DRIVE_DEFAULT }, + { "gmac0_rxd2", 2, GPIO_PIN_PA3, 2, GPIO_PIN_PULL_NONE, GPIO_PIN_DRIVE_DEFAULT }, + { "gmac0_rxd3", 2, GPIO_PIN_PA4, 2, GPIO_PIN_PULL_NONE, GPIO_PIN_DRIVE_DEFAULT }, + { "gmac0_txd2", 2, GPIO_PIN_PA6, 2, GPIO_PIN_PULL_NONE, GPIO_PIN_DRIVE_2 }, + { "gmac0_txd3", 2, GPIO_PIN_PA7, 2, GPIO_PIN_PULL_NONE, GPIO_PIN_DRIVE_2 }, +}; + +STATIC CONST GPIO_IOMUX_CONFIG mSdmmc2IomuxConfig[] = { + { "sdmmc2_d0m0", 3, GPIO_PIN_PC6, 3, GPIO_PIN_PULL_UP, GPIO_PIN_DRIVE_2 }, + { "sdmmc2_d1m0", 3, GPIO_PIN_PC7, 3, GPIO_PIN_PULL_UP, GPIO_PIN_DRIVE_2 }, + { "sdmmc2_d2m0", 3, GPIO_PIN_PD0, 3, GPIO_PIN_PULL_UP, GPIO_PIN_DRIVE_2 }, + { "sdmmc2_d3m0", 3, GPIO_PIN_PD1, 3, GPIO_PIN_PULL_UP, GPIO_PIN_DRIVE_2 }, + { "sdmmc2_cmdm0", 3, GPIO_PIN_PD2, 3, GPIO_PIN_PULL_UP, GPIO_PIN_DRIVE_2 }, + { "sdmmc2_clkm0", 3, GPIO_PIN_PD3, 3, GPIO_PIN_PULL_UP, GPIO_PIN_DRIVE_2 }, +}; + +// PCIE30X2_CLKREQn_M1 - GPIO2_D4 +// PCIE30X2_WAKEn_M1 - GPIO2_D5 +// PCIE30X2_PERSTn_M1 - GPIO2_D6 - NVMe +STATIC CONST GPIO_IOMUX_CONFIG mPcie30x2IomuxConfig[] = { + { "pcie30x2_clkreqnm1", 2, GPIO_PIN_PD4, 4, GPIO_PIN_PULL_NONE, GPIO_PIN_DRIVE_DEFAULT }, + { "pcie30x2_perstnm1", 2, GPIO_PIN_PD6, 4, GPIO_PIN_PULL_NONE, GPIO_PIN_DRIVE_DEFAULT }, + { "pcie30x2_wakenm1", 2, GPIO_PIN_PD5, 4, GPIO_PIN_PULL_NONE, GPIO_PIN_DRIVE_DEFAULT }, +}; + +STATIC +VOID +BoardInitGmac ( + VOID + ) +{ + UINT32 MacLo, MacHi; + + /* Assert reset */ + CruAssertSoftReset (13, 7); // GMAC0 + + /* Configure pins */ + GpioSetIomuxConfig (mGmac0IomuxConfig, ARRAY_SIZE (mGmac0IomuxConfig)); + + /* Setup GMAC0 clocks */ + MmioWrite32 (CRU_CLKSEL_CON (31), 0x00370004); // Set rmii1_mode to rgmii mode + // Set rgmii1_clk_sel to 125M + // Set rmii1_extclk_sel to mac1 clock from IO + + /* Configure GMAC0 */ + MmioWrite32 (GRF_MAC0_CON0, + 0x7F7F0000U | + (TX_DELAY_GMAC0 << CLK_TX_DL_CFG_SHIFT) | + (RX_DELAY_GMAC0 << CLK_RX_DL_CFG_SHIFT)); + MmioWrite32 (GRF_MAC0_CON1, + ((PHY_INTF_SEL_MASK | TXCLK_DLY_ENA | RXCLK_DLY_ENA) << 16) | + PHY_INTF_SEL_RGMII | + TXCLK_DLY_ENA | + RXCLK_DLY_ENA); + + /* Reset GMAC0 PHY */ + GpioPinSetDirection (0, GPIO_PIN_PC5, GPIO_PIN_OUTPUT); + MicroSecondDelay (1000); + GpioPinWrite (0, GPIO_PIN_PC5, 0); + MicroSecondDelay (20000); + GpioPinWrite (0, GPIO_PIN_PC5, 1); + MicroSecondDelay (100000); + + /* Deassert reset */ + CruDeassertSoftReset (13, 7); // GMAC0 + + /* Generate MAC addresses from the first 32 bytes in the OTP and write it to GMAC0 */ + OtpGetMacAddress (&MacLo, &MacHi); + + /* Use sequential MAC addresses. Last byte is even for GMAC0. */ + MacHi &= ~(1 << 8); + MmioWrite32 (GMAC0_MAC_ADDRESS0_LOW, MacLo); + MmioWrite32 (GMAC0_MAC_ADDRESS0_HIGH, MacHi); + + EthernetPhyInit (GMAC0_BASE); +} + +STATIC +VOID +BoardInitPcie ( + VOID + ) +{ + GpioSetIomuxConfig (mPcie30x2IomuxConfig, ARRAY_SIZE (mPcie30x2IomuxConfig)); + + /* PCIe30x2 IO mux selection - M1 */ + MmioWrite32 (GRF_IOFUNC_SEL5, (PCIE30X2_IOMUX_SEL_MASK << 16) | PCIE30X2_IOMUX_SEL_M1); + + /* PCIECLKIC_OE_H_GPIO3_A7 */ + GpioPinSetPull (3, GPIO_PIN_PA7, GPIO_PIN_PULL_NONE); + GpioPinSetDirection (3, GPIO_PIN_PA7, GPIO_PIN_OUTPUT); + GpioPinWrite (3, GPIO_PIN_PA7, FALSE); +} + +STATIC +EFI_STATUS +PmicRead ( + IN UINT8 Register, + OUT UINT8 *Value + ) +{ + return I2cRead (I2C0_BASE, PMIC_I2C_ADDR, + &Register, sizeof (Register), + Value, sizeof (*Value)); +} + +STATIC +EFI_STATUS +PmicWrite ( + IN UINT8 Register, + IN UINT8 Value + ) +{ + return I2cWrite (I2C0_BASE, PMIC_I2C_ADDR, + &Register, sizeof (Register), + &Value, sizeof (Value)); +} + +STATIC +VOID +BoardInitPmic ( + VOID + ) +{ + EFI_STATUS Status; + UINT16 ChipName; + UINT8 ChipVer; + UINT8 Value; + + DEBUG ((DEBUG_INFO, "BOARD: PMIC init\n")); + + GpioPinSetPull (0, GPIO_PIN_PB1, GPIO_PIN_PULL_NONE); + GpioPinSetInput (0, GPIO_PIN_PB1, GPIO_PIN_INPUT_SCHMITT); + GpioPinSetFunction (0, GPIO_PIN_PB1, 1); + GpioPinSetPull (0, GPIO_PIN_PB2, GPIO_PIN_PULL_NONE); + GpioPinSetInput (0, GPIO_PIN_PB2, GPIO_PIN_INPUT_SCHMITT); + GpioPinSetFunction (0, GPIO_PIN_PB2, 1); + + Status = PmicRead (PMIC_CHIP_NAME, &Value); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_WARN, "Failed to read PMIC chip name! %r\n", Status)); + ASSERT (FALSE); + } + ChipName = (UINT16)Value << 4; + + Status = PmicRead (PMIC_CHIP_VER, &Value); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_WARN, "Failed to read PMIC chip version! %r\n", Status)); + ASSERT (FALSE); + } + ChipName |= (Value >> 4) & 0xF; + ChipVer = Value & 0xF; + + DEBUG ((DEBUG_INFO, "PMIC: Detected RK%03X ver 0x%X\n", ChipName, ChipVer)); + ASSERT (ChipName == 0x809); + + /* Initialize PMIC for HDMI */ + PmicWrite (PMIC_LDO1_ON_VSEL, 0x0c); /* 0.9V - vdda0v9_image */ + PmicWrite (PMIC_LDO2_ON_VSEL, 0x0c); /* 0.9V - vdda_0v9 */ + PmicWrite (PMIC_LDO3_ON_VSEL, 0x0c); /* 0.9V - vdd0v9_pmu */ + PmicWrite (PMIC_LDO4_ON_VSEL, 0x6c); /* 3.3V - vccio_acodec */ + /* Skip LDO5 for now; 1.8V/3.3V - vccio_sd */ + PmicWrite (PMIC_LDO6_ON_VSEL, 0x6c); /* 3.3V - vcc3v3_pmu */ + PmicWrite (PMIC_LDO7_ON_VSEL, 0x30); /* 1.8V - vcca_1v8 */ + PmicWrite (PMIC_LDO8_ON_VSEL, 0x30); /* 1.8V - vcca1v8_pmu */ + PmicWrite (PMIC_LDO9_ON_VSEL, 0x30); /* 1.8V - vcca1v8_image */ + + PmicWrite (PMIC_POWER_EN1, 0xff); /* LDO1, LDO2, LDO3, LDO4 */ + PmicWrite (PMIC_POWER_EN2, 0xee); /* LDO6, LDO7, LDO8 */ + PmicWrite (PMIC_POWER_EN3, 0x55); /* LDO9, SW1*/ +} + +EFI_STATUS +EFIAPI +BoardInitDriverEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + DEBUG ((DEBUG_INFO, "BOARD: BoardInitDriverEntryPoint() called\n")); + + SocSetDomainVoltage (PMUIO2, VCC_3V3); + SocSetDomainVoltage (VCCIO1, VCC_3V3); + SocSetDomainVoltage (VCCIO4, VCC_1V8); + SocSetDomainVoltage (VCCIO5, VCC_3V3); + SocSetDomainVoltage (VCCIO6, VCC_1V8); + SocSetDomainVoltage (VCCIO7, VCC_3V3); + + BoardInitPmic (); + + /* I2C5 bus, used for RTC */ + //GpioPinSetPull (3, GPIO_PIN_PB3, GPIO_PIN_PULL_NONE); + //GpioPinSetInput (3, GPIO_PIN_PB3, GPIO_PIN_INPUT_SCHMITT); + //GpioPinSetFunction (3, GPIO_PIN_PB3, 4); + //GpioPinSetPull (3, GPIO_PIN_PB4, GPIO_PIN_PULL_NONE); + //GpioPinSetInput (3, GPIO_PIN_PB4, GPIO_PIN_INPUT_SCHMITT); + //GpioPinSetFunction (3, GPIO_PIN_PB4, 4); + + /* Set GPIO4 PD2 (SYS_LED) output high to enable LED */ + GpioPinSetDirection (4, GPIO_PIN_PD2, GPIO_PIN_OUTPUT); + GpioPinWrite (4, GPIO_PIN_PD2, TRUE); + + /* Enable automatic clock gating */ + MmioWrite32 (PMU_NOC_AUTO_CON0, 0xFFFFFFFFU); + MmioWrite32 (PMU_NOC_AUTO_CON1, 0x000F000FU); + + /* Set core_pvtpll ring length */ + MmioWrite32 (GRF_CPU_COREPVTPLL_CON0, + ((CORE_PVTPLL_RING_LENGTH_SEL_MASK | CORE_PVTPLL_OSC_EN | CORE_PVTPLL_START) << 16) | + (5U << CORE_PVTPLL_RING_LENGTH_SEL_SHIFT) | CORE_PVTPLL_OSC_EN | CORE_PVTPLL_START); + + /* Configure MULTI-PHY 0 and 1 for USB3 mode */ + MultiPhySetMode (0, MULTIPHY_MODE_USB3); + MultiPhySetMode (1, MULTIPHY_MODE_USB3); + + /* Set GPIO0 PA5 (USB_OTG5V_EN) output high to power USB ports */ + GpioPinSetDirection (0, GPIO_PIN_PA5, GPIO_PIN_OUTPUT); + GpioPinWrite (0, GPIO_PIN_PA5, TRUE); + /* Set GPIO0 PA6 (USB_HOST5V_EN) output high to power USB ports */ + GpioPinSetDirection (0, GPIO_PIN_PA6, GPIO_PIN_OUTPUT); + GpioPinWrite (0, GPIO_PIN_PA6, TRUE); + + /* PCIe setup */ + BoardInitPcie (); + + /* GMAC setup */ + BoardInitGmac (); + + return EFI_SUCCESS; +} diff --git a/edk2-rockchip/Platform/FriendlyElec/NanoPi-R5S/Drivers/BoardInitDxe/BoardInitDxe.inf b/edk2-rockchip/Platform/FriendlyElec/NanoPi-R5S/Drivers/BoardInitDxe/BoardInitDxe.inf new file mode 100644 index 000000000..080e90079 --- /dev/null +++ b/edk2-rockchip/Platform/FriendlyElec/NanoPi-R5S/Drivers/BoardInitDxe/BoardInitDxe.inf @@ -0,0 +1,55 @@ +#/** @file +# +# Board init FriendlyElec NanoPi-R5S platforms +# +# Copyright (c) 2022 Jared McNeill +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = BoardInitDxe + FILE_GUID = D595E3B3-A972-4A6D-94F6-11309E3FA496 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = BoardInitDriverEntryPoint + +[Sources] + BoardInitDxe.c + EthernetPhy.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + ArmPkg/ArmPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + Platform/Rockchip/Rk356x/Rk356x.dec + Silicon/Rockchip/Rk356x/Rk356x.dec + +[LibraryClasses] + ArmLib + UefiBootServicesTableLib + MemoryAllocationLib + BaseMemoryLib + BaseLib + UefiLib + UefiDriverEntryPoint + DebugLib + PrintLib + TimeBaseLib + TimerLib + CruLib + GpioLib + I2cLib + MultiPhyLib + OtpLib + SocLib + Pcie30PhyLib + +[Protocols] + +[Depex] + TRUE diff --git a/edk2-rockchip/Platform/FriendlyElec/NanoPi-R5S/Drivers/BoardInitDxe/EthernetPhy.c b/edk2-rockchip/Platform/FriendlyElec/NanoPi-R5S/Drivers/BoardInitDxe/EthernetPhy.c new file mode 100644 index 000000000..559287a57 --- /dev/null +++ b/edk2-rockchip/Platform/FriendlyElec/NanoPi-R5S/Drivers/BoardInitDxe/EthernetPhy.c @@ -0,0 +1,144 @@ +/** @file + * + * Board init for the ROC-RK3568-PC platform + * + * Copyright (c) 2021-2022, Jared McNeill + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "EthernetPhy.h" + +/* GMAC registers */ +#define GMAC_MAC_MDIO_ADDRESS 0x0200 +#define GMAC_MAC_MDIO_ADDRESS_PA_SHIFT 21 +#define GMAC_MAC_MDIO_ADDRESS_RDA_SHIFT 16 +#define GMAC_MAC_MDIO_ADDRESS_CR_SHIFT 8 +#define GMAC_MAC_MDIO_ADDRESS_CR_100_150 (1U << GMAC_MAC_MDIO_ADDRESS_CR_SHIFT) +#define GMAC_MAC_MDIO_ADDRESS_GOC_SHIFT 2 +#define GMAC_MAC_MDIO_ADDRESS_GOC_READ (3U << GMAC_MAC_MDIO_ADDRESS_GOC_SHIFT) +#define GMAC_MAC_MDIO_ADDRESS_GOC_WRITE (1U << GMAC_MAC_MDIO_ADDRESS_GOC_SHIFT) +#define GMAC_MAC_MDIO_ADDRESS_GB BIT0 +#define GMAC_MAC_MDIO_DATA 0x0204 + +/* MII registers */ +#define MII_PHYIDR1 0x02 +#define MII_PHYIDR2 0x03 + +/* Realtek RTL8211F PHY registers */ +#define PAGSR 0x1F +#define LCR 0x10 +#define LCR_VALUE 0x6940 + +STATIC +VOID +PhyRead ( + IN EFI_PHYSICAL_ADDRESS GmacBase, + IN UINT8 Phy, + IN UINT16 Reg, + OUT UINT16 *Value + ) +{ + UINT32 Addr; + UINTN Retry; + + Addr = GMAC_MAC_MDIO_ADDRESS_CR_100_150 | + (Phy << GMAC_MAC_MDIO_ADDRESS_PA_SHIFT) | + (Reg << GMAC_MAC_MDIO_ADDRESS_RDA_SHIFT) | + GMAC_MAC_MDIO_ADDRESS_GOC_READ | + GMAC_MAC_MDIO_ADDRESS_GB; + MmioWrite32 (GmacBase + GMAC_MAC_MDIO_ADDRESS, Addr); + + MicroSecondDelay (10000); + + for (Retry = 1000; Retry > 0; Retry--) { + Addr = MmioRead32 (GmacBase + GMAC_MAC_MDIO_ADDRESS); + if ((Addr & GMAC_MAC_MDIO_ADDRESS_GB) == 0) { + *Value = MmioRead32 (GmacBase + GMAC_MAC_MDIO_DATA) & 0xFFFFu; + break; + } + MicroSecondDelay (10); + } + if (Retry == 0) { + DEBUG ((DEBUG_WARN, "MDIO: PHY read timeout!\n")); + *Value = 0xFFFFU; + ASSERT (FALSE); + } +} + +STATIC +VOID +PhyWrite ( + IN EFI_PHYSICAL_ADDRESS GmacBase, + IN UINT8 Phy, + IN UINT16 Reg, + IN UINT16 Value + ) +{ + UINT32 Addr; + UINTN Retry; + + MmioWrite32 (GmacBase + GMAC_MAC_MDIO_DATA, Value); + + Addr = GMAC_MAC_MDIO_ADDRESS_CR_100_150 | + (Phy << GMAC_MAC_MDIO_ADDRESS_PA_SHIFT) | + (Reg << GMAC_MAC_MDIO_ADDRESS_RDA_SHIFT) | + GMAC_MAC_MDIO_ADDRESS_GOC_WRITE | + GMAC_MAC_MDIO_ADDRESS_GB; + MmioWrite32 (GmacBase + GMAC_MAC_MDIO_ADDRESS, Addr); + + MicroSecondDelay (10000); + + for (Retry = 1000; Retry > 0; Retry--) { + Addr = MmioRead32 (GmacBase + GMAC_MAC_MDIO_ADDRESS); + if ((Addr & GMAC_MAC_MDIO_ADDRESS_GB) == 0) { + break; + } + MicroSecondDelay (10); + } + if (Retry == 0) { + DEBUG ((DEBUG_WARN, "MDIO: PHY write timeout!\n")); + ASSERT (FALSE); + } +} + +STATIC +VOID +RTL8211FPhyInit ( + IN EFI_PHYSICAL_ADDRESS GmacBase + ) +{ + DEBUG ((DEBUG_INFO, "MDIO: Realtek RTL8211F GbE PHY Init\n")); + PhyWrite (GmacBase, 0, PAGSR, 0xD04); + MicroSecondDelay (10000); + PhyWrite (GmacBase, 0, LCR, LCR_VALUE); + MicroSecondDelay (10000); + PhyWrite (GmacBase, 0, PAGSR, 0); +} + +VOID +EthernetPhyInit ( + IN EFI_PHYSICAL_ADDRESS GmacBase + ) +{ + UINT16 PhyId[2]; + + PhyRead (GmacBase, 0, MII_PHYIDR1, &PhyId[0]); + PhyRead (GmacBase, 0, MII_PHYIDR2, &PhyId[1]); + + if (PhyId[0] == 0x001C && PhyId[1] == 0xC916) { + DEBUG ((DEBUG_INFO, "MDIO: Found Realtek RTL8211F GbE PHY\n")); + RTL8211FPhyInit (GmacBase); + } else { + DEBUG ((DEBUG_INFO, "MDIO: Unknown PHY ID %04X %04X\n", PhyId[0], PhyId[1])); + } +} diff --git a/edk2-rockchip/Platform/FriendlyElec/NanoPi-R5S/Drivers/BoardInitDxe/EthernetPhy.h b/edk2-rockchip/Platform/FriendlyElec/NanoPi-R5S/Drivers/BoardInitDxe/EthernetPhy.h new file mode 100644 index 000000000..22bda2ee0 --- /dev/null +++ b/edk2-rockchip/Platform/FriendlyElec/NanoPi-R5S/Drivers/BoardInitDxe/EthernetPhy.h @@ -0,0 +1,17 @@ +/** @file + * + * Copyright (c) 2022, Jared McNeill + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#ifndef ETHERNETPHY_H__ +#define ETHERNETPHY_H__ + +VOID +EthernetPhyInit ( + IN EFI_PHYSICAL_ADDRESS GmacBase + ); + +#endif /* ETHERNETPHY_H__ */ \ No newline at end of file diff --git a/edk2-rockchip/Platform/FriendlyElec/NanoPi-R5S/NanoPi-R5S.dsc b/edk2-rockchip/Platform/FriendlyElec/NanoPi-R5S/NanoPi-R5S.dsc new file mode 100644 index 000000000..142733632 --- /dev/null +++ b/edk2-rockchip/Platform/FriendlyElec/NanoPi-R5S/NanoPi-R5S.dsc @@ -0,0 +1,741 @@ +# @file +# +# Copyright (c) 2011 - 2020, ARM Limited. All rights reserved. +# Copyright (c) 2014, Linaro Limited. All rights reserved. +# +# Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved. +# Copyright (c) 2017 - 2021, Andrei Warkentin +# Copyright (C) 2021 - 2023, Jared McNeill +# Copyright (c) 2022 - 2023, Sergey Tyuryukanov +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + PLATFORM_NAME = NanoPi-R5S + PLATFORM_GUID = 381B9B4F-A5CD-44E0-B781-CD7036A900F9 + PLATFORM_VERSION = 1.0 + DSC_SPECIFICATION = 0x0001001A + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) + SUPPORTED_ARCHITECTURES = AARCH64 + BUILD_TARGETS = DEBUG|RELEASE|NOOPT + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = Platform/Rockchip/Rk356x/Rk356x.fdf + BOARD_DXE_FV_COMPONENTS = Platform/FriendlyElec/NanoPi-R5S/NanoPi-R5S.fdf.inc + + # + # Defines for default states. These can be changed on the command line. + # -D FLAG=VALUE + # + #DEFINE DEBUG_PRINT_ERROR_LEVEL = 0x8014004F + DEFINE DEBUG_PRINT_ERROR_LEVEL = 0x8000004F + +################################################################################ +# +# Library Class section - list of all Library Classes needed by this Platform. +# +################################################################################ + +!include MdePkg/MdeLibs.dsc.inc + +[LibraryClasses.common] +!if $(TARGET) == RELEASE + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +!else + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +!endif + DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf + + BaseLib|MdePkg/Library/BaseLib/BaseLib.inf + SafeIntLib|MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf + BmpSupportLib|MdeModulePkg/Library/BaseBmpSupportLib/BaseBmpSupportLib.inf + SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf + PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf + ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull/BaseReportStatusCodeLibNull.inf + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf + PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf + IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf + PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf + UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf + CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf + + UefiLib|MdePkg/Library/UefiLib/UefiLib.inf + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf + UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf + DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf + UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf + HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf + UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf + SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf + + UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf + OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib/BaseOrderedCollectionRedBlackTreeLib.inf + + # + # Ramdisk Requirements + # + FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf + + # Allow dynamic PCDs + # + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf + + # use the accelerated BaseMemoryLibOptDxe by default, overrides for SEC/PEI below + BaseMemoryLib|MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf + + # + # It is not possible to prevent the ARM compiler from inserting calls to intrinsic functions. + # This library provides the instrinsic functions such a compiler may generate calls to. + # + NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf + + # Add support for GCC stack protector + NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf + + # ARM Architectural Libraries + CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf + DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf + CpuExceptionHandlerLib|ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf + ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf + ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf + ArmGicArchLib|ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.inf + DmaLib|EmbeddedPkg/Library/NonCoherentDmaLib/NonCoherentDmaLib.inf + TimeBaseLib|EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.inf + ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf + ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf + ArmHvcLib|ArmPkg/Library/ArmHvcLib/ArmHvcLib.inf + ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/ArmGenericTimerPhyCounterLib.inf + + # Rockchip SoC libraries + CpuVoltageLib|Silicon/Rockchip/Rk356x/Library/Tsc4525CpuVoltageLib/CpuVoltageLib.inf + CruLib|Silicon/Rockchip/Rk356x/Library/CruLib/CruLib.inf + GpioLib|Silicon/Rockchip/Rk356x/Library/GpioLib/GpioLib.inf + I2cLib|Silicon/Rockchip/Rk356x/Library/I2cLib/I2cLib.inf + MultiPhyLib|Silicon/Rockchip/Rk356x/Library/MultiPhyLib/MultiPhyLib.inf + OtpLib|Silicon/Rockchip/Rk356x/Library/OtpLib/OtpLib.inf + Pcie30PhyLib|Silicon/Rockchip/Rk356x/Library/Pcie30PhyLib/Pcie30PhyLib.inf + SdramLib|Silicon/Rockchip/Rk356x/Library/SdramLib/SdramLib.inf + SocLib|Silicon/Rockchip/Rk356x/Library/SocLib/SocLib.inf + + # Devices + NonDiscoverableDeviceRegistrationLib|MdeModulePkg/Library/NonDiscoverableDeviceRegistrationLib/NonDiscoverableDeviceRegistrationLib.inf + + # UART + SerialPortLib|MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf + PlatformHookLib|MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.inf + + # Cryptographic libraries + RngLib|MdePkg/Library/DxeRngLib/DxeRngLib.inf + IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf + OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf + TlsLib|CryptoPkg/Library/TlsLib/TlsLib.inf + + # + # Uncomment (and comment out the next line) For RealView Debugger. The Standard IO window + # in the debugger will show load and unload commands for symbols. You can cut and paste this + # into the command window to load symbols. We should be able to use a script to do this, but + # the version of RVD I have does not support scripts accessing system memory. + # + #PeCoffExtraActionLib|ArmPkg/Library/RvdPeCoffExtraActionLib/RvdPeCoffExtraActionLib.inf + PeCoffExtraActionLib|ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.inf + #PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf + + DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf + DebugAgentTimerLib|EmbeddedPkg/Library/DebugAgentTimerLibNull/DebugAgentTimerLibNull.inf + + # Flattened Device Tree (FDT) access library + FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf + + # USB Libraries + UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf + + # SCMI Mailbox Transport Layer + ArmMtlLib|Platform/Rockchip/Rk356x/Library/RkMtlLib/RkMtlLib.inf + + # + # Secure Boot dependencies + # + TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf + AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf + VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf + VariablePolicyLib|MdeModulePkg/Library/VariablePolicyLib/VariablePolicyLib.inf + VariablePolicyHelperLib|MdeModulePkg/Library/VariablePolicyHelperLib/VariablePolicyHelperLib.inf + + # + # PCI support + # + PciSegmentLib|Silicon/Rockchip/Rk356x/Library/Rk356xPciSegmentLib/Rk356xPciSegmentLib.inf + PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf + PciHostBridgeLib|Silicon/Rockchip/Rk356x/Library/Rk356xPciHostBridgeLib/Rk356xPciHostBridgeLib.inf + + # Storage + UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf + +[LibraryClasses.common.SEC] + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + MemoryInitPeiLib|Platform/Rockchip/Rk356x/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf + PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf + ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf + LzmaDecompressLib|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf + PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf + HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf + PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf + MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf + +[LibraryClasses.common.DXE_CORE] + HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf + MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf + DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf + ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf + PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf + +[LibraryClasses.common.DXE_DRIVER] + SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf + VariablePolicyHelperLib|MdeModulePkg/Library/VariablePolicyHelperLib/VariablePolicyHelperLib.inf + +[LibraryClasses.common.UEFI_APPLICATION] + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf + HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf + FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf + +[LibraryClasses.common.UEFI_DRIVER] + ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf + +[LibraryClasses.common.DXE_RUNTIME_DRIVER] + # Runtime debug messages may crash an OS unless serial output to MMIO mapped UARTs is inhibited + DebugLib|MdePkg/Library/DxeRuntimeDebugLibSerialPort/DxeRuntimeDebugLibSerialPort.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf + EfiResetSystemLib|Platform/Rockchip/Rk356x/Library/ResetLib/ResetLib.inf + ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf + VariablePolicyLib|MdeModulePkg/Library/VariablePolicyLib/VariablePolicyLibRuntimeDxe.inf + +################################################################################################### +# BuildOptions Section - Define the module specific tool chain flags that should be used as +# the default flags for a module. These flags are appended to any +# standard flags that are defined by the build process. +################################################################################################### + +[BuildOptions] + GCC:*_*_*_CC_FLAGS = -DRK356X + GCC:*_*_*_PP_FLAGS = -DRK356X + GCC:*_*_*_ASLPP_FLAGS = -DRK356X + GCC:*_*_*_ASLCC_FLAGS = -DRK356X + GCC:*_*_*_VFRPP_FLAGS = -DRK356X + GCC:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG -DNDEBUG + +[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER] + GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x10000 + +################################################################################ +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +################################################################################ + +[PcdsFeatureFlag.common] + # Use the Vector Table location in CpuDxe. We will not copy the Vector Table at PcdCpuVectorBaseAddress + gArmTokenSpaceGuid.PcdRelocateVectorTable|FALSE + + gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE + + ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe. + # It could be set FALSE to save size. + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE + gEfiMdePkgTokenSpaceGuid.PcdUgaConsumeSupport|FALSE + + gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|FALSE + + +[PcdsFixedAtBuild.common] + gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000 + gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000 + gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000 + gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000 + gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF + gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|1 + gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0 + gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320 + + # DEBUG_ASSERT_ENABLED 0x01 + # DEBUG_PRINT_ENABLED 0x02 + # DEBUG_CODE_ENABLED 0x04 + # CLEAR_MEMORY_ENABLED 0x08 + # ASSERT_BREAKPOINT_ENABLED 0x10 + # ASSERT_DEADLOOP_ENABLED 0x20 +!if $(TARGET) == RELEASE + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x21 +!else + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2f +!endif + + # DEBUG_INIT 0x00000001 // Initialization + # DEBUG_WARN 0x00000002 // Warnings + # DEBUG_LOAD 0x00000004 // Load events + # DEBUG_FS 0x00000008 // EFI File system + # DEBUG_POOL 0x00000010 // Alloc & Free (pool) + # DEBUG_PAGE 0x00000020 // Alloc & Free (page) + # DEBUG_INFO 0x00000040 // Informational debug messages + # DEBUG_DISPATCH 0x00000080 // PEI/DXE/SMM Dispatchers + # DEBUG_VARIABLE 0x00000100 // Variable + # DEBUG_BM 0x00000400 // Boot Manager + # DEBUG_BLKIO 0x00001000 // BlkIo Driver + # DEBUG_NET 0x00004000 // SNP Driver + # DEBUG_UNDI 0x00010000 // UNDI Driver + # DEBUG_LOADFILE 0x00020000 // LoadFile + # DEBUG_EVENT 0x00080000 // Event messages + # DEBUG_GCD 0x00100000 // Global Coherency Database changes + # DEBUG_CACHE 0x00200000 // Memory range cachability changes + # DEBUG_VERBOSE 0x00400000 // Detailed debug messages that may + # // significantly impact boot performance + # DEBUG_ERROR 0x80000000 // Error + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|$(DEBUG_PRINT_ERROR_LEVEL) + + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 + + # + # Optional feature to help prevent EFI memory map fragments + # Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob + # Values are in EFI Pages (4K). DXE Core will make sure that + # at least this much of each type of memory can be allocated + # from a single memory range. This way you only end up with + # maximum of two fragments for each type in the memory map + # (the memory used, and the free memory that was prereserved + # but not used). + # + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|300 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|150 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|1000 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|12000 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|20 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0 + +!ifdef $(FIRMWARE_VER) + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"$(FIRMWARE_VER)" +!else + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"EDK2-DEV" +!endif + + # Default platform supported RFC 4646 languages: (American) English + gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultPlatformLangCodes|"en-US" + + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x10000 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x8000 + gEfiMdeModulePkgTokenSpaceGuid.PcdVariableStoreSize|0x10000 + +[LibraryClasses.common] + ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf + ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf + ArmPlatformLib|Platform/Rockchip/Rk356x/Library/PlatformLib/PlatformLib.inf + TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf + UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf + BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf + PlatformBootManagerLib|ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf + CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf + FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf + AcpiLib|EmbeddedPkg/Library/AcpiLib/AcpiLib.inf + +[LibraryClasses.common.UEFI_DRIVER] + +################################################################################ +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +################################################################################ + +[PcdsFeatureFlag.common] + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE + +[PcdsFixedAtBuild.common] + gArmPlatformTokenSpaceGuid.PcdCoreCount|4 + gArmPlatformTokenSpaceGuid.PcdClusterCount|1 + + gArmTokenSpaceGuid.PcdVFPEnabled|1 + + # ARM Architectural Timer Frequency + gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|24000000 + gEmbeddedTokenSpaceGuid.PcdMetronomeTickPeriod|1000 + gEmbeddedTokenSpaceGuid.PcdTimerPeriod|1000 + + gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x4000 + + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxAuthVariableSize|0x2800 + + # Smallest possible memory size + gArmTokenSpaceGuid.PcdSystemMemoryBase|0 + gArmTokenSpaceGuid.PcdSystemMemorySize|0x40000000 + + # Size of the region used by UEFI in permanent memory (Reserved 64MB) + gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x04000000 + + # UART2 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0xFE660000 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate|24000000 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride|4 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterAccessWidth|32 + + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200 + + # + # ARM General Interrupt Controller (GIC600) + # + gArmTokenSpaceGuid.PcdGicDistributorBase|0xFD400000 + gArmTokenSpaceGuid.PcdGicRedistributorsBase|0xFD460000 + gRk356xTokenSpaceGuid.PcdGicPmuIrq0|260 + gRk356xTokenSpaceGuid.PcdGicPmuIrq1|261 + gRk356xTokenSpaceGuid.PcdGicPmuIrq2|262 + gRk356xTokenSpaceGuid.PcdGicPmuIrq3|263 + + ## Default Terminal Type + ## 0-PCANSI, 1-VT100, 2-VT00+, 3-UTF8, 4-TTYTERM + gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4 + + gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 } + + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVendor|L"EDK2" + gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdImageProtectionPolicy|0x3 + gRk356xTokenSpaceGuid.PcdPlatformName|"NanoPi-R5S" + gRk356xTokenSpaceGuid.PcdCpuName|"Rockchip RK3568 (Cortex-A55)" + gRk356xTokenSpaceGuid.PcdPlatformVendorName|"FriendlyElec" + gRk356xTokenSpaceGuid.PcdFamilyName|"NanoPi5" + gRk356xTokenSpaceGuid.PcdProductUrl|"https://wiki.friendlyelec.com/wiki/index.php/NanoPi_R5S" + gRk356xTokenSpaceGuid.PcdMemoryVendorName|"Hynix" + + # + # USB support + # + gRk356xTokenSpaceGuid.PcdOhc0Status|0xF + gRk356xTokenSpaceGuid.PcdOhc1Status|0xF + gRk356xTokenSpaceGuid.PcdEhc0Status|0xF + gRk356xTokenSpaceGuid.PcdEhc1Status|0xF + gRk356xTokenSpaceGuid.PcdXhc0Status|0xF + gRk356xTokenSpaceGuid.PcdXhc1Status|0xF + + # + # Ethernet support + # + gRk356xTokenSpaceGuid.PcdMac0Status|0xF + + # + # PCI support + # + gRk356xTokenSpaceGuid.PcdPcieApbBase|0xFE280000 + gRk356xTokenSpaceGuid.PcdPcieDbiBase|0x00000003C0800000 + + gArmTokenSpaceGuid.PcdPciBusMin|0 + gArmTokenSpaceGuid.PcdPciBusMax|1 + gArmTokenSpaceGuid.PcdPciMmio32Base|0xF0000000 + gArmTokenSpaceGuid.PcdPciMmio32Size|0x02000000 + gArmTokenSpaceGuid.PcdPciMmio64Base|0x0000000390000000 + gArmTokenSpaceGuid.PcdPciMmio64Size|0x000000002FFF0000 + gArmTokenSpaceGuid.PcdPciIoBase|0x0000 + gArmTokenSpaceGuid.PcdPciIoSize|0x10000 + + gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|34 + + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x0000000380000000 + gEfiMdePkgTokenSpaceGuid.PcdPciIoTranslation|0x00000003BFFF0000 + + gRk356xTokenSpaceGuid.PcdPcieNumLanes|0x2 + gRk356xTokenSpaceGuid.PcdPcieLinkSpeed|0x3 + + gRk356xTokenSpaceGuid.PcdPcie30PhyLane0LinkNum|1 + gRk356xTokenSpaceGuid.PcdPcie30PhyLane1LinkNum|1 + + gRk356xTokenSpaceGuid.PcdPcieResetGpioBank|2 + gRk356xTokenSpaceGuid.PcdPcieResetGpioPin|30 + gRk356xTokenSpaceGuid.PcdPciePowerGpioBank|0 + gRk356xTokenSpaceGuid.PcdPciePowerGpioPin|28 + + # + # SD card support + # + gRk356xTokenSpaceGuid.PcdMshcDxePwrEnUsed|TRUE + gRk356xTokenSpaceGuid.PcdMshcDxePwrEnInverted|TRUE + + # + # Limit eMMC to 52 MHz + # + gRk356xTokenSpaceGuid.PcdEmmcForceHighSpeed|TRUE + + # + # RTC support (hym8563 at 0x51 on I2C5) + # + gRk356xTokenSpaceGuid.PcdRtcI2cBusBase|0xFE5E0000 + gRk356xTokenSpaceGuid.PcdRtcI2cAddr|0x51 + +[PcdsDynamicHii.common.DEFAULT] + + # + # Reset-related. + # + gRk356xTokenSpaceGuid.PcdPlatformResetDelay|L"ResetDelay"|gRk356xTokenSpaceGuid|0x0|0 + + # + # ConfigDxe + gRk356xTokenSpaceGuid.PcdSystemTableMode|L"SystemTableMode"|gConfigDxeFormSetGuid|0x0|1 + gRk356xTokenSpaceGuid.PcdCpuClock|L"CpuClock"|gConfigDxeFormSetGuid|0x0|2 + gRk356xTokenSpaceGuid.PcdCustomCpuClock|L"CustomCpuClock"|gConfigDxeFormSetGuid|0x0|816 + + # + # Common UEFI ones. + # + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|5 + +[PcdsDynamicDefault.common] + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0 + + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|1920 + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|1080 + +################################################################################ +# +# Components Section - list of all EDK II Modules needed by this Platform +# +################################################################################ +[Components.common] + # + # PEI Phase modules + # + ArmPlatformPkg/PrePi/PeiUniCore.inf { + + SerialPortLib|MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf + } + + # + # DXE + # + MdeModulePkg/Core/Dxe/DxeMain.inf { + + NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf + } + MdeModulePkg/Universal/PCD/Dxe/Pcd.inf { + + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + } + + # + # Architectural Protocols + # + ArmPkg/Drivers/CpuDxe/CpuDxe.inf + MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + Platform/Rockchip/Rk356x/Drivers/VarBlockServiceDxe/VarBlockServiceDxe.inf + MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf { + + VariableFlashInfoLib|MdeModulePkg/Library/BaseVariableFlashInfoLib/BaseVariableFlashInfoLib.inf + } + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf { + + NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf + VariableFlashInfoLib|MdeModulePkg/Library/BaseVariableFlashInfoLib/BaseVariableFlashInfoLib.inf + } + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf + EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf + EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf { + + RealTimeClockLib|Silicon/Rockchip/Rk356x/Library/Hym8563RtcLib/RtcLib.inf + } + EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + + MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf + MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + MdeModulePkg/Universal/SerialDxe/SerialDxe.inf { + + SerialPortLib|MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf + } + Silicon/Rockchip/Rk356x/Drivers/DisplayDxe/DisplayDxe.inf + EmbeddedPkg/Drivers/ConsolePrefDxe/ConsolePrefDxe.inf + + MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + + ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf + ArmPkg/Drivers/TimerDxe/TimerDxe.inf + MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf + MdeModulePkg/Universal/EbcDxe/EbcDxe.inf + + # + # SCMI Driver + # + ArmPkg/Drivers/ArmScmiDxe/ArmScmiDxe.inf + + # + # Board specific + # + Platform/FriendlyElec/NanoPi-R5S/Drivers/BoardInitDxe/BoardInitDxe.inf + + # + # Config + # + Platform/Rockchip/Rk356x/Drivers/ConfigDxe/ConfigDxe.inf + + # + # FAT filesystem + GPT/MBR partitioning + # + MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + FatPkg/EnhancedFatDxe/Fat.inf + + # + # USB + # + Silicon/Rockchip/Rk356x/Drivers/OhciDxe/OhciDxe.inf + MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf + MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf + MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf + MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf + MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf + Silicon/Rockchip/Rk356x/Drivers/UsbHcdInitDxe/UsbHcd.inf + + # + # SD + # + EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf + Silicon/Rockchip/Rk356x/Drivers/MshcDxe/MshcDxe.inf + + # + # eMMC + # + MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.inf + MdeModulePkg/Bus/Sd/EmmcDxe/EmmcDxe.inf + Silicon/Rockchip/Rk356x/Drivers/EmmcDxe/EmmcDxe.inf + + # + # Devicetree support + # + Platform/Rockchip/Rk356x/Drivers/FdtDxe/FdtDxe.inf + + # + # ACPI Support + # + MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf + MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf + Platform/Rockchip/Rk356x/Drivers/PlatformAcpiDxe/PlatformAcpiDxe.inf + Platform/Rockchip/Rk356x/AcpiTables/$(PLATFORM_NAME).inf + + # + # SMBIOS Support + # + Platform/Rockchip/Rk356x/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf + MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + + # + # PCI Support + # + MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf + MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf + EmbeddedPkg/Drivers/NonCoherentIoMmuDxe/NonCoherentIoMmuDxe.inf + MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf + + # + # AHCI Support + # + MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf + MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf + MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf + MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf + MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf + Silicon/Rockchip/Rk356x/Drivers/SataDxe/SataDxe.inf + + # + # TRNG Support + # + Silicon/Rockchip/Rk356x/Drivers/TrngDxe/TrngDxe.inf + + # + # TS-ADC Support + # + Silicon/Rockchip/Rk356x/Drivers/TsadcDxe/TsadcDxe.inf + + # + # RAM Disk Support + # + MdeModulePkg/Universal/Disk/RamDiskDxe/RamDiskDxe.inf + + # + # Bds + # + MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf + MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + MdeModulePkg/Logo/LogoDxe.inf + + MdeModulePkg/Application/UiApp/UiApp.inf { + + NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf + NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf + NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf + } + + # + # UEFI application (Shell Embedded Boot Loader) + # + ShellPkg/Application/Shell/Shell.inf { + + ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf + NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf + NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf + NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellAcpiViewCommandLib/UefiShellAcpiViewCommandLib.inf + NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf + HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf + NetLib|NetworkPkg/Library/DxeNetLib/DxeNetLib.inf + OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib/BaseOrderedCollectionRedBlackTreeLib.inf + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf + + + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE + gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000 + gEfiShellPkgTokenSpaceGuid.PcdShellFileOperationSize|0x200000 + } diff --git a/edk2-rockchip/Platform/FriendlyElec/NanoPi-R5S/NanoPi-R5S.fdf.inc b/edk2-rockchip/Platform/FriendlyElec/NanoPi-R5S/NanoPi-R5S.fdf.inc new file mode 100644 index 000000000..de74aba5d --- /dev/null +++ b/edk2-rockchip/Platform/FriendlyElec/NanoPi-R5S/NanoPi-R5S.fdf.inc @@ -0,0 +1,35 @@ +# +# Copyright (c) 2021, Jared McNeill +# Copyright (c) 2022, Sergey Tyuryukanov +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +# +# Board specific initialization +# +INF Platform/FriendlyElec/NanoPi-R5S/Drivers/BoardInitDxe/BoardInitDxe.inf + +# +# Devicetree support +# +INF Platform/Rockchip/Rk356x/Drivers/FdtDxe/FdtDxe.inf + +# +# ACPI Support +# +INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf +INF MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf +INF Platform/Rockchip/Rk356x/Drivers/PlatformAcpiDxe/PlatformAcpiDxe.inf +INF RuleOverride = ACPITABLE Platform/Rockchip/Rk356x/AcpiTables/$(PLATFORM_NAME).inf + +# +# SMBIOS Support +# +INF Platform/Rockchip/Rk356x/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf +INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + +# +# TianoCore logo (splash screen) +# +INF MdeModulePkg/Logo/LogoDxe.inf diff --git a/edk2-rockchip/Platform/Rockchip/Rk356x/AcpiTables/NanoPi-R5S.inf b/edk2-rockchip/Platform/Rockchip/Rk356x/AcpiTables/NanoPi-R5S.inf new file mode 100755 index 000000000..c1d0af06e --- /dev/null +++ b/edk2-rockchip/Platform/Rockchip/Rk356x/AcpiTables/NanoPi-R5S.inf @@ -0,0 +1,76 @@ +## @file +# +# ACPI table data and ASL sources required to boot the platform. +# +# Copyright (c) 2021, Jared McNeill +# Copyright (c) 2020, Linaro Ltd. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = Rk356xAcpiTables + FILE_GUID = 0FBE0D20-3528-4F07-838B-9A711C62654F + MODULE_TYPE = USER_DEFINED + VERSION_STRING = 1.0 + +[Sources] + NanoPi-R5S/Dsdt.asl + Dbg2.aslc + Fadt.aslc + Gtdt.aslc + Madt.aslc + Mcfg.aslc + Spcr.aslc + +[Packages] + ArmPlatformPkg/ArmPlatformPkg.dec + ArmPkg/ArmPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Platform/Rockchip/Rk356x/Rk356x.dec + Silicon/Rockchip/Rk356x/Rk356x.dec + +[FixedPcd] + gArmTokenSpaceGuid.PcdGicDistributorBase + gArmTokenSpaceGuid.PcdGicRedistributorsBase + + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum + + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision + + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate + + gRk356xTokenSpaceGuid.PcdOhc0Status + gRk356xTokenSpaceGuid.PcdOhc1Status + gRk356xTokenSpaceGuid.PcdEhc0Status + gRk356xTokenSpaceGuid.PcdEhc1Status + gRk356xTokenSpaceGuid.PcdXhc0Status + gRk356xTokenSpaceGuid.PcdXhc1Status + gRk356xTokenSpaceGuid.PcdMac0Status + gRk356xTokenSpaceGuid.PcdMac1Status + gRk356xTokenSpaceGuid.PcdUart3Status + gRk356xTokenSpaceGuid.PcdUart4Status + + gRk356xTokenSpaceGuid.PcdMshc1Status + gRk356xTokenSpaceGuid.PcdMshc1SdioIrq + gRk356xTokenSpaceGuid.PcdMshc1NonRemovable + gRk356xTokenSpaceGuid.PcdMshc2Status + gRk356xTokenSpaceGuid.PcdMshc2SdioIrq + gRk356xTokenSpaceGuid.PcdMshc2NonRemovable + + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress + +[BuildOptions] + GCC:*_*_*_ASL_FLAGS = -vw3133 -vw3150 diff --git a/edk2-rockchip/Platform/Rockchip/Rk356x/AcpiTables/NanoPi-R5S/Dsdt.asl b/edk2-rockchip/Platform/Rockchip/Rk356x/AcpiTables/NanoPi-R5S/Dsdt.asl new file mode 100755 index 000000000..1f3d590e8 --- /dev/null +++ b/edk2-rockchip/Platform/Rockchip/Rk356x/AcpiTables/NanoPi-R5S/Dsdt.asl @@ -0,0 +1,30 @@ +/** @file +* Differentiated System Description Table Fields (DSDT) for the FriendlyELEC NanoPi-R5S +* +* Copyright (c) 2022, Jared McNeill +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include + +DefinitionBlock ("DsdtTable.aml", "DSDT", + EFI_ACPI_6_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION, + "RKCP ", "RK356X ", FixedPcdGet32 (PcdAcpiDefaultOemRevision)) { + Scope (_SB) { + + include ("Cpu.asl") + include ("Tsadc.asl") + include ("Uart.asl") + include ("Wdt.asl") + include ("Usb2.asl") + include ("Usb3.asl") + include ("Gmac.asl") + include ("Mshc.asl") + include ("Emmc.asl") + //include ("Pcie2x1.asl") + //include ("Pcie3x1.asl") + include ("Pcie3x2.asl") + + } // Scope (_SB) +}