diff --git a/vga.cache/wt/project.wpc b/vga.cache/wt/project.wpc index 693370e..e3636b5 100644 --- a/vga.cache/wt/project.wpc +++ b/vga.cache/wt/project.wpc @@ -1,4 +1,4 @@ version:1 -57656254616c6b5472616e736d697373696f6e417474656d70746564:18 -6d6f64655f636f756e7465727c4755494d6f6465:11 +57656254616c6b5472616e736d697373696f6e417474656d70746564:19 +6d6f64655f636f756e7465727c4755494d6f6465:12 eof: diff --git a/vga.cache/wt/synthesis.wdf b/vga.cache/wt/synthesis.wdf index 71b6b22..88b74f9 100644 --- a/vga.cache/wt/synthesis.wdf +++ b/vga.cache/wt/synthesis.wdf @@ -45,7 +45,7 @@ version:1 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d64656275675f6c6f67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d657374:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 -73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a343273:00:00 -73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:313636312e3735344d42:00:00 -73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:313038332e3633374d42:00:00 -eof:2232251964 +73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30363a313173:00:00 +73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:323539392e3834344d42:00:00 +73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:323032342e3833364d42:00:00 +eof:2561300227 diff --git a/vga.cache/wt/webtalk_pa.xml b/vga.cache/wt/webtalk_pa.xml index fa4da5e..84e29ff 100644 --- a/vga.cache/wt/webtalk_pa.xml +++ b/vga.cache/wt/webtalk_pa.xml @@ -3,10 +3,10 @@ - +
- +
diff --git a/vga.runs/.jobs/vrs_config_68.xml b/vga.runs/.jobs/vrs_config_68.xml new file mode 100644 index 0000000..705f9a9 --- /dev/null +++ b/vga.runs/.jobs/vrs_config_68.xml @@ -0,0 +1,14 @@ + + + + + + + + + + + + + + diff --git a/vga.runs/impl_1/.init_design.begin.rst b/vga.runs/impl_1/.init_design.begin.rst index 5608f3c..a1962d2 100644 --- a/vga.runs/impl_1/.init_design.begin.rst +++ b/vga.runs/impl_1/.init_design.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/vga.runs/impl_1/.opt_design.begin.rst b/vga.runs/impl_1/.opt_design.begin.rst index 5608f3c..a1962d2 100644 --- a/vga.runs/impl_1/.opt_design.begin.rst +++ b/vga.runs/impl_1/.opt_design.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/vga.runs/impl_1/.phys_opt_design.begin.rst b/vga.runs/impl_1/.phys_opt_design.begin.rst index 5608f3c..a1962d2 100644 --- a/vga.runs/impl_1/.phys_opt_design.begin.rst +++ b/vga.runs/impl_1/.phys_opt_design.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/vga.runs/impl_1/.place_design.begin.rst b/vga.runs/impl_1/.place_design.begin.rst index 5608f3c..a1962d2 100644 --- a/vga.runs/impl_1/.place_design.begin.rst +++ b/vga.runs/impl_1/.place_design.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/vga.runs/impl_1/.route_design.begin.rst b/vga.runs/impl_1/.route_design.begin.rst index 5608f3c..a1962d2 100644 --- a/vga.runs/impl_1/.route_design.begin.rst +++ b/vga.runs/impl_1/.route_design.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/vga.runs/impl_1/.vivado.begin.rst b/vga.runs/impl_1/.vivado.begin.rst index 9e34260..aa673a9 100644 --- a/vga.runs/impl_1/.vivado.begin.rst +++ b/vga.runs/impl_1/.vivado.begin.rst @@ -1,30 +1,5 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - + diff --git a/vga.runs/impl_1/.write_bitstream.begin.rst b/vga.runs/impl_1/.write_bitstream.begin.rst index 5608f3c..a1962d2 100644 --- a/vga.runs/impl_1/.write_bitstream.begin.rst +++ b/vga.runs/impl_1/.write_bitstream.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/vga.runs/impl_1/clockInfo.txt b/vga.runs/impl_1/clockInfo.txt index 855efe0..47db5b3 100644 --- a/vga.runs/impl_1/clockInfo.txt +++ b/vga.runs/impl_1/clockInfo.txt @@ -1,6 +1,6 @@ ------------------------------------- | Tool Version : Vivado v.2023.2 -| Date : Thu Apr 18 03:15:20 2024 +| Date : Mon Apr 22 21:23:41 2024 | Host : me | Design : design_1 | Device : xc7a100t-csg324-1-- diff --git a/vga.runs/impl_1/gen_run.xml b/vga.runs/impl_1/gen_run.xml index b17a2e2..46ebd8a 100644 --- a/vga.runs/impl_1/gen_run.xml +++ b/vga.runs/impl_1/gen_run.xml @@ -1,5 +1,5 @@ - + @@ -135,73 +135,71 @@ - + - + - + - + - + - + - + - + - + - - + - @@ -240,9 +238,7 @@ - - Default settings for Implementation. - + diff --git a/vga.runs/impl_1/init_design.pb b/vga.runs/impl_1/init_design.pb index 3fe6916..87ee0cb 100644 Binary files a/vga.runs/impl_1/init_design.pb and b/vga.runs/impl_1/init_design.pb differ diff --git a/vga.runs/impl_1/opt_design.pb b/vga.runs/impl_1/opt_design.pb index 844ef03..45bb1c1 100644 Binary files a/vga.runs/impl_1/opt_design.pb and b/vga.runs/impl_1/opt_design.pb differ diff --git a/vga.runs/impl_1/phys_opt_design.pb b/vga.runs/impl_1/phys_opt_design.pb index 37ccdd4..34e78e1 100644 Binary files a/vga.runs/impl_1/phys_opt_design.pb and b/vga.runs/impl_1/phys_opt_design.pb differ diff --git a/vga.runs/impl_1/place_design.pb b/vga.runs/impl_1/place_design.pb index a28d96b..cf327be 100644 Binary files a/vga.runs/impl_1/place_design.pb and b/vga.runs/impl_1/place_design.pb differ diff --git a/vga.runs/impl_1/route_design.pb b/vga.runs/impl_1/route_design.pb index a6eb6cc..d50bdc6 100644 Binary files a/vga.runs/impl_1/route_design.pb and b/vga.runs/impl_1/route_design.pb differ diff --git a/vga.runs/impl_1/runme.log b/vga.runs/impl_1/runme.log index 2912a76..e253733 100644 --- a/vga.runs/impl_1/runme.log +++ b/vga.runs/impl_1/runme.log @@ -12,157 +12,146 @@ ** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. source vga.tcl -notrace - -*** Running vivado - with args -log vga.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source vga.tcl -notrace - - - -****** Vivado v2023.2 (64-bit) - **** SW Build 4029153 on Fri Oct 13 20:14:34 MDT 2023 - **** IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 - **** SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 - ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. - ** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. - -source vga.tcl -notrace +create_project: Time (s): cpu = 00:00:06 ; elapsed = 00:00:16 . Memory (MB): peak = 564.539 ; gain = 179.887 Command: link_design -top vga -part xc7a100tcsg324-1 Design is defaulting to srcset: sources_1 Design is defaulting to constrset: constrs_1 INFO: [Device 21-403] Loading part xc7a100tcsg324-1 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 978.199 ; gain = 0.000 -INFO: [Netlist 29-17] Analyzing 121 Unisim elements for replacement +Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.301 . Memory (MB): peak = 996.578 ; gain = 0.000 +INFO: [Netlist 29-17] Analyzing 2282 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +WARNING: [Netlist 29-101] Netlist 'vga' is not ideal for floorplanning, since the cellview 'connect4_core_design' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Project 1-479] Netlist was created with Vivado 2023.2 INFO: [Project 1-570] Preparing netlist for logic optimization -Parsing XDC File [C:/Users/james/Documents/vga/vga.srcs/constrs_1/new/vga.xdc] -CRITICAL WARNING: [Common 17-165] Too many positional options when parsing 'period', please type 'create_clock -help' for usage info. [C:/Users/james/Documents/vga/vga.srcs/constrs_1/new/vga.xdc:7] -Finished Parsing XDC File [C:/Users/james/Documents/vga/vga.srcs/constrs_1/new/vga.xdc] +Parsing XDC File [C:/Users/james/Documents/fpga-connect4/vga.srcs/constrs_1/new/vga.xdc] +CRITICAL WARNING: [Common 17-165] Too many positional options when parsing 'period', please type 'create_clock -help' for usage info. [C:/Users/james/Documents/fpga-connect4/vga.srcs/constrs_1/new/vga.xdc:7] +Finished Parsing XDC File [C:/Users/james/Documents/fpga-connect4/vga.srcs/constrs_1/new/vga.xdc] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1102.758 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 1140.879 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. The system cannot find the path specified. -7 Infos, 0 Warnings, 1 Critical Warnings and 0 Errors encountered. +7 Infos, 1 Warnings, 1 Critical Warnings and 0 Errors encountered. link_design completed successfully +link_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:29 . Memory (MB): peak = 1143.879 ; gain = 579.340 Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' Running DRC as a precondition to command opt_design Starting DRC Task -INFO: [DRC 23-27] Running DRC with 20 threads +INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.604 . Memory (MB): peak = 1129.141 ; gain = 21.395 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1162.836 ; gain = 18.957 Starting Cache Timing Information Task INFO: [Timing 38-35] Done setting XDC timing constraints. -Ending Cache Timing Information Task | Checksum: 16679ec0a +Ending Cache Timing Information Task | Checksum: 13016d3f7 -Time (s): cpu = 00:00:02 ; elapsed = 00:00:05 . Memory (MB): peak = 1685.547 ; gain = 556.406 +Time (s): cpu = 00:00:10 ; elapsed = 00:00:16 . Memory (MB): peak = 1721.156 ; gain = 558.320 Starting Logic Optimization Task Phase 1 Initialization Phase 1.1 Core Generation And Design Setup -Phase 1.1 Core Generation And Design Setup | Checksum: 16679ec0a +Phase 1.1 Core Generation And Design Setup | Checksum: 13016d3f7 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2053.059 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 2087.371 ; gain = 0.000 Phase 1.2 Setup Constraints And Sort Netlist -Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 16679ec0a +Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 13016d3f7 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 2053.059 ; gain = 0.000 -Phase 1 Initialization | Checksum: 16679ec0a +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.041 . Memory (MB): peak = 2087.371 ; gain = 0.000 +Phase 1 Initialization | Checksum: 13016d3f7 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 2053.059 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.047 . Memory (MB): peak = 2087.371 ; gain = 0.000 Phase 2 Timer Update And Timing Data Collection Phase 2.1 Timer Update -Phase 2.1 Timer Update | Checksum: 16679ec0a +Phase 2.1 Timer Update | Checksum: 13016d3f7 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 2053.059 ; gain = 0.000 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.931 . Memory (MB): peak = 2087.371 ; gain = 0.000 Phase 2.2 Timing Data Collection -Phase 2.2 Timing Data Collection | Checksum: 16679ec0a +Phase 2.2 Timing Data Collection | Checksum: 13016d3f7 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.016 . Memory (MB): peak = 2053.059 ; gain = 0.000 -Phase 2 Timer Update And Timing Data Collection | Checksum: 16679ec0a +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2087.371 ; gain = 0.000 +Phase 2 Timer Update And Timing Data Collection | Checksum: 13016d3f7 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.016 . Memory (MB): peak = 2053.059 ; gain = 0.000 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2087.371 ; gain = 0.000 Phase 3 Retarget -INFO: [Opt 31-1566] Pulled 1 inverters resulting in an inversion of 3 pins +INFO: [Opt 31-1566] Pulled 130 inverters resulting in an inversion of 700 pins INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). -Phase 3 Retarget | Checksum: b4b20813 +Phase 3 Retarget | Checksum: 20866344c -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.029 . Memory (MB): peak = 2053.059 ; gain = 0.000 -Retarget | Checksum: b4b20813 -INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 1 cells +Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 2087.371 ; gain = 0.000 +Retarget | Checksum: 20866344c +INFO: [Opt 31-389] Phase Retarget created 102 cells and removed 339 cells Phase 4 Constant propagation -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Phase 4 Constant propagation | Checksum: b4b20813 +INFO: [Opt 31-138] Pushed 5 inverter(s) to 17 load pin(s). +Phase 4 Constant propagation | Checksum: 1a0a6e9dc -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.036 . Memory (MB): peak = 2053.059 ; gain = 0.000 -Constant propagation | Checksum: b4b20813 -INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells +Time (s): cpu = 00:00:02 ; elapsed = 00:00:04 . Memory (MB): peak = 2087.371 ; gain = 0.000 +Constant propagation | Checksum: 1a0a6e9dc +INFO: [Opt 31-389] Phase Constant propagation created 411 cells and removed 1297 cells Phase 5 Sweep -Phase 5 Sweep | Checksum: 88dbd75c +Phase 5 Sweep | Checksum: 28ea2516d -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.043 . Memory (MB): peak = 2053.059 ; gain = 0.000 -Sweep | Checksum: 88dbd75c -INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells +Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 2087.371 ; gain = 0.000 +Sweep | Checksum: 28ea2516d +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 1112 cells Phase 6 BUFG optimization INFO: [Opt 31-194] Inserted BUFG lineClk_reg_n_0_BUFG_inst to drive 31 load(s) on clock net lineClk_reg_n_0_BUFG INFO: [Opt 31-193] Inserted 1 BUFG(s) on clock nets -Phase 6 BUFG optimization | Checksum: 105eb5ce4 +Phase 6 BUFG optimization | Checksum: 1b8d12271 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.066 . Memory (MB): peak = 2053.059 ; gain = 0.000 -BUFG optimization | Checksum: 105eb5ce4 +Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 2087.371 ; gain = 0.000 +BUFG optimization | Checksum: 1b8d12271 INFO: [Opt 31-662] Phase BUFG optimization created 1 cells of which 1 are BUFGs and removed 0 cells. Phase 7 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs -Phase 7 Shift Register Optimization | Checksum: 105eb5ce4 +Phase 7 Shift Register Optimization | Checksum: 1b8d12271 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.067 . Memory (MB): peak = 2053.059 ; gain = 0.000 -Shift Register Optimization | Checksum: 105eb5ce4 +Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 2087.371 ; gain = 0.000 +Shift Register Optimization | Checksum: 1b8d12271 INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Phase 8 Post Processing Netlist -Phase 8 Post Processing Netlist | Checksum: 105eb5ce4 +Phase 8 Post Processing Netlist | Checksum: 1b8d12271 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.070 . Memory (MB): peak = 2053.059 ; gain = 0.000 -Post Processing Netlist | Checksum: 105eb5ce4 +Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 2087.371 ; gain = 0.000 +Post Processing Netlist | Checksum: 1b8d12271 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells Phase 9 Finalization Phase 9.1 Finalizing Design Cores and Updating Shapes -Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: d551731e +Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 195354e19 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.097 . Memory (MB): peak = 2053.059 ; gain = 0.000 +Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 2087.371 ; gain = 0.000 Phase 9.2 Verifying Netlist Connectivity Starting Connectivity Check Task -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 2053.059 ; gain = 0.000 -Phase 9.2 Verifying Netlist Connectivity | Checksum: d551731e +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.168 . Memory (MB): peak = 2087.371 ; gain = 0.000 +Phase 9.2 Verifying Netlist Connectivity | Checksum: 195354e19 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.099 . Memory (MB): peak = 2053.059 ; gain = 0.000 -Phase 9 Finalization | Checksum: d551731e +Time (s): cpu = 00:00:04 ; elapsed = 00:00:07 . Memory (MB): peak = 2087.371 ; gain = 0.000 +Phase 9 Finalization | Checksum: 195354e19 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.099 . Memory (MB): peak = 2053.059 ; gain = 0.000 +Time (s): cpu = 00:00:04 ; elapsed = 00:00:07 . Memory (MB): peak = 2087.371 ; gain = 0.000 Opt_design Change Summary ========================= @@ -170,181 +159,182 @@ Opt_design Change Summary ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- -| Retarget | 0 | 1 | 0 | -| Constant propagation | 0 | 0 | 0 | -| Sweep | 0 | 0 | 0 | +| Retarget | 102 | 339 | 0 | +| Constant propagation | 411 | 1297 | 0 | +| Sweep | 0 | 1112 | 0 | | BUFG optimization | 1 | 0 | 0 | | Shift Register Optimization | 0 | 0 | 0 | | Post Processing Netlist | 0 | 0 | 0 | ------------------------------------------------------------------------------------------------------------------------- -Ending Logic Optimization Task | Checksum: d551731e +Ending Logic Optimization Task | Checksum: 195354e19 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.100 . Memory (MB): peak = 2053.059 ; gain = 0.000 +Time (s): cpu = 00:00:04 ; elapsed = 00:00:07 . Memory (MB): peak = 2087.371 ; gain = 0.000 INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8 -Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2053.059 ; gain = 0.000 +Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 2087.371 ; gain = 0.000 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. -Ending Power Optimization Task | Checksum: d551731e +Ending Power Optimization Task | Checksum: 195354e19 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 2053.059 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.062 . Memory (MB): peak = 2087.371 ; gain = 0.000 Starting Final Cleanup Task -Ending Final Cleanup Task | Checksum: d551731e +Ending Final Cleanup Task | Checksum: 195354e19 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2053.059 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 2087.371 ; gain = 0.000 Starting Netlist Obfuscation Task -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2053.059 ; gain = 0.000 -Ending Netlist Obfuscation Task | Checksum: d551731e +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 2087.371 ; gain = 0.000 +Ending Netlist Obfuscation Task | Checksum: 195354e19 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 2053.059 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.021 . Memory (MB): peak = 2087.371 ; gain = 0.000 INFO: [Common 17-83] Releasing license: Implementation -28 Infos, 0 Warnings, 1 Critical Warnings and 0 Errors encountered. +28 Infos, 1 Warnings, 1 Critical Warnings and 0 Errors encountered. opt_design completed successfully -opt_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 2053.059 ; gain = 945.312 +opt_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:32 . Memory (MB): peak = 2087.371 ; gain = 943.492 INFO: [runtcl-4] Executing : report_drc -file vga_drc_opted.rpt -pb vga_drc_opted.pb -rpx vga_drc_opted.rpx Command: report_drc -file vga_drc_opted.rpt -pb vga_drc_opted.pb -rpx vga_drc_opted.rpx INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2023.2/data/ip'. -INFO: [DRC 23-27] Running DRC with 20 threads -INFO: [Vivado_Tcl 2-168] The results of DRC are in file C:/Users/james/Documents/vga/vga.runs/impl_1/vga_drc_opted.rpt. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 2-168] The results of DRC are in file C:/Users/james/Documents/fpga-connect4/vga.runs/impl_1/vga_drc_opted.rpt. report_drc completed successfully +report_drc: Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 2087.371 ; gain = 0.000 INFO: [Timing 38-480] Writing timing data to binary archive. -Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 2053.059 ; gain = 0.000 -Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 2053.059 ; gain = 0.000 -Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 2053.059 ; gain = 0.000 +Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 2087.371 ; gain = 0.000 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 2087.371 ; gain = 0.000 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. -Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 2053.059 ; gain = 0.000 -Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2053.059 ; gain = 0.000 -Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 2053.059 ; gain = 0.000 -Write Physdb Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 2053.059 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/Users/james/Documents/vga/vga.runs/impl_1/vga_opt.dcp' has been generated. +Wrote RouteStorage: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.069 . Memory (MB): peak = 2087.371 ; gain = 0.000 +Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2087.371 ; gain = 0.000 +Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 2087.371 ; gain = 0.000 +Write Physdb Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.098 . Memory (MB): peak = 2087.371 ; gain = 0.000 +Write ShapeDB Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.123 . Memory (MB): peak = 2087.371 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'C:/Users/james/Documents/fpga-connect4/vga.runs/impl_1/vga_opt.dcp' has been generated. Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-83] Releasing license: Implementation -INFO: [DRC 23-27] Running DRC with 20 threads +INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design -INFO: [DRC 23-27] Running DRC with 20 threads +INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. -INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 20 CPUs +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs Starting Placer Task Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2053.059 ; gain = 0.000 -Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 7aedd225 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 2087.371 ; gain = 0.000 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1075f8cec -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2053.059 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2053.059 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.024 . Memory (MB): peak = 2087.371 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 2087.371 ; gain = 0.000 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Timing 38-35] Done setting XDC timing constraints. -Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 11fe61d6a +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 15b9d75d8 -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.544 . Memory (MB): peak = 2053.059 ; gain = 0.000 +Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2087.371 ; gain = 0.000 Phase 1.3 Build Placer Netlist Model -Phase 1.3 Build Placer Netlist Model | Checksum: 15a27be48 +Phase 1.3 Build Placer Netlist Model | Checksum: 18e8513f2 -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.607 . Memory (MB): peak = 2053.059 ; gain = 0.000 +Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2087.371 ; gain = 0.000 Phase 1.4 Constrain Clocks/Macros -Phase 1.4 Constrain Clocks/Macros | Checksum: 15a27be48 +Phase 1.4 Constrain Clocks/Macros | Checksum: 18e8513f2 -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.609 . Memory (MB): peak = 2053.059 ; gain = 0.000 -Phase 1 Placer Initialization | Checksum: 15a27be48 +Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2087.371 ; gain = 0.000 +Phase 1 Placer Initialization | Checksum: 18e8513f2 -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.611 . Memory (MB): peak = 2053.059 ; gain = 0.000 +Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2087.371 ; gain = 0.000 Phase 2 Global Placement Phase 2.1 Floorplanning -Phase 2.1 Floorplanning | Checksum: 15a27be48 +Phase 2.1 Floorplanning | Checksum: 18e8513f2 -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.613 . Memory (MB): peak = 2053.059 ; gain = 0.000 +Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2087.371 ; gain = 0.000 Phase 2.2 Update Timing before SLR Path Opt -Phase 2.2 Update Timing before SLR Path Opt | Checksum: 15a27be48 +Phase 2.2 Update Timing before SLR Path Opt | Checksum: 18e8513f2 -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.614 . Memory (MB): peak = 2053.059 ; gain = 0.000 +Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2087.371 ; gain = 0.000 Phase 2.3 Post-Processing in Floorplanning -Phase 2.3 Post-Processing in Floorplanning | Checksum: 15a27be48 +Phase 2.3 Post-Processing in Floorplanning | Checksum: 18e8513f2 -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.614 . Memory (MB): peak = 2053.059 ; gain = 0.000 +Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2087.371 ; gain = 0.000 Phase 2.4 Global Placement Core WARNING: [Place 46-29] Timing had been disabled during Placer and, therefore, physical synthesis in Placer will be skipped. -Phase 2.4 Global Placement Core | Checksum: 1c54d897d +Phase 2.4 Global Placement Core | Checksum: 2366771d4 -Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2053.059 ; gain = 0.000 -Phase 2 Global Placement | Checksum: 1c54d897d +Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2098.195 ; gain = 10.824 +Phase 2 Global Placement | Checksum: 2366771d4 -Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2053.059 ; gain = 0.000 +Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2098.195 ; gain = 10.824 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros -Phase 3.1 Commit Multi Column Macros | Checksum: 1c54d897d +Phase 3.1 Commit Multi Column Macros | Checksum: 2366771d4 -Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2053.059 ; gain = 0.000 +Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2098.195 ; gain = 10.824 Phase 3.2 Commit Most Macros & LUTRAMs -Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1f802df27 +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 22bdf292e -Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2053.059 ; gain = 0.000 +Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 2098.195 ; gain = 10.824 Phase 3.3 Area Swap Optimization -Phase 3.3 Area Swap Optimization | Checksum: 2483c3c15 +Phase 3.3 Area Swap Optimization | Checksum: 207090e45 -Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2053.059 ; gain = 0.000 +Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2098.195 ; gain = 10.824 Phase 3.4 Pipeline Register Optimization -Phase 3.4 Pipeline Register Optimization | Checksum: 2483c3c15 +Phase 3.4 Pipeline Register Optimization | Checksum: 207090e45 -Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2053.059 ; gain = 0.000 +Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2098.195 ; gain = 10.824 Phase 3.5 Small Shape Detail Placement -Phase 3.5 Small Shape Detail Placement | Checksum: 2018ae0ac +Phase 3.5 Small Shape Detail Placement | Checksum: 126884462 -Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2053.059 ; gain = 0.000 +Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 2098.195 ; gain = 10.824 Phase 3.6 Re-assign LUT pins -Phase 3.6 Re-assign LUT pins | Checksum: 2018ae0ac +Phase 3.6 Re-assign LUT pins | Checksum: 126884462 -Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2053.059 ; gain = 0.000 +Time (s): cpu = 00:00:26 ; elapsed = 00:00:32 . Memory (MB): peak = 2098.195 ; gain = 10.824 Phase 3.7 Pipeline Register Optimization -Phase 3.7 Pipeline Register Optimization | Checksum: 2018ae0ac +Phase 3.7 Pipeline Register Optimization | Checksum: 126884462 -Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2053.059 ; gain = 0.000 -Phase 3 Detail Placement | Checksum: 2018ae0ac +Time (s): cpu = 00:00:26 ; elapsed = 00:00:33 . Memory (MB): peak = 2098.195 ; gain = 10.824 +Phase 3 Detail Placement | Checksum: 126884462 -Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2053.059 ; gain = 0.000 +Time (s): cpu = 00:00:26 ; elapsed = 00:00:33 . Memory (MB): peak = 2098.195 ; gain = 10.824 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization -Phase 4.1 Post Commit Optimization | Checksum: 2018ae0ac +Phase 4.1 Post Commit Optimization | Checksum: 126884462 -Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2053.059 ; gain = 0.000 +Time (s): cpu = 00:00:27 ; elapsed = 00:00:33 . Memory (MB): peak = 2098.195 ; gain = 10.824 Phase 4.2 Post Placement Cleanup -Phase 4.2 Post Placement Cleanup | Checksum: 2018ae0ac +Phase 4.2 Post Placement Cleanup | Checksum: 126884462 -Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2053.059 ; gain = 0.000 +Time (s): cpu = 00:00:27 ; elapsed = 00:00:34 . Memory (MB): peak = 2098.195 ; gain = 10.824 Phase 4.3 Placer Reporting @@ -356,78 +346,80 @@ INFO: [Place 30-612] Post-Placement Estimated Congestion |___________|___________________|___________________| | North| 1x1| 1x1| |___________|___________________|___________________| -| South| 1x1| 1x1| +| South| 1x1| 2x2| |___________|___________________|___________________| | East| 1x1| 1x1| |___________|___________________|___________________| | West| 1x1| 1x1| |___________|___________________|___________________| -Phase 4.3.1 Print Estimated Congestion | Checksum: 2018ae0ac +Phase 4.3.1 Print Estimated Congestion | Checksum: 126884462 -Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2053.059 ; gain = 0.000 -Phase 4.3 Placer Reporting | Checksum: 2018ae0ac +Time (s): cpu = 00:00:27 ; elapsed = 00:00:34 . Memory (MB): peak = 2098.195 ; gain = 10.824 +Phase 4.3 Placer Reporting | Checksum: 126884462 -Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2053.059 ; gain = 0.000 +Time (s): cpu = 00:00:27 ; elapsed = 00:00:34 . Memory (MB): peak = 2098.195 ; gain = 10.824 Phase 4.4 Final Placement Cleanup -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2053.059 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 2098.195 ; gain = 0.000 -Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2053.059 ; gain = 0.000 -Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1b15da112 +Time (s): cpu = 00:00:27 ; elapsed = 00:00:34 . Memory (MB): peak = 2098.195 ; gain = 10.824 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: e5a0d00f -Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2053.059 ; gain = 0.000 -Ending Placer Task | Checksum: 13de07455 +Time (s): cpu = 00:00:28 ; elapsed = 00:00:34 . Memory (MB): peak = 2098.195 ; gain = 10.824 +Ending Placer Task | Checksum: 9fddad01 -Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2053.059 ; gain = 0.000 -47 Infos, 1 Warnings, 1 Critical Warnings and 0 Errors encountered. +Time (s): cpu = 00:00:28 ; elapsed = 00:00:35 . Memory (MB): peak = 2098.195 ; gain = 10.824 +47 Infos, 2 Warnings, 1 Critical Warnings and 0 Errors encountered. place_design completed successfully -place_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2053.059 ; gain = 0.000 +place_design: Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2098.195 ; gain = 10.824 INFO: [runtcl-4] Executing : report_io -file vga_io_placed.rpt -report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.040 . Memory (MB): peak = 2053.059 ; gain = 0.000 +report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.092 . Memory (MB): peak = 2098.195 ; gain = 0.000 INFO: [runtcl-4] Executing : report_utilization -file vga_utilization_placed.rpt -pb vga_utilization_placed.pb INFO: [runtcl-4] Executing : report_control_sets -verbose -file vga_control_sets_placed.rpt -report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 2053.059 ; gain = 0.000 +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.061 . Memory (MB): peak = 2098.195 ; gain = 0.000 INFO: [Timing 38-480] Writing timing data to binary archive. -Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 2065.988 ; gain = 5.977 -Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.064 . Memory (MB): peak = 2065.988 ; gain = 5.965 -Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2065.988 ; gain = 0.000 +Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.126 . Memory (MB): peak = 2104.945 ; gain = 0.934 +Wrote PlaceDB: Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 2104.945 ; gain = 0.000 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2104.945 ; gain = 0.000 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. -Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 2065.988 ; gain = 0.000 -Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 2065.988 ; gain = 0.000 -Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 2065.988 ; gain = 0.000 -Write Physdb Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.085 . Memory (MB): peak = 2065.988 ; gain = 5.977 -INFO: [Common 17-1381] The checkpoint 'C:/Users/james/Documents/vga/vga.runs/impl_1/vga_placed.dcp' has been generated. +Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.066 . Memory (MB): peak = 2104.945 ; gain = 0.000 +Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.080 . Memory (MB): peak = 2104.945 ; gain = 0.000 +Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 2104.945 ; gain = 0.000 +Write Physdb Complete: Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 2104.945 ; gain = 0.934 +INFO: [Common 17-1381] The checkpoint 'C:/Users/james/Documents/fpga-connect4/vga.runs/impl_1/vga_placed.dcp' has been generated. +write_checkpoint: Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 2104.945 ; gain = 6.750 Command: phys_opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' Starting Initial Update Timing Task -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.033 . Memory (MB): peak = 2074.875 ; gain = 8.887 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 2126.109 ; gain = 21.164 INFO: [Vivado_Tcl 4-235] No timing constraint found. The netlist was not modified. INFO: [Common 17-83] Releasing license: Implementation -55 Infos, 1 Warnings, 1 Critical Warnings and 0 Errors encountered. +55 Infos, 2 Warnings, 1 Critical Warnings and 0 Errors encountered. phys_opt_design completed successfully INFO: [Timing 38-480] Writing timing data to binary archive. -Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 2098.730 ; gain = 5.965 -Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.065 . Memory (MB): peak = 2098.738 ; gain = 5.973 -Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2098.738 ; gain = 0.000 +Write ShapeDB Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.150 . Memory (MB): peak = 2151.465 ; gain = 7.066 +Wrote PlaceDB: Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 2151.777 ; gain = 0.312 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2151.777 ; gain = 0.000 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. -Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 2098.738 ; gain = 0.000 -Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 2098.738 ; gain = 0.000 -Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 2098.738 ; gain = 0.000 -Write Physdb Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.091 . Memory (MB): peak = 2098.738 ; gain = 5.973 -INFO: [Common 17-1381] The checkpoint 'C:/Users/james/Documents/vga/vga.runs/impl_1/vga_physopt.dcp' has been generated. +Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.058 . Memory (MB): peak = 2151.777 ; gain = 0.000 +Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.072 . Memory (MB): peak = 2151.777 ; gain = 0.000 +Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 2151.777 ; gain = 0.000 +Write Physdb Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 2151.777 ; gain = 7.379 +INFO: [Common 17-1381] The checkpoint 'C:/Users/james/Documents/fpga-connect4/vga.runs/impl_1/vga_physopt.dcp' has been generated. +write_checkpoint: Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2151.777 ; gain = 25.668 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' Running DRC as a precondition to command route_design -INFO: [DRC 23-27] Running DRC with 20 threads +INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. @@ -436,24 +428,24 @@ Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Phase 1 Build RT Design -Checksum: PlaceDB: ed255003 ConstDB: 0 ShapeSum: 50bb2452 RouteDB: 0 -Post Restoration Checksum: NetGraph: a5b02f1 | NumContArr: 65bf0a03 | Constraints: c2a8fa9d | Timing: c2a8fa9d -Phase 1 Build RT Design | Checksum: 1f56c022e +Checksum: PlaceDB: 1e674953 ConstDB: 0 ShapeSum: 817663ae RouteDB: 0 +Post Restoration Checksum: NetGraph: 45bd39b2 | NumContArr: 85803fac | Constraints: c2a8fa9d | Timing: c2a8fa9d +Phase 1 Build RT Design | Checksum: 2508f6e98 -Time (s): cpu = 00:00:08 ; elapsed = 00:00:20 . Memory (MB): peak = 2205.078 ; gain = 84.922 +Time (s): cpu = 00:00:08 ; elapsed = 00:00:19 . Memory (MB): peak = 2315.918 ; gain = 136.215 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints -Phase 2.1 Fix Topology Constraints | Checksum: 1f56c022e +Phase 2.1 Fix Topology Constraints | Checksum: 2508f6e98 -Time (s): cpu = 00:00:08 ; elapsed = 00:00:20 . Memory (MB): peak = 2236.242 ; gain = 116.086 +Time (s): cpu = 00:00:08 ; elapsed = 00:00:20 . Memory (MB): peak = 2350.602 ; gain = 170.898 Phase 2.2 Pre Route Cleanup -Phase 2.2 Pre Route Cleanup | Checksum: 1f56c022e +Phase 2.2 Pre Route Cleanup | Checksum: 2508f6e98 -Time (s): cpu = 00:00:08 ; elapsed = 00:00:20 . Memory (MB): peak = 2236.242 ; gain = 116.086 +Time (s): cpu = 00:00:08 ; elapsed = 00:00:20 . Memory (MB): peak = 2350.602 ; gain = 170.898 Number of Nodes with overlaps = 0 Router Utilization Summary @@ -462,63 +454,64 @@ Router Utilization Summary Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. - Number of Failed Nets = 1329 + Number of Failed Nets = 21329 (Failed Nets is the sum of unrouted and partially routed nets) - Number of Unrouted Nets = 1329 + Number of Unrouted Nets = 21329 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 -Phase 2 Router Initialization | Checksum: 2fa67463b +Phase 2 Router Initialization | Checksum: 2ae9740a8 -Time (s): cpu = 00:00:08 ; elapsed = 00:00:20 . Memory (MB): peak = 2321.195 ; gain = 201.039 +Time (s): cpu = 00:00:09 ; elapsed = 00:00:20 . Memory (MB): peak = 2443.273 ; gain = 263.570 Phase 3 Initial Routing Phase 3.1 Global Routing -Phase 3.1 Global Routing | Checksum: 2fa67463b +Phase 3.1 Global Routing | Checksum: 2ae9740a8 -Time (s): cpu = 00:00:08 ; elapsed = 00:00:20 . Memory (MB): peak = 2321.195 ; gain = 201.039 +Time (s): cpu = 00:00:09 ; elapsed = 00:00:20 . Memory (MB): peak = 2443.273 ; gain = 263.570 Phase 3.2 Initial Net Routing -Phase 3.2 Initial Net Routing | Checksum: 269db9cbb +Phase 3.2 Initial Net Routing | Checksum: 2592ca907 -Time (s): cpu = 00:00:08 ; elapsed = 00:00:20 . Memory (MB): peak = 2321.195 ; gain = 201.039 -Phase 3 Initial Routing | Checksum: 269db9cbb +Time (s): cpu = 00:00:09 ; elapsed = 00:00:21 . Memory (MB): peak = 2443.273 ; gain = 263.570 +Phase 3 Initial Routing | Checksum: 2592ca907 -Time (s): cpu = 00:00:08 ; elapsed = 00:00:20 . Memory (MB): peak = 2321.195 ; gain = 201.039 +Time (s): cpu = 00:00:09 ; elapsed = 00:00:21 . Memory (MB): peak = 2443.273 ; gain = 263.570 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 - Number of Nodes with overlaps = 96 + Number of Nodes with overlaps = 2487 + Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 -Phase 4.1 Global Iteration 0 | Checksum: 2ac366ad0 +Phase 4.1 Global Iteration 0 | Checksum: 1f67e4b47 -Time (s): cpu = 00:00:08 ; elapsed = 00:00:20 . Memory (MB): peak = 2321.195 ; gain = 201.039 -Phase 4 Rip-up And Reroute | Checksum: 2ac366ad0 +Time (s): cpu = 00:00:11 ; elapsed = 00:00:25 . Memory (MB): peak = 2443.273 ; gain = 263.570 +Phase 4 Rip-up And Reroute | Checksum: 1f67e4b47 -Time (s): cpu = 00:00:08 ; elapsed = 00:00:20 . Memory (MB): peak = 2321.195 ; gain = 201.039 +Time (s): cpu = 00:00:11 ; elapsed = 00:00:25 . Memory (MB): peak = 2443.273 ; gain = 263.570 Phase 5 Delay and Skew Optimization -Phase 5 Delay and Skew Optimization | Checksum: 2ac366ad0 +Phase 5 Delay and Skew Optimization | Checksum: 1f67e4b47 -Time (s): cpu = 00:00:08 ; elapsed = 00:00:20 . Memory (MB): peak = 2321.195 ; gain = 201.039 +Time (s): cpu = 00:00:11 ; elapsed = 00:00:25 . Memory (MB): peak = 2443.273 ; gain = 263.570 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter -Phase 6.1 Hold Fix Iter | Checksum: 2ac366ad0 +Phase 6.1 Hold Fix Iter | Checksum: 1f67e4b47 -Time (s): cpu = 00:00:08 ; elapsed = 00:00:20 . Memory (MB): peak = 2321.195 ; gain = 201.039 -Phase 6 Post Hold Fix | Checksum: 2ac366ad0 +Time (s): cpu = 00:00:11 ; elapsed = 00:00:25 . Memory (MB): peak = 2443.273 ; gain = 263.570 +Phase 6 Post Hold Fix | Checksum: 1f67e4b47 -Time (s): cpu = 00:00:08 ; elapsed = 00:00:20 . Memory (MB): peak = 2321.195 ; gain = 201.039 +Time (s): cpu = 00:00:11 ; elapsed = 00:00:25 . Memory (MB): peak = 2443.273 ; gain = 263.570 Phase 7 Route finalize Router Utilization Summary - Global Vertical Routing Utilization = 0.151804 % - Global Horizontal Routing Utilization = 0.171 % + Global Vertical Routing Utilization = 4.3228 % + Global Horizontal Routing Utilization = 5.41411 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. @@ -532,10 +525,10 @@ Router Utilization Summary --GLOBAL Congestion: Utilization threshold used for congestion level computation: 0.85 Congestion Report -North Dir 1x1 Area, Max Cong = 25.2252%, No Congested Regions. -South Dir 1x1 Area, Max Cong = 18.9189%, No Congested Regions. -East Dir 1x1 Area, Max Cong = 27.9412%, No Congested Regions. -West Dir 1x1 Area, Max Cong = 22.0588%, No Congested Regions. +North Dir 1x1 Area, Max Cong = 59.4595%, No Congested Regions. +South Dir 1x1 Area, Max Cong = 45.9459%, No Congested Regions. +East Dir 1x1 Area, Max Cong = 58.8235%, No Congested Regions. +West Dir 1x1 Area, Max Cong = 52.9412%, No Congested Regions. ------------------------------ Reporting congestion hotspots @@ -557,48 +550,49 @@ Direction: West Congested clusters found at Level 0 Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 -Phase 7 Route finalize | Checksum: 2ac366ad0 +Phase 7 Route finalize | Checksum: 1f67e4b47 -Time (s): cpu = 00:00:08 ; elapsed = 00:00:21 . Memory (MB): peak = 2321.195 ; gain = 201.039 +Time (s): cpu = 00:00:11 ; elapsed = 00:00:25 . Memory (MB): peak = 2443.273 ; gain = 263.570 Phase 8 Verifying routed nets Verification completed successfully -Phase 8 Verifying routed nets | Checksum: 2ac366ad0 +Phase 8 Verifying routed nets | Checksum: 1f67e4b47 -Time (s): cpu = 00:00:08 ; elapsed = 00:00:21 . Memory (MB): peak = 2321.195 ; gain = 201.039 +Time (s): cpu = 00:00:11 ; elapsed = 00:00:25 . Memory (MB): peak = 2443.273 ; gain = 263.570 Phase 9 Depositing Routes -Phase 9 Depositing Routes | Checksum: 2505d48c0 +Phase 9 Depositing Routes | Checksum: 254a9f66c -Time (s): cpu = 00:00:08 ; elapsed = 00:00:21 . Memory (MB): peak = 2321.195 ; gain = 201.039 +Time (s): cpu = 00:00:11 ; elapsed = 00:00:26 . Memory (MB): peak = 2443.273 ; gain = 263.570 INFO: [Route 35-16] Router Completed Successfully Phase 10 Post-Route Event Processing -Phase 10 Post-Route Event Processing | Checksum: 10244244e +Phase 10 Post-Route Event Processing | Checksum: 19f3316b5 -Time (s): cpu = 00:00:08 ; elapsed = 00:00:21 . Memory (MB): peak = 2321.195 ; gain = 201.039 -Ending Routing Task | Checksum: 10244244e +Time (s): cpu = 00:00:11 ; elapsed = 00:00:26 . Memory (MB): peak = 2443.273 ; gain = 263.570 +Ending Routing Task | Checksum: 19f3316b5 -Time (s): cpu = 00:00:08 ; elapsed = 00:00:21 . Memory (MB): peak = 2321.195 ; gain = 201.039 +Time (s): cpu = 00:00:11 ; elapsed = 00:00:27 . Memory (MB): peak = 2443.273 ; gain = 263.570 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation -65 Infos, 1 Warnings, 1 Critical Warnings and 0 Errors encountered. +65 Infos, 2 Warnings, 1 Critical Warnings and 0 Errors encountered. route_design completed successfully -route_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:21 . Memory (MB): peak = 2321.195 ; gain = 222.457 +route_design: Time (s): cpu = 00:00:15 ; elapsed = 00:00:31 . Memory (MB): peak = 2443.273 ; gain = 291.496 INFO: [runtcl-4] Executing : report_drc -file vga_drc_routed.rpt -pb vga_drc_routed.pb -rpx vga_drc_routed.rpx Command: report_drc -file vga_drc_routed.rpt -pb vga_drc_routed.pb -rpx vga_drc_routed.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. -INFO: [DRC 23-27] Running DRC with 20 threads -INFO: [Vivado_Tcl 2-168] The results of DRC are in file C:/Users/james/Documents/vga/vga.runs/impl_1/vga_drc_routed.rpt. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 2-168] The results of DRC are in file C:/Users/james/Documents/fpga-connect4/vga.runs/impl_1/vga_drc_routed.rpt. report_drc completed successfully INFO: [runtcl-4] Executing : report_methodology -file vga_methodology_drc_routed.rpt -pb vga_methodology_drc_routed.pb -rpx vga_methodology_drc_routed.rpx Command: report_methodology -file vga_methodology_drc_routed.rpt -pb vga_methodology_drc_routed.pb -rpx vga_methodology_drc_routed.rpx INFO: [Timing 38-35] Done setting XDC timing constraints. -INFO: [DRC 23-133] Running Methodology with 20 threads -INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file C:/Users/james/Documents/vga/vga.runs/impl_1/vga_methodology_drc_routed.rpt. +INFO: [DRC 23-133] Running Methodology with 2 threads +INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file C:/Users/james/Documents/fpga-connect4/vga.runs/impl_1/vga_methodology_drc_routed.rpt. report_methodology completed successfully +report_methodology: Time (s): cpu = 00:00:03 ; elapsed = 00:00:07 . Memory (MB): peak = 2499.105 ; gain = 55.832 INFO: [runtcl-4] Executing : report_power -file vga_power_routed.rpt -pb vga_power_summary_routed.pb -rpx vga_power_routed.rpx Command: report_power -file vga_power_routed.rpt -pb vga_power_summary_routed.pb -rpx vga_power_routed.rpx INFO: [Timing 38-35] Done setting XDC timing constraints. @@ -607,37 +601,38 @@ Resolution: Please specify clocks using create_clock/create_generated_clock for Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation -75 Infos, 2 Warnings, 1 Critical Warnings and 0 Errors encountered. +75 Infos, 3 Warnings, 1 Critical Warnings and 0 Errors encountered. report_power completed successfully +report_power: Time (s): cpu = 00:00:04 ; elapsed = 00:00:07 . Memory (MB): peak = 2546.715 ; gain = 47.609 INFO: [runtcl-4] Executing : report_route_status -file vga_route_status.rpt -pb vga_route_status.pb INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -report_unconstrained -file vga_timing_summary_routed.rpt -pb vga_timing_summary_routed.pb -rpx vga_timing_summary_routed.rpx -warn_on_violation INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. -INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 20 CPUs +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. INFO: [runtcl-4] Executing : report_incremental_reuse -file vga_incremental_reuse_routed.rpt INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. INFO: [runtcl-4] Executing : report_clock_utilization -file vga_clock_utilization_routed.rpt INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file vga_bus_skew_routed.rpt -pb vga_bus_skew_routed.pb -rpx vga_bus_skew_routed.rpx INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. -INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 20 CPUs +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs INFO: [Timing 38-480] Writing timing data to binary archive. -Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 2485.504 ; gain = 0.000 -Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.063 . Memory (MB): peak = 2485.504 ; gain = 0.000 -Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2485.504 ; gain = 0.000 +Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.040 . Memory (MB): peak = 2571.660 ; gain = 5.945 +Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 2571.660 ; gain = 5.945 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2571.660 ; gain = 0.000 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. -Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.021 . Memory (MB): peak = 2485.504 ; gain = 0.000 -Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 2485.504 ; gain = 0.000 -Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 2485.504 ; gain = 0.000 -Write Physdb Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.092 . Memory (MB): peak = 2485.504 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/Users/james/Documents/vga/vga.runs/impl_1/vga_routed.dcp' has been generated. +Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.184 . Memory (MB): peak = 2571.660 ; gain = 0.000 +Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.026 . Memory (MB): peak = 2571.660 ; gain = 0.000 +Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 2571.660 ; gain = 0.000 +Write Physdb Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 2571.660 ; gain = 5.945 +INFO: [Common 17-1381] The checkpoint 'C:/Users/james/Documents/fpga-connect4/vga.runs/impl_1/vga_routed.dcp' has been generated. Command: write_bitstream -force vga.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' Running DRC as a precondition to command write_bitstream INFO: [IP_Flow 19-1839] IP Catalog is up to date. -INFO: [DRC 23-27] Running DRC with 20 threads +INFO: [DRC 23-27] Running DRC with 2 threads WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: set_property CFGBVS value1 [current_design] @@ -647,9 +642,107 @@ WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Nei #where value2 is the voltage provided to configuration bank 0 Refer to the device configuration user guide for more information. -INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[0][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[0][8]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[0][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[0][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[0][9]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[0][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[10][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[10][8]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[10][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[10][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[10][9]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[10][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[11][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[11][8]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[11][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[11][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[11][9]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[11][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[12][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[12][8]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[12][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[12][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[12][9]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[12][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[13][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[13][8]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[13][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[13][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[13][9]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[13][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[14][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[14][8]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[14][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[14][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[14][9]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[14][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[15][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[15][8]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[15][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[15][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[15][9]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[15][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[16][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[16][8]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[16][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[16][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[16][9]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[16][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[17][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[17][8]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[17][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[17][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[17][9]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[17][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[18][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[18][8]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[18][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[18][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[18][9]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[18][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[19][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[19][8]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[19][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[19][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[19][9]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[19][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[20][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[20][8]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[20][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[20][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[20][9]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[20][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[2][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[2][8]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[2][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[2][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[2][9]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[2][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[3][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[3][8]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[3][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[3][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[3][9]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[3][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[4][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[4][8]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[4][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[4][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[4][9]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[4][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[5][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[5][8]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[5][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[5][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[5][9]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[5][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[6][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[6][8]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[6][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[6][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[6][9]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[6][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[7][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[7][8]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[7][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[7][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[7][9]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[7][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[8][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[8][8]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[8][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[8][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[8][9]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[8][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[9][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[9][8]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[9][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[9][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[9][9]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[9][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[0][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[0][8]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[0][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[0][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[0][9]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[0][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[10][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[10][8]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[10][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[10][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[10][9]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[10][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[11][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[11][8]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[11][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[11][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[11][9]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[11][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[12][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[12][8]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[12][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[12][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[12][9]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[12][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[13][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[13][8]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[13][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[13][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[13][9]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[13][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[14][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[14][8]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[14][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[14][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[14][9]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[14][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[15][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[15][8]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[15][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[15][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[15][9]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[15][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[17][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[17][8]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[17][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[17][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[17][9]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[17][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[18][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[18][8]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[18][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[18][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[18][9]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[18][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[19][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[19][8]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[19][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[19][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[19][9]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[19][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[1][3]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[1][3]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[1][3]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[1][5]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[1][5]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[1][5]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[1][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[1][8]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[1][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[1][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[1][9]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[1][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[20][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[20][8]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[20][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[20][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[20][9]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[20][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[2][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[2][8]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[2][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[2][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[2][9]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[2][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[3][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[3][8]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[3][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[3][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[3][9]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[3][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[4][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[4][8]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[4][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[4][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[4][9]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[4][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[5][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[5][8]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[5][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[5][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[5][9]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[5][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[6][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[6][8]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[6][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[6][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[6][9]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[6][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[7][0]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[7][0]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[7][0]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[7][1]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[7][1]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[7][1]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[7][2]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[7][2]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[7][2]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[7][3]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[7][3]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[7][3]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[7][4]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[7][4]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[7][4]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[7][5]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[7][5]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[7][5]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[7][6]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[7][6]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[7][6]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[7][7]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[7][7]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[7][7]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[7][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[7][8]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[7][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[7][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[7][9]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[7][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[8][0]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[8][0]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[8][0]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[8][1]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[8][1]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[8][1]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[8][2]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[8][2]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[8][2]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[8][3]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[8][3]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[8][3]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[8][4]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[8][4]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[8][4]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[8][5]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[8][5]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[8][5]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[8][6]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[8][6]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[8][6]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[8][7]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[8][7]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[8][7]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[8][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[8][8]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[8][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[8][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[8][9]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[8][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[9][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[9][8]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[9][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[9][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[9][9]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[9][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +INFO: [Vivado 12-3199] DRC finished with 0 Errors, 99 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. -INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. +INFO: [Designutils 20-2272] Running write_bitstream with 2 threads. Loading data files... Loading site data... Loading route data... @@ -660,7 +753,7 @@ Writing bitstream ./vga.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Common 17-83] Releasing license: Implementation -14 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +14 Infos, 99 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully -write_bitstream: Time (s): cpu = 00:00:04 ; elapsed = 00:00:08 . Memory (MB): peak = 2734.930 ; gain = 249.426 -INFO: [Common 17-206] Exiting Vivado at Thu Apr 18 03:15:58 2024... +write_bitstream: Time (s): cpu = 00:00:06 ; elapsed = 00:00:14 . Memory (MB): peak = 3061.438 ; gain = 489.777 +INFO: [Common 17-206] Exiting Vivado at Mon Apr 22 21:25:33 2024... diff --git a/vga.runs/impl_1/runme.sh b/vga.runs/impl_1/runme.sh index dac37bd..6194a8c 100644 --- a/vga.runs/impl_1/runme.sh +++ b/vga.runs/impl_1/runme.sh @@ -25,7 +25,7 @@ else fi export LD_LIBRARY_PATH -HD_PWD='C:/Users/james/Documents/vga/vga.runs/impl_1' +HD_PWD='C:/Users/james/Documents/fpga-connect4/vga.runs/impl_1' cd "$HD_PWD" HD_LOG=runme.log diff --git a/vga.runs/impl_1/vga.bit b/vga.runs/impl_1/vga.bit index c9cfa6a..8a6f72c 100644 Binary files a/vga.runs/impl_1/vga.bit and b/vga.runs/impl_1/vga.bit differ diff --git a/vga.runs/impl_1/vga.tcl b/vga.runs/impl_1/vga.tcl index 532f562..d954dc8 100644 --- a/vga.runs/impl_1/vga.tcl +++ b/vga.runs/impl_1/vga.tcl @@ -17,7 +17,7 @@ proc create_report { reportName command } { } } namespace eval ::optrace { - variable script "C:/Users/james/Documents/vga/vga.runs/impl_1/vga.tcl" + variable script "C:/Users/james/Documents/fpga-connect4/vga.runs/impl_1/vga.tcl" variable category "vivado_impl" } @@ -115,8 +115,6 @@ proc step_failed { step } { OPTRACE "impl_1" END { } } -set_msg_config -id {Synth 8-256} -limit 10000 -set_msg_config -id {Synth 8-638} -limit 10000 OPTRACE "impl_1" START { ROLLUP_1 } OPTRACE "Phase: Init Design" START { ROLLUP_AUTO } @@ -124,11 +122,7 @@ start_step init_design set ACTIVE_STEP init_design set rc [catch { create_msg_db init_design.pb - set_param checkpoint.writeSynthRtdsInDcp 1 - set_param general.maxThreads 20 set_param chipscope.maxJobs 5 - set_param synth.incrementalSynthesisCache C:/Users/james/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-22316-me/incrSyn - set_param xicom.use_bs_reader 1 set_param runs.launchOptions { -jobs 20 } OPTRACE "create in-memory project" START { } create_project -in_memory -part xc7a100tcsg324-1 @@ -136,15 +130,15 @@ OPTRACE "create in-memory project" START { } set_param project.singleFileAddWarning.threshold 0 OPTRACE "create in-memory project" END { } OPTRACE "set parameters" START { } - set_property webtalk.parent_dir C:/Users/james/Documents/vga/vga.cache/wt [current_project] - set_property parent.project_path C:/Users/james/Documents/vga/vga.xpr [current_project] - set_property ip_output_repo C:/Users/james/Documents/vga/vga.cache/ip [current_project] + set_property webtalk.parent_dir C:/Users/james/Documents/fpga-connect4/vga.cache/wt [current_project] + set_property parent.project_path C:/Users/james/Documents/fpga-connect4/vga.xpr [current_project] + set_property ip_output_repo C:/Users/james/Documents/fpga-connect4/vga.cache/ip [current_project] set_property ip_cache_permissions {read write} [current_project] OPTRACE "set parameters" END { } OPTRACE "add files" START { } - add_files -quiet C:/Users/james/Documents/vga/vga.runs/synth_1/vga.dcp + add_files -quiet C:/Users/james/Documents/fpga-connect4/vga.runs/synth_1/vga.dcp OPTRACE "read constraints: implementation" START { } - read_xdc C:/Users/james/Documents/vga/vga.srcs/constrs_1/new/vga.xdc + read_xdc C:/Users/james/Documents/fpga-connect4/vga.srcs/constrs_1/new/vga.xdc OPTRACE "read constraints: implementation" END { } OPTRACE "read constraints: implementation_pre" START { } OPTRACE "read constraints: implementation_pre" END { } diff --git a/vga.runs/impl_1/vga.vdi b/vga.runs/impl_1/vga.vdi index 2547074..6dcd55c 100644 --- a/vga.runs/impl_1/vga.vdi +++ b/vga.runs/impl_1/vga.vdi @@ -3,151 +3,154 @@ # SW Build 4029153 on Fri Oct 13 20:14:34 MDT 2023 # IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 # SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 -# Start of session at: Thu Apr 18 03:14:59 2024 -# Process ID: 43744 -# Current directory: C:/Users/james/Documents/vga/vga.runs/impl_1 +# Start of session at: Mon Apr 22 21:21:53 2024 +# Process ID: 13628 +# Current directory: C:/Users/james/Documents/fpga-connect4/vga.runs/impl_1 # Command line: vivado.exe -log vga.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source vga.tcl -notrace -# Log file: C:/Users/james/Documents/vga/vga.runs/impl_1/vga.vdi -# Journal file: C:/Users/james/Documents/vga/vga.runs/impl_1\vivado.jou +# Log file: C:/Users/james/Documents/fpga-connect4/vga.runs/impl_1/vga.vdi +# Journal file: C:/Users/james/Documents/fpga-connect4/vga.runs/impl_1\vivado.jou # Running On: me, OS: Windows, CPU Frequency: 2918 MHz, CPU Physical cores: 14, Host memory: 34016 MB #----------------------------------------------------------- source vga.tcl -notrace +create_project: Time (s): cpu = 00:00:06 ; elapsed = 00:00:16 . Memory (MB): peak = 564.539 ; gain = 179.887 Command: link_design -top vga -part xc7a100tcsg324-1 Design is defaulting to srcset: sources_1 Design is defaulting to constrset: constrs_1 INFO: [Device 21-403] Loading part xc7a100tcsg324-1 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 978.199 ; gain = 0.000 -INFO: [Netlist 29-17] Analyzing 121 Unisim elements for replacement +Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.301 . Memory (MB): peak = 996.578 ; gain = 0.000 +INFO: [Netlist 29-17] Analyzing 2282 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +WARNING: [Netlist 29-101] Netlist 'vga' is not ideal for floorplanning, since the cellview 'connect4_core_design' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Project 1-479] Netlist was created with Vivado 2023.2 INFO: [Project 1-570] Preparing netlist for logic optimization -Parsing XDC File [C:/Users/james/Documents/vga/vga.srcs/constrs_1/new/vga.xdc] -CRITICAL WARNING: [Common 17-165] Too many positional options when parsing 'period', please type 'create_clock -help' for usage info. [C:/Users/james/Documents/vga/vga.srcs/constrs_1/new/vga.xdc:7] -Finished Parsing XDC File [C:/Users/james/Documents/vga/vga.srcs/constrs_1/new/vga.xdc] +Parsing XDC File [C:/Users/james/Documents/fpga-connect4/vga.srcs/constrs_1/new/vga.xdc] +CRITICAL WARNING: [Common 17-165] Too many positional options when parsing 'period', please type 'create_clock -help' for usage info. [C:/Users/james/Documents/fpga-connect4/vga.srcs/constrs_1/new/vga.xdc:7] +Finished Parsing XDC File [C:/Users/james/Documents/fpga-connect4/vga.srcs/constrs_1/new/vga.xdc] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1102.758 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 1140.879 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. -7 Infos, 0 Warnings, 1 Critical Warnings and 0 Errors encountered. +7 Infos, 1 Warnings, 1 Critical Warnings and 0 Errors encountered. link_design completed successfully +link_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:29 . Memory (MB): peak = 1143.879 ; gain = 579.340 Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' Running DRC as a precondition to command opt_design Starting DRC Task -INFO: [DRC 23-27] Running DRC with 20 threads +INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.604 . Memory (MB): peak = 1129.141 ; gain = 21.395 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1162.836 ; gain = 18.957 Starting Cache Timing Information Task INFO: [Timing 38-35] Done setting XDC timing constraints. -Ending Cache Timing Information Task | Checksum: 16679ec0a +Ending Cache Timing Information Task | Checksum: 13016d3f7 -Time (s): cpu = 00:00:02 ; elapsed = 00:00:05 . Memory (MB): peak = 1685.547 ; gain = 556.406 +Time (s): cpu = 00:00:10 ; elapsed = 00:00:16 . Memory (MB): peak = 1721.156 ; gain = 558.320 Starting Logic Optimization Task Phase 1 Initialization Phase 1.1 Core Generation And Design Setup -Phase 1.1 Core Generation And Design Setup | Checksum: 16679ec0a +Phase 1.1 Core Generation And Design Setup | Checksum: 13016d3f7 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2053.059 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 2087.371 ; gain = 0.000 Phase 1.2 Setup Constraints And Sort Netlist -Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 16679ec0a +Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 13016d3f7 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 2053.059 ; gain = 0.000 -Phase 1 Initialization | Checksum: 16679ec0a +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.041 . Memory (MB): peak = 2087.371 ; gain = 0.000 +Phase 1 Initialization | Checksum: 13016d3f7 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 2053.059 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.047 . Memory (MB): peak = 2087.371 ; gain = 0.000 Phase 2 Timer Update And Timing Data Collection Phase 2.1 Timer Update -Phase 2.1 Timer Update | Checksum: 16679ec0a +Phase 2.1 Timer Update | Checksum: 13016d3f7 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 2053.059 ; gain = 0.000 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.931 . Memory (MB): peak = 2087.371 ; gain = 0.000 Phase 2.2 Timing Data Collection -Phase 2.2 Timing Data Collection | Checksum: 16679ec0a +Phase 2.2 Timing Data Collection | Checksum: 13016d3f7 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.016 . Memory (MB): peak = 2053.059 ; gain = 0.000 -Phase 2 Timer Update And Timing Data Collection | Checksum: 16679ec0a +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2087.371 ; gain = 0.000 +Phase 2 Timer Update And Timing Data Collection | Checksum: 13016d3f7 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.016 . Memory (MB): peak = 2053.059 ; gain = 0.000 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2087.371 ; gain = 0.000 Phase 3 Retarget -INFO: [Opt 31-1566] Pulled 1 inverters resulting in an inversion of 3 pins +INFO: [Opt 31-1566] Pulled 130 inverters resulting in an inversion of 700 pins INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). -Phase 3 Retarget | Checksum: b4b20813 +Phase 3 Retarget | Checksum: 20866344c -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.029 . Memory (MB): peak = 2053.059 ; gain = 0.000 -Retarget | Checksum: b4b20813 -INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 1 cells +Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 2087.371 ; gain = 0.000 +Retarget | Checksum: 20866344c +INFO: [Opt 31-389] Phase Retarget created 102 cells and removed 339 cells Phase 4 Constant propagation -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Phase 4 Constant propagation | Checksum: b4b20813 +INFO: [Opt 31-138] Pushed 5 inverter(s) to 17 load pin(s). +Phase 4 Constant propagation | Checksum: 1a0a6e9dc -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.036 . Memory (MB): peak = 2053.059 ; gain = 0.000 -Constant propagation | Checksum: b4b20813 -INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells +Time (s): cpu = 00:00:02 ; elapsed = 00:00:04 . Memory (MB): peak = 2087.371 ; gain = 0.000 +Constant propagation | Checksum: 1a0a6e9dc +INFO: [Opt 31-389] Phase Constant propagation created 411 cells and removed 1297 cells Phase 5 Sweep -Phase 5 Sweep | Checksum: 88dbd75c +Phase 5 Sweep | Checksum: 28ea2516d -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.043 . Memory (MB): peak = 2053.059 ; gain = 0.000 -Sweep | Checksum: 88dbd75c -INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells +Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 2087.371 ; gain = 0.000 +Sweep | Checksum: 28ea2516d +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 1112 cells Phase 6 BUFG optimization INFO: [Opt 31-194] Inserted BUFG lineClk_reg_n_0_BUFG_inst to drive 31 load(s) on clock net lineClk_reg_n_0_BUFG INFO: [Opt 31-193] Inserted 1 BUFG(s) on clock nets -Phase 6 BUFG optimization | Checksum: 105eb5ce4 +Phase 6 BUFG optimization | Checksum: 1b8d12271 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.066 . Memory (MB): peak = 2053.059 ; gain = 0.000 -BUFG optimization | Checksum: 105eb5ce4 +Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 2087.371 ; gain = 0.000 +BUFG optimization | Checksum: 1b8d12271 INFO: [Opt 31-662] Phase BUFG optimization created 1 cells of which 1 are BUFGs and removed 0 cells. Phase 7 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs -Phase 7 Shift Register Optimization | Checksum: 105eb5ce4 +Phase 7 Shift Register Optimization | Checksum: 1b8d12271 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.067 . Memory (MB): peak = 2053.059 ; gain = 0.000 -Shift Register Optimization | Checksum: 105eb5ce4 +Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 2087.371 ; gain = 0.000 +Shift Register Optimization | Checksum: 1b8d12271 INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Phase 8 Post Processing Netlist -Phase 8 Post Processing Netlist | Checksum: 105eb5ce4 +Phase 8 Post Processing Netlist | Checksum: 1b8d12271 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.070 . Memory (MB): peak = 2053.059 ; gain = 0.000 -Post Processing Netlist | Checksum: 105eb5ce4 +Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 2087.371 ; gain = 0.000 +Post Processing Netlist | Checksum: 1b8d12271 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells Phase 9 Finalization Phase 9.1 Finalizing Design Cores and Updating Shapes -Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: d551731e +Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 195354e19 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.097 . Memory (MB): peak = 2053.059 ; gain = 0.000 +Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 2087.371 ; gain = 0.000 Phase 9.2 Verifying Netlist Connectivity Starting Connectivity Check Task -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 2053.059 ; gain = 0.000 -Phase 9.2 Verifying Netlist Connectivity | Checksum: d551731e +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.168 . Memory (MB): peak = 2087.371 ; gain = 0.000 +Phase 9.2 Verifying Netlist Connectivity | Checksum: 195354e19 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.099 . Memory (MB): peak = 2053.059 ; gain = 0.000 -Phase 9 Finalization | Checksum: d551731e +Time (s): cpu = 00:00:04 ; elapsed = 00:00:07 . Memory (MB): peak = 2087.371 ; gain = 0.000 +Phase 9 Finalization | Checksum: 195354e19 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.099 . Memory (MB): peak = 2053.059 ; gain = 0.000 +Time (s): cpu = 00:00:04 ; elapsed = 00:00:07 . Memory (MB): peak = 2087.371 ; gain = 0.000 Opt_design Change Summary ========================= @@ -155,181 +158,182 @@ Opt_design Change Summary ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- -| Retarget | 0 | 1 | 0 | -| Constant propagation | 0 | 0 | 0 | -| Sweep | 0 | 0 | 0 | +| Retarget | 102 | 339 | 0 | +| Constant propagation | 411 | 1297 | 0 | +| Sweep | 0 | 1112 | 0 | | BUFG optimization | 1 | 0 | 0 | | Shift Register Optimization | 0 | 0 | 0 | | Post Processing Netlist | 0 | 0 | 0 | ------------------------------------------------------------------------------------------------------------------------- -Ending Logic Optimization Task | Checksum: d551731e +Ending Logic Optimization Task | Checksum: 195354e19 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.100 . Memory (MB): peak = 2053.059 ; gain = 0.000 +Time (s): cpu = 00:00:04 ; elapsed = 00:00:07 . Memory (MB): peak = 2087.371 ; gain = 0.000 INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8 -Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2053.059 ; gain = 0.000 +Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 2087.371 ; gain = 0.000 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. -Ending Power Optimization Task | Checksum: d551731e +Ending Power Optimization Task | Checksum: 195354e19 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 2053.059 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.062 . Memory (MB): peak = 2087.371 ; gain = 0.000 Starting Final Cleanup Task -Ending Final Cleanup Task | Checksum: d551731e +Ending Final Cleanup Task | Checksum: 195354e19 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2053.059 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 2087.371 ; gain = 0.000 Starting Netlist Obfuscation Task -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2053.059 ; gain = 0.000 -Ending Netlist Obfuscation Task | Checksum: d551731e +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 2087.371 ; gain = 0.000 +Ending Netlist Obfuscation Task | Checksum: 195354e19 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 2053.059 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.021 . Memory (MB): peak = 2087.371 ; gain = 0.000 INFO: [Common 17-83] Releasing license: Implementation -28 Infos, 0 Warnings, 1 Critical Warnings and 0 Errors encountered. +28 Infos, 1 Warnings, 1 Critical Warnings and 0 Errors encountered. opt_design completed successfully -opt_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 2053.059 ; gain = 945.312 +opt_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:32 . Memory (MB): peak = 2087.371 ; gain = 943.492 INFO: [runtcl-4] Executing : report_drc -file vga_drc_opted.rpt -pb vga_drc_opted.pb -rpx vga_drc_opted.rpx Command: report_drc -file vga_drc_opted.rpt -pb vga_drc_opted.pb -rpx vga_drc_opted.rpx INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2023.2/data/ip'. -INFO: [DRC 23-27] Running DRC with 20 threads -INFO: [Vivado_Tcl 2-168] The results of DRC are in file C:/Users/james/Documents/vga/vga.runs/impl_1/vga_drc_opted.rpt. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 2-168] The results of DRC are in file C:/Users/james/Documents/fpga-connect4/vga.runs/impl_1/vga_drc_opted.rpt. report_drc completed successfully +report_drc: Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 2087.371 ; gain = 0.000 INFO: [Timing 38-480] Writing timing data to binary archive. -Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 2053.059 ; gain = 0.000 -Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 2053.059 ; gain = 0.000 -Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 2053.059 ; gain = 0.000 +Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 2087.371 ; gain = 0.000 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 2087.371 ; gain = 0.000 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. -Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 2053.059 ; gain = 0.000 -Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2053.059 ; gain = 0.000 -Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 2053.059 ; gain = 0.000 -Write Physdb Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 2053.059 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/Users/james/Documents/vga/vga.runs/impl_1/vga_opt.dcp' has been generated. +Wrote RouteStorage: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.069 . Memory (MB): peak = 2087.371 ; gain = 0.000 +Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2087.371 ; gain = 0.000 +Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 2087.371 ; gain = 0.000 +Write Physdb Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.098 . Memory (MB): peak = 2087.371 ; gain = 0.000 +Write ShapeDB Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.123 . Memory (MB): peak = 2087.371 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'C:/Users/james/Documents/fpga-connect4/vga.runs/impl_1/vga_opt.dcp' has been generated. Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-83] Releasing license: Implementation -INFO: [DRC 23-27] Running DRC with 20 threads +INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design -INFO: [DRC 23-27] Running DRC with 20 threads +INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. -INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 20 CPUs +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs Starting Placer Task Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2053.059 ; gain = 0.000 -Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 7aedd225 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 2087.371 ; gain = 0.000 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1075f8cec -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2053.059 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2053.059 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.024 . Memory (MB): peak = 2087.371 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 2087.371 ; gain = 0.000 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Timing 38-35] Done setting XDC timing constraints. -Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 11fe61d6a +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 15b9d75d8 -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.544 . Memory (MB): peak = 2053.059 ; gain = 0.000 +Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2087.371 ; gain = 0.000 Phase 1.3 Build Placer Netlist Model -Phase 1.3 Build Placer Netlist Model | Checksum: 15a27be48 +Phase 1.3 Build Placer Netlist Model | Checksum: 18e8513f2 -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.607 . Memory (MB): peak = 2053.059 ; gain = 0.000 +Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2087.371 ; gain = 0.000 Phase 1.4 Constrain Clocks/Macros -Phase 1.4 Constrain Clocks/Macros | Checksum: 15a27be48 +Phase 1.4 Constrain Clocks/Macros | Checksum: 18e8513f2 -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.609 . Memory (MB): peak = 2053.059 ; gain = 0.000 -Phase 1 Placer Initialization | Checksum: 15a27be48 +Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2087.371 ; gain = 0.000 +Phase 1 Placer Initialization | Checksum: 18e8513f2 -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.611 . Memory (MB): peak = 2053.059 ; gain = 0.000 +Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2087.371 ; gain = 0.000 Phase 2 Global Placement Phase 2.1 Floorplanning -Phase 2.1 Floorplanning | Checksum: 15a27be48 +Phase 2.1 Floorplanning | Checksum: 18e8513f2 -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.613 . Memory (MB): peak = 2053.059 ; gain = 0.000 +Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2087.371 ; gain = 0.000 Phase 2.2 Update Timing before SLR Path Opt -Phase 2.2 Update Timing before SLR Path Opt | Checksum: 15a27be48 +Phase 2.2 Update Timing before SLR Path Opt | Checksum: 18e8513f2 -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.614 . Memory (MB): peak = 2053.059 ; gain = 0.000 +Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2087.371 ; gain = 0.000 Phase 2.3 Post-Processing in Floorplanning -Phase 2.3 Post-Processing in Floorplanning | Checksum: 15a27be48 +Phase 2.3 Post-Processing in Floorplanning | Checksum: 18e8513f2 -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.614 . Memory (MB): peak = 2053.059 ; gain = 0.000 +Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2087.371 ; gain = 0.000 Phase 2.4 Global Placement Core WARNING: [Place 46-29] Timing had been disabled during Placer and, therefore, physical synthesis in Placer will be skipped. -Phase 2.4 Global Placement Core | Checksum: 1c54d897d +Phase 2.4 Global Placement Core | Checksum: 2366771d4 -Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2053.059 ; gain = 0.000 -Phase 2 Global Placement | Checksum: 1c54d897d +Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2098.195 ; gain = 10.824 +Phase 2 Global Placement | Checksum: 2366771d4 -Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2053.059 ; gain = 0.000 +Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2098.195 ; gain = 10.824 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros -Phase 3.1 Commit Multi Column Macros | Checksum: 1c54d897d +Phase 3.1 Commit Multi Column Macros | Checksum: 2366771d4 -Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2053.059 ; gain = 0.000 +Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2098.195 ; gain = 10.824 Phase 3.2 Commit Most Macros & LUTRAMs -Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1f802df27 +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 22bdf292e -Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2053.059 ; gain = 0.000 +Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 2098.195 ; gain = 10.824 Phase 3.3 Area Swap Optimization -Phase 3.3 Area Swap Optimization | Checksum: 2483c3c15 +Phase 3.3 Area Swap Optimization | Checksum: 207090e45 -Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2053.059 ; gain = 0.000 +Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2098.195 ; gain = 10.824 Phase 3.4 Pipeline Register Optimization -Phase 3.4 Pipeline Register Optimization | Checksum: 2483c3c15 +Phase 3.4 Pipeline Register Optimization | Checksum: 207090e45 -Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2053.059 ; gain = 0.000 +Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2098.195 ; gain = 10.824 Phase 3.5 Small Shape Detail Placement -Phase 3.5 Small Shape Detail Placement | Checksum: 2018ae0ac +Phase 3.5 Small Shape Detail Placement | Checksum: 126884462 -Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2053.059 ; gain = 0.000 +Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 2098.195 ; gain = 10.824 Phase 3.6 Re-assign LUT pins -Phase 3.6 Re-assign LUT pins | Checksum: 2018ae0ac +Phase 3.6 Re-assign LUT pins | Checksum: 126884462 -Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2053.059 ; gain = 0.000 +Time (s): cpu = 00:00:26 ; elapsed = 00:00:32 . Memory (MB): peak = 2098.195 ; gain = 10.824 Phase 3.7 Pipeline Register Optimization -Phase 3.7 Pipeline Register Optimization | Checksum: 2018ae0ac +Phase 3.7 Pipeline Register Optimization | Checksum: 126884462 -Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2053.059 ; gain = 0.000 -Phase 3 Detail Placement | Checksum: 2018ae0ac +Time (s): cpu = 00:00:26 ; elapsed = 00:00:33 . Memory (MB): peak = 2098.195 ; gain = 10.824 +Phase 3 Detail Placement | Checksum: 126884462 -Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2053.059 ; gain = 0.000 +Time (s): cpu = 00:00:26 ; elapsed = 00:00:33 . Memory (MB): peak = 2098.195 ; gain = 10.824 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization -Phase 4.1 Post Commit Optimization | Checksum: 2018ae0ac +Phase 4.1 Post Commit Optimization | Checksum: 126884462 -Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2053.059 ; gain = 0.000 +Time (s): cpu = 00:00:27 ; elapsed = 00:00:33 . Memory (MB): peak = 2098.195 ; gain = 10.824 Phase 4.2 Post Placement Cleanup -Phase 4.2 Post Placement Cleanup | Checksum: 2018ae0ac +Phase 4.2 Post Placement Cleanup | Checksum: 126884462 -Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2053.059 ; gain = 0.000 +Time (s): cpu = 00:00:27 ; elapsed = 00:00:34 . Memory (MB): peak = 2098.195 ; gain = 10.824 Phase 4.3 Placer Reporting @@ -341,78 +345,80 @@ INFO: [Place 30-612] Post-Placement Estimated Congestion |___________|___________________|___________________| | North| 1x1| 1x1| |___________|___________________|___________________| -| South| 1x1| 1x1| +| South| 1x1| 2x2| |___________|___________________|___________________| | East| 1x1| 1x1| |___________|___________________|___________________| | West| 1x1| 1x1| |___________|___________________|___________________| -Phase 4.3.1 Print Estimated Congestion | Checksum: 2018ae0ac +Phase 4.3.1 Print Estimated Congestion | Checksum: 126884462 -Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2053.059 ; gain = 0.000 -Phase 4.3 Placer Reporting | Checksum: 2018ae0ac +Time (s): cpu = 00:00:27 ; elapsed = 00:00:34 . Memory (MB): peak = 2098.195 ; gain = 10.824 +Phase 4.3 Placer Reporting | Checksum: 126884462 -Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2053.059 ; gain = 0.000 +Time (s): cpu = 00:00:27 ; elapsed = 00:00:34 . Memory (MB): peak = 2098.195 ; gain = 10.824 Phase 4.4 Final Placement Cleanup -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2053.059 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 2098.195 ; gain = 0.000 -Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2053.059 ; gain = 0.000 -Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1b15da112 +Time (s): cpu = 00:00:27 ; elapsed = 00:00:34 . Memory (MB): peak = 2098.195 ; gain = 10.824 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: e5a0d00f -Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2053.059 ; gain = 0.000 -Ending Placer Task | Checksum: 13de07455 +Time (s): cpu = 00:00:28 ; elapsed = 00:00:34 . Memory (MB): peak = 2098.195 ; gain = 10.824 +Ending Placer Task | Checksum: 9fddad01 -Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2053.059 ; gain = 0.000 -47 Infos, 1 Warnings, 1 Critical Warnings and 0 Errors encountered. +Time (s): cpu = 00:00:28 ; elapsed = 00:00:35 . Memory (MB): peak = 2098.195 ; gain = 10.824 +47 Infos, 2 Warnings, 1 Critical Warnings and 0 Errors encountered. place_design completed successfully -place_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2053.059 ; gain = 0.000 +place_design: Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2098.195 ; gain = 10.824 INFO: [runtcl-4] Executing : report_io -file vga_io_placed.rpt -report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.040 . Memory (MB): peak = 2053.059 ; gain = 0.000 +report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.092 . Memory (MB): peak = 2098.195 ; gain = 0.000 INFO: [runtcl-4] Executing : report_utilization -file vga_utilization_placed.rpt -pb vga_utilization_placed.pb INFO: [runtcl-4] Executing : report_control_sets -verbose -file vga_control_sets_placed.rpt -report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 2053.059 ; gain = 0.000 +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.061 . Memory (MB): peak = 2098.195 ; gain = 0.000 INFO: [Timing 38-480] Writing timing data to binary archive. -Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 2065.988 ; gain = 5.977 -Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.064 . Memory (MB): peak = 2065.988 ; gain = 5.965 -Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2065.988 ; gain = 0.000 +Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.126 . Memory (MB): peak = 2104.945 ; gain = 0.934 +Wrote PlaceDB: Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 2104.945 ; gain = 0.000 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2104.945 ; gain = 0.000 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. -Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 2065.988 ; gain = 0.000 -Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 2065.988 ; gain = 0.000 -Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 2065.988 ; gain = 0.000 -Write Physdb Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.085 . Memory (MB): peak = 2065.988 ; gain = 5.977 -INFO: [Common 17-1381] The checkpoint 'C:/Users/james/Documents/vga/vga.runs/impl_1/vga_placed.dcp' has been generated. +Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.066 . Memory (MB): peak = 2104.945 ; gain = 0.000 +Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.080 . Memory (MB): peak = 2104.945 ; gain = 0.000 +Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 2104.945 ; gain = 0.000 +Write Physdb Complete: Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 2104.945 ; gain = 0.934 +INFO: [Common 17-1381] The checkpoint 'C:/Users/james/Documents/fpga-connect4/vga.runs/impl_1/vga_placed.dcp' has been generated. +write_checkpoint: Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 2104.945 ; gain = 6.750 Command: phys_opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' Starting Initial Update Timing Task -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.033 . Memory (MB): peak = 2074.875 ; gain = 8.887 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 2126.109 ; gain = 21.164 INFO: [Vivado_Tcl 4-235] No timing constraint found. The netlist was not modified. INFO: [Common 17-83] Releasing license: Implementation -55 Infos, 1 Warnings, 1 Critical Warnings and 0 Errors encountered. +55 Infos, 2 Warnings, 1 Critical Warnings and 0 Errors encountered. phys_opt_design completed successfully INFO: [Timing 38-480] Writing timing data to binary archive. -Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 2098.730 ; gain = 5.965 -Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.065 . Memory (MB): peak = 2098.738 ; gain = 5.973 -Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2098.738 ; gain = 0.000 +Write ShapeDB Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.150 . Memory (MB): peak = 2151.465 ; gain = 7.066 +Wrote PlaceDB: Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 2151.777 ; gain = 0.312 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2151.777 ; gain = 0.000 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. -Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 2098.738 ; gain = 0.000 -Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 2098.738 ; gain = 0.000 -Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 2098.738 ; gain = 0.000 -Write Physdb Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.091 . Memory (MB): peak = 2098.738 ; gain = 5.973 -INFO: [Common 17-1381] The checkpoint 'C:/Users/james/Documents/vga/vga.runs/impl_1/vga_physopt.dcp' has been generated. +Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.058 . Memory (MB): peak = 2151.777 ; gain = 0.000 +Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.072 . Memory (MB): peak = 2151.777 ; gain = 0.000 +Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 2151.777 ; gain = 0.000 +Write Physdb Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 2151.777 ; gain = 7.379 +INFO: [Common 17-1381] The checkpoint 'C:/Users/james/Documents/fpga-connect4/vga.runs/impl_1/vga_physopt.dcp' has been generated. +write_checkpoint: Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2151.777 ; gain = 25.668 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' Running DRC as a precondition to command route_design -INFO: [DRC 23-27] Running DRC with 20 threads +INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. @@ -421,24 +427,24 @@ Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Phase 1 Build RT Design -Checksum: PlaceDB: ed255003 ConstDB: 0 ShapeSum: 50bb2452 RouteDB: 0 -Post Restoration Checksum: NetGraph: a5b02f1 | NumContArr: 65bf0a03 | Constraints: c2a8fa9d | Timing: c2a8fa9d -Phase 1 Build RT Design | Checksum: 1f56c022e +Checksum: PlaceDB: 1e674953 ConstDB: 0 ShapeSum: 817663ae RouteDB: 0 +Post Restoration Checksum: NetGraph: 45bd39b2 | NumContArr: 85803fac | Constraints: c2a8fa9d | Timing: c2a8fa9d +Phase 1 Build RT Design | Checksum: 2508f6e98 -Time (s): cpu = 00:00:08 ; elapsed = 00:00:20 . Memory (MB): peak = 2205.078 ; gain = 84.922 +Time (s): cpu = 00:00:08 ; elapsed = 00:00:19 . Memory (MB): peak = 2315.918 ; gain = 136.215 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints -Phase 2.1 Fix Topology Constraints | Checksum: 1f56c022e +Phase 2.1 Fix Topology Constraints | Checksum: 2508f6e98 -Time (s): cpu = 00:00:08 ; elapsed = 00:00:20 . Memory (MB): peak = 2236.242 ; gain = 116.086 +Time (s): cpu = 00:00:08 ; elapsed = 00:00:20 . Memory (MB): peak = 2350.602 ; gain = 170.898 Phase 2.2 Pre Route Cleanup -Phase 2.2 Pre Route Cleanup | Checksum: 1f56c022e +Phase 2.2 Pre Route Cleanup | Checksum: 2508f6e98 -Time (s): cpu = 00:00:08 ; elapsed = 00:00:20 . Memory (MB): peak = 2236.242 ; gain = 116.086 +Time (s): cpu = 00:00:08 ; elapsed = 00:00:20 . Memory (MB): peak = 2350.602 ; gain = 170.898 Number of Nodes with overlaps = 0 Router Utilization Summary @@ -447,63 +453,64 @@ Router Utilization Summary Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. - Number of Failed Nets = 1329 + Number of Failed Nets = 21329 (Failed Nets is the sum of unrouted and partially routed nets) - Number of Unrouted Nets = 1329 + Number of Unrouted Nets = 21329 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 -Phase 2 Router Initialization | Checksum: 2fa67463b +Phase 2 Router Initialization | Checksum: 2ae9740a8 -Time (s): cpu = 00:00:08 ; elapsed = 00:00:20 . Memory (MB): peak = 2321.195 ; gain = 201.039 +Time (s): cpu = 00:00:09 ; elapsed = 00:00:20 . Memory (MB): peak = 2443.273 ; gain = 263.570 Phase 3 Initial Routing Phase 3.1 Global Routing -Phase 3.1 Global Routing | Checksum: 2fa67463b +Phase 3.1 Global Routing | Checksum: 2ae9740a8 -Time (s): cpu = 00:00:08 ; elapsed = 00:00:20 . Memory (MB): peak = 2321.195 ; gain = 201.039 +Time (s): cpu = 00:00:09 ; elapsed = 00:00:20 . Memory (MB): peak = 2443.273 ; gain = 263.570 Phase 3.2 Initial Net Routing -Phase 3.2 Initial Net Routing | Checksum: 269db9cbb +Phase 3.2 Initial Net Routing | Checksum: 2592ca907 -Time (s): cpu = 00:00:08 ; elapsed = 00:00:20 . Memory (MB): peak = 2321.195 ; gain = 201.039 -Phase 3 Initial Routing | Checksum: 269db9cbb +Time (s): cpu = 00:00:09 ; elapsed = 00:00:21 . Memory (MB): peak = 2443.273 ; gain = 263.570 +Phase 3 Initial Routing | Checksum: 2592ca907 -Time (s): cpu = 00:00:08 ; elapsed = 00:00:20 . Memory (MB): peak = 2321.195 ; gain = 201.039 +Time (s): cpu = 00:00:09 ; elapsed = 00:00:21 . Memory (MB): peak = 2443.273 ; gain = 263.570 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 - Number of Nodes with overlaps = 96 + Number of Nodes with overlaps = 2487 + Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 -Phase 4.1 Global Iteration 0 | Checksum: 2ac366ad0 +Phase 4.1 Global Iteration 0 | Checksum: 1f67e4b47 -Time (s): cpu = 00:00:08 ; elapsed = 00:00:20 . Memory (MB): peak = 2321.195 ; gain = 201.039 -Phase 4 Rip-up And Reroute | Checksum: 2ac366ad0 +Time (s): cpu = 00:00:11 ; elapsed = 00:00:25 . Memory (MB): peak = 2443.273 ; gain = 263.570 +Phase 4 Rip-up And Reroute | Checksum: 1f67e4b47 -Time (s): cpu = 00:00:08 ; elapsed = 00:00:20 . Memory (MB): peak = 2321.195 ; gain = 201.039 +Time (s): cpu = 00:00:11 ; elapsed = 00:00:25 . Memory (MB): peak = 2443.273 ; gain = 263.570 Phase 5 Delay and Skew Optimization -Phase 5 Delay and Skew Optimization | Checksum: 2ac366ad0 +Phase 5 Delay and Skew Optimization | Checksum: 1f67e4b47 -Time (s): cpu = 00:00:08 ; elapsed = 00:00:20 . Memory (MB): peak = 2321.195 ; gain = 201.039 +Time (s): cpu = 00:00:11 ; elapsed = 00:00:25 . Memory (MB): peak = 2443.273 ; gain = 263.570 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter -Phase 6.1 Hold Fix Iter | Checksum: 2ac366ad0 +Phase 6.1 Hold Fix Iter | Checksum: 1f67e4b47 -Time (s): cpu = 00:00:08 ; elapsed = 00:00:20 . Memory (MB): peak = 2321.195 ; gain = 201.039 -Phase 6 Post Hold Fix | Checksum: 2ac366ad0 +Time (s): cpu = 00:00:11 ; elapsed = 00:00:25 . Memory (MB): peak = 2443.273 ; gain = 263.570 +Phase 6 Post Hold Fix | Checksum: 1f67e4b47 -Time (s): cpu = 00:00:08 ; elapsed = 00:00:20 . Memory (MB): peak = 2321.195 ; gain = 201.039 +Time (s): cpu = 00:00:11 ; elapsed = 00:00:25 . Memory (MB): peak = 2443.273 ; gain = 263.570 Phase 7 Route finalize Router Utilization Summary - Global Vertical Routing Utilization = 0.151804 % - Global Horizontal Routing Utilization = 0.171 % + Global Vertical Routing Utilization = 4.3228 % + Global Horizontal Routing Utilization = 5.41411 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. @@ -517,10 +524,10 @@ Router Utilization Summary --GLOBAL Congestion: Utilization threshold used for congestion level computation: 0.85 Congestion Report -North Dir 1x1 Area, Max Cong = 25.2252%, No Congested Regions. -South Dir 1x1 Area, Max Cong = 18.9189%, No Congested Regions. -East Dir 1x1 Area, Max Cong = 27.9412%, No Congested Regions. -West Dir 1x1 Area, Max Cong = 22.0588%, No Congested Regions. +North Dir 1x1 Area, Max Cong = 59.4595%, No Congested Regions. +South Dir 1x1 Area, Max Cong = 45.9459%, No Congested Regions. +East Dir 1x1 Area, Max Cong = 58.8235%, No Congested Regions. +West Dir 1x1 Area, Max Cong = 52.9412%, No Congested Regions. ------------------------------ Reporting congestion hotspots @@ -542,48 +549,49 @@ Direction: West Congested clusters found at Level 0 Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 -Phase 7 Route finalize | Checksum: 2ac366ad0 +Phase 7 Route finalize | Checksum: 1f67e4b47 -Time (s): cpu = 00:00:08 ; elapsed = 00:00:21 . Memory (MB): peak = 2321.195 ; gain = 201.039 +Time (s): cpu = 00:00:11 ; elapsed = 00:00:25 . Memory (MB): peak = 2443.273 ; gain = 263.570 Phase 8 Verifying routed nets Verification completed successfully -Phase 8 Verifying routed nets | Checksum: 2ac366ad0 +Phase 8 Verifying routed nets | Checksum: 1f67e4b47 -Time (s): cpu = 00:00:08 ; elapsed = 00:00:21 . Memory (MB): peak = 2321.195 ; gain = 201.039 +Time (s): cpu = 00:00:11 ; elapsed = 00:00:25 . Memory (MB): peak = 2443.273 ; gain = 263.570 Phase 9 Depositing Routes -Phase 9 Depositing Routes | Checksum: 2505d48c0 +Phase 9 Depositing Routes | Checksum: 254a9f66c -Time (s): cpu = 00:00:08 ; elapsed = 00:00:21 . Memory (MB): peak = 2321.195 ; gain = 201.039 +Time (s): cpu = 00:00:11 ; elapsed = 00:00:26 . Memory (MB): peak = 2443.273 ; gain = 263.570 INFO: [Route 35-16] Router Completed Successfully Phase 10 Post-Route Event Processing -Phase 10 Post-Route Event Processing | Checksum: 10244244e +Phase 10 Post-Route Event Processing | Checksum: 19f3316b5 -Time (s): cpu = 00:00:08 ; elapsed = 00:00:21 . Memory (MB): peak = 2321.195 ; gain = 201.039 -Ending Routing Task | Checksum: 10244244e +Time (s): cpu = 00:00:11 ; elapsed = 00:00:26 . Memory (MB): peak = 2443.273 ; gain = 263.570 +Ending Routing Task | Checksum: 19f3316b5 -Time (s): cpu = 00:00:08 ; elapsed = 00:00:21 . Memory (MB): peak = 2321.195 ; gain = 201.039 +Time (s): cpu = 00:00:11 ; elapsed = 00:00:27 . Memory (MB): peak = 2443.273 ; gain = 263.570 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation -65 Infos, 1 Warnings, 1 Critical Warnings and 0 Errors encountered. +65 Infos, 2 Warnings, 1 Critical Warnings and 0 Errors encountered. route_design completed successfully -route_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:21 . Memory (MB): peak = 2321.195 ; gain = 222.457 +route_design: Time (s): cpu = 00:00:15 ; elapsed = 00:00:31 . Memory (MB): peak = 2443.273 ; gain = 291.496 INFO: [runtcl-4] Executing : report_drc -file vga_drc_routed.rpt -pb vga_drc_routed.pb -rpx vga_drc_routed.rpx Command: report_drc -file vga_drc_routed.rpt -pb vga_drc_routed.pb -rpx vga_drc_routed.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. -INFO: [DRC 23-27] Running DRC with 20 threads -INFO: [Vivado_Tcl 2-168] The results of DRC are in file C:/Users/james/Documents/vga/vga.runs/impl_1/vga_drc_routed.rpt. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 2-168] The results of DRC are in file C:/Users/james/Documents/fpga-connect4/vga.runs/impl_1/vga_drc_routed.rpt. report_drc completed successfully INFO: [runtcl-4] Executing : report_methodology -file vga_methodology_drc_routed.rpt -pb vga_methodology_drc_routed.pb -rpx vga_methodology_drc_routed.rpx Command: report_methodology -file vga_methodology_drc_routed.rpt -pb vga_methodology_drc_routed.pb -rpx vga_methodology_drc_routed.rpx INFO: [Timing 38-35] Done setting XDC timing constraints. -INFO: [DRC 23-133] Running Methodology with 20 threads -INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file C:/Users/james/Documents/vga/vga.runs/impl_1/vga_methodology_drc_routed.rpt. +INFO: [DRC 23-133] Running Methodology with 2 threads +INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file C:/Users/james/Documents/fpga-connect4/vga.runs/impl_1/vga_methodology_drc_routed.rpt. report_methodology completed successfully +report_methodology: Time (s): cpu = 00:00:03 ; elapsed = 00:00:07 . Memory (MB): peak = 2499.105 ; gain = 55.832 INFO: [runtcl-4] Executing : report_power -file vga_power_routed.rpt -pb vga_power_summary_routed.pb -rpx vga_power_routed.rpx Command: report_power -file vga_power_routed.rpt -pb vga_power_summary_routed.pb -rpx vga_power_routed.rpx INFO: [Timing 38-35] Done setting XDC timing constraints. @@ -592,37 +600,38 @@ Resolution: Please specify clocks using create_clock/create_generated_clock for Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation -75 Infos, 2 Warnings, 1 Critical Warnings and 0 Errors encountered. +75 Infos, 3 Warnings, 1 Critical Warnings and 0 Errors encountered. report_power completed successfully +report_power: Time (s): cpu = 00:00:04 ; elapsed = 00:00:07 . Memory (MB): peak = 2546.715 ; gain = 47.609 INFO: [runtcl-4] Executing : report_route_status -file vga_route_status.rpt -pb vga_route_status.pb INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -report_unconstrained -file vga_timing_summary_routed.rpt -pb vga_timing_summary_routed.pb -rpx vga_timing_summary_routed.rpx -warn_on_violation INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. -INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 20 CPUs +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. INFO: [runtcl-4] Executing : report_incremental_reuse -file vga_incremental_reuse_routed.rpt INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. INFO: [runtcl-4] Executing : report_clock_utilization -file vga_clock_utilization_routed.rpt INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file vga_bus_skew_routed.rpt -pb vga_bus_skew_routed.pb -rpx vga_bus_skew_routed.rpx INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. -INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 20 CPUs +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs INFO: [Timing 38-480] Writing timing data to binary archive. -Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 2485.504 ; gain = 0.000 -Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.063 . Memory (MB): peak = 2485.504 ; gain = 0.000 -Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2485.504 ; gain = 0.000 +Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.040 . Memory (MB): peak = 2571.660 ; gain = 5.945 +Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 2571.660 ; gain = 5.945 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2571.660 ; gain = 0.000 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. -Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.021 . Memory (MB): peak = 2485.504 ; gain = 0.000 -Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 2485.504 ; gain = 0.000 -Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 2485.504 ; gain = 0.000 -Write Physdb Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.092 . Memory (MB): peak = 2485.504 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/Users/james/Documents/vga/vga.runs/impl_1/vga_routed.dcp' has been generated. +Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.184 . Memory (MB): peak = 2571.660 ; gain = 0.000 +Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.026 . Memory (MB): peak = 2571.660 ; gain = 0.000 +Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 2571.660 ; gain = 0.000 +Write Physdb Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 2571.660 ; gain = 5.945 +INFO: [Common 17-1381] The checkpoint 'C:/Users/james/Documents/fpga-connect4/vga.runs/impl_1/vga_routed.dcp' has been generated. Command: write_bitstream -force vga.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' Running DRC as a precondition to command write_bitstream INFO: [IP_Flow 19-1839] IP Catalog is up to date. -INFO: [DRC 23-27] Running DRC with 20 threads +INFO: [DRC 23-27] Running DRC with 2 threads WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: set_property CFGBVS value1 [current_design] @@ -632,9 +641,107 @@ WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Nei #where value2 is the voltage provided to configuration bank 0 Refer to the device configuration user guide for more information. -INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[0][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[0][8]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[0][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[0][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[0][9]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[0][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[10][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[10][8]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[10][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[10][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[10][9]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[10][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[11][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[11][8]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[11][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[11][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[11][9]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[11][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[12][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[12][8]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[12][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[12][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[12][9]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[12][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[13][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[13][8]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[13][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[13][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[13][9]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[13][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[14][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[14][8]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[14][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[14][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[14][9]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[14][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[15][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[15][8]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[15][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[15][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[15][9]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[15][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[16][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[16][8]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[16][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[16][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[16][9]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[16][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[17][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[17][8]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[17][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[17][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[17][9]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[17][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[18][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[18][8]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[18][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[18][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[18][9]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[18][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[19][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[19][8]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[19][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[19][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[19][9]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[19][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[20][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[20][8]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[20][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[20][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[20][9]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[20][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[2][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[2][8]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[2][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[2][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[2][9]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[2][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[3][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[3][8]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[3][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[3][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[3][9]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[3][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[4][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[4][8]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[4][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[4][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[4][9]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[4][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[5][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[5][8]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[5][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[5][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[5][9]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[5][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[6][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[6][8]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[6][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[6][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[6][9]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[6][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[7][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[7][8]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[7][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[7][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[7][9]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[7][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[8][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[8][8]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[8][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[8][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[8][9]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[8][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[9][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[9][8]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[9][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/redPieceYOffset_reg[9][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[9][9]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[9][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[0][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[0][8]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[0][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[0][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[0][9]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[0][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[10][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[10][8]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[10][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[10][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[10][9]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[10][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[11][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[11][8]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[11][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[11][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[11][9]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[11][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[12][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[12][8]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[12][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[12][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[12][9]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[12][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[13][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[13][8]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[13][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[13][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[13][9]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[13][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[14][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[14][8]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[14][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[14][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[14][9]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[14][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[15][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[15][8]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[15][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[15][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[15][9]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[15][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[17][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[17][8]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[17][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[17][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[17][9]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[17][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[18][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[18][8]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[18][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[18][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[18][9]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[18][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[19][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[19][8]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[19][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[19][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[19][9]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[19][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[1][3]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[1][3]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[1][3]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[1][5]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[1][5]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[1][5]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[1][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[1][8]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[1][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[1][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[1][9]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[1][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[20][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[20][8]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[20][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[20][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[20][9]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[20][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[2][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[2][8]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[2][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[2][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[2][9]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[2][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[3][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[3][8]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[3][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[3][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[3][9]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[3][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[4][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[4][8]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[4][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[4][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[4][9]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[4][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[5][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[5][8]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[5][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[5][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[5][9]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[5][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[6][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[6][8]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[6][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[6][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[6][9]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[6][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[7][0]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[7][0]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[7][0]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[7][1]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[7][1]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[7][1]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[7][2]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[7][2]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[7][2]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[7][3]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[7][3]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[7][3]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[7][4]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[7][4]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[7][4]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[7][5]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[7][5]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[7][5]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[7][6]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[7][6]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[7][6]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[7][7]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[7][7]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[7][7]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[7][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[7][8]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[7][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[7][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[7][9]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[7][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[8][0]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[8][0]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[8][0]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[8][1]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[8][1]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[8][1]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[8][2]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[8][2]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[8][2]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[8][3]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[8][3]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[8][3]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[8][4]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[8][4]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[8][4]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[8][5]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[8][5]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[8][5]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[8][6]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[8][6]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[8][6]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[8][7]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[8][7]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[8][7]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[8][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[8][8]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[8][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[8][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[8][9]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[8][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[9][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[9][8]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[9][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net core_design/yellowPieceYOffset_reg[9][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[9][9]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[9][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +INFO: [Vivado 12-3199] DRC finished with 0 Errors, 99 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. -INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. +INFO: [Designutils 20-2272] Running write_bitstream with 2 threads. Loading data files... Loading site data... Loading route data... @@ -645,7 +752,7 @@ Writing bitstream ./vga.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Common 17-83] Releasing license: Implementation -14 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +14 Infos, 99 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully -write_bitstream: Time (s): cpu = 00:00:04 ; elapsed = 00:00:08 . Memory (MB): peak = 2734.930 ; gain = 249.426 -INFO: [Common 17-206] Exiting Vivado at Thu Apr 18 03:15:58 2024... +write_bitstream: Time (s): cpu = 00:00:06 ; elapsed = 00:00:14 . Memory (MB): peak = 3061.438 ; gain = 489.777 +INFO: [Common 17-206] Exiting Vivado at Mon Apr 22 21:25:33 2024... diff --git a/vga.runs/impl_1/vga_20064.backup.vdi b/vga.runs/impl_1/vga_20064.backup.vdi deleted file mode 100644 index fd9ddb4..0000000 --- a/vga.runs/impl_1/vga_20064.backup.vdi +++ /dev/null @@ -1,619 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2023.2 (64-bit) -# SW Build 4029153 on Fri Oct 13 20:14:34 MDT 2023 -# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 -# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 -# Start of session at: Thu Apr 18 02:49:21 2024 -# Process ID: 20064 -# Current directory: C:/Users/james/Documents/vga/vga.runs/impl_1 -# Command line: vivado.exe -log vga.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source vga.tcl -notrace -# Log file: C:/Users/james/Documents/vga/vga.runs/impl_1/vga.vdi -# Journal file: C:/Users/james/Documents/vga/vga.runs/impl_1\vivado.jou -# Running On: me, OS: Windows, CPU Frequency: 2918 MHz, CPU Physical cores: 14, Host memory: 34016 MB -#----------------------------------------------------------- -source vga.tcl -notrace -Command: link_design -top vga -part xc7a100tcsg324-1 -Design is defaulting to srcset: sources_1 -Design is defaulting to constrset: constrs_1 -INFO: [Device 21-403] Loading part xc7a100tcsg324-1 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 978.465 ; gain = 0.000 -INFO: [Netlist 29-17] Analyzing 349 Unisim elements for replacement -INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds -INFO: [Project 1-479] Netlist was created with Vivado 2023.2 -INFO: [Project 1-570] Preparing netlist for logic optimization -Parsing XDC File [C:/Users/james/Documents/vga/vga.srcs/constrs_1/new/vga.xdc] -CRITICAL WARNING: [Common 17-165] Too many positional options when parsing 'period', please type 'create_clock -help' for usage info. [C:/Users/james/Documents/vga/vga.srcs/constrs_1/new/vga.xdc:7] -Finished Parsing XDC File [C:/Users/james/Documents/vga/vga.srcs/constrs_1/new/vga.xdc] -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1104.617 ; gain = 0.000 -INFO: [Project 1-111] Unisim Transformation Summary: -No Unisim elements were transformed. - -7 Infos, 0 Warnings, 1 Critical Warnings and 0 Errors encountered. -link_design completed successfully -Command: opt_design -Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' -Running DRC as a precondition to command opt_design - -Starting DRC Task -INFO: [DRC 23-27] Running DRC with 20 threads -INFO: [Project 1-461] DRC finished with 0 Errors -INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.640 . Memory (MB): peak = 1131.289 ; gain = 22.684 - -Starting Cache Timing Information Task -INFO: [Timing 38-35] Done setting XDC timing constraints. -Ending Cache Timing Information Task | Checksum: 1cea5469c - -Time (s): cpu = 00:00:03 ; elapsed = 00:00:06 . Memory (MB): peak = 1686.711 ; gain = 555.422 - -Starting Logic Optimization Task - -Phase 1 Initialization - -Phase 1.1 Core Generation And Design Setup -Phase 1.1 Core Generation And Design Setup | Checksum: 1cea5469c - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 2052.297 ; gain = 0.000 - -Phase 1.2 Setup Constraints And Sort Netlist -Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 1cea5469c - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 2052.297 ; gain = 0.000 -Phase 1 Initialization | Checksum: 1cea5469c - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 2052.297 ; gain = 0.000 - -Phase 2 Timer Update And Timing Data Collection - -Phase 2.1 Timer Update -Phase 2.1 Timer Update | Checksum: 1cea5469c - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.019 . Memory (MB): peak = 2052.297 ; gain = 0.000 - -Phase 2.2 Timing Data Collection -Phase 2.2 Timing Data Collection | Checksum: 1cea5469c - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.028 . Memory (MB): peak = 2052.297 ; gain = 0.000 -Phase 2 Timer Update And Timing Data Collection | Checksum: 1cea5469c - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.028 . Memory (MB): peak = 2052.297 ; gain = 0.000 - -Phase 3 Retarget -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -INFO: [Opt 31-49] Retargeted 0 cell(s). -Phase 3 Retarget | Checksum: 1cea5469c - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.052 . Memory (MB): peak = 2052.297 ; gain = 0.000 -Retarget | Checksum: 1cea5469c -INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells - -Phase 4 Constant propagation -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Phase 4 Constant propagation | Checksum: 1cea5469c - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.065 . Memory (MB): peak = 2052.297 ; gain = 0.000 -Constant propagation | Checksum: 1cea5469c -INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells - -Phase 5 Sweep -Phase 5 Sweep | Checksum: 1ee1e6c45 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.080 . Memory (MB): peak = 2052.297 ; gain = 0.000 -Sweep | Checksum: 1ee1e6c45 -INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells - -Phase 6 BUFG optimization -INFO: [Opt 31-194] Inserted BUFG lineClk_reg_n_0_BUFG_inst to drive 31 load(s) on clock net lineClk_reg_n_0_BUFG -INFO: [Opt 31-193] Inserted 1 BUFG(s) on clock nets -Phase 6 BUFG optimization | Checksum: 1c52d7041 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.109 . Memory (MB): peak = 2052.297 ; gain = 0.000 -BUFG optimization | Checksum: 1c52d7041 -INFO: [Opt 31-662] Phase BUFG optimization created 1 cells of which 1 are BUFGs and removed 0 cells. - -Phase 7 Shift Register Optimization -INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs -Phase 7 Shift Register Optimization | Checksum: 1c52d7041 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.111 . Memory (MB): peak = 2052.297 ; gain = 0.000 -Shift Register Optimization | Checksum: 1c52d7041 -INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells - -Phase 8 Post Processing Netlist -Phase 8 Post Processing Netlist | Checksum: 1c52d7041 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.119 . Memory (MB): peak = 2052.297 ; gain = 0.000 -Post Processing Netlist | Checksum: 1c52d7041 -INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells - -Phase 9 Finalization - -Phase 9.1 Finalizing Design Cores and Updating Shapes -Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 20bf60b61 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.182 . Memory (MB): peak = 2052.297 ; gain = 0.000 - -Phase 9.2 Verifying Netlist Connectivity - -Starting Connectivity Check Task - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 2052.297 ; gain = 0.000 -Phase 9.2 Verifying Netlist Connectivity | Checksum: 20bf60b61 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.188 . Memory (MB): peak = 2052.297 ; gain = 0.000 -Phase 9 Finalization | Checksum: 20bf60b61 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.188 . Memory (MB): peak = 2052.297 ; gain = 0.000 -Opt_design Change Summary -========================= - - -------------------------------------------------------------------------------------------------------------------------- -| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | -------------------------------------------------------------------------------------------------------------------------- -| Retarget | 0 | 0 | 0 | -| Constant propagation | 0 | 0 | 0 | -| Sweep | 0 | 0 | 0 | -| BUFG optimization | 1 | 0 | 0 | -| Shift Register Optimization | 0 | 0 | 0 | -| Post Processing Netlist | 0 | 0 | 0 | -------------------------------------------------------------------------------------------------------------------------- - - -Ending Logic Optimization Task | Checksum: 20bf60b61 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.190 . Memory (MB): peak = 2052.297 ; gain = 0.000 -INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8 -Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 2052.297 ; gain = 0.000 - -Starting Power Optimization Task -INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. -Ending Power Optimization Task | Checksum: 20bf60b61 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.020 . Memory (MB): peak = 2052.297 ; gain = 0.000 - -Starting Final Cleanup Task -Ending Final Cleanup Task | Checksum: 20bf60b61 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 2052.297 ; gain = 0.000 - -Starting Netlist Obfuscation Task -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 2052.297 ; gain = 0.000 -Ending Netlist Obfuscation Task | Checksum: 20bf60b61 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 2052.297 ; gain = 0.000 -INFO: [Common 17-83] Releasing license: Implementation -27 Infos, 0 Warnings, 1 Critical Warnings and 0 Errors encountered. -opt_design completed successfully -opt_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:09 . Memory (MB): peak = 2052.297 ; gain = 943.691 -INFO: [runtcl-4] Executing : report_drc -file vga_drc_opted.rpt -pb vga_drc_opted.pb -rpx vga_drc_opted.rpx -Command: report_drc -file vga_drc_opted.rpt -pb vga_drc_opted.pb -rpx vga_drc_opted.rpx -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1704] No user IP repositories specified -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2023.2/data/ip'. -INFO: [DRC 23-27] Running DRC with 20 threads -INFO: [Vivado_Tcl 2-168] The results of DRC are in file C:/Users/james/Documents/vga/vga.runs/impl_1/vga_drc_opted.rpt. -report_drc completed successfully -INFO: [Timing 38-480] Writing timing data to binary archive. -Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 2052.297 ; gain = 0.000 -Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 2052.297 ; gain = 0.000 -Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2052.297 ; gain = 0.000 -Writing XDEF routing. -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 2052.297 ; gain = 0.000 -Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2052.297 ; gain = 0.000 -Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 2052.297 ; gain = 0.000 -Write Physdb Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.020 . Memory (MB): peak = 2052.297 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/Users/james/Documents/vga/vga.runs/impl_1/vga_opt.dcp' has been generated. -Command: place_design -Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' -INFO: [Common 17-83] Releasing license: Implementation -INFO: [DRC 23-27] Running DRC with 20 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. -Running DRC as a precondition to command place_design -INFO: [DRC 23-27] Running DRC with 20 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. -INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 20 CPUs - -Starting Placer Task - -Phase 1 Placer Initialization - -Phase 1.1 Placer Initialization Netlist Sorting -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 2052.297 ; gain = 0.000 -Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1126efb8b - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 2052.297 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 2052.297 ; gain = 0.000 - -Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device -INFO: [Timing 38-35] Done setting XDC timing constraints. -Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: ac010e80 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.609 . Memory (MB): peak = 2052.297 ; gain = 0.000 - -Phase 1.3 Build Placer Netlist Model -Phase 1.3 Build Placer Netlist Model | Checksum: 1881e74df - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.685 . Memory (MB): peak = 2052.297 ; gain = 0.000 - -Phase 1.4 Constrain Clocks/Macros -Phase 1.4 Constrain Clocks/Macros | Checksum: 1881e74df - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.690 . Memory (MB): peak = 2052.297 ; gain = 0.000 -Phase 1 Placer Initialization | Checksum: 1881e74df - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.695 . Memory (MB): peak = 2052.297 ; gain = 0.000 - -Phase 2 Global Placement - -Phase 2.1 Floorplanning -Phase 2.1 Floorplanning | Checksum: 1881e74df - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.704 . Memory (MB): peak = 2052.297 ; gain = 0.000 - -Phase 2.2 Update Timing before SLR Path Opt -Phase 2.2 Update Timing before SLR Path Opt | Checksum: 1881e74df - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.704 . Memory (MB): peak = 2052.297 ; gain = 0.000 - -Phase 2.3 Post-Processing in Floorplanning -Phase 2.3 Post-Processing in Floorplanning | Checksum: 1881e74df - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.705 . Memory (MB): peak = 2052.297 ; gain = 0.000 - -Phase 2.4 Global Placement Core -WARNING: [Place 46-29] Timing had been disabled during Placer and, therefore, physical synthesis in Placer will be skipped. -Phase 2.4 Global Placement Core | Checksum: 100400c78 - -Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 2052.297 ; gain = 0.000 -Phase 2 Global Placement | Checksum: 100400c78 - -Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 2052.297 ; gain = 0.000 - -Phase 3 Detail Placement - -Phase 3.1 Commit Multi Column Macros -Phase 3.1 Commit Multi Column Macros | Checksum: 100400c78 - -Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 2052.297 ; gain = 0.000 - -Phase 3.2 Commit Most Macros & LUTRAMs -Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 84f6ce21 - -Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 2052.297 ; gain = 0.000 - -Phase 3.3 Area Swap Optimization -Phase 3.3 Area Swap Optimization | Checksum: 11b432465 - -Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 2052.297 ; gain = 0.000 - -Phase 3.4 Pipeline Register Optimization -Phase 3.4 Pipeline Register Optimization | Checksum: 11b432465 - -Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 2052.297 ; gain = 0.000 - -Phase 3.5 Small Shape Detail Placement -Phase 3.5 Small Shape Detail Placement | Checksum: 17dc3a9a3 - -Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 2053.227 ; gain = 0.930 - -Phase 3.6 Re-assign LUT pins -Phase 3.6 Re-assign LUT pins | Checksum: 17dc3a9a3 - -Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 2053.227 ; gain = 0.930 - -Phase 3.7 Pipeline Register Optimization -Phase 3.7 Pipeline Register Optimization | Checksum: 17dc3a9a3 - -Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 2053.227 ; gain = 0.930 -Phase 3 Detail Placement | Checksum: 17dc3a9a3 - -Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 2053.227 ; gain = 0.930 - -Phase 4 Post Placement Optimization and Clean-Up - -Phase 4.1 Post Commit Optimization -Phase 4.1 Post Commit Optimization | Checksum: 17dc3a9a3 - -Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 2053.227 ; gain = 0.930 - -Phase 4.2 Post Placement Cleanup -Phase 4.2 Post Placement Cleanup | Checksum: 17dc3a9a3 - -Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 2053.227 ; gain = 0.930 - -Phase 4.3 Placer Reporting - -Phase 4.3.1 Print Estimated Congestion -INFO: [Place 30-612] Post-Placement Estimated Congestion - ____________________________________________________ -| | Global Congestion | Short Congestion | -| Direction | Region Size | Region Size | -|___________|___________________|___________________| -| North| 1x1| 1x1| -|___________|___________________|___________________| -| South| 1x1| 1x1| -|___________|___________________|___________________| -| East| 1x1| 1x1| -|___________|___________________|___________________| -| West| 1x1| 1x1| -|___________|___________________|___________________| - -Phase 4.3.1 Print Estimated Congestion | Checksum: 17dc3a9a3 - -Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 2053.227 ; gain = 0.930 -Phase 4.3 Placer Reporting | Checksum: 17dc3a9a3 - -Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 2053.227 ; gain = 0.930 - -Phase 4.4 Final Placement Cleanup -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 2053.227 ; gain = 0.000 - -Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 2053.227 ; gain = 0.930 -Phase 4 Post Placement Optimization and Clean-Up | Checksum: 234d37e32 - -Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 2053.227 ; gain = 0.930 -Ending Placer Task | Checksum: 1d8e89b7b - -Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 2053.227 ; gain = 0.930 -46 Infos, 1 Warnings, 1 Critical Warnings and 0 Errors encountered. -place_design completed successfully -place_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 2053.227 ; gain = 0.930 -INFO: [runtcl-4] Executing : report_io -file vga_io_placed.rpt -report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.035 . Memory (MB): peak = 2053.227 ; gain = 0.000 -INFO: [runtcl-4] Executing : report_utilization -file vga_utilization_placed.rpt -pb vga_utilization_placed.pb -INFO: [runtcl-4] Executing : report_control_sets -verbose -file vga_control_sets_placed.rpt -report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 2053.227 ; gain = 0.000 -INFO: [Timing 38-480] Writing timing data to binary archive. -Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 2075.250 ; gain = 5.930 -Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.119 . Memory (MB): peak = 2075.250 ; gain = 5.930 -Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2075.250 ; gain = 0.000 -Writing XDEF routing. -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 2075.250 ; gain = 0.000 -Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 2075.250 ; gain = 0.000 -Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 2075.250 ; gain = 0.000 -Write Physdb Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.140 . Memory (MB): peak = 2075.250 ; gain = 5.930 -INFO: [Common 17-1381] The checkpoint 'C:/Users/james/Documents/vga/vga.runs/impl_1/vga_placed.dcp' has been generated. -Command: phys_opt_design -Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' - -Starting Initial Update Timing Task - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.050 . Memory (MB): peak = 2084.129 ; gain = 8.879 -INFO: [Vivado_Tcl 4-235] No timing constraint found. The netlist was not modified. -INFO: [Common 17-83] Releasing license: Implementation -54 Infos, 1 Warnings, 1 Critical Warnings and 0 Errors encountered. -phys_opt_design completed successfully -INFO: [Timing 38-480] Writing timing data to binary archive. -Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 2101.973 ; gain = 0.000 -Wrote PlaceDB: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.117 . Memory (MB): peak = 2107.938 ; gain = 5.965 -Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2107.938 ; gain = 0.000 -Writing XDEF routing. -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 2107.938 ; gain = 0.000 -Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 2107.938 ; gain = 0.000 -Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 2107.938 ; gain = 0.000 -Write Physdb Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.143 . Memory (MB): peak = 2107.938 ; gain = 5.965 -INFO: [Common 17-1381] The checkpoint 'C:/Users/james/Documents/vga/vga.runs/impl_1/vga_physopt.dcp' has been generated. -Command: route_design -Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' -Running DRC as a precondition to command route_design -INFO: [DRC 23-27] Running DRC with 20 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. - - -Starting Routing Task -INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs - -Phase 1 Build RT Design -Checksum: PlaceDB: f4d571ea ConstDB: 0 ShapeSum: e4132991 RouteDB: 0 -Post Restoration Checksum: NetGraph: 3801824b | NumContArr: 10e62473 | Constraints: c2a8fa9d | Timing: c2a8fa9d -Phase 1 Build RT Design | Checksum: 1ce399bf8 - -Time (s): cpu = 00:00:07 ; elapsed = 00:00:19 . Memory (MB): peak = 2216.688 ; gain = 87.242 - -Phase 2 Router Initialization -INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. - -Phase 2.1 Fix Topology Constraints -Phase 2.1 Fix Topology Constraints | Checksum: 1ce399bf8 - -Time (s): cpu = 00:00:07 ; elapsed = 00:00:19 . Memory (MB): peak = 2248.059 ; gain = 118.613 - -Phase 2.2 Pre Route Cleanup -Phase 2.2 Pre Route Cleanup | Checksum: 1ce399bf8 - -Time (s): cpu = 00:00:07 ; elapsed = 00:00:19 . Memory (MB): peak = 2248.059 ; gain = 118.613 - Number of Nodes with overlaps = 0 - -Router Utilization Summary - Global Vertical Routing Utilization = 0 % - Global Horizontal Routing Utilization = 0 % - Routable Net Status* - *Does not include unroutable nets such as driverless and loadless. - Run report_route_status for detailed report. - Number of Failed Nets = 2044 - (Failed Nets is the sum of unrouted and partially routed nets) - Number of Unrouted Nets = 2044 - Number of Partially Routed Nets = 0 - Number of Node Overlaps = 0 - -Phase 2 Router Initialization | Checksum: 24d8a4854 - -Time (s): cpu = 00:00:08 ; elapsed = 00:00:20 . Memory (MB): peak = 2332.684 ; gain = 203.238 - -Phase 3 Initial Routing - -Phase 3.1 Global Routing -Phase 3.1 Global Routing | Checksum: 24d8a4854 - -Time (s): cpu = 00:00:08 ; elapsed = 00:00:20 . Memory (MB): peak = 2332.684 ; gain = 203.238 - -Phase 3.2 Initial Net Routing -Phase 3.2 Initial Net Routing | Checksum: 21ac77c72 - -Time (s): cpu = 00:00:08 ; elapsed = 00:00:20 . Memory (MB): peak = 2332.684 ; gain = 203.238 -Phase 3 Initial Routing | Checksum: 21ac77c72 - -Time (s): cpu = 00:00:08 ; elapsed = 00:00:20 . Memory (MB): peak = 2332.684 ; gain = 203.238 - -Phase 4 Rip-up And Reroute - -Phase 4.1 Global Iteration 0 - Number of Nodes with overlaps = 132 - Number of Nodes with overlaps = 0 -Phase 4.1 Global Iteration 0 | Checksum: 2789b9845 - -Time (s): cpu = 00:00:08 ; elapsed = 00:00:20 . Memory (MB): peak = 2332.684 ; gain = 203.238 -Phase 4 Rip-up And Reroute | Checksum: 2789b9845 - -Time (s): cpu = 00:00:08 ; elapsed = 00:00:20 . Memory (MB): peak = 2332.684 ; gain = 203.238 - -Phase 5 Delay and Skew Optimization -Phase 5 Delay and Skew Optimization | Checksum: 2789b9845 - -Time (s): cpu = 00:00:08 ; elapsed = 00:00:20 . Memory (MB): peak = 2332.684 ; gain = 203.238 - -Phase 6 Post Hold Fix - -Phase 6.1 Hold Fix Iter -Phase 6.1 Hold Fix Iter | Checksum: 2789b9845 - -Time (s): cpu = 00:00:08 ; elapsed = 00:00:20 . Memory (MB): peak = 2332.684 ; gain = 203.238 -Phase 6 Post Hold Fix | Checksum: 2789b9845 - -Time (s): cpu = 00:00:08 ; elapsed = 00:00:20 . Memory (MB): peak = 2332.684 ; gain = 203.238 - -Phase 7 Route finalize - -Router Utilization Summary - Global Vertical Routing Utilization = 0.224355 % - Global Horizontal Routing Utilization = 0.24865 % - Routable Net Status* - *Does not include unroutable nets such as driverless and loadless. - Run report_route_status for detailed report. - Number of Failed Nets = 0 - (Failed Nets is the sum of unrouted and partially routed nets) - Number of Unrouted Nets = 0 - Number of Partially Routed Nets = 0 - Number of Node Overlaps = 0 - - ---GLOBAL Congestion: -Utilization threshold used for congestion level computation: 0.85 -Congestion Report -North Dir 1x1 Area, Max Cong = 22.5225%, No Congested Regions. -South Dir 1x1 Area, Max Cong = 25.2252%, No Congested Regions. -East Dir 1x1 Area, Max Cong = 25%, No Congested Regions. -West Dir 1x1 Area, Max Cong = 20.5882%, No Congested Regions. - ------------------------------- -Reporting congestion hotspots ------------------------------- -Direction: North ----------------- -Congested clusters found at Level 0 -Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 -Direction: South ----------------- -Congested clusters found at Level 0 -Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 -Direction: East ----------------- -Congested clusters found at Level 0 -Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 -Direction: West ----------------- -Congested clusters found at Level 0 -Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 - -Phase 7 Route finalize | Checksum: 2789b9845 - -Time (s): cpu = 00:00:08 ; elapsed = 00:00:20 . Memory (MB): peak = 2332.684 ; gain = 203.238 - -Phase 8 Verifying routed nets - - Verification completed successfully -Phase 8 Verifying routed nets | Checksum: 2789b9845 - -Time (s): cpu = 00:00:08 ; elapsed = 00:00:20 . Memory (MB): peak = 2332.684 ; gain = 203.238 - -Phase 9 Depositing Routes -Phase 9 Depositing Routes | Checksum: 277da3c2d - -Time (s): cpu = 00:00:08 ; elapsed = 00:00:20 . Memory (MB): peak = 2332.684 ; gain = 203.238 -INFO: [Route 35-16] Router Completed Successfully - -Phase 10 Post-Route Event Processing -Phase 10 Post-Route Event Processing | Checksum: 22b587a64 - -Time (s): cpu = 00:00:08 ; elapsed = 00:00:20 . Memory (MB): peak = 2332.684 ; gain = 203.238 -Ending Routing Task | Checksum: 22b587a64 - -Time (s): cpu = 00:00:08 ; elapsed = 00:00:20 . Memory (MB): peak = 2332.684 ; gain = 203.238 - -Routing Is Done. -INFO: [Common 17-83] Releasing license: Implementation -64 Infos, 1 Warnings, 1 Critical Warnings and 0 Errors encountered. -route_design completed successfully -route_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:21 . Memory (MB): peak = 2332.684 ; gain = 224.746 -INFO: [runtcl-4] Executing : report_drc -file vga_drc_routed.rpt -pb vga_drc_routed.pb -rpx vga_drc_routed.rpx -Command: report_drc -file vga_drc_routed.rpt -pb vga_drc_routed.pb -rpx vga_drc_routed.rpx -INFO: [IP_Flow 19-1839] IP Catalog is up to date. -INFO: [DRC 23-27] Running DRC with 20 threads -INFO: [Vivado_Tcl 2-168] The results of DRC are in file C:/Users/james/Documents/vga/vga.runs/impl_1/vga_drc_routed.rpt. -report_drc completed successfully -INFO: [runtcl-4] Executing : report_methodology -file vga_methodology_drc_routed.rpt -pb vga_methodology_drc_routed.pb -rpx vga_methodology_drc_routed.rpx -Command: report_methodology -file vga_methodology_drc_routed.rpt -pb vga_methodology_drc_routed.pb -rpx vga_methodology_drc_routed.rpx -INFO: [Timing 38-35] Done setting XDC timing constraints. -INFO: [DRC 23-133] Running Methodology with 20 threads -INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file C:/Users/james/Documents/vga/vga.runs/impl_1/vga_methodology_drc_routed.rpt. -report_methodology completed successfully -INFO: [runtcl-4] Executing : report_power -file vga_power_routed.rpt -pb vga_power_summary_routed.pb -rpx vga_power_routed.rpx -Command: report_power -file vga_power_routed.rpt -pb vga_power_summary_routed.pb -rpx vga_power_routed.rpx -INFO: [Timing 38-35] Done setting XDC timing constraints. -WARNING: [Power 33-232] No user defined clocks were found in the design! Power estimation will be inaccurate until this is corrected. -Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate -Running Vector-less Activity Propagation... - -Finished Running Vector-less Activity Propagation -74 Infos, 2 Warnings, 1 Critical Warnings and 0 Errors encountered. -report_power completed successfully -INFO: [runtcl-4] Executing : report_route_status -file vga_route_status.rpt -pb vga_route_status.pb -INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -report_unconstrained -file vga_timing_summary_routed.rpt -pb vga_timing_summary_routed.pb -rpx vga_timing_summary_routed.rpx -warn_on_violation -INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. -INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 20 CPUs -WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. -INFO: [runtcl-4] Executing : report_incremental_reuse -file vga_incremental_reuse_routed.rpt -INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. -INFO: [runtcl-4] Executing : report_clock_utilization -file vga_clock_utilization_routed.rpt -INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file vga_bus_skew_routed.rpt -pb vga_bus_skew_routed.pb -rpx vga_bus_skew_routed.rpx -INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. -INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 20 CPUs -INFO: [Timing 38-480] Writing timing data to binary archive. -Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 2490.969 ; gain = 0.000 -Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.119 . Memory (MB): peak = 2490.969 ; gain = 0.000 -Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2490.969 ; gain = 0.000 -Writing XDEF routing. -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.030 . Memory (MB): peak = 2490.969 ; gain = 0.000 -Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 2490.969 ; gain = 0.000 -Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 2490.969 ; gain = 0.000 -Write Physdb Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.161 . Memory (MB): peak = 2490.969 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/Users/james/Documents/vga/vga.runs/impl_1/vga_routed.dcp' has been generated. -INFO: [Common 17-206] Exiting Vivado at Thu Apr 18 02:50:16 2024... diff --git a/vga.runs/impl_1/vga_bus_skew_routed.rpt b/vga.runs/impl_1/vga_bus_skew_routed.rpt index be1b0e9..4b04d4e 100644 --- a/vga.runs/impl_1/vga_bus_skew_routed.rpt +++ b/vga.runs/impl_1/vga_bus_skew_routed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 -| Date : Thu Apr 18 03:15:50 2024 +| Date : Mon Apr 22 21:25:16 2024 | Host : me running 64-bit major release (build 9200) | Command : report_bus_skew -warn_on_violation -file vga_bus_skew_routed.rpt -pb vga_bus_skew_routed.pb -rpx vga_bus_skew_routed.rpx | Design : vga diff --git a/vga.runs/impl_1/vga_bus_skew_routed.rpx b/vga.runs/impl_1/vga_bus_skew_routed.rpx index aa857c4..1d6048d 100644 Binary files a/vga.runs/impl_1/vga_bus_skew_routed.rpx and b/vga.runs/impl_1/vga_bus_skew_routed.rpx differ diff --git a/vga.runs/impl_1/vga_clock_utilization_routed.rpt b/vga.runs/impl_1/vga_clock_utilization_routed.rpt index 7329e72..d068f49 100644 --- a/vga.runs/impl_1/vga_clock_utilization_routed.rpt +++ b/vga.runs/impl_1/vga_clock_utilization_routed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 -| Date : Thu Apr 18 03:15:50 2024 +| Date : Mon Apr 22 21:25:16 2024 | Host : me running 64-bit major release (build 9200) | Command : report_clock_utilization -file vga_clock_utilization_routed.rpt | Design : vga @@ -22,9 +22,13 @@ Table of Contents 6. Device Cell Placement Summary for Global Clock g0 7. Device Cell Placement Summary for Global Clock g1 8. Device Cell Placement Summary for Global Clock g2 -9. Clock Region Cell Placement per Global Clock: Region X1Y1 -10. Clock Region Cell Placement per Global Clock: Region X1Y2 -11. Clock Region Cell Placement per Global Clock: Region X1Y3 +9. Device Cell Placement Summary for Global Clock g3 +10. Clock Region Cell Placement per Global Clock: Region X0Y1 +11. Clock Region Cell Placement per Global Clock: Region X1Y1 +12. Clock Region Cell Placement per Global Clock: Region X0Y2 +13. Clock Region Cell Placement per Global Clock: Region X1Y2 +14. Clock Region Cell Placement per Global Clock: Region X0Y3 +15. Clock Region Cell Placement per Global Clock: Region X1Y3 1. Clock Primitive Utilization ------------------------------ @@ -32,7 +36,7 @@ Table of Contents +----------+------+-----------+-----+--------------+--------+ | Type | Used | Available | LOC | Clock Region | Pblock | +----------+------+-----------+-----+--------------+--------+ -| BUFGCTRL | 3 | 32 | 0 | 0 | 0 | +| BUFGCTRL | 4 | 32 | 0 | 0 | 0 | | BUFH | 0 | 96 | 0 | 0 | 0 | | BUFIO | 0 | 24 | 0 | 0 | 0 | | BUFMR | 0 | 12 | 0 | 0 | 0 | @@ -45,13 +49,14 @@ Table of Contents 2. Global Clock Resources ------------------------- -+-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+-------+-----------------------------+----------------------+ -| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | -+-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+-------+-----------------------------+----------------------+ -| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 2 | 186 | 0 | | | pixClk_BUFG_inst/O | pixClk_BUFG | -| g1 | src1 | BUFG/O | None | BUFGCTRL_X0Y1 | n/a | 1 | 30 | 1 | | | lineClk_reg_n_0_BUFG_inst/O | lineClk_reg_n_0_BUFG | -| g2 | src2 | BUFG/O | None | BUFGCTRL_X0Y16 | n/a | 1 | 2 | 0 | | | sysClk_IBUF_BUFG_inst/O | sysClk_IBUF_BUFG | -+-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+-------+-----------------------------+----------------------+ ++-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+-------+------------------------------+-----------------------+ +| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+-------+------------------------------+-----------------------+ +| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 5 | 1930 | 0 | | | frameClk_reg_n_0_BUFG_inst/O | frameClk_reg_n_0_BUFG | +| g1 | src1 | BUFG/O | None | BUFGCTRL_X0Y1 | n/a | 3 | 248 | 0 | | | pixClk_BUFG_inst/O | pixClk_BUFG | +| g2 | src2 | BUFG/O | None | BUFGCTRL_X0Y2 | n/a | 2 | 30 | 1 | | | lineClk_reg_n_0_BUFG_inst/O | lineClk_reg_n_0_BUFG | +| g3 | src3 | BUFG/O | None | BUFGCTRL_X0Y16 | n/a | 1 | 2 | 0 | | | sysClk_IBUF_BUFG_inst/O | sysClk_IBUF_BUFG | ++-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+-------+------------------------------+-----------------------+ * Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered ** Non-Clock Loads column represents cell count of non-clock pin loads @@ -59,13 +64,14 @@ Table of Contents 3. Global Clock Source Details ------------------------------ -+-----------+-----------+-----------------+------------+---------------+--------------+-------------+-----------------+---------------------+--------------+--------------------+-----------------+ -| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net | -+-----------+-----------+-----------------+------------+---------------+--------------+-------------+-----------------+---------------------+--------------+--------------------+-----------------+ -| src0 | g0 | FDRE/Q | None | SLICE_X52Y96 | X1Y1 | 1 | 1 | | | pixClk_reg/Q | pixClk | -| src1 | g1 | FDRE/Q | None | SLICE_X60Y151 | X1Y3 | 1 | 0 | | | lineClk_reg/Q | lineClk_reg_n_0 | -| src2 | g2 | IBUF/O | IOB_X1Y126 | IOB_X1Y126 | X1Y2 | 1 | 0 | | | sysClk_IBUF_inst/O | sysClk_IBUF | -+-----------+-----------+-----------------+------------+---------------+--------------+-------------+-----------------+---------------------+--------------+--------------------+-----------------+ ++-----------+-----------+-----------------+------------+---------------+--------------+-------------+-----------------+---------------------+--------------+--------------------+--------------------------------+ +| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+---------------+--------------+-------------+-----------------+---------------------+--------------+--------------------+--------------------------------+ +| src0 | g0 | FDRE/Q | None | SLICE_X78Y150 | X1Y3 | 1 | 1 | | | frameClk_reg/Q | frameClk_reg_n_0_BUFG_inst_n_0 | +| src1 | g1 | FDRE/Q | None | SLICE_X51Y96 | X0Y1 | 1 | 1 | | | pixClk_reg/Q | pixClk | +| src2 | g2 | FDRE/Q | None | SLICE_X75Y149 | X1Y2 | 1 | 0 | | | lineClk_reg/Q | lineClk_reg_n_0 | +| src3 | g3 | IBUF/O | IOB_X1Y126 | IOB_X1Y126 | X1Y2 | 1 | 0 | | | sysClk_IBUF_inst/O | sysClk_IBUF | ++-----------+-----------+-----------------+------------+---------------+--------------+-------------+-----------------+---------------------+--------------+--------------------+--------------------------------+ * Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered ** Non-Clock Loads column represents cell count of non-clock pin loads @@ -80,12 +86,12 @@ Table of Contents +-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ | X0Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2600 | 0 | 600 | 0 | 20 | 0 | 10 | 0 | 20 | | X1Y0 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1500 | 0 | 550 | 0 | 40 | 0 | 20 | 0 | 40 | -| X0Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2000 | 0 | 600 | 0 | 20 | 0 | 10 | 0 | 20 | -| X1Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 2 | 1900 | 0 | 650 | 0 | 60 | 0 | 30 | 0 | 40 | -| X0Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2000 | 0 | 600 | 0 | 20 | 0 | 10 | 0 | 20 | -| X1Y2 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 141 | 1900 | 41 | 650 | 0 | 60 | 0 | 30 | 0 | 40 | -| X0Y3 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2600 | 0 | 600 | 0 | 20 | 0 | 10 | 0 | 20 | -| X1Y3 | 2 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 75 | 1350 | 28 | 500 | 0 | 30 | 0 | 15 | 0 | 40 | +| X0Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 2 | 2000 | 0 | 600 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 27 | 1900 | 14 | 650 | 0 | 60 | 0 | 30 | 0 | 40 | +| X0Y2 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 89 | 2000 | 30 | 600 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y2 | 3 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 204 | 1900 | 64 | 650 | 0 | 60 | 0 | 30 | 0 | 40 | +| X0Y3 | 2 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 1345 | 2600 | 293 | 600 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y3 | 3 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 543 | 1350 | 170 | 500 | 0 | 30 | 0 | 15 | 0 | 40 | +-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ * Global Clock column represents track count; while other columns represents cell counts @@ -107,10 +113,34 @@ All Modules 6. Device Cell Placement Summary for Global Clock g0 ---------------------------------------------------- ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+-----------------------+ +| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+-----------------------+ +| g0 | BUFG/O | n/a | | | | 1930 | 0 | 0 | 0 | frameClk_reg_n_0_BUFG | ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+-----------------------+ +* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources +** IO Loads column represents load cell count of IO types +*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) +**** GT Loads column represents load cell count of GT types + + ++----+-------+------+-----------------------+ +| | X0 | X1 | HORIZONTAL PROG DELAY | ++----+-------+------+-----------------------+ +| Y3 | 1264 | 412 | 0 | +| Y2 | 89 | 138 | 0 | +| Y1 | 0 | 27 | 0 | +| Y0 | 0 | 0 | - | ++----+-------+------+-----------------------+ + + +7. Device Cell Placement Summary for Global Clock g1 +---------------------------------------------------- + +-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+-------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+-------------+ -| g0 | BUFG/O | n/a | | | | 186 | 0 | 0 | 0 | pixClk_BUFG | +| g1 | BUFG/O | n/a | | | | 248 | 0 | 0 | 0 | pixClk_BUFG | +-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+-------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types @@ -118,23 +148,23 @@ All Modules **** GT Loads column represents load cell count of GT types -+----+----+------+-----------------------+ -| | X0 | X1 | HORIZONTAL PROG DELAY | -+----+----+------+-----------------------+ -| Y3 | 0 | 45 | 0 | -| Y2 | 0 | 141 | 0 | -| Y1 | 0 | 0 | - | -| Y0 | 0 | 0 | - | -+----+----+------+-----------------------+ ++----+-----+------+-----------------------+ +| | X0 | X1 | HORIZONTAL PROG DELAY | ++----+-----+------+-----------------------+ +| Y3 | 81 | 104 | 0 | +| Y2 | 0 | 63 | 0 | +| Y1 | 0 | 0 | - | +| Y0 | 0 | 0 | - | ++----+-----+------+-----------------------+ -7. Device Cell Placement Summary for Global Clock g1 +8. Device Cell Placement Summary for Global Clock g2 ---------------------------------------------------- +-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+----------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+----------------------+ -| g1 | BUFG/O | n/a | | | | 31 | 0 | 0 | 0 | lineClk_reg_n_0_BUFG | +| g2 | BUFG/O | n/a | | | | 31 | 0 | 0 | 0 | lineClk_reg_n_0_BUFG | +-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+----------------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types @@ -145,20 +175,20 @@ All Modules +----+----+-----+-----------------------+ | | X0 | X1 | HORIZONTAL PROG DELAY | +----+----+-----+-----------------------+ -| Y3 | 0 | 31 | 0 | -| Y2 | 0 | 0 | - | +| Y3 | 0 | 27 | 0 | +| Y2 | 0 | 4 | 0 | | Y1 | 0 | 0 | - | | Y0 | 0 | 0 | - | +----+----+-----+-----------------------+ -8. Device Cell Placement Summary for Global Clock g2 +9. Device Cell Placement Summary for Global Clock g3 ---------------------------------------------------- +-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+------------------+ -| g2 | BUFG/O | n/a | | | | 2 | 0 | 0 | 0 | sysClk_IBUF_BUFG | +| g3 | BUFG/O | n/a | | | | 2 | 0 | 0 | 0 | sysClk_IBUF_BUFG | +-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+------------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types @@ -171,46 +201,89 @@ All Modules +----+----+----+-----------------------+ | Y3 | 0 | 0 | - | | Y2 | 0 | 0 | - | -| Y1 | 0 | 2 | 0 | +| Y1 | 2 | 0 | 0 | | Y0 | 0 | 0 | - | +----+----+----+-----------------------+ -9. Clock Region Cell Placement per Global Clock: Region X1Y1 ------------------------------------------------------------- +10. Clock Region Cell Placement per Global Clock: Region X0Y1 +------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+----+-------------+------+-----+----+------+-----+---------+------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+----+-------------+------+-----+----+------+-----+---------+------------------+ -| g2 | n/a | BUFG/O | None | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | sysClk_IBUF_BUFG | +| g3 | n/a | BUFG/O | None | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | sysClk_IBUF_BUFG | +-----------+-------+-----------------+------------+-------------+-----------------+----+-------------+------+-----+----+------+-----+---------+------------------+ * Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered ** Non-Clock Loads column represents cell count of non-clock pin loads *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts -10. Clock Region Cell Placement per Global Clock: Region X1Y2 +11. Clock Region Cell Placement per Global Clock: Region X1Y1 ------------------------------------------------------------- -+-----------+-------+-----------------+------------+-------------+-----------------+-----+-------------+------+-----+----+------+-----+---------+-------------+ -| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | -+-----------+-------+-----------------+------------+-------------+-----------------+-----+-------------+------+-----+----+------+-----+---------+-------------+ -| g0 | n/a | BUFG/O | None | 141 | 0 | 141 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pixClk_BUFG | -+-----------+-------+-----------------+------------+-------------+-----------------+-----+-------------+------+-----+----+------+-----+---------+-------------+ ++-----------+-------+-----------------+------------+-------------+-----------------+----+-------------+------+-----+----+------+-----+---------+-----------------------+ +| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | ++-----------+-------+-----------------+------------+-------------+-----------------+----+-------------+------+-----+----+------+-----+---------+-----------------------+ +| g0 | n/a | BUFG/O | None | 27 | 0 | 27 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | frameClk_reg_n_0_BUFG | ++-----------+-------+-----------------+------------+-------------+-----------------+----+-------------+------+-----+----+------+-----+---------+-----------------------+ * Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered ** Non-Clock Loads column represents cell count of non-clock pin loads *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts -11. Clock Region Cell Placement per Global Clock: Region X1Y3 +12. Clock Region Cell Placement per Global Clock: Region X0Y2 ------------------------------------------------------------- -+-----------+-------+-----------------+------------+-------------+-----------------+----+-------------+------+-----+----+------+-----+---------+----------------------+ -| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | -+-----------+-------+-----------------+------------+-------------+-----------------+----+-------------+------+-----+----+------+-----+---------+----------------------+ -| g0 | n/a | BUFG/O | None | 45 | 0 | 45 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pixClk_BUFG | -| g1 | n/a | BUFG/O | None | 30 | 1 | 30 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | lineClk_reg_n_0_BUFG | -+-----------+-------+-----------------+------------+-------------+-----------------+----+-------------+------+-----+----+------+-----+---------+----------------------+ ++-----------+-------+-----------------+------------+-------------+-----------------+----+-------------+------+-----+----+------+-----+---------+-----------------------+ +| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | ++-----------+-------+-----------------+------------+-------------+-----------------+----+-------------+------+-----+----+------+-----+---------+-----------------------+ +| g0 | n/a | BUFG/O | None | 89 | 0 | 89 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | frameClk_reg_n_0_BUFG | ++-----------+-------+-----------------+------------+-------------+-----------------+----+-------------+------+-----+----+------+-----+---------+-----------------------+ +* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered +** Non-Clock Loads column represents cell count of non-clock pin loads +*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts + + +13. Clock Region Cell Placement per Global Clock: Region X1Y2 +------------------------------------------------------------- + ++-----------+-------+-----------------+------------+-------------+-----------------+-----+-------------+------+-----+----+------+-----+---------+-----------------------+ +| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | ++-----------+-------+-----------------+------------+-------------+-----------------+-----+-------------+------+-----+----+------+-----+---------+-----------------------+ +| g0 | n/a | BUFG/O | None | 138 | 0 | 138 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | frameClk_reg_n_0_BUFG | +| g1 | n/a | BUFG/O | None | 63 | 0 | 63 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pixClk_BUFG | +| g2 | n/a | BUFG/O | None | 3 | 1 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | lineClk_reg_n_0_BUFG | ++-----------+-------+-----------------+------------+-------------+-----------------+-----+-------------+------+-----+----+------+-----+---------+-----------------------+ +* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered +** Non-Clock Loads column represents cell count of non-clock pin loads +*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts + + +14. Clock Region Cell Placement per Global Clock: Region X0Y3 +------------------------------------------------------------- + ++-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-----------------------+ +| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | ++-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-----------------------+ +| g0 | n/a | BUFG/O | None | 1264 | 0 | 1264 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | frameClk_reg_n_0_BUFG | +| g1 | n/a | BUFG/O | None | 81 | 0 | 81 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pixClk_BUFG | ++-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-----------------------+ +* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered +** Non-Clock Loads column represents cell count of non-clock pin loads +*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts + + +15. Clock Region Cell Placement per Global Clock: Region X1Y3 +------------------------------------------------------------- + ++-----------+-------+-----------------+------------+-------------+-----------------+-----+-------------+------+-----+----+------+-----+---------+-----------------------+ +| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | ++-----------+-------+-----------------+------------+-------------+-----------------+-----+-------------+------+-----+----+------+-----+---------+-----------------------+ +| g0 | n/a | BUFG/O | None | 412 | 0 | 412 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | frameClk_reg_n_0_BUFG | +| g1 | n/a | BUFG/O | None | 104 | 0 | 104 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pixClk_BUFG | +| g2 | n/a | BUFG/O | None | 27 | 0 | 27 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | lineClk_reg_n_0_BUFG | ++-----------+-------+-----------------+------------+-------------+-----------------+-----+-------------+------+-----+----+------+-----+---------+-----------------------+ * Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered ** Non-Clock Loads column represents cell count of non-clock pin loads *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts @@ -219,8 +292,9 @@ All Modules # Location of BUFG Primitives set_property LOC BUFGCTRL_X0Y16 [get_cells sysClk_IBUF_BUFG_inst] -set_property LOC BUFGCTRL_X0Y0 [get_cells pixClk_BUFG_inst] -set_property LOC BUFGCTRL_X0Y1 [get_cells lineClk_reg_n_0_BUFG_inst] +set_property LOC BUFGCTRL_X0Y1 [get_cells pixClk_BUFG_inst] +set_property LOC BUFGCTRL_X0Y2 [get_cells lineClk_reg_n_0_BUFG_inst] +set_property LOC BUFGCTRL_X0Y0 [get_cells frameClk_reg_n_0_BUFG_inst] # Location of IO Primitives which is load of clock spine @@ -231,19 +305,26 @@ set_property LOC IOB_X1Y126 [get_ports sysClk] #startgroup create_pblock {CLKAG_sysClk_IBUF_BUFG} add_cells_to_pblock [get_pblocks {CLKAG_sysClk_IBUF_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="sysClk_IBUF_BUFG"}]]] -resize_pblock [get_pblocks {CLKAG_sysClk_IBUF_BUFG}] -add {CLOCKREGION_X1Y1:CLOCKREGION_X1Y1} +resize_pblock [get_pblocks {CLKAG_sysClk_IBUF_BUFG}] -add {CLOCKREGION_X0Y1:CLOCKREGION_X0Y1} #endgroup -# Clock net "pixClk_BUFG" driven by instance "pixClk_BUFG_inst" located at site "BUFGCTRL_X0Y0" +# Clock net "pixClk_BUFG" driven by instance "pixClk_BUFG_inst" located at site "BUFGCTRL_X0Y1" #startgroup create_pblock {CLKAG_pixClk_BUFG} add_cells_to_pblock [get_pblocks {CLKAG_pixClk_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="pixClk_BUFG"}]]] -resize_pblock [get_pblocks {CLKAG_pixClk_BUFG}] -add {CLOCKREGION_X1Y2:CLOCKREGION_X1Y2 CLOCKREGION_X1Y3:CLOCKREGION_X1Y3} +resize_pblock [get_pblocks {CLKAG_pixClk_BUFG}] -add {CLOCKREGION_X0Y3:CLOCKREGION_X0Y3 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2 CLOCKREGION_X1Y3:CLOCKREGION_X1Y3} #endgroup -# Clock net "lineClk_reg_n_0_BUFG" driven by instance "lineClk_reg_n_0_BUFG_inst" located at site "BUFGCTRL_X0Y1" +# Clock net "lineClk_reg_n_0_BUFG" driven by instance "lineClk_reg_n_0_BUFG_inst" located at site "BUFGCTRL_X0Y2" #startgroup create_pblock {CLKAG_lineClk_reg_n_0_BUFG} add_cells_to_pblock [get_pblocks {CLKAG_lineClk_reg_n_0_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="lineClk_reg_n_0_BUFG"}]]] -resize_pblock [get_pblocks {CLKAG_lineClk_reg_n_0_BUFG}] -add {CLOCKREGION_X1Y3:CLOCKREGION_X1Y3} +resize_pblock [get_pblocks {CLKAG_lineClk_reg_n_0_BUFG}] -add {CLOCKREGION_X1Y2:CLOCKREGION_X1Y2 CLOCKREGION_X1Y3:CLOCKREGION_X1Y3} +#endgroup + +# Clock net "frameClk_reg_n_0_BUFG" driven by instance "frameClk_reg_n_0_BUFG_inst" located at site "BUFGCTRL_X0Y0" +#startgroup +create_pblock {CLKAG_frameClk_reg_n_0_BUFG} +add_cells_to_pblock [get_pblocks {CLKAG_frameClk_reg_n_0_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="frameClk_reg_n_0_BUFG"}]]] +resize_pblock [get_pblocks {CLKAG_frameClk_reg_n_0_BUFG}] -add {CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X0Y3:CLOCKREGION_X0Y3 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2 CLOCKREGION_X1Y3:CLOCKREGION_X1Y3} #endgroup diff --git a/vga.runs/impl_1/vga_control_sets_placed.rpt b/vga.runs/impl_1/vga_control_sets_placed.rpt index 3978692..53d8c8d 100644 --- a/vga.runs/impl_1/vga_control_sets_placed.rpt +++ b/vga.runs/impl_1/vga_control_sets_placed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 -| Date : Thu Apr 18 03:15:25 2024 +| Date : Mon Apr 22 21:24:10 2024 | Host : me running 64-bit major release (build 9200) | Command : report_control_sets -verbose -file vga_control_sets_placed.rpt | Design : vga @@ -23,11 +23,11 @@ Table of Contents +----------------------------------------------------------+-------+ | Status | Count | +----------------------------------------------------------+-------+ -| Total control sets | 12 | -| Minimum number of control sets | 12 | +| Total control sets | 456 | +| Minimum number of control sets | 456 | | Addition due to synthesis replication | 0 | | Addition due to physical synthesis replication | 0 | -| Unused register locations in slices containing registers | 54 | +| Unused register locations in slices containing registers | 2716 | +----------------------------------------------------------+-------+ * Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers ** Run report_qor_suggestions for automated merging and remapping suggestions @@ -39,15 +39,15 @@ Table of Contents +--------------------+-------+ | Fanout | Count | +--------------------+-------+ -| Total control sets | 12 | -| >= 0 to < 4 | 4 | -| >= 4 to < 6 | 0 | -| >= 6 to < 8 | 2 | -| >= 8 to < 10 | 2 | -| >= 10 to < 12 | 0 | -| >= 12 to < 14 | 3 | -| >= 14 to < 16 | 0 | -| >= 16 | 1 | +| Total control sets | 456 | +| >= 0 to < 4 | 298 | +| >= 4 to < 6 | 42 | +| >= 6 to < 8 | 42 | +| >= 8 to < 10 | 43 | +| >= 10 to < 12 | 17 | +| >= 12 to < 14 | 4 | +| >= 14 to < 16 | 1 | +| >= 16 | 9 | +--------------------+-------+ * Control sets can be remapped at either synth_design or opt_design @@ -58,33 +58,477 @@ Table of Contents +--------------+-----------------------+------------------------+-----------------+--------------+ | Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices | +--------------+-----------------------+------------------------+-----------------+--------------+ -| No | No | No | 147 | 95 | -| No | No | Yes | 0 | 0 | -| No | Yes | No | 30 | 10 | -| Yes | No | No | 16 | 7 | -| Yes | No | Yes | 0 | 0 | -| Yes | Yes | No | 25 | 8 | +| No | No | No | 204 | 143 | +| No | No | Yes | 513 | 393 | +| No | Yes | No | 119 | 102 | +| Yes | No | No | 16 | 6 | +| Yes | No | Yes | 1416 | 769 | +| Yes | Yes | No | 40 | 12 | +--------------+-----------------------+------------------------+-----------------+--------------+ 4. Detailed Control Set Information ----------------------------------- -+-----------------------+---------------+-------------------+------------------+----------------+--------------+ -| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | Bels / Slice | -+-----------------------+---------------+-------------------+------------------+----------------+--------------+ -| pixClk_BUFG | hSync_i_1_n_0 | | 1 | 1 | 1.00 | -| lineClk_reg_n_0_BUFG | | | 1 | 1 | 1.00 | -| lineClk_reg_n_0_BUFG | vSync_i_1_n_0 | | 1 | 1 | 1.00 | -| sysClk_IBUF_BUFG | | | 1 | 2 | 2.00 | -| pixClk_BUFG | hState | | 2 | 7 | 3.50 | -| lineClk_reg_n_0_BUFG | vState | | 3 | 7 | 2.33 | -| pixClk_BUFG | | hCnt[9]_i_1_n_0 | 3 | 9 | 3.00 | -| lineClk_reg_n_0_BUFG | | vCnt[9]_i_1_n_0 | 5 | 9 | 1.80 | -| pixClk_BUFG | | vgaRed[3]_i_1_n_0 | 2 | 12 | 6.00 | -| lineClk_reg_n_0_BUFG | pixY | pixY0 | 3 | 12 | 4.00 | -| pixClk_BUFG | pixX | lineClk | 5 | 13 | 2.60 | -| pixClk_BUFG | | | 93 | 144 | 1.55 | -+-----------------------+---------------+-------------------+------------------+----------------+--------------+ ++--------------------------------------------------------+----------------------------------------------------+-------------------------------------------------------+------------------+----------------+--------------+ +| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | Bels / Slice | ++--------------------------------------------------------+----------------------------------------------------+-------------------------------------------------------+------------------+----------------+--------------+ +| core_design/redPieceYOffset_reg[18][9]_LDC_i_1_n_0 | | core_design/redPieceYOffset_reg[18][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/redPieceYOffset_reg[18][8]_LDC_i_1_n_0 | | core_design/redPieceYOffset_reg[18][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/redPieceYOffset_reg[19][9]_LDC_i_1_n_0 | | core_design/redPieceYOffset_reg[19][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/redPieceYOffset_reg[19][8]_LDC_i_1_n_0 | | core_design/redPieceYOffset_reg[19][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/redPieceYOffset_reg[20][8]_LDC_i_1_n_0 | | core_design/redPieceYOffset_reg[20][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/redPieceYOffset_reg[20][9]_LDC_i_1_n_0 | | core_design/redPieceYOffset_reg[20][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/redPieceYOffset_reg[2][9]_LDC_i_1_n_0 | | core_design/redPieceYOffset_reg[2][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/redPieceYOffset_reg[2][8]_LDC_i_1_n_0 | | core_design/redPieceYOffset_reg[2][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/redPieceYOffset_reg[3][9]_LDC_i_1_n_0 | | core_design/redPieceYOffset_reg[3][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/redPieceYOffset_reg[3][8]_LDC_i_1_n_0 | | core_design/redPieceYOffset_reg[3][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/redPieceYOffset_reg[4][9]_LDC_i_1_n_0 | | core_design/redPieceYOffset_reg[4][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/redPieceYOffset_reg[4][8]_LDC_i_1_n_0 | | core_design/redPieceYOffset_reg[4][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/redPieceYOffset_reg[5][9]_LDC_i_1_n_0 | | core_design/redPieceYOffset_reg[5][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/redPieceYOffset_reg[5][8]_LDC_i_1_n_0 | | core_design/redPieceYOffset_reg[5][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/redPieceYOffset_reg[6][9]_LDC_i_1_n_0 | | core_design/redPieceYOffset_reg[6][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/redPieceYOffset_reg[6][8]_LDC_i_1_n_0 | | core_design/redPieceYOffset_reg[6][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/redPieceYOffset_reg[7][8]_LDC_i_1_n_0 | | core_design/redPieceYOffset_reg[7][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/redPieceYOffset_reg[7][9]_LDC_i_1_n_0 | | core_design/redPieceYOffset_reg[7][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/redPieceYOffset_reg[8][8]_LDC_i_1_n_0 | | core_design/redPieceYOffset_reg[8][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/redPieceYOffset_reg[8][9]_LDC_i_1_n_0 | | core_design/redPieceYOffset_reg[8][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/redPieceYOffset_reg[9][8]_LDC_i_1_n_0 | | core_design/redPieceYOffset_reg[9][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/redPieceYOffset_reg[9][9]_LDC_i_1_n_0 | | core_design/redPieceYOffset_reg[9][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/redPieceYOffset_reg[0][9]_LDC_i_1_n_0 | | core_design/redPieceYOffset_reg[0][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/redPieceYOffset_reg[0][8]_LDC_i_1_n_0 | | core_design/redPieceYOffset_reg[0][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/redPieceYOffset_reg[10][9]_LDC_i_1_n_0 | | core_design/redPieceYOffset_reg[10][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/redPieceYOffset_reg[10][8]_LDC_i_1_n_0 | | core_design/redPieceYOffset_reg[10][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/redPieceYOffset_reg[11][9]_LDC_i_1_n_0 | | core_design/redPieceYOffset_reg[11][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/redPieceYOffset_reg[11][8]_LDC_i_1_n_0 | | core_design/redPieceYOffset_reg[11][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/redPieceYOffset_reg[12][8]_LDC_i_1_n_0 | | core_design/redPieceYOffset_reg[12][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/redPieceYOffset_reg[12][9]_LDC_i_1_n_0 | | core_design/redPieceYOffset_reg[12][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/redPieceYOffset_reg[13][8]_LDC_i_1_n_0 | | core_design/redPieceYOffset_reg[13][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/redPieceYOffset_reg[13][9]_LDC_i_1_n_0 | | core_design/redPieceYOffset_reg[13][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/redPieceYOffset_reg[14][8]_LDC_i_1_n_0 | | core_design/redPieceYOffset_reg[14][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/redPieceYOffset_reg[14][9]_LDC_i_1_n_0 | | core_design/redPieceYOffset_reg[14][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/redPieceYOffset_reg[15][9]_LDC_i_1_n_0 | | core_design/redPieceYOffset_reg[15][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/redPieceYOffset_reg[15][8]_LDC_i_1_n_0 | | core_design/redPieceYOffset_reg[15][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/redPieceYOffset_reg[16][8]_LDC_i_1_n_0 | | core_design/redPieceYOffset_reg[16][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/redPieceYOffset_reg[16][9]_LDC_i_1_n_0 | | core_design/redPieceYOffset_reg[16][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/redPieceYOffset_reg[17][9]_LDC_i_1_n_0 | | core_design/redPieceYOffset_reg[17][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/redPieceYOffset_reg[17][8]_LDC_i_1_n_0 | | core_design/redPieceYOffset_reg[17][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYOffset[8][9]_P_i_1_n_0 | core_design/yellowPieceYOffset_reg[8][1]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/redPieceYOffset_reg[18][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/redPieceYOffset_reg[18][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/redPieceYOffset_reg[19][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/redPieceYOffset_reg[19][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/redPieceYOffset_reg[20][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/redPieceYOffset_reg[20][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/redPieceYOffset_reg[2][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/redPieceYOffset_reg[2][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/redPieceYOffset_reg[3][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/redPieceYOffset_reg[3][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/redPieceYOffset_reg[4][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/redPieceYOffset_reg[4][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/redPieceYOffset_reg[5][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/redPieceYOffset_reg[5][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/redPieceYOffset_reg[6][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/redPieceYOffset_reg[6][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/redPieceYOffset_reg[7][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/redPieceYOffset_reg[7][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/redPieceYOffset_reg[8][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/redPieceYOffset_reg[8][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/redPieceYOffset_reg[9][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/redPieceYOffset_reg[9][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/redPieceYOffset_reg[0][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/redPieceYOffset_reg[0][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/redPieceYOffset_reg[10][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/redPieceYOffset_reg[10][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/redPieceYOffset_reg[11][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/redPieceYOffset_reg[11][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/redPieceYOffset_reg[13][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/redPieceYOffset_reg[12][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/redPieceYOffset_reg[12][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/redPieceYOffset_reg[13][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/redPieceYOffset_reg[14][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/redPieceYOffset_reg[14][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/redPieceYOffset_reg[15][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/redPieceYOffset_reg[15][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/redPieceYOffset_reg[16][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/redPieceYOffset_reg[16][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/redPieceYOffset_reg[17][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/redPieceYOffset_reg[17][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/yellowPieceYOffset_reg[19][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/yellowPieceYOffset_reg[1][3]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/yellowPieceYOffset_reg[19][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/yellowPieceYOffset_reg[0][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/yellowPieceYOffset_reg[10][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/yellowPieceYOffset_reg[0][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/yellowPieceYOffset_reg[10][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/yellowPieceYOffset_reg[11][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/yellowPieceYOffset_reg[11][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/yellowPieceYOffset_reg[12][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/yellowPieceYOffset_reg[12][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/yellowPieceYOffset_reg[13][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/yellowPieceYOffset_reg[13][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/yellowPieceYOffset_reg[14][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/yellowPieceYOffset_reg[14][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/yellowPieceYOffset_reg[15][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/yellowPieceYOffset_reg[15][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/yellowPieceYOffset_reg[17][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/yellowPieceYOffset_reg[17][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/yellowPieceYOffset_reg[18][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/yellowPieceYOffset_reg[18][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/yellowPieceYOffset_reg[1][5]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/yellowPieceYOffset_reg[1][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/yellowPieceYOffset_reg[1][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/yellowPieceYOffset_reg[20][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/yellowPieceYOffset_reg[20][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/yellowPieceYOffset_reg[2][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/yellowPieceYOffset_reg[2][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/yellowPieceYOffset_reg[3][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/yellowPieceYOffset_reg[3][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/yellowPieceYOffset_reg[4][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/yellowPieceYOffset_reg[4][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/yellowPieceYOffset_reg[5][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/yellowPieceYOffset_reg[5][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/yellowPieceYOffset_reg[7][1]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/yellowPieceYOffset_reg[7][3]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/yellowPieceYOffset_reg[6][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/yellowPieceYOffset_reg[6][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/yellowPieceYOffset_reg[7][0]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/yellowPieceYOffset_reg[7][2]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/yellowPieceYOffset_reg[7][7]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/yellowPieceYOffset_reg[7][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/yellowPieceYOffset_reg[7][5]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/yellowPieceYOffset_reg[7][6]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/yellowPieceYOffset_reg[7][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/yellowPieceYOffset_reg[7][4]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/yellowPieceYOffset_reg[8][2]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/yellowPieceYOffset_reg[8][6]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/yellowPieceYOffset_reg[8][3]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/yellowPieceYOffset_reg[8][1]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/yellowPieceYOffset_reg[8][4]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/yellowPieceYOffset_reg[8][0]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/yellowPieceYOffset_reg[8][5]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/yellowPieceYOffset_reg[8][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/yellowPieceYOffset_reg[8][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/yellowPieceYOffset_reg[8][7]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/yellowPieceYOffset_reg[9][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | | core_design/yellowPieceYOffset_reg[9][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYOffset[8][9]_P_i_1_n_0 | core_design/yellowPieceYOffset_reg[8][4]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYOffset[8][9]_P_i_1_n_0 | core_design/yellowPieceYOffset_reg[8][0]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYOffset[8][9]_P_i_1_n_0 | core_design/yellowPieceYOffset_reg[8][5]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYOffset[8][9]_P_i_1_n_0 | core_design/yellowPieceYOffset_reg[8][3]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYOffset[8][9]_P_i_1_n_0 | core_design/yellowPieceYOffset_reg[8][9]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYOffset[8][9]_P_i_1_n_0 | core_design/yellowPieceYOffset_reg[8][8]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYOffset[8][9]_P_i_1_n_0 | core_design/yellowPieceYOffset_reg[8][7]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYOffset[6][9]_P_i_1_n_0 | core_design/yellowPieceYOffset_reg[6][8]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYOffset[6][9]_P_i_1_n_0 | core_design/yellowPieceYOffset_reg[6][9]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYOffset[9][9]_P_i_1_n_0 | core_design/yellowPieceYOffset_reg[9][8]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYOffset[9][9]_P_i_1_n_0 | core_design/yellowPieceYOffset_reg[9][9]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| lineClk_reg_n_0_BUFG | vSync_i_1_n_0 | | 1 | 1 | 1.00 | +| pixClk_BUFG | hSync_i_1_n_0 | | 1 | 1 | 1.00 | +| core_design/yellowPieceYOffset_reg[19][9]_LDC_i_1_n_0 | | core_design/yellowPieceYOffset_reg[19][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/yellowPieceYOffset_reg[1][3]_LDC_i_1_n_0 | | core_design/yellowPieceYOffset_reg[1][3]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/yellowPieceYOffset_reg[0][8]_LDC_i_1_n_0 | | core_design/yellowPieceYOffset_reg[0][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/yellowPieceYOffset_reg[0][9]_LDC_i_1_n_0 | | core_design/yellowPieceYOffset_reg[0][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/yellowPieceYOffset_reg[10][8]_LDC_i_1_n_0 | | core_design/yellowPieceYOffset_reg[10][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/yellowPieceYOffset_reg[10][9]_LDC_i_1_n_0 | | core_design/yellowPieceYOffset_reg[10][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/yellowPieceYOffset_reg[11][9]_LDC_i_1_n_0 | | core_design/yellowPieceYOffset_reg[11][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/yellowPieceYOffset_reg[11][8]_LDC_i_1_n_0 | | core_design/yellowPieceYOffset_reg[11][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/yellowPieceYOffset_reg[12][8]_LDC_i_1_n_0 | | core_design/yellowPieceYOffset_reg[12][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/yellowPieceYOffset_reg[12][9]_LDC_i_1_n_0 | | core_design/yellowPieceYOffset_reg[12][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/yellowPieceYOffset_reg[13][8]_LDC_i_1_n_0 | | core_design/yellowPieceYOffset_reg[13][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/yellowPieceYOffset_reg[13][9]_LDC_i_1_n_0 | | core_design/yellowPieceYOffset_reg[13][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/yellowPieceYOffset_reg[14][8]_LDC_i_1_n_0 | | core_design/yellowPieceYOffset_reg[14][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/yellowPieceYOffset_reg[14][9]_LDC_i_1_n_0 | | core_design/yellowPieceYOffset_reg[14][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/yellowPieceYOffset_reg[15][8]_LDC_i_1_n_0 | | core_design/yellowPieceYOffset_reg[15][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/yellowPieceYOffset_reg[15][9]_LDC_i_1_n_0 | | core_design/yellowPieceYOffset_reg[15][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/yellowPieceYOffset_reg[17][9]_LDC_i_1_n_0 | | core_design/yellowPieceYOffset_reg[17][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/yellowPieceYOffset_reg[17][8]_LDC_i_1_n_0 | | core_design/yellowPieceYOffset_reg[17][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/yellowPieceYOffset_reg[18][8]_LDC_i_1_n_0 | | core_design/yellowPieceYOffset_reg[18][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/redPieceYOffset[20][9]_P_i_1_n_0 | core_design/redPieceYOffset_reg[20][8]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/redPieceYOffset[20][9]_P_i_1_n_0 | core_design/redPieceYOffset_reg[20][9]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/redPieceYOffset[2][9]_P_i_1_n_0 | core_design/redPieceYOffset_reg[2][9]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/redPieceYOffset[2][9]_P_i_1_n_0 | core_design/redPieceYOffset_reg[2][8]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/redPieceYOffset[3][9]_P_i_1_n_0 | core_design/redPieceYOffset_reg[3][9]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/redPieceYOffset[3][9]_P_i_1_n_0 | core_design/redPieceYOffset_reg[3][8]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/redPieceYOffset[4][9]_P_i_1_n_0 | core_design/redPieceYOffset_reg[4][9]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/redPieceYOffset[4][9]_P_i_1_n_0 | core_design/redPieceYOffset_reg[4][8]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/redPieceYOffset[5][9]_P_i_1_n_0 | core_design/redPieceYOffset_reg[5][9]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/redPieceYOffset[5][9]_P_i_1_n_0 | core_design/redPieceYOffset_reg[5][8]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/redPieceYOffset[6][9]_P_i_1_n_0 | core_design/redPieceYOffset_reg[6][9]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/redPieceYOffset[6][9]_P_i_1_n_0 | core_design/redPieceYOffset_reg[6][8]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/redPieceYOffset[7][9]_P_i_1_n_0 | core_design/redPieceYOffset_reg[7][8]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/redPieceYOffset[7][9]_P_i_1_n_0 | core_design/redPieceYOffset_reg[7][9]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/redPieceYOffset[8][9]_P_i_1_n_0 | core_design/redPieceYOffset_reg[8][8]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/redPieceYOffset[8][9]_P_i_1_n_0 | core_design/redPieceYOffset_reg[8][9]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/redPieceYOffset[9][9]_P_i_1_n_0 | core_design/redPieceYOffset_reg[9][8]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/redPieceYOffset[9][9]_P_i_1_n_0 | core_design/redPieceYOffset_reg[9][9]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| core_design/yellowPieceYOffset_reg[18][9]_LDC_i_1_n_0 | | core_design/yellowPieceYOffset_reg[18][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/yellowPieceYOffset_reg[1][9]_LDC_i_1_n_0 | | core_design/yellowPieceYOffset_reg[1][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/yellowPieceYOffset_reg[1][8]_LDC_i_1_n_0 | | core_design/yellowPieceYOffset_reg[1][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/yellowPieceYOffset_reg[1][5]_LDC_i_1_n_0 | | core_design/yellowPieceYOffset_reg[1][5]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/yellowPieceYOffset_reg[20][9]_LDC_i_1_n_0 | | core_design/yellowPieceYOffset_reg[20][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/yellowPieceYOffset_reg[20][8]_LDC_i_1_n_0 | | core_design/yellowPieceYOffset_reg[20][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/yellowPieceYOffset_reg[2][8]_LDC_i_1_n_0 | | core_design/yellowPieceYOffset_reg[2][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/yellowPieceYOffset_reg[2][9]_LDC_i_1_n_0 | | core_design/yellowPieceYOffset_reg[2][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/yellowPieceYOffset_reg[3][8]_LDC_i_1_n_0 | | core_design/yellowPieceYOffset_reg[3][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/yellowPieceYOffset_reg[3][9]_LDC_i_1_n_0 | | core_design/yellowPieceYOffset_reg[3][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/yellowPieceYOffset_reg[4][9]_LDC_i_1_n_0 | | core_design/yellowPieceYOffset_reg[4][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/yellowPieceYOffset_reg[4][8]_LDC_i_1_n_0 | | core_design/yellowPieceYOffset_reg[4][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/yellowPieceYOffset_reg[5][8]_LDC_i_1_n_0 | | core_design/yellowPieceYOffset_reg[5][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/yellowPieceYOffset_reg[5][9]_LDC_i_1_n_0 | | core_design/yellowPieceYOffset_reg[5][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/yellowPieceYOffset_reg[7][1]_LDC_i_1_n_0 | | core_design/yellowPieceYOffset_reg[7][1]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/yellowPieceYOffset_reg[7][0]_LDC_i_1_n_0 | | core_design/yellowPieceYOffset_reg[7][0]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/yellowPieceYOffset_reg[6][8]_LDC_i_1_n_0 | | core_design/yellowPieceYOffset_reg[6][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/yellowPieceYOffset_reg[7][2]_LDC_i_1_n_0 | | core_design/yellowPieceYOffset_reg[7][2]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/yellowPieceYOffset_reg[7][3]_LDC_i_1_n_0 | | core_design/yellowPieceYOffset_reg[7][3]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/yellowPieceYOffset_reg[6][9]_LDC_i_1_n_0 | | core_design/yellowPieceYOffset_reg[6][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/yellowPieceYOffset_reg[7][7]_LDC_i_1_n_0 | | core_design/yellowPieceYOffset_reg[7][7]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/yellowPieceYOffset_reg[7][6]_LDC_i_1_n_0 | | core_design/yellowPieceYOffset_reg[7][6]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/yellowPieceYOffset_reg[7][5]_LDC_i_1_n_0 | | core_design/yellowPieceYOffset_reg[7][5]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/yellowPieceYOffset_reg[7][8]_LDC_i_1_n_0 | | core_design/yellowPieceYOffset_reg[7][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/yellowPieceYOffset_reg[7][9]_LDC_i_1_n_0 | | core_design/yellowPieceYOffset_reg[7][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/yellowPieceYOffset_reg[7][4]_LDC_i_1_n_0 | | core_design/yellowPieceYOffset_reg[7][4]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/yellowPieceYOffset_reg[8][2]_LDC_i_1_n_0 | | core_design/yellowPieceYOffset_reg[8][2]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/yellowPieceYOffset_reg[8][6]_LDC_i_1_n_0 | | core_design/yellowPieceYOffset_reg[8][6]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/yellowPieceYOffset_reg[8][1]_LDC_i_1_n_0 | | core_design/yellowPieceYOffset_reg[8][1]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/yellowPieceYOffset_reg[8][4]_LDC_i_1_n_0 | | core_design/yellowPieceYOffset_reg[8][4]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/yellowPieceYOffset_reg[8][0]_LDC_i_1_n_0 | | core_design/yellowPieceYOffset_reg[8][0]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/yellowPieceYOffset_reg[8][5]_LDC_i_1_n_0 | | core_design/yellowPieceYOffset_reg[8][5]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/yellowPieceYOffset_reg[8][3]_LDC_i_1_n_0 | | core_design/yellowPieceYOffset_reg[8][3]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/yellowPieceYOffset_reg[8][9]_LDC_i_1_n_0 | | core_design/yellowPieceYOffset_reg[8][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/yellowPieceYOffset_reg[8][8]_LDC_i_1_n_0 | | core_design/yellowPieceYOffset_reg[8][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/yellowPieceYOffset_reg[8][7]_LDC_i_1_n_0 | | core_design/yellowPieceYOffset_reg[8][7]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/yellowPieceYOffset_reg[9][8]_LDC_i_1_n_0 | | core_design/yellowPieceYOffset_reg[9][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/yellowPieceYOffset_reg[9][9]_LDC_i_1_n_0 | | core_design/yellowPieceYOffset_reg[9][9]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| core_design/yellowPieceYOffset_reg[19][8]_LDC_i_1_n_0 | | core_design/yellowPieceYOffset_reg[19][8]_LDC_i_2_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/redPieceYOffset[0][9]_P_i_1_n_0 | core_design/redPieceYOffset_reg[0][9]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/redPieceYOffset[0][9]_P_i_1_n_0 | core_design/redPieceYOffset_reg[0][8]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/redPieceYOffset[10][9]_P_i_1_n_0 | core_design/redPieceYOffset_reg[10][9]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/redPieceYOffset[10][9]_P_i_1_n_0 | core_design/redPieceYOffset_reg[10][8]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/redPieceYOffset[11][9]_P_i_1_n_0 | core_design/redPieceYOffset_reg[11][9]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/redPieceYOffset[11][9]_P_i_1_n_0 | core_design/redPieceYOffset_reg[11][8]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/redPieceYOffset[12][9]_P_i_1_n_0 | core_design/redPieceYOffset_reg[12][8]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/redPieceYOffset[12][9]_P_i_1_n_0 | core_design/redPieceYOffset_reg[12][9]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/redPieceYOffset[13][9]_P_i_1_n_0 | core_design/redPieceYOffset_reg[13][8]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/redPieceYOffset[13][9]_P_i_1_n_0 | core_design/redPieceYOffset_reg[13][9]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/redPieceYOffset[14][9]_P_i_1_n_0 | core_design/redPieceYOffset_reg[14][8]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/redPieceYOffset[14][9]_P_i_1_n_0 | core_design/redPieceYOffset_reg[14][9]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/redPieceYOffset[15][9]_P_i_1_n_0 | core_design/redPieceYOffset_reg[15][9]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/redPieceYOffset[15][9]_P_i_1_n_0 | core_design/redPieceYOffset_reg[15][8]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/redPieceYOffset[16][9]_P_i_1_n_0 | core_design/redPieceYOffset_reg[16][8]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/redPieceYOffset[16][9]_P_i_1_n_0 | core_design/redPieceYOffset_reg[16][9]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/redPieceYOffset[17][9]_P_i_1_n_0 | core_design/redPieceYOffset_reg[17][9]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/redPieceYOffset[17][9]_P_i_1_n_0 | core_design/redPieceYOffset_reg[17][8]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/redPieceYOffset[18][9]_P_i_1_n_0 | core_design/redPieceYOffset_reg[18][9]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/redPieceYOffset[18][9]_P_i_1_n_0 | core_design/redPieceYOffset_reg[18][8]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/redPieceYOffset[19][9]_P_i_1_n_0 | core_design/redPieceYOffset_reg[19][9]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/redPieceYOffset[19][9]_P_i_1_n_0 | core_design/redPieceYOffset_reg[19][8]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYOffset[17][9]_P_i_1_n_0 | core_design/yellowPieceYOffset_reg[17][9]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYOffset[17][9]_P_i_1_n_0 | core_design/yellowPieceYOffset_reg[17][8]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYOffset[0][9]_P_i_1_n_0 | core_design/yellowPieceYOffset_reg[0][8]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYOffset[0][9]_P_i_1_n_0 | core_design/yellowPieceYOffset_reg[0][9]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYOffset[10][9]_P_i_1_n_0 | core_design/yellowPieceYOffset_reg[10][8]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYOffset[10][9]_P_i_1_n_0 | core_design/yellowPieceYOffset_reg[10][9]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYOffset[11][9]_P_i_1_n_0 | core_design/yellowPieceYOffset_reg[11][9]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYOffset[11][9]_P_i_1_n_0 | core_design/yellowPieceYOffset_reg[11][8]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYOffset[12][9]_P_i_1_n_0 | core_design/yellowPieceYOffset_reg[12][8]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYOffset[12][9]_P_i_1_n_0 | core_design/yellowPieceYOffset_reg[12][9]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYOffset[13][9]_P_i_1_n_0 | core_design/yellowPieceYOffset_reg[13][8]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYOffset[13][9]_P_i_1_n_0 | core_design/yellowPieceYOffset_reg[13][9]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYOffset[14][9]_P_i_1_n_0 | core_design/yellowPieceYOffset_reg[14][8]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYOffset[14][9]_P_i_1_n_0 | core_design/yellowPieceYOffset_reg[14][9]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYOffset[15][9]_P_i_1_n_0 | core_design/yellowPieceYOffset_reg[15][8]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYOffset[15][9]_P_i_1_n_0 | core_design/yellowPieceYOffset_reg[15][9]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYOffset[18][9]_P_i_1_n_0 | core_design/yellowPieceYOffset_reg[18][8]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYOffset[18][9]_P_i_1_n_0 | core_design/yellowPieceYOffset_reg[18][9]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYOffset[19][9]_P_i_1_n_0 | core_design/yellowPieceYOffset_reg[19][8]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYOffset[19][9]_P_i_1_n_0 | core_design/yellowPieceYOffset_reg[19][9]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYOffset[1][9]_P_i_1_n_0 | core_design/yellowPieceYOffset_reg[1][3]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYOffset[1][9]_P_i_1_n_0 | core_design/yellowPieceYOffset_reg[1][9]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYOffset[1][9]_P_i_1_n_0 | core_design/yellowPieceYOffset_reg[1][8]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYOffset[1][9]_P_i_1_n_0 | core_design/yellowPieceYOffset_reg[1][5]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYOffset[20][9]_P_i_1_n_0 | core_design/yellowPieceYOffset_reg[20][9]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYOffset[20][9]_P_i_1_n_0 | core_design/yellowPieceYOffset_reg[20][8]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYOffset[2][9]_P_i_1_n_0 | core_design/yellowPieceYOffset_reg[2][8]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYOffset[2][9]_P_i_1_n_0 | core_design/yellowPieceYOffset_reg[2][9]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYOffset[3][9]_P_i_1_n_0 | core_design/yellowPieceYOffset_reg[3][8]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYOffset[3][9]_P_i_1_n_0 | core_design/yellowPieceYOffset_reg[3][9]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYOffset[4][9]_P_i_1_n_0 | core_design/yellowPieceYOffset_reg[4][9]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYOffset[4][9]_P_i_1_n_0 | core_design/yellowPieceYOffset_reg[4][8]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYOffset[5][9]_P_i_1_n_0 | core_design/yellowPieceYOffset_reg[5][8]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYOffset[5][9]_P_i_1_n_0 | core_design/yellowPieceYOffset_reg[5][9]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYOffset[7][9]_P_i_1_n_0 | core_design/yellowPieceYOffset_reg[7][1]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYOffset[7][9]_P_i_1_n_0 | core_design/yellowPieceYOffset_reg[7][0]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYOffset[7][9]_P_i_1_n_0 | core_design/yellowPieceYOffset_reg[7][2]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYOffset[7][9]_P_i_1_n_0 | core_design/yellowPieceYOffset_reg[7][3]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYOffset[7][9]_P_i_1_n_0 | core_design/yellowPieceYOffset_reg[7][7]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYOffset[7][9]_P_i_1_n_0 | core_design/yellowPieceYOffset_reg[7][6]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYOffset[7][9]_P_i_1_n_0 | core_design/yellowPieceYOffset_reg[7][5]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYOffset[7][9]_P_i_1_n_0 | core_design/yellowPieceYOffset_reg[7][8]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYOffset[7][9]_P_i_1_n_0 | core_design/yellowPieceYOffset_reg[7][9]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYOffset[7][9]_P_i_1_n_0 | core_design/yellowPieceYOffset_reg[7][4]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYOffset[8][9]_P_i_1_n_0 | core_design/yellowPieceYOffset_reg[8][2]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYOffset[8][9]_P_i_1_n_0 | core_design/yellowPieceYOffset_reg[8][6]_LDC_i_1_n_0 | 1 | 1 | 1.00 | +| sysClk_IBUF_BUFG | | | 1 | 2 | 2.00 | +| frameClk_reg_n_0_BUFG | core_design/redPieceYVelocity[6][4]_i_1_n_0 | core_design/reset | 4 | 5 | 1.25 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYVelocity[15][4]_i_1_n_0 | core_design/reset | 4 | 5 | 1.25 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYVelocity[8][4]_i_1_n_0 | core_design/reset | 3 | 5 | 1.67 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYVelocity[9][4]_i_1_n_0 | core_design/reset | 5 | 5 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYVelocity[7][4]_i_1_n_0 | core_design/reset | 4 | 5 | 1.25 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYVelocity[6][4]_i_1_n_0 | core_design/reset | 5 | 5 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYVelocity[16][4]_i_1_n_0 | core_design/reset | 5 | 5 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYVelocity[17][4]_i_1_n_0 | core_design/reset | 5 | 5 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/redPieceYVelocity[15][4]_i_1_n_0 | core_design/reset | 4 | 5 | 1.25 | +| frameClk_reg_n_0_BUFG | core_design/redPieceYVelocity[16][4]_i_1_n_0 | core_design/reset | 5 | 5 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/redPieceYVelocity[18][4]_i_1_n_0 | core_design/reset | 5 | 5 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/redPieceYVelocity[19][4]_i_1_n_0 | core_design/reset | 5 | 5 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/redPieceYVelocity[20][4]_i_1_n_0 | core_design/reset | 5 | 5 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/redPieceYVelocity[1][4]_i_1_n_0 | core_design/reset | 4 | 5 | 1.25 | +| frameClk_reg_n_0_BUFG | core_design/redPieceYVelocity[4][4]_i_1_n_0 | core_design/reset | 5 | 5 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/redPieceYVelocity[2][4]_i_1_n_0 | core_design/reset | 5 | 5 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/redPieceYVelocity[3][4]_i_1_n_0 | core_design/reset | 5 | 5 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/redPieceYVelocity[7][4]_i_1_n_0 | core_design/reset | 4 | 5 | 1.25 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYVelocity[19][4]_i_1_n_0 | core_design/reset | 4 | 5 | 1.25 | +| frameClk_reg_n_0_BUFG | core_design/redPieceYVelocity[5][4]_i_1_n_0 | core_design/reset | 4 | 5 | 1.25 | +| frameClk_reg_n_0_BUFG | core_design/redPieceYVelocity[8][4]_i_1_n_0 | core_design/reset | 4 | 5 | 1.25 | +| frameClk_reg_n_0_BUFG | core_design/redPieceYVelocity[9][4]_i_1_n_0 | core_design/reset | 5 | 5 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYVelocity[1][4]_i_1_n_0 | core_design/reset | 4 | 5 | 1.25 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYVelocity[2][4]_i_1_n_0 | core_design/reset | 4 | 5 | 1.25 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYVelocity[20][4]_i_1_n_0 | core_design/reset | 5 | 5 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/redPieceYVelocity | core_design/reset | 4 | 5 | 1.25 | +| frameClk_reg_n_0_BUFG | core_design/redPieceYVelocity[0][4]_i_1_n_0 | core_design/reset | 5 | 5 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/redPieceYVelocity[10][4]_i_1_n_0 | core_design/reset | 5 | 5 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/redPieceYVelocity[12][4]_i_1_n_0 | core_design/reset | 4 | 5 | 1.25 | +| frameClk_reg_n_0_BUFG | core_design/redPieceYVelocity[11][4]_i_1_n_0 | core_design/reset | 3 | 5 | 1.67 | +| frameClk_reg_n_0_BUFG | core_design/redPieceYVelocity[13][4]_i_1_n_0 | core_design/reset | 5 | 5 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/redPieceYVelocity[14][4]_i_1_n_0 | core_design/reset | 4 | 5 | 1.25 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYVelocity[3][4]_i_1_n_0 | core_design/reset | 4 | 5 | 1.25 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYVelocity[5][4]_i_1_n_0 | core_design/reset | 5 | 5 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYVelocity[14][4]_i_1_n_0 | core_design/reset | 4 | 5 | 1.25 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYVelocity[13][4]_i_1_n_0 | core_design/reset | 3 | 5 | 1.67 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYVelocity[12][4]_i_1_n_0 | core_design/reset | 5 | 5 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYVelocity[4][4]_i_1_n_0 | core_design/reset | 3 | 5 | 1.67 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYVelocity[11][4]_i_1_n_0 | core_design/reset | 4 | 5 | 1.25 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYVelocity[10][4]_i_1_n_0 | core_design/reset | 5 | 5 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYVelocity[0][4]_i_1_n_0 | core_design/reset | 4 | 5 | 1.25 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceYVelocity[18][4]_i_1_n_0 | core_design/reset | 5 | 5 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowIndexToCol[2][2]_i_1_n_0 | core_design/reset | 2 | 6 | 3.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowIndexToCol[4][2]_i_1_n_0 | core_design/reset | 3 | 6 | 2.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowIndexToCol[0][2]_i_1_n_0 | core_design/reset | 5 | 6 | 1.20 | +| frameClk_reg_n_0_BUFG | core_design/yellowIndexToCol[1][2]_i_1_n_0 | core_design/reset | 4 | 6 | 1.50 | +| frameClk_reg_n_0_BUFG | core_design/yellowIndexToRow[12][2]_i_1_n_0 | core_design/reset | 4 | 6 | 1.50 | +| frameClk_reg_n_0_BUFG | core_design/yellowIndexToRow[10][2]_i_1_n_0 | core_design/reset | 2 | 6 | 3.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowIndexToRow[11][2]_i_1_n_0 | core_design/reset | 4 | 6 | 1.50 | +| frameClk_reg_n_0_BUFG | core_design/yellowIndexToRow[13][2]_i_1_n_0 | core_design/reset | 3 | 6 | 2.00 | +| frameClk_reg_n_0_BUFG | core_design/redIndexToCol[16][2]_i_1_n_0 | core_design/reset | 2 | 6 | 3.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowIndexToRow[15][2]_i_1_n_0 | core_design/reset | 2 | 6 | 3.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowIndexToRow[16][2]_i_1_n_0 | core_design/reset | 3 | 6 | 2.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowIndexToRow[14][2]_i_1_n_0 | core_design/reset | 4 | 6 | 1.50 | +| frameClk_reg_n_0_BUFG | core_design/redIndexToCol[18][2]_i_1_n_0 | core_design/reset | 2 | 6 | 3.00 | +| frameClk_reg_n_0_BUFG | core_design/redIndexToCol[12][2]_i_1_n_0 | core_design/reset | 3 | 6 | 2.00 | +| frameClk_reg_n_0_BUFG | core_design/redIndexToCol[2][2]_i_1_n_0 | core_design/reset | 3 | 6 | 2.00 | +| frameClk_reg_n_0_BUFG | core_design/redIndexToCol[1][2]_i_1_n_0 | core_design/reset | 2 | 6 | 3.00 | +| frameClk_reg_n_0_BUFG | core_design/redIndexToCol[14][2]_i_1_n_0 | core_design/reset | 3 | 6 | 2.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowIndexToRow[17][2]_i_1_n_0 | core_design/reset | 3 | 6 | 2.00 | +| frameClk_reg_n_0_BUFG | core_design/redIndexToCol[6][2]_i_1_n_0 | core_design/reset | 3 | 6 | 2.00 | +| frameClk_reg_n_0_BUFG | core_design/redIndexToCol[19][2]_i_1_n_0 | core_design/reset | 3 | 6 | 2.00 | +| frameClk_reg_n_0_BUFG | core_design/redIndexToCol[17][2]_i_1_n_0 | core_design/reset | 3 | 6 | 2.00 | +| frameClk_reg_n_0_BUFG | core_design/redIndexToCol[9][2]_i_1_n_0 | core_design/reset | 2 | 6 | 3.00 | +| frameClk_reg_n_0_BUFG | core_design/redIndexToCol[10][2]_i_1_n_0 | core_design/reset | 3 | 6 | 2.00 | +| frameClk_reg_n_0_BUFG | core_design/redIndexToCol[3][2]_i_1_n_0 | core_design/reset | 2 | 6 | 3.00 | +| frameClk_reg_n_0_BUFG | core_design/redIndexToCol[4][2]_i_1_n_0 | core_design/reset | 3 | 6 | 2.00 | +| frameClk_reg_n_0_BUFG | core_design/redIndexToCol[7][2]_i_1_n_0 | core_design/reset | 3 | 6 | 2.00 | +| frameClk_reg_n_0_BUFG | core_design/redIndexToCol[13][2]_i_1_n_0 | core_design/reset | 2 | 6 | 3.00 | +| frameClk_reg_n_0_BUFG | core_design/redIndexToRow | core_design/reset | 3 | 6 | 2.00 | +| frameClk_reg_n_0_BUFG | core_design/redIndexToRow[20][2]_i_1_n_0 | core_design/reset | 3 | 6 | 2.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowIndexToRow[18][2]_i_1_n_0 | core_design/reset | 3 | 6 | 2.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowIndexToRow[19][2]_i_1_n_0 | core_design/reset | 3 | 6 | 2.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowIndexToRow[20][2]_i_1_n_0 | core_design/reset | 3 | 6 | 2.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowIndexToRow[5][2]_i_1_n_0 | core_design/reset | 4 | 6 | 1.50 | +| frameClk_reg_n_0_BUFG | core_design/yellowIndexToRow[6][2]_i_1_n_0 | core_design/reset | 3 | 6 | 2.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowIndexToRow[8][2]_i_1_n_0 | core_design/reset | 3 | 6 | 2.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowIndexToRow[9][2]_i_1_n_0 | core_design/reset | 3 | 6 | 2.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowIndexToRow[7][2]_i_1_n_0 | core_design/reset | 2 | 6 | 3.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowIndexToCol[3][2]_i_1_n_0 | core_design/reset | 2 | 6 | 3.00 | +| frameClk_reg_n_0_BUFG | core_design/showYellowWinIndicator[6]_i_1_n_0 | core_design/reset | 4 | 7 | 1.75 | +| lineClk_reg_n_0_BUFG | vState | | 2 | 7 | 3.50 | +| frameClk_reg_n_0_BUFG | core_design/showRedWinIndicator[6]_i_1_n_0 | core_design/reset | 4 | 7 | 1.75 | +| pixClk_BUFG | hState__0 | | 2 | 7 | 3.50 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceXOffset[2][9]_i_1_n_0 | core_design/reset | 3 | 9 | 3.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceXOffset[19][9]_i_1_n_0 | core_design/reset | 5 | 9 | 1.80 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceXOffset[12][9]_i_1_n_0 | core_design/reset | 3 | 9 | 3.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceXOffset[4][9]_i_1_n_0 | core_design/reset | 3 | 9 | 3.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceXOffset[1][9]_i_1_n_0 | core_design/reset | 3 | 9 | 3.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceXOffset[11][9]_i_1_n_0 | core_design/reset | 3 | 9 | 3.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceXOffset[7][9]_i_1_n_0 | core_design/reset | 3 | 9 | 3.00 | +| frameClk_reg_n_0_BUFG | core_design/redPieceXOffset[8][9]_i_1_n_0 | core_design/reset | 2 | 9 | 4.50 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceXOffset[14][9]_i_1_n_0 | core_design/reset | 3 | 9 | 3.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceXOffset[3][9]_i_1_n_0 | core_design/reset | 3 | 9 | 3.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceXOffset[6][9]_i_1_n_0 | core_design/reset | 3 | 9 | 3.00 | +| frameClk_reg_n_0_BUFG | core_design/redPieceXOffset[10][9]_i_1_n_0 | core_design/reset | 2 | 9 | 4.50 | +| frameClk_reg_n_0_BUFG | core_design/redPieceXOffset[19][9]_i_1_n_0 | core_design/reset | 6 | 9 | 1.50 | +| frameClk_reg_n_0_BUFG | core_design/redPieceXOffset[5][9]_i_1_n_0 | core_design/reset | 3 | 9 | 3.00 | +| frameClk_reg_n_0_BUFG | core_design/redPieceXOffset[3][9]_i_1_n_0 | core_design/reset | 4 | 9 | 2.25 | +| frameClk_reg_n_0_BUFG | core_design/redPieceXOffset[7][9]_i_1_n_0 | core_design/reset | 3 | 9 | 3.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceXOffset[8][9]_i_1_n_0 | core_design/reset | 3 | 9 | 3.00 | +| frameClk_reg_n_0_BUFG | core_design/redPieceXOffset[18][9]_i_1_n_0 | core_design/reset | 3 | 9 | 3.00 | +| frameClk_reg_n_0_BUFG | core_design/redPieceXOffset[16][9]_i_1_n_0 | core_design/reset | 3 | 9 | 3.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceXOffset__1 | core_design/reset | 3 | 9 | 3.00 | +| frameClk_reg_n_0_BUFG | core_design/redPieceXOffset[13][9]_i_1_n_0 | core_design/reset | 4 | 9 | 2.25 | +| frameClk_reg_n_0_BUFG | core_design/redPieceXOffset[4][9]_i_1_n_0 | core_design/reset | 3 | 9 | 3.00 | +| frameClk_reg_n_0_BUFG | core_design/redPieceXOffset[2][9]_i_1_n_0 | core_design/reset | 3 | 9 | 3.00 | +| frameClk_reg_n_0_BUFG | core_design/redPieceXOffset[12][9]_i_1_n_0 | core_design/reset | 2 | 9 | 4.50 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceXOffset__0 | core_design/reset | 3 | 9 | 3.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceXOffset[13][9]_i_1_n_0 | core_design/reset | 3 | 9 | 3.00 | +| frameClk_reg_n_0_BUFG | core_design/redPieceXOffset[11][9]_i_1_n_0 | core_design/reset | 3 | 9 | 3.00 | +| frameClk_reg_n_0_BUFG | core_design/redPieceXOffset[0][9]_i_1_n_0 | core_design/reset | 3 | 9 | 3.00 | +| frameClk_reg_n_0_BUFG | core_design/redPieceXOffset[14][9]_i_1_n_0 | core_design/reset | 3 | 9 | 3.00 | +| frameClk_reg_n_0_BUFG | core_design/redPieceXOffset__0 | core_design/reset | 3 | 9 | 3.00 | +| frameClk_reg_n_0_BUFG | core_design/redPieceXOffset[6][9]_i_1_n_0 | core_design/reset | 4 | 9 | 2.25 | +| frameClk_reg_n_0_BUFG | core_design/redPieceXOffset[15][9]_i_1_n_0 | core_design/reset | 3 | 9 | 3.00 | +| frameClk_reg_n_0_BUFG | core_design/redPieceXOffset[17][9]_i_1_n_0 | core_design/reset | 3 | 9 | 3.00 | +| frameClk_reg_n_0_BUFG | core_design/redPieceXOffset[9][9]_i_1_n_0 | core_design/reset | 3 | 9 | 3.00 | +| pixClk_BUFG | | hCnt[9]_i_1_n_0 | 2 | 9 | 4.50 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceXOffset[5][9]_i_1_n_0 | core_design/reset | 3 | 9 | 3.00 | +| frameClk_reg_n_0_BUFG | core_design/redPieceXOffset[1][9]_i_1_n_0 | core_design/reset | 3 | 9 | 3.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceXOffset[9][9]_i_1_n_0 | core_design/reset | 3 | 9 | 3.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceXOffset[10][9]_i_1_n_0 | core_design/reset | 3 | 9 | 3.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceXOffset[16][9]_i_1_n_0 | core_design/reset | 3 | 9 | 3.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceXOffset[0][9]_i_1_n_0 | core_design/reset | 3 | 9 | 3.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceXOffset[18][9]_i_1_n_0 | core_design/reset | 3 | 9 | 3.00 | +| frameClk_reg_n_0_BUFG | core_design/yellowPieceXOffset[15][9]_i_1_n_0 | core_design/reset | 4 | 9 | 2.25 | +| frameClk_reg_n_0_BUFG | core_design/redWinYOffset | core_design/reset | 4 | 10 | 2.50 | +| frameClk_reg_n_0_BUFG | core_design/redWinXOffset[4][6]_i_1_n_0 | core_design/reset | 4 | 10 | 2.50 | +| frameClk_reg_n_0_BUFG | core_design/redWinXOffset[5][6]_i_1_n_0 | core_design/reset | 4 | 10 | 2.50 | +| frameClk_reg_n_0_BUFG | core_design/redWinXOffset[0][6]_i_1_n_0 | core_design/reset | 7 | 10 | 1.43 | +| frameClk_reg_n_0_BUFG | core_design/boardYOffset[9]_i_1_n_0 | core_design/reset | 2 | 10 | 5.00 | +| frameClk_reg_n_0_BUFG | core_design/redIndicatorXOffset[9]_i_1_n_0 | core_design/reset | 9 | 10 | 1.11 | +| frameClk_reg_n_0_BUFG | core_design/yellowWinXOffset[4][6]_i_1_n_0 | core_design/reset | 3 | 10 | 3.33 | +| frameClk_reg_n_0_BUFG | core_design/yellowIndicatorXOffset[9]_i_1_n_0 | core_design/reset | 10 | 10 | 1.00 | +| frameClk_reg_n_0_BUFG | core_design/redWinXOffset[2][6]_i_1_n_0 | core_design/reset | 6 | 11 | 1.83 | +| frameClk_reg_n_0_BUFG | core_design/redWinXOffset[6][6]_i_1_n_0 | core_design/reset | 4 | 11 | 2.75 | +| frameClk_reg_n_0_BUFG | core_design/redWinXOffset[1][6]_i_1_n_0 | core_design/reset | 6 | 11 | 1.83 | +| frameClk_reg_n_0_BUFG | core_design/yellowWinXOffset[0][6]_i_1_n_0 | core_design/reset | 4 | 11 | 2.75 | +| frameClk_reg_n_0_BUFG | core_design/yellowWinXOffset[2][6]_i_1_n_0 | core_design/reset | 6 | 11 | 1.83 | +| frameClk_reg_n_0_BUFG | core_design/yellowWinXOffset[6][6]_i_1_n_0 | core_design/reset | 6 | 11 | 1.83 | +| lineClk_reg_n_0_BUFG | | | 7 | 11 | 1.57 | +| lineClk_reg_n_0_BUFG | pixY | pixY[9]_i_1_n_0 | 3 | 11 | 3.67 | +| frameClk_reg_n_0_BUFG | core_design/yellowWinXOffset[5][6]_i_1_n_0 | core_design/reset | 2 | 11 | 5.50 | +| frameClk_reg_n_0_BUFG | core_design/yellowWinXOffset[3][6]_i_1_n_0 | core_design/reset | 7 | 12 | 1.71 | +| frameClk_reg_n_0_BUFG | core_design/yellowWinYOffset__0 | core_design/reset | 6 | 12 | 2.00 | +| pixClk_BUFG | | vgaRed[3]_i_1_n_0 | 2 | 12 | 6.00 | +| frameClk_reg_n_0_BUFG | core_design/currYellow[4]_i_1_n_0 | core_design/reset | 7 | 13 | 1.86 | +| frameClk_reg_n_0_BUFG | core_design/currRed[4]_i_1_n_0 | core_design/reset | 7 | 15 | 2.14 | +| frameClk_reg_n_0_BUFG | core_design/column[5]_C_i_1_n_0 | core_design/reset | 8 | 22 | 2.75 | +| frameClk_reg_n_0_BUFG | core_design/state_reg[5]_i_1_n_0 | core_design/reset | 13 | 28 | 2.15 | +| pixClk_BUFG | pixX | lineClk | 9 | 29 | 3.22 | +| frameClk_reg_n_0_BUFG | core_design/animateResetTimer[0]_i_1_n_0 | core_design/reset | 8 | 32 | 4.00 | +| frameClk_reg_n_0_BUFG | core_design/winIndicatorAnimationTimer[31]_i_1_n_0 | core_design/reset | 11 | 32 | 2.91 | +| frameClk_reg_n_0_BUFG | core_design/pieceAnimationTimer[31]_i_1_n_0 | core_design/reset | 7 | 32 | 4.57 | +| frameClk_reg_n_0_BUFG | core_design/board[4][1]_i_1_n_0 | core_design/reset | 86 | 133 | 1.55 | +| pixClk_BUFG | | | 134 | 190 | 1.42 | +| frameClk_reg_n_0_BUFG | | core_design/reset | 295 | 415 | 1.41 | ++--------------------------------------------------------+----------------------------------------------------+-------------------------------------------------------+------------------+----------------+--------------+ diff --git a/vga.runs/impl_1/vga_drc_opted.rpt b/vga.runs/impl_1/vga_drc_opted.rpt index 04a277d..ec70845 100644 --- a/vga.runs/impl_1/vga_drc_opted.rpt +++ b/vga.runs/impl_1/vga_drc_opted.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 -| Date : Thu Apr 18 03:15:18 2024 +| Date : Mon Apr 22 21:23:29 2024 | Host : me running 64-bit major release (build 9200) | Command : report_drc -file vga_drc_opted.rpt -pb vga_drc_opted.pb -rpx vga_drc_opted.rpx | Design : vga diff --git a/vga.runs/impl_1/vga_drc_routed.pb b/vga.runs/impl_1/vga_drc_routed.pb index 70698d1..60310d2 100644 Binary files a/vga.runs/impl_1/vga_drc_routed.pb and b/vga.runs/impl_1/vga_drc_routed.pb differ diff --git a/vga.runs/impl_1/vga_drc_routed.rpt b/vga.runs/impl_1/vga_drc_routed.rpt index 98e96a7..f773034 100644 --- a/vga.runs/impl_1/vga_drc_routed.rpt +++ b/vga.runs/impl_1/vga_drc_routed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 -| Date : Thu Apr 18 03:15:48 2024 +| Date : Mon Apr 22 21:25:02 2024 | Host : me running 64-bit major release (build 9200) | Command : report_drc -file vga_drc_routed.rpt -pb vga_drc_routed.pb -rpx vga_drc_routed.rpx | Design : vga @@ -24,11 +24,12 @@ Table of Contents Design limits: Ruledeck: default Max violations: - Violations found: 1 + Violations found: 99 +----------+----------+-----------------------------------------------------+------------+ | Rule | Severity | Description | Violations | +----------+----------+-----------------------------------------------------+------------+ | CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | +| PDRC-153 | Warning | Gated clock check | 98 | +----------+----------+-----------------------------------------------------+------------+ 2. REPORT DETAILS @@ -46,4 +47,494 @@ Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_des Refer to the device configuration user guide for more information. Related violations: +PDRC-153#1 Warning +Gated clock check +Net core_design/redPieceYOffset_reg[0][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[0][8]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[0][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#2 Warning +Gated clock check +Net core_design/redPieceYOffset_reg[0][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[0][9]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[0][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#3 Warning +Gated clock check +Net core_design/redPieceYOffset_reg[10][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[10][8]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[10][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#4 Warning +Gated clock check +Net core_design/redPieceYOffset_reg[10][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[10][9]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[10][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#5 Warning +Gated clock check +Net core_design/redPieceYOffset_reg[11][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[11][8]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[11][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#6 Warning +Gated clock check +Net core_design/redPieceYOffset_reg[11][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[11][9]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[11][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#7 Warning +Gated clock check +Net core_design/redPieceYOffset_reg[12][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[12][8]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[12][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#8 Warning +Gated clock check +Net core_design/redPieceYOffset_reg[12][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[12][9]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[12][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#9 Warning +Gated clock check +Net core_design/redPieceYOffset_reg[13][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[13][8]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[13][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#10 Warning +Gated clock check +Net core_design/redPieceYOffset_reg[13][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[13][9]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[13][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#11 Warning +Gated clock check +Net core_design/redPieceYOffset_reg[14][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[14][8]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[14][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#12 Warning +Gated clock check +Net core_design/redPieceYOffset_reg[14][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[14][9]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[14][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#13 Warning +Gated clock check +Net core_design/redPieceYOffset_reg[15][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[15][8]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[15][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#14 Warning +Gated clock check +Net core_design/redPieceYOffset_reg[15][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[15][9]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[15][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#15 Warning +Gated clock check +Net core_design/redPieceYOffset_reg[16][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[16][8]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[16][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#16 Warning +Gated clock check +Net core_design/redPieceYOffset_reg[16][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[16][9]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[16][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#17 Warning +Gated clock check +Net core_design/redPieceYOffset_reg[17][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[17][8]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[17][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#18 Warning +Gated clock check +Net core_design/redPieceYOffset_reg[17][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[17][9]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[17][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#19 Warning +Gated clock check +Net core_design/redPieceYOffset_reg[18][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[18][8]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[18][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#20 Warning +Gated clock check +Net core_design/redPieceYOffset_reg[18][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[18][9]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[18][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#21 Warning +Gated clock check +Net core_design/redPieceYOffset_reg[19][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[19][8]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[19][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#22 Warning +Gated clock check +Net core_design/redPieceYOffset_reg[19][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[19][9]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[19][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#23 Warning +Gated clock check +Net core_design/redPieceYOffset_reg[20][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[20][8]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[20][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#24 Warning +Gated clock check +Net core_design/redPieceYOffset_reg[20][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[20][9]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[20][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#25 Warning +Gated clock check +Net core_design/redPieceYOffset_reg[2][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[2][8]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[2][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#26 Warning +Gated clock check +Net core_design/redPieceYOffset_reg[2][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[2][9]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[2][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#27 Warning +Gated clock check +Net core_design/redPieceYOffset_reg[3][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[3][8]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[3][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#28 Warning +Gated clock check +Net core_design/redPieceYOffset_reg[3][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[3][9]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[3][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#29 Warning +Gated clock check +Net core_design/redPieceYOffset_reg[4][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[4][8]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[4][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#30 Warning +Gated clock check +Net core_design/redPieceYOffset_reg[4][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[4][9]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[4][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#31 Warning +Gated clock check +Net core_design/redPieceYOffset_reg[5][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[5][8]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[5][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#32 Warning +Gated clock check +Net core_design/redPieceYOffset_reg[5][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[5][9]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[5][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#33 Warning +Gated clock check +Net core_design/redPieceYOffset_reg[6][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[6][8]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[6][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#34 Warning +Gated clock check +Net core_design/redPieceYOffset_reg[6][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[6][9]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[6][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#35 Warning +Gated clock check +Net core_design/redPieceYOffset_reg[7][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[7][8]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[7][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#36 Warning +Gated clock check +Net core_design/redPieceYOffset_reg[7][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[7][9]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[7][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#37 Warning +Gated clock check +Net core_design/redPieceYOffset_reg[8][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[8][8]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[8][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#38 Warning +Gated clock check +Net core_design/redPieceYOffset_reg[8][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[8][9]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[8][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#39 Warning +Gated clock check +Net core_design/redPieceYOffset_reg[9][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[9][8]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[9][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#40 Warning +Gated clock check +Net core_design/redPieceYOffset_reg[9][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/redPieceYOffset_reg[9][9]_LDC_i_1/O, cell core_design/redPieceYOffset_reg[9][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#41 Warning +Gated clock check +Net core_design/yellowPieceYOffset_reg[0][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[0][8]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[0][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#42 Warning +Gated clock check +Net core_design/yellowPieceYOffset_reg[0][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[0][9]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[0][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#43 Warning +Gated clock check +Net core_design/yellowPieceYOffset_reg[10][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[10][8]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[10][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#44 Warning +Gated clock check +Net core_design/yellowPieceYOffset_reg[10][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[10][9]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[10][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#45 Warning +Gated clock check +Net core_design/yellowPieceYOffset_reg[11][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[11][8]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[11][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#46 Warning +Gated clock check +Net core_design/yellowPieceYOffset_reg[11][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[11][9]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[11][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#47 Warning +Gated clock check +Net core_design/yellowPieceYOffset_reg[12][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[12][8]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[12][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#48 Warning +Gated clock check +Net core_design/yellowPieceYOffset_reg[12][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[12][9]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[12][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#49 Warning +Gated clock check +Net core_design/yellowPieceYOffset_reg[13][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[13][8]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[13][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#50 Warning +Gated clock check +Net core_design/yellowPieceYOffset_reg[13][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[13][9]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[13][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#51 Warning +Gated clock check +Net core_design/yellowPieceYOffset_reg[14][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[14][8]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[14][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#52 Warning +Gated clock check +Net core_design/yellowPieceYOffset_reg[14][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[14][9]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[14][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#53 Warning +Gated clock check +Net core_design/yellowPieceYOffset_reg[15][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[15][8]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[15][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#54 Warning +Gated clock check +Net core_design/yellowPieceYOffset_reg[15][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[15][9]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[15][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#55 Warning +Gated clock check +Net core_design/yellowPieceYOffset_reg[17][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[17][8]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[17][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#56 Warning +Gated clock check +Net core_design/yellowPieceYOffset_reg[17][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[17][9]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[17][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#57 Warning +Gated clock check +Net core_design/yellowPieceYOffset_reg[18][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[18][8]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[18][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#58 Warning +Gated clock check +Net core_design/yellowPieceYOffset_reg[18][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[18][9]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[18][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#59 Warning +Gated clock check +Net core_design/yellowPieceYOffset_reg[19][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[19][8]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[19][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#60 Warning +Gated clock check +Net core_design/yellowPieceYOffset_reg[19][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[19][9]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[19][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#61 Warning +Gated clock check +Net core_design/yellowPieceYOffset_reg[1][3]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[1][3]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[1][3]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#62 Warning +Gated clock check +Net core_design/yellowPieceYOffset_reg[1][5]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[1][5]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[1][5]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#63 Warning +Gated clock check +Net core_design/yellowPieceYOffset_reg[1][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[1][8]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[1][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#64 Warning +Gated clock check +Net core_design/yellowPieceYOffset_reg[1][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[1][9]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[1][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#65 Warning +Gated clock check +Net core_design/yellowPieceYOffset_reg[20][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[20][8]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[20][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#66 Warning +Gated clock check +Net core_design/yellowPieceYOffset_reg[20][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[20][9]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[20][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#67 Warning +Gated clock check +Net core_design/yellowPieceYOffset_reg[2][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[2][8]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[2][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#68 Warning +Gated clock check +Net core_design/yellowPieceYOffset_reg[2][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[2][9]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[2][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#69 Warning +Gated clock check +Net core_design/yellowPieceYOffset_reg[3][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[3][8]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[3][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#70 Warning +Gated clock check +Net core_design/yellowPieceYOffset_reg[3][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[3][9]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[3][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#71 Warning +Gated clock check +Net core_design/yellowPieceYOffset_reg[4][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[4][8]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[4][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#72 Warning +Gated clock check +Net core_design/yellowPieceYOffset_reg[4][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[4][9]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[4][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#73 Warning +Gated clock check +Net core_design/yellowPieceYOffset_reg[5][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[5][8]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[5][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#74 Warning +Gated clock check +Net core_design/yellowPieceYOffset_reg[5][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[5][9]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[5][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#75 Warning +Gated clock check +Net core_design/yellowPieceYOffset_reg[6][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[6][8]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[6][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#76 Warning +Gated clock check +Net core_design/yellowPieceYOffset_reg[6][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[6][9]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[6][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#77 Warning +Gated clock check +Net core_design/yellowPieceYOffset_reg[7][0]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[7][0]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[7][0]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#78 Warning +Gated clock check +Net core_design/yellowPieceYOffset_reg[7][1]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[7][1]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[7][1]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#79 Warning +Gated clock check +Net core_design/yellowPieceYOffset_reg[7][2]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[7][2]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[7][2]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#80 Warning +Gated clock check +Net core_design/yellowPieceYOffset_reg[7][3]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[7][3]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[7][3]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#81 Warning +Gated clock check +Net core_design/yellowPieceYOffset_reg[7][4]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[7][4]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[7][4]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#82 Warning +Gated clock check +Net core_design/yellowPieceYOffset_reg[7][5]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[7][5]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[7][5]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#83 Warning +Gated clock check +Net core_design/yellowPieceYOffset_reg[7][6]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[7][6]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[7][6]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#84 Warning +Gated clock check +Net core_design/yellowPieceYOffset_reg[7][7]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[7][7]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[7][7]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#85 Warning +Gated clock check +Net core_design/yellowPieceYOffset_reg[7][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[7][8]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[7][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#86 Warning +Gated clock check +Net core_design/yellowPieceYOffset_reg[7][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[7][9]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[7][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#87 Warning +Gated clock check +Net core_design/yellowPieceYOffset_reg[8][0]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[8][0]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[8][0]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#88 Warning +Gated clock check +Net core_design/yellowPieceYOffset_reg[8][1]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[8][1]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[8][1]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#89 Warning +Gated clock check +Net core_design/yellowPieceYOffset_reg[8][2]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[8][2]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[8][2]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#90 Warning +Gated clock check +Net core_design/yellowPieceYOffset_reg[8][3]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[8][3]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[8][3]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#91 Warning +Gated clock check +Net core_design/yellowPieceYOffset_reg[8][4]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[8][4]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[8][4]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#92 Warning +Gated clock check +Net core_design/yellowPieceYOffset_reg[8][5]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[8][5]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[8][5]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#93 Warning +Gated clock check +Net core_design/yellowPieceYOffset_reg[8][6]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[8][6]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[8][6]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#94 Warning +Gated clock check +Net core_design/yellowPieceYOffset_reg[8][7]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[8][7]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[8][7]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#95 Warning +Gated clock check +Net core_design/yellowPieceYOffset_reg[8][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[8][8]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[8][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#96 Warning +Gated clock check +Net core_design/yellowPieceYOffset_reg[8][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[8][9]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[8][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#97 Warning +Gated clock check +Net core_design/yellowPieceYOffset_reg[9][8]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[9][8]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[9][8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#98 Warning +Gated clock check +Net core_design/yellowPieceYOffset_reg[9][9]_LDC_i_1_n_0 is a gated clock net sourced by a combinational pin core_design/yellowPieceYOffset_reg[9][9]_LDC_i_1/O, cell core_design/yellowPieceYOffset_reg[9][9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + diff --git a/vga.runs/impl_1/vga_drc_routed.rpx b/vga.runs/impl_1/vga_drc_routed.rpx index 2e8fbc6..90a3bfa 100644 Binary files a/vga.runs/impl_1/vga_drc_routed.rpx and b/vga.runs/impl_1/vga_drc_routed.rpx differ diff --git a/vga.runs/impl_1/vga_io_placed.rpt b/vga.runs/impl_1/vga_io_placed.rpt index fa8995d..5b97f67 100644 --- a/vga.runs/impl_1/vga_io_placed.rpt +++ b/vga.runs/impl_1/vga_io_placed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. ---------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 -| Date : Thu Apr 18 03:15:25 2024 +| Date : Mon Apr 22 21:24:10 2024 | Host : me running 64-bit major release (build 9200) | Command : report_io -file vga_io_placed.rpt | Design : vga @@ -25,341 +25,341 @@ Table of Contents +---------------+ | Total User IO | +---------------+ -| 15 | +| 22 | +---------------+ 2. IO Assignments by Package Pin -------------------------------- -+------------+-------------+------------+------------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ -| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization | -+------------+-------------+------------+------------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ -| A1 | | High Range | IO_L9N_T1_DQS_AD7N_35 | User IO | | 35 | | | | | | | | | | | | | | -| A2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| A3 | vgaRed[0] | High Range | IO_L8N_T1_AD14N_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | -| A4 | vgaRed[3] | High Range | IO_L8P_T1_AD14P_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | -| A5 | vgaGrn[1] | High Range | IO_L3N_T0_DQS_AD5N_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | -| A6 | vgaGrn[3] | High Range | IO_L3P_T0_DQS_AD5P_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | -| A7 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | -| A8 | | High Range | IO_L12N_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | -| A9 | | High Range | IO_L14N_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | -| A10 | | High Range | IO_L14P_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | -| A11 | | High Range | IO_L4N_T0_15 | User IO | | 15 | | | | | | | | | | | | | | -| A12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| A13 | | High Range | IO_L9P_T1_DQS_AD3P_15 | User IO | | 15 | | | | | | | | | | | | | | -| A14 | | High Range | IO_L9N_T1_DQS_AD3N_15 | User IO | | 15 | | | | | | | | | | | | | | -| A15 | | High Range | IO_L8P_T1_AD10P_15 | User IO | | 15 | | | | | | | | | | | | | | -| A16 | | High Range | IO_L8N_T1_AD10N_15 | User IO | | 15 | | | | | | | | | | | | | | -| A17 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | | -| A18 | | High Range | IO_L10N_T1_AD11N_15 | User IO | | 15 | | | | | | | | | | | | | | -| B1 | | High Range | IO_L9P_T1_DQS_AD7P_35 | User IO | | 35 | | | | | | | | | | | | | | -| B2 | | High Range | IO_L10N_T1_AD15N_35 | User IO | | 35 | | | | | | | | | | | | | | -| B3 | | High Range | IO_L10P_T1_AD15P_35 | User IO | | 35 | | | | | | | | | | | | | | -| B4 | vgaRed[1] | High Range | IO_L7N_T1_AD6N_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | -| B5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| B6 | vgaGrn[2] | High Range | IO_L2N_T0_AD12N_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | -| B7 | vgaBlu[0] | High Range | IO_L2P_T0_AD12P_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | -| B8 | | High Range | IO_L12P_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | -| B9 | | High Range | IO_L11N_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | -| B10 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | -| B11 | hSync | High Range | IO_L4P_T0_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | -| B12 | vSync | High Range | IO_L3N_T0_DQS_AD1N_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | -| B13 | | High Range | IO_L2P_T0_AD8P_15 | User IO | | 15 | | | | | | | | | | | | | | -| B14 | | High Range | IO_L2N_T0_AD8N_15 | User IO | | 15 | | | | | | | | | | | | | | -| B15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| B16 | | High Range | IO_L7P_T1_AD2P_15 | User IO | | 15 | | | | | | | | | | | | | | -| B17 | | High Range | IO_L7N_T1_AD2N_15 | User IO | | 15 | | | | | | | | | | | | | | -| B18 | | High Range | IO_L10P_T1_AD11P_15 | User IO | | 15 | | | | | | | | | | | | | | -| C1 | | High Range | IO_L16N_T2_35 | User IO | | 35 | | | | | | | | | | | | | | -| C2 | | High Range | IO_L16P_T2_35 | User IO | | 35 | | | | | | | | | | | | | | -| C3 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | -| C4 | | High Range | IO_L7P_T1_AD6P_35 | User IO | | 35 | | | | | | | | | | | | | | -| C5 | vgaRed[2] | High Range | IO_L1N_T0_AD4N_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | -| C6 | vgaGrn[0] | High Range | IO_L1P_T0_AD4P_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | -| C7 | vgaBlu[1] | High Range | IO_L4N_T0_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | -| C8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| C9 | | High Range | IO_L11P_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | -| C10 | | High Range | IO_L13N_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | -| C11 | | High Range | IO_L13P_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | -| C12 | | High Range | IO_L3P_T0_DQS_AD1P_15 | User IO | | 15 | | | | | | | | | | | | | | -| C13 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | | -| C14 | | High Range | IO_L1N_T0_AD0N_15 | User IO | | 15 | | | | | | | | | | | | | | -| C15 | | High Range | IO_L12N_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | -| C16 | | High Range | IO_L20P_T3_A20_15 | User IO | | 15 | | | | | | | | | | | | | | -| C17 | | High Range | IO_L20N_T3_A19_15 | User IO | | 15 | | | | | | | | | | | | | | -| C18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| D1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| D2 | | High Range | IO_L14N_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | -| D3 | | High Range | IO_L12N_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | -| D4 | | High Range | IO_L11N_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | -| D5 | | High Range | IO_L11P_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | -| D6 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | -| D7 | vgaBlu[2] | High Range | IO_L6N_T0_VREF_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | -| D8 | vgaBlu[3] | High Range | IO_L4P_T0_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | -| D9 | | High Range | IO_L6N_T0_VREF_16 | User IO | | 16 | | | | | | | | | | | | | | -| D10 | | High Range | IO_L19N_T3_VREF_16 | User IO | | 16 | | | | | | | | | | | | | | -| D11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| D12 | | High Range | IO_L6P_T0_15 | User IO | | 15 | | | | | | | | | | | | | | -| D13 | | High Range | IO_L6N_T0_VREF_15 | User IO | | 15 | | | | | | | | | | | | | | -| D14 | | High Range | IO_L1P_T0_AD0P_15 | User IO | | 15 | | | | | | | | | | | | | | -| D15 | | High Range | IO_L12P_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | -| D16 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | | -| D17 | | High Range | IO_L16N_T2_A27_15 | User IO | | 15 | | | | | | | | | | | | | | -| D18 | | High Range | IO_L21N_T3_DQS_A18_15 | User IO | | 15 | | | | | | | | | | | | | | -| E1 | | High Range | IO_L18N_T2_35 | User IO | | 35 | | | | | | | | | | | | | | -| E2 | | High Range | IO_L14P_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | -| E3 | sysClk | High Range | IO_L12P_T1_MRCC_35 | INPUT | LVCMOS33 | 35 | | | | NONE | | FIXED | | | | NONE | | | | -| E4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| E5 | | High Range | IO_L5N_T0_AD13N_35 | User IO | | 35 | | | | | | | | | | | | | | -| E6 | | High Range | IO_L5P_T0_AD13P_35 | User IO | | 35 | | | | | | | | | | | | | | -| E7 | | High Range | IO_L6P_T0_35 | User IO | | 35 | | | | | | | | | | | | | | -| E8 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | | -| E9 | | Dedicated | CCLK_0 | Config | | 0 | | | | | | | | | | | | | | -| E10 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | | -| E11 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | | | -| E12 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | | | | -| E13 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | | | -| E14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| E15 | | High Range | IO_L11P_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | -| E16 | | High Range | IO_L11N_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | -| E17 | | High Range | IO_L16P_T2_A28_15 | User IO | | 15 | | | | | | | | | | | | | | -| E18 | | High Range | IO_L21P_T3_DQS_15 | User IO | | 15 | | | | | | | | | | | | | | -| F1 | | High Range | IO_L18P_T2_35 | User IO | | 35 | | | | | | | | | | | | | | -| F2 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | -| F3 | | High Range | IO_L13N_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | -| F4 | | High Range | IO_L13P_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | -| F5 | | High Range | IO_0_35 | User IO | | 35 | | | | | | | | | | | | | | -| F6 | | High Range | IO_L19N_T3_VREF_35 | User IO | | 35 | | | | | | | | | | | | | | -| F7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| F8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | -| F9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| F10 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | -| F11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| F12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | -| F13 | | High Range | IO_L5P_T0_AD9P_15 | User IO | | 15 | | | | | | | | | | | | | | -| F14 | | High Range | IO_L5N_T0_AD9N_15 | User IO | | 15 | | | | | | | | | | | | | | -| F15 | | High Range | IO_L14P_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | -| F16 | | High Range | IO_L14N_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | -| F17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| F18 | | High Range | IO_L22N_T3_A16_15 | User IO | | 15 | | | | | | | | | | | | | | -| G1 | | High Range | IO_L17N_T2_35 | User IO | | 35 | | | | | | | | | | | | | | -| G2 | | High Range | IO_L15N_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | -| G3 | | High Range | IO_L20N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | -| G4 | | High Range | IO_L20P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | -| G5 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | -| G6 | | High Range | IO_L19P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | -| G7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | -| G8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| G9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | -| G10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| G11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | -| G12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| G13 | | High Range | IO_0_15 | User IO | | 15 | | | | | | | | | | | | | | -| G14 | | High Range | IO_L15N_T2_DQS_ADV_B_15 | User IO | | 15 | | | | | | | | | | | | | | -| G15 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | | -| G16 | | High Range | IO_L13N_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | -| G17 | | High Range | IO_L18N_T2_A23_15 | User IO | | 15 | | | | | | | | | | | | | | -| G18 | | High Range | IO_L22P_T3_A17_15 | User IO | | 15 | | | | | | | | | | | | | | -| H1 | | High Range | IO_L17P_T2_35 | User IO | | 35 | | | | | | | | | | | | | | -| H2 | | High Range | IO_L15P_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | -| H3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| H4 | | High Range | IO_L21N_T3_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | -| H5 | | High Range | IO_L24N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | -| H6 | | High Range | IO_L24P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | -| H7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| H8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | -| H9 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | | | | -| H10 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | | | | -| H11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| H12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | -| H13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| H14 | | High Range | IO_L15P_T2_DQS_15 | User IO | | 15 | | | | | | | | | | | | | | -| H15 | | High Range | IO_L19N_T3_A21_VREF_15 | User IO | | 15 | | | | | | | | | | | | | | -| H16 | | High Range | IO_L13P_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | -| H17 | | High Range | IO_L18P_T2_A24_15 | User IO | | 15 | | | | | | | | | | | | | | -| H18 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | | -| J1 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | -| J2 | | High Range | IO_L22N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | -| J3 | | High Range | IO_L22P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | -| J4 | | High Range | IO_L21P_T3_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | -| J5 | | High Range | IO_25_35 | User IO | | 35 | | | | | | | | | | | | | | -| J6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| J7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | -| J8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| J9 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | | -| J10 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | | -| J11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | -| J12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| J13 | | High Range | IO_L17N_T2_A25_15 | User IO | | 15 | | | | | | | | | | | | | | -| J14 | | High Range | IO_L19P_T3_A22_15 | User IO | | 15 | | | | | | | | | | | | | | -| J15 | | High Range | IO_L24N_T3_RS0_15 | User IO | | 15 | | | | | | | | | | | | | | -| J16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| J17 | | High Range | IO_L23P_T3_FOE_B_15 | User IO | | 15 | | | | | | | | | | | | | | -| J18 | | High Range | IO_L23N_T3_FWE_B_15 | User IO | | 15 | | | | | | | | | | | | | | -| K1 | | High Range | IO_L23N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | -| K2 | | High Range | IO_L23P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | -| K3 | | High Range | IO_L2P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | -| K4 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | -| K5 | | High Range | IO_L5P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | -| K6 | | High Range | IO_0_34 | User IO | | 34 | | | | | | | | | | | | | | -| K7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| K8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | -| K9 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | | -| K10 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | | -| K11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| K12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | -| K13 | | High Range | IO_L17P_T2_A26_15 | User IO | | 15 | | | | | | | | | | | | | | -| K14 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | | -| K15 | | High Range | IO_L24P_T3_RS1_15 | User IO | | 15 | | | | | | | | | | | | | | -| K16 | | High Range | IO_25_15 | User IO | | 15 | | | | | | | | | | | | | | -| K17 | | High Range | IO_L1P_T0_D00_MOSI_14 | User IO | | 14 | | | | | | | | | | | | | | -| K18 | | High Range | IO_L1N_T0_D01_DIN_14 | User IO | | 14 | | | | | | | | | | | | | | -| L1 | | High Range | IO_L1P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | -| L2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| L3 | | High Range | IO_L2N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | -| L4 | | High Range | IO_L5N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | -| L5 | | High Range | IO_L6N_T0_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | -| L6 | | High Range | IO_L6P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | -| L7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | -| L8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| L9 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | -| L10 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | -| L11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | -| L12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| L13 | | High Range | IO_L6P_T0_FCS_B_14 | User IO | | 14 | | | | | | | | | | | | | | -| L14 | | High Range | IO_L2P_T0_D02_14 | User IO | | 14 | | | | | | | | | | | | | | -| L15 | | High Range | IO_L3P_T0_DQS_PUDC_B_14 | User IO | | 14 | | | | | | | | | | | | | | -| L16 | | High Range | IO_L3N_T0_DQS_EMCCLK_14 | User IO | | 14 | | | | | | | | | | | | | | -| L17 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | -| L18 | | High Range | IO_L4P_T0_D04_14 | User IO | | 14 | | | | | | | | | | | | | | -| M1 | | High Range | IO_L1N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | -| M2 | | High Range | IO_L4N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | -| M3 | | High Range | IO_L4P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | -| M4 | | High Range | IO_L16P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | -| M5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| M6 | | High Range | IO_L18P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | -| M7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| M8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | -| M9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| M10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | -| M11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| M12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | -| M13 | | High Range | IO_L6N_T0_D08_VREF_14 | User IO | | 14 | | | | | | | | | | | | | | -| M14 | | High Range | IO_L2N_T0_D03_14 | User IO | | 14 | | | | | | | | | | | | | | -| M15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| M16 | | High Range | IO_L10P_T1_D14_14 | User IO | | 14 | | | | | | | | | | | | | | -| M17 | | High Range | IO_L10N_T1_D15_14 | User IO | | 14 | | | | | | | | | | | | | | -| M18 | | High Range | IO_L4N_T0_D05_14 | User IO | | 14 | | | | | | | | | | | | | | -| N1 | | High Range | IO_L3N_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | -| N2 | | High Range | IO_L3P_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | -| N3 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | -| N4 | | High Range | IO_L16N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | -| N5 | | High Range | IO_L13P_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | -| N6 | | High Range | IO_L18N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | -| N7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | -| N8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| N9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | -| N10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| N11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | -| N12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| N13 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | -| N14 | | High Range | IO_L8P_T1_D11_14 | User IO | | 14 | | | | | | | | | | | | | | -| N15 | | High Range | IO_L11P_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | -| N16 | | High Range | IO_L11N_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | -| N17 | | High Range | IO_L9P_T1_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | -| N18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| P1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| P2 | | High Range | IO_L15P_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | -| P3 | | High Range | IO_L14N_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | -| P4 | | High Range | IO_L14P_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | -| P5 | | High Range | IO_L13N_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | -| P6 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | -| P7 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | | -| P8 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | | | | | | | | | | -| P9 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | | -| P10 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | | -| P11 | | Dedicated | M2_0 | Config | | 0 | | | | | | | | | | | | | | -| P12 | | Dedicated | M0_0 | Config | | 0 | | | | | | | | | | | | | | -| P13 | | Dedicated | M1_0 | Config | | 0 | | | | | | | | | | | | | | -| P14 | | High Range | IO_L8N_T1_D12_14 | User IO | | 14 | | | | | | | | | | | | | | -| P15 | | High Range | IO_L13P_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | -| P16 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | -| P17 | | High Range | IO_L12P_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | -| P18 | | High Range | IO_L9N_T1_DQS_D13_14 | User IO | | 14 | | | | | | | | | | | | | | -| R1 | | High Range | IO_L17P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | -| R2 | | High Range | IO_L15N_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | -| R3 | | High Range | IO_L11P_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | -| R4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| R5 | | High Range | IO_L19N_T3_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | -| R6 | | High Range | IO_L19P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | -| R7 | | High Range | IO_L23P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | -| R8 | | High Range | IO_L24P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | -| R9 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | | -| R10 | | High Range | IO_25_14 | User IO | | 14 | | | | | | | | | | | | | | -| R11 | | High Range | IO_0_14 | User IO | | 14 | | | | | | | | | | | | | | -| R12 | | High Range | IO_L5P_T0_D06_14 | User IO | | 14 | | | | | | | | | | | | | | -| R13 | | High Range | IO_L5N_T0_D07_14 | User IO | | 14 | | | | | | | | | | | | | | -| R14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| R15 | | High Range | IO_L13N_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | -| R16 | | High Range | IO_L15P_T2_DQS_RDWR_B_14 | User IO | | 14 | | | | | | | | | | | | | | -| R17 | | High Range | IO_L12N_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | -| R18 | | High Range | IO_L7P_T1_D09_14 | User IO | | 14 | | | | | | | | | | | | | | -| T1 | | High Range | IO_L17N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | -| T2 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | -| T3 | | High Range | IO_L11N_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | -| T4 | | High Range | IO_L12N_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | -| T5 | | High Range | IO_L12P_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | -| T6 | | High Range | IO_L23N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | -| T7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| T8 | | High Range | IO_L24N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | -| T9 | | High Range | IO_L24P_T3_A01_D17_14 | User IO | | 14 | | | | | | | | | | | | | | -| T10 | | High Range | IO_L24N_T3_A00_D16_14 | User IO | | 14 | | | | | | | | | | | | | | -| T11 | | High Range | IO_L19P_T3_A10_D26_14 | User IO | | 14 | | | | | | | | | | | | | | -| T12 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | -| T13 | | High Range | IO_L23P_T3_A03_D19_14 | User IO | | 14 | | | | | | | | | | | | | | -| T14 | | High Range | IO_L14P_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | -| T15 | | High Range | IO_L14N_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | -| T16 | | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | User IO | | 14 | | | | | | | | | | | | | | -| T17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| T18 | | High Range | IO_L7N_T1_D10_14 | User IO | | 14 | | | | | | | | | | | | | | -| U1 | | High Range | IO_L7P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | -| U2 | | High Range | IO_L9P_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | -| U3 | | High Range | IO_L8N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | -| U4 | | High Range | IO_L8P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | -| U5 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | -| U6 | | High Range | IO_L22N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | -| U7 | | High Range | IO_L22P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | -| U8 | | High Range | IO_25_34 | User IO | | 34 | | | | | | | | | | | | | | -| U9 | | High Range | IO_L21P_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | -| U10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| U11 | | High Range | IO_L19N_T3_A09_D25_VREF_14 | User IO | | 14 | | | | | | | | | | | | | | -| U12 | | High Range | IO_L20P_T3_A08_D24_14 | User IO | | 14 | | | | | | | | | | | | | | -| U13 | | High Range | IO_L23N_T3_A02_D18_14 | User IO | | 14 | | | | | | | | | | | | | | -| U14 | | High Range | IO_L22P_T3_A05_D21_14 | User IO | | 14 | | | | | | | | | | | | | | -| U15 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | -| U16 | | High Range | IO_L18P_T2_A12_D28_14 | User IO | | 14 | | | | | | | | | | | | | | -| U17 | | High Range | IO_L17P_T2_A14_D30_14 | User IO | | 14 | | | | | | | | | | | | | | -| U18 | | High Range | IO_L17N_T2_A13_D29_14 | User IO | | 14 | | | | | | | | | | | | | | -| V1 | | High Range | IO_L7N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | -| V2 | | High Range | IO_L9N_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | -| V3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| V4 | | High Range | IO_L10N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | -| V5 | | High Range | IO_L10P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | -| V6 | | High Range | IO_L20N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | -| V7 | | High Range | IO_L20P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | -| V8 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | -| V9 | | High Range | IO_L21N_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | -| V10 | | High Range | IO_L21P_T3_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | -| V11 | | High Range | IO_L21N_T3_DQS_A06_D22_14 | User IO | | 14 | | | | | | | | | | | | | | -| V12 | | High Range | IO_L20N_T3_A07_D23_14 | User IO | | 14 | | | | | | | | | | | | | | -| V13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| V14 | | High Range | IO_L22N_T3_A04_D20_14 | User IO | | 14 | | | | | | | | | | | | | | -| V15 | | High Range | IO_L16P_T2_CSI_B_14 | User IO | | 14 | | | | | | | | | | | | | | -| V16 | | High Range | IO_L16N_T2_A15_D31_14 | User IO | | 14 | | | | | | | | | | | | | | -| V17 | | High Range | IO_L18N_T2_A11_D27_14 | User IO | | 14 | | | | | | | | | | | | | | -| V18 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | -+------------+-------------+------------+------------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ ++------------+---------------+------------+------------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization | ++------------+---------------+------------+------------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +| A1 | | High Range | IO_L9N_T1_DQS_AD7N_35 | User IO | | 35 | | | | | | | | | | | | | | +| A2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A3 | vgaRed[0] | High Range | IO_L8N_T1_AD14N_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| A4 | vgaRed[3] | High Range | IO_L8P_T1_AD14P_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| A5 | vgaGrn[1] | High Range | IO_L3N_T0_DQS_AD5N_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| A6 | vgaGrn[3] | High Range | IO_L3P_T0_DQS_AD5P_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| A7 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| A8 | | High Range | IO_L12N_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| A9 | | High Range | IO_L14N_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| A10 | | High Range | IO_L14P_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| A11 | | High Range | IO_L4N_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| A12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A13 | | High Range | IO_L9P_T1_DQS_AD3P_15 | User IO | | 15 | | | | | | | | | | | | | | +| A14 | | High Range | IO_L9N_T1_DQS_AD3N_15 | User IO | | 15 | | | | | | | | | | | | | | +| A15 | | High Range | IO_L8P_T1_AD10P_15 | User IO | | 15 | | | | | | | | | | | | | | +| A16 | | High Range | IO_L8N_T1_AD10N_15 | User IO | | 15 | | | | | | | | | | | | | | +| A17 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | | +| A18 | | High Range | IO_L10N_T1_AD11N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B1 | | High Range | IO_L9P_T1_DQS_AD7P_35 | User IO | | 35 | | | | | | | | | | | | | | +| B2 | | High Range | IO_L10N_T1_AD15N_35 | User IO | | 35 | | | | | | | | | | | | | | +| B3 | | High Range | IO_L10P_T1_AD15P_35 | User IO | | 35 | | | | | | | | | | | | | | +| B4 | vgaRed[1] | High Range | IO_L7N_T1_AD6N_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| B5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B6 | vgaGrn[2] | High Range | IO_L2N_T0_AD12N_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| B7 | vgaBlu[0] | High Range | IO_L2P_T0_AD12P_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| B8 | | High Range | IO_L12P_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| B9 | | High Range | IO_L11N_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| B10 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| B11 | hSync | High Range | IO_L4P_T0_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| B12 | vSync | High Range | IO_L3N_T0_DQS_AD1N_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| B13 | | High Range | IO_L2P_T0_AD8P_15 | User IO | | 15 | | | | | | | | | | | | | | +| B14 | | High Range | IO_L2N_T0_AD8N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B16 | | High Range | IO_L7P_T1_AD2P_15 | User IO | | 15 | | | | | | | | | | | | | | +| B17 | | High Range | IO_L7N_T1_AD2N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B18 | | High Range | IO_L10P_T1_AD11P_15 | User IO | | 15 | | | | | | | | | | | | | | +| C1 | | High Range | IO_L16N_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| C2 | | High Range | IO_L16P_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| C3 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| C4 | | High Range | IO_L7P_T1_AD6P_35 | User IO | | 35 | | | | | | | | | | | | | | +| C5 | vgaRed[2] | High Range | IO_L1N_T0_AD4N_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| C6 | vgaGrn[0] | High Range | IO_L1P_T0_AD4P_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| C7 | vgaBlu[1] | High Range | IO_L4N_T0_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| C8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C9 | | High Range | IO_L11P_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C10 | | High Range | IO_L13N_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C11 | | High Range | IO_L13P_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C12 | btnCPUReset | High Range | IO_L3P_T0_DQS_AD1P_15 | INPUT | LVCMOS33 | 15 | | | | NONE | | FIXED | | | | NONE | | | | +| C13 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | | +| C14 | | High Range | IO_L1N_T0_AD0N_15 | User IO | | 15 | | | | | | | | | | | | | | +| C15 | | High Range | IO_L12N_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| C16 | | High Range | IO_L20P_T3_A20_15 | User IO | | 15 | | | | | | | | | | | | | | +| C17 | | High Range | IO_L20N_T3_A19_15 | User IO | | 15 | | | | | | | | | | | | | | +| C18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D2 | | High Range | IO_L14N_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| D3 | | High Range | IO_L12N_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| D4 | | High Range | IO_L11N_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| D5 | | High Range | IO_L11P_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| D6 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| D7 | vgaBlu[2] | High Range | IO_L6N_T0_VREF_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| D8 | vgaBlu[3] | High Range | IO_L4P_T0_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| D9 | | High Range | IO_L6N_T0_VREF_16 | User IO | | 16 | | | | | | | | | | | | | | +| D10 | | High Range | IO_L19N_T3_VREF_16 | User IO | | 16 | | | | | | | | | | | | | | +| D11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D12 | | High Range | IO_L6P_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| D13 | | High Range | IO_L6N_T0_VREF_15 | User IO | | 15 | | | | | | | | | | | | | | +| D14 | | High Range | IO_L1P_T0_AD0P_15 | User IO | | 15 | | | | | | | | | | | | | | +| D15 | | High Range | IO_L12P_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| D16 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | | +| D17 | | High Range | IO_L16N_T2_A27_15 | User IO | | 15 | | | | | | | | | | | | | | +| D18 | | High Range | IO_L21N_T3_DQS_A18_15 | User IO | | 15 | | | | | | | | | | | | | | +| E1 | | High Range | IO_L18N_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| E2 | | High Range | IO_L14P_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| E3 | sysClk | High Range | IO_L12P_T1_MRCC_35 | INPUT | LVCMOS33 | 35 | | | | NONE | | FIXED | | | | NONE | | | | +| E4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E5 | | High Range | IO_L5N_T0_AD13N_35 | User IO | | 35 | | | | | | | | | | | | | | +| E6 | | High Range | IO_L5P_T0_AD13P_35 | User IO | | 35 | | | | | | | | | | | | | | +| E7 | | High Range | IO_L6P_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| E8 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | | +| E9 | | Dedicated | CCLK_0 | Config | | 0 | | | | | | | | | | | | | | +| E10 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | | +| E11 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | | | +| E12 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | | | | +| E13 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | | | +| E14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E15 | | High Range | IO_L11P_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| E16 | | High Range | IO_L11N_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| E17 | | High Range | IO_L16P_T2_A28_15 | User IO | | 15 | | | | | | | | | | | | | | +| E18 | | High Range | IO_L21P_T3_DQS_15 | User IO | | 15 | | | | | | | | | | | | | | +| F1 | | High Range | IO_L18P_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| F2 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| F3 | | High Range | IO_L13N_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| F4 | | High Range | IO_L13P_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| F5 | | High Range | IO_0_35 | User IO | | 35 | | | | | | | | | | | | | | +| F6 | | High Range | IO_L19N_T3_VREF_35 | User IO | | 35 | | | | | | | | | | | | | | +| F7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| F9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F10 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| F11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| F13 | | High Range | IO_L5P_T0_AD9P_15 | User IO | | 15 | | | | | | | | | | | | | | +| F14 | | High Range | IO_L5N_T0_AD9N_15 | User IO | | 15 | | | | | | | | | | | | | | +| F15 | | High Range | IO_L14P_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| F16 | | High Range | IO_L14N_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| F17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F18 | | High Range | IO_L22N_T3_A16_15 | User IO | | 15 | | | | | | | | | | | | | | +| G1 | | High Range | IO_L17N_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| G2 | | High Range | IO_L15N_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| G3 | | High Range | IO_L20N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| G4 | | High Range | IO_L20P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| G5 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| G6 | | High Range | IO_L19P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| G7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| G8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| G10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| G12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G13 | | High Range | IO_0_15 | User IO | | 15 | | | | | | | | | | | | | | +| G14 | | High Range | IO_L15N_T2_DQS_ADV_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| G15 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | | +| G16 | | High Range | IO_L13N_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| G17 | | High Range | IO_L18N_T2_A23_15 | User IO | | 15 | | | | | | | | | | | | | | +| G18 | | High Range | IO_L22P_T3_A17_15 | User IO | | 15 | | | | | | | | | | | | | | +| H1 | | High Range | IO_L17P_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| H2 | | High Range | IO_L15P_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| H3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H4 | | High Range | IO_L21N_T3_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| H5 | | High Range | IO_L24N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| H6 | | High Range | IO_L24P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| H7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| H9 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| H10 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| H11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| H13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H14 | | High Range | IO_L15P_T2_DQS_15 | User IO | | 15 | | | | | | | | | | | | | | +| H15 | | High Range | IO_L19N_T3_A21_VREF_15 | User IO | | 15 | | | | | | | | | | | | | | +| H16 | | High Range | IO_L13P_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| H17 | | High Range | IO_L18P_T2_A24_15 | User IO | | 15 | | | | | | | | | | | | | | +| H18 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | | +| J1 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| J2 | | High Range | IO_L22N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| J3 | | High Range | IO_L22P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| J4 | | High Range | IO_L21P_T3_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| J5 | | High Range | IO_25_35 | User IO | | 35 | | | | | | | | | | | | | | +| J6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J9 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | | +| J10 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | | +| J11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J13 | | High Range | IO_L17N_T2_A25_15 | User IO | | 15 | | | | | | | | | | | | | | +| J14 | | High Range | IO_L19P_T3_A22_15 | User IO | | 15 | | | | | | | | | | | | | | +| J15 | | High Range | IO_L24N_T3_RS0_15 | User IO | | 15 | | | | | | | | | | | | | | +| J16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J17 | | High Range | IO_L23P_T3_FOE_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| J18 | | High Range | IO_L23N_T3_FWE_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| K1 | | High Range | IO_L23N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| K2 | | High Range | IO_L23P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| K3 | | High Range | IO_L2P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| K4 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | +| K5 | | High Range | IO_L5P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| K6 | | High Range | IO_0_34 | User IO | | 34 | | | | | | | | | | | | | | +| K7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| K9 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | | +| K10 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | | +| K11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| K13 | | High Range | IO_L17P_T2_A26_15 | User IO | | 15 | | | | | | | | | | | | | | +| K14 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | | +| K15 | | High Range | IO_L24P_T3_RS1_15 | User IO | | 15 | | | | | | | | | | | | | | +| K16 | | High Range | IO_25_15 | User IO | | 15 | | | | | | | | | | | | | | +| K17 | | High Range | IO_L1P_T0_D00_MOSI_14 | User IO | | 14 | | | | | | | | | | | | | | +| K18 | | High Range | IO_L1N_T0_D01_DIN_14 | User IO | | 14 | | | | | | | | | | | | | | +| L1 | | High Range | IO_L1P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| L2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L3 | | High Range | IO_L2N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| L4 | | High Range | IO_L5N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| L5 | | High Range | IO_L6N_T0_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | +| L6 | | High Range | IO_L6P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| L7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| L8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L9 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| L10 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| L11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| L12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L13 | | High Range | IO_L6P_T0_FCS_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| L14 | | High Range | IO_L2P_T0_D02_14 | User IO | | 14 | | | | | | | | | | | | | | +| L15 | | High Range | IO_L3P_T0_DQS_PUDC_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| L16 | | High Range | IO_L3N_T0_DQS_EMCCLK_14 | User IO | | 14 | | | | | | | | | | | | | | +| L17 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| L18 | | High Range | IO_L4P_T0_D04_14 | User IO | | 14 | | | | | | | | | | | | | | +| M1 | | High Range | IO_L1N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| M2 | | High Range | IO_L4N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| M3 | | High Range | IO_L4P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| M4 | | High Range | IO_L16P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| M5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M6 | | High Range | IO_L18P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| M7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| M9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| M11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| M13 | | High Range | IO_L6N_T0_D08_VREF_14 | User IO | | 14 | | | | | | | | | | | | | | +| M14 | | High Range | IO_L2N_T0_D03_14 | User IO | | 14 | | | | | | | | | | | | | | +| M15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M16 | | High Range | IO_L10P_T1_D14_14 | User IO | | 14 | | | | | | | | | | | | | | +| M17 | BtnR | High Range | IO_L10N_T1_D15_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | | +| M18 | BtnU | High Range | IO_L4N_T0_D05_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | | +| N1 | | High Range | IO_L3N_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| N2 | | High Range | IO_L3P_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| N3 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | +| N4 | | High Range | IO_L16N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| N5 | | High Range | IO_L13P_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| N6 | | High Range | IO_L18N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| N7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N13 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| N14 | | High Range | IO_L8P_T1_D11_14 | User IO | | 14 | | | | | | | | | | | | | | +| N15 | | High Range | IO_L11P_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| N16 | | High Range | IO_L11N_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| N17 | BtnC | High Range | IO_L9P_T1_DQS_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | | +| N18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P2 | | High Range | IO_L15P_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| P3 | | High Range | IO_L14N_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| P4 | | High Range | IO_L14P_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| P5 | | High Range | IO_L13N_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| P6 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | +| P7 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | | +| P8 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | | | | | | | | | | +| P9 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | | +| P10 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | | +| P11 | | Dedicated | M2_0 | Config | | 0 | | | | | | | | | | | | | | +| P12 | | Dedicated | M0_0 | Config | | 0 | | | | | | | | | | | | | | +| P13 | | Dedicated | M1_0 | Config | | 0 | | | | | | | | | | | | | | +| P14 | | High Range | IO_L8N_T1_D12_14 | User IO | | 14 | | | | | | | | | | | | | | +| P15 | | High Range | IO_L13P_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| P16 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| P17 | BtnL | High Range | IO_L12P_T1_MRCC_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | | +| P18 | BtnD | High Range | IO_L9N_T1_DQS_D13_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | | +| R1 | | High Range | IO_L17P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| R2 | | High Range | IO_L15N_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| R3 | | High Range | IO_L11P_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| R4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R5 | | High Range | IO_L19N_T3_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | +| R6 | | High Range | IO_L19P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| R7 | | High Range | IO_L23P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| R8 | | High Range | IO_L24P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| R9 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | | +| R10 | | High Range | IO_25_14 | User IO | | 14 | | | | | | | | | | | | | | +| R11 | | High Range | IO_0_14 | User IO | | 14 | | | | | | | | | | | | | | +| R12 | | High Range | IO_L5P_T0_D06_14 | User IO | | 14 | | | | | | | | | | | | | | +| R13 | | High Range | IO_L5N_T0_D07_14 | User IO | | 14 | | | | | | | | | | | | | | +| R14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R15 | | High Range | IO_L13N_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| R16 | | High Range | IO_L15P_T2_DQS_RDWR_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| R17 | | High Range | IO_L12N_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| R18 | | High Range | IO_L7P_T1_D09_14 | User IO | | 14 | | | | | | | | | | | | | | +| T1 | | High Range | IO_L17N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| T2 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | +| T3 | | High Range | IO_L11N_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| T4 | | High Range | IO_L12N_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| T5 | | High Range | IO_L12P_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| T6 | | High Range | IO_L23N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| T7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T8 | | High Range | IO_L24N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| T9 | | High Range | IO_L24P_T3_A01_D17_14 | User IO | | 14 | | | | | | | | | | | | | | +| T10 | | High Range | IO_L24N_T3_A00_D16_14 | User IO | | 14 | | | | | | | | | | | | | | +| T11 | | High Range | IO_L19P_T3_A10_D26_14 | User IO | | 14 | | | | | | | | | | | | | | +| T12 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| T13 | | High Range | IO_L23P_T3_A03_D19_14 | User IO | | 14 | | | | | | | | | | | | | | +| T14 | | High Range | IO_L14P_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| T15 | | High Range | IO_L14N_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| T16 | | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| T17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T18 | | High Range | IO_L7N_T1_D10_14 | User IO | | 14 | | | | | | | | | | | | | | +| U1 | | High Range | IO_L7P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| U2 | | High Range | IO_L9P_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| U3 | | High Range | IO_L8N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| U4 | | High Range | IO_L8P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| U5 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | +| U6 | | High Range | IO_L22N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| U7 | | High Range | IO_L22P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| U8 | | High Range | IO_25_34 | User IO | | 34 | | | | | | | | | | | | | | +| U9 | | High Range | IO_L21P_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| U10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| U11 | | High Range | IO_L19N_T3_A09_D25_VREF_14 | User IO | | 14 | | | | | | | | | | | | | | +| U12 | | High Range | IO_L20P_T3_A08_D24_14 | User IO | | 14 | | | | | | | | | | | | | | +| U13 | | High Range | IO_L23N_T3_A02_D18_14 | User IO | | 14 | | | | | | | | | | | | | | +| U14 | | High Range | IO_L22P_T3_A05_D21_14 | User IO | | 14 | | | | | | | | | | | | | | +| U15 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| U16 | | High Range | IO_L18P_T2_A12_D28_14 | User IO | | 14 | | | | | | | | | | | | | | +| U17 | | High Range | IO_L17P_T2_A14_D30_14 | User IO | | 14 | | | | | | | | | | | | | | +| U18 | | High Range | IO_L17N_T2_A13_D29_14 | User IO | | 14 | | | | | | | | | | | | | | +| V1 | | High Range | IO_L7N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| V2 | | High Range | IO_L9N_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| V3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V4 | | High Range | IO_L10N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| V5 | | High Range | IO_L10P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| V6 | | High Range | IO_L20N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| V7 | | High Range | IO_L20P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| V8 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | +| V9 | | High Range | IO_L21N_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| V10 | switch15Debug | High Range | IO_L21P_T3_DQS_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | | +| V11 | | High Range | IO_L21N_T3_DQS_A06_D22_14 | User IO | | 14 | | | | | | | | | | | | | | +| V12 | | High Range | IO_L20N_T3_A07_D23_14 | User IO | | 14 | | | | | | | | | | | | | | +| V13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V14 | | High Range | IO_L22N_T3_A04_D20_14 | User IO | | 14 | | | | | | | | | | | | | | +| V15 | | High Range | IO_L16P_T2_CSI_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| V16 | | High Range | IO_L16N_T2_A15_D31_14 | User IO | | 14 | | | | | | | | | | | | | | +| V17 | | High Range | IO_L18N_T2_A11_D27_14 | User IO | | 14 | | | | | | | | | | | | | | +| V18 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | ++------------+---------------+------------+------------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ * Default value ** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements. diff --git a/vga.runs/impl_1/vga_methodology_drc_routed.pb b/vga.runs/impl_1/vga_methodology_drc_routed.pb index d149743..a10a2e5 100644 Binary files a/vga.runs/impl_1/vga_methodology_drc_routed.pb and b/vga.runs/impl_1/vga_methodology_drc_routed.pb differ diff --git a/vga.runs/impl_1/vga_methodology_drc_routed.rpt b/vga.runs/impl_1/vga_methodology_drc_routed.rpt index 188e6b0..dbc92b9 100644 --- a/vga.runs/impl_1/vga_methodology_drc_routed.rpt +++ b/vga.runs/impl_1/vga_methodology_drc_routed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. ----------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 -| Date : Thu Apr 18 03:15:49 2024 +| Date : Mon Apr 22 21:25:09 2024 | Host : me running 64-bit major release (build 9200) | Command : report_methodology -file vga_methodology_drc_routed.rpt -pb vga_methodology_drc_routed.pb -rpx vga_methodology_drc_routed.rpx | Design : vga @@ -23,12 +23,15 @@ Table of Contents Floorplan: design_1 Design limits: Max violations: - Violations found: 218 -+-----------+------------------+-----------------------------+------------+ -| Rule | Severity | Description | Violations | -+-----------+------------------+-----------------------------+------------+ -| TIMING-17 | Critical Warning | Non-clocked sequential cell | 218 | -+-----------+------------------+-----------------------------+------------+ + Violations found: 1295 ++-----------+------------------+--------------------------------+------------+ +| Rule | Severity | Description | Violations | ++-----------+------------------+--------------------------------+------------+ +| TIMING-17 | Critical Warning | Non-clocked sequential cell | 1000 | +| LUTAR-1 | Warning | LUT drives async reset alert | 196 | +| TIMING-20 | Warning | Non-clocked latch | 98 | +| LATCH-1 | Advisory | Existing latches in the design | 1 | ++-----------+------------------+--------------------------------+------------+ 2. REPORT DETAILS ----------------- @@ -69,1057 +72,6540 @@ Related violations: TIMING-17#8 Critical Warning Non-clocked sequential cell -The clock pin corner_border_check_gfx/paletteIndex_reg[0]/C is not reached by a timing clock +The clock pin core_design/animateResetTimer_reg[0]/C is not reached by a timing clock Related violations: TIMING-17#9 Critical Warning Non-clocked sequential cell -The clock pin corner_border_check_gfx/paletteIndex_reg[1]/C is not reached by a timing clock +The clock pin core_design/animateResetTimer_reg[10]/C is not reached by a timing clock Related violations: TIMING-17#10 Critical Warning Non-clocked sequential cell -The clock pin corner_border_check_gfx/paletteIndex_reg[2]/C is not reached by a timing clock +The clock pin core_design/animateResetTimer_reg[11]/C is not reached by a timing clock Related violations: TIMING-17#11 Critical Warning Non-clocked sequential cell -The clock pin corner_border_check_gfx/valid_reg/C is not reached by a timing clock +The clock pin core_design/animateResetTimer_reg[12]/C is not reached by a timing clock Related violations: TIMING-17#12 Critical Warning Non-clocked sequential cell -The clock pin genblk1[0].red_piece_gfx/paletteIndex_reg[0]/C is not reached by a timing clock +The clock pin core_design/animateResetTimer_reg[13]/C is not reached by a timing clock Related violations: TIMING-17#13 Critical Warning Non-clocked sequential cell -The clock pin genblk1[0].red_piece_gfx/paletteIndex_reg[1]/C is not reached by a timing clock +The clock pin core_design/animateResetTimer_reg[14]/C is not reached by a timing clock Related violations: TIMING-17#14 Critical Warning Non-clocked sequential cell -The clock pin genblk1[0].red_piece_gfx/valid_reg/C is not reached by a timing clock +The clock pin core_design/animateResetTimer_reg[15]/C is not reached by a timing clock Related violations: TIMING-17#15 Critical Warning Non-clocked sequential cell -The clock pin genblk1[10].red_piece_gfx/paletteIndex_reg[0]/C is not reached by a timing clock +The clock pin core_design/animateResetTimer_reg[16]/C is not reached by a timing clock Related violations: TIMING-17#16 Critical Warning Non-clocked sequential cell -The clock pin genblk1[10].red_piece_gfx/paletteIndex_reg[1]/C is not reached by a timing clock +The clock pin core_design/animateResetTimer_reg[17]/C is not reached by a timing clock Related violations: TIMING-17#17 Critical Warning Non-clocked sequential cell -The clock pin genblk1[10].red_piece_gfx/valid_reg/C is not reached by a timing clock +The clock pin core_design/animateResetTimer_reg[18]/C is not reached by a timing clock Related violations: TIMING-17#18 Critical Warning Non-clocked sequential cell -The clock pin genblk1[11].red_piece_gfx/paletteIndex_reg[0]/C is not reached by a timing clock +The clock pin core_design/animateResetTimer_reg[19]/C is not reached by a timing clock Related violations: TIMING-17#19 Critical Warning Non-clocked sequential cell -The clock pin genblk1[11].red_piece_gfx/paletteIndex_reg[1]/C is not reached by a timing clock +The clock pin core_design/animateResetTimer_reg[1]/C is not reached by a timing clock Related violations: TIMING-17#20 Critical Warning Non-clocked sequential cell -The clock pin genblk1[11].red_piece_gfx/valid_reg/C is not reached by a timing clock +The clock pin core_design/animateResetTimer_reg[20]/C is not reached by a timing clock Related violations: TIMING-17#21 Critical Warning Non-clocked sequential cell -The clock pin genblk1[12].red_piece_gfx/paletteIndex_reg[0]/C is not reached by a timing clock +The clock pin core_design/animateResetTimer_reg[21]/C is not reached by a timing clock Related violations: TIMING-17#22 Critical Warning Non-clocked sequential cell -The clock pin genblk1[12].red_piece_gfx/paletteIndex_reg[1]/C is not reached by a timing clock +The clock pin core_design/animateResetTimer_reg[22]/C is not reached by a timing clock Related violations: TIMING-17#23 Critical Warning Non-clocked sequential cell -The clock pin genblk1[12].red_piece_gfx/valid_reg/C is not reached by a timing clock +The clock pin core_design/animateResetTimer_reg[23]/C is not reached by a timing clock Related violations: TIMING-17#24 Critical Warning Non-clocked sequential cell -The clock pin genblk1[13].red_piece_gfx/paletteIndex_reg[0]/C is not reached by a timing clock +The clock pin core_design/animateResetTimer_reg[24]/C is not reached by a timing clock Related violations: TIMING-17#25 Critical Warning Non-clocked sequential cell -The clock pin genblk1[13].red_piece_gfx/paletteIndex_reg[1]/C is not reached by a timing clock +The clock pin core_design/animateResetTimer_reg[25]/C is not reached by a timing clock Related violations: TIMING-17#26 Critical Warning Non-clocked sequential cell -The clock pin genblk1[13].red_piece_gfx/valid_reg/C is not reached by a timing clock +The clock pin core_design/animateResetTimer_reg[26]/C is not reached by a timing clock Related violations: TIMING-17#27 Critical Warning Non-clocked sequential cell -The clock pin genblk1[14].red_piece_gfx/paletteIndex_reg[0]/C is not reached by a timing clock +The clock pin core_design/animateResetTimer_reg[27]/C is not reached by a timing clock Related violations: TIMING-17#28 Critical Warning Non-clocked sequential cell -The clock pin genblk1[14].red_piece_gfx/paletteIndex_reg[1]/C is not reached by a timing clock +The clock pin core_design/animateResetTimer_reg[28]/C is not reached by a timing clock Related violations: TIMING-17#29 Critical Warning Non-clocked sequential cell -The clock pin genblk1[14].red_piece_gfx/valid_reg/C is not reached by a timing clock +The clock pin core_design/animateResetTimer_reg[29]/C is not reached by a timing clock Related violations: TIMING-17#30 Critical Warning Non-clocked sequential cell -The clock pin genblk1[15].red_piece_gfx/paletteIndex_reg[0]/C is not reached by a timing clock +The clock pin core_design/animateResetTimer_reg[2]/C is not reached by a timing clock Related violations: TIMING-17#31 Critical Warning Non-clocked sequential cell -The clock pin genblk1[15].red_piece_gfx/paletteIndex_reg[1]/C is not reached by a timing clock +The clock pin core_design/animateResetTimer_reg[30]/C is not reached by a timing clock Related violations: TIMING-17#32 Critical Warning Non-clocked sequential cell -The clock pin genblk1[15].red_piece_gfx/valid_reg/C is not reached by a timing clock +The clock pin core_design/animateResetTimer_reg[31]/C is not reached by a timing clock Related violations: TIMING-17#33 Critical Warning Non-clocked sequential cell -The clock pin genblk1[16].red_piece_gfx/paletteIndex_reg[0]/C is not reached by a timing clock +The clock pin core_design/animateResetTimer_reg[3]/C is not reached by a timing clock Related violations: TIMING-17#34 Critical Warning Non-clocked sequential cell -The clock pin genblk1[16].red_piece_gfx/paletteIndex_reg[1]/C is not reached by a timing clock +The clock pin core_design/animateResetTimer_reg[4]/C is not reached by a timing clock Related violations: TIMING-17#35 Critical Warning Non-clocked sequential cell -The clock pin genblk1[16].red_piece_gfx/valid_reg/C is not reached by a timing clock +The clock pin core_design/animateResetTimer_reg[5]/C is not reached by a timing clock Related violations: TIMING-17#36 Critical Warning Non-clocked sequential cell -The clock pin genblk1[17].red_piece_gfx/paletteIndex_reg[0]/C is not reached by a timing clock +The clock pin core_design/animateResetTimer_reg[6]/C is not reached by a timing clock Related violations: TIMING-17#37 Critical Warning Non-clocked sequential cell -The clock pin genblk1[17].red_piece_gfx/paletteIndex_reg[1]/C is not reached by a timing clock +The clock pin core_design/animateResetTimer_reg[7]/C is not reached by a timing clock Related violations: TIMING-17#38 Critical Warning Non-clocked sequential cell -The clock pin genblk1[17].red_piece_gfx/valid_reg/C is not reached by a timing clock +The clock pin core_design/animateResetTimer_reg[8]/C is not reached by a timing clock Related violations: TIMING-17#39 Critical Warning Non-clocked sequential cell -The clock pin genblk1[18].red_piece_gfx/paletteIndex_reg[0]/C is not reached by a timing clock +The clock pin core_design/animateResetTimer_reg[9]/C is not reached by a timing clock Related violations: TIMING-17#40 Critical Warning Non-clocked sequential cell -The clock pin genblk1[18].red_piece_gfx/paletteIndex_reg[1]/C is not reached by a timing clock +The clock pin core_design/boardYOffset_reg[0]/C is not reached by a timing clock Related violations: TIMING-17#41 Critical Warning Non-clocked sequential cell -The clock pin genblk1[18].red_piece_gfx/valid_reg/C is not reached by a timing clock +The clock pin core_design/boardYOffset_reg[1]/C is not reached by a timing clock Related violations: TIMING-17#42 Critical Warning Non-clocked sequential cell -The clock pin genblk1[19].red_piece_gfx/paletteIndex_reg[0]/C is not reached by a timing clock +The clock pin core_design/boardYOffset_reg[2]/C is not reached by a timing clock Related violations: TIMING-17#43 Critical Warning Non-clocked sequential cell -The clock pin genblk1[19].red_piece_gfx/paletteIndex_reg[1]/C is not reached by a timing clock +The clock pin core_design/boardYOffset_reg[3]/C is not reached by a timing clock Related violations: TIMING-17#44 Critical Warning Non-clocked sequential cell -The clock pin genblk1[19].red_piece_gfx/valid_reg/C is not reached by a timing clock +The clock pin core_design/boardYOffset_reg[4]/C is not reached by a timing clock Related violations: TIMING-17#45 Critical Warning Non-clocked sequential cell -The clock pin genblk1[1].red_piece_gfx/paletteIndex_reg[0]/C is not reached by a timing clock +The clock pin core_design/boardYOffset_reg[5]/C is not reached by a timing clock Related violations: TIMING-17#46 Critical Warning Non-clocked sequential cell -The clock pin genblk1[1].red_piece_gfx/paletteIndex_reg[1]/C is not reached by a timing clock +The clock pin core_design/boardYOffset_reg[6]/C is not reached by a timing clock Related violations: TIMING-17#47 Critical Warning Non-clocked sequential cell -The clock pin genblk1[1].red_piece_gfx/valid_reg/C is not reached by a timing clock +The clock pin core_design/boardYOffset_reg[7]/C is not reached by a timing clock Related violations: TIMING-17#48 Critical Warning Non-clocked sequential cell -The clock pin genblk1[20].red_piece_gfx/paletteIndex_reg[0]/C is not reached by a timing clock +The clock pin core_design/boardYOffset_reg[8]/C is not reached by a timing clock Related violations: TIMING-17#49 Critical Warning Non-clocked sequential cell -The clock pin genblk1[20].red_piece_gfx/paletteIndex_reg[1]/C is not reached by a timing clock +The clock pin core_design/boardYOffset_reg[9]/C is not reached by a timing clock Related violations: TIMING-17#50 Critical Warning Non-clocked sequential cell -The clock pin genblk1[20].red_piece_gfx/valid_reg/C is not reached by a timing clock +The clock pin core_design/board_reg[0][0]/C is not reached by a timing clock Related violations: TIMING-17#51 Critical Warning Non-clocked sequential cell -The clock pin genblk1[2].red_piece_gfx/paletteIndex_reg[0]/C is not reached by a timing clock +The clock pin core_design/board_reg[0][1]/C is not reached by a timing clock Related violations: TIMING-17#52 Critical Warning Non-clocked sequential cell -The clock pin genblk1[2].red_piece_gfx/paletteIndex_reg[1]/C is not reached by a timing clock +The clock pin core_design/board_reg[10][0]/C is not reached by a timing clock Related violations: TIMING-17#53 Critical Warning Non-clocked sequential cell -The clock pin genblk1[2].red_piece_gfx/valid_reg/C is not reached by a timing clock +The clock pin core_design/board_reg[10][1]/C is not reached by a timing clock Related violations: TIMING-17#54 Critical Warning Non-clocked sequential cell -The clock pin genblk1[3].red_piece_gfx/paletteIndex_reg[0]/C is not reached by a timing clock +The clock pin core_design/board_reg[11][0]/C is not reached by a timing clock Related violations: TIMING-17#55 Critical Warning Non-clocked sequential cell -The clock pin genblk1[3].red_piece_gfx/paletteIndex_reg[1]/C is not reached by a timing clock +The clock pin core_design/board_reg[11][0]_rep/C is not reached by a timing clock Related violations: TIMING-17#56 Critical Warning Non-clocked sequential cell -The clock pin genblk1[3].red_piece_gfx/valid_reg/C is not reached by a timing clock +The clock pin core_design/board_reg[11][0]_rep__0/C is not reached by a timing clock Related violations: TIMING-17#57 Critical Warning Non-clocked sequential cell -The clock pin genblk1[4].red_piece_gfx/paletteIndex_reg[0]/C is not reached by a timing clock +The clock pin core_design/board_reg[11][1]/C is not reached by a timing clock Related violations: TIMING-17#58 Critical Warning Non-clocked sequential cell -The clock pin genblk1[4].red_piece_gfx/paletteIndex_reg[1]/C is not reached by a timing clock +The clock pin core_design/board_reg[11][1]_rep/C is not reached by a timing clock Related violations: TIMING-17#59 Critical Warning Non-clocked sequential cell -The clock pin genblk1[4].red_piece_gfx/valid_reg/C is not reached by a timing clock +The clock pin core_design/board_reg[11][1]_rep__0/C is not reached by a timing clock Related violations: TIMING-17#60 Critical Warning Non-clocked sequential cell -The clock pin genblk1[5].red_piece_gfx/paletteIndex_reg[0]/C is not reached by a timing clock +The clock pin core_design/board_reg[12][0]/C is not reached by a timing clock Related violations: TIMING-17#61 Critical Warning Non-clocked sequential cell -The clock pin genblk1[5].red_piece_gfx/paletteIndex_reg[1]/C is not reached by a timing clock +The clock pin core_design/board_reg[12][1]/C is not reached by a timing clock Related violations: TIMING-17#62 Critical Warning Non-clocked sequential cell -The clock pin genblk1[5].red_piece_gfx/valid_reg/C is not reached by a timing clock +The clock pin core_design/board_reg[13][0]/C is not reached by a timing clock Related violations: TIMING-17#63 Critical Warning Non-clocked sequential cell -The clock pin genblk1[6].red_piece_gfx/paletteIndex_reg[0]/C is not reached by a timing clock +The clock pin core_design/board_reg[13][1]/C is not reached by a timing clock Related violations: TIMING-17#64 Critical Warning Non-clocked sequential cell -The clock pin genblk1[6].red_piece_gfx/paletteIndex_reg[1]/C is not reached by a timing clock +The clock pin core_design/board_reg[14][0]/C is not reached by a timing clock Related violations: TIMING-17#65 Critical Warning Non-clocked sequential cell -The clock pin genblk1[6].red_piece_gfx/valid_reg/C is not reached by a timing clock +The clock pin core_design/board_reg[14][1]/C is not reached by a timing clock Related violations: TIMING-17#66 Critical Warning Non-clocked sequential cell -The clock pin genblk1[7].red_piece_gfx/paletteIndex_reg[0]/C is not reached by a timing clock +The clock pin core_design/board_reg[15][0]/C is not reached by a timing clock Related violations: TIMING-17#67 Critical Warning Non-clocked sequential cell -The clock pin genblk1[7].red_piece_gfx/paletteIndex_reg[1]/C is not reached by a timing clock +The clock pin core_design/board_reg[15][0]_rep/C is not reached by a timing clock Related violations: TIMING-17#68 Critical Warning Non-clocked sequential cell -The clock pin genblk1[7].red_piece_gfx/valid_reg/C is not reached by a timing clock +The clock pin core_design/board_reg[15][0]_rep__0/C is not reached by a timing clock Related violations: TIMING-17#69 Critical Warning Non-clocked sequential cell -The clock pin genblk1[8].red_piece_gfx/paletteIndex_reg[0]/C is not reached by a timing clock +The clock pin core_design/board_reg[15][1]/C is not reached by a timing clock Related violations: TIMING-17#70 Critical Warning Non-clocked sequential cell -The clock pin genblk1[8].red_piece_gfx/paletteIndex_reg[1]/C is not reached by a timing clock +The clock pin core_design/board_reg[15][1]_rep/C is not reached by a timing clock Related violations: TIMING-17#71 Critical Warning Non-clocked sequential cell -The clock pin genblk1[8].red_piece_gfx/valid_reg/C is not reached by a timing clock +The clock pin core_design/board_reg[15][1]_rep__0/C is not reached by a timing clock Related violations: TIMING-17#72 Critical Warning Non-clocked sequential cell -The clock pin genblk1[9].red_piece_gfx/paletteIndex_reg[0]/C is not reached by a timing clock +The clock pin core_design/board_reg[16][0]/C is not reached by a timing clock Related violations: TIMING-17#73 Critical Warning Non-clocked sequential cell -The clock pin genblk1[9].red_piece_gfx/paletteIndex_reg[1]/C is not reached by a timing clock +The clock pin core_design/board_reg[16][0]_rep/C is not reached by a timing clock Related violations: TIMING-17#74 Critical Warning Non-clocked sequential cell -The clock pin genblk1[9].red_piece_gfx/valid_reg/C is not reached by a timing clock +The clock pin core_design/board_reg[16][0]_rep__0/C is not reached by a timing clock Related violations: TIMING-17#75 Critical Warning Non-clocked sequential cell -The clock pin genblk2[0].yellow_piece_gfx/paletteIndex_reg[1]/C is not reached by a timing clock +The clock pin core_design/board_reg[16][1]/C is not reached by a timing clock Related violations: TIMING-17#76 Critical Warning Non-clocked sequential cell -The clock pin genblk2[0].yellow_piece_gfx/paletteIndex_reg[3]/C is not reached by a timing clock +The clock pin core_design/board_reg[16][1]_rep/C is not reached by a timing clock Related violations: TIMING-17#77 Critical Warning Non-clocked sequential cell -The clock pin genblk2[0].yellow_piece_gfx/valid_reg/C is not reached by a timing clock +The clock pin core_design/board_reg[16][1]_rep__0/C is not reached by a timing clock Related violations: TIMING-17#78 Critical Warning Non-clocked sequential cell -The clock pin genblk2[10].yellow_piece_gfx/paletteIndex_reg[1]/C is not reached by a timing clock +The clock pin core_design/board_reg[17][0]/C is not reached by a timing clock Related violations: TIMING-17#79 Critical Warning Non-clocked sequential cell -The clock pin genblk2[10].yellow_piece_gfx/paletteIndex_reg[3]/C is not reached by a timing clock +The clock pin core_design/board_reg[17][0]_rep/C is not reached by a timing clock Related violations: TIMING-17#80 Critical Warning Non-clocked sequential cell -The clock pin genblk2[10].yellow_piece_gfx/valid_reg/C is not reached by a timing clock +The clock pin core_design/board_reg[17][0]_rep__0/C is not reached by a timing clock Related violations: TIMING-17#81 Critical Warning Non-clocked sequential cell -The clock pin genblk2[11].yellow_piece_gfx/paletteIndex_reg[1]/C is not reached by a timing clock +The clock pin core_design/board_reg[17][0]_rep__1/C is not reached by a timing clock Related violations: TIMING-17#82 Critical Warning Non-clocked sequential cell -The clock pin genblk2[11].yellow_piece_gfx/paletteIndex_reg[3]/C is not reached by a timing clock +The clock pin core_design/board_reg[17][1]/C is not reached by a timing clock Related violations: TIMING-17#83 Critical Warning Non-clocked sequential cell -The clock pin genblk2[11].yellow_piece_gfx/valid_reg/C is not reached by a timing clock +The clock pin core_design/board_reg[17][1]_rep/C is not reached by a timing clock Related violations: TIMING-17#84 Critical Warning Non-clocked sequential cell -The clock pin genblk2[12].yellow_piece_gfx/paletteIndex_reg[1]/C is not reached by a timing clock +The clock pin core_design/board_reg[17][1]_rep__0/C is not reached by a timing clock Related violations: TIMING-17#85 Critical Warning Non-clocked sequential cell -The clock pin genblk2[12].yellow_piece_gfx/paletteIndex_reg[3]/C is not reached by a timing clock +The clock pin core_design/board_reg[18][0]/C is not reached by a timing clock Related violations: TIMING-17#86 Critical Warning Non-clocked sequential cell -The clock pin genblk2[12].yellow_piece_gfx/valid_reg/C is not reached by a timing clock +The clock pin core_design/board_reg[18][0]_rep/C is not reached by a timing clock Related violations: TIMING-17#87 Critical Warning Non-clocked sequential cell -The clock pin genblk2[13].yellow_piece_gfx/paletteIndex_reg[1]/C is not reached by a timing clock +The clock pin core_design/board_reg[18][0]_rep__0/C is not reached by a timing clock Related violations: TIMING-17#88 Critical Warning Non-clocked sequential cell -The clock pin genblk2[13].yellow_piece_gfx/paletteIndex_reg[3]/C is not reached by a timing clock +The clock pin core_design/board_reg[18][1]/C is not reached by a timing clock Related violations: TIMING-17#89 Critical Warning Non-clocked sequential cell -The clock pin genblk2[13].yellow_piece_gfx/valid_reg/C is not reached by a timing clock +The clock pin core_design/board_reg[18][1]_rep/C is not reached by a timing clock Related violations: TIMING-17#90 Critical Warning Non-clocked sequential cell -The clock pin genblk2[14].yellow_piece_gfx/paletteIndex_reg[1]/C is not reached by a timing clock +The clock pin core_design/board_reg[18][1]_rep__0/C is not reached by a timing clock Related violations: TIMING-17#91 Critical Warning Non-clocked sequential cell -The clock pin genblk2[14].yellow_piece_gfx/paletteIndex_reg[3]/C is not reached by a timing clock +The clock pin core_design/board_reg[19][0]/C is not reached by a timing clock Related violations: TIMING-17#92 Critical Warning Non-clocked sequential cell -The clock pin genblk2[14].yellow_piece_gfx/valid_reg/C is not reached by a timing clock +The clock pin core_design/board_reg[19][0]_rep/C is not reached by a timing clock Related violations: TIMING-17#93 Critical Warning Non-clocked sequential cell -The clock pin genblk2[15].yellow_piece_gfx/paletteIndex_reg[1]/C is not reached by a timing clock +The clock pin core_design/board_reg[19][0]_rep__0/C is not reached by a timing clock Related violations: TIMING-17#94 Critical Warning Non-clocked sequential cell -The clock pin genblk2[15].yellow_piece_gfx/paletteIndex_reg[3]/C is not reached by a timing clock +The clock pin core_design/board_reg[19][1]/C is not reached by a timing clock Related violations: TIMING-17#95 Critical Warning Non-clocked sequential cell -The clock pin genblk2[15].yellow_piece_gfx/valid_reg/C is not reached by a timing clock +The clock pin core_design/board_reg[19][1]_rep/C is not reached by a timing clock Related violations: TIMING-17#96 Critical Warning Non-clocked sequential cell -The clock pin genblk2[16].yellow_piece_gfx/paletteIndex_reg[1]/C is not reached by a timing clock +The clock pin core_design/board_reg[19][1]_rep__0/C is not reached by a timing clock Related violations: TIMING-17#97 Critical Warning Non-clocked sequential cell -The clock pin genblk2[16].yellow_piece_gfx/paletteIndex_reg[3]/C is not reached by a timing clock +The clock pin core_design/board_reg[1][0]/C is not reached by a timing clock Related violations: TIMING-17#98 Critical Warning Non-clocked sequential cell -The clock pin genblk2[16].yellow_piece_gfx/valid_reg/C is not reached by a timing clock +The clock pin core_design/board_reg[1][1]/C is not reached by a timing clock Related violations: TIMING-17#99 Critical Warning Non-clocked sequential cell -The clock pin genblk2[17].yellow_piece_gfx/paletteIndex_reg[1]/C is not reached by a timing clock +The clock pin core_design/board_reg[20][0]/C is not reached by a timing clock Related violations: TIMING-17#100 Critical Warning Non-clocked sequential cell -The clock pin genblk2[17].yellow_piece_gfx/paletteIndex_reg[3]/C is not reached by a timing clock +The clock pin core_design/board_reg[20][1]/C is not reached by a timing clock Related violations: TIMING-17#101 Critical Warning Non-clocked sequential cell -The clock pin genblk2[17].yellow_piece_gfx/valid_reg/C is not reached by a timing clock +The clock pin core_design/board_reg[21][0]/C is not reached by a timing clock Related violations: TIMING-17#102 Critical Warning Non-clocked sequential cell -The clock pin genblk2[18].yellow_piece_gfx/paletteIndex_reg[1]/C is not reached by a timing clock +The clock pin core_design/board_reg[21][1]/C is not reached by a timing clock Related violations: TIMING-17#103 Critical Warning Non-clocked sequential cell -The clock pin genblk2[18].yellow_piece_gfx/paletteIndex_reg[3]/C is not reached by a timing clock +The clock pin core_design/board_reg[22][0]/C is not reached by a timing clock Related violations: TIMING-17#104 Critical Warning Non-clocked sequential cell -The clock pin genblk2[18].yellow_piece_gfx/valid_reg/C is not reached by a timing clock +The clock pin core_design/board_reg[22][0]_rep/C is not reached by a timing clock Related violations: TIMING-17#105 Critical Warning Non-clocked sequential cell -The clock pin genblk2[19].yellow_piece_gfx/paletteIndex_reg[1]/C is not reached by a timing clock +The clock pin core_design/board_reg[22][0]_rep__0/C is not reached by a timing clock Related violations: TIMING-17#106 Critical Warning Non-clocked sequential cell -The clock pin genblk2[19].yellow_piece_gfx/paletteIndex_reg[3]/C is not reached by a timing clock +The clock pin core_design/board_reg[22][1]/C is not reached by a timing clock Related violations: TIMING-17#107 Critical Warning Non-clocked sequential cell -The clock pin genblk2[19].yellow_piece_gfx/valid_reg/C is not reached by a timing clock +The clock pin core_design/board_reg[22][1]_rep/C is not reached by a timing clock Related violations: TIMING-17#108 Critical Warning Non-clocked sequential cell -The clock pin genblk2[1].yellow_piece_gfx/paletteIndex_reg[1]/C is not reached by a timing clock +The clock pin core_design/board_reg[22][1]_rep__0/C is not reached by a timing clock Related violations: TIMING-17#109 Critical Warning Non-clocked sequential cell -The clock pin genblk2[1].yellow_piece_gfx/paletteIndex_reg[3]/C is not reached by a timing clock +The clock pin core_design/board_reg[23][0]/C is not reached by a timing clock Related violations: TIMING-17#110 Critical Warning Non-clocked sequential cell -The clock pin genblk2[1].yellow_piece_gfx/valid_reg/C is not reached by a timing clock +The clock pin core_design/board_reg[23][0]_rep/C is not reached by a timing clock Related violations: TIMING-17#111 Critical Warning Non-clocked sequential cell -The clock pin genblk2[20].yellow_piece_gfx/paletteIndex_reg[1]/C is not reached by a timing clock +The clock pin core_design/board_reg[23][0]_rep__0/C is not reached by a timing clock Related violations: TIMING-17#112 Critical Warning Non-clocked sequential cell -The clock pin genblk2[20].yellow_piece_gfx/paletteIndex_reg[3]/C is not reached by a timing clock +The clock pin core_design/board_reg[23][1]/C is not reached by a timing clock Related violations: TIMING-17#113 Critical Warning Non-clocked sequential cell -The clock pin genblk2[20].yellow_piece_gfx/valid_reg/C is not reached by a timing clock +The clock pin core_design/board_reg[23][1]_rep/C is not reached by a timing clock Related violations: TIMING-17#114 Critical Warning Non-clocked sequential cell -The clock pin genblk2[2].yellow_piece_gfx/paletteIndex_reg[1]/C is not reached by a timing clock +The clock pin core_design/board_reg[23][1]_rep__0/C is not reached by a timing clock Related violations: TIMING-17#115 Critical Warning Non-clocked sequential cell -The clock pin genblk2[2].yellow_piece_gfx/paletteIndex_reg[3]/C is not reached by a timing clock +The clock pin core_design/board_reg[24][0]/C is not reached by a timing clock Related violations: TIMING-17#116 Critical Warning Non-clocked sequential cell -The clock pin genblk2[2].yellow_piece_gfx/valid_reg/C is not reached by a timing clock +The clock pin core_design/board_reg[24][0]_rep/C is not reached by a timing clock Related violations: TIMING-17#117 Critical Warning Non-clocked sequential cell -The clock pin genblk2[3].yellow_piece_gfx/paletteIndex_reg[1]/C is not reached by a timing clock +The clock pin core_design/board_reg[24][0]_rep__0/C is not reached by a timing clock Related violations: TIMING-17#118 Critical Warning Non-clocked sequential cell -The clock pin genblk2[3].yellow_piece_gfx/paletteIndex_reg[3]/C is not reached by a timing clock +The clock pin core_design/board_reg[24][1]/C is not reached by a timing clock Related violations: TIMING-17#119 Critical Warning Non-clocked sequential cell -The clock pin genblk2[3].yellow_piece_gfx/valid_reg/C is not reached by a timing clock +The clock pin core_design/board_reg[24][1]_rep/C is not reached by a timing clock Related violations: TIMING-17#120 Critical Warning Non-clocked sequential cell -The clock pin genblk2[4].yellow_piece_gfx/paletteIndex_reg[1]/C is not reached by a timing clock +The clock pin core_design/board_reg[24][1]_rep__0/C is not reached by a timing clock Related violations: TIMING-17#121 Critical Warning Non-clocked sequential cell -The clock pin genblk2[4].yellow_piece_gfx/paletteIndex_reg[3]/C is not reached by a timing clock +The clock pin core_design/board_reg[25][0]/C is not reached by a timing clock Related violations: TIMING-17#122 Critical Warning Non-clocked sequential cell -The clock pin genblk2[4].yellow_piece_gfx/valid_reg/C is not reached by a timing clock +The clock pin core_design/board_reg[25][0]_rep/C is not reached by a timing clock Related violations: TIMING-17#123 Critical Warning Non-clocked sequential cell -The clock pin genblk2[5].yellow_piece_gfx/paletteIndex_reg[1]/C is not reached by a timing clock +The clock pin core_design/board_reg[25][0]_rep__0/C is not reached by a timing clock Related violations: TIMING-17#124 Critical Warning Non-clocked sequential cell -The clock pin genblk2[5].yellow_piece_gfx/paletteIndex_reg[3]/C is not reached by a timing clock +The clock pin core_design/board_reg[25][1]/C is not reached by a timing clock Related violations: TIMING-17#125 Critical Warning Non-clocked sequential cell -The clock pin genblk2[5].yellow_piece_gfx/valid_reg/C is not reached by a timing clock +The clock pin core_design/board_reg[25][1]_rep/C is not reached by a timing clock Related violations: TIMING-17#126 Critical Warning Non-clocked sequential cell -The clock pin genblk2[6].yellow_piece_gfx/paletteIndex_reg[1]/C is not reached by a timing clock +The clock pin core_design/board_reg[25][1]_rep__0/C is not reached by a timing clock Related violations: TIMING-17#127 Critical Warning Non-clocked sequential cell -The clock pin genblk2[6].yellow_piece_gfx/paletteIndex_reg[3]/C is not reached by a timing clock +The clock pin core_design/board_reg[26][0]/C is not reached by a timing clock Related violations: TIMING-17#128 Critical Warning Non-clocked sequential cell -The clock pin genblk2[6].yellow_piece_gfx/valid_reg/C is not reached by a timing clock +The clock pin core_design/board_reg[26][1]/C is not reached by a timing clock Related violations: TIMING-17#129 Critical Warning Non-clocked sequential cell -The clock pin genblk2[7].yellow_piece_gfx/paletteIndex_reg[1]/C is not reached by a timing clock +The clock pin core_design/board_reg[27][0]/C is not reached by a timing clock Related violations: TIMING-17#130 Critical Warning Non-clocked sequential cell -The clock pin genblk2[7].yellow_piece_gfx/paletteIndex_reg[3]/C is not reached by a timing clock +The clock pin core_design/board_reg[27][1]/C is not reached by a timing clock Related violations: TIMING-17#131 Critical Warning Non-clocked sequential cell -The clock pin genblk2[7].yellow_piece_gfx/valid_reg/C is not reached by a timing clock +The clock pin core_design/board_reg[28][0]/C is not reached by a timing clock Related violations: TIMING-17#132 Critical Warning Non-clocked sequential cell -The clock pin genblk2[8].yellow_piece_gfx/paletteIndex_reg[1]/C is not reached by a timing clock +The clock pin core_design/board_reg[28][1]/C is not reached by a timing clock Related violations: TIMING-17#133 Critical Warning Non-clocked sequential cell -The clock pin genblk2[8].yellow_piece_gfx/paletteIndex_reg[3]/C is not reached by a timing clock +The clock pin core_design/board_reg[29][0]/C is not reached by a timing clock Related violations: TIMING-17#134 Critical Warning Non-clocked sequential cell -The clock pin genblk2[8].yellow_piece_gfx/valid_reg/C is not reached by a timing clock +The clock pin core_design/board_reg[29][1]/C is not reached by a timing clock Related violations: TIMING-17#135 Critical Warning Non-clocked sequential cell -The clock pin genblk2[9].yellow_piece_gfx/paletteIndex_reg[1]/C is not reached by a timing clock +The clock pin core_design/board_reg[2][0]/C is not reached by a timing clock Related violations: TIMING-17#136 Critical Warning Non-clocked sequential cell -The clock pin genblk2[9].yellow_piece_gfx/paletteIndex_reg[3]/C is not reached by a timing clock +The clock pin core_design/board_reg[2][1]/C is not reached by a timing clock Related violations: TIMING-17#137 Critical Warning Non-clocked sequential cell -The clock pin genblk2[9].yellow_piece_gfx/valid_reg/C is not reached by a timing clock +The clock pin core_design/board_reg[30][0]/C is not reached by a timing clock Related violations: TIMING-17#138 Critical Warning Non-clocked sequential cell -The clock pin hCnt_reg[0]/C is not reached by a timing clock +The clock pin core_design/board_reg[30][1]/C is not reached by a timing clock Related violations: TIMING-17#139 Critical Warning Non-clocked sequential cell -The clock pin hCnt_reg[1]/C is not reached by a timing clock +The clock pin core_design/board_reg[31][0]/C is not reached by a timing clock Related violations: TIMING-17#140 Critical Warning Non-clocked sequential cell -The clock pin hCnt_reg[2]/C is not reached by a timing clock +The clock pin core_design/board_reg[31][0]_rep/C is not reached by a timing clock Related violations: TIMING-17#141 Critical Warning Non-clocked sequential cell -The clock pin hCnt_reg[3]/C is not reached by a timing clock +The clock pin core_design/board_reg[31][0]_rep__0/C is not reached by a timing clock Related violations: TIMING-17#142 Critical Warning Non-clocked sequential cell -The clock pin hCnt_reg[4]/C is not reached by a timing clock +The clock pin core_design/board_reg[31][1]/C is not reached by a timing clock Related violations: TIMING-17#143 Critical Warning Non-clocked sequential cell -The clock pin hCnt_reg[5]/C is not reached by a timing clock +The clock pin core_design/board_reg[31][1]_rep/C is not reached by a timing clock Related violations: TIMING-17#144 Critical Warning Non-clocked sequential cell -The clock pin hCnt_reg[6]/C is not reached by a timing clock +The clock pin core_design/board_reg[31][1]_rep__0/C is not reached by a timing clock Related violations: TIMING-17#145 Critical Warning Non-clocked sequential cell -The clock pin hCnt_reg[7]/C is not reached by a timing clock +The clock pin core_design/board_reg[32][0]/C is not reached by a timing clock Related violations: TIMING-17#146 Critical Warning Non-clocked sequential cell -The clock pin hCnt_reg[8]/C is not reached by a timing clock +The clock pin core_design/board_reg[32][0]_rep/C is not reached by a timing clock Related violations: TIMING-17#147 Critical Warning Non-clocked sequential cell -The clock pin hCnt_reg[9]/C is not reached by a timing clock +The clock pin core_design/board_reg[32][0]_rep__0/C is not reached by a timing clock Related violations: TIMING-17#148 Critical Warning Non-clocked sequential cell -The clock pin hState_reg[0]/C is not reached by a timing clock +The clock pin core_design/board_reg[32][1]/C is not reached by a timing clock Related violations: TIMING-17#149 Critical Warning Non-clocked sequential cell -The clock pin hState_reg[1]/C is not reached by a timing clock +The clock pin core_design/board_reg[32][1]_rep/C is not reached by a timing clock Related violations: TIMING-17#150 Critical Warning Non-clocked sequential cell -The clock pin hState_reg[1]__0/C is not reached by a timing clock +The clock pin core_design/board_reg[32][1]_rep__0/C is not reached by a timing clock Related violations: TIMING-17#151 Critical Warning Non-clocked sequential cell -The clock pin hState_reg[2]/C is not reached by a timing clock +The clock pin core_design/board_reg[33][0]/C is not reached by a timing clock Related violations: TIMING-17#152 Critical Warning Non-clocked sequential cell -The clock pin hState_reg[2]__0/C is not reached by a timing clock +The clock pin core_design/board_reg[33][1]/C is not reached by a timing clock Related violations: TIMING-17#153 Critical Warning Non-clocked sequential cell -The clock pin hState_reg[3]/C is not reached by a timing clock +The clock pin core_design/board_reg[34][0]/C is not reached by a timing clock Related violations: TIMING-17#154 Critical Warning Non-clocked sequential cell -The clock pin hState_reg[3]__0/C is not reached by a timing clock +The clock pin core_design/board_reg[34][1]/C is not reached by a timing clock Related violations: TIMING-17#155 Critical Warning Non-clocked sequential cell -The clock pin hSync_reg/C is not reached by a timing clock +The clock pin core_design/board_reg[35][0]/C is not reached by a timing clock Related violations: TIMING-17#156 Critical Warning Non-clocked sequential cell -The clock pin lineClk_reg/C is not reached by a timing clock +The clock pin core_design/board_reg[35][1]/C is not reached by a timing clock Related violations: TIMING-17#157 Critical Warning Non-clocked sequential cell -The clock pin logo_gfx/paletteIndex_reg[0]/C is not reached by a timing clock +The clock pin core_design/board_reg[36][0]/C is not reached by a timing clock Related violations: TIMING-17#158 Critical Warning Non-clocked sequential cell -The clock pin logo_gfx/paletteIndex_reg[1]/C is not reached by a timing clock +The clock pin core_design/board_reg[36][1]/C is not reached by a timing clock Related violations: TIMING-17#159 Critical Warning Non-clocked sequential cell -The clock pin logo_gfx/paletteIndex_reg[2]/C is not reached by a timing clock +The clock pin core_design/board_reg[37][0]/C is not reached by a timing clock Related violations: TIMING-17#160 Critical Warning Non-clocked sequential cell -The clock pin logo_gfx/paletteIndex_reg[3]/C is not reached by a timing clock +The clock pin core_design/board_reg[37][1]/C is not reached by a timing clock Related violations: TIMING-17#161 Critical Warning Non-clocked sequential cell -The clock pin logo_gfx/valid_reg/C is not reached by a timing clock +The clock pin core_design/board_reg[38][0]/C is not reached by a timing clock Related violations: TIMING-17#162 Critical Warning Non-clocked sequential cell -The clock pin pixClkCnt_reg/C is not reached by a timing clock +The clock pin core_design/board_reg[38][1]/C is not reached by a timing clock Related violations: TIMING-17#163 Critical Warning Non-clocked sequential cell -The clock pin pixClk_reg/C is not reached by a timing clock +The clock pin core_design/board_reg[39][0]/C is not reached by a timing clock Related violations: TIMING-17#164 Critical Warning Non-clocked sequential cell -The clock pin pixX_reg[0]/C is not reached by a timing clock +The clock pin core_design/board_reg[39][1]/C is not reached by a timing clock Related violations: TIMING-17#165 Critical Warning Non-clocked sequential cell -The clock pin pixX_reg[1]/C is not reached by a timing clock +The clock pin core_design/board_reg[3][0]/C is not reached by a timing clock Related violations: TIMING-17#166 Critical Warning Non-clocked sequential cell -The clock pin pixX_reg[2]/C is not reached by a timing clock +The clock pin core_design/board_reg[3][1]/C is not reached by a timing clock Related violations: TIMING-17#167 Critical Warning Non-clocked sequential cell -The clock pin pixX_reg[2]_rep/C is not reached by a timing clock +The clock pin core_design/board_reg[40][0]/C is not reached by a timing clock Related violations: TIMING-17#168 Critical Warning Non-clocked sequential cell -The clock pin pixX_reg[2]_rep__0/C is not reached by a timing clock +The clock pin core_design/board_reg[40][1]/C is not reached by a timing clock Related violations: TIMING-17#169 Critical Warning Non-clocked sequential cell -The clock pin pixX_reg[2]_rep__1/C is not reached by a timing clock +The clock pin core_design/board_reg[41][0]/C is not reached by a timing clock Related violations: TIMING-17#170 Critical Warning Non-clocked sequential cell -The clock pin pixX_reg[3]/C is not reached by a timing clock +The clock pin core_design/board_reg[41][1]/C is not reached by a timing clock Related violations: TIMING-17#171 Critical Warning Non-clocked sequential cell -The clock pin pixX_reg[4]/C is not reached by a timing clock +The clock pin core_design/board_reg[4][0]/C is not reached by a timing clock Related violations: TIMING-17#172 Critical Warning Non-clocked sequential cell -The clock pin pixX_reg[5]/C is not reached by a timing clock +The clock pin core_design/board_reg[4][1]/C is not reached by a timing clock Related violations: TIMING-17#173 Critical Warning Non-clocked sequential cell -The clock pin pixX_reg[6]/C is not reached by a timing clock +The clock pin core_design/board_reg[5][0]/C is not reached by a timing clock Related violations: TIMING-17#174 Critical Warning Non-clocked sequential cell -The clock pin pixX_reg[7]/C is not reached by a timing clock +The clock pin core_design/board_reg[5][1]/C is not reached by a timing clock Related violations: TIMING-17#175 Critical Warning Non-clocked sequential cell -The clock pin pixX_reg[8]/C is not reached by a timing clock +The clock pin core_design/board_reg[6][0]/C is not reached by a timing clock Related violations: TIMING-17#176 Critical Warning Non-clocked sequential cell -The clock pin pixX_reg[9]/C is not reached by a timing clock +The clock pin core_design/board_reg[6][1]/C is not reached by a timing clock Related violations: TIMING-17#177 Critical Warning Non-clocked sequential cell -The clock pin pixY_reg[0]/C is not reached by a timing clock +The clock pin core_design/board_reg[7][0]/C is not reached by a timing clock Related violations: TIMING-17#178 Critical Warning Non-clocked sequential cell -The clock pin pixY_reg[1]/C is not reached by a timing clock +The clock pin core_design/board_reg[7][1]/C is not reached by a timing clock Related violations: TIMING-17#179 Critical Warning Non-clocked sequential cell -The clock pin pixY_reg[2]/C is not reached by a timing clock +The clock pin core_design/board_reg[8][0]/C is not reached by a timing clock Related violations: TIMING-17#180 Critical Warning Non-clocked sequential cell -The clock pin pixY_reg[2]_rep/C is not reached by a timing clock +The clock pin core_design/board_reg[8][1]/C is not reached by a timing clock Related violations: TIMING-17#181 Critical Warning Non-clocked sequential cell -The clock pin pixY_reg[2]_rep__0/C is not reached by a timing clock +The clock pin core_design/board_reg[9][0]/C is not reached by a timing clock Related violations: TIMING-17#182 Critical Warning Non-clocked sequential cell -The clock pin pixY_reg[3]/C is not reached by a timing clock +The clock pin core_design/board_reg[9][1]/C is not reached by a timing clock Related violations: TIMING-17#183 Critical Warning Non-clocked sequential cell -The clock pin pixY_reg[4]/C is not reached by a timing clock +The clock pin core_design/column_reg[0]_P/C is not reached by a timing clock Related violations: TIMING-17#184 Critical Warning Non-clocked sequential cell -The clock pin pixY_reg[5]/C is not reached by a timing clock +The clock pin core_design/column_reg[0]_P_rep/C is not reached by a timing clock Related violations: TIMING-17#185 Critical Warning Non-clocked sequential cell -The clock pin pixY_reg[6]/C is not reached by a timing clock +The clock pin core_design/column_reg[0]_P_rep__0/C is not reached by a timing clock Related violations: TIMING-17#186 Critical Warning Non-clocked sequential cell -The clock pin pixY_reg[7]/C is not reached by a timing clock +The clock pin core_design/column_reg[0]_P_rep__1/C is not reached by a timing clock Related violations: TIMING-17#187 Critical Warning Non-clocked sequential cell -The clock pin pixY_reg[8]/C is not reached by a timing clock +The clock pin core_design/column_reg[0]_P_rep__2/C is not reached by a timing clock Related violations: TIMING-17#188 Critical Warning Non-clocked sequential cell -The clock pin pixY_reg[9]/C is not reached by a timing clock +The clock pin core_design/column_reg[1]_P/C is not reached by a timing clock Related violations: TIMING-17#189 Critical Warning Non-clocked sequential cell -The clock pin vCnt_reg[0]/C is not reached by a timing clock +The clock pin core_design/column_reg[1]_P_rep/C is not reached by a timing clock Related violations: TIMING-17#190 Critical Warning Non-clocked sequential cell -The clock pin vCnt_reg[1]/C is not reached by a timing clock +The clock pin core_design/column_reg[1]_P_rep__0/C is not reached by a timing clock Related violations: TIMING-17#191 Critical Warning Non-clocked sequential cell -The clock pin vCnt_reg[2]/C is not reached by a timing clock +The clock pin core_design/column_reg[1]_P_rep__1/C is not reached by a timing clock Related violations: TIMING-17#192 Critical Warning Non-clocked sequential cell -The clock pin vCnt_reg[3]/C is not reached by a timing clock +The clock pin core_design/column_reg[2]_C/C is not reached by a timing clock Related violations: TIMING-17#193 Critical Warning Non-clocked sequential cell -The clock pin vCnt_reg[4]/C is not reached by a timing clock +The clock pin core_design/column_reg[2]_C_rep/C is not reached by a timing clock Related violations: TIMING-17#194 Critical Warning Non-clocked sequential cell -The clock pin vCnt_reg[5]/C is not reached by a timing clock +The clock pin core_design/column_reg[2]_C_rep__0/C is not reached by a timing clock Related violations: TIMING-17#195 Critical Warning Non-clocked sequential cell -The clock pin vCnt_reg[6]/C is not reached by a timing clock +The clock pin core_design/column_reg[2]_C_rep__1/C is not reached by a timing clock Related violations: TIMING-17#196 Critical Warning Non-clocked sequential cell -The clock pin vCnt_reg[7]/C is not reached by a timing clock +The clock pin core_design/column_reg[3]_C/C is not reached by a timing clock Related violations: TIMING-17#197 Critical Warning Non-clocked sequential cell -The clock pin vCnt_reg[8]/C is not reached by a timing clock +The clock pin core_design/column_reg[3]_C_rep/C is not reached by a timing clock Related violations: TIMING-17#198 Critical Warning Non-clocked sequential cell -The clock pin vCnt_reg[9]/C is not reached by a timing clock +The clock pin core_design/column_reg[3]_C_rep__0/C is not reached by a timing clock Related violations: TIMING-17#199 Critical Warning Non-clocked sequential cell -The clock pin vState_reg[0]/C is not reached by a timing clock +The clock pin core_design/column_reg[4]_C/C is not reached by a timing clock Related violations: TIMING-17#200 Critical Warning Non-clocked sequential cell -The clock pin vState_reg[1]/C is not reached by a timing clock +The clock pin core_design/column_reg[4]_C_rep/C is not reached by a timing clock Related violations: TIMING-17#201 Critical Warning Non-clocked sequential cell -The clock pin vState_reg[1]__0/C is not reached by a timing clock +The clock pin core_design/column_reg[4]_C_rep__0/C is not reached by a timing clock Related violations: TIMING-17#202 Critical Warning Non-clocked sequential cell -The clock pin vState_reg[2]/C is not reached by a timing clock +The clock pin core_design/column_reg[5]_C/C is not reached by a timing clock Related violations: TIMING-17#203 Critical Warning Non-clocked sequential cell -The clock pin vState_reg[2]__0/C is not reached by a timing clock +The clock pin core_design/column_reg[5]_C_rep/C is not reached by a timing clock Related violations: TIMING-17#204 Critical Warning Non-clocked sequential cell -The clock pin vState_reg[3]/C is not reached by a timing clock +The clock pin core_design/column_reg[5]_C_rep__0/C is not reached by a timing clock Related violations: TIMING-17#205 Critical Warning Non-clocked sequential cell -The clock pin vState_reg[3]__0/C is not reached by a timing clock +The clock pin core_design/currRed_reg[0]/C is not reached by a timing clock Related violations: TIMING-17#206 Critical Warning Non-clocked sequential cell -The clock pin vSync_reg/C is not reached by a timing clock +The clock pin core_design/currRed_reg[0]_rep/C is not reached by a timing clock Related violations: TIMING-17#207 Critical Warning Non-clocked sequential cell -The clock pin vgaBlu_reg[0]/C is not reached by a timing clock +The clock pin core_design/currRed_reg[0]_rep__0/C is not reached by a timing clock Related violations: TIMING-17#208 Critical Warning Non-clocked sequential cell -The clock pin vgaBlu_reg[1]/C is not reached by a timing clock +The clock pin core_design/currRed_reg[0]_rep__1/C is not reached by a timing clock Related violations: TIMING-17#209 Critical Warning Non-clocked sequential cell -The clock pin vgaBlu_reg[2]/C is not reached by a timing clock +The clock pin core_design/currRed_reg[1]/C is not reached by a timing clock Related violations: TIMING-17#210 Critical Warning Non-clocked sequential cell -The clock pin vgaBlu_reg[3]/C is not reached by a timing clock +The clock pin core_design/currRed_reg[1]_rep/C is not reached by a timing clock Related violations: TIMING-17#211 Critical Warning Non-clocked sequential cell -The clock pin vgaGrn_reg[0]/C is not reached by a timing clock +The clock pin core_design/currRed_reg[1]_rep__0/C is not reached by a timing clock Related violations: TIMING-17#212 Critical Warning Non-clocked sequential cell -The clock pin vgaGrn_reg[1]/C is not reached by a timing clock +The clock pin core_design/currRed_reg[1]_rep__1/C is not reached by a timing clock Related violations: TIMING-17#213 Critical Warning Non-clocked sequential cell -The clock pin vgaGrn_reg[2]/C is not reached by a timing clock +The clock pin core_design/currRed_reg[1]_rep__2/C is not reached by a timing clock Related violations: TIMING-17#214 Critical Warning Non-clocked sequential cell -The clock pin vgaGrn_reg[3]/C is not reached by a timing clock +The clock pin core_design/currRed_reg[2]/C is not reached by a timing clock Related violations: TIMING-17#215 Critical Warning Non-clocked sequential cell -The clock pin vgaRed_reg[0]/C is not reached by a timing clock +The clock pin core_design/currRed_reg[2]_rep/C is not reached by a timing clock Related violations: TIMING-17#216 Critical Warning Non-clocked sequential cell -The clock pin vgaRed_reg[1]/C is not reached by a timing clock +The clock pin core_design/currRed_reg[2]_rep__0/C is not reached by a timing clock Related violations: TIMING-17#217 Critical Warning Non-clocked sequential cell -The clock pin vgaRed_reg[2]/C is not reached by a timing clock +The clock pin core_design/currRed_reg[2]_rep__1/C is not reached by a timing clock Related violations: TIMING-17#218 Critical Warning Non-clocked sequential cell -The clock pin vgaRed_reg[3]/C is not reached by a timing clock +The clock pin core_design/currRed_reg[3]/C is not reached by a timing clock +Related violations: + +TIMING-17#219 Critical Warning +Non-clocked sequential cell +The clock pin core_design/currRed_reg[4]/C is not reached by a timing clock +Related violations: + +TIMING-17#220 Critical Warning +Non-clocked sequential cell +The clock pin core_design/currYellow_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#221 Critical Warning +Non-clocked sequential cell +The clock pin core_design/currYellow_reg[0]_rep/C is not reached by a timing clock +Related violations: + +TIMING-17#222 Critical Warning +Non-clocked sequential cell +The clock pin core_design/currYellow_reg[0]_rep__0/C is not reached by a timing clock +Related violations: + +TIMING-17#223 Critical Warning +Non-clocked sequential cell +The clock pin core_design/currYellow_reg[0]_rep__1/C is not reached by a timing clock +Related violations: + +TIMING-17#224 Critical Warning +Non-clocked sequential cell +The clock pin core_design/currYellow_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#225 Critical Warning +Non-clocked sequential cell +The clock pin core_design/currYellow_reg[1]_rep/C is not reached by a timing clock +Related violations: + +TIMING-17#226 Critical Warning +Non-clocked sequential cell +The clock pin core_design/currYellow_reg[1]_rep__0/C is not reached by a timing clock +Related violations: + +TIMING-17#227 Critical Warning +Non-clocked sequential cell +The clock pin core_design/currYellow_reg[2]/C is not reached by a timing clock +Related violations: + +TIMING-17#228 Critical Warning +Non-clocked sequential cell +The clock pin core_design/currYellow_reg[2]_rep/C is not reached by a timing clock +Related violations: + +TIMING-17#229 Critical Warning +Non-clocked sequential cell +The clock pin core_design/currYellow_reg[2]_rep__0/C is not reached by a timing clock +Related violations: + +TIMING-17#230 Critical Warning +Non-clocked sequential cell +The clock pin core_design/currYellow_reg[2]_rep__1/C is not reached by a timing clock +Related violations: + +TIMING-17#231 Critical Warning +Non-clocked sequential cell +The clock pin core_design/currYellow_reg[3]/C is not reached by a timing clock +Related violations: + +TIMING-17#232 Critical Warning +Non-clocked sequential cell +The clock pin core_design/currYellow_reg[4]/C is not reached by a timing clock +Related violations: + +TIMING-17#233 Critical Warning +Non-clocked sequential cell +The clock pin core_design/current_player_reg/C is not reached by a timing clock +Related violations: + +TIMING-17#234 Critical Warning +Non-clocked sequential cell +The clock pin core_design/current_player_reg_rep/C is not reached by a timing clock +Related violations: + +TIMING-17#235 Critical Warning +Non-clocked sequential cell +The clock pin core_design/current_player_reg_rep__0/C is not reached by a timing clock +Related violations: + +TIMING-17#236 Critical Warning +Non-clocked sequential cell +The clock pin core_design/current_player_reg_rep__1/C is not reached by a timing clock +Related violations: + +TIMING-17#237 Critical Warning +Non-clocked sequential cell +The clock pin core_design/current_player_reg_rep__2/C is not reached by a timing clock +Related violations: + +TIMING-17#238 Critical Warning +Non-clocked sequential cell +The clock pin core_design/current_player_reg_rep__3/C is not reached by a timing clock +Related violations: + +TIMING-17#239 Critical Warning +Non-clocked sequential cell +The clock pin core_design/pieceAnimationTimer_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#240 Critical Warning +Non-clocked sequential cell +The clock pin core_design/pieceAnimationTimer_reg[10]/C is not reached by a timing clock +Related violations: + +TIMING-17#241 Critical Warning +Non-clocked sequential cell +The clock pin core_design/pieceAnimationTimer_reg[11]/C is not reached by a timing clock +Related violations: + +TIMING-17#242 Critical Warning +Non-clocked sequential cell +The clock pin core_design/pieceAnimationTimer_reg[12]/C is not reached by a timing clock +Related violations: + +TIMING-17#243 Critical Warning +Non-clocked sequential cell +The clock pin core_design/pieceAnimationTimer_reg[13]/C is not reached by a timing clock +Related violations: + +TIMING-17#244 Critical Warning +Non-clocked sequential cell +The clock pin core_design/pieceAnimationTimer_reg[14]/C is not reached by a timing clock +Related violations: + +TIMING-17#245 Critical Warning +Non-clocked sequential cell +The clock pin core_design/pieceAnimationTimer_reg[15]/C is not reached by a timing clock +Related violations: + +TIMING-17#246 Critical Warning +Non-clocked sequential cell +The clock pin core_design/pieceAnimationTimer_reg[16]/C is not reached by a timing clock +Related violations: + +TIMING-17#247 Critical Warning +Non-clocked sequential cell +The clock pin core_design/pieceAnimationTimer_reg[17]/C is not reached by a timing clock +Related violations: + +TIMING-17#248 Critical Warning +Non-clocked sequential cell +The clock pin core_design/pieceAnimationTimer_reg[18]/C is not reached by a timing clock +Related violations: + +TIMING-17#249 Critical Warning +Non-clocked sequential cell +The clock pin core_design/pieceAnimationTimer_reg[19]/C is not reached by a timing clock +Related violations: + +TIMING-17#250 Critical Warning +Non-clocked sequential cell +The clock pin core_design/pieceAnimationTimer_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#251 Critical Warning +Non-clocked sequential cell +The clock pin core_design/pieceAnimationTimer_reg[20]/C is not reached by a timing clock +Related violations: + +TIMING-17#252 Critical Warning +Non-clocked sequential cell +The clock pin core_design/pieceAnimationTimer_reg[21]/C is not reached by a timing clock +Related violations: + +TIMING-17#253 Critical Warning +Non-clocked sequential cell +The clock pin core_design/pieceAnimationTimer_reg[22]/C is not reached by a timing clock +Related violations: + +TIMING-17#254 Critical Warning +Non-clocked sequential cell +The clock pin core_design/pieceAnimationTimer_reg[23]/C is not reached by a timing clock +Related violations: + +TIMING-17#255 Critical Warning +Non-clocked sequential cell +The clock pin core_design/pieceAnimationTimer_reg[24]/C is not reached by a timing clock +Related violations: + +TIMING-17#256 Critical Warning +Non-clocked sequential cell +The clock pin core_design/pieceAnimationTimer_reg[25]/C is not reached by a timing clock +Related violations: + +TIMING-17#257 Critical Warning +Non-clocked sequential cell +The clock pin core_design/pieceAnimationTimer_reg[26]/C is not reached by a timing clock +Related violations: + +TIMING-17#258 Critical Warning +Non-clocked sequential cell +The clock pin core_design/pieceAnimationTimer_reg[27]/C is not reached by a timing clock +Related violations: + +TIMING-17#259 Critical Warning +Non-clocked sequential cell +The clock pin core_design/pieceAnimationTimer_reg[28]/C is not reached by a timing clock +Related violations: + +TIMING-17#260 Critical Warning +Non-clocked sequential cell +The clock pin core_design/pieceAnimationTimer_reg[29]/C is not reached by a timing clock +Related violations: + +TIMING-17#261 Critical Warning +Non-clocked sequential cell +The clock pin core_design/pieceAnimationTimer_reg[2]/C is not reached by a timing clock +Related violations: + +TIMING-17#262 Critical Warning +Non-clocked sequential cell +The clock pin core_design/pieceAnimationTimer_reg[30]/C is not reached by a timing clock +Related violations: + +TIMING-17#263 Critical Warning +Non-clocked sequential cell +The clock pin core_design/pieceAnimationTimer_reg[31]/C is not reached by a timing clock +Related violations: + +TIMING-17#264 Critical Warning +Non-clocked sequential cell +The clock pin core_design/pieceAnimationTimer_reg[3]/C is not reached by a timing clock +Related violations: + +TIMING-17#265 Critical Warning +Non-clocked sequential cell +The clock pin core_design/pieceAnimationTimer_reg[4]/C is not reached by a timing clock +Related violations: + +TIMING-17#266 Critical Warning +Non-clocked sequential cell +The clock pin core_design/pieceAnimationTimer_reg[5]/C is not reached by a timing clock +Related violations: + +TIMING-17#267 Critical Warning +Non-clocked sequential cell +The clock pin core_design/pieceAnimationTimer_reg[6]/C is not reached by a timing clock +Related violations: + +TIMING-17#268 Critical Warning +Non-clocked sequential cell +The clock pin core_design/pieceAnimationTimer_reg[7]/C is not reached by a timing clock +Related violations: + +TIMING-17#269 Critical Warning +Non-clocked sequential cell +The clock pin core_design/pieceAnimationTimer_reg[8]/C is not reached by a timing clock +Related violations: + +TIMING-17#270 Critical Warning +Non-clocked sequential cell +The clock pin core_design/pieceAnimationTimer_reg[9]/C is not reached by a timing clock +Related violations: + +TIMING-17#271 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToCol_reg[0][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#272 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToCol_reg[0][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#273 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToCol_reg[0][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#274 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToCol_reg[10][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#275 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToCol_reg[10][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#276 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToCol_reg[10][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#277 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToCol_reg[11][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#278 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToCol_reg[11][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#279 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToCol_reg[11][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#280 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToCol_reg[12][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#281 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToCol_reg[12][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#282 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToCol_reg[12][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#283 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToCol_reg[13][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#284 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToCol_reg[13][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#285 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToCol_reg[13][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#286 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToCol_reg[14][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#287 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToCol_reg[14][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#288 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToCol_reg[14][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#289 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToCol_reg[15][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#290 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToCol_reg[15][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#291 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToCol_reg[15][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#292 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToCol_reg[16][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#293 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToCol_reg[16][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#294 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToCol_reg[16][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#295 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToCol_reg[17][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#296 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToCol_reg[17][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#297 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToCol_reg[17][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#298 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToCol_reg[18][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#299 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToCol_reg[18][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#300 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToCol_reg[18][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#301 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToCol_reg[19][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#302 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToCol_reg[19][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#303 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToCol_reg[19][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#304 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToCol_reg[1][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#305 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToCol_reg[1][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#306 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToCol_reg[1][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#307 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToCol_reg[20][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#308 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToCol_reg[20][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#309 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToCol_reg[20][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#310 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToCol_reg[2][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#311 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToCol_reg[2][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#312 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToCol_reg[2][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#313 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToCol_reg[3][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#314 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToCol_reg[3][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#315 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToCol_reg[3][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#316 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToCol_reg[4][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#317 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToCol_reg[4][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#318 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToCol_reg[4][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#319 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToCol_reg[5][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#320 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToCol_reg[5][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#321 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToCol_reg[5][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#322 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToCol_reg[6][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#323 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToCol_reg[6][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#324 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToCol_reg[6][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#325 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToCol_reg[7][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#326 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToCol_reg[7][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#327 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToCol_reg[7][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#328 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToCol_reg[8][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#329 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToCol_reg[8][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#330 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToCol_reg[8][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#331 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToCol_reg[9][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#332 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToCol_reg[9][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#333 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToCol_reg[9][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#334 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToRow_reg[0][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#335 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToRow_reg[0][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#336 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToRow_reg[0][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#337 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToRow_reg[10][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#338 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToRow_reg[10][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#339 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToRow_reg[10][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#340 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToRow_reg[11][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#341 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToRow_reg[11][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#342 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToRow_reg[11][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#343 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToRow_reg[12][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#344 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToRow_reg[12][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#345 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToRow_reg[12][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#346 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToRow_reg[13][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#347 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToRow_reg[13][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#348 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToRow_reg[13][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#349 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToRow_reg[14][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#350 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToRow_reg[14][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#351 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToRow_reg[14][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#352 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToRow_reg[15][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#353 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToRow_reg[15][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#354 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToRow_reg[15][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#355 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToRow_reg[16][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#356 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToRow_reg[16][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#357 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToRow_reg[16][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#358 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToRow_reg[17][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#359 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToRow_reg[17][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#360 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToRow_reg[17][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#361 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToRow_reg[18][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#362 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToRow_reg[18][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#363 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToRow_reg[18][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#364 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToRow_reg[19][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#365 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToRow_reg[19][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#366 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToRow_reg[19][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#367 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToRow_reg[1][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#368 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToRow_reg[1][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#369 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToRow_reg[1][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#370 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToRow_reg[20][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#371 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToRow_reg[20][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#372 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToRow_reg[20][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#373 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToRow_reg[2][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#374 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToRow_reg[2][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#375 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToRow_reg[2][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#376 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToRow_reg[3][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#377 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToRow_reg[3][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#378 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToRow_reg[3][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#379 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToRow_reg[4][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#380 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToRow_reg[4][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#381 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToRow_reg[4][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#382 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToRow_reg[5][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#383 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToRow_reg[5][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#384 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToRow_reg[5][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#385 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToRow_reg[6][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#386 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToRow_reg[6][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#387 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToRow_reg[6][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#388 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToRow_reg[7][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#389 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToRow_reg[7][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#390 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToRow_reg[7][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#391 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToRow_reg[8][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#392 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToRow_reg[8][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#393 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToRow_reg[8][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#394 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToRow_reg[9][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#395 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToRow_reg[9][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#396 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndexToRow_reg[9][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#397 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndicatorXOffset_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#398 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndicatorXOffset_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#399 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndicatorXOffset_reg[2]/C is not reached by a timing clock +Related violations: + +TIMING-17#400 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndicatorXOffset_reg[3]/C is not reached by a timing clock +Related violations: + +TIMING-17#401 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndicatorXOffset_reg[4]/C is not reached by a timing clock +Related violations: + +TIMING-17#402 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndicatorXOffset_reg[5]/C is not reached by a timing clock +Related violations: + +TIMING-17#403 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndicatorXOffset_reg[6]/C is not reached by a timing clock +Related violations: + +TIMING-17#404 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndicatorXOffset_reg[7]/C is not reached by a timing clock +Related violations: + +TIMING-17#405 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndicatorXOffset_reg[8]/C is not reached by a timing clock +Related violations: + +TIMING-17#406 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redIndicatorXOffset_reg[9]/C is not reached by a timing clock +Related violations: + +TIMING-17#407 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[0][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#408 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[0][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#409 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[0][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#410 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[0][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#411 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[0][5]/C is not reached by a timing clock +Related violations: + +TIMING-17#412 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[0][6]/C is not reached by a timing clock +Related violations: + +TIMING-17#413 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[0][7]/C is not reached by a timing clock +Related violations: + +TIMING-17#414 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[0][8]/C is not reached by a timing clock +Related violations: + +TIMING-17#415 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[0][9]/C is not reached by a timing clock +Related violations: + +TIMING-17#416 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[10][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#417 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[10][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#418 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[10][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#419 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[10][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#420 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[10][5]/C is not reached by a timing clock +Related violations: + +TIMING-17#421 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[10][6]/C is not reached by a timing clock +Related violations: + +TIMING-17#422 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[10][7]/C is not reached by a timing clock +Related violations: + +TIMING-17#423 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[10][8]/C is not reached by a timing clock +Related violations: + +TIMING-17#424 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[10][9]/C is not reached by a timing clock +Related violations: + +TIMING-17#425 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[11][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#426 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[11][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#427 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[11][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#428 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[11][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#429 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[11][5]/C is not reached by a timing clock +Related violations: + +TIMING-17#430 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[11][6]/C is not reached by a timing clock +Related violations: + +TIMING-17#431 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[11][7]/C is not reached by a timing clock +Related violations: + +TIMING-17#432 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[11][8]/C is not reached by a timing clock +Related violations: + +TIMING-17#433 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[11][9]/C is not reached by a timing clock +Related violations: + +TIMING-17#434 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[12][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#435 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[12][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#436 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[12][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#437 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[12][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#438 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[12][5]/C is not reached by a timing clock +Related violations: + +TIMING-17#439 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[12][6]/C is not reached by a timing clock +Related violations: + +TIMING-17#440 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[12][7]/C is not reached by a timing clock +Related violations: + +TIMING-17#441 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[12][8]/C is not reached by a timing clock +Related violations: + +TIMING-17#442 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[12][9]/C is not reached by a timing clock +Related violations: + +TIMING-17#443 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[13][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#444 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[13][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#445 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[13][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#446 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[13][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#447 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[13][5]/C is not reached by a timing clock +Related violations: + +TIMING-17#448 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[13][6]/C is not reached by a timing clock +Related violations: + +TIMING-17#449 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[13][7]/C is not reached by a timing clock +Related violations: + +TIMING-17#450 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[13][8]/C is not reached by a timing clock +Related violations: + +TIMING-17#451 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[13][9]/C is not reached by a timing clock +Related violations: + +TIMING-17#452 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[14][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#453 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[14][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#454 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[14][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#455 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[14][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#456 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[14][5]/C is not reached by a timing clock +Related violations: + +TIMING-17#457 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[14][6]/C is not reached by a timing clock +Related violations: + +TIMING-17#458 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[14][7]/C is not reached by a timing clock +Related violations: + +TIMING-17#459 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[14][8]/C is not reached by a timing clock +Related violations: + +TIMING-17#460 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[14][9]/C is not reached by a timing clock +Related violations: + +TIMING-17#461 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[15][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#462 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[15][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#463 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[15][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#464 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[15][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#465 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[15][5]/C is not reached by a timing clock +Related violations: + +TIMING-17#466 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[15][6]/C is not reached by a timing clock +Related violations: + +TIMING-17#467 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[15][7]/C is not reached by a timing clock +Related violations: + +TIMING-17#468 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[15][8]/C is not reached by a timing clock +Related violations: + +TIMING-17#469 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[15][9]/C is not reached by a timing clock +Related violations: + +TIMING-17#470 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[16][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#471 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[16][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#472 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[16][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#473 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[16][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#474 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[16][5]/C is not reached by a timing clock +Related violations: + +TIMING-17#475 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[16][6]/C is not reached by a timing clock +Related violations: + +TIMING-17#476 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[16][7]/C is not reached by a timing clock +Related violations: + +TIMING-17#477 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[16][8]/C is not reached by a timing clock +Related violations: + +TIMING-17#478 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[16][9]/C is not reached by a timing clock +Related violations: + +TIMING-17#479 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[17][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#480 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[17][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#481 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[17][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#482 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[17][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#483 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[17][5]/C is not reached by a timing clock +Related violations: + +TIMING-17#484 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[17][6]/C is not reached by a timing clock +Related violations: + +TIMING-17#485 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[17][7]/C is not reached by a timing clock +Related violations: + +TIMING-17#486 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[17][8]/C is not reached by a timing clock +Related violations: + +TIMING-17#487 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[17][9]/C is not reached by a timing clock +Related violations: + +TIMING-17#488 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[18][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#489 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[18][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#490 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[18][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#491 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[18][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#492 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[18][5]/C is not reached by a timing clock +Related violations: + +TIMING-17#493 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[18][6]/C is not reached by a timing clock +Related violations: + +TIMING-17#494 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[18][7]/C is not reached by a timing clock +Related violations: + +TIMING-17#495 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[18][8]/C is not reached by a timing clock +Related violations: + +TIMING-17#496 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[18][9]/C is not reached by a timing clock +Related violations: + +TIMING-17#497 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[19][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#498 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[19][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#499 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[19][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#500 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[19][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#501 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[19][5]/C is not reached by a timing clock +Related violations: + +TIMING-17#502 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[19][6]/C is not reached by a timing clock +Related violations: + +TIMING-17#503 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[19][7]/C is not reached by a timing clock +Related violations: + +TIMING-17#504 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[19][8]/C is not reached by a timing clock +Related violations: + +TIMING-17#505 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[19][9]/C is not reached by a timing clock +Related violations: + +TIMING-17#506 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[1][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#507 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[1][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#508 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[1][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#509 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[1][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#510 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[1][5]/C is not reached by a timing clock +Related violations: + +TIMING-17#511 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[1][6]/C is not reached by a timing clock +Related violations: + +TIMING-17#512 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[1][7]/C is not reached by a timing clock +Related violations: + +TIMING-17#513 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[1][8]/C is not reached by a timing clock +Related violations: + +TIMING-17#514 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[1][9]/C is not reached by a timing clock +Related violations: + +TIMING-17#515 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[20][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#516 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[20][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#517 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[20][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#518 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[20][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#519 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[20][5]/C is not reached by a timing clock +Related violations: + +TIMING-17#520 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[20][6]/C is not reached by a timing clock +Related violations: + +TIMING-17#521 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[20][7]/C is not reached by a timing clock +Related violations: + +TIMING-17#522 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[20][8]/C is not reached by a timing clock +Related violations: + +TIMING-17#523 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[20][9]/C is not reached by a timing clock +Related violations: + +TIMING-17#524 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[2][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#525 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[2][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#526 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[2][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#527 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[2][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#528 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[2][5]/C is not reached by a timing clock +Related violations: + +TIMING-17#529 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[2][6]/C is not reached by a timing clock +Related violations: + +TIMING-17#530 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[2][7]/C is not reached by a timing clock +Related violations: + +TIMING-17#531 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[2][8]/C is not reached by a timing clock +Related violations: + +TIMING-17#532 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[2][9]/C is not reached by a timing clock +Related violations: + +TIMING-17#533 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[3][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#534 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[3][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#535 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[3][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#536 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[3][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#537 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[3][5]/C is not reached by a timing clock +Related violations: + +TIMING-17#538 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[3][6]/C is not reached by a timing clock +Related violations: + +TIMING-17#539 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[3][7]/C is not reached by a timing clock +Related violations: + +TIMING-17#540 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[3][8]/C is not reached by a timing clock +Related violations: + +TIMING-17#541 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[3][9]/C is not reached by a timing clock +Related violations: + +TIMING-17#542 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[4][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#543 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[4][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#544 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[4][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#545 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[4][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#546 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[4][5]/C is not reached by a timing clock +Related violations: + +TIMING-17#547 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[4][6]/C is not reached by a timing clock +Related violations: + +TIMING-17#548 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[4][7]/C is not reached by a timing clock +Related violations: + +TIMING-17#549 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[4][8]/C is not reached by a timing clock +Related violations: + +TIMING-17#550 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[4][9]/C is not reached by a timing clock +Related violations: + +TIMING-17#551 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[5][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#552 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[5][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#553 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[5][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#554 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[5][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#555 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[5][5]/C is not reached by a timing clock +Related violations: + +TIMING-17#556 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[5][6]/C is not reached by a timing clock +Related violations: + +TIMING-17#557 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[5][7]/C is not reached by a timing clock +Related violations: + +TIMING-17#558 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[5][8]/C is not reached by a timing clock +Related violations: + +TIMING-17#559 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[5][9]/C is not reached by a timing clock +Related violations: + +TIMING-17#560 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[6][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#561 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[6][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#562 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[6][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#563 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[6][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#564 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[6][5]/C is not reached by a timing clock +Related violations: + +TIMING-17#565 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[6][6]/C is not reached by a timing clock +Related violations: + +TIMING-17#566 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[6][7]/C is not reached by a timing clock +Related violations: + +TIMING-17#567 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[6][8]/C is not reached by a timing clock +Related violations: + +TIMING-17#568 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[6][9]/C is not reached by a timing clock +Related violations: + +TIMING-17#569 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[7][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#570 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[7][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#571 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[7][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#572 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[7][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#573 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[7][5]/C is not reached by a timing clock +Related violations: + +TIMING-17#574 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[7][6]/C is not reached by a timing clock +Related violations: + +TIMING-17#575 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[7][7]/C is not reached by a timing clock +Related violations: + +TIMING-17#576 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[7][8]/C is not reached by a timing clock +Related violations: + +TIMING-17#577 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[7][9]/C is not reached by a timing clock +Related violations: + +TIMING-17#578 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[8][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#579 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[8][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#580 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[8][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#581 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[8][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#582 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[8][5]/C is not reached by a timing clock +Related violations: + +TIMING-17#583 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[8][6]/C is not reached by a timing clock +Related violations: + +TIMING-17#584 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[8][7]/C is not reached by a timing clock +Related violations: + +TIMING-17#585 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[8][8]/C is not reached by a timing clock +Related violations: + +TIMING-17#586 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[8][9]/C is not reached by a timing clock +Related violations: + +TIMING-17#587 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[9][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#588 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[9][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#589 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[9][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#590 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[9][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#591 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[9][5]/C is not reached by a timing clock +Related violations: + +TIMING-17#592 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[9][6]/C is not reached by a timing clock +Related violations: + +TIMING-17#593 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[9][7]/C is not reached by a timing clock +Related violations: + +TIMING-17#594 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[9][8]/C is not reached by a timing clock +Related violations: + +TIMING-17#595 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceXOffset_reg[9][9]/C is not reached by a timing clock +Related violations: + +TIMING-17#596 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[0][0]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#597 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[0][1]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#598 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[0][2]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#599 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[0][3]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#600 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[0][4]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#601 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[0][5]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#602 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[0][6]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#603 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[0][7]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#604 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[0][8]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#605 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[0][8]_P/C is not reached by a timing clock +Related violations: + +TIMING-17#606 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[0][9]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#607 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[0][9]_P/C is not reached by a timing clock +Related violations: + +TIMING-17#608 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[10][0]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#609 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[10][1]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#610 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[10][2]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#611 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[10][3]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#612 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[10][4]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#613 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[10][5]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#614 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[10][6]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#615 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[10][7]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#616 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[10][8]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#617 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[10][8]_P/C is not reached by a timing clock +Related violations: + +TIMING-17#618 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[10][9]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#619 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[10][9]_P/C is not reached by a timing clock +Related violations: + +TIMING-17#620 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[11][0]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#621 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[11][1]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#622 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[11][2]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#623 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[11][3]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#624 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[11][4]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#625 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[11][5]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#626 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[11][6]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#627 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[11][7]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#628 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[11][8]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#629 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[11][8]_P/C is not reached by a timing clock +Related violations: + +TIMING-17#630 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[11][9]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#631 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[11][9]_P/C is not reached by a timing clock +Related violations: + +TIMING-17#632 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[12][0]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#633 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[12][1]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#634 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[12][2]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#635 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[12][3]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#636 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[12][4]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#637 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[12][5]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#638 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[12][6]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#639 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[12][7]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#640 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[12][8]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#641 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[12][8]_P/C is not reached by a timing clock +Related violations: + +TIMING-17#642 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[12][9]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#643 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[12][9]_P/C is not reached by a timing clock +Related violations: + +TIMING-17#644 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[13][0]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#645 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[13][1]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#646 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[13][2]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#647 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[13][3]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#648 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[13][4]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#649 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[13][5]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#650 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[13][6]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#651 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[13][7]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#652 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[13][8]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#653 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[13][8]_P/C is not reached by a timing clock +Related violations: + +TIMING-17#654 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[13][9]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#655 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[13][9]_P/C is not reached by a timing clock +Related violations: + +TIMING-17#656 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[14][0]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#657 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[14][1]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#658 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[14][2]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#659 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[14][3]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#660 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[14][4]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#661 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[14][5]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#662 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[14][6]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#663 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[14][7]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#664 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[14][8]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#665 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[14][8]_P/C is not reached by a timing clock +Related violations: + +TIMING-17#666 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[14][9]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#667 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[14][9]_P/C is not reached by a timing clock +Related violations: + +TIMING-17#668 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[15][0]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#669 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[15][1]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#670 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[15][2]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#671 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[15][3]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#672 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[15][4]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#673 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[15][5]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#674 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[15][6]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#675 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[15][7]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#676 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[15][8]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#677 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[15][8]_P/C is not reached by a timing clock +Related violations: + +TIMING-17#678 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[15][9]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#679 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[15][9]_P/C is not reached by a timing clock +Related violations: + +TIMING-17#680 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[16][0]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#681 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[16][1]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#682 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[16][2]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#683 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[16][3]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#684 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[16][4]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#685 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[16][5]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#686 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[16][6]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#687 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[16][7]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#688 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[16][8]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#689 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[16][8]_P/C is not reached by a timing clock +Related violations: + +TIMING-17#690 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[16][9]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#691 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[16][9]_P/C is not reached by a timing clock +Related violations: + +TIMING-17#692 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[17][0]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#693 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[17][1]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#694 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[17][2]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#695 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[17][3]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#696 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[17][4]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#697 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[17][5]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#698 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[17][6]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#699 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[17][7]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#700 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[17][8]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#701 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[17][8]_P/C is not reached by a timing clock +Related violations: + +TIMING-17#702 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[17][9]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#703 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[17][9]_P/C is not reached by a timing clock +Related violations: + +TIMING-17#704 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[18][0]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#705 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[18][1]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#706 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[18][2]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#707 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[18][3]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#708 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[18][4]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#709 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[18][5]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#710 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[18][6]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#711 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[18][7]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#712 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[18][8]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#713 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[18][8]_P/C is not reached by a timing clock +Related violations: + +TIMING-17#714 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[18][9]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#715 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[18][9]_P/C is not reached by a timing clock +Related violations: + +TIMING-17#716 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[19][0]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#717 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[19][1]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#718 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[19][2]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#719 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[19][3]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#720 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[19][4]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#721 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[19][5]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#722 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[19][6]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#723 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[19][7]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#724 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[19][8]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#725 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[19][8]_P/C is not reached by a timing clock +Related violations: + +TIMING-17#726 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[19][9]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#727 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[19][9]_P/C is not reached by a timing clock +Related violations: + +TIMING-17#728 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[1][0]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#729 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[1][1]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#730 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[1][2]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#731 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[1][3]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#732 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[1][4]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#733 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[1][5]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#734 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[1][6]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#735 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[1][7]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#736 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[1][8]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#737 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[1][9]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#738 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[20][0]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#739 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[20][1]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#740 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[20][2]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#741 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[20][3]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#742 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[20][4]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#743 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[20][5]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#744 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[20][6]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#745 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[20][7]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#746 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[20][8]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#747 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[20][8]_P/C is not reached by a timing clock +Related violations: + +TIMING-17#748 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[20][9]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#749 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[20][9]_P/C is not reached by a timing clock +Related violations: + +TIMING-17#750 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[2][0]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#751 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[2][1]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#752 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[2][2]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#753 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[2][3]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#754 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[2][4]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#755 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[2][5]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#756 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[2][6]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#757 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[2][7]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#758 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[2][8]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#759 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[2][8]_P/C is not reached by a timing clock +Related violations: + +TIMING-17#760 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[2][9]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#761 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[2][9]_P/C is not reached by a timing clock +Related violations: + +TIMING-17#762 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[3][0]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#763 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[3][1]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#764 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[3][2]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#765 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[3][3]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#766 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[3][4]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#767 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[3][5]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#768 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[3][6]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#769 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[3][7]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#770 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[3][8]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#771 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[3][8]_P/C is not reached by a timing clock +Related violations: + +TIMING-17#772 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[3][9]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#773 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[3][9]_P/C is not reached by a timing clock +Related violations: + +TIMING-17#774 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[4][0]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#775 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[4][1]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#776 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[4][2]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#777 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[4][3]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#778 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[4][4]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#779 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[4][5]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#780 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[4][6]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#781 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[4][7]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#782 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[4][8]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#783 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[4][8]_P/C is not reached by a timing clock +Related violations: + +TIMING-17#784 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[4][9]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#785 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[4][9]_P/C is not reached by a timing clock +Related violations: + +TIMING-17#786 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[5][0]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#787 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[5][1]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#788 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[5][2]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#789 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[5][3]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#790 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[5][4]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#791 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[5][5]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#792 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[5][6]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#793 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[5][7]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#794 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[5][8]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#795 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[5][8]_P/C is not reached by a timing clock +Related violations: + +TIMING-17#796 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[5][9]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#797 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[5][9]_P/C is not reached by a timing clock +Related violations: + +TIMING-17#798 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[6][0]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#799 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[6][1]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#800 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[6][2]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#801 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[6][3]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#802 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[6][4]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#803 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[6][5]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#804 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[6][6]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#805 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[6][7]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#806 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[6][8]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#807 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[6][8]_P/C is not reached by a timing clock +Related violations: + +TIMING-17#808 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[6][9]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#809 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[6][9]_P/C is not reached by a timing clock +Related violations: + +TIMING-17#810 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[7][0]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#811 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[7][1]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#812 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[7][2]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#813 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[7][3]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#814 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[7][4]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#815 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[7][5]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#816 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[7][6]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#817 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[7][7]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#818 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[7][8]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#819 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[7][8]_P/C is not reached by a timing clock +Related violations: + +TIMING-17#820 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[7][9]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#821 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[7][9]_P/C is not reached by a timing clock +Related violations: + +TIMING-17#822 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[8][0]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#823 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[8][1]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#824 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[8][2]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#825 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[8][3]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#826 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[8][4]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#827 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[8][5]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#828 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[8][6]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#829 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[8][7]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#830 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[8][8]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#831 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[8][8]_P/C is not reached by a timing clock +Related violations: + +TIMING-17#832 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[8][9]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#833 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[8][9]_P/C is not reached by a timing clock +Related violations: + +TIMING-17#834 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[9][0]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#835 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[9][1]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#836 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[9][2]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#837 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[9][3]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#838 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[9][4]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#839 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[9][5]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#840 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[9][6]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#841 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[9][7]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#842 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[9][8]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#843 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[9][8]_P/C is not reached by a timing clock +Related violations: + +TIMING-17#844 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[9][9]_C/C is not reached by a timing clock +Related violations: + +TIMING-17#845 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYOffset_reg[9][9]_P/C is not reached by a timing clock +Related violations: + +TIMING-17#846 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocitySign_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#847 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocitySign_reg[10]/C is not reached by a timing clock +Related violations: + +TIMING-17#848 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocitySign_reg[11]/C is not reached by a timing clock +Related violations: + +TIMING-17#849 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocitySign_reg[12]/C is not reached by a timing clock +Related violations: + +TIMING-17#850 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocitySign_reg[13]/C is not reached by a timing clock +Related violations: + +TIMING-17#851 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocitySign_reg[14]/C is not reached by a timing clock +Related violations: + +TIMING-17#852 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocitySign_reg[15]/C is not reached by a timing clock +Related violations: + +TIMING-17#853 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocitySign_reg[16]/C is not reached by a timing clock +Related violations: + +TIMING-17#854 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocitySign_reg[17]/C is not reached by a timing clock +Related violations: + +TIMING-17#855 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocitySign_reg[18]/C is not reached by a timing clock +Related violations: + +TIMING-17#856 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocitySign_reg[19]/C is not reached by a timing clock +Related violations: + +TIMING-17#857 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocitySign_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#858 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocitySign_reg[20]/C is not reached by a timing clock +Related violations: + +TIMING-17#859 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocitySign_reg[2]/C is not reached by a timing clock +Related violations: + +TIMING-17#860 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocitySign_reg[3]/C is not reached by a timing clock +Related violations: + +TIMING-17#861 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocitySign_reg[4]/C is not reached by a timing clock +Related violations: + +TIMING-17#862 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocitySign_reg[5]/C is not reached by a timing clock +Related violations: + +TIMING-17#863 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocitySign_reg[6]/C is not reached by a timing clock +Related violations: + +TIMING-17#864 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocitySign_reg[7]/C is not reached by a timing clock +Related violations: + +TIMING-17#865 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocitySign_reg[8]/C is not reached by a timing clock +Related violations: + +TIMING-17#866 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocitySign_reg[9]/C is not reached by a timing clock +Related violations: + +TIMING-17#867 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[0][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#868 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[0][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#869 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[0][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#870 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[0][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#871 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[0][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#872 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[10][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#873 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[10][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#874 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[10][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#875 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[10][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#876 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[10][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#877 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[11][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#878 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[11][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#879 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[11][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#880 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[11][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#881 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[11][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#882 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[12][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#883 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[12][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#884 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[12][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#885 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[12][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#886 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[12][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#887 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[13][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#888 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[13][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#889 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[13][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#890 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[13][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#891 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[13][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#892 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[14][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#893 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[14][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#894 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[14][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#895 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[14][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#896 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[14][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#897 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[15][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#898 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[15][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#899 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[15][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#900 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[15][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#901 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[15][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#902 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[16][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#903 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[16][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#904 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[16][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#905 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[16][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#906 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[16][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#907 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[17][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#908 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[17][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#909 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[17][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#910 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[17][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#911 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[17][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#912 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[18][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#913 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[18][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#914 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[18][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#915 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[18][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#916 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[18][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#917 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[19][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#918 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[19][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#919 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[19][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#920 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[19][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#921 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[19][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#922 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[1][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#923 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[1][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#924 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[1][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#925 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[1][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#926 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[1][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#927 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[20][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#928 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[20][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#929 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[20][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#930 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[20][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#931 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[20][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#932 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[2][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#933 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[2][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#934 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[2][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#935 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[2][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#936 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[2][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#937 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[3][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#938 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[3][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#939 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[3][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#940 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[3][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#941 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[3][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#942 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[4][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#943 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[4][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#944 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[4][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#945 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[4][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#946 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[4][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#947 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[5][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#948 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[5][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#949 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[5][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#950 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[5][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#951 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[5][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#952 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[6][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#953 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[6][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#954 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[6][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#955 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[6][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#956 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[6][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#957 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[7][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#958 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[7][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#959 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[7][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#960 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[7][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#961 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[7][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#962 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[8][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#963 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[8][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#964 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[8][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#965 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[8][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#966 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[8][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#967 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[9][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#968 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[9][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#969 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[9][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#970 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[9][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#971 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redPieceYVelocity_reg[9][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#972 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redWinXOffset_reg[0][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#973 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redWinXOffset_reg[0][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#974 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redWinXOffset_reg[0][5]/C is not reached by a timing clock +Related violations: + +TIMING-17#975 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redWinXOffset_reg[0][6]/C is not reached by a timing clock +Related violations: + +TIMING-17#976 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redWinXOffset_reg[1][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#977 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redWinXOffset_reg[1][2]/C is not reached by a timing clock +Related violations: + +TIMING-17#978 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redWinXOffset_reg[1][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#979 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redWinXOffset_reg[1][5]/C is not reached by a timing clock +Related violations: + +TIMING-17#980 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redWinXOffset_reg[1][6]/C is not reached by a timing clock +Related violations: + +TIMING-17#981 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redWinXOffset_reg[2][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#982 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redWinXOffset_reg[2][3]/C is not reached by a timing clock +Related violations: + +TIMING-17#983 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redWinXOffset_reg[2][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#984 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redWinXOffset_reg[2][5]/C is not reached by a timing clock +Related violations: + +TIMING-17#985 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redWinXOffset_reg[2][6]/C is not reached by a timing clock +Related violations: + +TIMING-17#986 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redWinXOffset_reg[3][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#987 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redWinXOffset_reg[3][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#988 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redWinXOffset_reg[3][5]/C is not reached by a timing clock +Related violations: + +TIMING-17#989 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redWinXOffset_reg[3][6]/C is not reached by a timing clock +Related violations: + +TIMING-17#990 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redWinXOffset_reg[4][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#991 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redWinXOffset_reg[4][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#992 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redWinXOffset_reg[4][5]/C is not reached by a timing clock +Related violations: + +TIMING-17#993 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redWinXOffset_reg[4][6]/C is not reached by a timing clock +Related violations: + +TIMING-17#994 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redWinXOffset_reg[5][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#995 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redWinXOffset_reg[5][4]/C is not reached by a timing clock +Related violations: + +TIMING-17#996 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redWinXOffset_reg[5][5]/C is not reached by a timing clock +Related violations: + +TIMING-17#997 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redWinXOffset_reg[5][6]/C is not reached by a timing clock +Related violations: + +TIMING-17#998 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redWinXOffset_reg[6][0]/C is not reached by a timing clock +Related violations: + +TIMING-17#999 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redWinXOffset_reg[6][1]/C is not reached by a timing clock +Related violations: + +TIMING-17#1000 Critical Warning +Non-clocked sequential cell +The clock pin core_design/redWinXOffset_reg[6][4]/C is not reached by a timing clock +Related violations: + +LUTAR-1#1 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[0][8]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[0][8]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#2 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[0][8]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[0][8]_C/CLR +core_design/redPieceYOffset_reg[0][8]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#3 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[0][9]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[0][9]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#4 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[0][9]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[0][9]_C/CLR +core_design/redPieceYOffset_reg[0][9]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#5 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[10][8]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[10][8]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#6 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[10][8]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[10][8]_C/CLR +core_design/redPieceYOffset_reg[10][8]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#7 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[10][9]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[10][9]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#8 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[10][9]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[10][9]_C/CLR +core_design/redPieceYOffset_reg[10][9]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#9 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[11][8]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[11][8]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#10 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[11][8]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[11][8]_C/CLR +core_design/redPieceYOffset_reg[11][8]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#11 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[11][9]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[11][9]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#12 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[11][9]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[11][9]_C/CLR +core_design/redPieceYOffset_reg[11][9]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#13 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[12][8]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[12][8]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#14 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[12][8]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[12][8]_C/CLR +core_design/redPieceYOffset_reg[12][8]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#15 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[12][9]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[12][9]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#16 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[12][9]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[12][9]_C/CLR +core_design/redPieceYOffset_reg[12][9]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#17 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[13][8]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[13][8]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#18 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[13][8]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[13][8]_C/CLR +core_design/redPieceYOffset_reg[13][8]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#19 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[13][9]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[13][9]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#20 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[13][9]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[13][9]_C/CLR +core_design/redPieceYOffset_reg[13][9]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#21 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[14][8]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[14][8]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#22 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[14][8]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[14][8]_C/CLR +core_design/redPieceYOffset_reg[14][8]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#23 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[14][9]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[14][9]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#24 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[14][9]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[14][9]_C/CLR +core_design/redPieceYOffset_reg[14][9]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#25 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[15][8]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[15][8]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#26 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[15][8]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[15][8]_C/CLR +core_design/redPieceYOffset_reg[15][8]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#27 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[15][9]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[15][9]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#28 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[15][9]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[15][9]_C/CLR +core_design/redPieceYOffset_reg[15][9]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#29 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[16][8]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[16][8]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#30 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[16][8]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[16][8]_C/CLR +core_design/redPieceYOffset_reg[16][8]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#31 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[16][9]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[16][9]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#32 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[16][9]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[16][9]_C/CLR +core_design/redPieceYOffset_reg[16][9]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#33 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[17][8]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[17][8]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#34 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[17][8]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[17][8]_C/CLR +core_design/redPieceYOffset_reg[17][8]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#35 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[17][9]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[17][9]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#36 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[17][9]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[17][9]_C/CLR +core_design/redPieceYOffset_reg[17][9]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#37 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[18][8]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[18][8]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#38 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[18][8]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[18][8]_C/CLR +core_design/redPieceYOffset_reg[18][8]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#39 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[18][9]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[18][9]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#40 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[18][9]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[18][9]_C/CLR +core_design/redPieceYOffset_reg[18][9]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#41 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[19][8]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[19][8]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#42 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[19][8]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[19][8]_C/CLR +core_design/redPieceYOffset_reg[19][8]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#43 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[19][9]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[19][9]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#44 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[19][9]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[19][9]_C/CLR +core_design/redPieceYOffset_reg[19][9]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#45 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[20][8]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[20][8]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#46 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[20][8]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[20][8]_C/CLR +core_design/redPieceYOffset_reg[20][8]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#47 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[20][9]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[20][9]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#48 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[20][9]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[20][9]_C/CLR +core_design/redPieceYOffset_reg[20][9]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#49 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[2][8]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[2][8]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#50 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[2][8]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[2][8]_C/CLR +core_design/redPieceYOffset_reg[2][8]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#51 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[2][9]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[2][9]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#52 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[2][9]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[2][9]_C/CLR +core_design/redPieceYOffset_reg[2][9]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#53 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[3][8]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[3][8]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#54 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[3][8]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[3][8]_C/CLR +core_design/redPieceYOffset_reg[3][8]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#55 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[3][9]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[3][9]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#56 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[3][9]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[3][9]_C/CLR +core_design/redPieceYOffset_reg[3][9]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#57 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[4][8]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[4][8]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#58 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[4][8]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[4][8]_C/CLR +core_design/redPieceYOffset_reg[4][8]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#59 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[4][9]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[4][9]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#60 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[4][9]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[4][9]_C/CLR +core_design/redPieceYOffset_reg[4][9]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#61 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[5][8]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[5][8]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#62 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[5][8]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[5][8]_C/CLR +core_design/redPieceYOffset_reg[5][8]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#63 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[5][9]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[5][9]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#64 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[5][9]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[5][9]_C/CLR +core_design/redPieceYOffset_reg[5][9]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#65 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[6][8]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[6][8]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#66 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[6][8]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[6][8]_C/CLR +core_design/redPieceYOffset_reg[6][8]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#67 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[6][9]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[6][9]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#68 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[6][9]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[6][9]_C/CLR +core_design/redPieceYOffset_reg[6][9]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#69 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[7][8]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[7][8]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#70 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[7][8]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[7][8]_C/CLR +core_design/redPieceYOffset_reg[7][8]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#71 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[7][9]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[7][9]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#72 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[7][9]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[7][9]_C/CLR +core_design/redPieceYOffset_reg[7][9]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#73 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[8][8]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[8][8]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#74 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[8][8]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[8][8]_C/CLR +core_design/redPieceYOffset_reg[8][8]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#75 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[8][9]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[8][9]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#76 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[8][9]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[8][9]_C/CLR +core_design/redPieceYOffset_reg[8][9]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#77 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[9][8]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[9][8]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#78 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[9][8]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[9][8]_C/CLR +core_design/redPieceYOffset_reg[9][8]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#79 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[9][9]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[9][9]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#80 Warning +LUT drives async reset alert +LUT cell core_design/redPieceYOffset_reg[9][9]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/redPieceYOffset_reg[9][9]_C/CLR +core_design/redPieceYOffset_reg[9][9]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#81 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[0][8]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[0][8]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#82 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[0][8]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[0][8]_C/CLR +core_design/yellowPieceYOffset_reg[0][8]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#83 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[0][9]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[0][9]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#84 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[0][9]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[0][9]_C/CLR +core_design/yellowPieceYOffset_reg[0][9]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#85 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[10][8]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[10][8]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#86 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[10][8]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[10][8]_C/CLR +core_design/yellowPieceYOffset_reg[10][8]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#87 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[10][9]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[10][9]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#88 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[10][9]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[10][9]_C/CLR +core_design/yellowPieceYOffset_reg[10][9]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#89 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[11][8]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[11][8]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#90 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[11][8]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[11][8]_C/CLR +core_design/yellowPieceYOffset_reg[11][8]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#91 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[11][9]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[11][9]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#92 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[11][9]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[11][9]_C/CLR +core_design/yellowPieceYOffset_reg[11][9]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#93 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[12][8]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[12][8]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#94 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[12][8]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[12][8]_C/CLR +core_design/yellowPieceYOffset_reg[12][8]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#95 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[12][9]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[12][9]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#96 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[12][9]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[12][9]_C/CLR +core_design/yellowPieceYOffset_reg[12][9]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#97 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[13][8]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[13][8]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#98 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[13][8]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[13][8]_C/CLR +core_design/yellowPieceYOffset_reg[13][8]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#99 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[13][9]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[13][9]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#100 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[13][9]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[13][9]_C/CLR +core_design/yellowPieceYOffset_reg[13][9]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#101 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[14][8]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[14][8]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#102 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[14][8]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[14][8]_C/CLR +core_design/yellowPieceYOffset_reg[14][8]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#103 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[14][9]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[14][9]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#104 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[14][9]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[14][9]_C/CLR +core_design/yellowPieceYOffset_reg[14][9]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#105 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[15][8]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[15][8]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#106 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[15][8]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[15][8]_C/CLR +core_design/yellowPieceYOffset_reg[15][8]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#107 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[15][9]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[15][9]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#108 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[15][9]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[15][9]_C/CLR +core_design/yellowPieceYOffset_reg[15][9]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#109 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[17][8]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[17][8]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#110 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[17][8]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[17][8]_C/CLR +core_design/yellowPieceYOffset_reg[17][8]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#111 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[17][9]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[17][9]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#112 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[17][9]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[17][9]_C/CLR +core_design/yellowPieceYOffset_reg[17][9]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#113 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[18][8]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[18][8]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#114 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[18][8]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[18][8]_C/CLR +core_design/yellowPieceYOffset_reg[18][8]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#115 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[18][9]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[18][9]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#116 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[18][9]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[18][9]_C/CLR +core_design/yellowPieceYOffset_reg[18][9]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#117 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[19][8]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[19][8]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#118 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[19][8]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[19][8]_C/CLR +core_design/yellowPieceYOffset_reg[19][8]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#119 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[19][9]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[19][9]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#120 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[19][9]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[19][9]_C/CLR +core_design/yellowPieceYOffset_reg[19][9]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#121 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[1][3]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[1][3]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#122 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[1][3]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[1][3]_C/CLR +core_design/yellowPieceYOffset_reg[1][3]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#123 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[1][5]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[1][5]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#124 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[1][5]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[1][5]_C/CLR +core_design/yellowPieceYOffset_reg[1][5]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#125 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[1][8]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[1][8]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#126 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[1][8]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[1][8]_C/CLR +core_design/yellowPieceYOffset_reg[1][8]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#127 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[1][9]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[1][9]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#128 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[1][9]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[1][9]_C/CLR +core_design/yellowPieceYOffset_reg[1][9]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#129 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[20][8]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[20][8]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#130 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[20][8]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[20][8]_C/CLR +core_design/yellowPieceYOffset_reg[20][8]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#131 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[20][9]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[20][9]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#132 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[20][9]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[20][9]_C/CLR +core_design/yellowPieceYOffset_reg[20][9]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#133 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[2][8]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[2][8]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#134 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[2][8]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[2][8]_C/CLR +core_design/yellowPieceYOffset_reg[2][8]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#135 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[2][9]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[2][9]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#136 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[2][9]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[2][9]_C/CLR +core_design/yellowPieceYOffset_reg[2][9]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#137 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[3][8]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[3][8]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#138 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[3][8]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[3][8]_C/CLR +core_design/yellowPieceYOffset_reg[3][8]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#139 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[3][9]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[3][9]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#140 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[3][9]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[3][9]_C/CLR +core_design/yellowPieceYOffset_reg[3][9]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#141 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[4][8]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[4][8]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#142 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[4][8]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[4][8]_C/CLR +core_design/yellowPieceYOffset_reg[4][8]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#143 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[4][9]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[4][9]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#144 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[4][9]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[4][9]_C/CLR +core_design/yellowPieceYOffset_reg[4][9]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#145 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[5][8]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[5][8]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#146 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[5][8]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[5][8]_C/CLR +core_design/yellowPieceYOffset_reg[5][8]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#147 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[5][9]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[5][9]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#148 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[5][9]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[5][9]_C/CLR +core_design/yellowPieceYOffset_reg[5][9]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#149 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[6][8]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[6][8]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#150 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[6][8]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[6][8]_C/CLR +core_design/yellowPieceYOffset_reg[6][8]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#151 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[6][9]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[6][9]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#152 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[6][9]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[6][9]_C/CLR +core_design/yellowPieceYOffset_reg[6][9]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#153 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[7][0]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[7][0]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#154 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[7][0]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[7][0]_C/CLR +core_design/yellowPieceYOffset_reg[7][0]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#155 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[7][1]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[7][1]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#156 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[7][1]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[7][1]_C/CLR +core_design/yellowPieceYOffset_reg[7][1]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#157 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[7][2]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[7][2]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#158 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[7][2]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[7][2]_C/CLR +core_design/yellowPieceYOffset_reg[7][2]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#159 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[7][3]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[7][3]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#160 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[7][3]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[7][3]_C/CLR +core_design/yellowPieceYOffset_reg[7][3]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#161 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[7][4]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[7][4]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#162 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[7][4]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[7][4]_C/CLR +core_design/yellowPieceYOffset_reg[7][4]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#163 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[7][5]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[7][5]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#164 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[7][5]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[7][5]_C/CLR +core_design/yellowPieceYOffset_reg[7][5]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#165 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[7][6]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[7][6]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#166 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[7][6]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[7][6]_C/CLR +core_design/yellowPieceYOffset_reg[7][6]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#167 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[7][7]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[7][7]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#168 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[7][7]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[7][7]_C/CLR +core_design/yellowPieceYOffset_reg[7][7]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#169 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[7][8]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[7][8]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#170 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[7][8]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[7][8]_C/CLR +core_design/yellowPieceYOffset_reg[7][8]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#171 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[7][9]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[7][9]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#172 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[7][9]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[7][9]_C/CLR +core_design/yellowPieceYOffset_reg[7][9]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#173 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[8][0]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[8][0]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#174 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[8][0]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[8][0]_C/CLR +core_design/yellowPieceYOffset_reg[8][0]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#175 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[8][1]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[8][1]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#176 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[8][1]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[8][1]_C/CLR +core_design/yellowPieceYOffset_reg[8][1]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#177 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[8][2]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[8][2]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#178 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[8][2]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[8][2]_C/CLR +core_design/yellowPieceYOffset_reg[8][2]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#179 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[8][3]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[8][3]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#180 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[8][3]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[8][3]_C/CLR +core_design/yellowPieceYOffset_reg[8][3]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#181 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[8][4]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[8][4]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#182 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[8][4]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[8][4]_C/CLR +core_design/yellowPieceYOffset_reg[8][4]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#183 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[8][5]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[8][5]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#184 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[8][5]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[8][5]_C/CLR +core_design/yellowPieceYOffset_reg[8][5]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#185 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[8][6]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[8][6]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#186 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[8][6]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[8][6]_C/CLR +core_design/yellowPieceYOffset_reg[8][6]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#187 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[8][7]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[8][7]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#188 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[8][7]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[8][7]_C/CLR +core_design/yellowPieceYOffset_reg[8][7]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#189 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[8][8]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[8][8]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#190 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[8][8]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[8][8]_C/CLR +core_design/yellowPieceYOffset_reg[8][8]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#191 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[8][9]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[8][9]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#192 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[8][9]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[8][9]_C/CLR +core_design/yellowPieceYOffset_reg[8][9]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#193 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[9][8]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[9][8]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#194 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[9][8]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[9][8]_C/CLR +core_design/yellowPieceYOffset_reg[9][8]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#195 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[9][9]_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[9][9]_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#196 Warning +LUT drives async reset alert +LUT cell core_design/yellowPieceYOffset_reg[9][9]_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) core_design/yellowPieceYOffset_reg[9][9]_C/CLR +core_design/yellowPieceYOffset_reg[9][9]_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +TIMING-20#1 Warning +Non-clocked latch +The latch core_design/redPieceYOffset_reg[0][8]_LDC cannot be properly analyzed as its control pin core_design/redPieceYOffset_reg[0][8]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#2 Warning +Non-clocked latch +The latch core_design/redPieceYOffset_reg[0][9]_LDC cannot be properly analyzed as its control pin core_design/redPieceYOffset_reg[0][9]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#3 Warning +Non-clocked latch +The latch core_design/redPieceYOffset_reg[10][8]_LDC cannot be properly analyzed as its control pin core_design/redPieceYOffset_reg[10][8]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#4 Warning +Non-clocked latch +The latch core_design/redPieceYOffset_reg[10][9]_LDC cannot be properly analyzed as its control pin core_design/redPieceYOffset_reg[10][9]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#5 Warning +Non-clocked latch +The latch core_design/redPieceYOffset_reg[11][8]_LDC cannot be properly analyzed as its control pin core_design/redPieceYOffset_reg[11][8]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#6 Warning +Non-clocked latch +The latch core_design/redPieceYOffset_reg[11][9]_LDC cannot be properly analyzed as its control pin core_design/redPieceYOffset_reg[11][9]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#7 Warning +Non-clocked latch +The latch core_design/redPieceYOffset_reg[12][8]_LDC cannot be properly analyzed as its control pin core_design/redPieceYOffset_reg[12][8]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#8 Warning +Non-clocked latch +The latch core_design/redPieceYOffset_reg[12][9]_LDC cannot be properly analyzed as its control pin core_design/redPieceYOffset_reg[12][9]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#9 Warning +Non-clocked latch +The latch core_design/redPieceYOffset_reg[13][8]_LDC cannot be properly analyzed as its control pin core_design/redPieceYOffset_reg[13][8]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#10 Warning +Non-clocked latch +The latch core_design/redPieceYOffset_reg[13][9]_LDC cannot be properly analyzed as its control pin core_design/redPieceYOffset_reg[13][9]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#11 Warning +Non-clocked latch +The latch core_design/redPieceYOffset_reg[14][8]_LDC cannot be properly analyzed as its control pin core_design/redPieceYOffset_reg[14][8]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#12 Warning +Non-clocked latch +The latch core_design/redPieceYOffset_reg[14][9]_LDC cannot be properly analyzed as its control pin core_design/redPieceYOffset_reg[14][9]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#13 Warning +Non-clocked latch +The latch core_design/redPieceYOffset_reg[15][8]_LDC cannot be properly analyzed as its control pin core_design/redPieceYOffset_reg[15][8]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#14 Warning +Non-clocked latch +The latch core_design/redPieceYOffset_reg[15][9]_LDC cannot be properly analyzed as its control pin core_design/redPieceYOffset_reg[15][9]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#15 Warning +Non-clocked latch +The latch core_design/redPieceYOffset_reg[16][8]_LDC cannot be properly analyzed as its control pin core_design/redPieceYOffset_reg[16][8]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#16 Warning +Non-clocked latch +The latch core_design/redPieceYOffset_reg[16][9]_LDC cannot be properly analyzed as its control pin core_design/redPieceYOffset_reg[16][9]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#17 Warning +Non-clocked latch +The latch core_design/redPieceYOffset_reg[17][8]_LDC cannot be properly analyzed as its control pin core_design/redPieceYOffset_reg[17][8]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#18 Warning +Non-clocked latch +The latch core_design/redPieceYOffset_reg[17][9]_LDC cannot be properly analyzed as its control pin core_design/redPieceYOffset_reg[17][9]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#19 Warning +Non-clocked latch +The latch core_design/redPieceYOffset_reg[18][8]_LDC cannot be properly analyzed as its control pin core_design/redPieceYOffset_reg[18][8]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#20 Warning +Non-clocked latch +The latch core_design/redPieceYOffset_reg[18][9]_LDC cannot be properly analyzed as its control pin core_design/redPieceYOffset_reg[18][9]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#21 Warning +Non-clocked latch +The latch core_design/redPieceYOffset_reg[19][8]_LDC cannot be properly analyzed as its control pin core_design/redPieceYOffset_reg[19][8]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#22 Warning +Non-clocked latch +The latch core_design/redPieceYOffset_reg[19][9]_LDC cannot be properly analyzed as its control pin core_design/redPieceYOffset_reg[19][9]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#23 Warning +Non-clocked latch +The latch core_design/redPieceYOffset_reg[20][8]_LDC cannot be properly analyzed as its control pin core_design/redPieceYOffset_reg[20][8]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#24 Warning +Non-clocked latch +The latch core_design/redPieceYOffset_reg[20][9]_LDC cannot be properly analyzed as its control pin core_design/redPieceYOffset_reg[20][9]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#25 Warning +Non-clocked latch +The latch core_design/redPieceYOffset_reg[2][8]_LDC cannot be properly analyzed as its control pin core_design/redPieceYOffset_reg[2][8]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#26 Warning +Non-clocked latch +The latch core_design/redPieceYOffset_reg[2][9]_LDC cannot be properly analyzed as its control pin core_design/redPieceYOffset_reg[2][9]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#27 Warning +Non-clocked latch +The latch core_design/redPieceYOffset_reg[3][8]_LDC cannot be properly analyzed as its control pin core_design/redPieceYOffset_reg[3][8]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#28 Warning +Non-clocked latch +The latch core_design/redPieceYOffset_reg[3][9]_LDC cannot be properly analyzed as its control pin core_design/redPieceYOffset_reg[3][9]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#29 Warning +Non-clocked latch +The latch core_design/redPieceYOffset_reg[4][8]_LDC cannot be properly analyzed as its control pin core_design/redPieceYOffset_reg[4][8]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#30 Warning +Non-clocked latch +The latch core_design/redPieceYOffset_reg[4][9]_LDC cannot be properly analyzed as its control pin core_design/redPieceYOffset_reg[4][9]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#31 Warning +Non-clocked latch +The latch core_design/redPieceYOffset_reg[5][8]_LDC cannot be properly analyzed as its control pin core_design/redPieceYOffset_reg[5][8]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#32 Warning +Non-clocked latch +The latch core_design/redPieceYOffset_reg[5][9]_LDC cannot be properly analyzed as its control pin core_design/redPieceYOffset_reg[5][9]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#33 Warning +Non-clocked latch +The latch core_design/redPieceYOffset_reg[6][8]_LDC cannot be properly analyzed as its control pin core_design/redPieceYOffset_reg[6][8]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#34 Warning +Non-clocked latch +The latch core_design/redPieceYOffset_reg[6][9]_LDC cannot be properly analyzed as its control pin core_design/redPieceYOffset_reg[6][9]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#35 Warning +Non-clocked latch +The latch core_design/redPieceYOffset_reg[7][8]_LDC cannot be properly analyzed as its control pin core_design/redPieceYOffset_reg[7][8]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#36 Warning +Non-clocked latch +The latch core_design/redPieceYOffset_reg[7][9]_LDC cannot be properly analyzed as its control pin core_design/redPieceYOffset_reg[7][9]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#37 Warning +Non-clocked latch +The latch core_design/redPieceYOffset_reg[8][8]_LDC cannot be properly analyzed as its control pin core_design/redPieceYOffset_reg[8][8]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#38 Warning +Non-clocked latch +The latch core_design/redPieceYOffset_reg[8][9]_LDC cannot be properly analyzed as its control pin core_design/redPieceYOffset_reg[8][9]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#39 Warning +Non-clocked latch +The latch core_design/redPieceYOffset_reg[9][8]_LDC cannot be properly analyzed as its control pin core_design/redPieceYOffset_reg[9][8]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#40 Warning +Non-clocked latch +The latch core_design/redPieceYOffset_reg[9][9]_LDC cannot be properly analyzed as its control pin core_design/redPieceYOffset_reg[9][9]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#41 Warning +Non-clocked latch +The latch core_design/yellowPieceYOffset_reg[0][8]_LDC cannot be properly analyzed as its control pin core_design/yellowPieceYOffset_reg[0][8]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#42 Warning +Non-clocked latch +The latch core_design/yellowPieceYOffset_reg[0][9]_LDC cannot be properly analyzed as its control pin core_design/yellowPieceYOffset_reg[0][9]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#43 Warning +Non-clocked latch +The latch core_design/yellowPieceYOffset_reg[10][8]_LDC cannot be properly analyzed as its control pin core_design/yellowPieceYOffset_reg[10][8]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#44 Warning +Non-clocked latch +The latch core_design/yellowPieceYOffset_reg[10][9]_LDC cannot be properly analyzed as its control pin core_design/yellowPieceYOffset_reg[10][9]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#45 Warning +Non-clocked latch +The latch core_design/yellowPieceYOffset_reg[11][8]_LDC cannot be properly analyzed as its control pin core_design/yellowPieceYOffset_reg[11][8]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#46 Warning +Non-clocked latch +The latch core_design/yellowPieceYOffset_reg[11][9]_LDC cannot be properly analyzed as its control pin core_design/yellowPieceYOffset_reg[11][9]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#47 Warning +Non-clocked latch +The latch core_design/yellowPieceYOffset_reg[12][8]_LDC cannot be properly analyzed as its control pin core_design/yellowPieceYOffset_reg[12][8]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#48 Warning +Non-clocked latch +The latch core_design/yellowPieceYOffset_reg[12][9]_LDC cannot be properly analyzed as its control pin core_design/yellowPieceYOffset_reg[12][9]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#49 Warning +Non-clocked latch +The latch core_design/yellowPieceYOffset_reg[13][8]_LDC cannot be properly analyzed as its control pin core_design/yellowPieceYOffset_reg[13][8]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#50 Warning +Non-clocked latch +The latch core_design/yellowPieceYOffset_reg[13][9]_LDC cannot be properly analyzed as its control pin core_design/yellowPieceYOffset_reg[13][9]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#51 Warning +Non-clocked latch +The latch core_design/yellowPieceYOffset_reg[14][8]_LDC cannot be properly analyzed as its control pin core_design/yellowPieceYOffset_reg[14][8]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#52 Warning +Non-clocked latch +The latch core_design/yellowPieceYOffset_reg[14][9]_LDC cannot be properly analyzed as its control pin core_design/yellowPieceYOffset_reg[14][9]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#53 Warning +Non-clocked latch +The latch core_design/yellowPieceYOffset_reg[15][8]_LDC cannot be properly analyzed as its control pin core_design/yellowPieceYOffset_reg[15][8]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#54 Warning +Non-clocked latch +The latch core_design/yellowPieceYOffset_reg[15][9]_LDC cannot be properly analyzed as its control pin core_design/yellowPieceYOffset_reg[15][9]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#55 Warning +Non-clocked latch +The latch core_design/yellowPieceYOffset_reg[17][8]_LDC cannot be properly analyzed as its control pin core_design/yellowPieceYOffset_reg[17][8]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#56 Warning +Non-clocked latch +The latch core_design/yellowPieceYOffset_reg[17][9]_LDC cannot be properly analyzed as its control pin core_design/yellowPieceYOffset_reg[17][9]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#57 Warning +Non-clocked latch +The latch core_design/yellowPieceYOffset_reg[18][8]_LDC cannot be properly analyzed as its control pin core_design/yellowPieceYOffset_reg[18][8]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#58 Warning +Non-clocked latch +The latch core_design/yellowPieceYOffset_reg[18][9]_LDC cannot be properly analyzed as its control pin core_design/yellowPieceYOffset_reg[18][9]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#59 Warning +Non-clocked latch +The latch core_design/yellowPieceYOffset_reg[19][8]_LDC cannot be properly analyzed as its control pin core_design/yellowPieceYOffset_reg[19][8]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#60 Warning +Non-clocked latch +The latch core_design/yellowPieceYOffset_reg[19][9]_LDC cannot be properly analyzed as its control pin core_design/yellowPieceYOffset_reg[19][9]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#61 Warning +Non-clocked latch +The latch core_design/yellowPieceYOffset_reg[1][3]_LDC cannot be properly analyzed as its control pin core_design/yellowPieceYOffset_reg[1][3]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#62 Warning +Non-clocked latch +The latch core_design/yellowPieceYOffset_reg[1][5]_LDC cannot be properly analyzed as its control pin core_design/yellowPieceYOffset_reg[1][5]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#63 Warning +Non-clocked latch +The latch core_design/yellowPieceYOffset_reg[1][8]_LDC cannot be properly analyzed as its control pin core_design/yellowPieceYOffset_reg[1][8]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#64 Warning +Non-clocked latch +The latch core_design/yellowPieceYOffset_reg[1][9]_LDC cannot be properly analyzed as its control pin core_design/yellowPieceYOffset_reg[1][9]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#65 Warning +Non-clocked latch +The latch core_design/yellowPieceYOffset_reg[20][8]_LDC cannot be properly analyzed as its control pin core_design/yellowPieceYOffset_reg[20][8]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#66 Warning +Non-clocked latch +The latch core_design/yellowPieceYOffset_reg[20][9]_LDC cannot be properly analyzed as its control pin core_design/yellowPieceYOffset_reg[20][9]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#67 Warning +Non-clocked latch +The latch core_design/yellowPieceYOffset_reg[2][8]_LDC cannot be properly analyzed as its control pin core_design/yellowPieceYOffset_reg[2][8]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#68 Warning +Non-clocked latch +The latch core_design/yellowPieceYOffset_reg[2][9]_LDC cannot be properly analyzed as its control pin core_design/yellowPieceYOffset_reg[2][9]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#69 Warning +Non-clocked latch +The latch core_design/yellowPieceYOffset_reg[3][8]_LDC cannot be properly analyzed as its control pin core_design/yellowPieceYOffset_reg[3][8]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#70 Warning +Non-clocked latch +The latch core_design/yellowPieceYOffset_reg[3][9]_LDC cannot be properly analyzed as its control pin core_design/yellowPieceYOffset_reg[3][9]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#71 Warning +Non-clocked latch +The latch core_design/yellowPieceYOffset_reg[4][8]_LDC cannot be properly analyzed as its control pin core_design/yellowPieceYOffset_reg[4][8]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#72 Warning +Non-clocked latch +The latch core_design/yellowPieceYOffset_reg[4][9]_LDC cannot be properly analyzed as its control pin core_design/yellowPieceYOffset_reg[4][9]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#73 Warning +Non-clocked latch +The latch core_design/yellowPieceYOffset_reg[5][8]_LDC cannot be properly analyzed as its control pin core_design/yellowPieceYOffset_reg[5][8]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#74 Warning +Non-clocked latch +The latch core_design/yellowPieceYOffset_reg[5][9]_LDC cannot be properly analyzed as its control pin core_design/yellowPieceYOffset_reg[5][9]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#75 Warning +Non-clocked latch +The latch core_design/yellowPieceYOffset_reg[6][8]_LDC cannot be properly analyzed as its control pin core_design/yellowPieceYOffset_reg[6][8]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#76 Warning +Non-clocked latch +The latch core_design/yellowPieceYOffset_reg[6][9]_LDC cannot be properly analyzed as its control pin core_design/yellowPieceYOffset_reg[6][9]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#77 Warning +Non-clocked latch +The latch core_design/yellowPieceYOffset_reg[7][0]_LDC cannot be properly analyzed as its control pin core_design/yellowPieceYOffset_reg[7][0]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#78 Warning +Non-clocked latch +The latch core_design/yellowPieceYOffset_reg[7][1]_LDC cannot be properly analyzed as its control pin core_design/yellowPieceYOffset_reg[7][1]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#79 Warning +Non-clocked latch +The latch core_design/yellowPieceYOffset_reg[7][2]_LDC cannot be properly analyzed as its control pin core_design/yellowPieceYOffset_reg[7][2]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#80 Warning +Non-clocked latch +The latch core_design/yellowPieceYOffset_reg[7][3]_LDC cannot be properly analyzed as its control pin core_design/yellowPieceYOffset_reg[7][3]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#81 Warning +Non-clocked latch +The latch core_design/yellowPieceYOffset_reg[7][4]_LDC cannot be properly analyzed as its control pin core_design/yellowPieceYOffset_reg[7][4]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#82 Warning +Non-clocked latch +The latch core_design/yellowPieceYOffset_reg[7][5]_LDC cannot be properly analyzed as its control pin core_design/yellowPieceYOffset_reg[7][5]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#83 Warning +Non-clocked latch +The latch core_design/yellowPieceYOffset_reg[7][6]_LDC cannot be properly analyzed as its control pin core_design/yellowPieceYOffset_reg[7][6]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#84 Warning +Non-clocked latch +The latch core_design/yellowPieceYOffset_reg[7][7]_LDC cannot be properly analyzed as its control pin core_design/yellowPieceYOffset_reg[7][7]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#85 Warning +Non-clocked latch +The latch core_design/yellowPieceYOffset_reg[7][8]_LDC cannot be properly analyzed as its control pin core_design/yellowPieceYOffset_reg[7][8]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#86 Warning +Non-clocked latch +The latch core_design/yellowPieceYOffset_reg[7][9]_LDC cannot be properly analyzed as its control pin core_design/yellowPieceYOffset_reg[7][9]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#87 Warning +Non-clocked latch +The latch core_design/yellowPieceYOffset_reg[8][0]_LDC cannot be properly analyzed as its control pin core_design/yellowPieceYOffset_reg[8][0]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#88 Warning +Non-clocked latch +The latch core_design/yellowPieceYOffset_reg[8][1]_LDC cannot be properly analyzed as its control pin core_design/yellowPieceYOffset_reg[8][1]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#89 Warning +Non-clocked latch +The latch core_design/yellowPieceYOffset_reg[8][2]_LDC cannot be properly analyzed as its control pin core_design/yellowPieceYOffset_reg[8][2]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#90 Warning +Non-clocked latch +The latch core_design/yellowPieceYOffset_reg[8][3]_LDC cannot be properly analyzed as its control pin core_design/yellowPieceYOffset_reg[8][3]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#91 Warning +Non-clocked latch +The latch core_design/yellowPieceYOffset_reg[8][4]_LDC cannot be properly analyzed as its control pin core_design/yellowPieceYOffset_reg[8][4]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#92 Warning +Non-clocked latch +The latch core_design/yellowPieceYOffset_reg[8][5]_LDC cannot be properly analyzed as its control pin core_design/yellowPieceYOffset_reg[8][5]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#93 Warning +Non-clocked latch +The latch core_design/yellowPieceYOffset_reg[8][6]_LDC cannot be properly analyzed as its control pin core_design/yellowPieceYOffset_reg[8][6]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#94 Warning +Non-clocked latch +The latch core_design/yellowPieceYOffset_reg[8][7]_LDC cannot be properly analyzed as its control pin core_design/yellowPieceYOffset_reg[8][7]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#95 Warning +Non-clocked latch +The latch core_design/yellowPieceYOffset_reg[8][8]_LDC cannot be properly analyzed as its control pin core_design/yellowPieceYOffset_reg[8][8]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#96 Warning +Non-clocked latch +The latch core_design/yellowPieceYOffset_reg[8][9]_LDC cannot be properly analyzed as its control pin core_design/yellowPieceYOffset_reg[8][9]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#97 Warning +Non-clocked latch +The latch core_design/yellowPieceYOffset_reg[9][8]_LDC cannot be properly analyzed as its control pin core_design/yellowPieceYOffset_reg[9][8]_LDC/G is not reached by a timing clock +Related violations: + +TIMING-20#98 Warning +Non-clocked latch +The latch core_design/yellowPieceYOffset_reg[9][9]_LDC cannot be properly analyzed as its control pin core_design/yellowPieceYOffset_reg[9][9]_LDC/G is not reached by a timing clock +Related violations: + +LATCH-1#1 Advisory +Existing latches in the design +There are 98 latches found in the design. Inferred latches are often the result of HDL coding mistakes, such as incomplete if or case statements. Related violations: diff --git a/vga.runs/impl_1/vga_methodology_drc_routed.rpx b/vga.runs/impl_1/vga_methodology_drc_routed.rpx index 6db2e21..c96b62b 100644 Binary files a/vga.runs/impl_1/vga_methodology_drc_routed.rpx and b/vga.runs/impl_1/vga_methodology_drc_routed.rpx differ diff --git a/vga.runs/impl_1/vga_opt.dcp b/vga.runs/impl_1/vga_opt.dcp index 7c1d229..d01d952 100644 Binary files a/vga.runs/impl_1/vga_opt.dcp and b/vga.runs/impl_1/vga_opt.dcp differ diff --git a/vga.runs/impl_1/vga_physopt.dcp b/vga.runs/impl_1/vga_physopt.dcp index 63c7f04..f9e60b5 100644 Binary files a/vga.runs/impl_1/vga_physopt.dcp and b/vga.runs/impl_1/vga_physopt.dcp differ diff --git a/vga.runs/impl_1/vga_placed.dcp b/vga.runs/impl_1/vga_placed.dcp index f9e0c25..436e47b 100644 Binary files a/vga.runs/impl_1/vga_placed.dcp and b/vga.runs/impl_1/vga_placed.dcp differ diff --git a/vga.runs/impl_1/vga_power_routed.rpt b/vga.runs/impl_1/vga_power_routed.rpt index e3df437..5a34580 100644 --- a/vga.runs/impl_1/vga_power_routed.rpt +++ b/vga.runs/impl_1/vga_power_routed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 -| Date : Thu Apr 18 03:15:50 2024 +| Date : Mon Apr 22 21:25:16 2024 | Host : me running 64-bit major release (build 9200) | Command : report_power -file vga_power_routed.rpt -pb vga_power_summary_routed.pb -rpx vga_power_routed.rpx | Design : vga @@ -29,20 +29,20 @@ Table of Contents 1. Summary ---------- -+--------------------------+--------------+ -| Total On-Chip Power (W) | 6.563 | -| Design Power Budget (W) | Unspecified* | -| Power Budget Margin (W) | NA | -| Dynamic (W) | 6.425 | -| Device Static (W) | 0.138 | -| Effective TJA (C/W) | 4.6 | -| Max Ambient (C) | 55.1 | -| Junction Temperature (C) | 54.9 | -| Confidence Level | Low | -| Setting File | --- | -| Simulation Activity File | --- | -| Design Nets Matched | NA | -+--------------------------+--------------+ ++--------------------------+----------------------------------+ +| Total On-Chip Power (W) | 87.423 (Junction temp exceeded!) | +| Design Power Budget (W) | Unspecified* | +| Power Budget Margin (W) | NA | +| Dynamic (W) | 86.626 | +| Device Static (W) | 0.797 | +| Effective TJA (C/W) | 4.6 | +| Max Ambient (C) | 0.0 | +| Junction Temperature (C) | 125.0 | +| Confidence Level | Low | +| Setting File | --- | +| Simulation Activity File | --- | +| Design Nets Matched | NA | ++--------------------------+----------------------------------+ * Specify Design Power Budget using, set_operating_conditions -design_power_budget @@ -52,17 +52,17 @@ Table of Contents +----------------+-----------+----------+-----------+-----------------+ | On-Chip | Power (W) | Used | Available | Utilization (%) | +----------------+-----------+----------+-----------+-----------------+ -| Slice Logic | 1.194 | 1560 | --- | --- | -| LUT as Logic | 1.095 | 1041 | 63400 | 1.64 | -| BUFG | 0.041 | 3 | 32 | 9.38 | -| Register | 0.032 | 218 | 126800 | 0.17 | -| CARRY4 | 0.024 | 102 | 15850 | 0.64 | -| F7/F8 Muxes | 0.001 | 19 | 63400 | 0.03 | -| Others | 0.000 | 94 | --- | --- | -| Signals | 1.073 | 1333 | --- | --- | -| I/O | 4.158 | 15 | 210 | 7.14 | -| Static Power | 0.138 | | | | -| Total | 6.563 | | | | +| Slice Logic | 42.476 | 26999 | --- | --- | +| LUT as Logic | 39.969 | 18983 | 63400 | 29.94 | +| CARRY4 | 1.791 | 1660 | 15850 | 10.47 | +| F7/F8 Muxes | 0.502 | 612 | 63400 | 0.97 | +| Register | 0.171 | 2308 | 126800 | 1.82 | +| BUFG | 0.041 | 4 | 32 | 12.50 | +| Others | 0.000 | 142 | --- | --- | +| Signals | 39.490 | 21334 | --- | --- | +| I/O | 4.661 | 20 | 210 | 9.52 | +| Static Power | 0.797 | | | | +| Total | 87.423 | | | | +----------------+-----------+----------+-----------+-----------------+ @@ -72,16 +72,16 @@ Table of Contents +-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+ | Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | Powerup (A) | Budget (A) | Margin (A) | +-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+ -| Vccint | 1.000 | 2.319 | 2.271 | 0.048 | NA | Unspecified | NA | -| Vccaux | 1.800 | 0.174 | 0.152 | 0.022 | NA | Unspecified | NA | -| Vcco33 | 3.300 | 1.180 | 1.176 | 0.004 | NA | Unspecified | NA | +| Vccint | 1.000 | 82.548 | 81.985 | 0.563 | NA | Unspecified | NA | +| Vccaux | 1.800 | 0.263 | 0.170 | 0.093 | NA | Unspecified | NA | +| Vcco33 | 3.300 | 1.317 | 1.313 | 0.004 | NA | Unspecified | NA | | Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | | Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | | Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | | Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | | Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | | Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | -| Vccbram | 1.000 | 0.001 | 0.000 | 0.001 | NA | Unspecified | NA | +| Vccbram | 1.000 | 0.018 | 0.000 | 0.018 | NA | Unspecified | NA | | MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | | MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | | Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | NA | Unspecified | NA | @@ -136,55 +136,78 @@ Table of Contents 3.1 By Hierarchy ---------------- -+--------------------------------+-----------+ -| Name | Power (W) | -+--------------------------------+-----------+ -| vga | 6.425 | -| board_gfx | 0.152 | -| corner_border_check_gfx | 0.006 | -| genblk1[0].red_piece_gfx | 0.032 | -| genblk1[10].red_piece_gfx | 0.016 | -| genblk1[11].red_piece_gfx | 0.018 | -| genblk1[12].red_piece_gfx | 0.017 | -| genblk1[13].red_piece_gfx | 0.039 | -| genblk1[14].red_piece_gfx | 0.040 | -| genblk1[15].red_piece_gfx | 0.038 | -| genblk1[16].red_piece_gfx | 0.043 | -| genblk1[17].red_piece_gfx | 0.039 | -| genblk1[18].red_piece_gfx | 0.038 | -| genblk1[19].red_piece_gfx | 0.038 | -| genblk1[1].red_piece_gfx | 0.029 | -| genblk1[20].red_piece_gfx | 0.050 | -| genblk1[2].red_piece_gfx | 0.031 | -| genblk1[3].red_piece_gfx | 0.027 | -| genblk1[4].red_piece_gfx | 0.029 | -| genblk1[5].red_piece_gfx | 0.026 | -| genblk1[6].red_piece_gfx | 0.017 | -| genblk1[7].red_piece_gfx | 0.016 | -| genblk1[8].red_piece_gfx | 0.015 | -| genblk1[9].red_piece_gfx | 0.015 | -| genblk2[0].yellow_piece_gfx | 0.017 | -| genblk2[10].yellow_piece_gfx | 0.025 | -| genblk2[11].yellow_piece_gfx | 0.022 | -| genblk2[12].yellow_piece_gfx | 0.023 | -| genblk2[13].yellow_piece_gfx | 0.024 | -| genblk2[14].yellow_piece_gfx | 0.032 | -| genblk2[15].yellow_piece_gfx | 0.031 | -| genblk2[16].yellow_piece_gfx | 0.035 | -| genblk2[17].yellow_piece_gfx | 0.033 | -| genblk2[18].yellow_piece_gfx | 0.032 | -| genblk2[19].yellow_piece_gfx | 0.033 | -| genblk2[1].yellow_piece_gfx | 0.023 | -| genblk2[20].yellow_piece_gfx | 0.040 | -| genblk2[2].yellow_piece_gfx | 0.024 | -| genblk2[3].yellow_piece_gfx | 0.023 | -| genblk2[4].yellow_piece_gfx | 0.024 | -| genblk2[5].yellow_piece_gfx | 0.024 | -| genblk2[6].yellow_piece_gfx | 0.024 | -| genblk2[7].yellow_piece_gfx | 0.025 | -| genblk2[8].yellow_piece_gfx | 0.024 | -| genblk2[9].yellow_piece_gfx | 0.023 | -| logo_gfx | 0.129 | -+--------------------------------+-----------+ ++---------------------------------------+-----------+ +| Name | Power (W) | ++---------------------------------------+-----------+ +| vga | 86.626 | +| bg_tile_gfx | 0.001 | +| board_gfx | 0.076 | +| core_design | 79.938 | +| corner_border_check_gfx | 0.063 | +| genblk1[0].red_piece_gfx | 0.005 | +| genblk1[10].red_piece_gfx | 0.008 | +| genblk1[11].red_piece_gfx | 0.003 | +| genblk1[12].red_piece_gfx | 0.007 | +| genblk1[13].red_piece_gfx | 0.004 | +| genblk1[14].red_piece_gfx | 0.004 | +| genblk1[15].red_piece_gfx | 0.006 | +| genblk1[16].red_piece_gfx | 0.004 | +| genblk1[17].red_piece_gfx | 0.003 | +| genblk1[18].red_piece_gfx | 0.003 | +| genblk1[19].red_piece_gfx | 0.003 | +| genblk1[1].red_piece_gfx | 0.006 | +| genblk1[20].red_piece_gfx | 0.008 | +| genblk1[2].red_piece_gfx | 0.003 | +| genblk1[3].red_piece_gfx | 0.007 | +| genblk1[4].red_piece_gfx | 0.003 | +| genblk1[5].red_piece_gfx | 0.004 | +| genblk1[6].red_piece_gfx | 0.004 | +| genblk1[7].red_piece_gfx | 0.003 | +| genblk1[8].red_piece_gfx | 0.006 | +| genblk1[9].red_piece_gfx | 0.005 | +| genblk2[0].yellow_piece_gfx | 0.003 | +| genblk2[10].yellow_piece_gfx | 0.003 | +| genblk2[11].yellow_piece_gfx | 0.003 | +| genblk2[12].yellow_piece_gfx | 0.009 | +| genblk2[13].yellow_piece_gfx | 0.004 | +| genblk2[14].yellow_piece_gfx | 0.004 | +| genblk2[15].yellow_piece_gfx | 0.004 | +| genblk2[16].yellow_piece_gfx | 0.004 | +| genblk2[17].yellow_piece_gfx | 0.011 | +| genblk2[18].yellow_piece_gfx | 0.008 | +| genblk2[19].yellow_piece_gfx | 0.005 | +| genblk2[1].yellow_piece_gfx | 0.007 | +| genblk2[20].yellow_piece_gfx | 0.004 | +| genblk2[2].yellow_piece_gfx | 0.007 | +| genblk2[3].yellow_piece_gfx | 0.008 | +| genblk2[4].yellow_piece_gfx | 0.004 | +| genblk2[5].yellow_piece_gfx | 0.005 | +| genblk2[6].yellow_piece_gfx | 0.008 | +| genblk2[7].yellow_piece_gfx | 0.004 | +| genblk2[8].yellow_piece_gfx | 0.006 | +| genblk2[9].yellow_piece_gfx | 0.008 | +| genblk3[0].yellow_win_highlight_gfx | 0.003 | +| genblk3[1].yellow_win_highlight_gfx | 0.002 | +| genblk3[2].yellow_win_highlight_gfx | 0.001 | +| genblk3[3].yellow_win_highlight_gfx | 0.002 | +| genblk3[4].yellow_win_highlight_gfx | 0.003 | +| genblk3[5].yellow_win_highlight_gfx | 0.003 | +| genblk3[6].yellow_win_highlight_gfx | 0.001 | +| genblk4[0].red_win_highlight_gfx | 0.002 | +| genblk4[1].red_win_highlight_gfx | 0.004 | +| genblk4[2].red_win_highlight_gfx | 0.003 | +| genblk4[3].red_win_highlight_gfx | 0.001 | +| genblk4[4].red_win_highlight_gfx | 0.002 | +| genblk4[5].red_win_highlight_gfx | 0.004 | +| genblk4[6].red_win_highlight_gfx | 0.003 | +| logo_gfx | 0.185 | +| red_indicator_gfx | 0.002 | +| red_wins_gfx | 0.033 | +| reds_turn_gfx | 0.012 | +| tie_game_gfx | 0.036 | +| yellow_indicator_gfx | 0.003 | +| yellow_wins_gfx | 0.048 | +| yellows_turn_gfx | 0.012 | ++---------------------------------------+-----------+ diff --git a/vga.runs/impl_1/vga_power_routed.rpx b/vga.runs/impl_1/vga_power_routed.rpx index a59cfd7..d724ce8 100644 Binary files a/vga.runs/impl_1/vga_power_routed.rpx and b/vga.runs/impl_1/vga_power_routed.rpx differ diff --git a/vga.runs/impl_1/vga_power_summary_routed.pb b/vga.runs/impl_1/vga_power_summary_routed.pb index 0af8f1a..4842a93 100644 Binary files a/vga.runs/impl_1/vga_power_summary_routed.pb and b/vga.runs/impl_1/vga_power_summary_routed.pb differ diff --git a/vga.runs/impl_1/vga_route_status.pb b/vga.runs/impl_1/vga_route_status.pb index 9466be1..7f648b4 100644 Binary files a/vga.runs/impl_1/vga_route_status.pb and b/vga.runs/impl_1/vga_route_status.pb differ diff --git a/vga.runs/impl_1/vga_route_status.rpt b/vga.runs/impl_1/vga_route_status.rpt index 023ee07..707b9df 100644 --- a/vga.runs/impl_1/vga_route_status.rpt +++ b/vga.runs/impl_1/vga_route_status.rpt @@ -1,11 +1,11 @@ Design Route Status : # nets : ------------------------------------------- : ----------- : - # of logical nets.......................... : 1725 : - # of nets not needing routing.......... : 390 : - # of internally routed nets........ : 390 : - # of routable nets..................... : 1335 : - # of fully routed nets............. : 1335 : + # of logical nets.......................... : 29869 : + # of nets not needing routing.......... : 8533 : + # of internally routed nets........ : 8533 : + # of routable nets..................... : 21336 : + # of fully routed nets............. : 21336 : # of nets with routing errors.......... : 0 : ------------------------------------------- : ----------- : diff --git a/vga.runs/impl_1/vga_routed.dcp b/vga.runs/impl_1/vga_routed.dcp index d80a015..ebdea35 100644 Binary files a/vga.runs/impl_1/vga_routed.dcp and b/vga.runs/impl_1/vga_routed.dcp differ diff --git a/vga.runs/impl_1/vga_timing_summary_routed.rpt b/vga.runs/impl_1/vga_timing_summary_routed.rpt index 51b31c5..283a4de 100644 --- a/vga.runs/impl_1/vga_timing_summary_routed.rpt +++ b/vga.runs/impl_1/vga_timing_summary_routed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 -| Date : Thu Apr 18 03:15:50 2024 +| Date : Mon Apr 22 21:25:16 2024 | Host : me running 64-bit major release (build 9200) | Command : report_timing_summary -max_paths 10 -report_unconstrained -file vga_timing_summary_routed.rpt -pb vga_timing_summary_routed.pb -rpx vga_timing_summary_routed.rpx -warn_on_violation | Design : vga @@ -41,9 +41,12 @@ Timing Summary Report | ------------------ ------------------------------------------------------------------------------------------------ -Rule Severity Description Violations ---------- ---------------- --------------------------- ---------- -TIMING-17 Critical Warning Non-clocked sequential cell 218 +Rule Severity Description Violations +--------- ---------------- ------------------------------ ---------- +TIMING-17 Critical Warning Non-clocked sequential cell 1000 +LUTAR-1 Warning LUT drives async reset alert 196 +TIMING-20 Warning Non-clocked latch 98 +LATCH-1 Advisory Existing latches in the design 1 Note: This report is based on the most recent report_methodology run and may not be up-to-date. Run report_methodology on the current design for the latest report. @@ -53,11 +56,11 @@ check_timing report Table of Contents ----------------- -1. checking no_clock (218) +1. checking no_clock (29555) 2. checking constant_clock (0) 3. checking pulse_width_clock (0) -4. checking unconstrained_internal_endpoints (314) -5. checking no_input_delay (0) +4. checking unconstrained_internal_endpoints (5770) +5. checking no_input_delay (5) 6. checking no_output_delay (14) 7. checking multiple_clock (0) 8. checking generated_clocks (0) @@ -66,13 +69,1499 @@ Table of Contents 11. checking partial_output_delay (0) 12. checking latch_loops (0) -1. checking no_clock (218) --------------------------- +1. checking no_clock (29555) +---------------------------- + There are 98 register/latch pins with no clock driven by root clock pin: btnCPUReset (HIGH) + There are 2 register/latch pins with no clock driven by root clock pin: sysClk (HIGH) + There are 39 register/latch pins with no clock driven by root clock pin: core_design/currRed_reg[0]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/currRed_reg[0]_rep/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/currRed_reg[0]_rep__0/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/currRed_reg[0]_rep__1/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/currRed_reg[1]_rep/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/currRed_reg[1]_rep__0/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/currRed_reg[1]_rep__1/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/currRed_reg[1]_rep__2/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/currRed_reg[2]_rep/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/currRed_reg[2]_rep__0/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/currRed_reg[2]_rep__1/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/currRed_reg[3]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/currRed_reg[4]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/currYellow_reg[0]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/currYellow_reg[0]_rep/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/currYellow_reg[0]_rep__0/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/currYellow_reg[0]_rep__1/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/currYellow_reg[1]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/currYellow_reg[1]_rep/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/currYellow_reg[1]_rep__0/Q (HIGH) + + There are 51 register/latch pins with no clock driven by root clock pin: core_design/currYellow_reg[2]_rep/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/currYellow_reg[2]_rep__0/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/currYellow_reg[2]_rep__1/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/currYellow_reg[3]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/currYellow_reg[4]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[0][0]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[0][1]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[0][2]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[0][3]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[0][4]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[0][5]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[0][6]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[0][7]_C/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/redPieceYOffset_reg[0][8]_C/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/redPieceYOffset_reg[0][8]_P/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/redPieceYOffset_reg[0][9]_C/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/redPieceYOffset_reg[0][9]_P/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[10][0]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[10][1]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[10][2]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[10][3]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[10][4]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[10][5]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[10][6]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[10][7]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[11][0]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[11][1]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[11][2]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[11][3]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[11][4]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[11][5]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[11][6]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[11][7]_C/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/redPieceYOffset_reg[11][9]_C/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/redPieceYOffset_reg[11][9]_P/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[12][0]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[12][1]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[12][2]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[12][3]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[12][4]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[12][5]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[12][6]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[12][7]_C/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/redPieceYOffset_reg[12][8]_C/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/redPieceYOffset_reg[12][8]_P/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/redPieceYOffset_reg[12][9]_C/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/redPieceYOffset_reg[12][9]_P/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[13][0]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[13][1]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[13][2]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[13][3]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[13][4]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[13][5]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[13][6]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[13][7]_C/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/redPieceYOffset_reg[13][9]_C/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/redPieceYOffset_reg[13][9]_P/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[14][0]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[14][1]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[14][2]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[14][3]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[14][4]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[14][5]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[14][6]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[14][7]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[15][0]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[15][1]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[15][2]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[15][3]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[15][4]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[15][5]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[15][6]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[15][7]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[16][0]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[16][1]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[16][2]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[16][3]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[16][4]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[16][5]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[16][6]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[16][7]_C/Q (HIGH) + + There are 18 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[16][8]_C/Q (HIGH) + + There are 17 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[16][8]_LDC/Q (HIGH) + + There are 18 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[16][8]_P/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/redPieceYOffset_reg[16][9]_C/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/redPieceYOffset_reg[16][9]_P/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[17][0]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[17][1]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[17][2]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[17][3]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[17][4]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[17][5]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[17][6]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[17][7]_C/Q (HIGH) + + There are 18 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[17][8]_C/Q (HIGH) + + There are 17 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[17][8]_LDC/Q (HIGH) + + There are 18 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[17][8]_P/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/redPieceYOffset_reg[17][9]_C/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/redPieceYOffset_reg[17][9]_P/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[18][0]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[18][1]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[18][2]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[18][3]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[18][4]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[18][5]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[18][6]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[18][7]_C/Q (HIGH) + + There are 17 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[18][8]_C/Q (HIGH) + + There are 17 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[18][8]_LDC/Q (HIGH) + + There are 17 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[18][8]_P/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[19][0]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[19][1]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[19][2]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[19][3]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[19][4]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[19][5]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[19][6]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[19][7]_C/Q (HIGH) + + There are 17 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[19][8]_C/Q (HIGH) + + There are 17 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[19][8]_LDC/Q (HIGH) + + There are 17 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[19][8]_P/Q (HIGH) + + There are 17 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[19][9]_C/Q (HIGH) + + There are 17 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[19][9]_LDC/Q (HIGH) + + There are 17 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[19][9]_P/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[1][0]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[1][1]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[1][2]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[1][3]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[1][4]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[1][5]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[1][6]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[1][7]_C/Q (HIGH) + + There are 37 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[1][8]_C/Q (HIGH) + + There are 18 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[1][9]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[20][0]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[20][1]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[20][2]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[20][3]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[20][4]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[20][5]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[20][6]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[20][7]_C/Q (HIGH) + + There are 18 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[20][8]_C/Q (HIGH) + + There are 17 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[20][8]_LDC/Q (HIGH) + + There are 18 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[20][8]_P/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/redPieceYOffset_reg[20][9]_C/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/redPieceYOffset_reg[20][9]_P/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[2][0]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[2][1]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[2][2]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[2][3]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[2][4]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[2][5]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[2][6]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[2][7]_C/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/redPieceYOffset_reg[2][8]_C/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/redPieceYOffset_reg[2][8]_P/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/redPieceYOffset_reg[2][9]_C/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/redPieceYOffset_reg[2][9]_P/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[3][0]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[3][1]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[3][2]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[3][3]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[3][4]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[3][5]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[3][6]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[3][7]_C/Q (HIGH) + + There are 37 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[3][8]_C/Q (HIGH) + + There are 37 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[3][8]_LDC/Q (HIGH) + + There are 37 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[3][8]_P/Q (HIGH) + + There are 18 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[3][9]_C/Q (HIGH) + + There are 18 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[3][9]_LDC/Q (HIGH) + + There are 18 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[3][9]_P/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[4][0]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[4][1]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[4][2]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[4][3]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[4][4]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[4][5]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[4][6]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[4][7]_C/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/redPieceYOffset_reg[4][8]_C/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/redPieceYOffset_reg[4][8]_P/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/redPieceYOffset_reg[4][9]_C/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/redPieceYOffset_reg[4][9]_P/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[5][0]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[5][1]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[5][2]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[5][3]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[5][4]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[5][5]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[5][6]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[5][7]_C/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/redPieceYOffset_reg[5][9]_C/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/redPieceYOffset_reg[5][9]_P/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[6][0]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[6][1]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[6][2]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[6][3]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[6][4]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[6][5]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[6][6]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[6][7]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[7][0]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[7][1]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[7][2]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[7][3]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[7][4]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[7][5]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[7][6]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[7][7]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[8][0]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[8][1]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[8][2]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[8][3]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[8][4]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[8][5]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[8][6]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[8][7]_C/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/redPieceYOffset_reg[8][8]_C/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/redPieceYOffset_reg[8][8]_P/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/redPieceYOffset_reg[8][9]_C/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/redPieceYOffset_reg[8][9]_P/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[9][0]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[9][1]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[9][2]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[9][3]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[9][4]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[9][5]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[9][6]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[9][7]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[9][9]_C/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[9][9]_LDC/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYOffset_reg[9][9]_P/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocitySign_reg[0]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocitySign_reg[10]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocitySign_reg[11]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocitySign_reg[12]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocitySign_reg[13]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocitySign_reg[14]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocitySign_reg[15]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocitySign_reg[16]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocitySign_reg[17]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocitySign_reg[18]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocitySign_reg[19]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocitySign_reg[1]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocitySign_reg[20]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocitySign_reg[2]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocitySign_reg[3]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocitySign_reg[4]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocitySign_reg[5]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocitySign_reg[6]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocitySign_reg[7]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocitySign_reg[8]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocitySign_reg[9]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[0][0]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[0][1]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[0][2]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[0][3]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[0][4]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[10][0]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[10][1]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[10][2]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[10][3]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[10][4]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[11][0]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[11][1]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[11][2]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[11][3]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[11][4]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[12][0]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[12][1]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[12][2]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[12][3]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[12][4]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[13][0]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[13][1]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[13][2]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[13][3]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[13][4]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[14][0]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[14][1]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[14][2]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[14][3]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[14][4]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[15][0]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[15][1]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[15][2]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[15][3]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[15][4]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[16][0]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[16][1]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[16][2]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[16][3]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[16][4]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[17][0]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[17][1]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[17][2]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[17][3]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[17][4]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[18][0]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[18][1]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[18][2]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[18][3]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[18][4]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[19][0]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[19][1]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[19][2]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[19][3]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[19][4]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[1][0]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[1][1]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[1][2]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[1][3]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[1][4]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[20][0]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[20][1]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[20][2]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[20][3]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[20][4]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[2][0]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[2][1]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[2][2]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[2][3]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[2][4]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[3][0]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[3][1]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[3][2]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[3][3]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[3][4]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[4][0]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[4][1]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[4][2]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[4][3]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[4][4]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[5][0]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[5][1]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[5][2]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[5][3]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[5][4]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[6][0]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[6][1]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[6][2]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[6][3]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[6][4]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[7][0]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[7][1]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[7][2]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[7][3]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[7][4]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[8][0]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[8][1]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[8][2]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[8][3]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[8][4]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[9][0]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[9][1]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[9][2]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[9][3]/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/redPieceYVelocity_reg[9][4]/Q (HIGH) + + There are 49 register/latch pins with no clock driven by root clock pin: core_design/row_reg[0]_rep__0/Q (HIGH) + + There are 8 register/latch pins with no clock driven by root clock pin: core_design/row_reg[1]_rep/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/row_reg[1]_rep__0/Q (HIGH) + + There are 44 register/latch pins with no clock driven by root clock pin: core_design/row_reg[1]_rep__1/Q (HIGH) + + There are 39 register/latch pins with no clock driven by root clock pin: core_design/row_reg[2]/Q (HIGH) + + There are 48 register/latch pins with no clock driven by root clock pin: core_design/row_reg[2]_rep/Q (HIGH) + + There are 41 register/latch pins with no clock driven by root clock pin: core_design/row_reg[2]_rep__0/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/state_reg[3]/Q (HIGH) + + There are 10 register/latch pins with no clock driven by root clock pin: core_design/state_reg[3]_rep__0/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/state_reg[3]_rep__1/Q (HIGH) + + There are 82 register/latch pins with no clock driven by root clock pin: core_design/state_reg[3]_rep__2/Q (HIGH) + + There are 13 register/latch pins with no clock driven by root clock pin: core_design/state_reg[4]_rep__0/Q (HIGH) + + There are 13 register/latch pins with no clock driven by root clock pin: core_design/state_reg[4]_rep__1/Q (HIGH) + + There are 2 register/latch pins with no clock driven by root clock pin: core_design/state_reg[4]_rep__3/Q (HIGH) + + There are 29 register/latch pins with no clock driven by root clock pin: core_design/state_reg[4]_rep__4/Q (HIGH) + + There are 9 register/latch pins with no clock driven by root clock pin: core_design/state_reg[4]_rep__5/Q (HIGH) + + There are 2 register/latch pins with no clock driven by root clock pin: core_design/state_reg[4]_rep__6/Q (HIGH) + + There are 85 register/latch pins with no clock driven by root clock pin: core_design/state_reg[4]_rep__7/Q (HIGH) + + There are 7 register/latch pins with no clock driven by root clock pin: core_design/state_reg[4]_rep__8/Q (HIGH) + + There are 49 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[0][0]_C/Q (HIGH) + + There are 48 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[0][1]_C/Q (HIGH) + + There are 47 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[0][2]_C/Q (HIGH) + + There are 44 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[0][4]_C/Q (HIGH) + + There are 40 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[0][6]_C/Q (HIGH) + + There are 38 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[0][7]_C/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[0][8]_C/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[0][8]_P/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[0][9]_C/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[0][9]_P/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[10][8]_C/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[10][8]_P/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[10][9]_C/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[10][9]_P/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[11][8]_C/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[11][8]_P/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[11][9]_C/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[11][9]_P/Q (HIGH) + + There are 44 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[12][4]_C/Q (HIGH) + + There are 43 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[12][5]_C/Q (HIGH) + + There are 40 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[12][6]_C/Q (HIGH) + + There are 38 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[12][7]_C/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[12][8]_C/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[12][8]_P/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[12][9]_C/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[12][9]_P/Q (HIGH) + + There are 44 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[13][4]_C/Q (HIGH) + + There are 43 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[13][5]_C/Q (HIGH) + + There are 40 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[13][6]_C/Q (HIGH) + + There are 38 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[13][7]_C/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[13][8]_C/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[13][8]_P/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[13][9]_C/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[13][9]_P/Q (HIGH) + + There are 44 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[14][4]_C/Q (HIGH) + + There are 43 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[14][5]_C/Q (HIGH) + + There are 40 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[14][6]_C/Q (HIGH) + + There are 38 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[14][7]_C/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[14][8]_C/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[14][8]_P/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[14][9]_C/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[14][9]_P/Q (HIGH) + + There are 44 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[15][4]_C/Q (HIGH) + + There are 43 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[15][5]_C/Q (HIGH) + + There are 40 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[15][6]_C/Q (HIGH) + + There are 38 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[15][7]_C/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[15][8]_C/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[15][8]_P/Q (HIGH) + + There are 49 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[16][0]_C/Q (HIGH) + + There are 48 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[16][1]_C/Q (HIGH) + + There are 47 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[16][2]_C/Q (HIGH) + + There are 46 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[16][3]_C/Q (HIGH) + + There are 44 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[16][4]_C/Q (HIGH) + + There are 43 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[16][5]_C/Q (HIGH) + + There are 40 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[16][6]_C/Q (HIGH) + + There are 38 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[16][7]_C/Q (HIGH) + + There are 18 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[16][8]_C/Q (HIGH) + + There are 17 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[16][9]_C/Q (HIGH) + + There are 49 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[17][0]_C/Q (HIGH) + + There are 48 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[17][1]_C/Q (HIGH) + + There are 47 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[17][2]_C/Q (HIGH) + + There are 46 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[17][3]_C/Q (HIGH) + + There are 44 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[17][4]_C/Q (HIGH) + + There are 43 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[17][5]_C/Q (HIGH) + + There are 40 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[17][6]_C/Q (HIGH) + + There are 38 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[17][7]_C/Q (HIGH) + + There are 19 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[17][8]_C/Q (HIGH) + + There are 18 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[17][8]_LDC/Q (HIGH) + + There are 19 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[17][8]_P/Q (HIGH) + + There are 17 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[17][9]_C/Q (HIGH) + + There are 17 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[17][9]_LDC/Q (HIGH) + + There are 17 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[17][9]_P/Q (HIGH) + + There are 49 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[18][0]_C/Q (HIGH) + + There are 48 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[18][1]_C/Q (HIGH) + + There are 47 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[18][2]_C/Q (HIGH) + + There are 46 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[18][3]_C/Q (HIGH) + + There are 44 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[18][4]_C/Q (HIGH) + + There are 43 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[18][5]_C/Q (HIGH) + + There are 40 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[18][6]_C/Q (HIGH) + + There are 38 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[18][7]_C/Q (HIGH) + + There are 19 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[18][8]_C/Q (HIGH) + + There are 18 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[18][8]_LDC/Q (HIGH) + + There are 19 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[18][8]_P/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[18][9]_C/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[18][9]_P/Q (HIGH) + + There are 49 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[19][0]_C/Q (HIGH) + + There are 48 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[19][1]_C/Q (HIGH) + + There are 47 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[19][2]_C/Q (HIGH) + + There are 46 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[19][3]_C/Q (HIGH) + + There are 44 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[19][4]_C/Q (HIGH) + + There are 43 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[19][5]_C/Q (HIGH) + + There are 40 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[19][6]_C/Q (HIGH) + + There are 38 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[19][7]_C/Q (HIGH) + + There are 19 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[19][8]_C/Q (HIGH) + + There are 18 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[19][8]_LDC/Q (HIGH) + + There are 19 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[19][8]_P/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[19][9]_C/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[19][9]_P/Q (HIGH) + + There are 49 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[1][0]_C/Q (HIGH) + + There are 48 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[1][1]_C/Q (HIGH) + + There are 47 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[1][2]_C/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[1][3]_C/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[1][3]_P/Q (HIGH) + + There are 44 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[1][4]_C/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[1][5]_C/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[1][5]_P/Q (HIGH) + + There are 40 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[1][6]_C/Q (HIGH) + + There are 38 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[1][7]_C/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[1][8]_C/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[1][8]_P/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[1][9]_C/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[1][9]_P/Q (HIGH) + + There are 49 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[20][0]_C/Q (HIGH) + + There are 48 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[20][1]_C/Q (HIGH) + + There are 47 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[20][2]_C/Q (HIGH) + + There are 46 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[20][3]_C/Q (HIGH) + + There are 44 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[20][4]_C/Q (HIGH) + + There are 43 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[20][5]_C/Q (HIGH) + + There are 40 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[20][6]_C/Q (HIGH) + + There are 38 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[20][7]_C/Q (HIGH) + + There are 19 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[20][8]_C/Q (HIGH) + + There are 18 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[20][8]_LDC/Q (HIGH) + + There are 19 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[20][8]_P/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[20][9]_C/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[20][9]_P/Q (HIGH) + + There are 49 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[2][0]_C/Q (HIGH) + + There are 48 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[2][1]_C/Q (HIGH) + + There are 47 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[2][2]_C/Q (HIGH) + + There are 44 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[2][4]_C/Q (HIGH) + + There are 40 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[2][6]_C/Q (HIGH) + + There are 38 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[2][7]_C/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[2][8]_C/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[2][8]_P/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[2][9]_C/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[2][9]_P/Q (HIGH) + + There are 49 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[3][0]_C/Q (HIGH) + + There are 48 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[3][1]_C/Q (HIGH) + + There are 47 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[3][2]_C/Q (HIGH) + + There are 44 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[3][4]_C/Q (HIGH) + + There are 40 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[3][6]_C/Q (HIGH) + + There are 38 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[3][7]_C/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[3][8]_C/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[3][8]_P/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[3][9]_C/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[3][9]_P/Q (HIGH) + + There are 49 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[4][0]_C/Q (HIGH) + + There are 48 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[4][1]_C/Q (HIGH) + + There are 47 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[4][2]_C/Q (HIGH) + + There are 46 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[4][3]_C/Q (HIGH) + + There are 44 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[4][4]_C/Q (HIGH) + + There are 43 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[4][5]_C/Q (HIGH) + + There are 40 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[4][6]_C/Q (HIGH) + + There are 38 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[4][7]_C/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[4][8]_C/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[4][8]_P/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[4][9]_C/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[4][9]_P/Q (HIGH) + + There are 49 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[5][0]_C/Q (HIGH) + + There are 48 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[5][1]_C/Q (HIGH) + + There are 47 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[5][2]_C/Q (HIGH) + + There are 46 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[5][3]_C/Q (HIGH) + + There are 44 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[5][4]_C/Q (HIGH) + + There are 43 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[5][5]_C/Q (HIGH) + + There are 40 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[5][6]_C/Q (HIGH) + + There are 38 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[5][7]_C/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[5][8]_C/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[5][8]_P/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[5][9]_C/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[5][9]_P/Q (HIGH) + + There are 49 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[6][0]_C/Q (HIGH) + + There are 48 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[6][1]_C/Q (HIGH) + + There are 47 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[6][2]_C/Q (HIGH) + + There are 46 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[6][3]_C/Q (HIGH) + + There are 44 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[6][4]_C/Q (HIGH) + + There are 43 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[6][5]_C/Q (HIGH) + + There are 40 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[6][6]_C/Q (HIGH) + + There are 38 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[6][7]_C/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[6][8]_C/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[6][8]_P/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[6][9]_C/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[6][9]_P/Q (HIGH) + + There are 50 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[7][0]_C/Q (HIGH) + + There are 50 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[7][0]_LDC/Q (HIGH) + + There are 50 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[7][0]_P/Q (HIGH) + + There are 49 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[7][1]_C/Q (HIGH) + + There are 49 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[7][1]_LDC/Q (HIGH) + + There are 49 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[7][1]_P/Q (HIGH) + + There are 48 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[7][2]_C/Q (HIGH) + + There are 48 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[7][2]_LDC/Q (HIGH) + + There are 48 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[7][2]_P/Q (HIGH) + + There are 46 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[7][3]_C/Q (HIGH) + + There are 46 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[7][3]_LDC/Q (HIGH) + + There are 46 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[7][3]_P/Q (HIGH) + + There are 44 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[7][4]_C/Q (HIGH) + + There are 44 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[7][4]_LDC/Q (HIGH) + + There are 44 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[7][4]_P/Q (HIGH) + + There are 43 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[7][5]_C/Q (HIGH) + + There are 43 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[7][5]_LDC/Q (HIGH) + + There are 43 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[7][5]_P/Q (HIGH) + + There are 40 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[7][6]_C/Q (HIGH) + + There are 40 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[7][6]_LDC/Q (HIGH) + + There are 40 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[7][6]_P/Q (HIGH) + + There are 38 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[7][7]_C/Q (HIGH) + + There are 38 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[7][7]_LDC/Q (HIGH) + + There are 38 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[7][7]_P/Q (HIGH) + + There are 37 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[7][8]_C/Q (HIGH) + + There are 37 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[7][8]_LDC/Q (HIGH) + + There are 37 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[7][8]_P/Q (HIGH) + + There are 18 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[7][9]_C/Q (HIGH) + + There are 18 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[7][9]_LDC/Q (HIGH) + + There are 18 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[7][9]_P/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[9][8]_C/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[9][8]_P/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[9][9]_C/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[9][9]_LDC/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYOffset_reg[9][9]_P/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocitySign_reg[0]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocitySign_reg[10]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocitySign_reg[11]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocitySign_reg[12]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocitySign_reg[13]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocitySign_reg[14]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocitySign_reg[15]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocitySign_reg[16]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocitySign_reg[17]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocitySign_reg[18]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocitySign_reg[19]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocitySign_reg[1]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocitySign_reg[20]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocitySign_reg[2]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocitySign_reg[3]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocitySign_reg[4]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocitySign_reg[5]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocitySign_reg[6]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocitySign_reg[7]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocitySign_reg[8]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocitySign_reg[9]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[0][0]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[0][1]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[0][2]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[0][3]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[0][4]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[10][0]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[10][1]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[10][2]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[10][3]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[10][4]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[11][0]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[11][1]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[11][2]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[11][3]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[11][4]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[12][0]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[12][1]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[12][2]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[12][3]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[12][4]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[13][0]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[13][1]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[13][2]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[13][3]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[13][4]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[14][0]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[14][1]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[14][2]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[14][3]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[14][4]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[15][0]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[15][1]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[15][2]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[15][3]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[15][4]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[16][0]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[16][1]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[16][2]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[16][3]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[16][4]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[17][0]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[17][1]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[17][2]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[17][3]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[17][4]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[18][0]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[18][1]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[18][2]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[18][3]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[18][4]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[19][0]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[19][1]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[19][2]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[19][3]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[19][4]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[1][0]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[1][1]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[1][2]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[1][3]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[1][4]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[20][0]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[20][1]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[20][2]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[20][3]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[20][4]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[2][0]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[2][1]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[2][2]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[2][3]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[2][4]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[3][0]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[3][1]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[3][2]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[3][3]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[3][4]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[4][0]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[4][1]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[4][2]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[4][3]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[4][4]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[5][0]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[5][1]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[5][2]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[5][3]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[5][4]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[6][0]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[6][1]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[6][2]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[6][3]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[6][4]/Q (HIGH) + + There are 57 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[7][0]/Q (HIGH) + + There are 57 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[7][1]/Q (HIGH) + + There are 57 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[7][2]/Q (HIGH) + + There are 57 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[7][3]/Q (HIGH) + + There are 57 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[7][4]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[8][0]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[8][1]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[8][2]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[8][3]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[8][4]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[9][0]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[9][1]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[9][2]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[9][3]/Q (HIGH) + + There are 56 register/latch pins with no clock driven by root clock pin: core_design/yellowPieceYVelocity_reg[9][4]/Q (HIGH) + + There are 1930 register/latch pins with no clock driven by root clock pin: frameClk_reg/Q (HIGH) + There are 30 register/latch pins with no clock driven by root clock pin: lineClk_reg/Q (HIGH) - There are 186 register/latch pins with no clock driven by root clock pin: pixClk_reg/Q (HIGH) + There are 248 register/latch pins with no clock driven by root clock pin: pixClk_reg/Q (HIGH) 2. checking constant_clock (0) @@ -85,16 +1574,16 @@ Table of Contents There are 0 register/latch pins which need pulse_width check -4. checking unconstrained_internal_endpoints (314) --------------------------------------------------- - There are 314 pins that are not constrained for maximum delay. (HIGH) +4. checking unconstrained_internal_endpoints (5770) +--------------------------------------------------- + There are 5770 pins that are not constrained for maximum delay. (HIGH) There are 0 pins that are not constrained for maximum delay due to constant clock. -5. checking no_input_delay (0) +5. checking no_input_delay (5) ------------------------------ - There are 0 input ports with no input delay specified. + There are 5 input ports with no input delay specified. (HIGH) There are 0 input ports with no input delay but user has a false path constraint. @@ -146,7 +1635,7 @@ Table of Contents WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- - inf 0.000 0 328 inf 0.000 0 328 NA NA NA NA + inf 0.000 0 5784 inf 0.000 0 5784 NA NA NA NA There are no user specified timing constraints. @@ -215,312 +1704,1221 @@ Path Group: (none) From Clock: To Clock: -Max Delay 328 Endpoints -Min Delay 328 Endpoints +Max Delay 5784 Endpoints +Min Delay 5784 Endpoints -------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack: inf - Source: pixY_reg[2]/C - (rising edge-triggered cell FDRE) - Destination: board_gfx/valid_reg/D + Source: core_design/board_reg[29][0]/C + (rising edge-triggered cell FDCE) + Destination: core_design/yellowWinXOffset_reg[5][4]/CE Path Group: (none) Path Type: Max at Slow Process Corner - Data Path Delay: 13.957ns (logic 2.380ns (17.052%) route 11.577ns (82.948%)) - Logic Levels: 9 (CARRY4=2 FDRE=1 LUT1=1 LUT5=3 LUT6=2) + Data Path Delay: 64.084ns (logic 10.806ns (16.862%) route 53.278ns (83.138%)) + Logic Levels: 50 (CARRY4=6 FDCE=1 LUT1=1 LUT2=2 LUT3=2 LUT4=5 LUT5=8 LUT6=23 MUXF7=2) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - SLICE_X73Y152 FDRE 0.000 0.000 r pixY_reg[2]/C - SLICE_X73Y152 FDRE (Prop_fdre_C_Q) 0.419 0.419 f pixY_reg[2]/Q - net (fo=186, routed) 5.949 6.368 board_gfx/Q[0] - SLICE_X85Y145 LUT1 (Prop_lut1_I0_O) 0.296 6.664 r board_gfx/paletteIndex[3]_i_9/O - net (fo=1, routed) 0.000 6.664 board_gfx/paletteIndex[3]_i_9_n_0 - SLICE_X85Y145 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 7.196 r board_gfx/paletteIndex_reg[3]_i_4__5/CO[3] - net (fo=1, routed) 0.000 7.196 board_gfx/paletteIndex_reg[3]_i_4__5_n_0 - SLICE_X85Y146 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 7.530 r board_gfx/valid_reg_i_3__20/O[1] - net (fo=10, routed) 1.061 8.591 board_gfx/y0173_out[5] - SLICE_X86Y144 LUT6 (Prop_lut6_I3_O) 0.303 8.894 r board_gfx/paletteIndex[3]_i_12__0/O - net (fo=1, routed) 0.798 9.692 board_gfx/paletteIndex[3]_i_12__0_n_0 - SLICE_X86Y144 LUT5 (Prop_lut5_I0_O) 0.124 9.816 r board_gfx/paletteIndex[3]_i_4__11/O - net (fo=8, routed) 1.866 11.682 board_gfx/paletteIndex[3]_i_4__11_n_0 - SLICE_X80Y150 LUT5 (Prop_lut5_I1_O) 0.124 11.806 f board_gfx/paletteIndex[3]_i_5__7/O - net (fo=1, routed) 0.778 12.585 board_gfx/paletteIndex[3]_i_5__7_n_0 - SLICE_X81Y149 LUT6 (Prop_lut6_I3_O) 0.124 12.709 f board_gfx/paletteIndex[3]_i_1__21/O - net (fo=2, routed) 1.125 13.833 board_gfx/paletteIndex[3]_i_1__21_n_0 - SLICE_X80Y149 LUT5 (Prop_lut5_I3_O) 0.124 13.957 r board_gfx/valid_i_1__21/O - net (fo=1, routed) 0.000 13.957 board_gfx/valid_i_1__21_n_0 - SLICE_X80Y149 FDRE r board_gfx/valid_reg/D + SLICE_X12Y150 FDCE 0.000 0.000 r core_design/board_reg[29][0]/C + SLICE_X12Y150 FDCE (Prop_fdce_C_Q) 0.518 0.518 r core_design/board_reg[29][0]/Q + net (fo=171, routed) 6.704 7.222 core_design/board_reg_n_0_[29][0] + SLICE_X47Y111 LUT2 (Prop_lut2_I0_O) 0.124 7.346 r core_design/showYellowWinIndicator[4]_i_200/O + net (fo=49, routed) 1.983 9.329 core_design/checkWinsYellow.(null)[2].(null)[5].c[0] + SLICE_X32Y109 LUT5 (Prop_lut5_I4_O) 0.124 9.453 r core_design/yellowWinXOffset[0][4]_i_874/O + net (fo=1, routed) 0.000 9.453 core_design/yellowWinXOffset[0][4]_i_874_n_0 + SLICE_X32Y109 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 10.003 r core_design/yellowWinXOffset_reg[0][4]_i_778/CO[3] + net (fo=1, routed) 0.000 10.003 core_design/yellowWinXOffset_reg[0][4]_i_778_n_0 + SLICE_X32Y110 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 10.225 r core_design/yellowWinXOffset_reg[0][4]_i_779/O[0] + net (fo=3, routed) 0.810 11.035 core_design/yellowWinXOffset_reg[0][4]_i_779_n_7 + SLICE_X33Y109 LUT4 (Prop_lut4_I1_O) 0.329 11.364 r core_design/yellowWinXOffset[0][4]_i_869/O + net (fo=4, routed) 1.007 12.370 core_design/yellowWinXOffset[0][4]_i_869_n_0 + SLICE_X33Y110 LUT3 (Prop_lut3_I1_O) 0.327 12.697 f core_design/yellowWinXOffset[0][4]_i_777/O + net (fo=1, routed) 0.000 12.697 core_design/yellowWinXOffset[0][4]_i_777_n_0 + SLICE_X33Y110 MUXF7 (Prop_muxf7_I1_O) 0.217 12.914 f core_design/yellowWinXOffset_reg[0][4]_i_625/O + net (fo=1, routed) 0.436 13.350 core_design/yellowWinXOffset_reg[0][4]_i_625_n_0 + SLICE_X33Y110 LUT5 (Prop_lut5_I2_O) 0.299 13.649 r core_design/yellowWinXOffset[0][4]_i_489/O + net (fo=9, routed) 0.806 14.455 core_design/yellowWinXOffset[0][4]_i_489_n_0 + SLICE_X38Y112 LUT6 (Prop_lut6_I5_O) 0.124 14.579 f core_design/yellowWinXOffset[0][4]_i_935/O + net (fo=4, routed) 0.632 15.211 core_design/yellowWinXOffset[0][4]_i_935_n_0 + SLICE_X33Y111 LUT1 (Prop_lut1_I0_O) 0.124 15.335 r core_design/yellowWinXOffset[0][4]_i_933/O + net (fo=1, routed) 0.000 15.335 core_design/yellowWinXOffset[0][4]_i_933_n_0 + SLICE_X33Y111 CARRY4 (Prop_carry4_S[1]_O[2]) + 0.580 15.915 r core_design/yellowWinXOffset_reg[0][4]_i_876/O[2] + net (fo=2, routed) 0.817 16.732 core_design/checkWinsYellow.(null)[0].(null)[5].count5[2] + SLICE_X32Y111 LUT5 (Prop_lut5_I4_O) 0.302 17.034 r core_design/yellowWinXOffset[0][4]_i_877/O + net (fo=1, routed) 0.000 17.034 core_design/yellowWinXOffset[0][4]_i_877_n_0 + SLICE_X32Y111 CARRY4 (Prop_carry4_S[2]_CO[3]) + 0.398 17.432 r core_design/yellowWinXOffset_reg[0][4]_i_780/CO[3] + net (fo=1, routed) 0.000 17.432 core_design/yellowWinXOffset_reg[0][4]_i_780_n_0 + SLICE_X32Y112 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 17.766 f core_design/yellowWinXOffset_reg[0][4]_i_781/O[1] + net (fo=4, routed) 0.675 18.441 core_design/yellowWinXOffset_reg[0][4]_i_781_n_6 + SLICE_X31Y111 LUT6 (Prop_lut6_I0_O) 0.303 18.744 r core_design/yellowWinXOffset[0][4]_i_785/O + net (fo=8, routed) 1.306 20.050 core_design/yellowWinXOffset[0][4]_i_785_n_0 + SLICE_X34Y114 LUT5 (Prop_lut5_I2_O) 0.124 20.174 f core_design/yellowWinXOffset[0][4]_i_882/O + net (fo=1, routed) 0.165 20.339 core_design/yellowWinXOffset[0][4]_i_882_n_0 + SLICE_X34Y114 LUT6 (Prop_lut6_I0_O) 0.124 20.463 r core_design/yellowWinXOffset[0][4]_i_782/O + net (fo=1, routed) 1.040 21.503 core_design/yellowWinXOffset[0][4]_i_782_n_0 + SLICE_X33Y113 LUT6 (Prop_lut6_I0_O) 0.124 21.627 r core_design/yellowWinXOffset[0][4]_i_628/O + net (fo=1, routed) 0.000 21.627 core_design/yellowWinXOffset[0][4]_i_628_n_0 + SLICE_X33Y113 MUXF7 (Prop_muxf7_I0_O) 0.212 21.839 r core_design/yellowWinXOffset_reg[0][4]_i_490/O + net (fo=3, routed) 1.185 23.024 core_design/yellowWinXOffset_reg[0][4]_i_490_n_0 + SLICE_X38Y112 LUT6 (Prop_lut6_I4_O) 0.299 23.323 r core_design/yellowWinXOffset[0][4]_i_361/O + net (fo=1, routed) 0.517 23.840 core_design/yellowWinXOffset[0][4]_i_361_n_0 + SLICE_X40Y112 CARRY4 (Prop_carry4_DI[0]_CO[1]) + 0.465 24.305 r core_design/yellowWinXOffset_reg[0][4]_i_249/CO[1] + net (fo=1, routed) 0.816 25.121 core_design/yellowWinXOffset_reg[0][4]_i_249_n_2 + SLICE_X41Y113 LUT6 (Prop_lut6_I4_O) 0.329 25.450 r core_design/yellowWinXOffset[0][4]_i_150/O + net (fo=15, routed) 2.286 27.736 core_design/showYellowWinIndicator1102_out + SLICE_X34Y90 LUT6 (Prop_lut6_I0_O) 0.124 27.860 r core_design/yellowWinXOffset[0][4]_i_138/O + net (fo=49, routed) 1.812 29.672 core_design/yellowWinXOffset[0][4]_i_138_n_0 + SLICE_X36Y87 LUT5 (Prop_lut5_I2_O) 0.150 29.822 r core_design/yellowWinXOffset[0][5]_i_123/O + net (fo=16, routed) 1.018 30.840 core_design/yellowWinXOffset[0][5]_i_123_n_0 + SLICE_X34Y89 LUT5 (Prop_lut5_I4_O) 0.326 31.166 f core_design/yellowWinXOffset[0][5]_i_125/O + net (fo=4, routed) 0.746 31.911 core_design/yellowWinXOffset[0][5]_i_125_n_0 + SLICE_X35Y88 LUT6 (Prop_lut6_I4_O) 0.124 32.035 r core_design/yellowWinXOffset[0][5]_i_57/O + net (fo=33, routed) 1.169 33.204 core_design/yellowWinXOffset[0][5]_i_57_n_0 + SLICE_X38Y88 LUT6 (Prop_lut6_I2_O) 0.124 33.328 r core_design/showYellowWinIndicator[1]_i_25/O + net (fo=39, routed) 2.027 35.355 core_design/showYellowWinIndicator[1]_i_25_n_0 + SLICE_X44Y96 LUT6 (Prop_lut6_I5_O) 0.124 35.479 r core_design/showYellowWinIndicator[1]_i_14/O + net (fo=25, routed) 0.868 36.347 core_design/showYellowWinIndicator[1]_i_14_n_0 + SLICE_X44Y95 LUT6 (Prop_lut6_I0_O) 0.124 36.471 r core_design/showYellowWinIndicator[6]_i_93/O + net (fo=17, routed) 1.048 37.519 core_design/showYellowWinIndicator[6]_i_93_n_0 + SLICE_X48Y90 LUT6 (Prop_lut6_I0_O) 0.124 37.643 r core_design/showYellowWinIndicator[6]_i_39/O + net (fo=21, routed) 1.768 39.412 core_design/showYellowWinIndicator[6]_i_39_n_0 + SLICE_X48Y97 LUT6 (Prop_lut6_I0_O) 0.124 39.536 f core_design/showYellowWinIndicator[6]_i_17/O + net (fo=20, routed) 1.453 40.988 core_design/showYellowWinIndicator[6]_i_17_n_0 + SLICE_X51Y88 LUT4 (Prop_lut4_I3_O) 0.118 41.106 r core_design/yellowWinXOffset[1][6]_i_255/O + net (fo=5, routed) 0.822 41.929 core_design/yellowWinXOffset[1][6]_i_255_n_0 + SLICE_X52Y87 LUT2 (Prop_lut2_I1_O) 0.326 42.255 r core_design/yellowWinXOffset[1][6]_i_201/O + net (fo=16, routed) 1.340 43.595 core_design/yellowWinXOffset[1][6]_i_201_n_0 + SLICE_X57Y84 LUT6 (Prop_lut6_I2_O) 0.124 43.719 r core_design/yellowWinXOffset[0][5]_i_90/O + net (fo=8, routed) 1.736 45.454 core_design/yellowWinXOffset[0][5]_i_90_n_0 + SLICE_X57Y88 LUT4 (Prop_lut4_I3_O) 0.124 45.578 r core_design/yellowWinXOffset[0][6]_i_239/O + net (fo=5, routed) 1.473 47.052 core_design/yellowWinXOffset[0][6]_i_239_n_0 + SLICE_X61Y86 LUT6 (Prop_lut6_I3_O) 0.124 47.176 r core_design/yellowWinXOffset[4][4]_i_52/O + net (fo=3, routed) 1.190 48.366 core_design/yellowWinXOffset[4][4]_i_52_n_0 + SLICE_X62Y88 LUT6 (Prop_lut6_I0_O) 0.124 48.490 r core_design/yellowWinXOffset[6][5]_i_54/O + net (fo=3, routed) 0.671 49.161 core_design/yellowWinXOffset[6][5]_i_54_n_0 + SLICE_X64Y87 LUT5 (Prop_lut5_I2_O) 0.124 49.285 f core_design/yellowWinXOffset[6][5]_i_25/O + net (fo=30, routed) 1.171 50.456 core_design/yellowWinXOffset[6][5]_i_25_n_0 + SLICE_X66Y86 LUT6 (Prop_lut6_I5_O) 0.124 50.580 r core_design/yellowWinXOffset[4][4]_i_21/O + net (fo=8, routed) 1.044 51.624 core_design/yellowWinXOffset[4][4]_i_21_n_0 + SLICE_X68Y90 LUT5 (Prop_lut5_I0_O) 0.124 51.748 f core_design/yellowWinXOffset[1][6]_i_81/O + net (fo=12, routed) 1.020 52.768 core_design/yellowWinXOffset[1][6]_i_81_n_0 + SLICE_X69Y94 LUT3 (Prop_lut3_I0_O) 0.152 52.920 r core_design/yellowWinXOffset[6][5]_i_64/O + net (fo=3, routed) 0.440 53.360 core_design/yellowWinXOffset[6][5]_i_64_n_0 + SLICE_X70Y94 LUT6 (Prop_lut6_I5_O) 0.326 53.686 r core_design/yellowWinYOffset[4][6]_i_57/O + net (fo=14, routed) 1.810 55.496 core_design/yellowWinYOffset[4][6]_i_57_n_0 + SLICE_X72Y98 LUT6 (Prop_lut6_I4_O) 0.124 55.620 r core_design/yellowWinXOffset[3][2]_i_7/O + net (fo=2, routed) 1.191 56.811 core_design/yellowWinXOffset[3][2]_i_7_n_0 + SLICE_X72Y100 LUT6 (Prop_lut6_I1_O) 0.124 56.935 f core_design/yellowWinXOffset[3][2]_i_5/O + net (fo=24, routed) 1.804 58.739 core_design/yellowWinXOffset[3][2]_i_5_n_0 + SLICE_X66Y99 LUT4 (Prop_lut4_I2_O) 0.152 58.891 f core_design/yellowWinXOffset[3][6]_i_16/O + net (fo=2, routed) 0.615 59.506 core_design/yellowWinXOffset[3][6]_i_16_n_0 + SLICE_X70Y101 LUT6 (Prop_lut6_I5_O) 0.348 59.854 f core_design/yellowWinXOffset[6][6]_i_6/O + net (fo=11, routed) 1.304 61.157 core_design/yellowWinXOffset[6][6]_i_6_n_0 + SLICE_X62Y100 LUT6 (Prop_lut6_I0_O) 0.124 61.281 f core_design/yellowWinXOffset[5][6]_i_10/O + net (fo=8, routed) 0.956 62.237 core_design/yellowWinXOffset[5][6]_i_10_n_0 + SLICE_X63Y100 LUT6 (Prop_lut6_I5_O) 0.124 62.361 r core_design/yellowWinXOffset[5][6]_i_3/O + net (fo=1, routed) 0.951 63.313 core_design/yellowWinXOffset[5][6]_i_3_n_0 + SLICE_X63Y104 LUT4 (Prop_lut4_I2_O) 0.124 63.437 r core_design/yellowWinXOffset[5][6]_i_1/O + net (fo=11, routed) 0.647 64.084 core_design/yellowWinXOffset[5][6]_i_1_n_0 + SLICE_X66Y104 FDCE r core_design/yellowWinXOffset_reg[5][4]/CE ------------------------------------------------------------------- ------------------- Slack: inf - Source: pixY_reg[2]/C - (rising edge-triggered cell FDRE) - Destination: board_gfx/paletteIndex_reg[3]/D + Source: core_design/board_reg[29][0]/C + (rising edge-triggered cell FDCE) + Destination: core_design/yellowWinXOffset_reg[5][5]/CE Path Group: (none) Path Type: Max at Slow Process Corner - Data Path Delay: 13.339ns (logic 2.256ns (16.913%) route 11.083ns (83.087%)) - Logic Levels: 8 (CARRY4=2 FDRE=1 LUT1=1 LUT5=2 LUT6=2) + Data Path Delay: 64.084ns (logic 10.806ns (16.862%) route 53.278ns (83.138%)) + Logic Levels: 50 (CARRY4=6 FDCE=1 LUT1=1 LUT2=2 LUT3=2 LUT4=5 LUT5=8 LUT6=23 MUXF7=2) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - SLICE_X73Y152 FDRE 0.000 0.000 r pixY_reg[2]/C - SLICE_X73Y152 FDRE (Prop_fdre_C_Q) 0.419 0.419 f pixY_reg[2]/Q - net (fo=186, routed) 5.949 6.368 board_gfx/Q[0] - SLICE_X85Y145 LUT1 (Prop_lut1_I0_O) 0.296 6.664 r board_gfx/paletteIndex[3]_i_9/O - net (fo=1, routed) 0.000 6.664 board_gfx/paletteIndex[3]_i_9_n_0 - SLICE_X85Y145 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 7.196 r board_gfx/paletteIndex_reg[3]_i_4__5/CO[3] - net (fo=1, routed) 0.000 7.196 board_gfx/paletteIndex_reg[3]_i_4__5_n_0 - SLICE_X85Y146 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 7.530 r board_gfx/valid_reg_i_3__20/O[1] - net (fo=10, routed) 1.061 8.591 board_gfx/y0173_out[5] - SLICE_X86Y144 LUT6 (Prop_lut6_I3_O) 0.303 8.894 r board_gfx/paletteIndex[3]_i_12__0/O - net (fo=1, routed) 0.798 9.692 board_gfx/paletteIndex[3]_i_12__0_n_0 - SLICE_X86Y144 LUT5 (Prop_lut5_I0_O) 0.124 9.816 r board_gfx/paletteIndex[3]_i_4__11/O - net (fo=8, routed) 1.866 11.682 board_gfx/paletteIndex[3]_i_4__11_n_0 - SLICE_X80Y150 LUT5 (Prop_lut5_I1_O) 0.124 11.806 r board_gfx/paletteIndex[3]_i_5__7/O - net (fo=1, routed) 0.778 12.585 board_gfx/paletteIndex[3]_i_5__7_n_0 - SLICE_X81Y149 LUT6 (Prop_lut6_I3_O) 0.124 12.709 r board_gfx/paletteIndex[3]_i_1__21/O - net (fo=2, routed) 0.630 13.339 board_gfx/paletteIndex[3]_i_1__21_n_0 - SLICE_X79Y151 FDRE r board_gfx/paletteIndex_reg[3]/D + SLICE_X12Y150 FDCE 0.000 0.000 r core_design/board_reg[29][0]/C + SLICE_X12Y150 FDCE (Prop_fdce_C_Q) 0.518 0.518 r core_design/board_reg[29][0]/Q + net (fo=171, routed) 6.704 7.222 core_design/board_reg_n_0_[29][0] + SLICE_X47Y111 LUT2 (Prop_lut2_I0_O) 0.124 7.346 r core_design/showYellowWinIndicator[4]_i_200/O + net (fo=49, routed) 1.983 9.329 core_design/checkWinsYellow.(null)[2].(null)[5].c[0] + SLICE_X32Y109 LUT5 (Prop_lut5_I4_O) 0.124 9.453 r core_design/yellowWinXOffset[0][4]_i_874/O + net (fo=1, routed) 0.000 9.453 core_design/yellowWinXOffset[0][4]_i_874_n_0 + SLICE_X32Y109 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 10.003 r core_design/yellowWinXOffset_reg[0][4]_i_778/CO[3] + net (fo=1, routed) 0.000 10.003 core_design/yellowWinXOffset_reg[0][4]_i_778_n_0 + SLICE_X32Y110 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 10.225 r core_design/yellowWinXOffset_reg[0][4]_i_779/O[0] + net (fo=3, routed) 0.810 11.035 core_design/yellowWinXOffset_reg[0][4]_i_779_n_7 + SLICE_X33Y109 LUT4 (Prop_lut4_I1_O) 0.329 11.364 r core_design/yellowWinXOffset[0][4]_i_869/O + net (fo=4, routed) 1.007 12.370 core_design/yellowWinXOffset[0][4]_i_869_n_0 + SLICE_X33Y110 LUT3 (Prop_lut3_I1_O) 0.327 12.697 f core_design/yellowWinXOffset[0][4]_i_777/O + net (fo=1, routed) 0.000 12.697 core_design/yellowWinXOffset[0][4]_i_777_n_0 + SLICE_X33Y110 MUXF7 (Prop_muxf7_I1_O) 0.217 12.914 f core_design/yellowWinXOffset_reg[0][4]_i_625/O + net (fo=1, routed) 0.436 13.350 core_design/yellowWinXOffset_reg[0][4]_i_625_n_0 + SLICE_X33Y110 LUT5 (Prop_lut5_I2_O) 0.299 13.649 r core_design/yellowWinXOffset[0][4]_i_489/O + net (fo=9, routed) 0.806 14.455 core_design/yellowWinXOffset[0][4]_i_489_n_0 + SLICE_X38Y112 LUT6 (Prop_lut6_I5_O) 0.124 14.579 f core_design/yellowWinXOffset[0][4]_i_935/O + net (fo=4, routed) 0.632 15.211 core_design/yellowWinXOffset[0][4]_i_935_n_0 + SLICE_X33Y111 LUT1 (Prop_lut1_I0_O) 0.124 15.335 r core_design/yellowWinXOffset[0][4]_i_933/O + net (fo=1, routed) 0.000 15.335 core_design/yellowWinXOffset[0][4]_i_933_n_0 + SLICE_X33Y111 CARRY4 (Prop_carry4_S[1]_O[2]) + 0.580 15.915 r core_design/yellowWinXOffset_reg[0][4]_i_876/O[2] + net (fo=2, routed) 0.817 16.732 core_design/checkWinsYellow.(null)[0].(null)[5].count5[2] + SLICE_X32Y111 LUT5 (Prop_lut5_I4_O) 0.302 17.034 r core_design/yellowWinXOffset[0][4]_i_877/O + net (fo=1, routed) 0.000 17.034 core_design/yellowWinXOffset[0][4]_i_877_n_0 + SLICE_X32Y111 CARRY4 (Prop_carry4_S[2]_CO[3]) + 0.398 17.432 r core_design/yellowWinXOffset_reg[0][4]_i_780/CO[3] + net (fo=1, routed) 0.000 17.432 core_design/yellowWinXOffset_reg[0][4]_i_780_n_0 + SLICE_X32Y112 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 17.766 f core_design/yellowWinXOffset_reg[0][4]_i_781/O[1] + net (fo=4, routed) 0.675 18.441 core_design/yellowWinXOffset_reg[0][4]_i_781_n_6 + SLICE_X31Y111 LUT6 (Prop_lut6_I0_O) 0.303 18.744 r core_design/yellowWinXOffset[0][4]_i_785/O + net (fo=8, routed) 1.306 20.050 core_design/yellowWinXOffset[0][4]_i_785_n_0 + SLICE_X34Y114 LUT5 (Prop_lut5_I2_O) 0.124 20.174 f core_design/yellowWinXOffset[0][4]_i_882/O + net (fo=1, routed) 0.165 20.339 core_design/yellowWinXOffset[0][4]_i_882_n_0 + SLICE_X34Y114 LUT6 (Prop_lut6_I0_O) 0.124 20.463 r core_design/yellowWinXOffset[0][4]_i_782/O + net (fo=1, routed) 1.040 21.503 core_design/yellowWinXOffset[0][4]_i_782_n_0 + SLICE_X33Y113 LUT6 (Prop_lut6_I0_O) 0.124 21.627 r core_design/yellowWinXOffset[0][4]_i_628/O + net (fo=1, routed) 0.000 21.627 core_design/yellowWinXOffset[0][4]_i_628_n_0 + SLICE_X33Y113 MUXF7 (Prop_muxf7_I0_O) 0.212 21.839 r core_design/yellowWinXOffset_reg[0][4]_i_490/O + net (fo=3, routed) 1.185 23.024 core_design/yellowWinXOffset_reg[0][4]_i_490_n_0 + SLICE_X38Y112 LUT6 (Prop_lut6_I4_O) 0.299 23.323 r core_design/yellowWinXOffset[0][4]_i_361/O + net (fo=1, routed) 0.517 23.840 core_design/yellowWinXOffset[0][4]_i_361_n_0 + SLICE_X40Y112 CARRY4 (Prop_carry4_DI[0]_CO[1]) + 0.465 24.305 r core_design/yellowWinXOffset_reg[0][4]_i_249/CO[1] + net (fo=1, routed) 0.816 25.121 core_design/yellowWinXOffset_reg[0][4]_i_249_n_2 + SLICE_X41Y113 LUT6 (Prop_lut6_I4_O) 0.329 25.450 r core_design/yellowWinXOffset[0][4]_i_150/O + net (fo=15, routed) 2.286 27.736 core_design/showYellowWinIndicator1102_out + SLICE_X34Y90 LUT6 (Prop_lut6_I0_O) 0.124 27.860 r core_design/yellowWinXOffset[0][4]_i_138/O + net (fo=49, routed) 1.812 29.672 core_design/yellowWinXOffset[0][4]_i_138_n_0 + SLICE_X36Y87 LUT5 (Prop_lut5_I2_O) 0.150 29.822 r core_design/yellowWinXOffset[0][5]_i_123/O + net (fo=16, routed) 1.018 30.840 core_design/yellowWinXOffset[0][5]_i_123_n_0 + SLICE_X34Y89 LUT5 (Prop_lut5_I4_O) 0.326 31.166 f core_design/yellowWinXOffset[0][5]_i_125/O + net (fo=4, routed) 0.746 31.911 core_design/yellowWinXOffset[0][5]_i_125_n_0 + SLICE_X35Y88 LUT6 (Prop_lut6_I4_O) 0.124 32.035 r core_design/yellowWinXOffset[0][5]_i_57/O + net (fo=33, routed) 1.169 33.204 core_design/yellowWinXOffset[0][5]_i_57_n_0 + SLICE_X38Y88 LUT6 (Prop_lut6_I2_O) 0.124 33.328 r core_design/showYellowWinIndicator[1]_i_25/O + net (fo=39, routed) 2.027 35.355 core_design/showYellowWinIndicator[1]_i_25_n_0 + SLICE_X44Y96 LUT6 (Prop_lut6_I5_O) 0.124 35.479 r core_design/showYellowWinIndicator[1]_i_14/O + net (fo=25, routed) 0.868 36.347 core_design/showYellowWinIndicator[1]_i_14_n_0 + SLICE_X44Y95 LUT6 (Prop_lut6_I0_O) 0.124 36.471 r core_design/showYellowWinIndicator[6]_i_93/O + net (fo=17, routed) 1.048 37.519 core_design/showYellowWinIndicator[6]_i_93_n_0 + SLICE_X48Y90 LUT6 (Prop_lut6_I0_O) 0.124 37.643 r core_design/showYellowWinIndicator[6]_i_39/O + net (fo=21, routed) 1.768 39.412 core_design/showYellowWinIndicator[6]_i_39_n_0 + SLICE_X48Y97 LUT6 (Prop_lut6_I0_O) 0.124 39.536 f core_design/showYellowWinIndicator[6]_i_17/O + net (fo=20, routed) 1.453 40.988 core_design/showYellowWinIndicator[6]_i_17_n_0 + SLICE_X51Y88 LUT4 (Prop_lut4_I3_O) 0.118 41.106 r core_design/yellowWinXOffset[1][6]_i_255/O + net (fo=5, routed) 0.822 41.929 core_design/yellowWinXOffset[1][6]_i_255_n_0 + SLICE_X52Y87 LUT2 (Prop_lut2_I1_O) 0.326 42.255 r core_design/yellowWinXOffset[1][6]_i_201/O + net (fo=16, routed) 1.340 43.595 core_design/yellowWinXOffset[1][6]_i_201_n_0 + SLICE_X57Y84 LUT6 (Prop_lut6_I2_O) 0.124 43.719 r core_design/yellowWinXOffset[0][5]_i_90/O + net (fo=8, routed) 1.736 45.454 core_design/yellowWinXOffset[0][5]_i_90_n_0 + SLICE_X57Y88 LUT4 (Prop_lut4_I3_O) 0.124 45.578 r core_design/yellowWinXOffset[0][6]_i_239/O + net (fo=5, routed) 1.473 47.052 core_design/yellowWinXOffset[0][6]_i_239_n_0 + SLICE_X61Y86 LUT6 (Prop_lut6_I3_O) 0.124 47.176 r core_design/yellowWinXOffset[4][4]_i_52/O + net (fo=3, routed) 1.190 48.366 core_design/yellowWinXOffset[4][4]_i_52_n_0 + SLICE_X62Y88 LUT6 (Prop_lut6_I0_O) 0.124 48.490 r core_design/yellowWinXOffset[6][5]_i_54/O + net (fo=3, routed) 0.671 49.161 core_design/yellowWinXOffset[6][5]_i_54_n_0 + SLICE_X64Y87 LUT5 (Prop_lut5_I2_O) 0.124 49.285 f core_design/yellowWinXOffset[6][5]_i_25/O + net (fo=30, routed) 1.171 50.456 core_design/yellowWinXOffset[6][5]_i_25_n_0 + SLICE_X66Y86 LUT6 (Prop_lut6_I5_O) 0.124 50.580 r core_design/yellowWinXOffset[4][4]_i_21/O + net (fo=8, routed) 1.044 51.624 core_design/yellowWinXOffset[4][4]_i_21_n_0 + SLICE_X68Y90 LUT5 (Prop_lut5_I0_O) 0.124 51.748 f core_design/yellowWinXOffset[1][6]_i_81/O + net (fo=12, routed) 1.020 52.768 core_design/yellowWinXOffset[1][6]_i_81_n_0 + SLICE_X69Y94 LUT3 (Prop_lut3_I0_O) 0.152 52.920 r core_design/yellowWinXOffset[6][5]_i_64/O + net (fo=3, routed) 0.440 53.360 core_design/yellowWinXOffset[6][5]_i_64_n_0 + SLICE_X70Y94 LUT6 (Prop_lut6_I5_O) 0.326 53.686 r core_design/yellowWinYOffset[4][6]_i_57/O + net (fo=14, routed) 1.810 55.496 core_design/yellowWinYOffset[4][6]_i_57_n_0 + SLICE_X72Y98 LUT6 (Prop_lut6_I4_O) 0.124 55.620 r core_design/yellowWinXOffset[3][2]_i_7/O + net (fo=2, routed) 1.191 56.811 core_design/yellowWinXOffset[3][2]_i_7_n_0 + SLICE_X72Y100 LUT6 (Prop_lut6_I1_O) 0.124 56.935 f core_design/yellowWinXOffset[3][2]_i_5/O + net (fo=24, routed) 1.804 58.739 core_design/yellowWinXOffset[3][2]_i_5_n_0 + SLICE_X66Y99 LUT4 (Prop_lut4_I2_O) 0.152 58.891 f core_design/yellowWinXOffset[3][6]_i_16/O + net (fo=2, routed) 0.615 59.506 core_design/yellowWinXOffset[3][6]_i_16_n_0 + SLICE_X70Y101 LUT6 (Prop_lut6_I5_O) 0.348 59.854 f core_design/yellowWinXOffset[6][6]_i_6/O + net (fo=11, routed) 1.304 61.157 core_design/yellowWinXOffset[6][6]_i_6_n_0 + SLICE_X62Y100 LUT6 (Prop_lut6_I0_O) 0.124 61.281 f core_design/yellowWinXOffset[5][6]_i_10/O + net (fo=8, routed) 0.956 62.237 core_design/yellowWinXOffset[5][6]_i_10_n_0 + SLICE_X63Y100 LUT6 (Prop_lut6_I5_O) 0.124 62.361 r core_design/yellowWinXOffset[5][6]_i_3/O + net (fo=1, routed) 0.951 63.313 core_design/yellowWinXOffset[5][6]_i_3_n_0 + SLICE_X63Y104 LUT4 (Prop_lut4_I2_O) 0.124 63.437 r core_design/yellowWinXOffset[5][6]_i_1/O + net (fo=11, routed) 0.647 64.084 core_design/yellowWinXOffset[5][6]_i_1_n_0 + SLICE_X66Y104 FDCE r core_design/yellowWinXOffset_reg[5][5]/CE ------------------------------------------------------------------- ------------------- Slack: inf - Source: pixY_reg[2]/C - (rising edge-triggered cell FDRE) - Destination: board_gfx/paletteIndex_reg[1]/D + Source: core_design/board_reg[29][0]/C + (rising edge-triggered cell FDCE) + Destination: core_design/yellowWinXOffset_reg[5][6]/CE Path Group: (none) Path Type: Max at Slow Process Corner - Data Path Delay: 12.447ns (logic 2.256ns (18.125%) route 10.191ns (81.875%)) - Logic Levels: 8 (CARRY4=2 FDRE=1 LUT1=1 LUT5=1 LUT6=3) + Data Path Delay: 64.084ns (logic 10.806ns (16.862%) route 53.278ns (83.138%)) + Logic Levels: 50 (CARRY4=6 FDCE=1 LUT1=1 LUT2=2 LUT3=2 LUT4=5 LUT5=8 LUT6=23 MUXF7=2) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - SLICE_X73Y152 FDRE 0.000 0.000 r pixY_reg[2]/C - SLICE_X73Y152 FDRE (Prop_fdre_C_Q) 0.419 0.419 f pixY_reg[2]/Q - net (fo=186, routed) 5.949 6.368 board_gfx/Q[0] - SLICE_X85Y145 LUT1 (Prop_lut1_I0_O) 0.296 6.664 r board_gfx/paletteIndex[3]_i_9/O - net (fo=1, routed) 0.000 6.664 board_gfx/paletteIndex[3]_i_9_n_0 - SLICE_X85Y145 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 7.196 r board_gfx/paletteIndex_reg[3]_i_4__5/CO[3] - net (fo=1, routed) 0.000 7.196 board_gfx/paletteIndex_reg[3]_i_4__5_n_0 - SLICE_X85Y146 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 7.530 r board_gfx/valid_reg_i_3__20/O[1] - net (fo=10, routed) 1.061 8.591 board_gfx/y0173_out[5] - SLICE_X86Y144 LUT6 (Prop_lut6_I3_O) 0.303 8.894 r board_gfx/paletteIndex[3]_i_12__0/O - net (fo=1, routed) 0.798 9.692 board_gfx/paletteIndex[3]_i_12__0_n_0 - SLICE_X86Y144 LUT5 (Prop_lut5_I0_O) 0.124 9.816 r board_gfx/paletteIndex[3]_i_4__11/O - net (fo=8, routed) 1.344 11.161 board_gfx/paletteIndex[3]_i_4__11_n_0 - SLICE_X81Y149 LUT6 (Prop_lut6_I4_O) 0.124 11.285 r board_gfx/paletteIndex[1]_i_2__36/O - net (fo=1, routed) 0.473 11.758 board_gfx/paletteIndex[1]_i_2__36_n_0 - SLICE_X81Y149 LUT6 (Prop_lut6_I3_O) 0.124 11.882 r board_gfx/paletteIndex[1]_i_1__43/O - net (fo=2, routed) 0.565 12.447 board_gfx/paletteIndex[1]_i_1__43_n_0 - SLICE_X79Y150 FDRE r board_gfx/paletteIndex_reg[1]/D + SLICE_X12Y150 FDCE 0.000 0.000 r core_design/board_reg[29][0]/C + SLICE_X12Y150 FDCE (Prop_fdce_C_Q) 0.518 0.518 r core_design/board_reg[29][0]/Q + net (fo=171, routed) 6.704 7.222 core_design/board_reg_n_0_[29][0] + SLICE_X47Y111 LUT2 (Prop_lut2_I0_O) 0.124 7.346 r core_design/showYellowWinIndicator[4]_i_200/O + net (fo=49, routed) 1.983 9.329 core_design/checkWinsYellow.(null)[2].(null)[5].c[0] + SLICE_X32Y109 LUT5 (Prop_lut5_I4_O) 0.124 9.453 r core_design/yellowWinXOffset[0][4]_i_874/O + net (fo=1, routed) 0.000 9.453 core_design/yellowWinXOffset[0][4]_i_874_n_0 + SLICE_X32Y109 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 10.003 r core_design/yellowWinXOffset_reg[0][4]_i_778/CO[3] + net (fo=1, routed) 0.000 10.003 core_design/yellowWinXOffset_reg[0][4]_i_778_n_0 + SLICE_X32Y110 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 10.225 r core_design/yellowWinXOffset_reg[0][4]_i_779/O[0] + net (fo=3, routed) 0.810 11.035 core_design/yellowWinXOffset_reg[0][4]_i_779_n_7 + SLICE_X33Y109 LUT4 (Prop_lut4_I1_O) 0.329 11.364 r core_design/yellowWinXOffset[0][4]_i_869/O + net (fo=4, routed) 1.007 12.370 core_design/yellowWinXOffset[0][4]_i_869_n_0 + SLICE_X33Y110 LUT3 (Prop_lut3_I1_O) 0.327 12.697 f core_design/yellowWinXOffset[0][4]_i_777/O + net (fo=1, routed) 0.000 12.697 core_design/yellowWinXOffset[0][4]_i_777_n_0 + SLICE_X33Y110 MUXF7 (Prop_muxf7_I1_O) 0.217 12.914 f core_design/yellowWinXOffset_reg[0][4]_i_625/O + net (fo=1, routed) 0.436 13.350 core_design/yellowWinXOffset_reg[0][4]_i_625_n_0 + SLICE_X33Y110 LUT5 (Prop_lut5_I2_O) 0.299 13.649 r core_design/yellowWinXOffset[0][4]_i_489/O + net (fo=9, routed) 0.806 14.455 core_design/yellowWinXOffset[0][4]_i_489_n_0 + SLICE_X38Y112 LUT6 (Prop_lut6_I5_O) 0.124 14.579 f core_design/yellowWinXOffset[0][4]_i_935/O + net (fo=4, routed) 0.632 15.211 core_design/yellowWinXOffset[0][4]_i_935_n_0 + SLICE_X33Y111 LUT1 (Prop_lut1_I0_O) 0.124 15.335 r core_design/yellowWinXOffset[0][4]_i_933/O + net (fo=1, routed) 0.000 15.335 core_design/yellowWinXOffset[0][4]_i_933_n_0 + SLICE_X33Y111 CARRY4 (Prop_carry4_S[1]_O[2]) + 0.580 15.915 r core_design/yellowWinXOffset_reg[0][4]_i_876/O[2] + net (fo=2, routed) 0.817 16.732 core_design/checkWinsYellow.(null)[0].(null)[5].count5[2] + SLICE_X32Y111 LUT5 (Prop_lut5_I4_O) 0.302 17.034 r core_design/yellowWinXOffset[0][4]_i_877/O + net (fo=1, routed) 0.000 17.034 core_design/yellowWinXOffset[0][4]_i_877_n_0 + SLICE_X32Y111 CARRY4 (Prop_carry4_S[2]_CO[3]) + 0.398 17.432 r core_design/yellowWinXOffset_reg[0][4]_i_780/CO[3] + net (fo=1, routed) 0.000 17.432 core_design/yellowWinXOffset_reg[0][4]_i_780_n_0 + SLICE_X32Y112 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 17.766 f core_design/yellowWinXOffset_reg[0][4]_i_781/O[1] + net (fo=4, routed) 0.675 18.441 core_design/yellowWinXOffset_reg[0][4]_i_781_n_6 + SLICE_X31Y111 LUT6 (Prop_lut6_I0_O) 0.303 18.744 r core_design/yellowWinXOffset[0][4]_i_785/O + net (fo=8, routed) 1.306 20.050 core_design/yellowWinXOffset[0][4]_i_785_n_0 + SLICE_X34Y114 LUT5 (Prop_lut5_I2_O) 0.124 20.174 f core_design/yellowWinXOffset[0][4]_i_882/O + net (fo=1, routed) 0.165 20.339 core_design/yellowWinXOffset[0][4]_i_882_n_0 + SLICE_X34Y114 LUT6 (Prop_lut6_I0_O) 0.124 20.463 r core_design/yellowWinXOffset[0][4]_i_782/O + net (fo=1, routed) 1.040 21.503 core_design/yellowWinXOffset[0][4]_i_782_n_0 + SLICE_X33Y113 LUT6 (Prop_lut6_I0_O) 0.124 21.627 r core_design/yellowWinXOffset[0][4]_i_628/O + net (fo=1, routed) 0.000 21.627 core_design/yellowWinXOffset[0][4]_i_628_n_0 + SLICE_X33Y113 MUXF7 (Prop_muxf7_I0_O) 0.212 21.839 r core_design/yellowWinXOffset_reg[0][4]_i_490/O + net (fo=3, routed) 1.185 23.024 core_design/yellowWinXOffset_reg[0][4]_i_490_n_0 + SLICE_X38Y112 LUT6 (Prop_lut6_I4_O) 0.299 23.323 r core_design/yellowWinXOffset[0][4]_i_361/O + net (fo=1, routed) 0.517 23.840 core_design/yellowWinXOffset[0][4]_i_361_n_0 + SLICE_X40Y112 CARRY4 (Prop_carry4_DI[0]_CO[1]) + 0.465 24.305 r core_design/yellowWinXOffset_reg[0][4]_i_249/CO[1] + net (fo=1, routed) 0.816 25.121 core_design/yellowWinXOffset_reg[0][4]_i_249_n_2 + SLICE_X41Y113 LUT6 (Prop_lut6_I4_O) 0.329 25.450 r core_design/yellowWinXOffset[0][4]_i_150/O + net (fo=15, routed) 2.286 27.736 core_design/showYellowWinIndicator1102_out + SLICE_X34Y90 LUT6 (Prop_lut6_I0_O) 0.124 27.860 r core_design/yellowWinXOffset[0][4]_i_138/O + net (fo=49, routed) 1.812 29.672 core_design/yellowWinXOffset[0][4]_i_138_n_0 + SLICE_X36Y87 LUT5 (Prop_lut5_I2_O) 0.150 29.822 r core_design/yellowWinXOffset[0][5]_i_123/O + net (fo=16, routed) 1.018 30.840 core_design/yellowWinXOffset[0][5]_i_123_n_0 + SLICE_X34Y89 LUT5 (Prop_lut5_I4_O) 0.326 31.166 f core_design/yellowWinXOffset[0][5]_i_125/O + net (fo=4, routed) 0.746 31.911 core_design/yellowWinXOffset[0][5]_i_125_n_0 + SLICE_X35Y88 LUT6 (Prop_lut6_I4_O) 0.124 32.035 r core_design/yellowWinXOffset[0][5]_i_57/O + net (fo=33, routed) 1.169 33.204 core_design/yellowWinXOffset[0][5]_i_57_n_0 + SLICE_X38Y88 LUT6 (Prop_lut6_I2_O) 0.124 33.328 r core_design/showYellowWinIndicator[1]_i_25/O + net (fo=39, routed) 2.027 35.355 core_design/showYellowWinIndicator[1]_i_25_n_0 + SLICE_X44Y96 LUT6 (Prop_lut6_I5_O) 0.124 35.479 r core_design/showYellowWinIndicator[1]_i_14/O + net (fo=25, routed) 0.868 36.347 core_design/showYellowWinIndicator[1]_i_14_n_0 + SLICE_X44Y95 LUT6 (Prop_lut6_I0_O) 0.124 36.471 r core_design/showYellowWinIndicator[6]_i_93/O + net (fo=17, routed) 1.048 37.519 core_design/showYellowWinIndicator[6]_i_93_n_0 + SLICE_X48Y90 LUT6 (Prop_lut6_I0_O) 0.124 37.643 r core_design/showYellowWinIndicator[6]_i_39/O + net (fo=21, routed) 1.768 39.412 core_design/showYellowWinIndicator[6]_i_39_n_0 + SLICE_X48Y97 LUT6 (Prop_lut6_I0_O) 0.124 39.536 f core_design/showYellowWinIndicator[6]_i_17/O + net (fo=20, routed) 1.453 40.988 core_design/showYellowWinIndicator[6]_i_17_n_0 + SLICE_X51Y88 LUT4 (Prop_lut4_I3_O) 0.118 41.106 r core_design/yellowWinXOffset[1][6]_i_255/O + net (fo=5, routed) 0.822 41.929 core_design/yellowWinXOffset[1][6]_i_255_n_0 + SLICE_X52Y87 LUT2 (Prop_lut2_I1_O) 0.326 42.255 r core_design/yellowWinXOffset[1][6]_i_201/O + net (fo=16, routed) 1.340 43.595 core_design/yellowWinXOffset[1][6]_i_201_n_0 + SLICE_X57Y84 LUT6 (Prop_lut6_I2_O) 0.124 43.719 r core_design/yellowWinXOffset[0][5]_i_90/O + net (fo=8, routed) 1.736 45.454 core_design/yellowWinXOffset[0][5]_i_90_n_0 + SLICE_X57Y88 LUT4 (Prop_lut4_I3_O) 0.124 45.578 r core_design/yellowWinXOffset[0][6]_i_239/O + net (fo=5, routed) 1.473 47.052 core_design/yellowWinXOffset[0][6]_i_239_n_0 + SLICE_X61Y86 LUT6 (Prop_lut6_I3_O) 0.124 47.176 r core_design/yellowWinXOffset[4][4]_i_52/O + net (fo=3, routed) 1.190 48.366 core_design/yellowWinXOffset[4][4]_i_52_n_0 + SLICE_X62Y88 LUT6 (Prop_lut6_I0_O) 0.124 48.490 r core_design/yellowWinXOffset[6][5]_i_54/O + net (fo=3, routed) 0.671 49.161 core_design/yellowWinXOffset[6][5]_i_54_n_0 + SLICE_X64Y87 LUT5 (Prop_lut5_I2_O) 0.124 49.285 f core_design/yellowWinXOffset[6][5]_i_25/O + net (fo=30, routed) 1.171 50.456 core_design/yellowWinXOffset[6][5]_i_25_n_0 + SLICE_X66Y86 LUT6 (Prop_lut6_I5_O) 0.124 50.580 r core_design/yellowWinXOffset[4][4]_i_21/O + net (fo=8, routed) 1.044 51.624 core_design/yellowWinXOffset[4][4]_i_21_n_0 + SLICE_X68Y90 LUT5 (Prop_lut5_I0_O) 0.124 51.748 f core_design/yellowWinXOffset[1][6]_i_81/O + net (fo=12, routed) 1.020 52.768 core_design/yellowWinXOffset[1][6]_i_81_n_0 + SLICE_X69Y94 LUT3 (Prop_lut3_I0_O) 0.152 52.920 r core_design/yellowWinXOffset[6][5]_i_64/O + net (fo=3, routed) 0.440 53.360 core_design/yellowWinXOffset[6][5]_i_64_n_0 + SLICE_X70Y94 LUT6 (Prop_lut6_I5_O) 0.326 53.686 r core_design/yellowWinYOffset[4][6]_i_57/O + net (fo=14, routed) 1.810 55.496 core_design/yellowWinYOffset[4][6]_i_57_n_0 + SLICE_X72Y98 LUT6 (Prop_lut6_I4_O) 0.124 55.620 r core_design/yellowWinXOffset[3][2]_i_7/O + net (fo=2, routed) 1.191 56.811 core_design/yellowWinXOffset[3][2]_i_7_n_0 + SLICE_X72Y100 LUT6 (Prop_lut6_I1_O) 0.124 56.935 f core_design/yellowWinXOffset[3][2]_i_5/O + net (fo=24, routed) 1.804 58.739 core_design/yellowWinXOffset[3][2]_i_5_n_0 + SLICE_X66Y99 LUT4 (Prop_lut4_I2_O) 0.152 58.891 f core_design/yellowWinXOffset[3][6]_i_16/O + net (fo=2, routed) 0.615 59.506 core_design/yellowWinXOffset[3][6]_i_16_n_0 + SLICE_X70Y101 LUT6 (Prop_lut6_I5_O) 0.348 59.854 f core_design/yellowWinXOffset[6][6]_i_6/O + net (fo=11, routed) 1.304 61.157 core_design/yellowWinXOffset[6][6]_i_6_n_0 + SLICE_X62Y100 LUT6 (Prop_lut6_I0_O) 0.124 61.281 f core_design/yellowWinXOffset[5][6]_i_10/O + net (fo=8, routed) 0.956 62.237 core_design/yellowWinXOffset[5][6]_i_10_n_0 + SLICE_X63Y100 LUT6 (Prop_lut6_I5_O) 0.124 62.361 r core_design/yellowWinXOffset[5][6]_i_3/O + net (fo=1, routed) 0.951 63.313 core_design/yellowWinXOffset[5][6]_i_3_n_0 + SLICE_X63Y104 LUT4 (Prop_lut4_I2_O) 0.124 63.437 r core_design/yellowWinXOffset[5][6]_i_1/O + net (fo=11, routed) 0.647 64.084 core_design/yellowWinXOffset[5][6]_i_1_n_0 + SLICE_X66Y104 FDCE r core_design/yellowWinXOffset_reg[5][6]/CE ------------------------------------------------------------------- ------------------- Slack: inf - Source: pixY_reg[2]/C - (rising edge-triggered cell FDRE) - Destination: board_gfx/paletteIndex_reg[0]/D + Source: core_design/board_reg[29][0]/C + (rising edge-triggered cell FDCE) + Destination: core_design/yellowWinYOffset_reg[5][0]/CE Path Group: (none) Path Type: Max at Slow Process Corner - Data Path Delay: 12.291ns (logic 2.186ns (17.785%) route 10.105ns (82.215%)) - Logic Levels: 8 (CARRY4=2 FDRE=1 LUT1=1 LUT4=2 LUT6=2) + Data Path Delay: 64.084ns (logic 10.806ns (16.862%) route 53.278ns (83.138%)) + Logic Levels: 50 (CARRY4=6 FDCE=1 LUT1=1 LUT2=2 LUT3=2 LUT4=5 LUT5=8 LUT6=23 MUXF7=2) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - SLICE_X73Y152 FDRE 0.000 0.000 r pixY_reg[2]/C - SLICE_X73Y152 FDRE (Prop_fdre_C_Q) 0.419 0.419 f pixY_reg[2]/Q - net (fo=186, routed) 5.949 6.368 board_gfx/Q[0] - SLICE_X85Y145 LUT1 (Prop_lut1_I0_O) 0.296 6.664 r board_gfx/paletteIndex[3]_i_9/O - net (fo=1, routed) 0.000 6.664 board_gfx/paletteIndex[3]_i_9_n_0 - SLICE_X85Y145 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 7.196 r board_gfx/paletteIndex_reg[3]_i_4__5/CO[3] - net (fo=1, routed) 0.000 7.196 board_gfx/paletteIndex_reg[3]_i_4__5_n_0 - SLICE_X85Y146 CARRY4 (Prop_carry4_CI_O[2]) - 0.239 7.435 f board_gfx/valid_reg_i_3__20/O[2] - net (fo=9, routed) 1.072 8.507 board_gfx/y0173_out[6] - SLICE_X86Y145 LUT6 (Prop_lut6_I5_O) 0.302 8.809 r board_gfx/paletteIndex[3]_i_10__0/O - net (fo=1, routed) 0.670 9.480 board_gfx/paletteIndex[3]_i_10__0_n_0 - SLICE_X86Y145 LUT4 (Prop_lut4_I1_O) 0.124 9.604 r board_gfx/paletteIndex[3]_i_3__6/O - net (fo=7, routed) 0.817 10.421 board_gfx/paletteIndex[3]_i_3__6_n_0 - SLICE_X86Y147 LUT6 (Prop_lut6_I2_O) 0.124 10.545 r board_gfx/paletteIndex[0]_i_2__17/O - net (fo=1, routed) 1.032 11.577 board_gfx/paletteIndex[0]_i_2__17_n_0 - SLICE_X81Y149 LUT4 (Prop_lut4_I3_O) 0.150 11.727 r board_gfx/paletteIndex[0]_i_1__22/O - net (fo=2, routed) 0.565 12.291 board_gfx/paletteIndex[0]_i_1__22_n_0 - SLICE_X78Y150 FDRE r board_gfx/paletteIndex_reg[0]/D + SLICE_X12Y150 FDCE 0.000 0.000 r core_design/board_reg[29][0]/C + SLICE_X12Y150 FDCE (Prop_fdce_C_Q) 0.518 0.518 r core_design/board_reg[29][0]/Q + net (fo=171, routed) 6.704 7.222 core_design/board_reg_n_0_[29][0] + SLICE_X47Y111 LUT2 (Prop_lut2_I0_O) 0.124 7.346 r core_design/showYellowWinIndicator[4]_i_200/O + net (fo=49, routed) 1.983 9.329 core_design/checkWinsYellow.(null)[2].(null)[5].c[0] + SLICE_X32Y109 LUT5 (Prop_lut5_I4_O) 0.124 9.453 r core_design/yellowWinXOffset[0][4]_i_874/O + net (fo=1, routed) 0.000 9.453 core_design/yellowWinXOffset[0][4]_i_874_n_0 + SLICE_X32Y109 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 10.003 r core_design/yellowWinXOffset_reg[0][4]_i_778/CO[3] + net (fo=1, routed) 0.000 10.003 core_design/yellowWinXOffset_reg[0][4]_i_778_n_0 + SLICE_X32Y110 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 10.225 r core_design/yellowWinXOffset_reg[0][4]_i_779/O[0] + net (fo=3, routed) 0.810 11.035 core_design/yellowWinXOffset_reg[0][4]_i_779_n_7 + SLICE_X33Y109 LUT4 (Prop_lut4_I1_O) 0.329 11.364 r core_design/yellowWinXOffset[0][4]_i_869/O + net (fo=4, routed) 1.007 12.370 core_design/yellowWinXOffset[0][4]_i_869_n_0 + SLICE_X33Y110 LUT3 (Prop_lut3_I1_O) 0.327 12.697 f core_design/yellowWinXOffset[0][4]_i_777/O + net (fo=1, routed) 0.000 12.697 core_design/yellowWinXOffset[0][4]_i_777_n_0 + SLICE_X33Y110 MUXF7 (Prop_muxf7_I1_O) 0.217 12.914 f core_design/yellowWinXOffset_reg[0][4]_i_625/O + net (fo=1, routed) 0.436 13.350 core_design/yellowWinXOffset_reg[0][4]_i_625_n_0 + SLICE_X33Y110 LUT5 (Prop_lut5_I2_O) 0.299 13.649 r core_design/yellowWinXOffset[0][4]_i_489/O + net (fo=9, routed) 0.806 14.455 core_design/yellowWinXOffset[0][4]_i_489_n_0 + SLICE_X38Y112 LUT6 (Prop_lut6_I5_O) 0.124 14.579 f core_design/yellowWinXOffset[0][4]_i_935/O + net (fo=4, routed) 0.632 15.211 core_design/yellowWinXOffset[0][4]_i_935_n_0 + SLICE_X33Y111 LUT1 (Prop_lut1_I0_O) 0.124 15.335 r core_design/yellowWinXOffset[0][4]_i_933/O + net (fo=1, routed) 0.000 15.335 core_design/yellowWinXOffset[0][4]_i_933_n_0 + SLICE_X33Y111 CARRY4 (Prop_carry4_S[1]_O[2]) + 0.580 15.915 r core_design/yellowWinXOffset_reg[0][4]_i_876/O[2] + net (fo=2, routed) 0.817 16.732 core_design/checkWinsYellow.(null)[0].(null)[5].count5[2] + SLICE_X32Y111 LUT5 (Prop_lut5_I4_O) 0.302 17.034 r core_design/yellowWinXOffset[0][4]_i_877/O + net (fo=1, routed) 0.000 17.034 core_design/yellowWinXOffset[0][4]_i_877_n_0 + SLICE_X32Y111 CARRY4 (Prop_carry4_S[2]_CO[3]) + 0.398 17.432 r core_design/yellowWinXOffset_reg[0][4]_i_780/CO[3] + net (fo=1, routed) 0.000 17.432 core_design/yellowWinXOffset_reg[0][4]_i_780_n_0 + SLICE_X32Y112 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 17.766 f core_design/yellowWinXOffset_reg[0][4]_i_781/O[1] + net (fo=4, routed) 0.675 18.441 core_design/yellowWinXOffset_reg[0][4]_i_781_n_6 + SLICE_X31Y111 LUT6 (Prop_lut6_I0_O) 0.303 18.744 r core_design/yellowWinXOffset[0][4]_i_785/O + net (fo=8, routed) 1.306 20.050 core_design/yellowWinXOffset[0][4]_i_785_n_0 + SLICE_X34Y114 LUT5 (Prop_lut5_I2_O) 0.124 20.174 f core_design/yellowWinXOffset[0][4]_i_882/O + net (fo=1, routed) 0.165 20.339 core_design/yellowWinXOffset[0][4]_i_882_n_0 + SLICE_X34Y114 LUT6 (Prop_lut6_I0_O) 0.124 20.463 r core_design/yellowWinXOffset[0][4]_i_782/O + net (fo=1, routed) 1.040 21.503 core_design/yellowWinXOffset[0][4]_i_782_n_0 + SLICE_X33Y113 LUT6 (Prop_lut6_I0_O) 0.124 21.627 r core_design/yellowWinXOffset[0][4]_i_628/O + net (fo=1, routed) 0.000 21.627 core_design/yellowWinXOffset[0][4]_i_628_n_0 + SLICE_X33Y113 MUXF7 (Prop_muxf7_I0_O) 0.212 21.839 r core_design/yellowWinXOffset_reg[0][4]_i_490/O + net (fo=3, routed) 1.185 23.024 core_design/yellowWinXOffset_reg[0][4]_i_490_n_0 + SLICE_X38Y112 LUT6 (Prop_lut6_I4_O) 0.299 23.323 r core_design/yellowWinXOffset[0][4]_i_361/O + net (fo=1, routed) 0.517 23.840 core_design/yellowWinXOffset[0][4]_i_361_n_0 + SLICE_X40Y112 CARRY4 (Prop_carry4_DI[0]_CO[1]) + 0.465 24.305 r core_design/yellowWinXOffset_reg[0][4]_i_249/CO[1] + net (fo=1, routed) 0.816 25.121 core_design/yellowWinXOffset_reg[0][4]_i_249_n_2 + SLICE_X41Y113 LUT6 (Prop_lut6_I4_O) 0.329 25.450 r core_design/yellowWinXOffset[0][4]_i_150/O + net (fo=15, routed) 2.286 27.736 core_design/showYellowWinIndicator1102_out + SLICE_X34Y90 LUT6 (Prop_lut6_I0_O) 0.124 27.860 r core_design/yellowWinXOffset[0][4]_i_138/O + net (fo=49, routed) 1.812 29.672 core_design/yellowWinXOffset[0][4]_i_138_n_0 + SLICE_X36Y87 LUT5 (Prop_lut5_I2_O) 0.150 29.822 r core_design/yellowWinXOffset[0][5]_i_123/O + net (fo=16, routed) 1.018 30.840 core_design/yellowWinXOffset[0][5]_i_123_n_0 + SLICE_X34Y89 LUT5 (Prop_lut5_I4_O) 0.326 31.166 f core_design/yellowWinXOffset[0][5]_i_125/O + net (fo=4, routed) 0.746 31.911 core_design/yellowWinXOffset[0][5]_i_125_n_0 + SLICE_X35Y88 LUT6 (Prop_lut6_I4_O) 0.124 32.035 r core_design/yellowWinXOffset[0][5]_i_57/O + net (fo=33, routed) 1.169 33.204 core_design/yellowWinXOffset[0][5]_i_57_n_0 + SLICE_X38Y88 LUT6 (Prop_lut6_I2_O) 0.124 33.328 r core_design/showYellowWinIndicator[1]_i_25/O + net (fo=39, routed) 2.027 35.355 core_design/showYellowWinIndicator[1]_i_25_n_0 + SLICE_X44Y96 LUT6 (Prop_lut6_I5_O) 0.124 35.479 r core_design/showYellowWinIndicator[1]_i_14/O + net (fo=25, routed) 0.868 36.347 core_design/showYellowWinIndicator[1]_i_14_n_0 + SLICE_X44Y95 LUT6 (Prop_lut6_I0_O) 0.124 36.471 r core_design/showYellowWinIndicator[6]_i_93/O + net (fo=17, routed) 1.048 37.519 core_design/showYellowWinIndicator[6]_i_93_n_0 + SLICE_X48Y90 LUT6 (Prop_lut6_I0_O) 0.124 37.643 r core_design/showYellowWinIndicator[6]_i_39/O + net (fo=21, routed) 1.768 39.412 core_design/showYellowWinIndicator[6]_i_39_n_0 + SLICE_X48Y97 LUT6 (Prop_lut6_I0_O) 0.124 39.536 f core_design/showYellowWinIndicator[6]_i_17/O + net (fo=20, routed) 1.453 40.988 core_design/showYellowWinIndicator[6]_i_17_n_0 + SLICE_X51Y88 LUT4 (Prop_lut4_I3_O) 0.118 41.106 r core_design/yellowWinXOffset[1][6]_i_255/O + net (fo=5, routed) 0.822 41.929 core_design/yellowWinXOffset[1][6]_i_255_n_0 + SLICE_X52Y87 LUT2 (Prop_lut2_I1_O) 0.326 42.255 r core_design/yellowWinXOffset[1][6]_i_201/O + net (fo=16, routed) 1.340 43.595 core_design/yellowWinXOffset[1][6]_i_201_n_0 + SLICE_X57Y84 LUT6 (Prop_lut6_I2_O) 0.124 43.719 r core_design/yellowWinXOffset[0][5]_i_90/O + net (fo=8, routed) 1.736 45.454 core_design/yellowWinXOffset[0][5]_i_90_n_0 + SLICE_X57Y88 LUT4 (Prop_lut4_I3_O) 0.124 45.578 r core_design/yellowWinXOffset[0][6]_i_239/O + net (fo=5, routed) 1.473 47.052 core_design/yellowWinXOffset[0][6]_i_239_n_0 + SLICE_X61Y86 LUT6 (Prop_lut6_I3_O) 0.124 47.176 r core_design/yellowWinXOffset[4][4]_i_52/O + net (fo=3, routed) 1.190 48.366 core_design/yellowWinXOffset[4][4]_i_52_n_0 + SLICE_X62Y88 LUT6 (Prop_lut6_I0_O) 0.124 48.490 r core_design/yellowWinXOffset[6][5]_i_54/O + net (fo=3, routed) 0.671 49.161 core_design/yellowWinXOffset[6][5]_i_54_n_0 + SLICE_X64Y87 LUT5 (Prop_lut5_I2_O) 0.124 49.285 f core_design/yellowWinXOffset[6][5]_i_25/O + net (fo=30, routed) 1.171 50.456 core_design/yellowWinXOffset[6][5]_i_25_n_0 + SLICE_X66Y86 LUT6 (Prop_lut6_I5_O) 0.124 50.580 r core_design/yellowWinXOffset[4][4]_i_21/O + net (fo=8, routed) 1.044 51.624 core_design/yellowWinXOffset[4][4]_i_21_n_0 + SLICE_X68Y90 LUT5 (Prop_lut5_I0_O) 0.124 51.748 f core_design/yellowWinXOffset[1][6]_i_81/O + net (fo=12, routed) 1.020 52.768 core_design/yellowWinXOffset[1][6]_i_81_n_0 + SLICE_X69Y94 LUT3 (Prop_lut3_I0_O) 0.152 52.920 r core_design/yellowWinXOffset[6][5]_i_64/O + net (fo=3, routed) 0.440 53.360 core_design/yellowWinXOffset[6][5]_i_64_n_0 + SLICE_X70Y94 LUT6 (Prop_lut6_I5_O) 0.326 53.686 r core_design/yellowWinYOffset[4][6]_i_57/O + net (fo=14, routed) 1.810 55.496 core_design/yellowWinYOffset[4][6]_i_57_n_0 + SLICE_X72Y98 LUT6 (Prop_lut6_I4_O) 0.124 55.620 r core_design/yellowWinXOffset[3][2]_i_7/O + net (fo=2, routed) 1.191 56.811 core_design/yellowWinXOffset[3][2]_i_7_n_0 + SLICE_X72Y100 LUT6 (Prop_lut6_I1_O) 0.124 56.935 f core_design/yellowWinXOffset[3][2]_i_5/O + net (fo=24, routed) 1.804 58.739 core_design/yellowWinXOffset[3][2]_i_5_n_0 + SLICE_X66Y99 LUT4 (Prop_lut4_I2_O) 0.152 58.891 f core_design/yellowWinXOffset[3][6]_i_16/O + net (fo=2, routed) 0.615 59.506 core_design/yellowWinXOffset[3][6]_i_16_n_0 + SLICE_X70Y101 LUT6 (Prop_lut6_I5_O) 0.348 59.854 f core_design/yellowWinXOffset[6][6]_i_6/O + net (fo=11, routed) 1.304 61.157 core_design/yellowWinXOffset[6][6]_i_6_n_0 + SLICE_X62Y100 LUT6 (Prop_lut6_I0_O) 0.124 61.281 f core_design/yellowWinXOffset[5][6]_i_10/O + net (fo=8, routed) 0.956 62.237 core_design/yellowWinXOffset[5][6]_i_10_n_0 + SLICE_X63Y100 LUT6 (Prop_lut6_I5_O) 0.124 62.361 r core_design/yellowWinXOffset[5][6]_i_3/O + net (fo=1, routed) 0.951 63.313 core_design/yellowWinXOffset[5][6]_i_3_n_0 + SLICE_X63Y104 LUT4 (Prop_lut4_I2_O) 0.124 63.437 r core_design/yellowWinXOffset[5][6]_i_1/O + net (fo=11, routed) 0.647 64.084 core_design/yellowWinXOffset[5][6]_i_1_n_0 + SLICE_X66Y104 FDCE r core_design/yellowWinYOffset_reg[5][0]/CE ------------------------------------------------------------------- ------------------- Slack: inf - Source: pixY_reg[2]/C - (rising edge-triggered cell FDRE) - Destination: board_gfx/paletteIndex_reg[2]/D + Source: core_design/board_reg[29][0]/C + (rising edge-triggered cell FDCE) + Destination: core_design/yellowWinYOffset_reg[5][1]/CE Path Group: (none) Path Type: Max at Slow Process Corner - Data Path Delay: 12.172ns (logic 2.256ns (18.535%) route 9.916ns (81.465%)) - Logic Levels: 8 (CARRY4=2 FDRE=1 LUT1=1 LUT5=1 LUT6=3) + Data Path Delay: 64.084ns (logic 10.806ns (16.862%) route 53.278ns (83.138%)) + Logic Levels: 50 (CARRY4=6 FDCE=1 LUT1=1 LUT2=2 LUT3=2 LUT4=5 LUT5=8 LUT6=23 MUXF7=2) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - SLICE_X73Y152 FDRE 0.000 0.000 r pixY_reg[2]/C - SLICE_X73Y152 FDRE (Prop_fdre_C_Q) 0.419 0.419 f pixY_reg[2]/Q - net (fo=186, routed) 5.949 6.368 board_gfx/Q[0] - SLICE_X85Y145 LUT1 (Prop_lut1_I0_O) 0.296 6.664 r board_gfx/paletteIndex[3]_i_9/O - net (fo=1, routed) 0.000 6.664 board_gfx/paletteIndex[3]_i_9_n_0 - SLICE_X85Y145 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 7.196 r board_gfx/paletteIndex_reg[3]_i_4__5/CO[3] - net (fo=1, routed) 0.000 7.196 board_gfx/paletteIndex_reg[3]_i_4__5_n_0 - SLICE_X85Y146 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 7.530 r board_gfx/valid_reg_i_3__20/O[1] - net (fo=10, routed) 1.061 8.591 board_gfx/y0173_out[5] - SLICE_X86Y144 LUT6 (Prop_lut6_I3_O) 0.303 8.894 r board_gfx/paletteIndex[3]_i_12__0/O - net (fo=1, routed) 0.798 9.692 board_gfx/paletteIndex[3]_i_12__0_n_0 - SLICE_X86Y144 LUT5 (Prop_lut5_I0_O) 0.124 9.816 r board_gfx/paletteIndex[3]_i_4__11/O - net (fo=8, routed) 1.090 10.906 board_gfx/paletteIndex[3]_i_4__11_n_0 - SLICE_X86Y149 LUT6 (Prop_lut6_I4_O) 0.124 11.030 r board_gfx/paletteIndex[2]_i_2__1/O - net (fo=1, routed) 0.307 11.337 board_gfx/paletteIndex[2]_i_2__1_n_0 - SLICE_X83Y149 LUT6 (Prop_lut6_I3_O) 0.124 11.461 r board_gfx/paletteIndex[2]_i_1__1/O - net (fo=2, routed) 0.711 12.172 board_gfx/paletteIndex[2]_i_1__1_n_0 - SLICE_X79Y149 FDRE r board_gfx/paletteIndex_reg[2]/D + SLICE_X12Y150 FDCE 0.000 0.000 r core_design/board_reg[29][0]/C + SLICE_X12Y150 FDCE (Prop_fdce_C_Q) 0.518 0.518 r core_design/board_reg[29][0]/Q + net (fo=171, routed) 6.704 7.222 core_design/board_reg_n_0_[29][0] + SLICE_X47Y111 LUT2 (Prop_lut2_I0_O) 0.124 7.346 r core_design/showYellowWinIndicator[4]_i_200/O + net (fo=49, routed) 1.983 9.329 core_design/checkWinsYellow.(null)[2].(null)[5].c[0] + SLICE_X32Y109 LUT5 (Prop_lut5_I4_O) 0.124 9.453 r core_design/yellowWinXOffset[0][4]_i_874/O + net (fo=1, routed) 0.000 9.453 core_design/yellowWinXOffset[0][4]_i_874_n_0 + SLICE_X32Y109 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 10.003 r core_design/yellowWinXOffset_reg[0][4]_i_778/CO[3] + net (fo=1, routed) 0.000 10.003 core_design/yellowWinXOffset_reg[0][4]_i_778_n_0 + SLICE_X32Y110 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 10.225 r core_design/yellowWinXOffset_reg[0][4]_i_779/O[0] + net (fo=3, routed) 0.810 11.035 core_design/yellowWinXOffset_reg[0][4]_i_779_n_7 + SLICE_X33Y109 LUT4 (Prop_lut4_I1_O) 0.329 11.364 r core_design/yellowWinXOffset[0][4]_i_869/O + net (fo=4, routed) 1.007 12.370 core_design/yellowWinXOffset[0][4]_i_869_n_0 + SLICE_X33Y110 LUT3 (Prop_lut3_I1_O) 0.327 12.697 f core_design/yellowWinXOffset[0][4]_i_777/O + net (fo=1, routed) 0.000 12.697 core_design/yellowWinXOffset[0][4]_i_777_n_0 + SLICE_X33Y110 MUXF7 (Prop_muxf7_I1_O) 0.217 12.914 f core_design/yellowWinXOffset_reg[0][4]_i_625/O + net (fo=1, routed) 0.436 13.350 core_design/yellowWinXOffset_reg[0][4]_i_625_n_0 + SLICE_X33Y110 LUT5 (Prop_lut5_I2_O) 0.299 13.649 r core_design/yellowWinXOffset[0][4]_i_489/O + net (fo=9, routed) 0.806 14.455 core_design/yellowWinXOffset[0][4]_i_489_n_0 + SLICE_X38Y112 LUT6 (Prop_lut6_I5_O) 0.124 14.579 f core_design/yellowWinXOffset[0][4]_i_935/O + net (fo=4, routed) 0.632 15.211 core_design/yellowWinXOffset[0][4]_i_935_n_0 + SLICE_X33Y111 LUT1 (Prop_lut1_I0_O) 0.124 15.335 r core_design/yellowWinXOffset[0][4]_i_933/O + net (fo=1, routed) 0.000 15.335 core_design/yellowWinXOffset[0][4]_i_933_n_0 + SLICE_X33Y111 CARRY4 (Prop_carry4_S[1]_O[2]) + 0.580 15.915 r core_design/yellowWinXOffset_reg[0][4]_i_876/O[2] + net (fo=2, routed) 0.817 16.732 core_design/checkWinsYellow.(null)[0].(null)[5].count5[2] + SLICE_X32Y111 LUT5 (Prop_lut5_I4_O) 0.302 17.034 r core_design/yellowWinXOffset[0][4]_i_877/O + net (fo=1, routed) 0.000 17.034 core_design/yellowWinXOffset[0][4]_i_877_n_0 + SLICE_X32Y111 CARRY4 (Prop_carry4_S[2]_CO[3]) + 0.398 17.432 r core_design/yellowWinXOffset_reg[0][4]_i_780/CO[3] + net (fo=1, routed) 0.000 17.432 core_design/yellowWinXOffset_reg[0][4]_i_780_n_0 + SLICE_X32Y112 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 17.766 f core_design/yellowWinXOffset_reg[0][4]_i_781/O[1] + net (fo=4, routed) 0.675 18.441 core_design/yellowWinXOffset_reg[0][4]_i_781_n_6 + SLICE_X31Y111 LUT6 (Prop_lut6_I0_O) 0.303 18.744 r core_design/yellowWinXOffset[0][4]_i_785/O + net (fo=8, routed) 1.306 20.050 core_design/yellowWinXOffset[0][4]_i_785_n_0 + SLICE_X34Y114 LUT5 (Prop_lut5_I2_O) 0.124 20.174 f core_design/yellowWinXOffset[0][4]_i_882/O + net (fo=1, routed) 0.165 20.339 core_design/yellowWinXOffset[0][4]_i_882_n_0 + SLICE_X34Y114 LUT6 (Prop_lut6_I0_O) 0.124 20.463 r core_design/yellowWinXOffset[0][4]_i_782/O + net (fo=1, routed) 1.040 21.503 core_design/yellowWinXOffset[0][4]_i_782_n_0 + SLICE_X33Y113 LUT6 (Prop_lut6_I0_O) 0.124 21.627 r core_design/yellowWinXOffset[0][4]_i_628/O + net (fo=1, routed) 0.000 21.627 core_design/yellowWinXOffset[0][4]_i_628_n_0 + SLICE_X33Y113 MUXF7 (Prop_muxf7_I0_O) 0.212 21.839 r core_design/yellowWinXOffset_reg[0][4]_i_490/O + net (fo=3, routed) 1.185 23.024 core_design/yellowWinXOffset_reg[0][4]_i_490_n_0 + SLICE_X38Y112 LUT6 (Prop_lut6_I4_O) 0.299 23.323 r core_design/yellowWinXOffset[0][4]_i_361/O + net (fo=1, routed) 0.517 23.840 core_design/yellowWinXOffset[0][4]_i_361_n_0 + SLICE_X40Y112 CARRY4 (Prop_carry4_DI[0]_CO[1]) + 0.465 24.305 r core_design/yellowWinXOffset_reg[0][4]_i_249/CO[1] + net (fo=1, routed) 0.816 25.121 core_design/yellowWinXOffset_reg[0][4]_i_249_n_2 + SLICE_X41Y113 LUT6 (Prop_lut6_I4_O) 0.329 25.450 r core_design/yellowWinXOffset[0][4]_i_150/O + net (fo=15, routed) 2.286 27.736 core_design/showYellowWinIndicator1102_out + SLICE_X34Y90 LUT6 (Prop_lut6_I0_O) 0.124 27.860 r core_design/yellowWinXOffset[0][4]_i_138/O + net (fo=49, routed) 1.812 29.672 core_design/yellowWinXOffset[0][4]_i_138_n_0 + SLICE_X36Y87 LUT5 (Prop_lut5_I2_O) 0.150 29.822 r core_design/yellowWinXOffset[0][5]_i_123/O + net (fo=16, routed) 1.018 30.840 core_design/yellowWinXOffset[0][5]_i_123_n_0 + SLICE_X34Y89 LUT5 (Prop_lut5_I4_O) 0.326 31.166 f core_design/yellowWinXOffset[0][5]_i_125/O + net (fo=4, routed) 0.746 31.911 core_design/yellowWinXOffset[0][5]_i_125_n_0 + SLICE_X35Y88 LUT6 (Prop_lut6_I4_O) 0.124 32.035 r core_design/yellowWinXOffset[0][5]_i_57/O + net (fo=33, routed) 1.169 33.204 core_design/yellowWinXOffset[0][5]_i_57_n_0 + SLICE_X38Y88 LUT6 (Prop_lut6_I2_O) 0.124 33.328 r core_design/showYellowWinIndicator[1]_i_25/O + net (fo=39, routed) 2.027 35.355 core_design/showYellowWinIndicator[1]_i_25_n_0 + SLICE_X44Y96 LUT6 (Prop_lut6_I5_O) 0.124 35.479 r core_design/showYellowWinIndicator[1]_i_14/O + net (fo=25, routed) 0.868 36.347 core_design/showYellowWinIndicator[1]_i_14_n_0 + SLICE_X44Y95 LUT6 (Prop_lut6_I0_O) 0.124 36.471 r core_design/showYellowWinIndicator[6]_i_93/O + net (fo=17, routed) 1.048 37.519 core_design/showYellowWinIndicator[6]_i_93_n_0 + SLICE_X48Y90 LUT6 (Prop_lut6_I0_O) 0.124 37.643 r core_design/showYellowWinIndicator[6]_i_39/O + net (fo=21, routed) 1.768 39.412 core_design/showYellowWinIndicator[6]_i_39_n_0 + SLICE_X48Y97 LUT6 (Prop_lut6_I0_O) 0.124 39.536 f core_design/showYellowWinIndicator[6]_i_17/O + net (fo=20, routed) 1.453 40.988 core_design/showYellowWinIndicator[6]_i_17_n_0 + SLICE_X51Y88 LUT4 (Prop_lut4_I3_O) 0.118 41.106 r core_design/yellowWinXOffset[1][6]_i_255/O + net (fo=5, routed) 0.822 41.929 core_design/yellowWinXOffset[1][6]_i_255_n_0 + SLICE_X52Y87 LUT2 (Prop_lut2_I1_O) 0.326 42.255 r core_design/yellowWinXOffset[1][6]_i_201/O + net (fo=16, routed) 1.340 43.595 core_design/yellowWinXOffset[1][6]_i_201_n_0 + SLICE_X57Y84 LUT6 (Prop_lut6_I2_O) 0.124 43.719 r core_design/yellowWinXOffset[0][5]_i_90/O + net (fo=8, routed) 1.736 45.454 core_design/yellowWinXOffset[0][5]_i_90_n_0 + SLICE_X57Y88 LUT4 (Prop_lut4_I3_O) 0.124 45.578 r core_design/yellowWinXOffset[0][6]_i_239/O + net (fo=5, routed) 1.473 47.052 core_design/yellowWinXOffset[0][6]_i_239_n_0 + SLICE_X61Y86 LUT6 (Prop_lut6_I3_O) 0.124 47.176 r core_design/yellowWinXOffset[4][4]_i_52/O + net (fo=3, routed) 1.190 48.366 core_design/yellowWinXOffset[4][4]_i_52_n_0 + SLICE_X62Y88 LUT6 (Prop_lut6_I0_O) 0.124 48.490 r core_design/yellowWinXOffset[6][5]_i_54/O + net (fo=3, routed) 0.671 49.161 core_design/yellowWinXOffset[6][5]_i_54_n_0 + SLICE_X64Y87 LUT5 (Prop_lut5_I2_O) 0.124 49.285 f core_design/yellowWinXOffset[6][5]_i_25/O + net (fo=30, routed) 1.171 50.456 core_design/yellowWinXOffset[6][5]_i_25_n_0 + SLICE_X66Y86 LUT6 (Prop_lut6_I5_O) 0.124 50.580 r core_design/yellowWinXOffset[4][4]_i_21/O + net (fo=8, routed) 1.044 51.624 core_design/yellowWinXOffset[4][4]_i_21_n_0 + SLICE_X68Y90 LUT5 (Prop_lut5_I0_O) 0.124 51.748 f core_design/yellowWinXOffset[1][6]_i_81/O + net (fo=12, routed) 1.020 52.768 core_design/yellowWinXOffset[1][6]_i_81_n_0 + SLICE_X69Y94 LUT3 (Prop_lut3_I0_O) 0.152 52.920 r core_design/yellowWinXOffset[6][5]_i_64/O + net (fo=3, routed) 0.440 53.360 core_design/yellowWinXOffset[6][5]_i_64_n_0 + SLICE_X70Y94 LUT6 (Prop_lut6_I5_O) 0.326 53.686 r core_design/yellowWinYOffset[4][6]_i_57/O + net (fo=14, routed) 1.810 55.496 core_design/yellowWinYOffset[4][6]_i_57_n_0 + SLICE_X72Y98 LUT6 (Prop_lut6_I4_O) 0.124 55.620 r core_design/yellowWinXOffset[3][2]_i_7/O + net (fo=2, routed) 1.191 56.811 core_design/yellowWinXOffset[3][2]_i_7_n_0 + SLICE_X72Y100 LUT6 (Prop_lut6_I1_O) 0.124 56.935 f core_design/yellowWinXOffset[3][2]_i_5/O + net (fo=24, routed) 1.804 58.739 core_design/yellowWinXOffset[3][2]_i_5_n_0 + SLICE_X66Y99 LUT4 (Prop_lut4_I2_O) 0.152 58.891 f core_design/yellowWinXOffset[3][6]_i_16/O + net (fo=2, routed) 0.615 59.506 core_design/yellowWinXOffset[3][6]_i_16_n_0 + SLICE_X70Y101 LUT6 (Prop_lut6_I5_O) 0.348 59.854 f core_design/yellowWinXOffset[6][6]_i_6/O + net (fo=11, routed) 1.304 61.157 core_design/yellowWinXOffset[6][6]_i_6_n_0 + SLICE_X62Y100 LUT6 (Prop_lut6_I0_O) 0.124 61.281 f core_design/yellowWinXOffset[5][6]_i_10/O + net (fo=8, routed) 0.956 62.237 core_design/yellowWinXOffset[5][6]_i_10_n_0 + SLICE_X63Y100 LUT6 (Prop_lut6_I5_O) 0.124 62.361 r core_design/yellowWinXOffset[5][6]_i_3/O + net (fo=1, routed) 0.951 63.313 core_design/yellowWinXOffset[5][6]_i_3_n_0 + SLICE_X63Y104 LUT4 (Prop_lut4_I2_O) 0.124 63.437 r core_design/yellowWinXOffset[5][6]_i_1/O + net (fo=11, routed) 0.647 64.084 core_design/yellowWinXOffset[5][6]_i_1_n_0 + SLICE_X66Y104 FDCE r core_design/yellowWinYOffset_reg[5][1]/CE ------------------------------------------------------------------- ------------------- Slack: inf - Source: pixY_reg[2]/C - (rising edge-triggered cell FDRE) - Destination: genblk1[19].red_piece_gfx/valid_reg/D + Source: core_design/board_reg[29][0]/C + (rising edge-triggered cell FDCE) + Destination: core_design/yellowWinYOffset_reg[5][2]/CE Path Group: (none) Path Type: Max at Slow Process Corner - Data Path Delay: 10.399ns (logic 1.878ns (18.060%) route 8.521ns (81.940%)) - Logic Levels: 6 (CARRY4=1 FDRE=1 LUT1=1 LUT6=3) + Data Path Delay: 64.084ns (logic 10.806ns (16.862%) route 53.278ns (83.138%)) + Logic Levels: 50 (CARRY4=6 FDCE=1 LUT1=1 LUT2=2 LUT3=2 LUT4=5 LUT5=8 LUT6=23 MUXF7=2) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - SLICE_X73Y152 FDRE 0.000 0.000 r pixY_reg[2]/C - SLICE_X73Y152 FDRE (Prop_fdre_C_Q) 0.419 0.419 f pixY_reg[2]/Q - net (fo=186, routed) 5.271 5.690 genblk1[1].red_piece_gfx/Q[0] - SLICE_X84Y141 LUT1 (Prop_lut1_I0_O) 0.296 5.986 r genblk1[1].red_piece_gfx/paletteIndex[1]_i_10__3/O - net (fo=1, routed) 0.000 5.986 genblk1[1].red_piece_gfx/paletteIndex[1]_i_10__3_n_0 - SLICE_X84Y141 CARRY4 (Prop_carry4_S[0]_O[3]) - 0.608 6.594 r genblk1[1].red_piece_gfx/paletteIndex_reg[1]_i_5__0/O[3] - net (fo=21, routed) 1.720 8.314 genblk1[19].red_piece_gfx/O[2] - SLICE_X85Y136 LUT6 (Prop_lut6_I1_O) 0.307 8.621 f genblk1[19].red_piece_gfx/paletteIndex[0]_i_2__14/O - net (fo=1, routed) 0.877 9.497 genblk1[19].red_piece_gfx/paletteIndex[0]_i_2__14_n_0 - SLICE_X85Y136 LUT6 (Prop_lut6_I1_O) 0.124 9.621 f genblk1[19].red_piece_gfx/paletteIndex[0]_i_1__18/O - net (fo=2, routed) 0.654 10.275 board_gfx/valid_reg_45[0] - SLICE_X83Y137 LUT6 (Prop_lut6_I4_O) 0.124 10.399 r board_gfx/valid_i_1__36/O - net (fo=1, routed) 0.000 10.399 genblk1[19].red_piece_gfx/valid_reg_1 - SLICE_X83Y137 FDRE r genblk1[19].red_piece_gfx/valid_reg/D + SLICE_X12Y150 FDCE 0.000 0.000 r core_design/board_reg[29][0]/C + SLICE_X12Y150 FDCE (Prop_fdce_C_Q) 0.518 0.518 r core_design/board_reg[29][0]/Q + net (fo=171, routed) 6.704 7.222 core_design/board_reg_n_0_[29][0] + SLICE_X47Y111 LUT2 (Prop_lut2_I0_O) 0.124 7.346 r core_design/showYellowWinIndicator[4]_i_200/O + net (fo=49, routed) 1.983 9.329 core_design/checkWinsYellow.(null)[2].(null)[5].c[0] + SLICE_X32Y109 LUT5 (Prop_lut5_I4_O) 0.124 9.453 r core_design/yellowWinXOffset[0][4]_i_874/O + net (fo=1, routed) 0.000 9.453 core_design/yellowWinXOffset[0][4]_i_874_n_0 + SLICE_X32Y109 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 10.003 r core_design/yellowWinXOffset_reg[0][4]_i_778/CO[3] + net (fo=1, routed) 0.000 10.003 core_design/yellowWinXOffset_reg[0][4]_i_778_n_0 + SLICE_X32Y110 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 10.225 r core_design/yellowWinXOffset_reg[0][4]_i_779/O[0] + net (fo=3, routed) 0.810 11.035 core_design/yellowWinXOffset_reg[0][4]_i_779_n_7 + SLICE_X33Y109 LUT4 (Prop_lut4_I1_O) 0.329 11.364 r core_design/yellowWinXOffset[0][4]_i_869/O + net (fo=4, routed) 1.007 12.370 core_design/yellowWinXOffset[0][4]_i_869_n_0 + SLICE_X33Y110 LUT3 (Prop_lut3_I1_O) 0.327 12.697 f core_design/yellowWinXOffset[0][4]_i_777/O + net (fo=1, routed) 0.000 12.697 core_design/yellowWinXOffset[0][4]_i_777_n_0 + SLICE_X33Y110 MUXF7 (Prop_muxf7_I1_O) 0.217 12.914 f core_design/yellowWinXOffset_reg[0][4]_i_625/O + net (fo=1, routed) 0.436 13.350 core_design/yellowWinXOffset_reg[0][4]_i_625_n_0 + SLICE_X33Y110 LUT5 (Prop_lut5_I2_O) 0.299 13.649 r core_design/yellowWinXOffset[0][4]_i_489/O + net (fo=9, routed) 0.806 14.455 core_design/yellowWinXOffset[0][4]_i_489_n_0 + SLICE_X38Y112 LUT6 (Prop_lut6_I5_O) 0.124 14.579 f core_design/yellowWinXOffset[0][4]_i_935/O + net (fo=4, routed) 0.632 15.211 core_design/yellowWinXOffset[0][4]_i_935_n_0 + SLICE_X33Y111 LUT1 (Prop_lut1_I0_O) 0.124 15.335 r core_design/yellowWinXOffset[0][4]_i_933/O + net (fo=1, routed) 0.000 15.335 core_design/yellowWinXOffset[0][4]_i_933_n_0 + SLICE_X33Y111 CARRY4 (Prop_carry4_S[1]_O[2]) + 0.580 15.915 r core_design/yellowWinXOffset_reg[0][4]_i_876/O[2] + net (fo=2, routed) 0.817 16.732 core_design/checkWinsYellow.(null)[0].(null)[5].count5[2] + SLICE_X32Y111 LUT5 (Prop_lut5_I4_O) 0.302 17.034 r core_design/yellowWinXOffset[0][4]_i_877/O + net (fo=1, routed) 0.000 17.034 core_design/yellowWinXOffset[0][4]_i_877_n_0 + SLICE_X32Y111 CARRY4 (Prop_carry4_S[2]_CO[3]) + 0.398 17.432 r core_design/yellowWinXOffset_reg[0][4]_i_780/CO[3] + net (fo=1, routed) 0.000 17.432 core_design/yellowWinXOffset_reg[0][4]_i_780_n_0 + SLICE_X32Y112 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 17.766 f core_design/yellowWinXOffset_reg[0][4]_i_781/O[1] + net (fo=4, routed) 0.675 18.441 core_design/yellowWinXOffset_reg[0][4]_i_781_n_6 + SLICE_X31Y111 LUT6 (Prop_lut6_I0_O) 0.303 18.744 r core_design/yellowWinXOffset[0][4]_i_785/O + net (fo=8, routed) 1.306 20.050 core_design/yellowWinXOffset[0][4]_i_785_n_0 + SLICE_X34Y114 LUT5 (Prop_lut5_I2_O) 0.124 20.174 f core_design/yellowWinXOffset[0][4]_i_882/O + net (fo=1, routed) 0.165 20.339 core_design/yellowWinXOffset[0][4]_i_882_n_0 + SLICE_X34Y114 LUT6 (Prop_lut6_I0_O) 0.124 20.463 r core_design/yellowWinXOffset[0][4]_i_782/O + net (fo=1, routed) 1.040 21.503 core_design/yellowWinXOffset[0][4]_i_782_n_0 + SLICE_X33Y113 LUT6 (Prop_lut6_I0_O) 0.124 21.627 r core_design/yellowWinXOffset[0][4]_i_628/O + net (fo=1, routed) 0.000 21.627 core_design/yellowWinXOffset[0][4]_i_628_n_0 + SLICE_X33Y113 MUXF7 (Prop_muxf7_I0_O) 0.212 21.839 r core_design/yellowWinXOffset_reg[0][4]_i_490/O + net (fo=3, routed) 1.185 23.024 core_design/yellowWinXOffset_reg[0][4]_i_490_n_0 + SLICE_X38Y112 LUT6 (Prop_lut6_I4_O) 0.299 23.323 r core_design/yellowWinXOffset[0][4]_i_361/O + net (fo=1, routed) 0.517 23.840 core_design/yellowWinXOffset[0][4]_i_361_n_0 + SLICE_X40Y112 CARRY4 (Prop_carry4_DI[0]_CO[1]) + 0.465 24.305 r core_design/yellowWinXOffset_reg[0][4]_i_249/CO[1] + net (fo=1, routed) 0.816 25.121 core_design/yellowWinXOffset_reg[0][4]_i_249_n_2 + SLICE_X41Y113 LUT6 (Prop_lut6_I4_O) 0.329 25.450 r core_design/yellowWinXOffset[0][4]_i_150/O + net (fo=15, routed) 2.286 27.736 core_design/showYellowWinIndicator1102_out + SLICE_X34Y90 LUT6 (Prop_lut6_I0_O) 0.124 27.860 r core_design/yellowWinXOffset[0][4]_i_138/O + net (fo=49, routed) 1.812 29.672 core_design/yellowWinXOffset[0][4]_i_138_n_0 + SLICE_X36Y87 LUT5 (Prop_lut5_I2_O) 0.150 29.822 r core_design/yellowWinXOffset[0][5]_i_123/O + net (fo=16, routed) 1.018 30.840 core_design/yellowWinXOffset[0][5]_i_123_n_0 + SLICE_X34Y89 LUT5 (Prop_lut5_I4_O) 0.326 31.166 f core_design/yellowWinXOffset[0][5]_i_125/O + net (fo=4, routed) 0.746 31.911 core_design/yellowWinXOffset[0][5]_i_125_n_0 + SLICE_X35Y88 LUT6 (Prop_lut6_I4_O) 0.124 32.035 r core_design/yellowWinXOffset[0][5]_i_57/O + net (fo=33, routed) 1.169 33.204 core_design/yellowWinXOffset[0][5]_i_57_n_0 + SLICE_X38Y88 LUT6 (Prop_lut6_I2_O) 0.124 33.328 r core_design/showYellowWinIndicator[1]_i_25/O + net (fo=39, routed) 2.027 35.355 core_design/showYellowWinIndicator[1]_i_25_n_0 + SLICE_X44Y96 LUT6 (Prop_lut6_I5_O) 0.124 35.479 r core_design/showYellowWinIndicator[1]_i_14/O + net (fo=25, routed) 0.868 36.347 core_design/showYellowWinIndicator[1]_i_14_n_0 + SLICE_X44Y95 LUT6 (Prop_lut6_I0_O) 0.124 36.471 r core_design/showYellowWinIndicator[6]_i_93/O + net (fo=17, routed) 1.048 37.519 core_design/showYellowWinIndicator[6]_i_93_n_0 + SLICE_X48Y90 LUT6 (Prop_lut6_I0_O) 0.124 37.643 r core_design/showYellowWinIndicator[6]_i_39/O + net (fo=21, routed) 1.768 39.412 core_design/showYellowWinIndicator[6]_i_39_n_0 + SLICE_X48Y97 LUT6 (Prop_lut6_I0_O) 0.124 39.536 f core_design/showYellowWinIndicator[6]_i_17/O + net (fo=20, routed) 1.453 40.988 core_design/showYellowWinIndicator[6]_i_17_n_0 + SLICE_X51Y88 LUT4 (Prop_lut4_I3_O) 0.118 41.106 r core_design/yellowWinXOffset[1][6]_i_255/O + net (fo=5, routed) 0.822 41.929 core_design/yellowWinXOffset[1][6]_i_255_n_0 + SLICE_X52Y87 LUT2 (Prop_lut2_I1_O) 0.326 42.255 r core_design/yellowWinXOffset[1][6]_i_201/O + net (fo=16, routed) 1.340 43.595 core_design/yellowWinXOffset[1][6]_i_201_n_0 + SLICE_X57Y84 LUT6 (Prop_lut6_I2_O) 0.124 43.719 r core_design/yellowWinXOffset[0][5]_i_90/O + net (fo=8, routed) 1.736 45.454 core_design/yellowWinXOffset[0][5]_i_90_n_0 + SLICE_X57Y88 LUT4 (Prop_lut4_I3_O) 0.124 45.578 r core_design/yellowWinXOffset[0][6]_i_239/O + net (fo=5, routed) 1.473 47.052 core_design/yellowWinXOffset[0][6]_i_239_n_0 + SLICE_X61Y86 LUT6 (Prop_lut6_I3_O) 0.124 47.176 r core_design/yellowWinXOffset[4][4]_i_52/O + net (fo=3, routed) 1.190 48.366 core_design/yellowWinXOffset[4][4]_i_52_n_0 + SLICE_X62Y88 LUT6 (Prop_lut6_I0_O) 0.124 48.490 r core_design/yellowWinXOffset[6][5]_i_54/O + net (fo=3, routed) 0.671 49.161 core_design/yellowWinXOffset[6][5]_i_54_n_0 + SLICE_X64Y87 LUT5 (Prop_lut5_I2_O) 0.124 49.285 f core_design/yellowWinXOffset[6][5]_i_25/O + net (fo=30, routed) 1.171 50.456 core_design/yellowWinXOffset[6][5]_i_25_n_0 + SLICE_X66Y86 LUT6 (Prop_lut6_I5_O) 0.124 50.580 r core_design/yellowWinXOffset[4][4]_i_21/O + net (fo=8, routed) 1.044 51.624 core_design/yellowWinXOffset[4][4]_i_21_n_0 + SLICE_X68Y90 LUT5 (Prop_lut5_I0_O) 0.124 51.748 f core_design/yellowWinXOffset[1][6]_i_81/O + net (fo=12, routed) 1.020 52.768 core_design/yellowWinXOffset[1][6]_i_81_n_0 + SLICE_X69Y94 LUT3 (Prop_lut3_I0_O) 0.152 52.920 r core_design/yellowWinXOffset[6][5]_i_64/O + net (fo=3, routed) 0.440 53.360 core_design/yellowWinXOffset[6][5]_i_64_n_0 + SLICE_X70Y94 LUT6 (Prop_lut6_I5_O) 0.326 53.686 r core_design/yellowWinYOffset[4][6]_i_57/O + net (fo=14, routed) 1.810 55.496 core_design/yellowWinYOffset[4][6]_i_57_n_0 + SLICE_X72Y98 LUT6 (Prop_lut6_I4_O) 0.124 55.620 r core_design/yellowWinXOffset[3][2]_i_7/O + net (fo=2, routed) 1.191 56.811 core_design/yellowWinXOffset[3][2]_i_7_n_0 + SLICE_X72Y100 LUT6 (Prop_lut6_I1_O) 0.124 56.935 f core_design/yellowWinXOffset[3][2]_i_5/O + net (fo=24, routed) 1.804 58.739 core_design/yellowWinXOffset[3][2]_i_5_n_0 + SLICE_X66Y99 LUT4 (Prop_lut4_I2_O) 0.152 58.891 f core_design/yellowWinXOffset[3][6]_i_16/O + net (fo=2, routed) 0.615 59.506 core_design/yellowWinXOffset[3][6]_i_16_n_0 + SLICE_X70Y101 LUT6 (Prop_lut6_I5_O) 0.348 59.854 f core_design/yellowWinXOffset[6][6]_i_6/O + net (fo=11, routed) 1.304 61.157 core_design/yellowWinXOffset[6][6]_i_6_n_0 + SLICE_X62Y100 LUT6 (Prop_lut6_I0_O) 0.124 61.281 f core_design/yellowWinXOffset[5][6]_i_10/O + net (fo=8, routed) 0.956 62.237 core_design/yellowWinXOffset[5][6]_i_10_n_0 + SLICE_X63Y100 LUT6 (Prop_lut6_I5_O) 0.124 62.361 r core_design/yellowWinXOffset[5][6]_i_3/O + net (fo=1, routed) 0.951 63.313 core_design/yellowWinXOffset[5][6]_i_3_n_0 + SLICE_X63Y104 LUT4 (Prop_lut4_I2_O) 0.124 63.437 r core_design/yellowWinXOffset[5][6]_i_1/O + net (fo=11, routed) 0.647 64.084 core_design/yellowWinXOffset[5][6]_i_1_n_0 + SLICE_X66Y104 FDCE r core_design/yellowWinYOffset_reg[5][2]/CE ------------------------------------------------------------------- ------------------- Slack: inf - Source: pixY_reg[2]/C - (rising edge-triggered cell FDRE) - Destination: genblk1[1].red_piece_gfx/valid_reg/D + Source: core_design/board_reg[29][0]/C + (rising edge-triggered cell FDCE) + Destination: core_design/yellowWinYOffset_reg[5][3]/CE Path Group: (none) Path Type: Max at Slow Process Corner - Data Path Delay: 10.260ns (logic 1.878ns (18.304%) route 8.382ns (81.696%)) - Logic Levels: 6 (CARRY4=1 FDRE=1 LUT1=1 LUT6=3) + Data Path Delay: 64.084ns (logic 10.806ns (16.862%) route 53.278ns (83.138%)) + Logic Levels: 50 (CARRY4=6 FDCE=1 LUT1=1 LUT2=2 LUT3=2 LUT4=5 LUT5=8 LUT6=23 MUXF7=2) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - SLICE_X73Y152 FDRE 0.000 0.000 r pixY_reg[2]/C - SLICE_X73Y152 FDRE (Prop_fdre_C_Q) 0.419 0.419 f pixY_reg[2]/Q - net (fo=186, routed) 5.271 5.690 genblk1[1].red_piece_gfx/Q[0] - SLICE_X84Y141 LUT1 (Prop_lut1_I0_O) 0.296 5.986 r genblk1[1].red_piece_gfx/paletteIndex[1]_i_10__3/O - net (fo=1, routed) 0.000 5.986 genblk1[1].red_piece_gfx/paletteIndex[1]_i_10__3_n_0 - SLICE_X84Y141 CARRY4 (Prop_carry4_S[0]_O[3]) - 0.608 6.594 r genblk1[1].red_piece_gfx/paletteIndex_reg[1]_i_5__0/O[3] - net (fo=21, routed) 1.333 7.927 genblk1[1].red_piece_gfx/O[2] - SLICE_X86Y138 LUT6 (Prop_lut6_I1_O) 0.307 8.234 f genblk1[1].red_piece_gfx/paletteIndex[1]_i_3__0/O - net (fo=1, routed) 0.972 9.206 genblk1[1].red_piece_gfx/paletteIndex[1]_i_3__0_n_0 - SLICE_X87Y138 LUT6 (Prop_lut6_I1_O) 0.124 9.330 f genblk1[1].red_piece_gfx/paletteIndex[1]_i_1__0/O - net (fo=2, routed) 0.806 10.136 board_gfx/valid_reg_47[1] - SLICE_X87Y137 LUT6 (Prop_lut6_I3_O) 0.124 10.260 r board_gfx/valid_i_1__39/O - net (fo=1, routed) 0.000 10.260 genblk1[1].red_piece_gfx/valid_reg_1 - SLICE_X87Y137 FDRE r genblk1[1].red_piece_gfx/valid_reg/D + SLICE_X12Y150 FDCE 0.000 0.000 r core_design/board_reg[29][0]/C + SLICE_X12Y150 FDCE (Prop_fdce_C_Q) 0.518 0.518 r core_design/board_reg[29][0]/Q + net (fo=171, routed) 6.704 7.222 core_design/board_reg_n_0_[29][0] + SLICE_X47Y111 LUT2 (Prop_lut2_I0_O) 0.124 7.346 r core_design/showYellowWinIndicator[4]_i_200/O + net (fo=49, routed) 1.983 9.329 core_design/checkWinsYellow.(null)[2].(null)[5].c[0] + SLICE_X32Y109 LUT5 (Prop_lut5_I4_O) 0.124 9.453 r core_design/yellowWinXOffset[0][4]_i_874/O + net (fo=1, routed) 0.000 9.453 core_design/yellowWinXOffset[0][4]_i_874_n_0 + SLICE_X32Y109 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 10.003 r core_design/yellowWinXOffset_reg[0][4]_i_778/CO[3] + net (fo=1, routed) 0.000 10.003 core_design/yellowWinXOffset_reg[0][4]_i_778_n_0 + SLICE_X32Y110 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 10.225 r core_design/yellowWinXOffset_reg[0][4]_i_779/O[0] + net (fo=3, routed) 0.810 11.035 core_design/yellowWinXOffset_reg[0][4]_i_779_n_7 + SLICE_X33Y109 LUT4 (Prop_lut4_I1_O) 0.329 11.364 r core_design/yellowWinXOffset[0][4]_i_869/O + net (fo=4, routed) 1.007 12.370 core_design/yellowWinXOffset[0][4]_i_869_n_0 + SLICE_X33Y110 LUT3 (Prop_lut3_I1_O) 0.327 12.697 f core_design/yellowWinXOffset[0][4]_i_777/O + net (fo=1, routed) 0.000 12.697 core_design/yellowWinXOffset[0][4]_i_777_n_0 + SLICE_X33Y110 MUXF7 (Prop_muxf7_I1_O) 0.217 12.914 f core_design/yellowWinXOffset_reg[0][4]_i_625/O + net (fo=1, routed) 0.436 13.350 core_design/yellowWinXOffset_reg[0][4]_i_625_n_0 + SLICE_X33Y110 LUT5 (Prop_lut5_I2_O) 0.299 13.649 r core_design/yellowWinXOffset[0][4]_i_489/O + net (fo=9, routed) 0.806 14.455 core_design/yellowWinXOffset[0][4]_i_489_n_0 + SLICE_X38Y112 LUT6 (Prop_lut6_I5_O) 0.124 14.579 f core_design/yellowWinXOffset[0][4]_i_935/O + net (fo=4, routed) 0.632 15.211 core_design/yellowWinXOffset[0][4]_i_935_n_0 + SLICE_X33Y111 LUT1 (Prop_lut1_I0_O) 0.124 15.335 r core_design/yellowWinXOffset[0][4]_i_933/O + net (fo=1, routed) 0.000 15.335 core_design/yellowWinXOffset[0][4]_i_933_n_0 + SLICE_X33Y111 CARRY4 (Prop_carry4_S[1]_O[2]) + 0.580 15.915 r core_design/yellowWinXOffset_reg[0][4]_i_876/O[2] + net (fo=2, routed) 0.817 16.732 core_design/checkWinsYellow.(null)[0].(null)[5].count5[2] + SLICE_X32Y111 LUT5 (Prop_lut5_I4_O) 0.302 17.034 r core_design/yellowWinXOffset[0][4]_i_877/O + net (fo=1, routed) 0.000 17.034 core_design/yellowWinXOffset[0][4]_i_877_n_0 + SLICE_X32Y111 CARRY4 (Prop_carry4_S[2]_CO[3]) + 0.398 17.432 r core_design/yellowWinXOffset_reg[0][4]_i_780/CO[3] + net (fo=1, routed) 0.000 17.432 core_design/yellowWinXOffset_reg[0][4]_i_780_n_0 + SLICE_X32Y112 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 17.766 f core_design/yellowWinXOffset_reg[0][4]_i_781/O[1] + net (fo=4, routed) 0.675 18.441 core_design/yellowWinXOffset_reg[0][4]_i_781_n_6 + SLICE_X31Y111 LUT6 (Prop_lut6_I0_O) 0.303 18.744 r core_design/yellowWinXOffset[0][4]_i_785/O + net (fo=8, routed) 1.306 20.050 core_design/yellowWinXOffset[0][4]_i_785_n_0 + SLICE_X34Y114 LUT5 (Prop_lut5_I2_O) 0.124 20.174 f core_design/yellowWinXOffset[0][4]_i_882/O + net (fo=1, routed) 0.165 20.339 core_design/yellowWinXOffset[0][4]_i_882_n_0 + SLICE_X34Y114 LUT6 (Prop_lut6_I0_O) 0.124 20.463 r core_design/yellowWinXOffset[0][4]_i_782/O + net (fo=1, routed) 1.040 21.503 core_design/yellowWinXOffset[0][4]_i_782_n_0 + SLICE_X33Y113 LUT6 (Prop_lut6_I0_O) 0.124 21.627 r core_design/yellowWinXOffset[0][4]_i_628/O + net (fo=1, routed) 0.000 21.627 core_design/yellowWinXOffset[0][4]_i_628_n_0 + SLICE_X33Y113 MUXF7 (Prop_muxf7_I0_O) 0.212 21.839 r core_design/yellowWinXOffset_reg[0][4]_i_490/O + net (fo=3, routed) 1.185 23.024 core_design/yellowWinXOffset_reg[0][4]_i_490_n_0 + SLICE_X38Y112 LUT6 (Prop_lut6_I4_O) 0.299 23.323 r core_design/yellowWinXOffset[0][4]_i_361/O + net (fo=1, routed) 0.517 23.840 core_design/yellowWinXOffset[0][4]_i_361_n_0 + SLICE_X40Y112 CARRY4 (Prop_carry4_DI[0]_CO[1]) + 0.465 24.305 r core_design/yellowWinXOffset_reg[0][4]_i_249/CO[1] + net (fo=1, routed) 0.816 25.121 core_design/yellowWinXOffset_reg[0][4]_i_249_n_2 + SLICE_X41Y113 LUT6 (Prop_lut6_I4_O) 0.329 25.450 r core_design/yellowWinXOffset[0][4]_i_150/O + net (fo=15, routed) 2.286 27.736 core_design/showYellowWinIndicator1102_out + SLICE_X34Y90 LUT6 (Prop_lut6_I0_O) 0.124 27.860 r core_design/yellowWinXOffset[0][4]_i_138/O + net (fo=49, routed) 1.812 29.672 core_design/yellowWinXOffset[0][4]_i_138_n_0 + SLICE_X36Y87 LUT5 (Prop_lut5_I2_O) 0.150 29.822 r core_design/yellowWinXOffset[0][5]_i_123/O + net (fo=16, routed) 1.018 30.840 core_design/yellowWinXOffset[0][5]_i_123_n_0 + SLICE_X34Y89 LUT5 (Prop_lut5_I4_O) 0.326 31.166 f core_design/yellowWinXOffset[0][5]_i_125/O + net (fo=4, routed) 0.746 31.911 core_design/yellowWinXOffset[0][5]_i_125_n_0 + SLICE_X35Y88 LUT6 (Prop_lut6_I4_O) 0.124 32.035 r core_design/yellowWinXOffset[0][5]_i_57/O + net (fo=33, routed) 1.169 33.204 core_design/yellowWinXOffset[0][5]_i_57_n_0 + SLICE_X38Y88 LUT6 (Prop_lut6_I2_O) 0.124 33.328 r core_design/showYellowWinIndicator[1]_i_25/O + net (fo=39, routed) 2.027 35.355 core_design/showYellowWinIndicator[1]_i_25_n_0 + SLICE_X44Y96 LUT6 (Prop_lut6_I5_O) 0.124 35.479 r core_design/showYellowWinIndicator[1]_i_14/O + net (fo=25, routed) 0.868 36.347 core_design/showYellowWinIndicator[1]_i_14_n_0 + SLICE_X44Y95 LUT6 (Prop_lut6_I0_O) 0.124 36.471 r core_design/showYellowWinIndicator[6]_i_93/O + net (fo=17, routed) 1.048 37.519 core_design/showYellowWinIndicator[6]_i_93_n_0 + SLICE_X48Y90 LUT6 (Prop_lut6_I0_O) 0.124 37.643 r core_design/showYellowWinIndicator[6]_i_39/O + net (fo=21, routed) 1.768 39.412 core_design/showYellowWinIndicator[6]_i_39_n_0 + SLICE_X48Y97 LUT6 (Prop_lut6_I0_O) 0.124 39.536 f core_design/showYellowWinIndicator[6]_i_17/O + net (fo=20, routed) 1.453 40.988 core_design/showYellowWinIndicator[6]_i_17_n_0 + SLICE_X51Y88 LUT4 (Prop_lut4_I3_O) 0.118 41.106 r core_design/yellowWinXOffset[1][6]_i_255/O + net (fo=5, routed) 0.822 41.929 core_design/yellowWinXOffset[1][6]_i_255_n_0 + SLICE_X52Y87 LUT2 (Prop_lut2_I1_O) 0.326 42.255 r core_design/yellowWinXOffset[1][6]_i_201/O + net (fo=16, routed) 1.340 43.595 core_design/yellowWinXOffset[1][6]_i_201_n_0 + SLICE_X57Y84 LUT6 (Prop_lut6_I2_O) 0.124 43.719 r core_design/yellowWinXOffset[0][5]_i_90/O + net (fo=8, routed) 1.736 45.454 core_design/yellowWinXOffset[0][5]_i_90_n_0 + SLICE_X57Y88 LUT4 (Prop_lut4_I3_O) 0.124 45.578 r core_design/yellowWinXOffset[0][6]_i_239/O + net (fo=5, routed) 1.473 47.052 core_design/yellowWinXOffset[0][6]_i_239_n_0 + SLICE_X61Y86 LUT6 (Prop_lut6_I3_O) 0.124 47.176 r core_design/yellowWinXOffset[4][4]_i_52/O + net (fo=3, routed) 1.190 48.366 core_design/yellowWinXOffset[4][4]_i_52_n_0 + SLICE_X62Y88 LUT6 (Prop_lut6_I0_O) 0.124 48.490 r core_design/yellowWinXOffset[6][5]_i_54/O + net (fo=3, routed) 0.671 49.161 core_design/yellowWinXOffset[6][5]_i_54_n_0 + SLICE_X64Y87 LUT5 (Prop_lut5_I2_O) 0.124 49.285 f core_design/yellowWinXOffset[6][5]_i_25/O + net (fo=30, routed) 1.171 50.456 core_design/yellowWinXOffset[6][5]_i_25_n_0 + SLICE_X66Y86 LUT6 (Prop_lut6_I5_O) 0.124 50.580 r core_design/yellowWinXOffset[4][4]_i_21/O + net (fo=8, routed) 1.044 51.624 core_design/yellowWinXOffset[4][4]_i_21_n_0 + SLICE_X68Y90 LUT5 (Prop_lut5_I0_O) 0.124 51.748 f core_design/yellowWinXOffset[1][6]_i_81/O + net (fo=12, routed) 1.020 52.768 core_design/yellowWinXOffset[1][6]_i_81_n_0 + SLICE_X69Y94 LUT3 (Prop_lut3_I0_O) 0.152 52.920 r core_design/yellowWinXOffset[6][5]_i_64/O + net (fo=3, routed) 0.440 53.360 core_design/yellowWinXOffset[6][5]_i_64_n_0 + SLICE_X70Y94 LUT6 (Prop_lut6_I5_O) 0.326 53.686 r core_design/yellowWinYOffset[4][6]_i_57/O + net (fo=14, routed) 1.810 55.496 core_design/yellowWinYOffset[4][6]_i_57_n_0 + SLICE_X72Y98 LUT6 (Prop_lut6_I4_O) 0.124 55.620 r core_design/yellowWinXOffset[3][2]_i_7/O + net (fo=2, routed) 1.191 56.811 core_design/yellowWinXOffset[3][2]_i_7_n_0 + SLICE_X72Y100 LUT6 (Prop_lut6_I1_O) 0.124 56.935 f core_design/yellowWinXOffset[3][2]_i_5/O + net (fo=24, routed) 1.804 58.739 core_design/yellowWinXOffset[3][2]_i_5_n_0 + SLICE_X66Y99 LUT4 (Prop_lut4_I2_O) 0.152 58.891 f core_design/yellowWinXOffset[3][6]_i_16/O + net (fo=2, routed) 0.615 59.506 core_design/yellowWinXOffset[3][6]_i_16_n_0 + SLICE_X70Y101 LUT6 (Prop_lut6_I5_O) 0.348 59.854 f core_design/yellowWinXOffset[6][6]_i_6/O + net (fo=11, routed) 1.304 61.157 core_design/yellowWinXOffset[6][6]_i_6_n_0 + SLICE_X62Y100 LUT6 (Prop_lut6_I0_O) 0.124 61.281 f core_design/yellowWinXOffset[5][6]_i_10/O + net (fo=8, routed) 0.956 62.237 core_design/yellowWinXOffset[5][6]_i_10_n_0 + SLICE_X63Y100 LUT6 (Prop_lut6_I5_O) 0.124 62.361 r core_design/yellowWinXOffset[5][6]_i_3/O + net (fo=1, routed) 0.951 63.313 core_design/yellowWinXOffset[5][6]_i_3_n_0 + SLICE_X63Y104 LUT4 (Prop_lut4_I2_O) 0.124 63.437 r core_design/yellowWinXOffset[5][6]_i_1/O + net (fo=11, routed) 0.647 64.084 core_design/yellowWinXOffset[5][6]_i_1_n_0 + SLICE_X66Y104 FDCE r core_design/yellowWinYOffset_reg[5][3]/CE ------------------------------------------------------------------- ------------------- Slack: inf - Source: pixY_reg[2]/C - (rising edge-triggered cell FDRE) - Destination: genblk1[4].red_piece_gfx/valid_reg/D + Source: core_design/board_reg[29][0]/C + (rising edge-triggered cell FDCE) + Destination: core_design/yellowWinYOffset_reg[5][6]/CE Path Group: (none) Path Type: Max at Slow Process Corner - Data Path Delay: 10.143ns (logic 1.878ns (18.515%) route 8.265ns (81.485%)) - Logic Levels: 5 (CARRY4=1 FDRE=1 LUT6=3) + Data Path Delay: 64.084ns (logic 10.806ns (16.862%) route 53.278ns (83.138%)) + Logic Levels: 50 (CARRY4=6 FDCE=1 LUT1=1 LUT2=2 LUT3=2 LUT4=5 LUT5=8 LUT6=23 MUXF7=2) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - SLICE_X73Y152 FDRE 0.000 0.000 r pixY_reg[2]/C - SLICE_X73Y152 FDRE (Prop_fdre_C_Q) 0.419 0.419 r pixY_reg[2]/Q - net (fo=186, routed) 5.290 5.709 genblk1[4].red_piece_gfx/Q[0] - SLICE_X84Y132 CARRY4 (Prop_carry4_S[0]_O[3]) - 0.904 6.613 r genblk1[4].red_piece_gfx/paletteIndex_reg[1]_i_6/O[3] - net (fo=16, routed) 1.178 7.791 genblk1[4].red_piece_gfx/pixY_reg[5][2] - SLICE_X83Y130 LUT6 (Prop_lut6_I1_O) 0.307 8.098 f genblk1[4].red_piece_gfx/paletteIndex[0]_i_3__1/O - net (fo=1, routed) 0.989 9.087 genblk1[4].red_piece_gfx/paletteIndex[0]_i_3__1_n_0 - SLICE_X83Y131 LUT6 (Prop_lut6_I1_O) 0.124 9.211 f genblk1[4].red_piece_gfx/paletteIndex[0]_i_1__3/O - net (fo=2, routed) 0.808 10.019 board_gfx/valid_reg_32[0] - SLICE_X84Y131 LUT6 (Prop_lut6_I4_O) 0.124 10.143 r board_gfx/valid_i_1__28/O - net (fo=1, routed) 0.000 10.143 genblk1[4].red_piece_gfx/valid_reg_3 - SLICE_X84Y131 FDRE r genblk1[4].red_piece_gfx/valid_reg/D + SLICE_X12Y150 FDCE 0.000 0.000 r core_design/board_reg[29][0]/C + SLICE_X12Y150 FDCE (Prop_fdce_C_Q) 0.518 0.518 r core_design/board_reg[29][0]/Q + net (fo=171, routed) 6.704 7.222 core_design/board_reg_n_0_[29][0] + SLICE_X47Y111 LUT2 (Prop_lut2_I0_O) 0.124 7.346 r core_design/showYellowWinIndicator[4]_i_200/O + net (fo=49, routed) 1.983 9.329 core_design/checkWinsYellow.(null)[2].(null)[5].c[0] + SLICE_X32Y109 LUT5 (Prop_lut5_I4_O) 0.124 9.453 r core_design/yellowWinXOffset[0][4]_i_874/O + net (fo=1, routed) 0.000 9.453 core_design/yellowWinXOffset[0][4]_i_874_n_0 + SLICE_X32Y109 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 10.003 r core_design/yellowWinXOffset_reg[0][4]_i_778/CO[3] + net (fo=1, routed) 0.000 10.003 core_design/yellowWinXOffset_reg[0][4]_i_778_n_0 + SLICE_X32Y110 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 10.225 r core_design/yellowWinXOffset_reg[0][4]_i_779/O[0] + net (fo=3, routed) 0.810 11.035 core_design/yellowWinXOffset_reg[0][4]_i_779_n_7 + SLICE_X33Y109 LUT4 (Prop_lut4_I1_O) 0.329 11.364 r core_design/yellowWinXOffset[0][4]_i_869/O + net (fo=4, routed) 1.007 12.370 core_design/yellowWinXOffset[0][4]_i_869_n_0 + SLICE_X33Y110 LUT3 (Prop_lut3_I1_O) 0.327 12.697 f core_design/yellowWinXOffset[0][4]_i_777/O + net (fo=1, routed) 0.000 12.697 core_design/yellowWinXOffset[0][4]_i_777_n_0 + SLICE_X33Y110 MUXF7 (Prop_muxf7_I1_O) 0.217 12.914 f core_design/yellowWinXOffset_reg[0][4]_i_625/O + net (fo=1, routed) 0.436 13.350 core_design/yellowWinXOffset_reg[0][4]_i_625_n_0 + SLICE_X33Y110 LUT5 (Prop_lut5_I2_O) 0.299 13.649 r core_design/yellowWinXOffset[0][4]_i_489/O + net (fo=9, routed) 0.806 14.455 core_design/yellowWinXOffset[0][4]_i_489_n_0 + SLICE_X38Y112 LUT6 (Prop_lut6_I5_O) 0.124 14.579 f core_design/yellowWinXOffset[0][4]_i_935/O + net (fo=4, routed) 0.632 15.211 core_design/yellowWinXOffset[0][4]_i_935_n_0 + SLICE_X33Y111 LUT1 (Prop_lut1_I0_O) 0.124 15.335 r core_design/yellowWinXOffset[0][4]_i_933/O + net (fo=1, routed) 0.000 15.335 core_design/yellowWinXOffset[0][4]_i_933_n_0 + SLICE_X33Y111 CARRY4 (Prop_carry4_S[1]_O[2]) + 0.580 15.915 r core_design/yellowWinXOffset_reg[0][4]_i_876/O[2] + net (fo=2, routed) 0.817 16.732 core_design/checkWinsYellow.(null)[0].(null)[5].count5[2] + SLICE_X32Y111 LUT5 (Prop_lut5_I4_O) 0.302 17.034 r core_design/yellowWinXOffset[0][4]_i_877/O + net (fo=1, routed) 0.000 17.034 core_design/yellowWinXOffset[0][4]_i_877_n_0 + SLICE_X32Y111 CARRY4 (Prop_carry4_S[2]_CO[3]) + 0.398 17.432 r core_design/yellowWinXOffset_reg[0][4]_i_780/CO[3] + net (fo=1, routed) 0.000 17.432 core_design/yellowWinXOffset_reg[0][4]_i_780_n_0 + SLICE_X32Y112 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 17.766 f core_design/yellowWinXOffset_reg[0][4]_i_781/O[1] + net (fo=4, routed) 0.675 18.441 core_design/yellowWinXOffset_reg[0][4]_i_781_n_6 + SLICE_X31Y111 LUT6 (Prop_lut6_I0_O) 0.303 18.744 r core_design/yellowWinXOffset[0][4]_i_785/O + net (fo=8, routed) 1.306 20.050 core_design/yellowWinXOffset[0][4]_i_785_n_0 + SLICE_X34Y114 LUT5 (Prop_lut5_I2_O) 0.124 20.174 f core_design/yellowWinXOffset[0][4]_i_882/O + net (fo=1, routed) 0.165 20.339 core_design/yellowWinXOffset[0][4]_i_882_n_0 + SLICE_X34Y114 LUT6 (Prop_lut6_I0_O) 0.124 20.463 r core_design/yellowWinXOffset[0][4]_i_782/O + net (fo=1, routed) 1.040 21.503 core_design/yellowWinXOffset[0][4]_i_782_n_0 + SLICE_X33Y113 LUT6 (Prop_lut6_I0_O) 0.124 21.627 r core_design/yellowWinXOffset[0][4]_i_628/O + net (fo=1, routed) 0.000 21.627 core_design/yellowWinXOffset[0][4]_i_628_n_0 + SLICE_X33Y113 MUXF7 (Prop_muxf7_I0_O) 0.212 21.839 r core_design/yellowWinXOffset_reg[0][4]_i_490/O + net (fo=3, routed) 1.185 23.024 core_design/yellowWinXOffset_reg[0][4]_i_490_n_0 + SLICE_X38Y112 LUT6 (Prop_lut6_I4_O) 0.299 23.323 r core_design/yellowWinXOffset[0][4]_i_361/O + net (fo=1, routed) 0.517 23.840 core_design/yellowWinXOffset[0][4]_i_361_n_0 + SLICE_X40Y112 CARRY4 (Prop_carry4_DI[0]_CO[1]) + 0.465 24.305 r core_design/yellowWinXOffset_reg[0][4]_i_249/CO[1] + net (fo=1, routed) 0.816 25.121 core_design/yellowWinXOffset_reg[0][4]_i_249_n_2 + SLICE_X41Y113 LUT6 (Prop_lut6_I4_O) 0.329 25.450 r core_design/yellowWinXOffset[0][4]_i_150/O + net (fo=15, routed) 2.286 27.736 core_design/showYellowWinIndicator1102_out + SLICE_X34Y90 LUT6 (Prop_lut6_I0_O) 0.124 27.860 r core_design/yellowWinXOffset[0][4]_i_138/O + net (fo=49, routed) 1.812 29.672 core_design/yellowWinXOffset[0][4]_i_138_n_0 + SLICE_X36Y87 LUT5 (Prop_lut5_I2_O) 0.150 29.822 r core_design/yellowWinXOffset[0][5]_i_123/O + net (fo=16, routed) 1.018 30.840 core_design/yellowWinXOffset[0][5]_i_123_n_0 + SLICE_X34Y89 LUT5 (Prop_lut5_I4_O) 0.326 31.166 f core_design/yellowWinXOffset[0][5]_i_125/O + net (fo=4, routed) 0.746 31.911 core_design/yellowWinXOffset[0][5]_i_125_n_0 + SLICE_X35Y88 LUT6 (Prop_lut6_I4_O) 0.124 32.035 r core_design/yellowWinXOffset[0][5]_i_57/O + net (fo=33, routed) 1.169 33.204 core_design/yellowWinXOffset[0][5]_i_57_n_0 + SLICE_X38Y88 LUT6 (Prop_lut6_I2_O) 0.124 33.328 r core_design/showYellowWinIndicator[1]_i_25/O + net (fo=39, routed) 2.027 35.355 core_design/showYellowWinIndicator[1]_i_25_n_0 + SLICE_X44Y96 LUT6 (Prop_lut6_I5_O) 0.124 35.479 r core_design/showYellowWinIndicator[1]_i_14/O + net (fo=25, routed) 0.868 36.347 core_design/showYellowWinIndicator[1]_i_14_n_0 + SLICE_X44Y95 LUT6 (Prop_lut6_I0_O) 0.124 36.471 r core_design/showYellowWinIndicator[6]_i_93/O + net (fo=17, routed) 1.048 37.519 core_design/showYellowWinIndicator[6]_i_93_n_0 + SLICE_X48Y90 LUT6 (Prop_lut6_I0_O) 0.124 37.643 r core_design/showYellowWinIndicator[6]_i_39/O + net (fo=21, routed) 1.768 39.412 core_design/showYellowWinIndicator[6]_i_39_n_0 + SLICE_X48Y97 LUT6 (Prop_lut6_I0_O) 0.124 39.536 f core_design/showYellowWinIndicator[6]_i_17/O + net (fo=20, routed) 1.453 40.988 core_design/showYellowWinIndicator[6]_i_17_n_0 + SLICE_X51Y88 LUT4 (Prop_lut4_I3_O) 0.118 41.106 r core_design/yellowWinXOffset[1][6]_i_255/O + net (fo=5, routed) 0.822 41.929 core_design/yellowWinXOffset[1][6]_i_255_n_0 + SLICE_X52Y87 LUT2 (Prop_lut2_I1_O) 0.326 42.255 r core_design/yellowWinXOffset[1][6]_i_201/O + net (fo=16, routed) 1.340 43.595 core_design/yellowWinXOffset[1][6]_i_201_n_0 + SLICE_X57Y84 LUT6 (Prop_lut6_I2_O) 0.124 43.719 r core_design/yellowWinXOffset[0][5]_i_90/O + net (fo=8, routed) 1.736 45.454 core_design/yellowWinXOffset[0][5]_i_90_n_0 + SLICE_X57Y88 LUT4 (Prop_lut4_I3_O) 0.124 45.578 r core_design/yellowWinXOffset[0][6]_i_239/O + net (fo=5, routed) 1.473 47.052 core_design/yellowWinXOffset[0][6]_i_239_n_0 + SLICE_X61Y86 LUT6 (Prop_lut6_I3_O) 0.124 47.176 r core_design/yellowWinXOffset[4][4]_i_52/O + net (fo=3, routed) 1.190 48.366 core_design/yellowWinXOffset[4][4]_i_52_n_0 + SLICE_X62Y88 LUT6 (Prop_lut6_I0_O) 0.124 48.490 r core_design/yellowWinXOffset[6][5]_i_54/O + net (fo=3, routed) 0.671 49.161 core_design/yellowWinXOffset[6][5]_i_54_n_0 + SLICE_X64Y87 LUT5 (Prop_lut5_I2_O) 0.124 49.285 f core_design/yellowWinXOffset[6][5]_i_25/O + net (fo=30, routed) 1.171 50.456 core_design/yellowWinXOffset[6][5]_i_25_n_0 + SLICE_X66Y86 LUT6 (Prop_lut6_I5_O) 0.124 50.580 r core_design/yellowWinXOffset[4][4]_i_21/O + net (fo=8, routed) 1.044 51.624 core_design/yellowWinXOffset[4][4]_i_21_n_0 + SLICE_X68Y90 LUT5 (Prop_lut5_I0_O) 0.124 51.748 f core_design/yellowWinXOffset[1][6]_i_81/O + net (fo=12, routed) 1.020 52.768 core_design/yellowWinXOffset[1][6]_i_81_n_0 + SLICE_X69Y94 LUT3 (Prop_lut3_I0_O) 0.152 52.920 r core_design/yellowWinXOffset[6][5]_i_64/O + net (fo=3, routed) 0.440 53.360 core_design/yellowWinXOffset[6][5]_i_64_n_0 + SLICE_X70Y94 LUT6 (Prop_lut6_I5_O) 0.326 53.686 r core_design/yellowWinYOffset[4][6]_i_57/O + net (fo=14, routed) 1.810 55.496 core_design/yellowWinYOffset[4][6]_i_57_n_0 + SLICE_X72Y98 LUT6 (Prop_lut6_I4_O) 0.124 55.620 r core_design/yellowWinXOffset[3][2]_i_7/O + net (fo=2, routed) 1.191 56.811 core_design/yellowWinXOffset[3][2]_i_7_n_0 + SLICE_X72Y100 LUT6 (Prop_lut6_I1_O) 0.124 56.935 f core_design/yellowWinXOffset[3][2]_i_5/O + net (fo=24, routed) 1.804 58.739 core_design/yellowWinXOffset[3][2]_i_5_n_0 + SLICE_X66Y99 LUT4 (Prop_lut4_I2_O) 0.152 58.891 f core_design/yellowWinXOffset[3][6]_i_16/O + net (fo=2, routed) 0.615 59.506 core_design/yellowWinXOffset[3][6]_i_16_n_0 + SLICE_X70Y101 LUT6 (Prop_lut6_I5_O) 0.348 59.854 f core_design/yellowWinXOffset[6][6]_i_6/O + net (fo=11, routed) 1.304 61.157 core_design/yellowWinXOffset[6][6]_i_6_n_0 + SLICE_X62Y100 LUT6 (Prop_lut6_I0_O) 0.124 61.281 f core_design/yellowWinXOffset[5][6]_i_10/O + net (fo=8, routed) 0.956 62.237 core_design/yellowWinXOffset[5][6]_i_10_n_0 + SLICE_X63Y100 LUT6 (Prop_lut6_I5_O) 0.124 62.361 r core_design/yellowWinXOffset[5][6]_i_3/O + net (fo=1, routed) 0.951 63.313 core_design/yellowWinXOffset[5][6]_i_3_n_0 + SLICE_X63Y104 LUT4 (Prop_lut4_I2_O) 0.124 63.437 r core_design/yellowWinXOffset[5][6]_i_1/O + net (fo=11, routed) 0.647 64.084 core_design/yellowWinXOffset[5][6]_i_1_n_0 + SLICE_X66Y104 FDCE r core_design/yellowWinYOffset_reg[5][6]/CE ------------------------------------------------------------------- ------------------- Slack: inf - Source: pixY_reg[2]/C - (rising edge-triggered cell FDRE) - Destination: genblk1[10].red_piece_gfx/valid_reg/D + Source: core_design/board_reg[29][0]/C + (rising edge-triggered cell FDCE) + Destination: core_design/yellowWinYOffset_reg[5][1]/D Path Group: (none) Path Type: Max at Slow Process Corner - Data Path Delay: 9.978ns (logic 1.878ns (18.822%) route 8.100ns (81.178%)) - Logic Levels: 5 (CARRY4=1 FDRE=1 LUT6=3) + Data Path Delay: 63.986ns (logic 11.039ns (17.252%) route 52.947ns (82.748%)) + Logic Levels: 50 (CARRY4=6 FDCE=1 LUT1=1 LUT2=3 LUT3=2 LUT4=4 LUT5=9 LUT6=22 MUXF7=2) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - SLICE_X73Y152 FDRE 0.000 0.000 r pixY_reg[2]/C - SLICE_X73Y152 FDRE (Prop_fdre_C_Q) 0.419 0.419 r pixY_reg[2]/Q - net (fo=186, routed) 5.290 5.709 genblk1[4].red_piece_gfx/Q[0] - SLICE_X84Y132 CARRY4 (Prop_carry4_S[0]_O[3]) - 0.904 6.613 r genblk1[4].red_piece_gfx/paletteIndex_reg[1]_i_6/O[3] - net (fo=16, routed) 1.283 7.895 genblk1[10].red_piece_gfx/y017_out[3] - SLICE_X87Y131 LUT6 (Prop_lut6_I1_O) 0.307 8.202 f genblk1[10].red_piece_gfx/paletteIndex[1]_i_2__2/O - net (fo=1, routed) 0.870 9.073 genblk1[10].red_piece_gfx/paletteIndex[1]_i_2__2_n_0 - SLICE_X86Y131 LUT6 (Prop_lut6_I1_O) 0.124 9.197 f genblk1[10].red_piece_gfx/paletteIndex[1]_i_1__9/O - net (fo=2, routed) 0.657 9.854 board_gfx/valid_reg_31[1] - SLICE_X86Y131 LUT6 (Prop_lut6_I3_O) 0.124 9.978 r board_gfx/valid_i_1__27/O - net (fo=1, routed) 0.000 9.978 genblk1[10].red_piece_gfx/valid_reg_0 - SLICE_X86Y131 FDRE r genblk1[10].red_piece_gfx/valid_reg/D + SLICE_X12Y150 FDCE 0.000 0.000 r core_design/board_reg[29][0]/C + SLICE_X12Y150 FDCE (Prop_fdce_C_Q) 0.518 0.518 r core_design/board_reg[29][0]/Q + net (fo=171, routed) 6.704 7.222 core_design/board_reg_n_0_[29][0] + SLICE_X47Y111 LUT2 (Prop_lut2_I0_O) 0.124 7.346 r core_design/showYellowWinIndicator[4]_i_200/O + net (fo=49, routed) 1.983 9.329 core_design/checkWinsYellow.(null)[2].(null)[5].c[0] + SLICE_X32Y109 LUT5 (Prop_lut5_I4_O) 0.124 9.453 r core_design/yellowWinXOffset[0][4]_i_874/O + net (fo=1, routed) 0.000 9.453 core_design/yellowWinXOffset[0][4]_i_874_n_0 + SLICE_X32Y109 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 10.003 r core_design/yellowWinXOffset_reg[0][4]_i_778/CO[3] + net (fo=1, routed) 0.000 10.003 core_design/yellowWinXOffset_reg[0][4]_i_778_n_0 + SLICE_X32Y110 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 10.225 r core_design/yellowWinXOffset_reg[0][4]_i_779/O[0] + net (fo=3, routed) 0.810 11.035 core_design/yellowWinXOffset_reg[0][4]_i_779_n_7 + SLICE_X33Y109 LUT4 (Prop_lut4_I1_O) 0.329 11.364 r core_design/yellowWinXOffset[0][4]_i_869/O + net (fo=4, routed) 1.007 12.370 core_design/yellowWinXOffset[0][4]_i_869_n_0 + SLICE_X33Y110 LUT3 (Prop_lut3_I1_O) 0.327 12.697 f core_design/yellowWinXOffset[0][4]_i_777/O + net (fo=1, routed) 0.000 12.697 core_design/yellowWinXOffset[0][4]_i_777_n_0 + SLICE_X33Y110 MUXF7 (Prop_muxf7_I1_O) 0.217 12.914 f core_design/yellowWinXOffset_reg[0][4]_i_625/O + net (fo=1, routed) 0.436 13.350 core_design/yellowWinXOffset_reg[0][4]_i_625_n_0 + SLICE_X33Y110 LUT5 (Prop_lut5_I2_O) 0.299 13.649 r core_design/yellowWinXOffset[0][4]_i_489/O + net (fo=9, routed) 0.806 14.455 core_design/yellowWinXOffset[0][4]_i_489_n_0 + SLICE_X38Y112 LUT6 (Prop_lut6_I5_O) 0.124 14.579 f core_design/yellowWinXOffset[0][4]_i_935/O + net (fo=4, routed) 0.632 15.211 core_design/yellowWinXOffset[0][4]_i_935_n_0 + SLICE_X33Y111 LUT1 (Prop_lut1_I0_O) 0.124 15.335 r core_design/yellowWinXOffset[0][4]_i_933/O + net (fo=1, routed) 0.000 15.335 core_design/yellowWinXOffset[0][4]_i_933_n_0 + SLICE_X33Y111 CARRY4 (Prop_carry4_S[1]_O[2]) + 0.580 15.915 r core_design/yellowWinXOffset_reg[0][4]_i_876/O[2] + net (fo=2, routed) 0.817 16.732 core_design/checkWinsYellow.(null)[0].(null)[5].count5[2] + SLICE_X32Y111 LUT5 (Prop_lut5_I4_O) 0.302 17.034 r core_design/yellowWinXOffset[0][4]_i_877/O + net (fo=1, routed) 0.000 17.034 core_design/yellowWinXOffset[0][4]_i_877_n_0 + SLICE_X32Y111 CARRY4 (Prop_carry4_S[2]_CO[3]) + 0.398 17.432 r core_design/yellowWinXOffset_reg[0][4]_i_780/CO[3] + net (fo=1, routed) 0.000 17.432 core_design/yellowWinXOffset_reg[0][4]_i_780_n_0 + SLICE_X32Y112 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 17.766 f core_design/yellowWinXOffset_reg[0][4]_i_781/O[1] + net (fo=4, routed) 0.675 18.441 core_design/yellowWinXOffset_reg[0][4]_i_781_n_6 + SLICE_X31Y111 LUT6 (Prop_lut6_I0_O) 0.303 18.744 r core_design/yellowWinXOffset[0][4]_i_785/O + net (fo=8, routed) 1.306 20.050 core_design/yellowWinXOffset[0][4]_i_785_n_0 + SLICE_X34Y114 LUT5 (Prop_lut5_I2_O) 0.124 20.174 f core_design/yellowWinXOffset[0][4]_i_882/O + net (fo=1, routed) 0.165 20.339 core_design/yellowWinXOffset[0][4]_i_882_n_0 + SLICE_X34Y114 LUT6 (Prop_lut6_I0_O) 0.124 20.463 r core_design/yellowWinXOffset[0][4]_i_782/O + net (fo=1, routed) 1.040 21.503 core_design/yellowWinXOffset[0][4]_i_782_n_0 + SLICE_X33Y113 LUT6 (Prop_lut6_I0_O) 0.124 21.627 r core_design/yellowWinXOffset[0][4]_i_628/O + net (fo=1, routed) 0.000 21.627 core_design/yellowWinXOffset[0][4]_i_628_n_0 + SLICE_X33Y113 MUXF7 (Prop_muxf7_I0_O) 0.212 21.839 r core_design/yellowWinXOffset_reg[0][4]_i_490/O + net (fo=3, routed) 1.185 23.024 core_design/yellowWinXOffset_reg[0][4]_i_490_n_0 + SLICE_X38Y112 LUT6 (Prop_lut6_I4_O) 0.299 23.323 r core_design/yellowWinXOffset[0][4]_i_361/O + net (fo=1, routed) 0.517 23.840 core_design/yellowWinXOffset[0][4]_i_361_n_0 + SLICE_X40Y112 CARRY4 (Prop_carry4_DI[0]_CO[1]) + 0.465 24.305 r core_design/yellowWinXOffset_reg[0][4]_i_249/CO[1] + net (fo=1, routed) 0.816 25.121 core_design/yellowWinXOffset_reg[0][4]_i_249_n_2 + SLICE_X41Y113 LUT6 (Prop_lut6_I4_O) 0.329 25.450 r core_design/yellowWinXOffset[0][4]_i_150/O + net (fo=15, routed) 2.286 27.736 core_design/showYellowWinIndicator1102_out + SLICE_X34Y90 LUT6 (Prop_lut6_I0_O) 0.124 27.860 r core_design/yellowWinXOffset[0][4]_i_138/O + net (fo=49, routed) 1.812 29.672 core_design/yellowWinXOffset[0][4]_i_138_n_0 + SLICE_X36Y87 LUT5 (Prop_lut5_I2_O) 0.150 29.822 r core_design/yellowWinXOffset[0][5]_i_123/O + net (fo=16, routed) 1.018 30.840 core_design/yellowWinXOffset[0][5]_i_123_n_0 + SLICE_X34Y89 LUT5 (Prop_lut5_I4_O) 0.326 31.166 f core_design/yellowWinXOffset[0][5]_i_125/O + net (fo=4, routed) 0.746 31.911 core_design/yellowWinXOffset[0][5]_i_125_n_0 + SLICE_X35Y88 LUT6 (Prop_lut6_I4_O) 0.124 32.035 r core_design/yellowWinXOffset[0][5]_i_57/O + net (fo=33, routed) 1.169 33.204 core_design/yellowWinXOffset[0][5]_i_57_n_0 + SLICE_X38Y88 LUT6 (Prop_lut6_I2_O) 0.124 33.328 r core_design/showYellowWinIndicator[1]_i_25/O + net (fo=39, routed) 2.027 35.355 core_design/showYellowWinIndicator[1]_i_25_n_0 + SLICE_X44Y96 LUT6 (Prop_lut6_I5_O) 0.124 35.479 r core_design/showYellowWinIndicator[1]_i_14/O + net (fo=25, routed) 0.868 36.347 core_design/showYellowWinIndicator[1]_i_14_n_0 + SLICE_X44Y95 LUT6 (Prop_lut6_I0_O) 0.124 36.471 r core_design/showYellowWinIndicator[6]_i_93/O + net (fo=17, routed) 1.048 37.519 core_design/showYellowWinIndicator[6]_i_93_n_0 + SLICE_X48Y90 LUT6 (Prop_lut6_I0_O) 0.124 37.643 r core_design/showYellowWinIndicator[6]_i_39/O + net (fo=21, routed) 1.768 39.412 core_design/showYellowWinIndicator[6]_i_39_n_0 + SLICE_X48Y97 LUT6 (Prop_lut6_I0_O) 0.124 39.536 f core_design/showYellowWinIndicator[6]_i_17/O + net (fo=20, routed) 1.453 40.988 core_design/showYellowWinIndicator[6]_i_17_n_0 + SLICE_X51Y88 LUT4 (Prop_lut4_I3_O) 0.118 41.106 r core_design/yellowWinXOffset[1][6]_i_255/O + net (fo=5, routed) 0.822 41.929 core_design/yellowWinXOffset[1][6]_i_255_n_0 + SLICE_X52Y87 LUT2 (Prop_lut2_I1_O) 0.326 42.255 r core_design/yellowWinXOffset[1][6]_i_201/O + net (fo=16, routed) 1.340 43.595 core_design/yellowWinXOffset[1][6]_i_201_n_0 + SLICE_X57Y84 LUT6 (Prop_lut6_I2_O) 0.124 43.719 r core_design/yellowWinXOffset[0][5]_i_90/O + net (fo=8, routed) 1.736 45.454 core_design/yellowWinXOffset[0][5]_i_90_n_0 + SLICE_X57Y88 LUT4 (Prop_lut4_I3_O) 0.124 45.578 r core_design/yellowWinXOffset[0][6]_i_239/O + net (fo=5, routed) 1.473 47.052 core_design/yellowWinXOffset[0][6]_i_239_n_0 + SLICE_X61Y86 LUT6 (Prop_lut6_I3_O) 0.124 47.176 r core_design/yellowWinXOffset[4][4]_i_52/O + net (fo=3, routed) 1.190 48.366 core_design/yellowWinXOffset[4][4]_i_52_n_0 + SLICE_X62Y88 LUT6 (Prop_lut6_I0_O) 0.124 48.490 r core_design/yellowWinXOffset[6][5]_i_54/O + net (fo=3, routed) 0.671 49.161 core_design/yellowWinXOffset[6][5]_i_54_n_0 + SLICE_X64Y87 LUT5 (Prop_lut5_I2_O) 0.124 49.285 f core_design/yellowWinXOffset[6][5]_i_25/O + net (fo=30, routed) 1.171 50.456 core_design/yellowWinXOffset[6][5]_i_25_n_0 + SLICE_X66Y86 LUT6 (Prop_lut6_I5_O) 0.124 50.580 r core_design/yellowWinXOffset[4][4]_i_21/O + net (fo=8, routed) 1.044 51.624 core_design/yellowWinXOffset[4][4]_i_21_n_0 + SLICE_X68Y90 LUT5 (Prop_lut5_I0_O) 0.124 51.748 f core_design/yellowWinXOffset[1][6]_i_81/O + net (fo=12, routed) 1.020 52.768 core_design/yellowWinXOffset[1][6]_i_81_n_0 + SLICE_X69Y94 LUT3 (Prop_lut3_I0_O) 0.152 52.920 r core_design/yellowWinXOffset[6][5]_i_64/O + net (fo=3, routed) 0.440 53.360 core_design/yellowWinXOffset[6][5]_i_64_n_0 + SLICE_X70Y94 LUT6 (Prop_lut6_I5_O) 0.326 53.686 r core_design/yellowWinYOffset[4][6]_i_57/O + net (fo=14, routed) 1.335 55.021 core_design/yellowWinYOffset[4][6]_i_57_n_0 + SLICE_X71Y96 LUT6 (Prop_lut6_I1_O) 0.124 55.145 r core_design/yellowWinXOffset[3][2]_i_8/O + net (fo=19, routed) 1.388 56.533 core_design/yellowWinXOffset[3][2]_i_8_n_0 + SLICE_X72Y100 LUT4 (Prop_lut4_I2_O) 0.150 56.683 r core_design/yellowWinYOffset[4][4]_i_6/O + net (fo=21, routed) 1.598 58.280 core_design/yellowWinYOffset[4][4]_i_6_n_0 + SLICE_X73Y99 LUT6 (Prop_lut6_I4_O) 0.326 58.606 r core_design/yellowWinYOffset[2][0]_i_6/O + net (fo=4, routed) 1.394 60.000 core_design/yellowWinYOffset[2][0]_i_6_n_0 + SLICE_X67Y100 LUT6 (Prop_lut6_I2_O) 0.124 60.124 r core_design/yellowWinYOffset[3][6]_i_4/O + net (fo=11, routed) 0.768 60.892 core_design/yellowWinYOffset[3][6]_i_4_n_0 + SLICE_X64Y98 LUT5 (Prop_lut5_I4_O) 0.150 61.042 f core_design/yellowWinXOffset[5][6]_i_8/O + net (fo=11, routed) 1.492 62.534 core_design/yellowWinXOffset[5][6]_i_8_n_0 + SLICE_X66Y101 LUT6 (Prop_lut6_I4_O) 0.326 62.860 r core_design/yellowWinYOffset[5][1]_i_2/O + net (fo=1, routed) 0.973 63.833 core_design/yellowWinYOffset[5][1]_i_2_n_0 + SLICE_X66Y104 LUT2 (Prop_lut2_I0_O) 0.153 63.986 r core_design/yellowWinYOffset[5][1]_i_1/O + net (fo=1, routed) 0.000 63.986 core_design/yellowWinYOffset[1] + SLICE_X66Y104 FDCE r core_design/yellowWinYOffset_reg[5][1]/D ------------------------------------------------------------------- ------------------- Slack: inf - Source: pixY_reg[2]/C - (rising edge-triggered cell FDRE) - Destination: genblk1[19].red_piece_gfx/paletteIndex_reg[0]/D + Source: core_design/board_reg[29][0]/C + (rising edge-triggered cell FDCE) + Destination: core_design/yellowWinYOffset_reg[5][0]/D Path Group: (none) Path Type: Max at Slow Process Corner - Data Path Delay: 9.967ns (logic 1.754ns (17.598%) route 8.213ns (82.402%)) - Logic Levels: 5 (CARRY4=1 FDRE=1 LUT1=1 LUT6=2) + Data Path Delay: 63.963ns (logic 11.010ns (17.213%) route 52.953ns (82.787%)) + Logic Levels: 50 (CARRY4=6 FDCE=1 LUT1=1 LUT2=3 LUT3=2 LUT4=4 LUT5=9 LUT6=22 MUXF7=2) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - SLICE_X73Y152 FDRE 0.000 0.000 r pixY_reg[2]/C - SLICE_X73Y152 FDRE (Prop_fdre_C_Q) 0.419 0.419 f pixY_reg[2]/Q - net (fo=186, routed) 5.271 5.690 genblk1[1].red_piece_gfx/Q[0] - SLICE_X84Y141 LUT1 (Prop_lut1_I0_O) 0.296 5.986 r genblk1[1].red_piece_gfx/paletteIndex[1]_i_10__3/O - net (fo=1, routed) 0.000 5.986 genblk1[1].red_piece_gfx/paletteIndex[1]_i_10__3_n_0 - SLICE_X84Y141 CARRY4 (Prop_carry4_S[0]_O[3]) - 0.608 6.594 r genblk1[1].red_piece_gfx/paletteIndex_reg[1]_i_5__0/O[3] - net (fo=21, routed) 1.720 8.314 genblk1[19].red_piece_gfx/O[2] - SLICE_X85Y136 LUT6 (Prop_lut6_I1_O) 0.307 8.621 r genblk1[19].red_piece_gfx/paletteIndex[0]_i_2__14/O - net (fo=1, routed) 0.877 9.497 genblk1[19].red_piece_gfx/paletteIndex[0]_i_2__14_n_0 - SLICE_X85Y136 LUT6 (Prop_lut6_I1_O) 0.124 9.621 r genblk1[19].red_piece_gfx/paletteIndex[0]_i_1__18/O - net (fo=2, routed) 0.346 9.967 genblk1[19].red_piece_gfx/D[0] - SLICE_X83Y137 FDRE r genblk1[19].red_piece_gfx/paletteIndex_reg[0]/D + SLICE_X12Y150 FDCE 0.000 0.000 r core_design/board_reg[29][0]/C + SLICE_X12Y150 FDCE (Prop_fdce_C_Q) 0.518 0.518 r core_design/board_reg[29][0]/Q + net (fo=171, routed) 6.704 7.222 core_design/board_reg_n_0_[29][0] + SLICE_X47Y111 LUT2 (Prop_lut2_I0_O) 0.124 7.346 r core_design/showYellowWinIndicator[4]_i_200/O + net (fo=49, routed) 1.983 9.329 core_design/checkWinsYellow.(null)[2].(null)[5].c[0] + SLICE_X32Y109 LUT5 (Prop_lut5_I4_O) 0.124 9.453 r core_design/yellowWinXOffset[0][4]_i_874/O + net (fo=1, routed) 0.000 9.453 core_design/yellowWinXOffset[0][4]_i_874_n_0 + SLICE_X32Y109 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 10.003 r core_design/yellowWinXOffset_reg[0][4]_i_778/CO[3] + net (fo=1, routed) 0.000 10.003 core_design/yellowWinXOffset_reg[0][4]_i_778_n_0 + SLICE_X32Y110 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 10.225 r core_design/yellowWinXOffset_reg[0][4]_i_779/O[0] + net (fo=3, routed) 0.810 11.035 core_design/yellowWinXOffset_reg[0][4]_i_779_n_7 + SLICE_X33Y109 LUT4 (Prop_lut4_I1_O) 0.329 11.364 r core_design/yellowWinXOffset[0][4]_i_869/O + net (fo=4, routed) 1.007 12.370 core_design/yellowWinXOffset[0][4]_i_869_n_0 + SLICE_X33Y110 LUT3 (Prop_lut3_I1_O) 0.327 12.697 f core_design/yellowWinXOffset[0][4]_i_777/O + net (fo=1, routed) 0.000 12.697 core_design/yellowWinXOffset[0][4]_i_777_n_0 + SLICE_X33Y110 MUXF7 (Prop_muxf7_I1_O) 0.217 12.914 f core_design/yellowWinXOffset_reg[0][4]_i_625/O + net (fo=1, routed) 0.436 13.350 core_design/yellowWinXOffset_reg[0][4]_i_625_n_0 + SLICE_X33Y110 LUT5 (Prop_lut5_I2_O) 0.299 13.649 r core_design/yellowWinXOffset[0][4]_i_489/O + net (fo=9, routed) 0.806 14.455 core_design/yellowWinXOffset[0][4]_i_489_n_0 + SLICE_X38Y112 LUT6 (Prop_lut6_I5_O) 0.124 14.579 f core_design/yellowWinXOffset[0][4]_i_935/O + net (fo=4, routed) 0.632 15.211 core_design/yellowWinXOffset[0][4]_i_935_n_0 + SLICE_X33Y111 LUT1 (Prop_lut1_I0_O) 0.124 15.335 r core_design/yellowWinXOffset[0][4]_i_933/O + net (fo=1, routed) 0.000 15.335 core_design/yellowWinXOffset[0][4]_i_933_n_0 + SLICE_X33Y111 CARRY4 (Prop_carry4_S[1]_O[2]) + 0.580 15.915 r core_design/yellowWinXOffset_reg[0][4]_i_876/O[2] + net (fo=2, routed) 0.817 16.732 core_design/checkWinsYellow.(null)[0].(null)[5].count5[2] + SLICE_X32Y111 LUT5 (Prop_lut5_I4_O) 0.302 17.034 r core_design/yellowWinXOffset[0][4]_i_877/O + net (fo=1, routed) 0.000 17.034 core_design/yellowWinXOffset[0][4]_i_877_n_0 + SLICE_X32Y111 CARRY4 (Prop_carry4_S[2]_CO[3]) + 0.398 17.432 r core_design/yellowWinXOffset_reg[0][4]_i_780/CO[3] + net (fo=1, routed) 0.000 17.432 core_design/yellowWinXOffset_reg[0][4]_i_780_n_0 + SLICE_X32Y112 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 17.766 f core_design/yellowWinXOffset_reg[0][4]_i_781/O[1] + net (fo=4, routed) 0.675 18.441 core_design/yellowWinXOffset_reg[0][4]_i_781_n_6 + SLICE_X31Y111 LUT6 (Prop_lut6_I0_O) 0.303 18.744 r core_design/yellowWinXOffset[0][4]_i_785/O + net (fo=8, routed) 1.306 20.050 core_design/yellowWinXOffset[0][4]_i_785_n_0 + SLICE_X34Y114 LUT5 (Prop_lut5_I2_O) 0.124 20.174 f core_design/yellowWinXOffset[0][4]_i_882/O + net (fo=1, routed) 0.165 20.339 core_design/yellowWinXOffset[0][4]_i_882_n_0 + SLICE_X34Y114 LUT6 (Prop_lut6_I0_O) 0.124 20.463 r core_design/yellowWinXOffset[0][4]_i_782/O + net (fo=1, routed) 1.040 21.503 core_design/yellowWinXOffset[0][4]_i_782_n_0 + SLICE_X33Y113 LUT6 (Prop_lut6_I0_O) 0.124 21.627 r core_design/yellowWinXOffset[0][4]_i_628/O + net (fo=1, routed) 0.000 21.627 core_design/yellowWinXOffset[0][4]_i_628_n_0 + SLICE_X33Y113 MUXF7 (Prop_muxf7_I0_O) 0.212 21.839 r core_design/yellowWinXOffset_reg[0][4]_i_490/O + net (fo=3, routed) 1.185 23.024 core_design/yellowWinXOffset_reg[0][4]_i_490_n_0 + SLICE_X38Y112 LUT6 (Prop_lut6_I4_O) 0.299 23.323 r core_design/yellowWinXOffset[0][4]_i_361/O + net (fo=1, routed) 0.517 23.840 core_design/yellowWinXOffset[0][4]_i_361_n_0 + SLICE_X40Y112 CARRY4 (Prop_carry4_DI[0]_CO[1]) + 0.465 24.305 r core_design/yellowWinXOffset_reg[0][4]_i_249/CO[1] + net (fo=1, routed) 0.816 25.121 core_design/yellowWinXOffset_reg[0][4]_i_249_n_2 + SLICE_X41Y113 LUT6 (Prop_lut6_I4_O) 0.329 25.450 r core_design/yellowWinXOffset[0][4]_i_150/O + net (fo=15, routed) 2.286 27.736 core_design/showYellowWinIndicator1102_out + SLICE_X34Y90 LUT6 (Prop_lut6_I0_O) 0.124 27.860 r core_design/yellowWinXOffset[0][4]_i_138/O + net (fo=49, routed) 1.812 29.672 core_design/yellowWinXOffset[0][4]_i_138_n_0 + SLICE_X36Y87 LUT5 (Prop_lut5_I2_O) 0.150 29.822 r core_design/yellowWinXOffset[0][5]_i_123/O + net (fo=16, routed) 1.018 30.840 core_design/yellowWinXOffset[0][5]_i_123_n_0 + SLICE_X34Y89 LUT5 (Prop_lut5_I4_O) 0.326 31.166 f core_design/yellowWinXOffset[0][5]_i_125/O + net (fo=4, routed) 0.746 31.911 core_design/yellowWinXOffset[0][5]_i_125_n_0 + SLICE_X35Y88 LUT6 (Prop_lut6_I4_O) 0.124 32.035 r core_design/yellowWinXOffset[0][5]_i_57/O + net (fo=33, routed) 1.169 33.204 core_design/yellowWinXOffset[0][5]_i_57_n_0 + SLICE_X38Y88 LUT6 (Prop_lut6_I2_O) 0.124 33.328 r core_design/showYellowWinIndicator[1]_i_25/O + net (fo=39, routed) 2.027 35.355 core_design/showYellowWinIndicator[1]_i_25_n_0 + SLICE_X44Y96 LUT6 (Prop_lut6_I5_O) 0.124 35.479 r core_design/showYellowWinIndicator[1]_i_14/O + net (fo=25, routed) 0.868 36.347 core_design/showYellowWinIndicator[1]_i_14_n_0 + SLICE_X44Y95 LUT6 (Prop_lut6_I0_O) 0.124 36.471 r core_design/showYellowWinIndicator[6]_i_93/O + net (fo=17, routed) 1.048 37.519 core_design/showYellowWinIndicator[6]_i_93_n_0 + SLICE_X48Y90 LUT6 (Prop_lut6_I0_O) 0.124 37.643 r core_design/showYellowWinIndicator[6]_i_39/O + net (fo=21, routed) 1.768 39.412 core_design/showYellowWinIndicator[6]_i_39_n_0 + SLICE_X48Y97 LUT6 (Prop_lut6_I0_O) 0.124 39.536 f core_design/showYellowWinIndicator[6]_i_17/O + net (fo=20, routed) 1.453 40.988 core_design/showYellowWinIndicator[6]_i_17_n_0 + SLICE_X51Y88 LUT4 (Prop_lut4_I3_O) 0.118 41.106 r core_design/yellowWinXOffset[1][6]_i_255/O + net (fo=5, routed) 0.822 41.929 core_design/yellowWinXOffset[1][6]_i_255_n_0 + SLICE_X52Y87 LUT2 (Prop_lut2_I1_O) 0.326 42.255 r core_design/yellowWinXOffset[1][6]_i_201/O + net (fo=16, routed) 1.340 43.595 core_design/yellowWinXOffset[1][6]_i_201_n_0 + SLICE_X57Y84 LUT6 (Prop_lut6_I2_O) 0.124 43.719 r core_design/yellowWinXOffset[0][5]_i_90/O + net (fo=8, routed) 1.736 45.454 core_design/yellowWinXOffset[0][5]_i_90_n_0 + SLICE_X57Y88 LUT4 (Prop_lut4_I3_O) 0.124 45.578 r core_design/yellowWinXOffset[0][6]_i_239/O + net (fo=5, routed) 1.473 47.052 core_design/yellowWinXOffset[0][6]_i_239_n_0 + SLICE_X61Y86 LUT6 (Prop_lut6_I3_O) 0.124 47.176 r core_design/yellowWinXOffset[4][4]_i_52/O + net (fo=3, routed) 1.190 48.366 core_design/yellowWinXOffset[4][4]_i_52_n_0 + SLICE_X62Y88 LUT6 (Prop_lut6_I0_O) 0.124 48.490 r core_design/yellowWinXOffset[6][5]_i_54/O + net (fo=3, routed) 0.671 49.161 core_design/yellowWinXOffset[6][5]_i_54_n_0 + SLICE_X64Y87 LUT5 (Prop_lut5_I2_O) 0.124 49.285 f core_design/yellowWinXOffset[6][5]_i_25/O + net (fo=30, routed) 1.171 50.456 core_design/yellowWinXOffset[6][5]_i_25_n_0 + SLICE_X66Y86 LUT6 (Prop_lut6_I5_O) 0.124 50.580 r core_design/yellowWinXOffset[4][4]_i_21/O + net (fo=8, routed) 1.044 51.624 core_design/yellowWinXOffset[4][4]_i_21_n_0 + SLICE_X68Y90 LUT5 (Prop_lut5_I0_O) 0.124 51.748 f core_design/yellowWinXOffset[1][6]_i_81/O + net (fo=12, routed) 1.020 52.768 core_design/yellowWinXOffset[1][6]_i_81_n_0 + SLICE_X69Y94 LUT3 (Prop_lut3_I0_O) 0.152 52.920 r core_design/yellowWinXOffset[6][5]_i_64/O + net (fo=3, routed) 0.440 53.360 core_design/yellowWinXOffset[6][5]_i_64_n_0 + SLICE_X70Y94 LUT6 (Prop_lut6_I5_O) 0.326 53.686 r core_design/yellowWinYOffset[4][6]_i_57/O + net (fo=14, routed) 1.335 55.021 core_design/yellowWinYOffset[4][6]_i_57_n_0 + SLICE_X71Y96 LUT6 (Prop_lut6_I1_O) 0.124 55.145 r core_design/yellowWinXOffset[3][2]_i_8/O + net (fo=19, routed) 1.388 56.533 core_design/yellowWinXOffset[3][2]_i_8_n_0 + SLICE_X72Y100 LUT4 (Prop_lut4_I2_O) 0.150 56.683 f core_design/yellowWinYOffset[4][4]_i_6/O + net (fo=21, routed) 1.598 58.280 core_design/yellowWinYOffset[4][4]_i_6_n_0 + SLICE_X73Y99 LUT6 (Prop_lut6_I4_O) 0.326 58.606 f core_design/yellowWinYOffset[2][0]_i_6/O + net (fo=4, routed) 1.394 60.000 core_design/yellowWinYOffset[2][0]_i_6_n_0 + SLICE_X67Y100 LUT6 (Prop_lut6_I2_O) 0.124 60.124 f core_design/yellowWinYOffset[3][6]_i_4/O + net (fo=11, routed) 0.768 60.892 core_design/yellowWinYOffset[3][6]_i_4_n_0 + SLICE_X64Y98 LUT5 (Prop_lut5_I4_O) 0.150 61.042 r core_design/yellowWinXOffset[5][6]_i_8/O + net (fo=11, routed) 1.320 62.362 core_design/yellowWinXOffset[5][6]_i_8_n_0 + SLICE_X64Y101 LUT6 (Prop_lut6_I4_O) 0.326 62.688 r core_design/yellowWinYOffset[5][0]_i_2/O + net (fo=1, routed) 1.151 63.839 core_design/yellowWinYOffset[5][0]_i_2_n_0 + SLICE_X66Y104 LUT2 (Prop_lut2_I0_O) 0.124 63.963 r core_design/yellowWinYOffset[5][0]_i_1/O + net (fo=1, routed) 0.000 63.963 core_design/yellowWinYOffset[0] + SLICE_X66Y104 FDCE r core_design/yellowWinYOffset_reg[5][0]/D ------------------------------------------------------------------- ------------------- @@ -530,189 +2928,189 @@ Slack: inf Min Delay Paths -------------------------------------------------------------------------------------- Slack: inf - Source: pixX_reg[6]/C + Source: vState_reg[1]__0/C (rising edge-triggered cell FDRE) - Destination: pixX_reg[7]/D + Destination: vState_reg[3]__0/D Path Group: (none) Path Type: Min at Fast Process Corner - Data Path Delay: 0.296ns (logic 0.186ns (62.765%) route 0.110ns (37.235%)) + Data Path Delay: 0.296ns (logic 0.227ns (76.736%) route 0.069ns (23.264%)) Logic Levels: 2 (FDRE=1 LUT3=1) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - SLICE_X75Y151 FDRE 0.000 0.000 r pixX_reg[6]/C - SLICE_X75Y151 FDRE (Prop_fdre_C_Q) 0.141 0.141 r pixX_reg[6]/Q - net (fo=184, routed) 0.110 0.251 pixX_reg[6] - SLICE_X74Y151 LUT3 (Prop_lut3_I0_O) 0.045 0.296 r pixX[7]_i_1/O - net (fo=1, routed) 0.000 0.296 p_0_in__0[7] - SLICE_X74Y151 FDRE r pixX_reg[7]/D + SLICE_X81Y148 FDRE 0.000 0.000 r vState_reg[1]__0/C + SLICE_X81Y148 FDRE (Prop_fdre_C_Q) 0.128 0.128 f vState_reg[1]__0/Q + net (fo=2, routed) 0.069 0.197 vValid + SLICE_X81Y148 LUT3 (Prop_lut3_I1_O) 0.099 0.296 r vState[3]__0_i_1/O + net (fo=1, routed) 0.000 0.296 vState[3]__0_i_1_n_0 + SLICE_X81Y148 FDRE r vState_reg[3]__0/D ------------------------------------------------------------------- ------------------- Slack: inf - Source: pixX_reg[6]/C + Source: hCnt_reg[0]/C (rising edge-triggered cell FDRE) - Destination: pixX_reg[9]/D + Destination: hCnt_reg[2]/D Path Group: (none) Path Type: Min at Fast Process Corner - Data Path Delay: 0.300ns (logic 0.186ns (61.929%) route 0.114ns (38.071%)) - Logic Levels: 2 (FDRE=1 LUT5=1) + Data Path Delay: 0.296ns (logic 0.186ns (62.765%) route 0.110ns (37.235%)) + Logic Levels: 2 (FDRE=1 LUT3=1) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - SLICE_X75Y151 FDRE 0.000 0.000 r pixX_reg[6]/C - SLICE_X75Y151 FDRE (Prop_fdre_C_Q) 0.141 0.141 r pixX_reg[6]/Q - net (fo=184, routed) 0.114 0.255 pixX_reg[6] - SLICE_X74Y151 LUT5 (Prop_lut5_I3_O) 0.045 0.300 r pixX[9]_i_3/O - net (fo=1, routed) 0.000 0.300 p_0_in__0[9] - SLICE_X74Y151 FDRE r pixX_reg[9]/D + SLICE_X75Y149 FDRE 0.000 0.000 r hCnt_reg[0]/C + SLICE_X75Y149 FDRE (Prop_fdre_C_Q) 0.141 0.141 r hCnt_reg[0]/Q + net (fo=8, routed) 0.110 0.251 hCnt_reg_n_0_[0] + SLICE_X74Y149 LUT3 (Prop_lut3_I1_O) 0.045 0.296 r hCnt[2]_i_1/O + net (fo=1, routed) 0.000 0.296 hCnt[2]_i_1_n_0 + SLICE_X74Y149 FDRE r hCnt_reg[2]/D ------------------------------------------------------------------- ------------------- Slack: inf - Source: vState_reg[1]__0/C + Source: hState_reg[1]__0/C (rising edge-triggered cell FDRE) - Destination: vState_reg[3]__0/D + Destination: hState_reg[3]__0/D Path Group: (none) Path Type: Min at Fast Process Corner - Data Path Delay: 0.303ns (logic 0.227ns (74.868%) route 0.076ns (25.132%)) + Data Path Delay: 0.297ns (logic 0.227ns (76.391%) route 0.070ns (23.609%)) Logic Levels: 2 (FDRE=1 LUT3=1) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - SLICE_X64Y151 FDRE 0.000 0.000 r vState_reg[1]__0/C - SLICE_X64Y151 FDRE (Prop_fdre_C_Q) 0.128 0.128 f vState_reg[1]__0/Q - net (fo=2, routed) 0.076 0.204 vValid - SLICE_X64Y151 LUT3 (Prop_lut3_I1_O) 0.099 0.303 r vState[3]__0_i_1/O - net (fo=1, routed) 0.000 0.303 vState[3]__0_i_1_n_0 - SLICE_X64Y151 FDRE r vState_reg[3]__0/D + SLICE_X79Y148 FDRE 0.000 0.000 r hState_reg[1]__0/C + SLICE_X79Y148 FDRE (Prop_fdre_C_Q) 0.128 0.128 f hState_reg[1]__0/Q + net (fo=2, routed) 0.070 0.198 hValid + SLICE_X79Y148 LUT3 (Prop_lut3_I1_O) 0.099 0.297 r hState[3]__0_i_1/O + net (fo=1, routed) 0.000 0.297 hState[3]__0_i_1_n_0 + SLICE_X79Y148 FDRE r hState_reg[3]__0/D ------------------------------------------------------------------- ------------------- Slack: inf - Source: vState_reg[3]/C + Source: hCnt_reg[0]/C (rising edge-triggered cell FDRE) - Destination: vSync_reg/D + Destination: hCnt_reg[3]/D Path Group: (none) Path Type: Min at Fast Process Corner - Data Path Delay: 0.307ns (logic 0.186ns (60.498%) route 0.121ns (39.502%)) - Logic Levels: 2 (FDRE=1 LUT2=1) + Data Path Delay: 0.299ns (logic 0.189ns (63.138%) route 0.110ns (36.862%)) + Logic Levels: 2 (FDRE=1 LUT4=1) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - SLICE_X63Y152 FDRE 0.000 0.000 r vState_reg[3]/C - SLICE_X63Y152 FDRE (Prop_fdre_C_Q) 0.141 0.141 f vState_reg[3]/Q - net (fo=12, routed) 0.121 0.262 vState__0[3] - SLICE_X62Y152 LUT2 (Prop_lut2_I1_O) 0.045 0.307 r vSync_i_2/O - net (fo=1, routed) 0.000 0.307 vSync_i_2_n_0 - SLICE_X62Y152 FDRE r vSync_reg/D + SLICE_X75Y149 FDRE 0.000 0.000 r hCnt_reg[0]/C + SLICE_X75Y149 FDRE (Prop_fdre_C_Q) 0.141 0.141 r hCnt_reg[0]/Q + net (fo=8, routed) 0.110 0.251 hCnt_reg_n_0_[0] + SLICE_X74Y149 LUT4 (Prop_lut4_I1_O) 0.048 0.299 r hCnt[3]_i_1/O + net (fo=1, routed) 0.000 0.299 hCnt[3]_i_1_n_0 + SLICE_X74Y149 FDRE r hCnt_reg[3]/D ------------------------------------------------------------------- ------------------- Slack: inf - Source: hState_reg[1]__0/C - (rising edge-triggered cell FDRE) - Destination: hState_reg[3]__0/D + Source: core_design/yellowPieceYVelocitySign_reg[0]/C + (rising edge-triggered cell FDCE) + Destination: core_design/yellowPieceYVelocitySign_reg[0]/D Path Group: (none) Path Type: Min at Fast Process Corner - Data Path Delay: 0.321ns (logic 0.246ns (76.675%) route 0.075ns (23.325%)) - Logic Levels: 2 (FDRE=1 LUT3=1) + Data Path Delay: 0.310ns (logic 0.186ns (59.973%) route 0.124ns (40.027%)) + Logic Levels: 2 (FDCE=1 LUT6=1) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - SLICE_X62Y151 FDRE 0.000 0.000 r hState_reg[1]__0/C - SLICE_X62Y151 FDRE (Prop_fdre_C_Q) 0.148 0.148 f hState_reg[1]__0/Q - net (fo=2, routed) 0.075 0.223 hValid - SLICE_X62Y151 LUT3 (Prop_lut3_I1_O) 0.098 0.321 r hState[3]__0_i_1/O - net (fo=1, routed) 0.000 0.321 hState[3]__0_i_1_n_0 - SLICE_X62Y151 FDRE r hState_reg[3]__0/D + SLICE_X25Y187 FDCE 0.000 0.000 r core_design/yellowPieceYVelocitySign_reg[0]/C + SLICE_X25Y187 FDCE (Prop_fdce_C_Q) 0.141 0.141 r core_design/yellowPieceYVelocitySign_reg[0]/Q + net (fo=3, routed) 0.124 0.265 core_design/yellowPieceYVelocitySign_reg_n_0_[0] + SLICE_X25Y187 LUT6 (Prop_lut6_I5_O) 0.045 0.310 r core_design/yellowPieceYVelocitySign[0]_i_1/O + net (fo=1, routed) 0.000 0.310 core_design/yellowPieceYVelocitySign[0]_i_1_n_0 + SLICE_X25Y187 FDCE r core_design/yellowPieceYVelocitySign_reg[0]/D ------------------------------------------------------------------- ------------------- Slack: inf - Source: vState_reg[3]__0/C - (rising edge-triggered cell FDRE) - Destination: vState_reg[2]__0/D + Source: core_design/redPieceYOffset_reg[4][6]_C/C + (rising edge-triggered cell FDCE) + Destination: core_design/redPieceYOffset_reg[4][6]_C/D Path Group: (none) Path Type: Min at Fast Process Corner - Data Path Delay: 0.326ns (logic 0.141ns (43.258%) route 0.185ns (56.742%)) - Logic Levels: 1 (FDRE=1) + Data Path Delay: 0.312ns (logic 0.186ns (59.586%) route 0.126ns (40.414%)) + Logic Levels: 2 (FDCE=1 LUT6=1) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - SLICE_X64Y151 FDRE 0.000 0.000 r vState_reg[3]__0/C - SLICE_X64Y151 FDRE (Prop_fdre_C_Q) 0.141 0.141 r vState_reg[3]__0/Q - net (fo=2, routed) 0.185 0.326 vState_reg[3]__0_n_0 - SLICE_X64Y151 FDRE r vState_reg[2]__0/D + SLICE_X5Y176 FDCE 0.000 0.000 r core_design/redPieceYOffset_reg[4][6]_C/C + SLICE_X5Y176 FDCE (Prop_fdce_C_Q) 0.141 0.141 r core_design/redPieceYOffset_reg[4][6]_C/Q + net (fo=7, routed) 0.126 0.267 core_design/redPieceYOffset_reg[4][6]_C_n_0 + SLICE_X5Y176 LUT6 (Prop_lut6_I5_O) 0.045 0.312 r core_design/redPieceYOffset[4][6]_C_i_1/O + net (fo=1, routed) 0.000 0.312 core_design/redPieceYOffset[4][6]_C_i_1_n_0 + SLICE_X5Y176 FDCE r core_design/redPieceYOffset_reg[4][6]_C/D ------------------------------------------------------------------- ------------------- Slack: inf - Source: pixX_reg[2]/C - (rising edge-triggered cell FDRE) - Destination: pixX_reg[2]_rep/D + Source: core_design/yellowPieceYOffset_reg[13][6]_C/C + (rising edge-triggered cell FDCE) + Destination: core_design/yellowPieceYOffset_reg[13][6]_C/D Path Group: (none) Path Type: Min at Fast Process Corner - Data Path Delay: 0.334ns (logic 0.227ns (68.027%) route 0.107ns (31.973%)) - Logic Levels: 2 (FDRE=1 LUT3=1) + Data Path Delay: 0.320ns (logic 0.186ns (58.114%) route 0.134ns (41.886%)) + Logic Levels: 2 (FDCE=1 LUT6=1) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - SLICE_X72Y152 FDRE 0.000 0.000 r pixX_reg[2]/C - SLICE_X72Y152 FDRE (Prop_fdre_C_Q) 0.128 0.128 r pixX_reg[2]/Q - net (fo=7, routed) 0.107 0.235 x027_out[0] - SLICE_X72Y152 LUT3 (Prop_lut3_I2_O) 0.099 0.334 r pixX[2]_rep_i_1/O - net (fo=1, routed) 0.000 0.334 pixX[2]_rep_i_1_n_0 - SLICE_X72Y152 FDRE r pixX_reg[2]_rep/D + SLICE_X47Y190 FDCE 0.000 0.000 r core_design/yellowPieceYOffset_reg[13][6]_C/C + SLICE_X47Y190 FDCE (Prop_fdce_C_Q) 0.141 0.141 r core_design/yellowPieceYOffset_reg[13][6]_C/Q + net (fo=7, routed) 0.134 0.275 core_design/yellowPieceYOffset_reg[13][6]_C_n_0 + SLICE_X47Y190 LUT6 (Prop_lut6_I5_O) 0.045 0.320 r core_design/yellowPieceYOffset[13][6]_C_i_1/O + net (fo=1, routed) 0.000 0.320 core_design/yellowPieceYOffset[13][6]_C_i_1_n_0 + SLICE_X47Y190 FDCE r core_design/yellowPieceYOffset_reg[13][6]_C/D ------------------------------------------------------------------- ------------------- Slack: inf - Source: hCnt_reg[1]/C + Source: hState_reg[3]__0/C (rising edge-triggered cell FDRE) - Destination: hCnt_reg[2]/D + Destination: hState_reg[2]__0/D Path Group: (none) Path Type: Min at Fast Process Corner - Data Path Delay: 0.336ns (logic 0.209ns (62.291%) route 0.127ns (37.709%)) - Logic Levels: 2 (FDRE=1 LUT3=1) + Data Path Delay: 0.322ns (logic 0.141ns (43.738%) route 0.181ns (56.262%)) + Logic Levels: 1 (FDRE=1) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - SLICE_X58Y151 FDRE 0.000 0.000 r hCnt_reg[1]/C - SLICE_X58Y151 FDRE (Prop_fdre_C_Q) 0.164 0.164 r hCnt_reg[1]/Q - net (fo=7, routed) 0.127 0.291 hCnt_reg_n_0_[1] - SLICE_X59Y151 LUT3 (Prop_lut3_I0_O) 0.045 0.336 r hCnt[2]_i_1/O - net (fo=1, routed) 0.000 0.336 hCnt[2]_i_1_n_0 - SLICE_X59Y151 FDRE r hCnt_reg[2]/D + SLICE_X79Y148 FDRE 0.000 0.000 r hState_reg[3]__0/C + SLICE_X79Y148 FDRE (Prop_fdre_C_Q) 0.141 0.141 r hState_reg[3]__0/Q + net (fo=2, routed) 0.181 0.322 hState_reg[3]__0_n_0 + SLICE_X79Y148 FDRE r hState_reg[2]__0/D ------------------------------------------------------------------- ------------------- Slack: inf - Source: vState_reg[2]__0/C + Source: vState_reg[3]__0/C (rising edge-triggered cell FDRE) - Destination: vState_reg[1]__0/D + Destination: vState_reg[2]__0/D Path Group: (none) Path Type: Min at Fast Process Corner - Data Path Delay: 0.336ns (logic 0.141ns (41.936%) route 0.195ns (58.064%)) + Data Path Delay: 0.322ns (logic 0.141ns (43.738%) route 0.181ns (56.262%)) Logic Levels: 1 (FDRE=1) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - SLICE_X64Y151 FDRE 0.000 0.000 r vState_reg[2]__0/C - SLICE_X64Y151 FDRE (Prop_fdre_C_Q) 0.141 0.141 r vState_reg[2]__0/Q - net (fo=2, routed) 0.195 0.336 vState_reg[2]__0_n_0 - SLICE_X64Y151 FDRE r vState_reg[1]__0/D + SLICE_X81Y148 FDRE 0.000 0.000 r vState_reg[3]__0/C + SLICE_X81Y148 FDRE (Prop_fdre_C_Q) 0.141 0.141 r vState_reg[3]__0/Q + net (fo=2, routed) 0.181 0.322 vState_reg[3]__0_n_0 + SLICE_X81Y148 FDRE r vState_reg[2]__0/D ------------------------------------------------------------------- ------------------- Slack: inf - Source: hCnt_reg[1]/C - (rising edge-triggered cell FDRE) - Destination: hCnt_reg[3]/D + Source: core_design/yellowPieceYOffset_reg[11][6]_C/C + (rising edge-triggered cell FDCE) + Destination: core_design/yellowPieceYOffset_reg[11][6]_C/D Path Group: (none) Path Type: Min at Fast Process Corner - Data Path Delay: 0.339ns (logic 0.212ns (62.626%) route 0.127ns (37.374%)) - Logic Levels: 2 (FDRE=1 LUT4=1) + Data Path Delay: 0.328ns (logic 0.186ns (56.770%) route 0.142ns (43.230%)) + Logic Levels: 2 (FDCE=1 LUT6=1) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - SLICE_X58Y151 FDRE 0.000 0.000 r hCnt_reg[1]/C - SLICE_X58Y151 FDRE (Prop_fdre_C_Q) 0.164 0.164 r hCnt_reg[1]/Q - net (fo=7, routed) 0.127 0.291 hCnt_reg_n_0_[1] - SLICE_X59Y151 LUT4 (Prop_lut4_I2_O) 0.048 0.339 r hCnt[3]_i_1/O - net (fo=1, routed) 0.000 0.339 hCnt[3]_i_1_n_0 - SLICE_X59Y151 FDRE r hCnt_reg[3]/D + SLICE_X47Y189 FDCE 0.000 0.000 r core_design/yellowPieceYOffset_reg[11][6]_C/C + SLICE_X47Y189 FDCE (Prop_fdce_C_Q) 0.141 0.141 r core_design/yellowPieceYOffset_reg[11][6]_C/Q + net (fo=7, routed) 0.142 0.283 core_design/yellowPieceYOffset_reg[11][6]_C_n_0 + SLICE_X47Y189 LUT6 (Prop_lut6_I5_O) 0.045 0.328 r core_design/yellowPieceYOffset[11][6]_C_i_1/O + net (fo=1, routed) 0.000 0.328 core_design/yellowPieceYOffset[11][6]_C_i_1_n_0 + SLICE_X47Y189 FDCE r core_design/yellowPieceYOffset_reg[11][6]_C/D ------------------------------------------------------------------- ------------------- diff --git a/vga.runs/impl_1/vga_timing_summary_routed.rpx b/vga.runs/impl_1/vga_timing_summary_routed.rpx index 3fd4044..e2e08cc 100644 Binary files a/vga.runs/impl_1/vga_timing_summary_routed.rpx and b/vga.runs/impl_1/vga_timing_summary_routed.rpx differ diff --git a/vga.runs/impl_1/vga_utilization_placed.pb b/vga.runs/impl_1/vga_utilization_placed.pb index 8efbc6a..0fbc589 100644 Binary files a/vga.runs/impl_1/vga_utilization_placed.pb and b/vga.runs/impl_1/vga_utilization_placed.pb differ diff --git a/vga.runs/impl_1/vga_utilization_placed.rpt b/vga.runs/impl_1/vga_utilization_placed.rpt index bbde94d..919b9ab 100644 --- a/vga.runs/impl_1/vga_utilization_placed.rpt +++ b/vga.runs/impl_1/vga_utilization_placed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 -| Date : Thu Apr 18 03:15:25 2024 +| Date : Mon Apr 22 21:24:10 2024 | Host : me running 64-bit major release (build 9200) | Command : report_utilization -file vga_utilization_placed.rpt -pb vga_utilization_placed.pb | Design : vga @@ -29,18 +29,18 @@ Table of Contents 1. Slice Logic -------------- -+-------------------------+------+-------+------------+-----------+-------+ -| Site Type | Used | Fixed | Prohibited | Available | Util% | -+-------------------------+------+-------+------------+-----------+-------+ -| Slice LUTs | 1041 | 0 | 0 | 63400 | 1.64 | -| LUT as Logic | 1041 | 0 | 0 | 63400 | 1.64 | -| LUT as Memory | 0 | 0 | 0 | 19000 | 0.00 | -| Slice Registers | 218 | 0 | 0 | 126800 | 0.17 | -| Register as Flip Flop | 218 | 0 | 0 | 126800 | 0.17 | -| Register as Latch | 0 | 0 | 0 | 126800 | 0.00 | -| F7 Muxes | 16 | 0 | 0 | 31700 | 0.05 | -| F8 Muxes | 3 | 0 | 0 | 15850 | 0.02 | -+-------------------------+------+-------+------------+-----------+-------+ ++-------------------------+-------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-------------------------+-------+-------+------------+-----------+-------+ +| Slice LUTs | 18983 | 0 | 0 | 63400 | 29.94 | +| LUT as Logic | 18983 | 0 | 0 | 63400 | 29.94 | +| LUT as Memory | 0 | 0 | 0 | 19000 | 0.00 | +| Slice Registers | 2308 | 0 | 0 | 126800 | 1.82 | +| Register as Flip Flop | 2210 | 0 | 0 | 126800 | 1.74 | +| Register as Latch | 98 | 0 | 0 | 126800 | 0.08 | +| F7 Muxes | 536 | 0 | 0 | 31700 | 1.69 | +| F8 Muxes | 76 | 0 | 0 | 15850 | 0.48 | ++-------------------------+-------+-------+------------+-----------+-------+ * Warning! LUT value is adjusted to account for LUT combining. @@ -56,36 +56,36 @@ Table of Contents | 0 | _ | Set | - | | 0 | _ | Reset | - | | 0 | Yes | - | - | -| 0 | Yes | - | Set | -| 0 | Yes | - | Reset | +| 466 | Yes | - | Set | +| 1561 | Yes | - | Reset | | 0 | Yes | Set | - | -| 218 | Yes | Reset | - | +| 281 | Yes | Reset | - | +-------+--------------+-------------+--------------+ 2. Slice Logic Distribution --------------------------- -+--------------------------------------------+------+-------+------------+-----------+-------+ -| Site Type | Used | Fixed | Prohibited | Available | Util% | -+--------------------------------------------+------+-------+------------+-----------+-------+ -| Slice | 363 | 0 | 0 | 15850 | 2.29 | -| SLICEL | 227 | 0 | | | | -| SLICEM | 136 | 0 | | | | -| LUT as Logic | 1041 | 0 | 0 | 63400 | 1.64 | -| using O5 output only | 0 | | | | | -| using O6 output only | 958 | | | | | -| using O5 and O6 | 83 | | | | | -| LUT as Memory | 0 | 0 | 0 | 19000 | 0.00 | -| LUT as Distributed RAM | 0 | 0 | | | | -| LUT as Shift Register | 0 | 0 | | | | -| Slice Registers | 218 | 0 | 0 | 126800 | 0.17 | -| Register driven from within the Slice | 170 | | | | | -| Register driven from outside the Slice | 48 | | | | | -| LUT in front of the register is unused | 9 | | | | | -| LUT in front of the register is used | 39 | | | | | -| Unique Control Sets | 12 | | 0 | 15850 | 0.08 | -+--------------------------------------------+------+-------+------------+-----------+-------+ ++--------------------------------------------+-------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++--------------------------------------------+-------+-------+------------+-----------+-------+ +| Slice | 5778 | 0 | 0 | 15850 | 36.45 | +| SLICEL | 4010 | 0 | | | | +| SLICEM | 1768 | 0 | | | | +| LUT as Logic | 18983 | 0 | 0 | 63400 | 29.94 | +| using O5 output only | 94 | | | | | +| using O6 output only | 15599 | | | | | +| using O5 and O6 | 3290 | | | | | +| LUT as Memory | 0 | 0 | 0 | 19000 | 0.00 | +| LUT as Distributed RAM | 0 | 0 | | | | +| LUT as Shift Register | 0 | 0 | | | | +| Slice Registers | 2308 | 0 | 0 | 126800 | 1.82 | +| Register driven from within the Slice | 1512 | | | | | +| Register driven from outside the Slice | 796 | | | | | +| LUT in front of the register is unused | 117 | | | | | +| LUT in front of the register is used | 679 | | | | | +| Unique Control Sets | 456 | | 0 | 15850 | 2.88 | ++--------------------------------------------+-------+-------+------------+-----------+-------+ * * Note: Available Control Sets calculated as Slice * 1, Review the Control Sets Report for more information regarding control sets. @@ -118,9 +118,9 @@ Table of Contents +-----------------------------+------+-------+------------+-----------+-------+ | Site Type | Used | Fixed | Prohibited | Available | Util% | +-----------------------------+------+-------+------------+-----------+-------+ -| Bonded IOB | 15 | 15 | 0 | 210 | 7.14 | -| IOB Master Pads | 7 | | | | | -| IOB Slave Pads | 8 | | | | | +| Bonded IOB | 20 | 20 | 0 | 210 | 9.52 | +| IOB Master Pads | 11 | | | | | +| IOB Slave Pads | 9 | | | | | | Bonded IPADs | 0 | 0 | 0 | 2 | 0.00 | | PHY_CONTROL | 0 | 0 | 0 | 6 | 0.00 | | PHASER_REF | 0 | 0 | 0 | 6 | 0.00 | @@ -142,7 +142,7 @@ Table of Contents +------------+------+-------+------------+-----------+-------+ | Site Type | Used | Fixed | Prohibited | Available | Util% | +------------+------+-------+------------+-----------+-------+ -| BUFGCTRL | 3 | 0 | 0 | 32 | 9.38 | +| BUFGCTRL | 4 | 0 | 0 | 32 | 12.50 | | BUFIO | 0 | 0 | 0 | 24 | 0.00 | | MMCME2_ADV | 0 | 0 | 0 | 6 | 0.00 | | PLLE2_ADV | 0 | 0 | 0 | 6 | 0.00 | @@ -173,23 +173,26 @@ Table of Contents 8. Primitives ------------- -+----------+------+---------------------+ -| Ref Name | Used | Functional Category | -+----------+------+---------------------+ -| LUT6 | 603 | LUT | -| FDRE | 218 | Flop & Latch | -| LUT1 | 194 | LUT | -| LUT5 | 105 | LUT | -| CARRY4 | 102 | CarryLogic | -| LUT4 | 88 | LUT | -| LUT2 | 69 | LUT | -| LUT3 | 65 | LUT | -| MUXF7 | 16 | MuxFx | -| OBUF | 14 | IO | -| MUXF8 | 3 | MuxFx | -| BUFG | 3 | Clock | -| IBUF | 1 | IO | -+----------+------+---------------------+ ++----------+-------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+-------+---------------------+ +| LUT6 | 10159 | LUT | +| LUT5 | 3643 | LUT | +| LUT3 | 2935 | LUT | +| LUT2 | 2701 | LUT | +| LUT4 | 2543 | LUT | +| CARRY4 | 1660 | CarryLogic | +| FDCE | 1463 | Flop & Latch | +| MUXF7 | 536 | MuxFx | +| FDPE | 466 | Flop & Latch | +| LUT1 | 292 | LUT | +| FDRE | 281 | Flop & Latch | +| LDCE | 98 | Flop & Latch | +| MUXF8 | 76 | MuxFx | +| OBUF | 14 | IO | +| IBUF | 6 | IO | +| BUFG | 4 | Clock | ++----------+-------+---------------------+ 9. Black Boxes diff --git a/vga.runs/impl_1/vivado.jou b/vga.runs/impl_1/vivado.jou index 790340f..3f62487 100644 --- a/vga.runs/impl_1/vivado.jou +++ b/vga.runs/impl_1/vivado.jou @@ -3,12 +3,12 @@ # SW Build 4029153 on Fri Oct 13 20:14:34 MDT 2023 # IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 # SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 -# Start of session at: Thu Apr 18 03:14:59 2024 -# Process ID: 43744 -# Current directory: C:/Users/james/Documents/vga/vga.runs/impl_1 +# Start of session at: Mon Apr 22 21:21:53 2024 +# Process ID: 13628 +# Current directory: C:/Users/james/Documents/fpga-connect4/vga.runs/impl_1 # Command line: vivado.exe -log vga.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source vga.tcl -notrace -# Log file: C:/Users/james/Documents/vga/vga.runs/impl_1/vga.vdi -# Journal file: C:/Users/james/Documents/vga/vga.runs/impl_1\vivado.jou +# Log file: C:/Users/james/Documents/fpga-connect4/vga.runs/impl_1/vga.vdi +# Journal file: C:/Users/james/Documents/fpga-connect4/vga.runs/impl_1\vivado.jou # Running On: me, OS: Windows, CPU Frequency: 2918 MHz, CPU Physical cores: 14, Host memory: 34016 MB #----------------------------------------------------------- source vga.tcl -notrace diff --git a/vga.runs/impl_1/vivado.pb b/vga.runs/impl_1/vivado.pb index 071bc1b..2ed1cb5 100644 Binary files a/vga.runs/impl_1/vivado.pb and b/vga.runs/impl_1/vivado.pb differ diff --git a/vga.runs/impl_1/vivado_20064.backup.jou b/vga.runs/impl_1/vivado_20064.backup.jou deleted file mode 100644 index 062c028..0000000 --- a/vga.runs/impl_1/vivado_20064.backup.jou +++ /dev/null @@ -1,14 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2023.2 (64-bit) -# SW Build 4029153 on Fri Oct 13 20:14:34 MDT 2023 -# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 -# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 -# Start of session at: Thu Apr 18 02:49:21 2024 -# Process ID: 20064 -# Current directory: C:/Users/james/Documents/vga/vga.runs/impl_1 -# Command line: vivado.exe -log vga.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source vga.tcl -notrace -# Log file: C:/Users/james/Documents/vga/vga.runs/impl_1/vga.vdi -# Journal file: C:/Users/james/Documents/vga/vga.runs/impl_1\vivado.jou -# Running On: me, OS: Windows, CPU Frequency: 2918 MHz, CPU Physical cores: 14, Host memory: 34016 MB -#----------------------------------------------------------- -source vga.tcl -notrace diff --git a/vga.runs/impl_1/write_bitstream.pb b/vga.runs/impl_1/write_bitstream.pb index 42fe5ac..3796f88 100644 Binary files a/vga.runs/impl_1/write_bitstream.pb and b/vga.runs/impl_1/write_bitstream.pb differ diff --git a/vga.runs/synth_1/.Xil/vga_propImpl.xdc b/vga.runs/synth_1/.Xil/vga_propImpl.xdc index 7431bd7..dedce46 100644 --- a/vga.runs/synth_1/.Xil/vga_propImpl.xdc +++ b/vga.runs/synth_1/.Xil/vga_propImpl.xdc @@ -1,4 +1,4 @@ -set_property SRC_FILE_INFO {cfile:C:/Users/james/Documents/vga/vga.srcs/constrs_1/new/vga.xdc rfile:../../../vga.srcs/constrs_1/new/vga.xdc id:1} [current_design] +set_property SRC_FILE_INFO {cfile:C:/Users/james/Documents/fpga-connect4/vga.srcs/constrs_1/new/vga.xdc rfile:../../../vga.srcs/constrs_1/new/vga.xdc id:1} [current_design] set_property src_info {type:XDC file:1 line:5 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN E3 [get_ports {sysClk}] set_property src_info {type:XDC file:1 line:7 export:INPUT save:INPUT read:READ} [current_design] @@ -31,3 +31,19 @@ set_property src_info {type:XDC file:1 line:49 export:INPUT save:INPUT read:READ set_property PACKAGE_PIN B11 [get_ports {hSync}] set_property src_info {type:XDC file:1 line:52 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN B12 [get_ports {vSync}] +set_property src_info {type:XDC file:1 line:55 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN N17 [get_ports BtnC] +set_property src_info {type:XDC file:1 line:58 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN M18 [get_ports BtnU] +set_property src_info {type:XDC file:1 line:61 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN P17 [get_ports BtnL] +set_property src_info {type:XDC file:1 line:64 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN M17 [get_ports BtnR] +set_property src_info {type:XDC file:1 line:67 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN P18 [get_ports BtnD] +set_property src_info {type:XDC file:1 line:70 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN D8 [get_ports {vgaBlu[3]}] +set_property src_info {type:XDC file:1 line:73 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN V10 [get_ports {switch15Debug}] +set_property src_info {type:XDC file:1 line:76 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN C12 [get_ports {btnCPUReset}] diff --git a/vga.runs/synth_1/.vivado.begin.rst b/vga.runs/synth_1/.vivado.begin.rst index 5fb6eaf..b5f3adb 100644 --- a/vga.runs/synth_1/.vivado.begin.rst +++ b/vga.runs/synth_1/.vivado.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/vga.runs/synth_1/gen_run.xml b/vga.runs/synth_1/gen_run.xml index a0e6ad3..d7db974 100644 --- a/vga.runs/synth_1/gen_run.xml +++ b/vga.runs/synth_1/gen_run.xml @@ -1,5 +1,5 @@ - + @@ -60,73 +60,71 @@ - + - + - + - + - + - + - + - + - + - - + - @@ -165,9 +163,7 @@ - - Vivado Synthesis Defaults - + diff --git a/vga.runs/synth_1/project.wdf b/vga.runs/synth_1/project.wdf deleted file mode 100644 index 54a3124..0000000 --- a/vga.runs/synth_1/project.wdf +++ /dev/null @@ -1,31 +0,0 @@ -version:1 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:3137:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:31:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:31:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:31:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:66616c7365:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:3238:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:31:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:31:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:31:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:31:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:31:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:31:00:00 -5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:6362643438373561643830303434633362396237343433643063373739653835:506172656e742050412070726f6a656374204944:00 -eof:1462968553 diff --git a/vga.runs/synth_1/runme.log b/vga.runs/synth_1/runme.log index 7d7820b..3c04a1f 100644 --- a/vga.runs/synth_1/runme.log +++ b/vga.runs/synth_1/runme.log @@ -12,8 +12,8 @@ ** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. source vga.tcl -notrace -Command: read_checkpoint -auto_incremental -incremental C:/Users/james/Documents/vga/vga.srcs/utils_1/imports/synth_1/vga.dcp -INFO: [Vivado 12-5825] Read reference checkpoint from C:/Users/james/Documents/vga/vga.srcs/utils_1/imports/synth_1/vga.dcp for incremental synthesis +Command: read_checkpoint -auto_incremental -incremental C:/Users/james/Documents/fpga-connect4/vga.srcs/utils_1/imports/synth_1/vga.dcp +INFO: [Vivado 12-5825] Read reference checkpoint from C:/Users/james/Documents/fpga-connect4/vga.srcs/utils_1/imports/synth_1/vga.dcp for incremental synthesis INFO: [Vivado 12-7989] Please ensure there are no constraint changes Command: synth_design -top vga -part xc7a100tcsg324-1 Starting synth_design @@ -22,266 +22,268 @@ INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100 INFO: [Device 21-403] Loading part xc7a100tcsg324-1 INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate} -INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. +INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes -INFO: [Synth 8-7075] Helper process launched with PID 28388 ---------------------------------------------------------------------------------- -Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:07 . Memory (MB): peak = 1417.863 ; gain = 440.387 ---------------------------------------------------------------------------------- -INFO: [Synth 8-11241] undeclared symbol 'hValid', assumed default net type 'wire' [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/vga.v:51] -INFO: [Synth 8-11241] undeclared symbol 'vValid', assumed default net type 'wire' [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/vga.v:118] -INFO: [Synth 8-6157] synthesizing module 'vga' [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/vga.v:23] -INFO: [Synth 8-6157] synthesizing module 'red_piece' [C:/Users/james/Documents/vga/sprite_modules/red_piece.v:20] -INFO: [Synth 8-6155] done synthesizing module 'red_piece' (0#1) [C:/Users/james/Documents/vga/sprite_modules/red_piece.v:20] -INFO: [Synth 8-6157] synthesizing module 'yellow_piece' [C:/Users/james/Documents/vga/sprite_modules/yellow_piece.v:20] -INFO: [Synth 8-6155] done synthesizing module 'yellow_piece' (0#1) [C:/Users/james/Documents/vga/sprite_modules/yellow_piece.v:20] -INFO: [Synth 8-155] case statement is not full and has no default [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/vga.v:73] -INFO: [Synth 8-155] case statement is not full and has no default [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/vga.v:140] -INFO: [Synth 8-6157] synthesizing module 'TESTcore_design' [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:23] -INFO: [Synth 8-6155] done synthesizing module 'TESTcore_design' (0#1) [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:23] -INFO: [Synth 8-6157] synthesizing module 'corner_border_check' [C:/Users/james/Documents/vga/sprite_modules/corner_border_check.v:20] -INFO: [Synth 8-6155] done synthesizing module 'corner_border_check' (0#1) [C:/Users/james/Documents/vga/sprite_modules/corner_border_check.v:20] -INFO: [Synth 8-6157] synthesizing module 'bg_tile' [C:/Users/james/Documents/vga/sprite_modules/bg_tile.v:20] -INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/vga/sprite_modules/bg_tile.v:40] -INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/vga/sprite_modules/bg_tile.v:43] -INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/vga/sprite_modules/bg_tile.v:85] -INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/vga/sprite_modules/bg_tile.v:127] -INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/vga/sprite_modules/bg_tile.v:169] -INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/vga/sprite_modules/bg_tile.v:211] -INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/vga/sprite_modules/bg_tile.v:253] -INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/vga/sprite_modules/bg_tile.v:295] -INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/vga/sprite_modules/bg_tile.v:337] -INFO: [Synth 8-6155] done synthesizing module 'bg_tile' (0#1) [C:/Users/james/Documents/vga/sprite_modules/bg_tile.v:20] -INFO: [Synth 8-6157] synthesizing module 'logo' [C:/Users/james/Documents/vga/sprite_modules/logo.v:20] -INFO: [Synth 8-6155] done synthesizing module 'logo' (0#1) [C:/Users/james/Documents/vga/sprite_modules/logo.v:20] -INFO: [Synth 8-6157] synthesizing module 'board' [C:/Users/james/Documents/vga/sprite_modules/board.v:20] -INFO: [Synth 8-6155] done synthesizing module 'board' (0#1) [C:/Users/james/Documents/vga/sprite_modules/board.v:20] -INFO: [Synth 8-6157] synthesizing module 'reds_turn' [C:/Users/james/Documents/vga/sprite_modules/reds_turn.v:20] -INFO: [Synth 8-6155] done synthesizing module 'reds_turn' (0#1) [C:/Users/james/Documents/vga/sprite_modules/reds_turn.v:20] -INFO: [Synth 8-6157] synthesizing module 'yellows_turn' [C:/Users/james/Documents/vga/sprite_modules/yellows_turn.v:20] -INFO: [Synth 8-6155] done synthesizing module 'yellows_turn' (0#1) [C:/Users/james/Documents/vga/sprite_modules/yellows_turn.v:20] -INFO: [Synth 8-6157] synthesizing module 'red_wins' [C:/Users/james/Documents/vga/sprite_modules/red_wins.v:20] -INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/vga/sprite_modules/red_wins.v:43] -INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/vga/sprite_modules/red_wins.v:309] -INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/vga/sprite_modules/red_wins.v:575] -INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/vga/sprite_modules/red_wins.v:841] -INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/vga/sprite_modules/red_wins.v:1107] -INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/vga/sprite_modules/red_wins.v:1373] -INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/vga/sprite_modules/red_wins.v:1639] -INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/vga/sprite_modules/red_wins.v:1905] -INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/vga/sprite_modules/red_wins.v:2171] -INFO: [Synth 8-6155] done synthesizing module 'red_wins' (0#1) [C:/Users/james/Documents/vga/sprite_modules/red_wins.v:20] -INFO: [Synth 8-6157] synthesizing module 'yellow_wins' [C:/Users/james/Documents/vga/sprite_modules/yellow_wins.v:20] -INFO: [Synth 8-6155] done synthesizing module 'yellow_wins' (0#1) [C:/Users/james/Documents/vga/sprite_modules/yellow_wins.v:20] -INFO: [Synth 8-6157] synthesizing module 'tie_game' [C:/Users/james/Documents/vga/sprite_modules/tie_game.v:20] -INFO: [Synth 8-6155] done synthesizing module 'tie_game' (0#1) [C:/Users/james/Documents/vga/sprite_modules/tie_game.v:20] -INFO: [Synth 8-6157] synthesizing module 'red_indicator' [C:/Users/james/Documents/vga/sprite_modules/red_indicator.v:20] -INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/vga/sprite_modules/red_indicator.v:43] -INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/vga/sprite_modules/red_indicator.v:85] -INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/vga/sprite_modules/red_indicator.v:127] -INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/vga/sprite_modules/red_indicator.v:169] -INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/vga/sprite_modules/red_indicator.v:211] -INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/vga/sprite_modules/red_indicator.v:253] -INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/vga/sprite_modules/red_indicator.v:295] -INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/vga/sprite_modules/red_indicator.v:337] -INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/vga/sprite_modules/red_indicator.v:379] -INFO: [Synth 8-6155] done synthesizing module 'red_indicator' (0#1) [C:/Users/james/Documents/vga/sprite_modules/red_indicator.v:20] -INFO: [Synth 8-6157] synthesizing module 'yellow_indicator' [C:/Users/james/Documents/vga/sprite_modules/yellow_indicator.v:20] -INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/vga/sprite_modules/yellow_indicator.v:43] -INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/vga/sprite_modules/yellow_indicator.v:85] -INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/vga/sprite_modules/yellow_indicator.v:127] -INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/vga/sprite_modules/yellow_indicator.v:169] -INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/vga/sprite_modules/yellow_indicator.v:211] -INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/vga/sprite_modules/yellow_indicator.v:253] -INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/vga/sprite_modules/yellow_indicator.v:295] -INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/vga/sprite_modules/yellow_indicator.v:337] -INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/vga/sprite_modules/yellow_indicator.v:379] -INFO: [Synth 8-6155] done synthesizing module 'yellow_indicator' (0#1) [C:/Users/james/Documents/vga/sprite_modules/yellow_indicator.v:20] -INFO: [Synth 8-6155] done synthesizing module 'vga' (0#1) [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/vga.v:23] -WARNING: [Synth 8-6014] Unused sequential element xOffset_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/red_piece.v:34] -WARNING: [Synth 8-6014] Unused sequential element yOffset_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/red_piece.v:35] -WARNING: [Synth 8-6014] Unused sequential element xSprite_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/red_piece.v:36] -WARNING: [Synth 8-6014] Unused sequential element ySprite_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/red_piece.v:37] -WARNING: [Synth 8-6014] Unused sequential element inBounds_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/red_piece.v:38] -WARNING: [Synth 8-6014] Unused sequential element xOffset_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/yellow_piece.v:34] -WARNING: [Synth 8-6014] Unused sequential element yOffset_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/yellow_piece.v:35] -WARNING: [Synth 8-6014] Unused sequential element xSprite_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/yellow_piece.v:36] -WARNING: [Synth 8-6014] Unused sequential element ySprite_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/yellow_piece.v:37] -WARNING: [Synth 8-6014] Unused sequential element inBounds_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/yellow_piece.v:38] -WARNING: [Synth 8-6014] Unused sequential element redPieceXOffset_reg[13] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:48] -WARNING: [Synth 8-6014] Unused sequential element redPieceXOffset_reg[12] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:48] -WARNING: [Synth 8-6014] Unused sequential element redPieceXOffset_reg[11] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:48] -WARNING: [Synth 8-6014] Unused sequential element redPieceXOffset_reg[10] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:48] -WARNING: [Synth 8-6014] Unused sequential element redPieceXOffset_reg[9] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:48] -WARNING: [Synth 8-6014] Unused sequential element redPieceXOffset_reg[8] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:48] -WARNING: [Synth 8-6014] Unused sequential element redPieceXOffset_reg[7] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:48] -WARNING: [Synth 8-6014] Unused sequential element redPieceXOffset_reg[6] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:48] -WARNING: [Synth 8-6014] Unused sequential element redPieceXOffset_reg[5] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:48] -WARNING: [Synth 8-6014] Unused sequential element redPieceXOffset_reg[4] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:48] -WARNING: [Synth 8-6014] Unused sequential element redPieceXOffset_reg[3] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:48] -WARNING: [Synth 8-6014] Unused sequential element redPieceXOffset_reg[2] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:48] -WARNING: [Synth 8-6014] Unused sequential element redPieceXOffset_reg[1] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:48] -WARNING: [Synth 8-6014] Unused sequential element redPieceXOffset_reg[0] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:48] -WARNING: [Synth 8-6014] Unused sequential element redPieceYOffset_reg[14] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:47] -WARNING: [Synth 8-6014] Unused sequential element redPieceYOffset_reg[13] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:47] -WARNING: [Synth 8-6014] Unused sequential element redPieceYOffset_reg[12] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:47] -WARNING: [Synth 8-6014] Unused sequential element redPieceYOffset_reg[11] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:47] -WARNING: [Synth 8-6014] Unused sequential element redPieceYOffset_reg[10] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:47] -WARNING: [Synth 8-6014] Unused sequential element redPieceYOffset_reg[9] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:47] -WARNING: [Synth 8-6014] Unused sequential element redPieceYOffset_reg[8] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:47] -WARNING: [Synth 8-6014] Unused sequential element redPieceYOffset_reg[7] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:47] -WARNING: [Synth 8-6014] Unused sequential element redPieceYOffset_reg[6] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:47] -WARNING: [Synth 8-6014] Unused sequential element redPieceYOffset_reg[5] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:47] -WARNING: [Synth 8-6014] Unused sequential element redPieceYOffset_reg[4] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:47] -WARNING: [Synth 8-6014] Unused sequential element redPieceYOffset_reg[3] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:47] -WARNING: [Synth 8-6014] Unused sequential element redPieceYOffset_reg[2] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:47] -WARNING: [Synth 8-6014] Unused sequential element redPieceYOffset_reg[1] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:47] -WARNING: [Synth 8-6014] Unused sequential element redPieceYOffset_reg[0] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:47] -WARNING: [Synth 8-6014] Unused sequential element yellowPieceXOffset_reg[20] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:50] -WARNING: [Synth 8-6014] Unused sequential element yellowPieceXOffset_reg[19] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:50] -WARNING: [Synth 8-6014] Unused sequential element yellowPieceXOffset_reg[18] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:50] -WARNING: [Synth 8-6014] Unused sequential element yellowPieceXOffset_reg[17] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:50] -WARNING: [Synth 8-6014] Unused sequential element yellowPieceXOffset_reg[16] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:50] -WARNING: [Synth 8-6014] Unused sequential element yellowPieceXOffset_reg[15] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:50] -WARNING: [Synth 8-6014] Unused sequential element yellowPieceXOffset_reg[14] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:50] -WARNING: [Synth 8-6014] Unused sequential element yellowPieceXOffset_reg[13] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:50] -WARNING: [Synth 8-6014] Unused sequential element yellowPieceXOffset_reg[12] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:50] -WARNING: [Synth 8-6014] Unused sequential element yellowPieceXOffset_reg[11] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:50] -WARNING: [Synth 8-6014] Unused sequential element yellowPieceXOffset_reg[10] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:50] -WARNING: [Synth 8-6014] Unused sequential element yellowPieceXOffset_reg[9] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:50] -WARNING: [Synth 8-6014] Unused sequential element yellowPieceXOffset_reg[8] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:50] -WARNING: [Synth 8-6014] Unused sequential element yellowPieceXOffset_reg[7] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:50] -WARNING: [Synth 8-6014] Unused sequential element yellowPieceXOffset_reg[6] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:50] -WARNING: [Synth 8-6014] Unused sequential element yellowPieceXOffset_reg[5] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:50] -WARNING: [Synth 8-6014] Unused sequential element yellowPieceXOffset_reg[4] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:50] -WARNING: [Synth 8-6014] Unused sequential element yellowPieceXOffset_reg[3] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:50] -WARNING: [Synth 8-6014] Unused sequential element yellowPieceXOffset_reg[2] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:50] -WARNING: [Synth 8-6014] Unused sequential element yellowPieceXOffset_reg[1] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:50] -WARNING: [Synth 8-6014] Unused sequential element yellowPieceXOffset_reg[0] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:50] -WARNING: [Synth 8-6014] Unused sequential element yellowPieceYOffset_reg[20] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:49] -WARNING: [Synth 8-6014] Unused sequential element yellowPieceYOffset_reg[0] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:49] -WARNING: [Synth 8-6014] Unused sequential element showLogo_reg was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:65] -WARNING: [Synth 8-3848] Net showRedsTurn in module/entity TESTcore_design does not have driver. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:27] -WARNING: [Synth 8-3848] Net showYellowsTurn in module/entity TESTcore_design does not have driver. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:28] -WARNING: [Synth 8-3848] Net showRedWins in module/entity TESTcore_design does not have driver. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:29] -WARNING: [Synth 8-3848] Net showYellowWins in module/entity TESTcore_design does not have driver. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:30] -WARNING: [Synth 8-3848] Net showTieGame in module/entity TESTcore_design does not have driver. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:31] -WARNING: [Synth 8-3848] Net showRedIndicator in module/entity TESTcore_design does not have driver. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:32] -WARNING: [Synth 8-3848] Net redIndicatorXOffset in module/entity TESTcore_design does not have driver. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:33] -WARNING: [Synth 8-3848] Net showYellowIndicator in module/entity TESTcore_design does not have driver. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:34] -WARNING: [Synth 8-3848] Net yellowIndicatorXOffset in module/entity TESTcore_design does not have driver. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:35] -WARNING: [Synth 8-6014] Unused sequential element xOffset_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/corner_border_check.v:34] -WARNING: [Synth 8-6014] Unused sequential element yOffset_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/corner_border_check.v:35] -WARNING: [Synth 8-6014] Unused sequential element xSprite_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/corner_border_check.v:36] -WARNING: [Synth 8-6014] Unused sequential element ySprite_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/corner_border_check.v:37] -WARNING: [Synth 8-6014] Unused sequential element inBounds_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/corner_border_check.v:38] -WARNING: [Synth 8-6014] Unused sequential element xOffset_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/bg_tile.v:34] -WARNING: [Synth 8-6014] Unused sequential element yOffset_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/bg_tile.v:35] -WARNING: [Synth 8-6014] Unused sequential element xSprite_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/bg_tile.v:36] -WARNING: [Synth 8-6014] Unused sequential element ySprite_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/bg_tile.v:37] -WARNING: [Synth 8-6014] Unused sequential element inBounds_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/bg_tile.v:38] -WARNING: [Synth 8-6014] Unused sequential element xOffset_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/logo.v:34] -WARNING: [Synth 8-6014] Unused sequential element yOffset_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/logo.v:35] -WARNING: [Synth 8-6014] Unused sequential element xSprite_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/logo.v:36] -WARNING: [Synth 8-6014] Unused sequential element ySprite_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/logo.v:37] -WARNING: [Synth 8-6014] Unused sequential element inBounds_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/logo.v:38] -WARNING: [Synth 8-6014] Unused sequential element xOffset_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/board.v:34] -WARNING: [Synth 8-6014] Unused sequential element yOffset_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/board.v:35] -WARNING: [Synth 8-6014] Unused sequential element xSprite_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/board.v:36] -WARNING: [Synth 8-6014] Unused sequential element ySprite_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/board.v:37] -WARNING: [Synth 8-6014] Unused sequential element inBounds_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/board.v:38] -WARNING: [Synth 8-6014] Unused sequential element xOffset_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/reds_turn.v:34] -WARNING: [Synth 8-6014] Unused sequential element yOffset_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/reds_turn.v:35] -WARNING: [Synth 8-6014] Unused sequential element xSprite_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/reds_turn.v:36] -WARNING: [Synth 8-6014] Unused sequential element ySprite_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/reds_turn.v:37] -WARNING: [Synth 8-6014] Unused sequential element inBounds_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/reds_turn.v:38] -WARNING: [Synth 8-6014] Unused sequential element xOffset_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/yellows_turn.v:34] -WARNING: [Synth 8-6014] Unused sequential element yOffset_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/yellows_turn.v:35] -WARNING: [Synth 8-6014] Unused sequential element xSprite_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/yellows_turn.v:36] -WARNING: [Synth 8-6014] Unused sequential element ySprite_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/yellows_turn.v:37] -WARNING: [Synth 8-6014] Unused sequential element inBounds_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/yellows_turn.v:38] -WARNING: [Synth 8-6014] Unused sequential element xOffset_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/red_wins.v:34] -WARNING: [Synth 8-6014] Unused sequential element yOffset_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/red_wins.v:35] -WARNING: [Synth 8-6014] Unused sequential element xSprite_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/red_wins.v:36] -WARNING: [Synth 8-6014] Unused sequential element ySprite_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/red_wins.v:37] -WARNING: [Synth 8-6014] Unused sequential element inBounds_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/red_wins.v:38] -WARNING: [Synth 8-6014] Unused sequential element xOffset_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/yellow_wins.v:34] -WARNING: [Synth 8-6014] Unused sequential element yOffset_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/yellow_wins.v:35] -INFO: [Common 17-14] Message 'Synth 8-6014' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [Synth 8-7129] Port showRedsTurn in module TESTcore_design is either unconnected or has no load -WARNING: [Synth 8-7129] Port showYellowsTurn in module TESTcore_design is either unconnected or has no load -WARNING: [Synth 8-7129] Port showRedWins in module TESTcore_design is either unconnected or has no load -WARNING: [Synth 8-7129] Port showYellowWins in module TESTcore_design is either unconnected or has no load -WARNING: [Synth 8-7129] Port showTieGame in module TESTcore_design is either unconnected or has no load -WARNING: [Synth 8-7129] Port showRedIndicator in module TESTcore_design is either unconnected or has no load -WARNING: [Synth 8-7129] Port redIndicatorXOffset[9] in module TESTcore_design is either unconnected or has no load -WARNING: [Synth 8-7129] Port redIndicatorXOffset[8] in module TESTcore_design is either unconnected or has no load -WARNING: [Synth 8-7129] Port redIndicatorXOffset[7] in module TESTcore_design is either unconnected or has no load -WARNING: [Synth 8-7129] Port redIndicatorXOffset[6] in module TESTcore_design is either unconnected or has no load -WARNING: [Synth 8-7129] Port redIndicatorXOffset[5] in module TESTcore_design is either unconnected or has no load -WARNING: [Synth 8-7129] Port redIndicatorXOffset[4] in module TESTcore_design is either unconnected or has no load -WARNING: [Synth 8-7129] Port redIndicatorXOffset[3] in module TESTcore_design is either unconnected or has no load -WARNING: [Synth 8-7129] Port redIndicatorXOffset[2] in module TESTcore_design is either unconnected or has no load -WARNING: [Synth 8-7129] Port redIndicatorXOffset[1] in module TESTcore_design is either unconnected or has no load -WARNING: [Synth 8-7129] Port redIndicatorXOffset[0] in module TESTcore_design is either unconnected or has no load -WARNING: [Synth 8-7129] Port showYellowIndicator in module TESTcore_design is either unconnected or has no load -WARNING: [Synth 8-7129] Port yellowIndicatorXOffset[9] in module TESTcore_design is either unconnected or has no load -WARNING: [Synth 8-7129] Port yellowIndicatorXOffset[8] in module TESTcore_design is either unconnected or has no load -WARNING: [Synth 8-7129] Port yellowIndicatorXOffset[7] in module TESTcore_design is either unconnected or has no load -WARNING: [Synth 8-7129] Port yellowIndicatorXOffset[6] in module TESTcore_design is either unconnected or has no load -WARNING: [Synth 8-7129] Port yellowIndicatorXOffset[5] in module TESTcore_design is either unconnected or has no load -WARNING: [Synth 8-7129] Port yellowIndicatorXOffset[4] in module TESTcore_design is either unconnected or has no load -WARNING: [Synth 8-7129] Port yellowIndicatorXOffset[3] in module TESTcore_design is either unconnected or has no load -WARNING: [Synth 8-7129] Port yellowIndicatorXOffset[2] in module TESTcore_design is either unconnected or has no load -WARNING: [Synth 8-7129] Port yellowIndicatorXOffset[1] in module TESTcore_design is either unconnected or has no load -WARNING: [Synth 8-7129] Port yellowIndicatorXOffset[0] in module TESTcore_design is either unconnected or has no load ---------------------------------------------------------------------------------- -Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:10 . Memory (MB): peak = 1598.531 ; gain = 621.055 +INFO: [Synth 8-7075] Helper process launched with PID 31760 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:04 . Memory (MB): peak = 1417.359 ; gain = 440.781 +--------------------------------------------------------------------------------- +INFO: [Synth 8-11241] undeclared symbol 'hValid', assumed default net type 'wire' [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/vga.v:51] +INFO: [Synth 8-11241] undeclared symbol 'vValid', assumed default net type 'wire' [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/vga.v:119] +INFO: [Synth 8-11241] undeclared symbol 'reset', assumed default net type 'wire' [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/vga.v:185] +INFO: [Synth 8-6157] synthesizing module 'vga' [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/vga.v:23] +INFO: [Synth 8-6157] synthesizing module 'red_piece' [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_piece.v:20] +INFO: [Synth 8-6155] done synthesizing module 'red_piece' (0#1) [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_piece.v:20] +INFO: [Synth 8-6157] synthesizing module 'yellow_piece' [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_piece.v:20] +INFO: [Synth 8-6155] done synthesizing module 'yellow_piece' (0#1) [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_piece.v:20] +INFO: [Synth 8-6157] synthesizing module 'yellow_win_highlight' [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_win_highlight.v:20] +INFO: [Synth 8-6155] done synthesizing module 'yellow_win_highlight' (0#1) [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_win_highlight.v:20] +INFO: [Synth 8-6157] synthesizing module 'red_win_highlight' [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_win_highlight.v:20] +INFO: [Synth 8-6155] done synthesizing module 'red_win_highlight' (0#1) [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_win_highlight.v:20] +INFO: [Synth 8-155] case statement is not full and has no default [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/vga.v:73] +INFO: [Synth 8-155] case statement is not full and has no default [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/vga.v:141] +INFO: [Synth 8-6157] synthesizing module 'connect4_core_design' [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:25] +WARNING: [Synth 8-6090] variable 'showRedWinIndicator' is written by both blocking and non-blocking assignments, entire logic could be removed [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:185] +WARNING: [Synth 8-6090] variable 'showYellowWinIndicator' is written by both blocking and non-blocking assignments, entire logic could be removed [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:186] +WARNING: [Synth 8-6090] variable 'showRedWinIndicator' is written by both blocking and non-blocking assignments, entire logic could be removed [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:442] +WARNING: [Synth 8-6090] variable 'showYellowWinIndicator' is written by both blocking and non-blocking assignments, entire logic could be removed [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:485] +INFO: [Synth 8-155] case statement is not full and has no default [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:508] +INFO: [Synth 8-155] case statement is not full and has no default [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:540] +INFO: [Synth 8-155] case statement is not full and has no default [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:576] +INFO: [Synth 8-155] case statement is not full and has no default [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:608] +INFO: [Synth 8-155] case statement is not full and has no default [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:192] +INFO: [Synth 8-6155] done synthesizing module 'connect4_core_design' (0#1) [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:25] +INFO: [Synth 8-6157] synthesizing module 'corner_border_check' [C:/Users/james/Documents/fpga-connect4/sprite_modules/corner_border_check.v:20] +INFO: [Synth 8-6155] done synthesizing module 'corner_border_check' (0#1) [C:/Users/james/Documents/fpga-connect4/sprite_modules/corner_border_check.v:20] +INFO: [Synth 8-6157] synthesizing module 'bg_tile' [C:/Users/james/Documents/fpga-connect4/sprite_modules/bg_tile.v:20] +INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/fpga-connect4/sprite_modules/bg_tile.v:40] +INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/fpga-connect4/sprite_modules/bg_tile.v:43] +INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/fpga-connect4/sprite_modules/bg_tile.v:85] +INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/fpga-connect4/sprite_modules/bg_tile.v:127] +INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/fpga-connect4/sprite_modules/bg_tile.v:169] +INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/fpga-connect4/sprite_modules/bg_tile.v:211] +INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/fpga-connect4/sprite_modules/bg_tile.v:253] +INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/fpga-connect4/sprite_modules/bg_tile.v:295] +INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/fpga-connect4/sprite_modules/bg_tile.v:337] +INFO: [Synth 8-6155] done synthesizing module 'bg_tile' (0#1) [C:/Users/james/Documents/fpga-connect4/sprite_modules/bg_tile.v:20] +INFO: [Synth 8-6157] synthesizing module 'logo' [C:/Users/james/Documents/fpga-connect4/sprite_modules/logo.v:20] +INFO: [Synth 8-6155] done synthesizing module 'logo' (0#1) [C:/Users/james/Documents/fpga-connect4/sprite_modules/logo.v:20] +INFO: [Synth 8-6157] synthesizing module 'board' [C:/Users/james/Documents/fpga-connect4/sprite_modules/board.v:20] +INFO: [Synth 8-6155] done synthesizing module 'board' (0#1) [C:/Users/james/Documents/fpga-connect4/sprite_modules/board.v:20] +INFO: [Synth 8-6157] synthesizing module 'reds_turn' [C:/Users/james/Documents/fpga-connect4/sprite_modules/reds_turn.v:20] +INFO: [Synth 8-6155] done synthesizing module 'reds_turn' (0#1) [C:/Users/james/Documents/fpga-connect4/sprite_modules/reds_turn.v:20] +INFO: [Synth 8-6157] synthesizing module 'yellows_turn' [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellows_turn.v:20] +INFO: [Synth 8-6155] done synthesizing module 'yellows_turn' (0#1) [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellows_turn.v:20] +INFO: [Synth 8-6157] synthesizing module 'red_wins' [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_wins.v:20] +INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_wins.v:43] +INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_wins.v:309] +INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_wins.v:575] +INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_wins.v:841] +INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_wins.v:1107] +INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_wins.v:1373] +INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_wins.v:1639] +INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_wins.v:1905] +INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_wins.v:2171] +INFO: [Synth 8-6155] done synthesizing module 'red_wins' (0#1) [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_wins.v:20] +INFO: [Synth 8-6157] synthesizing module 'yellow_wins' [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_wins.v:20] +INFO: [Synth 8-6155] done synthesizing module 'yellow_wins' (0#1) [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_wins.v:20] +INFO: [Synth 8-6157] synthesizing module 'tie_game' [C:/Users/james/Documents/fpga-connect4/sprite_modules/tie_game.v:20] +INFO: [Synth 8-6155] done synthesizing module 'tie_game' (0#1) [C:/Users/james/Documents/fpga-connect4/sprite_modules/tie_game.v:20] +INFO: [Synth 8-6157] synthesizing module 'red_indicator' [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_indicator.v:20] +INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_indicator.v:43] +INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_indicator.v:85] +INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_indicator.v:127] +INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_indicator.v:169] +INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_indicator.v:211] +INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_indicator.v:253] +INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_indicator.v:295] +INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_indicator.v:337] +INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_indicator.v:379] +INFO: [Synth 8-6155] done synthesizing module 'red_indicator' (0#1) [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_indicator.v:20] +INFO: [Synth 8-6157] synthesizing module 'yellow_indicator' [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_indicator.v:20] +INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_indicator.v:43] +INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_indicator.v:85] +INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_indicator.v:127] +INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_indicator.v:169] +INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_indicator.v:211] +INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_indicator.v:253] +INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_indicator.v:295] +INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_indicator.v:337] +INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_indicator.v:379] +INFO: [Synth 8-6155] done synthesizing module 'yellow_indicator' (0#1) [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_indicator.v:20] +INFO: [Synth 8-6155] done synthesizing module 'vga' (0#1) [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/vga.v:23] +WARNING: [Synth 8-6014] Unused sequential element xOffset_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_piece.v:34] +WARNING: [Synth 8-6014] Unused sequential element yOffset_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_piece.v:35] +WARNING: [Synth 8-6014] Unused sequential element xSprite_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_piece.v:36] +WARNING: [Synth 8-6014] Unused sequential element ySprite_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_piece.v:37] +WARNING: [Synth 8-6014] Unused sequential element inBounds_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_piece.v:38] +WARNING: [Synth 8-6014] Unused sequential element xOffset_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_piece.v:34] +WARNING: [Synth 8-6014] Unused sequential element yOffset_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_piece.v:35] +WARNING: [Synth 8-6014] Unused sequential element xSprite_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_piece.v:36] +WARNING: [Synth 8-6014] Unused sequential element ySprite_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_piece.v:37] +WARNING: [Synth 8-6014] Unused sequential element inBounds_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_piece.v:38] +WARNING: [Synth 8-6014] Unused sequential element xOffset_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_win_highlight.v:34] +WARNING: [Synth 8-6014] Unused sequential element yOffset_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_win_highlight.v:35] +WARNING: [Synth 8-6014] Unused sequential element xSprite_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_win_highlight.v:36] +WARNING: [Synth 8-6014] Unused sequential element ySprite_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_win_highlight.v:37] +WARNING: [Synth 8-6014] Unused sequential element inBounds_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_win_highlight.v:38] +WARNING: [Synth 8-6014] Unused sequential element xOffset_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_win_highlight.v:34] +WARNING: [Synth 8-6014] Unused sequential element yOffset_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_win_highlight.v:35] +WARNING: [Synth 8-6014] Unused sequential element xSprite_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_win_highlight.v:36] +WARNING: [Synth 8-6014] Unused sequential element ySprite_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_win_highlight.v:37] +WARNING: [Synth 8-6014] Unused sequential element inBounds_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_win_highlight.v:38] +WARNING: [Synth 8-6014] Unused sequential element checkWinsRed.a_reg was removed. [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:421] +WARNING: [Synth 8-6014] Unused sequential element checkWinsYellow.a_reg was removed. [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:464] +WARNING: [Synth 8-6014] Unused sequential element animateResetPieces.r_reg was removed. [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:774] +WARNING: [Synth 8-6014] Unused sequential element animateResetPieces.c_reg was removed. [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:775] +WARNING: [Synth 8-7137] Register redPieceYOffset_reg[20] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:90] +WARNING: [Synth 8-7137] Register redPieceYOffset_reg[19] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:90] +WARNING: [Synth 8-7137] Register redPieceYOffset_reg[18] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:90] +WARNING: [Synth 8-7137] Register redPieceYOffset_reg[17] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:90] +WARNING: [Synth 8-7137] Register redPieceYOffset_reg[16] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:90] +WARNING: [Synth 8-7137] Register redPieceYOffset_reg[15] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:90] +WARNING: [Synth 8-7137] Register redPieceYOffset_reg[14] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:90] +WARNING: [Synth 8-7137] Register redPieceYOffset_reg[13] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:90] +WARNING: [Synth 8-7137] Register redPieceYOffset_reg[12] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:90] +WARNING: [Synth 8-7137] Register redPieceYOffset_reg[11] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:90] +WARNING: [Synth 8-7137] Register redPieceYOffset_reg[10] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:90] +WARNING: [Synth 8-7137] Register redPieceYOffset_reg[9] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:90] +WARNING: [Synth 8-7137] Register redPieceYOffset_reg[8] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:90] +WARNING: [Synth 8-7137] Register redPieceYOffset_reg[7] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:90] +WARNING: [Synth 8-7137] Register redPieceYOffset_reg[6] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:90] +WARNING: [Synth 8-7137] Register redPieceYOffset_reg[5] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:90] +WARNING: [Synth 8-7137] Register redPieceYOffset_reg[4] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:90] +WARNING: [Synth 8-7137] Register redPieceYOffset_reg[3] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:90] +WARNING: [Synth 8-7137] Register redPieceYOffset_reg[2] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:90] +WARNING: [Synth 8-7137] Register redPieceYOffset_reg[1] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:90] +WARNING: [Synth 8-7137] Register redPieceYOffset_reg[0] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:90] +WARNING: [Synth 8-7137] Register yellowPieceYOffset_reg[20] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:92] +WARNING: [Synth 8-7137] Register yellowPieceYOffset_reg[19] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:92] +WARNING: [Synth 8-7137] Register yellowPieceYOffset_reg[18] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:92] +WARNING: [Synth 8-7137] Register yellowPieceYOffset_reg[17] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:92] +WARNING: [Synth 8-7137] Register yellowPieceYOffset_reg[16] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:92] +WARNING: [Synth 8-7137] Register yellowPieceYOffset_reg[15] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:92] +WARNING: [Synth 8-7137] Register yellowPieceYOffset_reg[14] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:92] +WARNING: [Synth 8-7137] Register yellowPieceYOffset_reg[13] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:92] +WARNING: [Synth 8-7137] Register yellowPieceYOffset_reg[12] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:92] +WARNING: [Synth 8-7137] Register yellowPieceYOffset_reg[11] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:92] +WARNING: [Synth 8-7137] Register yellowPieceYOffset_reg[10] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:92] +WARNING: [Synth 8-7137] Register yellowPieceYOffset_reg[9] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:92] +WARNING: [Synth 8-7137] Register yellowPieceYOffset_reg[8] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:92] +WARNING: [Synth 8-7137] Register yellowPieceYOffset_reg[7] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:92] +WARNING: [Synth 8-7137] Register yellowPieceYOffset_reg[6] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:92] +WARNING: [Synth 8-7137] Register yellowPieceYOffset_reg[5] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:92] +WARNING: [Synth 8-7137] Register yellowPieceYOffset_reg[4] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:92] +WARNING: [Synth 8-7137] Register yellowPieceYOffset_reg[3] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:92] +WARNING: [Synth 8-7137] Register yellowPieceYOffset_reg[2] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:92] +WARNING: [Synth 8-7137] Register yellowPieceYOffset_reg[1] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:92] +WARNING: [Synth 8-7137] Register yellowPieceYOffset_reg[0] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:92] +WARNING: [Synth 8-7137] Register game_over_reg in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:167] +WARNING: [Synth 8-7137] Register column_reg in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:169] +WARNING: [Synth 8-7137] Register current_player_reg in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:170] +WARNING: [Synth 8-7137] Register update_reg in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:252] +WARNING: [Synth 8-6014] Unused sequential element xOffset_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/corner_border_check.v:34] +WARNING: [Synth 8-6014] Unused sequential element yOffset_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/corner_border_check.v:35] +WARNING: [Synth 8-6014] Unused sequential element xSprite_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/corner_border_check.v:36] +WARNING: [Synth 8-6014] Unused sequential element ySprite_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/corner_border_check.v:37] +WARNING: [Synth 8-6014] Unused sequential element inBounds_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/corner_border_check.v:38] +WARNING: [Synth 8-6014] Unused sequential element xOffset_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/bg_tile.v:34] +WARNING: [Synth 8-6014] Unused sequential element yOffset_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/bg_tile.v:35] +WARNING: [Synth 8-6014] Unused sequential element xSprite_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/bg_tile.v:36] +WARNING: [Synth 8-6014] Unused sequential element ySprite_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/bg_tile.v:37] +WARNING: [Synth 8-6014] Unused sequential element inBounds_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/bg_tile.v:38] +WARNING: [Synth 8-6014] Unused sequential element xOffset_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/logo.v:34] +WARNING: [Synth 8-6014] Unused sequential element yOffset_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/logo.v:35] +WARNING: [Synth 8-6014] Unused sequential element xSprite_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/logo.v:36] +WARNING: [Synth 8-6014] Unused sequential element ySprite_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/logo.v:37] +WARNING: [Synth 8-6014] Unused sequential element inBounds_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/logo.v:38] +WARNING: [Synth 8-6014] Unused sequential element xOffset_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/board.v:34] +WARNING: [Synth 8-6014] Unused sequential element yOffset_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/board.v:35] +WARNING: [Synth 8-6014] Unused sequential element xSprite_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/board.v:36] +WARNING: [Synth 8-6014] Unused sequential element ySprite_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/board.v:37] +WARNING: [Synth 8-6014] Unused sequential element inBounds_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/board.v:38] +WARNING: [Synth 8-6014] Unused sequential element xOffset_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/reds_turn.v:34] +WARNING: [Synth 8-6014] Unused sequential element yOffset_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/reds_turn.v:35] +WARNING: [Synth 8-6014] Unused sequential element xSprite_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/reds_turn.v:36] +WARNING: [Synth 8-6014] Unused sequential element ySprite_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/reds_turn.v:37] +WARNING: [Synth 8-6014] Unused sequential element inBounds_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/reds_turn.v:38] +WARNING: [Synth 8-6014] Unused sequential element xOffset_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellows_turn.v:34] +WARNING: [Synth 8-6014] Unused sequential element yOffset_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellows_turn.v:35] +WARNING: [Synth 8-6014] Unused sequential element xSprite_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellows_turn.v:36] +WARNING: [Synth 8-6014] Unused sequential element ySprite_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellows_turn.v:37] +WARNING: [Synth 8-6014] Unused sequential element inBounds_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellows_turn.v:38] +WARNING: [Synth 8-6014] Unused sequential element xOffset_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_wins.v:34] +WARNING: [Synth 8-6014] Unused sequential element yOffset_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_wins.v:35] +WARNING: [Synth 8-6014] Unused sequential element xSprite_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_wins.v:36] +WARNING: [Synth 8-6014] Unused sequential element ySprite_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_wins.v:37] +WARNING: [Synth 8-6014] Unused sequential element inBounds_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_wins.v:38] +WARNING: [Synth 8-6014] Unused sequential element xOffset_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_wins.v:34] +WARNING: [Synth 8-6014] Unused sequential element yOffset_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_wins.v:35] +WARNING: [Synth 8-6014] Unused sequential element xSprite_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_wins.v:36] +WARNING: [Synth 8-6014] Unused sequential element ySprite_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_wins.v:37] +WARNING: [Synth 8-6014] Unused sequential element inBounds_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_wins.v:38] +WARNING: [Synth 8-6014] Unused sequential element xOffset_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/tie_game.v:34] +WARNING: [Synth 8-6014] Unused sequential element yOffset_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/tie_game.v:35] +WARNING: [Synth 8-6014] Unused sequential element xSprite_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/tie_game.v:36] +WARNING: [Synth 8-6014] Unused sequential element ySprite_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/tie_game.v:37] +WARNING: [Synth 8-6014] Unused sequential element inBounds_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/tie_game.v:38] +WARNING: [Synth 8-6014] Unused sequential element xOffset_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_indicator.v:34] +WARNING: [Synth 8-6014] Unused sequential element yOffset_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_indicator.v:35] +WARNING: [Synth 8-6014] Unused sequential element xSprite_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_indicator.v:36] +WARNING: [Synth 8-6014] Unused sequential element ySprite_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_indicator.v:37] +WARNING: [Synth 8-6014] Unused sequential element inBounds_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_indicator.v:38] +WARNING: [Synth 8-6014] Unused sequential element xOffset_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_indicator.v:34] +WARNING: [Synth 8-6014] Unused sequential element yOffset_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_indicator.v:35] +WARNING: [Synth 8-6014] Unused sequential element xSprite_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_indicator.v:36] +WARNING: [Synth 8-6014] Unused sequential element ySprite_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_indicator.v:37] +WARNING: [Synth 8-6014] Unused sequential element inBounds_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_indicator.v:38] +WARNING: [Synth 8-6014] Unused sequential element winIndicatorIndex_reg was removed. [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/vga.v:369] +WARNING: [Synth 8-6014] Unused sequential element frontIndex_reg was removed. [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/vga.v:383] +WARNING: [Synth 8-6014] Unused sequential element pieceIndex_reg was removed. [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/vga.v:416] +WARNING: [Synth 8-6014] Unused sequential element finalIndex_reg was removed. [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/vga.v:429] +WARNING: [Synth 8-7129] Port BtnU in module vga is either unconnected or has no load +WARNING: [Synth 8-7129] Port BtnD in module vga is either unconnected or has no load +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:38 ; elapsed = 00:01:12 . Memory (MB): peak = 2413.395 ; gain = 1436.816 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:04 ; elapsed = 00:00:10 . Memory (MB): peak = 1598.531 ; gain = 621.055 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:40 ; elapsed = 00:01:16 . Memory (MB): peak = 2413.395 ; gain = 1436.816 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:10 . Memory (MB): peak = 1598.531 ; gain = 621.055 +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:40 ; elapsed = 00:01:16 . Memory (MB): peak = 2413.395 ; gain = 1436.816 --------------------------------------------------------------------------------- -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.026 . Memory (MB): peak = 1598.531 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2413.395 ; gain = 0.000 INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine -Parsing XDC File [C:/Users/james/Documents/vga/vga.srcs/constrs_1/new/vga.xdc] -CRITICAL WARNING: [Common 17-165] Too many positional options when parsing 'period', please type 'create_clock -help' for usage info. [C:/Users/james/Documents/vga/vga.srcs/constrs_1/new/vga.xdc:7] -Finished Parsing XDC File [C:/Users/james/Documents/vga/vga.srcs/constrs_1/new/vga.xdc] -INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Users/james/Documents/vga/vga.srcs/constrs_1/new/vga.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/vga_propImpl.xdc]. +Parsing XDC File [C:/Users/james/Documents/fpga-connect4/vga.srcs/constrs_1/new/vga.xdc] +CRITICAL WARNING: [Common 17-165] Too many positional options when parsing 'period', please type 'create_clock -help' for usage info. [C:/Users/james/Documents/fpga-connect4/vga.srcs/constrs_1/new/vga.xdc:7] +Finished Parsing XDC File [C:/Users/james/Documents/fpga-connect4/vga.srcs/constrs_1/new/vga.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Users/james/Documents/fpga-connect4/vga.srcs/constrs_1/new/vga.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/vga_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/vga_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Completed Processing XDC Constraints -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1661.754 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 2599.844 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. The system cannot find the path specified. -Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1661.754 ; gain = 0.000 +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.108 . Memory (MB): peak = 2599.844 ; gain = 0.000 INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate} --------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:06 ; elapsed = 00:00:15 . Memory (MB): peak = 1661.754 ; gain = 684.277 +Finished Constraint Validation : Time (s): cpu = 00:01:13 ; elapsed = 00:02:03 . Memory (MB): peak = 2599.844 ; gain = 1623.266 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7a100tcsg324-1 --------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:06 ; elapsed = 00:00:15 . Memory (MB): peak = 1661.754 ; gain = 684.277 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Applying 'set_property' XDC Constraints ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:06 ; elapsed = 00:00:15 . Memory (MB): peak = 1661.754 ; gain = 684.277 +Finished Loading Part and Timing Information : Time (s): cpu = 00:01:13 ; elapsed = 00:02:03 . Memory (MB): peak = 2599.844 ; gain = 1623.266 --------------------------------------------------------------------------------- INFO: [Synth 8-802] inferred FSM for state register 'hState_reg' in module 'vga' INFO: [Synth 8-802] inferred FSM for state register 'vState_reg' in module 'vga' @@ -306,24 +308,64 @@ INFO: [Synth 8-3898] No Re-encoding of one hot register 'hState_reg' in module ' --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3898] No Re-encoding of one hot register 'vState_reg' in module 'vga' --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:17 . Memory (MB): peak = 1661.754 ; gain = 684.277 +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:01:35 ; elapsed = 00:03:09 . Memory (MB): peak = 2599.844 ; gain = 1623.266 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : - 2 Input 10 Bit Adders := 62 - 3 Input 10 Bit Adders := 87 + 2 Input 32 Bit Adders := 8 + 2 Input 10 Bit Adders := 119 + 3 Input 10 Bit Adders := 117 + 2 Input 8 Bit Adders := 6 + 2 Input 7 Bit Adders := 125 + 2 Input 6 Bit Adders := 194 + 2 Input 5 Bit Adders := 537 + 2 Input 4 Bit Adders := 1714 + 2 Input 3 Bit Adders := 709 + 2 Input 2 Bit Adders := 119 2 Input 1 Bit Adders := 1 +---Registers : - 10 Bit Registers := 37 - 4 Bit Registers := 58 - 1 Bit Registers := 60 + 32 Bit Registers := 1 + 21 Bit Registers := 2 + 10 Bit Registers := 119 + 7 Bit Registers := 2 + 5 Bit Registers := 42 + 4 Bit Registers := 72 + 3 Bit Registers := 85 + 1 Bit Registers := 85 +---Muxes : + 2 Input 32 Bit Muxes := 180 + 2 Input 21 Bit Muxes := 12 + 4 Input 21 Bit Muxes := 2 + 2 Input 16 Bit Muxes := 266 + 2 Input 15 Bit Muxes := 266 + 2 Input 14 Bit Muxes := 266 + 2 Input 13 Bit Muxes := 266 + 2 Input 12 Bit Muxes := 532 + 2 Input 11 Bit Muxes := 532 + 2 Input 10 Bit Muxes := 752 + 4 Input 10 Bit Muxes := 1 + 8 Input 10 Bit Muxes := 4 5 Input 10 Bit Muxes := 2 - 2 Input 10 Bit Muxes := 1 - 13 Input 4 Bit Muxes := 378 + 2 Input 9 Bit Muxes := 338 + 2 Input 8 Bit Muxes := 338 + 2 Input 7 Bit Muxes := 2156 + 3 Input 7 Bit Muxes := 8 + 3 Input 6 Bit Muxes := 20 + 2 Input 6 Bit Muxes := 1073 + 8 Input 6 Bit Muxes := 1 + 5 Input 6 Bit Muxes := 2 + 2 Input 5 Bit Muxes := 1654 + 2 Input 4 Bit Muxes := 828 + 9 Input 4 Bit Muxes := 54 + 16 Input 4 Bit Muxes := 99 + 14 Input 4 Bit Muxes := 6 + 13 Input 4 Bit Muxes := 382 + 12 Input 4 Bit Muxes := 10 + 15 Input 4 Bit Muxes := 84 + 7 Input 4 Bit Muxes := 14 161 Input 4 Bit Muxes := 5 8 Input 4 Bit Muxes := 10 107 Input 4 Bit Muxes := 18 @@ -336,17 +378,33 @@ Detailed RTL Component Info : 86 Input 4 Bit Muxes := 4 55 Input 4 Bit Muxes := 3 10 Input 4 Bit Muxes := 1 - 2 Input 4 Bit Muxes := 2 - 16 Input 4 Bit Muxes := 1 + 2 Input 3 Bit Muxes := 775 + 3 Input 3 Bit Muxes := 42 + 12 Input 3 Bit Muxes := 2 + 8 Input 3 Bit Muxes := 24 + 15 Input 3 Bit Muxes := 14 5 Input 3 Bit Muxes := 1 107 Input 3 Bit Muxes := 3 100 Input 3 Bit Muxes := 1 + 2 Input 2 Bit Muxes := 1590 + 12 Input 2 Bit Muxes := 56 + 3 Input 2 Bit Muxes := 148 + 4 Input 2 Bit Muxes := 448 + 9 Input 2 Bit Muxes := 54 + 42 Input 2 Bit Muxes := 4 + 16 Input 2 Bit Muxes := 98 + 14 Input 2 Bit Muxes := 6 + 8 Input 2 Bit Muxes := 24 + 13 Input 2 Bit Muxes := 4 133 Input 2 Bit Muxes := 1 51 Input 2 Bit Muxes := 4 86 Input 2 Bit Muxes := 5 + 2 Input 1 Bit Muxes := 4048 + 12 Input 1 Bit Muxes := 195 + 8 Input 1 Bit Muxes := 2 + 3 Input 1 Bit Muxes := 3 + 4 Input 1 Bit Muxes := 4 5 Input 1 Bit Muxes := 7 - 4 Input 1 Bit Muxes := 3 - 2 Input 1 Bit Muxes := 4 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- @@ -362,9 +420,215 @@ Finished Part Resource Summary --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- -WARNING: [Synth 8-7080] Parallel synthesis criteria is not met ---------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:32 . Memory (MB): peak = 1661.754 ; gain = 684.277 +WARNING: [Synth 8-7129] Port BtnU in module vga is either unconnected or has no load +WARNING: [Synth 8-7129] Port BtnD in module vga is either unconnected or has no load +INFO: [Synth 8-3886] merging instance 'redWinYOffset_reg[0][7]' (FDCE) to 'redWinXOffset_reg[0][7]' +INFO: [Synth 8-3886] merging instance 'redWinYOffset_reg[0][8]' (FDCE) to 'redWinXOffset_reg[0][7]' +INFO: [Synth 8-3886] merging instance 'redWinYOffset_reg[0][9]' (FDCE) to 'redWinXOffset_reg[0][7]' +INFO: [Synth 8-3886] merging instance 'redWinYOffset_reg[1][7]' (FDCE) to 'redWinXOffset_reg[1][7]' +INFO: [Synth 8-3886] merging instance 'redWinYOffset_reg[1][8]' (FDCE) to 'redWinXOffset_reg[1][7]' +INFO: [Synth 8-3886] merging instance 'redWinYOffset_reg[1][9]' (FDCE) to 'redWinXOffset_reg[1][7]' +INFO: [Synth 8-3886] merging instance 'redWinYOffset_reg[2][7]' (FDCE) to 'redWinXOffset_reg[2][7]' +INFO: [Synth 8-3886] merging instance 'redWinYOffset_reg[2][8]' (FDCE) to 'redWinXOffset_reg[2][7]' +INFO: [Synth 8-3886] merging instance 'redWinYOffset_reg[2][9]' (FDCE) to 'redWinXOffset_reg[2][7]' +INFO: [Synth 8-3886] merging instance 'redWinYOffset_reg[3][7]' (FDCE) to 'redWinYOffset_reg[3][8]' +INFO: [Synth 8-3886] merging instance 'redWinYOffset_reg[3][8]' (FDCE) to 'redWinYOffset_reg[3][9]' +INFO: [Synth 8-3886] merging instance 'redWinYOffset_reg[3][9]' (FDCE) to 'redWinXOffset_reg[3][7]' +INFO: [Synth 8-3886] merging instance 'redWinYOffset_reg[4][7]' (FDCE) to 'redWinXOffset_reg[4][7]' +INFO: [Synth 8-3886] merging instance 'redWinYOffset_reg[4][8]' (FDCE) to 'redWinXOffset_reg[4][7]' +INFO: [Synth 8-3886] merging instance 'redWinYOffset_reg[4][9]' (FDCE) to 'redWinXOffset_reg[4][7]' +INFO: [Synth 8-3886] merging instance 'redWinYOffset_reg[5][7]' (FDCE) to 'redWinXOffset_reg[5][7]' +INFO: [Synth 8-3886] merging instance 'redWinYOffset_reg[5][8]' (FDCE) to 'redWinXOffset_reg[5][7]' +INFO: [Synth 8-3886] merging instance 'redWinYOffset_reg[5][9]' (FDCE) to 'redWinXOffset_reg[5][7]' +INFO: [Synth 8-3886] merging instance 'redWinYOffset_reg[6][7]' (FDCE) to 'redWinXOffset_reg[6][7]' +INFO: [Synth 8-3886] merging instance 'redWinYOffset_reg[6][8]' (FDCE) to 'redWinXOffset_reg[6][7]' +INFO: [Synth 8-3886] merging instance 'redWinYOffset_reg[6][9]' (FDCE) to 'redWinXOffset_reg[6][7]' +INFO: [Synth 8-3886] merging instance 'yellowWinYOffset_reg[4][7]' (FDCE) to 'yellowWinXOffset_reg[4][7]' +INFO: [Synth 8-3886] merging instance 'yellowWinYOffset_reg[4][8]' (FDCE) to 'yellowWinXOffset_reg[4][7]' +INFO: [Synth 8-3886] merging instance 'yellowWinYOffset_reg[4][9]' (FDCE) to 'yellowWinXOffset_reg[4][7]' +INFO: [Synth 8-3886] merging instance 'yellowWinYOffset_reg[5][7]' (FDCE) to 'yellowWinXOffset_reg[5][7]' +INFO: [Synth 8-3886] merging instance 'yellowWinYOffset_reg[5][8]' (FDCE) to 'yellowWinXOffset_reg[5][7]' +INFO: [Synth 8-3886] merging instance 'yellowWinYOffset_reg[5][9]' (FDCE) to 'yellowWinXOffset_reg[5][7]' +INFO: [Synth 8-3886] merging instance 'yellowWinXOffset_reg[4][7]' (FDCE) to 'yellowWinXOffset_reg[4][8]' +INFO: [Synth 8-3886] merging instance 'yellowWinXOffset_reg[4][8]' (FDCE) to 'yellowWinXOffset_reg[4][9]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\yellowWinXOffset_reg[4][9] ) +INFO: [Synth 8-3886] merging instance 'yellowWinXOffset_reg[5][7]' (FDCE) to 'yellowWinXOffset_reg[5][8]' +INFO: [Synth 8-3886] merging instance 'yellowWinXOffset_reg[5][8]' (FDCE) to 'yellowWinXOffset_reg[5][9]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\yellowWinXOffset_reg[5][9] ) +INFO: [Synth 8-3886] merging instance 'redWinXOffset_reg[0][7]' (FDCE) to 'redWinXOffset_reg[0][8]' +INFO: [Synth 8-3886] merging instance 'redWinXOffset_reg[0][8]' (FDCE) to 'redWinXOffset_reg[0][9]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\redWinXOffset_reg[0][9] ) +INFO: [Synth 8-3886] merging instance 'redWinXOffset_reg[1][7]' (FDCE) to 'redWinXOffset_reg[1][8]' +INFO: [Synth 8-3886] merging instance 'redWinXOffset_reg[1][8]' (FDCE) to 'redWinXOffset_reg[1][9]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\redWinXOffset_reg[1][9] ) +INFO: [Synth 8-3886] merging instance 'redWinXOffset_reg[2][7]' (FDCE) to 'redWinXOffset_reg[2][8]' +INFO: [Synth 8-3886] merging instance 'redWinXOffset_reg[2][8]' (FDCE) to 'redWinXOffset_reg[2][9]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\redWinXOffset_reg[2][9] ) +INFO: [Synth 8-3886] merging instance 'redWinXOffset_reg[3][7]' (FDCE) to 'redWinXOffset_reg[3][8]' +INFO: [Synth 8-3886] merging instance 'redWinXOffset_reg[3][8]' (FDCE) to 'redWinXOffset_reg[3][9]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\redWinXOffset_reg[3][9] ) +INFO: [Synth 8-3886] merging instance 'redWinXOffset_reg[4][7]' (FDCE) to 'redWinXOffset_reg[4][8]' +INFO: [Synth 8-3886] merging instance 'redWinXOffset_reg[4][8]' (FDCE) to 'redWinXOffset_reg[4][9]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\redWinXOffset_reg[4][9] ) +INFO: [Synth 8-3886] merging instance 'redWinXOffset_reg[5][7]' (FDCE) to 'redWinXOffset_reg[5][8]' +INFO: [Synth 8-3886] merging instance 'redWinXOffset_reg[5][8]' (FDCE) to 'redWinXOffset_reg[5][9]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\redWinXOffset_reg[5][9] ) +INFO: [Synth 8-3886] merging instance 'redWinXOffset_reg[6][7]' (FDCE) to 'redWinXOffset_reg[6][8]' +INFO: [Synth 8-3886] merging instance 'redWinXOffset_reg[6][8]' (FDCE) to 'redWinXOffset_reg[6][9]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\redWinXOffset_reg[6][9] ) +INFO: [Synth 8-3886] merging instance 'yellowWinYOffset_reg[0][7]' (FDCE) to 'yellowWinXOffset_reg[0][7]' +INFO: [Synth 8-3886] merging instance 'yellowWinYOffset_reg[0][8]' (FDCE) to 'yellowWinXOffset_reg[0][7]' +INFO: [Synth 8-3886] merging instance 'yellowWinYOffset_reg[0][9]' (FDCE) to 'yellowWinXOffset_reg[0][7]' +INFO: [Synth 8-3886] merging instance 'yellowWinYOffset_reg[1][7]' (FDCE) to 'yellowWinYOffset_reg[1][8]' +INFO: [Synth 8-3886] merging instance 'yellowWinYOffset_reg[1][8]' (FDCE) to 'yellowWinYOffset_reg[1][9]' +INFO: [Synth 8-3886] merging instance 'yellowWinYOffset_reg[1][9]' (FDCE) to 'yellowWinXOffset_reg[1][7]' +INFO: [Synth 8-3886] merging instance 'yellowWinYOffset_reg[2][7]' (FDCE) to 'yellowWinXOffset_reg[2][7]' +INFO: [Synth 8-3886] merging instance 'yellowWinYOffset_reg[2][8]' (FDCE) to 'yellowWinXOffset_reg[2][7]' +INFO: [Synth 8-3886] merging instance 'yellowWinYOffset_reg[2][9]' (FDCE) to 'yellowWinXOffset_reg[2][7]' +INFO: [Synth 8-3886] merging instance 'yellowWinYOffset_reg[3][7]' (FDCE) to 'yellowWinXOffset_reg[3][7]' +INFO: [Synth 8-3886] merging instance 'yellowWinYOffset_reg[3][8]' (FDCE) to 'yellowWinXOffset_reg[3][7]' +INFO: [Synth 8-3886] merging instance 'yellowWinYOffset_reg[3][9]' (FDCE) to 'yellowWinXOffset_reg[3][7]' +INFO: [Synth 8-3886] merging instance 'yellowWinYOffset_reg[6][7]' (FDCE) to 'yellowWinXOffset_reg[6][7]' +INFO: [Synth 8-3886] merging instance 'yellowWinYOffset_reg[6][8]' (FDCE) to 'yellowWinXOffset_reg[6][7]' +INFO: [Synth 8-3886] merging instance 'yellowWinYOffset_reg[6][9]' (FDCE) to 'yellowWinXOffset_reg[6][7]' +INFO: [Synth 8-3886] merging instance 'yellowWinXOffset_reg[0][7]' (FDCE) to 'yellowWinXOffset_reg[0][8]' +INFO: [Synth 8-3886] merging instance 'yellowWinXOffset_reg[0][8]' (FDCE) to 'yellowWinXOffset_reg[0][9]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\yellowWinXOffset_reg[0][9] ) +INFO: [Synth 8-3886] merging instance 'yellowWinXOffset_reg[1][7]' (FDCE) to 'yellowWinXOffset_reg[1][8]' +INFO: [Synth 8-3886] merging instance 'yellowWinXOffset_reg[1][8]' (FDCE) to 'yellowWinXOffset_reg[1][9]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\yellowWinXOffset_reg[1][9] ) +INFO: [Synth 8-3886] merging instance 'yellowWinXOffset_reg[2][7]' (FDCE) to 'yellowWinXOffset_reg[2][8]' +INFO: [Synth 8-3886] merging instance 'yellowWinXOffset_reg[2][8]' (FDCE) to 'yellowWinXOffset_reg[2][9]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\yellowWinXOffset_reg[2][9] ) +INFO: [Synth 8-3886] merging instance 'yellowWinXOffset_reg[3][7]' (FDCE) to 'yellowWinXOffset_reg[3][8]' +INFO: [Synth 8-3886] merging instance 'yellowWinXOffset_reg[3][8]' (FDCE) to 'yellowWinXOffset_reg[3][9]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\yellowWinXOffset_reg[3][9] ) +INFO: [Synth 8-3886] merging instance 'yellowWinXOffset_reg[6][7]' (FDCE) to 'yellowWinXOffset_reg[6][8]' +INFO: [Synth 8-3886] merging instance 'yellowWinXOffset_reg[6][8]' (FDCE) to 'yellowWinXOffset_reg[6][9]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\yellowWinXOffset_reg[6][9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\redPieceXOffset_reg[0][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\redPieceXOffset_reg[1][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\redPieceXOffset_reg[2][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\redPieceXOffset_reg[3][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\redPieceXOffset_reg[4][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\redPieceXOffset_reg[5][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\redPieceXOffset_reg[6][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\redPieceXOffset_reg[7][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\redPieceXOffset_reg[8][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\redPieceXOffset_reg[9][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\redPieceXOffset_reg[10][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\redPieceXOffset_reg[11][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\redPieceXOffset_reg[12][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\redPieceXOffset_reg[13][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\redPieceXOffset_reg[15][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\redPieceXOffset_reg[16][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\redPieceXOffset_reg[17][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\redPieceXOffset_reg[19][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\yellowPieceXOffset_reg[0][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\yellowPieceXOffset_reg[1][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\yellowPieceXOffset_reg[2][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\yellowPieceXOffset_reg[3][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\yellowPieceXOffset_reg[5][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\yellowPieceXOffset_reg[6][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\yellowPieceXOffset_reg[7][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\yellowPieceXOffset_reg[8][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\yellowPieceXOffset_reg[9][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\yellowPieceXOffset_reg[10][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\yellowPieceXOffset_reg[11][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\yellowPieceXOffset_reg[12][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\yellowPieceXOffset_reg[13][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\yellowPieceXOffset_reg[14][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\yellowPieceXOffset_reg[15][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\yellowPieceXOffset_reg[16][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\yellowPieceXOffset_reg[18][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\yellowPieceXOffset_reg[19][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\yellowPieceXOffset_reg[20][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (loop_done_reg) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\column_reg[0]_LDC ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\column_reg[1]_LDC ) +INFO: [Synth 8-5544] ROM "vgaRed" won't be mapped to Block RAM because address size (4) smaller than threshold (5) +INFO: [Synth 8-5544] ROM "vgaGrn" won't be mapped to Block RAM because address size (4) smaller than threshold (5) +INFO: [Synth 8-3886] merging instance 'bg_tile_gfx/paletteIndex_reg[0]' (FD) to 'bg_tile_gfx/paletteIndex_reg[1]' +INFO: [Synth 8-3886] merging instance 'bg_tile_gfx/paletteIndex_reg[1]' (FD) to 'bg_tile_gfx/paletteIndex_reg[2]' +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk2[0].yellow_piece_gfx /\paletteIndex_reg[0] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk2[1].yellow_piece_gfx /\paletteIndex_reg[0] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk2[2].yellow_piece_gfx /\paletteIndex_reg[0] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk2[3].yellow_piece_gfx /\paletteIndex_reg[0] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk2[4].yellow_piece_gfx /\paletteIndex_reg[0] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk2[5].yellow_piece_gfx /\paletteIndex_reg[0] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk2[6].yellow_piece_gfx /\paletteIndex_reg[0] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk2[7].yellow_piece_gfx /\paletteIndex_reg[0] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk2[8].yellow_piece_gfx /\paletteIndex_reg[0] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk2[9].yellow_piece_gfx /\paletteIndex_reg[0] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk2[10].yellow_piece_gfx /\paletteIndex_reg[0] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk2[11].yellow_piece_gfx /\paletteIndex_reg[0] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk2[12].yellow_piece_gfx /\paletteIndex_reg[0] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk2[13].yellow_piece_gfx /\paletteIndex_reg[0] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk2[14].yellow_piece_gfx /\paletteIndex_reg[0] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk2[15].yellow_piece_gfx /\paletteIndex_reg[0] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk2[16].yellow_piece_gfx /\paletteIndex_reg[0] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk2[17].yellow_piece_gfx /\paletteIndex_reg[0] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk2[18].yellow_piece_gfx /\paletteIndex_reg[0] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk2[19].yellow_piece_gfx /\paletteIndex_reg[0] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk2[20].yellow_piece_gfx /\paletteIndex_reg[0] ) +INFO: [Synth 8-3886] merging instance 'genblk1[0].red_piece_gfx/paletteIndex_reg[3]' (FD) to 'genblk1[0].red_piece_gfx/paletteIndex_reg[2]' +INFO: [Synth 8-3886] merging instance 'genblk1[1].red_piece_gfx/paletteIndex_reg[3]' (FD) to 'genblk1[1].red_piece_gfx/paletteIndex_reg[2]' +INFO: [Synth 8-3886] merging instance 'genblk1[2].red_piece_gfx/paletteIndex_reg[3]' (FD) to 'genblk1[2].red_piece_gfx/paletteIndex_reg[2]' +INFO: [Synth 8-3886] merging instance 'genblk1[3].red_piece_gfx/paletteIndex_reg[3]' (FD) to 'genblk1[3].red_piece_gfx/paletteIndex_reg[2]' +INFO: [Synth 8-3886] merging instance 'genblk1[4].red_piece_gfx/paletteIndex_reg[3]' (FD) to 'genblk1[4].red_piece_gfx/paletteIndex_reg[2]' +INFO: [Synth 8-3886] merging instance 'genblk1[5].red_piece_gfx/paletteIndex_reg[3]' (FD) to 'genblk1[5].red_piece_gfx/paletteIndex_reg[2]' +INFO: [Synth 8-3886] merging instance 'genblk1[6].red_piece_gfx/paletteIndex_reg[3]' (FD) to 'genblk1[6].red_piece_gfx/paletteIndex_reg[2]' +INFO: [Synth 8-3886] merging instance 'genblk1[7].red_piece_gfx/paletteIndex_reg[3]' (FD) to 'genblk1[7].red_piece_gfx/paletteIndex_reg[2]' +INFO: [Synth 8-3886] merging instance 'genblk1[8].red_piece_gfx/paletteIndex_reg[3]' (FD) to 'genblk1[8].red_piece_gfx/paletteIndex_reg[2]' +INFO: [Synth 8-3886] merging instance 'genblk1[9].red_piece_gfx/paletteIndex_reg[3]' (FD) to 'genblk1[9].red_piece_gfx/paletteIndex_reg[2]' +INFO: [Synth 8-3886] merging instance 'genblk1[10].red_piece_gfx/paletteIndex_reg[3]' (FD) to 'genblk1[10].red_piece_gfx/paletteIndex_reg[2]' +INFO: [Synth 8-3886] merging instance 'genblk1[11].red_piece_gfx/paletteIndex_reg[3]' (FD) to 'genblk1[11].red_piece_gfx/paletteIndex_reg[2]' +INFO: [Synth 8-3886] merging instance 'genblk1[12].red_piece_gfx/paletteIndex_reg[3]' (FD) to 'genblk1[12].red_piece_gfx/paletteIndex_reg[2]' +INFO: [Synth 8-3886] merging instance 'genblk1[13].red_piece_gfx/paletteIndex_reg[3]' (FD) to 'genblk1[13].red_piece_gfx/paletteIndex_reg[2]' +INFO: [Synth 8-3886] merging instance 'genblk1[14].red_piece_gfx/paletteIndex_reg[3]' (FD) to 'genblk1[14].red_piece_gfx/paletteIndex_reg[2]' +INFO: [Synth 8-3886] merging instance 'genblk1[15].red_piece_gfx/paletteIndex_reg[3]' (FD) to 'genblk1[15].red_piece_gfx/paletteIndex_reg[2]' +INFO: [Synth 8-3886] merging instance 'genblk1[16].red_piece_gfx/paletteIndex_reg[3]' (FD) to 'genblk1[16].red_piece_gfx/paletteIndex_reg[2]' +INFO: [Synth 8-3886] merging instance 'genblk1[17].red_piece_gfx/paletteIndex_reg[3]' (FD) to 'genblk1[17].red_piece_gfx/paletteIndex_reg[2]' +INFO: [Synth 8-3886] merging instance 'genblk1[18].red_piece_gfx/paletteIndex_reg[3]' (FD) to 'genblk1[18].red_piece_gfx/paletteIndex_reg[2]' +INFO: [Synth 8-3886] merging instance 'genblk1[19].red_piece_gfx/paletteIndex_reg[3]' (FD) to 'genblk1[19].red_piece_gfx/paletteIndex_reg[2]' +INFO: [Synth 8-3886] merging instance 'genblk1[20].red_piece_gfx/paletteIndex_reg[3]' (FD) to 'genblk1[20].red_piece_gfx/paletteIndex_reg[2]' +INFO: [Synth 8-3886] merging instance 'genblk2[0].yellow_piece_gfx/paletteIndex_reg[3]' (FD) to 'genblk2[0].yellow_piece_gfx/paletteIndex_reg[2]' +INFO: [Synth 8-3886] merging instance 'genblk2[1].yellow_piece_gfx/paletteIndex_reg[3]' (FD) to 'genblk2[1].yellow_piece_gfx/paletteIndex_reg[2]' +INFO: [Synth 8-3886] merging instance 'genblk2[2].yellow_piece_gfx/paletteIndex_reg[3]' (FD) to 'genblk2[2].yellow_piece_gfx/paletteIndex_reg[2]' +INFO: [Synth 8-3886] merging instance 'genblk2[3].yellow_piece_gfx/paletteIndex_reg[3]' (FD) to 'genblk2[3].yellow_piece_gfx/paletteIndex_reg[2]' +INFO: [Synth 8-3886] merging instance 'genblk2[4].yellow_piece_gfx/paletteIndex_reg[3]' (FD) to 'genblk2[4].yellow_piece_gfx/paletteIndex_reg[2]' +INFO: [Synth 8-3886] merging instance 'genblk2[5].yellow_piece_gfx/paletteIndex_reg[3]' (FD) to 'genblk2[5].yellow_piece_gfx/paletteIndex_reg[2]' +INFO: [Synth 8-3886] merging instance 'genblk2[6].yellow_piece_gfx/paletteIndex_reg[3]' (FD) to 'genblk2[6].yellow_piece_gfx/paletteIndex_reg[2]' +INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk1[0].red_piece_gfx /\paletteIndex_reg[2] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk1[1].red_piece_gfx /\paletteIndex_reg[2] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk1[2].red_piece_gfx /\paletteIndex_reg[2] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk1[3].red_piece_gfx /\paletteIndex_reg[2] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk1[4].red_piece_gfx /\paletteIndex_reg[2] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk1[5].red_piece_gfx /\paletteIndex_reg[2] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk1[6].red_piece_gfx /\paletteIndex_reg[2] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk1[7].red_piece_gfx /\paletteIndex_reg[2] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk1[8].red_piece_gfx /\paletteIndex_reg[2] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk1[9].red_piece_gfx /\paletteIndex_reg[2] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk1[10].red_piece_gfx /\paletteIndex_reg[2] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk1[11].red_piece_gfx /\paletteIndex_reg[2] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk1[12].red_piece_gfx /\paletteIndex_reg[2] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk1[13].red_piece_gfx /\paletteIndex_reg[2] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk1[14].red_piece_gfx /\paletteIndex_reg[2] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk1[15].red_piece_gfx /\paletteIndex_reg[2] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk1[16].red_piece_gfx /\paletteIndex_reg[2] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk1[17].red_piece_gfx /\paletteIndex_reg[2] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk1[18].red_piece_gfx /\paletteIndex_reg[2] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk1[19].red_piece_gfx /\paletteIndex_reg[2] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk1[20].red_piece_gfx /\paletteIndex_reg[2] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (yellow_indicator_gfx/\paletteIndex_reg[0] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (yellow_wins_gfx/\paletteIndex_reg[0] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (yellows_turn_gfx/\paletteIndex_reg[0] ) +INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-3333] propagating constant 1 across sequential element (red_indicator_gfx/\paletteIndex_reg[2] ) +INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:02:12 ; elapsed = 00:05:23 . Memory (MB): peak = 2599.844 ; gain = 1623.266 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting @@ -400,31 +664,6 @@ ROM: Preliminary Mapping Report |tie_game | paletteIndex | 64x3 | LUT | |tie_game | paletteIndex | 64x3 | LUT | |tie_game | paletteIndex | 64x3 | LUT | -|logo | paletteIndex | 128x3 | LUT | -|logo | paletteIndex | 128x3 | LUT | -|logo | paletteIndex | 128x3 | LUT | -|logo | paletteIndex | 128x3 | LUT | -|logo | paletteIndex | 128x3 | LUT | -|logo | paletteIndex | 128x3 | LUT | -|logo | paletteIndex | 128x3 | LUT | -|logo | paletteIndex | 128x3 | LUT | -|logo | paletteIndex | 128x3 | LUT | -|logo | paletteIndex | 128x3 | LUT | -|board | paletteIndex | 256x4 | LUT | -|board | paletteIndex | 256x4 | LUT | -|board | paletteIndex | 256x4 | LUT | -|red_wins | paletteIndex | 64x2 | LUT | -|red_wins | paletteIndex | 64x2 | LUT | -|red_wins | paletteIndex | 64x2 | LUT | -|red_wins | paletteIndex | 64x2 | LUT | -|red_wins | paletteIndex | 64x2 | LUT | -|red_wins | paletteIndex | 64x2 | LUT | -|tie_game | paletteIndex | 64x3 | LUT | -|tie_game | paletteIndex | 64x3 | LUT | -|tie_game | paletteIndex | 64x3 | LUT | -|tie_game | paletteIndex | 64x3 | LUT | -|tie_game | paletteIndex | 64x3 | LUT | -|tie_game | paletteIndex | 64x3 | LUT | +------------+--------------+---------------+----------------+ --------------------------------------------------------------------------------- @@ -434,19 +673,19 @@ Finished ROM, RAM, DSP, Shift Register and Retiming Reporting Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:14 ; elapsed = 00:00:35 . Memory (MB): peak = 1661.754 ; gain = 684.277 +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:02:14 ; elapsed = 00:05:28 . Memory (MB): peak = 2599.844 ; gain = 1623.266 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:14 ; elapsed = 00:00:36 . Memory (MB): peak = 1661.754 ; gain = 684.277 +Finished Timing Optimization : Time (s): cpu = 00:02:16 ; elapsed = 00:05:34 . Memory (MB): peak = 2599.844 ; gain = 1623.266 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:14 ; elapsed = 00:00:36 . Memory (MB): peak = 1661.754 ; gain = 684.277 +Finished Technology Mapping : Time (s): cpu = 00:02:28 ; elapsed = 00:05:54 . Memory (MB): peak = 2599.844 ; gain = 1623.266 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion @@ -464,37 +703,37 @@ Start Final Netlist Cleanup Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:00:15 ; elapsed = 00:00:39 . Memory (MB): peak = 1661.754 ; gain = 684.277 +Finished IO Insertion : Time (s): cpu = 00:02:34 ; elapsed = 00:06:06 . Memory (MB): peak = 2599.844 ; gain = 1623.266 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:00:15 ; elapsed = 00:00:39 . Memory (MB): peak = 1661.754 ; gain = 684.277 +Finished Renaming Generated Instances : Time (s): cpu = 00:02:34 ; elapsed = 00:06:06 . Memory (MB): peak = 2599.844 ; gain = 1623.266 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:15 ; elapsed = 00:00:39 . Memory (MB): peak = 1661.754 ; gain = 684.277 +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:02:35 ; elapsed = 00:06:06 . Memory (MB): peak = 2599.844 ; gain = 1623.266 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:00:15 ; elapsed = 00:00:39 . Memory (MB): peak = 1661.754 ; gain = 684.277 +Finished Renaming Generated Ports : Time (s): cpu = 00:02:35 ; elapsed = 00:06:06 . Memory (MB): peak = 2599.844 ; gain = 1623.266 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:15 ; elapsed = 00:00:39 . Memory (MB): peak = 1661.754 ; gain = 684.277 +Finished Handling Custom Attributes : Time (s): cpu = 00:02:35 ; elapsed = 00:06:08 . Memory (MB): peak = 2599.844 ; gain = 1623.266 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:00:15 ; elapsed = 00:00:39 . Memory (MB): peak = 1661.754 ; gain = 684.277 +Finished Renaming Generated Nets : Time (s): cpu = 00:02:35 ; elapsed = 00:06:08 . Memory (MB): peak = 2599.844 ; gain = 1623.266 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report @@ -510,44 +749,50 @@ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ -|1 |BUFG | 2| -|2 |CARRY4 | 102| -|3 |LUT1 | 195| -|4 |LUT2 | 69| -|5 |LUT3 | 65| -|6 |LUT4 | 88| -|7 |LUT5 | 105| -|8 |LUT6 | 603| -|9 |MUXF7 | 16| -|10 |MUXF8 | 3| -|11 |FDRE | 218| -|12 |IBUF | 1| -|13 |OBUF | 14| +|1 |BUFG | 3| +|2 |CARRY4 | 1667| +|3 |LUT1 | 851| +|4 |LUT2 | 2641| +|5 |LUT3 | 3249| +|6 |LUT4 | 2736| +|7 |LUT5 | 3875| +|8 |LUT6 | 10502| +|9 |MUXF7 | 539| +|10 |MUXF8 | 76| +|11 |FDCE | 1463| +|12 |FDPE | 788| +|13 |FDRE | 281| +|14 |LDC | 420| +|15 |IBUF | 6| +|16 |OBUF | 14| +------+-------+------+ --------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:00:15 ; elapsed = 00:00:39 . Memory (MB): peak = 1661.754 ; gain = 684.277 +Finished Writing Synthesis Report : Time (s): cpu = 00:02:35 ; elapsed = 00:06:08 . Memory (MB): peak = 2599.844 ; gain = 1623.266 --------------------------------------------------------------------------------- -Synthesis finished with 0 errors, 0 critical warnings and 1 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:10 ; elapsed = 00:00:38 . Memory (MB): peak = 1661.754 ; gain = 621.055 -Synthesis Optimization Complete : Time (s): cpu = 00:00:15 ; elapsed = 00:00:39 . Memory (MB): peak = 1661.754 ; gain = 684.277 +Synthesis finished with 0 errors, 0 critical warnings and 2 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:01:24 ; elapsed = 00:05:27 . Memory (MB): peak = 2599.844 ; gain = 1436.816 +Synthesis Optimization Complete : Time (s): cpu = 00:02:35 ; elapsed = 00:06:08 . Memory (MB): peak = 2599.844 ; gain = 1623.266 INFO: [Project 1-571] Translating synthesized netlist -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 1661.754 ; gain = 0.000 -INFO: [Netlist 29-17] Analyzing 121 Unisim elements for replacement +Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.216 . Memory (MB): peak = 2599.844 ; gain = 0.000 +INFO: [Netlist 29-17] Analyzing 2702 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +WARNING: [Netlist 29-101] Netlist 'vga' is not ideal for floorplanning, since the cellview 'connect4_core_design' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1661.754 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 2599.844 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: -No Unisim elements were transformed. + A total of 420 instances were transformed. + LDC => LDCE: 420 instances The system cannot find the path specified. -Synth Design complete | Checksum: 99d812a8 +Synth Design complete | Checksum: dcbcac8 INFO: [Common 17-83] Releasing license: Synthesis -96 Infos, 137 Warnings, 1 Critical Warnings and 0 Errors encountered. +310 Infos, 138 Warnings, 1 Critical Warnings and 0 Errors encountered. synth_design completed successfully -synth_design: Time (s): cpu = 00:00:17 ; elapsed = 00:00:42 . Memory (MB): peak = 1661.754 ; gain = 1091.055 +synth_design: Time (s): cpu = 00:02:38 ; elapsed = 00:06:16 . Memory (MB): peak = 2599.844 ; gain = 2031.355 INFO: [runtcl-6] Synthesis results are not added to the cache due to CRITICAL_WARNING -Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1661.754 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/Users/james/Documents/vga/vga.runs/synth_1/vga.dcp' has been generated. +Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.031 . Memory (MB): peak = 2599.844 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'C:/Users/james/Documents/fpga-connect4/vga.runs/synth_1/vga.dcp' has been generated. +write_checkpoint: Time (s): cpu = 00:00:02 ; elapsed = 00:00:06 . Memory (MB): peak = 2599.844 ; gain = 0.000 INFO: [runtcl-4] Executing : report_utilization -file vga_utilization_synth.rpt -pb vga_utilization_synth.pb -INFO: [Common 17-206] Exiting Vivado at Thu Apr 18 03:14:41 2024... +INFO: [Common 17-206] Exiting Vivado at Mon Apr 22 21:21:43 2024... diff --git a/vga.runs/synth_1/runme.sh b/vga.runs/synth_1/runme.sh index 888b716..7561dbf 100644 --- a/vga.runs/synth_1/runme.sh +++ b/vga.runs/synth_1/runme.sh @@ -25,7 +25,7 @@ else fi export LD_LIBRARY_PATH -HD_PWD='C:/Users/james/Documents/vga/vga.runs/synth_1' +HD_PWD='C:/Users/james/Documents/fpga-connect4/vga.runs/synth_1' cd "$HD_PWD" HD_LOG=runme.log diff --git a/vga.runs/synth_1/vga.dcp b/vga.runs/synth_1/vga.dcp index d3f2b97..4a12a51 100644 Binary files a/vga.runs/synth_1/vga.dcp and b/vga.runs/synth_1/vga.dcp differ diff --git a/vga.runs/synth_1/vga.tcl b/vga.runs/synth_1/vga.tcl index f44eb0f..28059fb 100644 --- a/vga.runs/synth_1/vga.tcl +++ b/vga.runs/synth_1/vga.tcl @@ -4,7 +4,7 @@ set TIME_start [clock seconds] namespace eval ::optrace { - variable script "C:/Users/james/Documents/vga/vga.runs/synth_1/vga.tcl" + variable script "C:/Users/james/Documents/fpga-connect4/vga.runs/synth_1/vga.tcl" variable category "vivado_synth" } @@ -70,43 +70,38 @@ proc create_report { reportName command } { } } OPTRACE "synth_1" START { ROLLUP_AUTO } -set_param checkpoint.writeSynthRtdsInDcp 1 -set_param general.maxThreads 20 -set_param chipscope.maxJobs 5 -set_param synth.incrementalSynthesisCache C:/Users/james/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-22316-me/incrSyn -set_param xicom.use_bs_reader 1 -set_msg_config -id {Synth 8-256} -limit 10000 -set_msg_config -id {Synth 8-638} -limit 10000 OPTRACE "Creating in-memory project" START { } create_project -in_memory -part xc7a100tcsg324-1 set_param project.singleFileAddWarning.threshold 0 set_param project.compositeFile.enableAutoGeneration 0 set_param synth.vivado.isSynthRun true -set_property webtalk.parent_dir C:/Users/james/Documents/vga/vga.cache/wt [current_project] -set_property parent.project_path C:/Users/james/Documents/vga/vga.xpr [current_project] +set_property webtalk.parent_dir C:/Users/james/Documents/fpga-connect4/vga.cache/wt [current_project] +set_property parent.project_path C:/Users/james/Documents/fpga-connect4/vga.xpr [current_project] set_property default_lib xil_defaultlib [current_project] set_property target_language Verilog [current_project] -set_property ip_output_repo c:/Users/james/Documents/vga/vga.cache/ip [current_project] +set_property ip_output_repo c:/Users/james/Documents/fpga-connect4/vga.cache/ip [current_project] set_property ip_cache_permissions {read write} [current_project] OPTRACE "Creating in-memory project" END { } OPTRACE "Adding files" START { } read_verilog -library xil_defaultlib { - C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v - C:/Users/james/Documents/vga/sprite_modules/bg_tile.v - C:/Users/james/Documents/vga/sprite_modules/board.v - C:/Users/james/Documents/vga/sprite_modules/corner_border_check.v - C:/Users/james/Documents/vga/sprite_modules/logo.v - C:/Users/james/Documents/vga/sprite_modules/red_indicator.v - C:/Users/james/Documents/vga/sprite_modules/red_piece.v - C:/Users/james/Documents/vga/sprite_modules/red_wins.v - C:/Users/james/Documents/vga/sprite_modules/reds_turn.v - C:/Users/james/Documents/vga/sprite_modules/tie_game.v - C:/Users/james/Documents/vga/sprite_modules/yellow_indicator.v - C:/Users/james/Documents/vga/sprite_modules/yellow_piece.v - C:/Users/james/Documents/vga/sprite_modules/yellow_wins.v - C:/Users/james/Documents/vga/sprite_modules/yellows_turn.v - C:/Users/james/Documents/vga/vga.srcs/sources_1/new/vga.v + C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v + C:/Users/james/Documents/fpga-connect4/sprite_modules/bg_tile.v + C:/Users/james/Documents/fpga-connect4/sprite_modules/board.v + C:/Users/james/Documents/fpga-connect4/sprite_modules/corner_border_check.v + C:/Users/james/Documents/fpga-connect4/sprite_modules/logo.v + C:/Users/james/Documents/fpga-connect4/sprite_modules/red_indicator.v + C:/Users/james/Documents/fpga-connect4/sprite_modules/red_piece.v + C:/Users/james/Documents/fpga-connect4/sprite_modules/red_win_highlight.v + C:/Users/james/Documents/fpga-connect4/sprite_modules/red_wins.v + C:/Users/james/Documents/fpga-connect4/sprite_modules/reds_turn.v + C:/Users/james/Documents/fpga-connect4/sprite_modules/tie_game.v + C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_indicator.v + C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_piece.v + C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_win_highlight.v + C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_wins.v + C:/Users/james/Documents/fpga-connect4/sprite_modules/yellows_turn.v + C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/vga.v } OPTRACE "Adding files" END { } # Mark all dcp files as not used in implementation to prevent them from being @@ -117,12 +112,12 @@ OPTRACE "Adding files" END { } foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { set_property used_in_implementation false $dcp } -read_xdc C:/Users/james/Documents/vga/vga.srcs/constrs_1/new/vga.xdc -set_property used_in_implementation false [get_files C:/Users/james/Documents/vga/vga.srcs/constrs_1/new/vga.xdc] +read_xdc C:/Users/james/Documents/fpga-connect4/vga.srcs/constrs_1/new/vga.xdc +set_property used_in_implementation false [get_files C:/Users/james/Documents/fpga-connect4/vga.srcs/constrs_1/new/vga.xdc] set_param ips.enableIPCacheLiteLoad 1 -read_checkpoint -auto_incremental -incremental C:/Users/james/Documents/vga/vga.srcs/utils_1/imports/synth_1/vga.dcp +read_checkpoint -auto_incremental -incremental C:/Users/james/Documents/fpga-connect4/vga.srcs/utils_1/imports/synth_1/vga.dcp close [open __synthesis_is_running__ w] OPTRACE "synth_design" START { } diff --git a/vga.runs/synth_1/vga.vds b/vga.runs/synth_1/vga.vds index 2279504..4e29e98 100644 --- a/vga.runs/synth_1/vga.vds +++ b/vga.runs/synth_1/vga.vds @@ -3,17 +3,17 @@ # SW Build 4029153 on Fri Oct 13 20:14:34 MDT 2023 # IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 # SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 -# Start of session at: Thu Apr 18 03:13:51 2024 -# Process ID: 40688 -# Current directory: C:/Users/james/Documents/vga/vga.runs/synth_1 +# Start of session at: Mon Apr 22 21:15:15 2024 +# Process ID: 36016 +# Current directory: C:/Users/james/Documents/fpga-connect4/vga.runs/synth_1 # Command line: vivado.exe -log vga.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source vga.tcl -# Log file: C:/Users/james/Documents/vga/vga.runs/synth_1/vga.vds -# Journal file: C:/Users/james/Documents/vga/vga.runs/synth_1\vivado.jou +# Log file: C:/Users/james/Documents/fpga-connect4/vga.runs/synth_1/vga.vds +# Journal file: C:/Users/james/Documents/fpga-connect4/vga.runs/synth_1\vivado.jou # Running On: me, OS: Windows, CPU Frequency: 2918 MHz, CPU Physical cores: 14, Host memory: 34016 MB #----------------------------------------------------------- source vga.tcl -notrace -Command: read_checkpoint -auto_incremental -incremental C:/Users/james/Documents/vga/vga.srcs/utils_1/imports/synth_1/vga.dcp -INFO: [Vivado 12-5825] Read reference checkpoint from C:/Users/james/Documents/vga/vga.srcs/utils_1/imports/synth_1/vga.dcp for incremental synthesis +Command: read_checkpoint -auto_incremental -incremental C:/Users/james/Documents/fpga-connect4/vga.srcs/utils_1/imports/synth_1/vga.dcp +INFO: [Vivado 12-5825] Read reference checkpoint from C:/Users/james/Documents/fpga-connect4/vga.srcs/utils_1/imports/synth_1/vga.dcp for incremental synthesis INFO: [Vivado 12-7989] Please ensure there are no constraint changes Command: synth_design -top vga -part xc7a100tcsg324-1 Starting synth_design @@ -22,265 +22,273 @@ INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100 INFO: [Device 21-403] Loading part xc7a100tcsg324-1 INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate} -INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. +INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes -INFO: [Synth 8-7075] Helper process launched with PID 28388 ---------------------------------------------------------------------------------- -Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:07 . Memory (MB): peak = 1417.863 ; gain = 440.387 ---------------------------------------------------------------------------------- -INFO: [Synth 8-11241] undeclared symbol 'hValid', assumed default net type 'wire' [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/vga.v:51] -INFO: [Synth 8-11241] undeclared symbol 'vValid', assumed default net type 'wire' [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/vga.v:118] -INFO: [Synth 8-6157] synthesizing module 'vga' [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/vga.v:23] -INFO: [Synth 8-6157] synthesizing module 'red_piece' [C:/Users/james/Documents/vga/sprite_modules/red_piece.v:20] -INFO: [Synth 8-6155] done synthesizing module 'red_piece' (0#1) [C:/Users/james/Documents/vga/sprite_modules/red_piece.v:20] -INFO: [Synth 8-6157] synthesizing module 'yellow_piece' [C:/Users/james/Documents/vga/sprite_modules/yellow_piece.v:20] -INFO: [Synth 8-6155] done synthesizing module 'yellow_piece' (0#1) [C:/Users/james/Documents/vga/sprite_modules/yellow_piece.v:20] -INFO: [Synth 8-155] case statement is not full and has no default [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/vga.v:73] -INFO: [Synth 8-155] case statement is not full and has no default [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/vga.v:140] -INFO: [Synth 8-6157] synthesizing module 'TESTcore_design' [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:23] -INFO: [Synth 8-6155] done synthesizing module 'TESTcore_design' (0#1) [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:23] -INFO: [Synth 8-6157] synthesizing module 'corner_border_check' [C:/Users/james/Documents/vga/sprite_modules/corner_border_check.v:20] -INFO: [Synth 8-6155] done synthesizing module 'corner_border_check' (0#1) [C:/Users/james/Documents/vga/sprite_modules/corner_border_check.v:20] -INFO: [Synth 8-6157] synthesizing module 'bg_tile' [C:/Users/james/Documents/vga/sprite_modules/bg_tile.v:20] -INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/vga/sprite_modules/bg_tile.v:40] -INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/vga/sprite_modules/bg_tile.v:43] -INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/vga/sprite_modules/bg_tile.v:85] -INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/vga/sprite_modules/bg_tile.v:127] -INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/vga/sprite_modules/bg_tile.v:169] -INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/vga/sprite_modules/bg_tile.v:211] -INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/vga/sprite_modules/bg_tile.v:253] -INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/vga/sprite_modules/bg_tile.v:295] -INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/vga/sprite_modules/bg_tile.v:337] -INFO: [Synth 8-6155] done synthesizing module 'bg_tile' (0#1) [C:/Users/james/Documents/vga/sprite_modules/bg_tile.v:20] -INFO: [Synth 8-6157] synthesizing module 'logo' [C:/Users/james/Documents/vga/sprite_modules/logo.v:20] -INFO: [Synth 8-6155] done synthesizing module 'logo' (0#1) [C:/Users/james/Documents/vga/sprite_modules/logo.v:20] -INFO: [Synth 8-6157] synthesizing module 'board' [C:/Users/james/Documents/vga/sprite_modules/board.v:20] -INFO: [Synth 8-6155] done synthesizing module 'board' (0#1) [C:/Users/james/Documents/vga/sprite_modules/board.v:20] -INFO: [Synth 8-6157] synthesizing module 'reds_turn' [C:/Users/james/Documents/vga/sprite_modules/reds_turn.v:20] -INFO: [Synth 8-6155] done synthesizing module 'reds_turn' (0#1) [C:/Users/james/Documents/vga/sprite_modules/reds_turn.v:20] -INFO: [Synth 8-6157] synthesizing module 'yellows_turn' [C:/Users/james/Documents/vga/sprite_modules/yellows_turn.v:20] -INFO: [Synth 8-6155] done synthesizing module 'yellows_turn' (0#1) [C:/Users/james/Documents/vga/sprite_modules/yellows_turn.v:20] -INFO: [Synth 8-6157] synthesizing module 'red_wins' [C:/Users/james/Documents/vga/sprite_modules/red_wins.v:20] -INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/vga/sprite_modules/red_wins.v:43] -INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/vga/sprite_modules/red_wins.v:309] -INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/vga/sprite_modules/red_wins.v:575] -INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/vga/sprite_modules/red_wins.v:841] -INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/vga/sprite_modules/red_wins.v:1107] -INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/vga/sprite_modules/red_wins.v:1373] -INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/vga/sprite_modules/red_wins.v:1639] -INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/vga/sprite_modules/red_wins.v:1905] -INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/vga/sprite_modules/red_wins.v:2171] -INFO: [Synth 8-6155] done synthesizing module 'red_wins' (0#1) [C:/Users/james/Documents/vga/sprite_modules/red_wins.v:20] -INFO: [Synth 8-6157] synthesizing module 'yellow_wins' [C:/Users/james/Documents/vga/sprite_modules/yellow_wins.v:20] -INFO: [Synth 8-6155] done synthesizing module 'yellow_wins' (0#1) [C:/Users/james/Documents/vga/sprite_modules/yellow_wins.v:20] -INFO: [Synth 8-6157] synthesizing module 'tie_game' [C:/Users/james/Documents/vga/sprite_modules/tie_game.v:20] -INFO: [Synth 8-6155] done synthesizing module 'tie_game' (0#1) [C:/Users/james/Documents/vga/sprite_modules/tie_game.v:20] -INFO: [Synth 8-6157] synthesizing module 'red_indicator' [C:/Users/james/Documents/vga/sprite_modules/red_indicator.v:20] -INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/vga/sprite_modules/red_indicator.v:43] -INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/vga/sprite_modules/red_indicator.v:85] -INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/vga/sprite_modules/red_indicator.v:127] -INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/vga/sprite_modules/red_indicator.v:169] -INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/vga/sprite_modules/red_indicator.v:211] -INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/vga/sprite_modules/red_indicator.v:253] -INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/vga/sprite_modules/red_indicator.v:295] -INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/vga/sprite_modules/red_indicator.v:337] -INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/vga/sprite_modules/red_indicator.v:379] -INFO: [Synth 8-6155] done synthesizing module 'red_indicator' (0#1) [C:/Users/james/Documents/vga/sprite_modules/red_indicator.v:20] -INFO: [Synth 8-6157] synthesizing module 'yellow_indicator' [C:/Users/james/Documents/vga/sprite_modules/yellow_indicator.v:20] -INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/vga/sprite_modules/yellow_indicator.v:43] -INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/vga/sprite_modules/yellow_indicator.v:85] -INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/vga/sprite_modules/yellow_indicator.v:127] -INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/vga/sprite_modules/yellow_indicator.v:169] -INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/vga/sprite_modules/yellow_indicator.v:211] -INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/vga/sprite_modules/yellow_indicator.v:253] -INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/vga/sprite_modules/yellow_indicator.v:295] -INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/vga/sprite_modules/yellow_indicator.v:337] -INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/vga/sprite_modules/yellow_indicator.v:379] -INFO: [Synth 8-6155] done synthesizing module 'yellow_indicator' (0#1) [C:/Users/james/Documents/vga/sprite_modules/yellow_indicator.v:20] -INFO: [Synth 8-6155] done synthesizing module 'vga' (0#1) [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/vga.v:23] -WARNING: [Synth 8-6014] Unused sequential element xOffset_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/red_piece.v:34] -WARNING: [Synth 8-6014] Unused sequential element yOffset_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/red_piece.v:35] -WARNING: [Synth 8-6014] Unused sequential element xSprite_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/red_piece.v:36] -WARNING: [Synth 8-6014] Unused sequential element ySprite_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/red_piece.v:37] -WARNING: [Synth 8-6014] Unused sequential element inBounds_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/red_piece.v:38] -WARNING: [Synth 8-6014] Unused sequential element xOffset_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/yellow_piece.v:34] -WARNING: [Synth 8-6014] Unused sequential element yOffset_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/yellow_piece.v:35] -WARNING: [Synth 8-6014] Unused sequential element xSprite_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/yellow_piece.v:36] -WARNING: [Synth 8-6014] Unused sequential element ySprite_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/yellow_piece.v:37] -WARNING: [Synth 8-6014] Unused sequential element inBounds_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/yellow_piece.v:38] -WARNING: [Synth 8-6014] Unused sequential element redPieceXOffset_reg[13] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:48] -WARNING: [Synth 8-6014] Unused sequential element redPieceXOffset_reg[12] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:48] -WARNING: [Synth 8-6014] Unused sequential element redPieceXOffset_reg[11] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:48] -WARNING: [Synth 8-6014] Unused sequential element redPieceXOffset_reg[10] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:48] -WARNING: [Synth 8-6014] Unused sequential element redPieceXOffset_reg[9] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:48] -WARNING: [Synth 8-6014] Unused sequential element redPieceXOffset_reg[8] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:48] -WARNING: [Synth 8-6014] Unused sequential element redPieceXOffset_reg[7] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:48] -WARNING: [Synth 8-6014] Unused sequential element redPieceXOffset_reg[6] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:48] -WARNING: [Synth 8-6014] Unused sequential element redPieceXOffset_reg[5] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:48] -WARNING: [Synth 8-6014] Unused sequential element redPieceXOffset_reg[4] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:48] -WARNING: [Synth 8-6014] Unused sequential element redPieceXOffset_reg[3] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:48] -WARNING: [Synth 8-6014] Unused sequential element redPieceXOffset_reg[2] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:48] -WARNING: [Synth 8-6014] Unused sequential element redPieceXOffset_reg[1] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:48] -WARNING: [Synth 8-6014] Unused sequential element redPieceXOffset_reg[0] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:48] -WARNING: [Synth 8-6014] Unused sequential element redPieceYOffset_reg[14] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:47] -WARNING: [Synth 8-6014] Unused sequential element redPieceYOffset_reg[13] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:47] -WARNING: [Synth 8-6014] Unused sequential element redPieceYOffset_reg[12] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:47] -WARNING: [Synth 8-6014] Unused sequential element redPieceYOffset_reg[11] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:47] -WARNING: [Synth 8-6014] Unused sequential element redPieceYOffset_reg[10] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:47] -WARNING: [Synth 8-6014] Unused sequential element redPieceYOffset_reg[9] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:47] -WARNING: [Synth 8-6014] Unused sequential element redPieceYOffset_reg[8] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:47] -WARNING: [Synth 8-6014] Unused sequential element redPieceYOffset_reg[7] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:47] -WARNING: [Synth 8-6014] Unused sequential element redPieceYOffset_reg[6] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:47] -WARNING: [Synth 8-6014] Unused sequential element redPieceYOffset_reg[5] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:47] -WARNING: [Synth 8-6014] Unused sequential element redPieceYOffset_reg[4] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:47] -WARNING: [Synth 8-6014] Unused sequential element redPieceYOffset_reg[3] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:47] -WARNING: [Synth 8-6014] Unused sequential element redPieceYOffset_reg[2] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:47] -WARNING: [Synth 8-6014] Unused sequential element redPieceYOffset_reg[1] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:47] -WARNING: [Synth 8-6014] Unused sequential element redPieceYOffset_reg[0] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:47] -WARNING: [Synth 8-6014] Unused sequential element yellowPieceXOffset_reg[20] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:50] -WARNING: [Synth 8-6014] Unused sequential element yellowPieceXOffset_reg[19] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:50] -WARNING: [Synth 8-6014] Unused sequential element yellowPieceXOffset_reg[18] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:50] -WARNING: [Synth 8-6014] Unused sequential element yellowPieceXOffset_reg[17] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:50] -WARNING: [Synth 8-6014] Unused sequential element yellowPieceXOffset_reg[16] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:50] -WARNING: [Synth 8-6014] Unused sequential element yellowPieceXOffset_reg[15] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:50] -WARNING: [Synth 8-6014] Unused sequential element yellowPieceXOffset_reg[14] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:50] -WARNING: [Synth 8-6014] Unused sequential element yellowPieceXOffset_reg[13] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:50] -WARNING: [Synth 8-6014] Unused sequential element yellowPieceXOffset_reg[12] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:50] -WARNING: [Synth 8-6014] Unused sequential element yellowPieceXOffset_reg[11] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:50] -WARNING: [Synth 8-6014] Unused sequential element yellowPieceXOffset_reg[10] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:50] -WARNING: [Synth 8-6014] Unused sequential element yellowPieceXOffset_reg[9] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:50] -WARNING: [Synth 8-6014] Unused sequential element yellowPieceXOffset_reg[8] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:50] -WARNING: [Synth 8-6014] Unused sequential element yellowPieceXOffset_reg[7] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:50] -WARNING: [Synth 8-6014] Unused sequential element yellowPieceXOffset_reg[6] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:50] -WARNING: [Synth 8-6014] Unused sequential element yellowPieceXOffset_reg[5] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:50] -WARNING: [Synth 8-6014] Unused sequential element yellowPieceXOffset_reg[4] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:50] -WARNING: [Synth 8-6014] Unused sequential element yellowPieceXOffset_reg[3] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:50] -WARNING: [Synth 8-6014] Unused sequential element yellowPieceXOffset_reg[2] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:50] -WARNING: [Synth 8-6014] Unused sequential element yellowPieceXOffset_reg[1] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:50] -WARNING: [Synth 8-6014] Unused sequential element yellowPieceXOffset_reg[0] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:50] -WARNING: [Synth 8-6014] Unused sequential element yellowPieceYOffset_reg[20] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:49] -WARNING: [Synth 8-6014] Unused sequential element yellowPieceYOffset_reg[0] was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:49] -WARNING: [Synth 8-6014] Unused sequential element showLogo_reg was removed. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:65] -WARNING: [Synth 8-3848] Net showRedsTurn in module/entity TESTcore_design does not have driver. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:27] -WARNING: [Synth 8-3848] Net showYellowsTurn in module/entity TESTcore_design does not have driver. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:28] -WARNING: [Synth 8-3848] Net showRedWins in module/entity TESTcore_design does not have driver. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:29] -WARNING: [Synth 8-3848] Net showYellowWins in module/entity TESTcore_design does not have driver. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:30] -WARNING: [Synth 8-3848] Net showTieGame in module/entity TESTcore_design does not have driver. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:31] -WARNING: [Synth 8-3848] Net showRedIndicator in module/entity TESTcore_design does not have driver. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:32] -WARNING: [Synth 8-3848] Net redIndicatorXOffset in module/entity TESTcore_design does not have driver. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:33] -WARNING: [Synth 8-3848] Net showYellowIndicator in module/entity TESTcore_design does not have driver. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:34] -WARNING: [Synth 8-3848] Net yellowIndicatorXOffset in module/entity TESTcore_design does not have driver. [C:/Users/james/Documents/vga/vga.srcs/sources_1/new/TESTcore_design.v:35] -WARNING: [Synth 8-6014] Unused sequential element xOffset_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/corner_border_check.v:34] -WARNING: [Synth 8-6014] Unused sequential element yOffset_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/corner_border_check.v:35] -WARNING: [Synth 8-6014] Unused sequential element xSprite_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/corner_border_check.v:36] -WARNING: [Synth 8-6014] Unused sequential element ySprite_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/corner_border_check.v:37] -WARNING: [Synth 8-6014] Unused sequential element inBounds_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/corner_border_check.v:38] -WARNING: [Synth 8-6014] Unused sequential element xOffset_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/bg_tile.v:34] -WARNING: [Synth 8-6014] Unused sequential element yOffset_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/bg_tile.v:35] -WARNING: [Synth 8-6014] Unused sequential element xSprite_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/bg_tile.v:36] -WARNING: [Synth 8-6014] Unused sequential element ySprite_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/bg_tile.v:37] -WARNING: [Synth 8-6014] Unused sequential element inBounds_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/bg_tile.v:38] -WARNING: [Synth 8-6014] Unused sequential element xOffset_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/logo.v:34] -WARNING: [Synth 8-6014] Unused sequential element yOffset_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/logo.v:35] -WARNING: [Synth 8-6014] Unused sequential element xSprite_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/logo.v:36] -WARNING: [Synth 8-6014] Unused sequential element ySprite_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/logo.v:37] -WARNING: [Synth 8-6014] Unused sequential element inBounds_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/logo.v:38] -WARNING: [Synth 8-6014] Unused sequential element xOffset_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/board.v:34] -WARNING: [Synth 8-6014] Unused sequential element yOffset_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/board.v:35] -WARNING: [Synth 8-6014] Unused sequential element xSprite_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/board.v:36] -WARNING: [Synth 8-6014] Unused sequential element ySprite_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/board.v:37] -WARNING: [Synth 8-6014] Unused sequential element inBounds_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/board.v:38] -WARNING: [Synth 8-6014] Unused sequential element xOffset_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/reds_turn.v:34] -WARNING: [Synth 8-6014] Unused sequential element yOffset_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/reds_turn.v:35] -WARNING: [Synth 8-6014] Unused sequential element xSprite_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/reds_turn.v:36] -WARNING: [Synth 8-6014] Unused sequential element ySprite_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/reds_turn.v:37] -WARNING: [Synth 8-6014] Unused sequential element inBounds_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/reds_turn.v:38] -WARNING: [Synth 8-6014] Unused sequential element xOffset_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/yellows_turn.v:34] -WARNING: [Synth 8-6014] Unused sequential element yOffset_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/yellows_turn.v:35] -WARNING: [Synth 8-6014] Unused sequential element xSprite_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/yellows_turn.v:36] -WARNING: [Synth 8-6014] Unused sequential element ySprite_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/yellows_turn.v:37] -WARNING: [Synth 8-6014] Unused sequential element inBounds_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/yellows_turn.v:38] -WARNING: [Synth 8-6014] Unused sequential element xOffset_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/red_wins.v:34] -WARNING: [Synth 8-6014] Unused sequential element yOffset_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/red_wins.v:35] -WARNING: [Synth 8-6014] Unused sequential element xSprite_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/red_wins.v:36] -WARNING: [Synth 8-6014] Unused sequential element ySprite_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/red_wins.v:37] -WARNING: [Synth 8-6014] Unused sequential element inBounds_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/red_wins.v:38] -WARNING: [Synth 8-6014] Unused sequential element xOffset_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/yellow_wins.v:34] -WARNING: [Synth 8-6014] Unused sequential element yOffset_reg was removed. [C:/Users/james/Documents/vga/sprite_modules/yellow_wins.v:35] -INFO: [Common 17-14] Message 'Synth 8-6014' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. -WARNING: [Synth 8-7129] Port showRedsTurn in module TESTcore_design is either unconnected or has no load -WARNING: [Synth 8-7129] Port showYellowsTurn in module TESTcore_design is either unconnected or has no load -WARNING: [Synth 8-7129] Port showRedWins in module TESTcore_design is either unconnected or has no load -WARNING: [Synth 8-7129] Port showYellowWins in module TESTcore_design is either unconnected or has no load -WARNING: [Synth 8-7129] Port showTieGame in module TESTcore_design is either unconnected or has no load -WARNING: [Synth 8-7129] Port showRedIndicator in module TESTcore_design is either unconnected or has no load -WARNING: [Synth 8-7129] Port redIndicatorXOffset[9] in module TESTcore_design is either unconnected or has no load -WARNING: [Synth 8-7129] Port redIndicatorXOffset[8] in module TESTcore_design is either unconnected or has no load -WARNING: [Synth 8-7129] Port redIndicatorXOffset[7] in module TESTcore_design is either unconnected or has no load -WARNING: [Synth 8-7129] Port redIndicatorXOffset[6] in module TESTcore_design is either unconnected or has no load -WARNING: [Synth 8-7129] Port redIndicatorXOffset[5] in module TESTcore_design is either unconnected or has no load -WARNING: [Synth 8-7129] Port redIndicatorXOffset[4] in module TESTcore_design is either unconnected or has no load -WARNING: [Synth 8-7129] Port redIndicatorXOffset[3] in module TESTcore_design is either unconnected or has no load -WARNING: [Synth 8-7129] Port redIndicatorXOffset[2] in module TESTcore_design is either unconnected or has no load -WARNING: [Synth 8-7129] Port redIndicatorXOffset[1] in module TESTcore_design is either unconnected or has no load -WARNING: [Synth 8-7129] Port redIndicatorXOffset[0] in module TESTcore_design is either unconnected or has no load -WARNING: [Synth 8-7129] Port showYellowIndicator in module TESTcore_design is either unconnected or has no load -WARNING: [Synth 8-7129] Port yellowIndicatorXOffset[9] in module TESTcore_design is either unconnected or has no load -WARNING: [Synth 8-7129] Port yellowIndicatorXOffset[8] in module TESTcore_design is either unconnected or has no load -WARNING: [Synth 8-7129] Port yellowIndicatorXOffset[7] in module TESTcore_design is either unconnected or has no load -WARNING: [Synth 8-7129] Port yellowIndicatorXOffset[6] in module TESTcore_design is either unconnected or has no load -WARNING: [Synth 8-7129] Port yellowIndicatorXOffset[5] in module TESTcore_design is either unconnected or has no load -WARNING: [Synth 8-7129] Port yellowIndicatorXOffset[4] in module TESTcore_design is either unconnected or has no load -WARNING: [Synth 8-7129] Port yellowIndicatorXOffset[3] in module TESTcore_design is either unconnected or has no load -WARNING: [Synth 8-7129] Port yellowIndicatorXOffset[2] in module TESTcore_design is either unconnected or has no load -WARNING: [Synth 8-7129] Port yellowIndicatorXOffset[1] in module TESTcore_design is either unconnected or has no load -WARNING: [Synth 8-7129] Port yellowIndicatorXOffset[0] in module TESTcore_design is either unconnected or has no load ---------------------------------------------------------------------------------- -Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:10 . Memory (MB): peak = 1598.531 ; gain = 621.055 +INFO: [Synth 8-7075] Helper process launched with PID 31760 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:04 . Memory (MB): peak = 1417.359 ; gain = 440.781 +--------------------------------------------------------------------------------- +INFO: [Synth 8-11241] undeclared symbol 'hValid', assumed default net type 'wire' [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/vga.v:51] +INFO: [Synth 8-11241] undeclared symbol 'vValid', assumed default net type 'wire' [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/vga.v:119] +INFO: [Synth 8-11241] undeclared symbol 'reset', assumed default net type 'wire' [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/vga.v:185] +INFO: [Synth 8-6157] synthesizing module 'vga' [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/vga.v:23] +INFO: [Synth 8-6157] synthesizing module 'red_piece' [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_piece.v:20] +INFO: [Synth 8-6155] done synthesizing module 'red_piece' (0#1) [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_piece.v:20] +INFO: [Synth 8-6157] synthesizing module 'yellow_piece' [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_piece.v:20] +INFO: [Synth 8-6155] done synthesizing module 'yellow_piece' (0#1) [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_piece.v:20] +INFO: [Synth 8-6157] synthesizing module 'yellow_win_highlight' [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_win_highlight.v:20] +INFO: [Synth 8-6155] done synthesizing module 'yellow_win_highlight' (0#1) [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_win_highlight.v:20] +INFO: [Synth 8-6157] synthesizing module 'red_win_highlight' [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_win_highlight.v:20] +INFO: [Synth 8-6155] done synthesizing module 'red_win_highlight' (0#1) [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_win_highlight.v:20] +INFO: [Synth 8-155] case statement is not full and has no default [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/vga.v:73] +INFO: [Synth 8-155] case statement is not full and has no default [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/vga.v:141] +INFO: [Synth 8-6157] synthesizing module 'connect4_core_design' [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:25] +WARNING: [Synth 8-6090] variable 'showRedWinIndicator' is written by both blocking and non-blocking assignments, entire logic could be removed [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:185] +WARNING: [Synth 8-6090] variable 'showYellowWinIndicator' is written by both blocking and non-blocking assignments, entire logic could be removed [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:186] +WARNING: [Synth 8-6090] variable 'showRedWinIndicator' is written by both blocking and non-blocking assignments, entire logic could be removed [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:442] +WARNING: [Synth 8-6090] variable 'showYellowWinIndicator' is written by both blocking and non-blocking assignments, entire logic could be removed [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:485] +INFO: [Synth 8-155] case statement is not full and has no default [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:508] +INFO: [Synth 8-155] case statement is not full and has no default [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:540] +INFO: [Synth 8-155] case statement is not full and has no default [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:576] +INFO: [Synth 8-155] case statement is not full and has no default [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:608] +INFO: [Synth 8-155] case statement is not full and has no default [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:192] +INFO: [Synth 8-6155] done synthesizing module 'connect4_core_design' (0#1) [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:25] +INFO: [Synth 8-6157] synthesizing module 'corner_border_check' [C:/Users/james/Documents/fpga-connect4/sprite_modules/corner_border_check.v:20] +INFO: [Synth 8-6155] done synthesizing module 'corner_border_check' (0#1) [C:/Users/james/Documents/fpga-connect4/sprite_modules/corner_border_check.v:20] +INFO: [Synth 8-6157] synthesizing module 'bg_tile' [C:/Users/james/Documents/fpga-connect4/sprite_modules/bg_tile.v:20] +INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/fpga-connect4/sprite_modules/bg_tile.v:40] +INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/fpga-connect4/sprite_modules/bg_tile.v:43] +INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/fpga-connect4/sprite_modules/bg_tile.v:85] +INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/fpga-connect4/sprite_modules/bg_tile.v:127] +INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/fpga-connect4/sprite_modules/bg_tile.v:169] +INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/fpga-connect4/sprite_modules/bg_tile.v:211] +INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/fpga-connect4/sprite_modules/bg_tile.v:253] +INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/fpga-connect4/sprite_modules/bg_tile.v:295] +INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/fpga-connect4/sprite_modules/bg_tile.v:337] +INFO: [Synth 8-6155] done synthesizing module 'bg_tile' (0#1) [C:/Users/james/Documents/fpga-connect4/sprite_modules/bg_tile.v:20] +INFO: [Synth 8-6157] synthesizing module 'logo' [C:/Users/james/Documents/fpga-connect4/sprite_modules/logo.v:20] +INFO: [Synth 8-6155] done synthesizing module 'logo' (0#1) [C:/Users/james/Documents/fpga-connect4/sprite_modules/logo.v:20] +INFO: [Synth 8-6157] synthesizing module 'board' [C:/Users/james/Documents/fpga-connect4/sprite_modules/board.v:20] +INFO: [Synth 8-6155] done synthesizing module 'board' (0#1) [C:/Users/james/Documents/fpga-connect4/sprite_modules/board.v:20] +INFO: [Synth 8-6157] synthesizing module 'reds_turn' [C:/Users/james/Documents/fpga-connect4/sprite_modules/reds_turn.v:20] +INFO: [Synth 8-6155] done synthesizing module 'reds_turn' (0#1) [C:/Users/james/Documents/fpga-connect4/sprite_modules/reds_turn.v:20] +INFO: [Synth 8-6157] synthesizing module 'yellows_turn' [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellows_turn.v:20] +INFO: [Synth 8-6155] done synthesizing module 'yellows_turn' (0#1) [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellows_turn.v:20] +INFO: [Synth 8-6157] synthesizing module 'red_wins' [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_wins.v:20] +INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_wins.v:43] +INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_wins.v:309] +INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_wins.v:575] +INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_wins.v:841] +INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_wins.v:1107] +INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_wins.v:1373] +INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_wins.v:1639] +INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_wins.v:1905] +INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_wins.v:2171] +INFO: [Synth 8-6155] done synthesizing module 'red_wins' (0#1) [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_wins.v:20] +INFO: [Synth 8-6157] synthesizing module 'yellow_wins' [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_wins.v:20] +INFO: [Synth 8-6155] done synthesizing module 'yellow_wins' (0#1) [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_wins.v:20] +INFO: [Synth 8-6157] synthesizing module 'tie_game' [C:/Users/james/Documents/fpga-connect4/sprite_modules/tie_game.v:20] +INFO: [Synth 8-6155] done synthesizing module 'tie_game' (0#1) [C:/Users/james/Documents/fpga-connect4/sprite_modules/tie_game.v:20] +INFO: [Synth 8-6157] synthesizing module 'red_indicator' [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_indicator.v:20] +INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_indicator.v:43] +INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_indicator.v:85] +INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_indicator.v:127] +INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_indicator.v:169] +INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_indicator.v:211] +INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_indicator.v:253] +INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_indicator.v:295] +INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_indicator.v:337] +INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_indicator.v:379] +INFO: [Synth 8-6155] done synthesizing module 'red_indicator' (0#1) [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_indicator.v:20] +INFO: [Synth 8-6157] synthesizing module 'yellow_indicator' [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_indicator.v:20] +INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_indicator.v:43] +INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_indicator.v:85] +INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_indicator.v:127] +INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_indicator.v:169] +INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_indicator.v:211] +INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_indicator.v:253] +INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_indicator.v:295] +INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_indicator.v:337] +INFO: [Synth 8-226] default block is never used [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_indicator.v:379] +INFO: [Synth 8-6155] done synthesizing module 'yellow_indicator' (0#1) [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_indicator.v:20] +INFO: [Synth 8-6155] done synthesizing module 'vga' (0#1) [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/vga.v:23] +WARNING: [Synth 8-6014] Unused sequential element xOffset_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_piece.v:34] +WARNING: [Synth 8-6014] Unused sequential element yOffset_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_piece.v:35] +WARNING: [Synth 8-6014] Unused sequential element xSprite_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_piece.v:36] +WARNING: [Synth 8-6014] Unused sequential element ySprite_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_piece.v:37] +WARNING: [Synth 8-6014] Unused sequential element inBounds_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_piece.v:38] +WARNING: [Synth 8-6014] Unused sequential element xOffset_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_piece.v:34] +WARNING: [Synth 8-6014] Unused sequential element yOffset_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_piece.v:35] +WARNING: [Synth 8-6014] Unused sequential element xSprite_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_piece.v:36] +WARNING: [Synth 8-6014] Unused sequential element ySprite_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_piece.v:37] +WARNING: [Synth 8-6014] Unused sequential element inBounds_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_piece.v:38] +WARNING: [Synth 8-6014] Unused sequential element xOffset_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_win_highlight.v:34] +WARNING: [Synth 8-6014] Unused sequential element yOffset_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_win_highlight.v:35] +WARNING: [Synth 8-6014] Unused sequential element xSprite_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_win_highlight.v:36] +WARNING: [Synth 8-6014] Unused sequential element ySprite_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_win_highlight.v:37] +WARNING: [Synth 8-6014] Unused sequential element inBounds_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_win_highlight.v:38] +WARNING: [Synth 8-6014] Unused sequential element xOffset_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_win_highlight.v:34] +WARNING: [Synth 8-6014] Unused sequential element yOffset_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_win_highlight.v:35] +WARNING: [Synth 8-6014] Unused sequential element xSprite_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_win_highlight.v:36] +WARNING: [Synth 8-6014] Unused sequential element ySprite_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_win_highlight.v:37] +WARNING: [Synth 8-6014] Unused sequential element inBounds_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_win_highlight.v:38] +WARNING: [Synth 8-6014] Unused sequential element checkWinsRed.a_reg was removed. [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:421] +WARNING: [Synth 8-6014] Unused sequential element checkWinsYellow.a_reg was removed. [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:464] +WARNING: [Synth 8-6014] Unused sequential element animateResetPieces.r_reg was removed. [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:774] +WARNING: [Synth 8-6014] Unused sequential element animateResetPieces.c_reg was removed. [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:775] +WARNING: [Synth 8-7137] Register redPieceYOffset_reg[20] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:90] +WARNING: [Synth 8-7137] Register redPieceYOffset_reg[19] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:90] +WARNING: [Synth 8-7137] Register redPieceYOffset_reg[18] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:90] +WARNING: [Synth 8-7137] Register redPieceYOffset_reg[17] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:90] +WARNING: [Synth 8-7137] Register redPieceYOffset_reg[16] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:90] +WARNING: [Synth 8-7137] Register redPieceYOffset_reg[15] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:90] +WARNING: [Synth 8-7137] Register redPieceYOffset_reg[14] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:90] +WARNING: [Synth 8-7137] Register redPieceYOffset_reg[13] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:90] +WARNING: [Synth 8-7137] Register redPieceYOffset_reg[12] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:90] +WARNING: [Synth 8-7137] Register redPieceYOffset_reg[11] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:90] +WARNING: [Synth 8-7137] Register redPieceYOffset_reg[10] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:90] +WARNING: [Synth 8-7137] Register redPieceYOffset_reg[9] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:90] +WARNING: [Synth 8-7137] Register redPieceYOffset_reg[8] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:90] +WARNING: [Synth 8-7137] Register redPieceYOffset_reg[7] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:90] +WARNING: [Synth 8-7137] Register redPieceYOffset_reg[6] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:90] +WARNING: [Synth 8-7137] Register redPieceYOffset_reg[5] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:90] +WARNING: [Synth 8-7137] Register redPieceYOffset_reg[4] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:90] +WARNING: [Synth 8-7137] Register redPieceYOffset_reg[3] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:90] +WARNING: [Synth 8-7137] Register redPieceYOffset_reg[2] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:90] +WARNING: [Synth 8-7137] Register redPieceYOffset_reg[1] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:90] +WARNING: [Synth 8-7137] Register redPieceYOffset_reg[0] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:90] +WARNING: [Synth 8-7137] Register yellowPieceYOffset_reg[20] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:92] +WARNING: [Synth 8-7137] Register yellowPieceYOffset_reg[19] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:92] +WARNING: [Synth 8-7137] Register yellowPieceYOffset_reg[18] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:92] +WARNING: [Synth 8-7137] Register yellowPieceYOffset_reg[17] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:92] +WARNING: [Synth 8-7137] Register yellowPieceYOffset_reg[16] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:92] +WARNING: [Synth 8-7137] Register yellowPieceYOffset_reg[15] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:92] +WARNING: [Synth 8-7137] Register yellowPieceYOffset_reg[14] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:92] +WARNING: [Synth 8-7137] Register yellowPieceYOffset_reg[13] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:92] +WARNING: [Synth 8-7137] Register yellowPieceYOffset_reg[12] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:92] +WARNING: [Synth 8-7137] Register yellowPieceYOffset_reg[11] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:92] +WARNING: [Synth 8-7137] Register yellowPieceYOffset_reg[10] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:92] +WARNING: [Synth 8-7137] Register yellowPieceYOffset_reg[9] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:92] +WARNING: [Synth 8-7137] Register yellowPieceYOffset_reg[8] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:92] +WARNING: [Synth 8-7137] Register yellowPieceYOffset_reg[7] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:92] +WARNING: [Synth 8-7137] Register yellowPieceYOffset_reg[6] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:92] +WARNING: [Synth 8-7137] Register yellowPieceYOffset_reg[5] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:92] +WARNING: [Synth 8-7137] Register yellowPieceYOffset_reg[4] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:92] +WARNING: [Synth 8-7137] Register yellowPieceYOffset_reg[3] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:92] +WARNING: [Synth 8-7137] Register yellowPieceYOffset_reg[2] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:92] +WARNING: [Synth 8-7137] Register yellowPieceYOffset_reg[1] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:92] +WARNING: [Synth 8-7137] Register yellowPieceYOffset_reg[0] in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:92] +WARNING: [Synth 8-7137] Register game_over_reg in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:167] +WARNING: [Synth 8-7137] Register column_reg in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:169] +WARNING: [Synth 8-7137] Register current_player_reg in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:170] +WARNING: [Synth 8-7137] Register update_reg in module connect4_core_design has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/TESTcore_design.v:252] +WARNING: [Synth 8-6014] Unused sequential element xOffset_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/corner_border_check.v:34] +WARNING: [Synth 8-6014] Unused sequential element yOffset_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/corner_border_check.v:35] +WARNING: [Synth 8-6014] Unused sequential element xSprite_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/corner_border_check.v:36] +WARNING: [Synth 8-6014] Unused sequential element ySprite_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/corner_border_check.v:37] +WARNING: [Synth 8-6014] Unused sequential element inBounds_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/corner_border_check.v:38] +WARNING: [Synth 8-6014] Unused sequential element xOffset_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/bg_tile.v:34] +WARNING: [Synth 8-6014] Unused sequential element yOffset_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/bg_tile.v:35] +WARNING: [Synth 8-6014] Unused sequential element xSprite_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/bg_tile.v:36] +WARNING: [Synth 8-6014] Unused sequential element ySprite_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/bg_tile.v:37] +WARNING: [Synth 8-6014] Unused sequential element inBounds_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/bg_tile.v:38] +WARNING: [Synth 8-6014] Unused sequential element xOffset_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/logo.v:34] +WARNING: [Synth 8-6014] Unused sequential element yOffset_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/logo.v:35] +WARNING: [Synth 8-6014] Unused sequential element xSprite_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/logo.v:36] +WARNING: [Synth 8-6014] Unused sequential element ySprite_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/logo.v:37] +WARNING: [Synth 8-6014] Unused sequential element inBounds_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/logo.v:38] +WARNING: [Synth 8-6014] Unused sequential element xOffset_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/board.v:34] +WARNING: [Synth 8-6014] Unused sequential element yOffset_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/board.v:35] +WARNING: [Synth 8-6014] Unused sequential element xSprite_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/board.v:36] +WARNING: [Synth 8-6014] Unused sequential element ySprite_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/board.v:37] +WARNING: [Synth 8-6014] Unused sequential element inBounds_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/board.v:38] +WARNING: [Synth 8-6014] Unused sequential element xOffset_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/reds_turn.v:34] +WARNING: [Synth 8-6014] Unused sequential element yOffset_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/reds_turn.v:35] +WARNING: [Synth 8-6014] Unused sequential element xSprite_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/reds_turn.v:36] +WARNING: [Synth 8-6014] Unused sequential element ySprite_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/reds_turn.v:37] +WARNING: [Synth 8-6014] Unused sequential element inBounds_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/reds_turn.v:38] +WARNING: [Synth 8-6014] Unused sequential element xOffset_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellows_turn.v:34] +WARNING: [Synth 8-6014] Unused sequential element yOffset_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellows_turn.v:35] +WARNING: [Synth 8-6014] Unused sequential element xSprite_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellows_turn.v:36] +WARNING: [Synth 8-6014] Unused sequential element ySprite_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellows_turn.v:37] +WARNING: [Synth 8-6014] Unused sequential element inBounds_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellows_turn.v:38] +WARNING: [Synth 8-6014] Unused sequential element xOffset_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_wins.v:34] +WARNING: [Synth 8-6014] Unused sequential element yOffset_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_wins.v:35] +WARNING: [Synth 8-6014] Unused sequential element xSprite_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_wins.v:36] +WARNING: [Synth 8-6014] Unused sequential element ySprite_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_wins.v:37] +WARNING: [Synth 8-6014] Unused sequential element inBounds_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_wins.v:38] +WARNING: [Synth 8-6014] Unused sequential element xOffset_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_wins.v:34] +WARNING: [Synth 8-6014] Unused sequential element yOffset_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_wins.v:35] +WARNING: [Synth 8-6014] Unused sequential element xSprite_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_wins.v:36] +WARNING: [Synth 8-6014] Unused sequential element ySprite_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_wins.v:37] +WARNING: [Synth 8-6014] Unused sequential element inBounds_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_wins.v:38] +WARNING: [Synth 8-6014] Unused sequential element xOffset_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/tie_game.v:34] +WARNING: [Synth 8-6014] Unused sequential element yOffset_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/tie_game.v:35] +WARNING: [Synth 8-6014] Unused sequential element xSprite_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/tie_game.v:36] +WARNING: [Synth 8-6014] Unused sequential element ySprite_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/tie_game.v:37] +WARNING: [Synth 8-6014] Unused sequential element inBounds_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/tie_game.v:38] +WARNING: [Synth 8-6014] Unused sequential element xOffset_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_indicator.v:34] +WARNING: [Synth 8-6014] Unused sequential element yOffset_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_indicator.v:35] +WARNING: [Synth 8-6014] Unused sequential element xSprite_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_indicator.v:36] +WARNING: [Synth 8-6014] Unused sequential element ySprite_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_indicator.v:37] +WARNING: [Synth 8-6014] Unused sequential element inBounds_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/red_indicator.v:38] +WARNING: [Synth 8-6014] Unused sequential element xOffset_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_indicator.v:34] +WARNING: [Synth 8-6014] Unused sequential element yOffset_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_indicator.v:35] +WARNING: [Synth 8-6014] Unused sequential element xSprite_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_indicator.v:36] +WARNING: [Synth 8-6014] Unused sequential element ySprite_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_indicator.v:37] +WARNING: [Synth 8-6014] Unused sequential element inBounds_reg was removed. [C:/Users/james/Documents/fpga-connect4/sprite_modules/yellow_indicator.v:38] +WARNING: [Synth 8-6014] Unused sequential element winIndicatorIndex_reg was removed. [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/vga.v:369] +WARNING: [Synth 8-6014] Unused sequential element frontIndex_reg was removed. [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/vga.v:383] +WARNING: [Synth 8-6014] Unused sequential element pieceIndex_reg was removed. [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/vga.v:416] +WARNING: [Synth 8-6014] Unused sequential element finalIndex_reg was removed. [C:/Users/james/Documents/fpga-connect4/vga.srcs/sources_1/new/vga.v:429] +WARNING: [Synth 8-7129] Port BtnU in module vga is either unconnected or has no load +WARNING: [Synth 8-7129] Port BtnD in module vga is either unconnected or has no load +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:38 ; elapsed = 00:01:12 . Memory (MB): peak = 2413.395 ; gain = 1436.816 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:04 ; elapsed = 00:00:10 . Memory (MB): peak = 1598.531 ; gain = 621.055 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:40 ; elapsed = 00:01:16 . Memory (MB): peak = 2413.395 ; gain = 1436.816 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:10 . Memory (MB): peak = 1598.531 ; gain = 621.055 +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:40 ; elapsed = 00:01:16 . Memory (MB): peak = 2413.395 ; gain = 1436.816 --------------------------------------------------------------------------------- -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.026 . Memory (MB): peak = 1598.531 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2413.395 ; gain = 0.000 INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine -Parsing XDC File [C:/Users/james/Documents/vga/vga.srcs/constrs_1/new/vga.xdc] -CRITICAL WARNING: [Common 17-165] Too many positional options when parsing 'period', please type 'create_clock -help' for usage info. [C:/Users/james/Documents/vga/vga.srcs/constrs_1/new/vga.xdc:7] -Finished Parsing XDC File [C:/Users/james/Documents/vga/vga.srcs/constrs_1/new/vga.xdc] -INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Users/james/Documents/vga/vga.srcs/constrs_1/new/vga.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/vga_propImpl.xdc]. +Parsing XDC File [C:/Users/james/Documents/fpga-connect4/vga.srcs/constrs_1/new/vga.xdc] +CRITICAL WARNING: [Common 17-165] Too many positional options when parsing 'period', please type 'create_clock -help' for usage info. [C:/Users/james/Documents/fpga-connect4/vga.srcs/constrs_1/new/vga.xdc:7] +Finished Parsing XDC File [C:/Users/james/Documents/fpga-connect4/vga.srcs/constrs_1/new/vga.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Users/james/Documents/fpga-connect4/vga.srcs/constrs_1/new/vga.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/vga_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/vga_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Completed Processing XDC Constraints -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1661.754 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 2599.844 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. -Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1661.754 ; gain = 0.000 +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.108 . Memory (MB): peak = 2599.844 ; gain = 0.000 INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate} --------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:06 ; elapsed = 00:00:15 . Memory (MB): peak = 1661.754 ; gain = 684.277 +Finished Constraint Validation : Time (s): cpu = 00:01:13 ; elapsed = 00:02:03 . Memory (MB): peak = 2599.844 ; gain = 1623.266 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7a100tcsg324-1 --------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:06 ; elapsed = 00:00:15 . Memory (MB): peak = 1661.754 ; gain = 684.277 +Finished Loading Part and Timing Information : Time (s): cpu = 00:01:13 ; elapsed = 00:02:03 . Memory (MB): peak = 2599.844 ; gain = 1623.266 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:06 ; elapsed = 00:00:15 . Memory (MB): peak = 1661.754 ; gain = 684.277 +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:01:13 ; elapsed = 00:02:03 . Memory (MB): peak = 2599.844 ; gain = 1623.266 --------------------------------------------------------------------------------- INFO: [Synth 8-802] inferred FSM for state register 'hState_reg' in module 'vga' INFO: [Synth 8-802] inferred FSM for state register 'vState_reg' in module 'vga' @@ -305,24 +313,64 @@ INFO: [Synth 8-3898] No Re-encoding of one hot register 'hState_reg' in module ' --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3898] No Re-encoding of one hot register 'vState_reg' in module 'vga' --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:17 . Memory (MB): peak = 1661.754 ; gain = 684.277 +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:01:35 ; elapsed = 00:03:09 . Memory (MB): peak = 2599.844 ; gain = 1623.266 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : - 2 Input 10 Bit Adders := 62 - 3 Input 10 Bit Adders := 87 + 2 Input 32 Bit Adders := 8 + 2 Input 10 Bit Adders := 119 + 3 Input 10 Bit Adders := 117 + 2 Input 8 Bit Adders := 6 + 2 Input 7 Bit Adders := 125 + 2 Input 6 Bit Adders := 194 + 2 Input 5 Bit Adders := 537 + 2 Input 4 Bit Adders := 1714 + 2 Input 3 Bit Adders := 709 + 2 Input 2 Bit Adders := 119 2 Input 1 Bit Adders := 1 +---Registers : - 10 Bit Registers := 37 - 4 Bit Registers := 58 - 1 Bit Registers := 60 + 32 Bit Registers := 1 + 21 Bit Registers := 2 + 10 Bit Registers := 119 + 7 Bit Registers := 2 + 5 Bit Registers := 42 + 4 Bit Registers := 72 + 3 Bit Registers := 85 + 1 Bit Registers := 85 +---Muxes : + 2 Input 32 Bit Muxes := 180 + 2 Input 21 Bit Muxes := 12 + 4 Input 21 Bit Muxes := 2 + 2 Input 16 Bit Muxes := 266 + 2 Input 15 Bit Muxes := 266 + 2 Input 14 Bit Muxes := 266 + 2 Input 13 Bit Muxes := 266 + 2 Input 12 Bit Muxes := 532 + 2 Input 11 Bit Muxes := 532 + 2 Input 10 Bit Muxes := 752 + 4 Input 10 Bit Muxes := 1 + 8 Input 10 Bit Muxes := 4 5 Input 10 Bit Muxes := 2 - 2 Input 10 Bit Muxes := 1 - 13 Input 4 Bit Muxes := 378 + 2 Input 9 Bit Muxes := 338 + 2 Input 8 Bit Muxes := 338 + 2 Input 7 Bit Muxes := 2156 + 3 Input 7 Bit Muxes := 8 + 3 Input 6 Bit Muxes := 20 + 2 Input 6 Bit Muxes := 1073 + 8 Input 6 Bit Muxes := 1 + 5 Input 6 Bit Muxes := 2 + 2 Input 5 Bit Muxes := 1654 + 2 Input 4 Bit Muxes := 828 + 9 Input 4 Bit Muxes := 54 + 16 Input 4 Bit Muxes := 99 + 14 Input 4 Bit Muxes := 6 + 13 Input 4 Bit Muxes := 382 + 12 Input 4 Bit Muxes := 10 + 15 Input 4 Bit Muxes := 84 + 7 Input 4 Bit Muxes := 14 161 Input 4 Bit Muxes := 5 8 Input 4 Bit Muxes := 10 107 Input 4 Bit Muxes := 18 @@ -335,17 +383,33 @@ Detailed RTL Component Info : 86 Input 4 Bit Muxes := 4 55 Input 4 Bit Muxes := 3 10 Input 4 Bit Muxes := 1 - 2 Input 4 Bit Muxes := 2 - 16 Input 4 Bit Muxes := 1 + 2 Input 3 Bit Muxes := 775 + 3 Input 3 Bit Muxes := 42 + 12 Input 3 Bit Muxes := 2 + 8 Input 3 Bit Muxes := 24 + 15 Input 3 Bit Muxes := 14 5 Input 3 Bit Muxes := 1 107 Input 3 Bit Muxes := 3 100 Input 3 Bit Muxes := 1 + 2 Input 2 Bit Muxes := 1590 + 12 Input 2 Bit Muxes := 56 + 3 Input 2 Bit Muxes := 148 + 4 Input 2 Bit Muxes := 448 + 9 Input 2 Bit Muxes := 54 + 42 Input 2 Bit Muxes := 4 + 16 Input 2 Bit Muxes := 98 + 14 Input 2 Bit Muxes := 6 + 8 Input 2 Bit Muxes := 24 + 13 Input 2 Bit Muxes := 4 133 Input 2 Bit Muxes := 1 51 Input 2 Bit Muxes := 4 86 Input 2 Bit Muxes := 5 + 2 Input 1 Bit Muxes := 4048 + 12 Input 1 Bit Muxes := 195 + 8 Input 1 Bit Muxes := 2 + 3 Input 1 Bit Muxes := 3 + 4 Input 1 Bit Muxes := 4 5 Input 1 Bit Muxes := 7 - 4 Input 1 Bit Muxes := 3 - 2 Input 1 Bit Muxes := 4 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- @@ -361,9 +425,215 @@ Finished Part Resource Summary --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- -WARNING: [Synth 8-7080] Parallel synthesis criteria is not met ---------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:32 . Memory (MB): peak = 1661.754 ; gain = 684.277 +WARNING: [Synth 8-7129] Port BtnU in module vga is either unconnected or has no load +WARNING: [Synth 8-7129] Port BtnD in module vga is either unconnected or has no load +INFO: [Synth 8-3886] merging instance 'redWinYOffset_reg[0][7]' (FDCE) to 'redWinXOffset_reg[0][7]' +INFO: [Synth 8-3886] merging instance 'redWinYOffset_reg[0][8]' (FDCE) to 'redWinXOffset_reg[0][7]' +INFO: [Synth 8-3886] merging instance 'redWinYOffset_reg[0][9]' (FDCE) to 'redWinXOffset_reg[0][7]' +INFO: [Synth 8-3886] merging instance 'redWinYOffset_reg[1][7]' (FDCE) to 'redWinXOffset_reg[1][7]' +INFO: [Synth 8-3886] merging instance 'redWinYOffset_reg[1][8]' (FDCE) to 'redWinXOffset_reg[1][7]' +INFO: [Synth 8-3886] merging instance 'redWinYOffset_reg[1][9]' (FDCE) to 'redWinXOffset_reg[1][7]' +INFO: [Synth 8-3886] merging instance 'redWinYOffset_reg[2][7]' (FDCE) to 'redWinXOffset_reg[2][7]' +INFO: [Synth 8-3886] merging instance 'redWinYOffset_reg[2][8]' (FDCE) to 'redWinXOffset_reg[2][7]' +INFO: [Synth 8-3886] merging instance 'redWinYOffset_reg[2][9]' (FDCE) to 'redWinXOffset_reg[2][7]' +INFO: [Synth 8-3886] merging instance 'redWinYOffset_reg[3][7]' (FDCE) to 'redWinYOffset_reg[3][8]' +INFO: [Synth 8-3886] merging instance 'redWinYOffset_reg[3][8]' (FDCE) to 'redWinYOffset_reg[3][9]' +INFO: [Synth 8-3886] merging instance 'redWinYOffset_reg[3][9]' (FDCE) to 'redWinXOffset_reg[3][7]' +INFO: [Synth 8-3886] merging instance 'redWinYOffset_reg[4][7]' (FDCE) to 'redWinXOffset_reg[4][7]' +INFO: [Synth 8-3886] merging instance 'redWinYOffset_reg[4][8]' (FDCE) to 'redWinXOffset_reg[4][7]' +INFO: [Synth 8-3886] merging instance 'redWinYOffset_reg[4][9]' (FDCE) to 'redWinXOffset_reg[4][7]' +INFO: [Synth 8-3886] merging instance 'redWinYOffset_reg[5][7]' (FDCE) to 'redWinXOffset_reg[5][7]' +INFO: [Synth 8-3886] merging instance 'redWinYOffset_reg[5][8]' (FDCE) to 'redWinXOffset_reg[5][7]' +INFO: [Synth 8-3886] merging instance 'redWinYOffset_reg[5][9]' (FDCE) to 'redWinXOffset_reg[5][7]' +INFO: [Synth 8-3886] merging instance 'redWinYOffset_reg[6][7]' (FDCE) to 'redWinXOffset_reg[6][7]' +INFO: [Synth 8-3886] merging instance 'redWinYOffset_reg[6][8]' (FDCE) to 'redWinXOffset_reg[6][7]' +INFO: [Synth 8-3886] merging instance 'redWinYOffset_reg[6][9]' (FDCE) to 'redWinXOffset_reg[6][7]' +INFO: [Synth 8-3886] merging instance 'yellowWinYOffset_reg[4][7]' (FDCE) to 'yellowWinXOffset_reg[4][7]' +INFO: [Synth 8-3886] merging instance 'yellowWinYOffset_reg[4][8]' (FDCE) to 'yellowWinXOffset_reg[4][7]' +INFO: [Synth 8-3886] merging instance 'yellowWinYOffset_reg[4][9]' (FDCE) to 'yellowWinXOffset_reg[4][7]' +INFO: [Synth 8-3886] merging instance 'yellowWinYOffset_reg[5][7]' (FDCE) to 'yellowWinXOffset_reg[5][7]' +INFO: [Synth 8-3886] merging instance 'yellowWinYOffset_reg[5][8]' (FDCE) to 'yellowWinXOffset_reg[5][7]' +INFO: [Synth 8-3886] merging instance 'yellowWinYOffset_reg[5][9]' (FDCE) to 'yellowWinXOffset_reg[5][7]' +INFO: [Synth 8-3886] merging instance 'yellowWinXOffset_reg[4][7]' (FDCE) to 'yellowWinXOffset_reg[4][8]' +INFO: [Synth 8-3886] merging instance 'yellowWinXOffset_reg[4][8]' (FDCE) to 'yellowWinXOffset_reg[4][9]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\yellowWinXOffset_reg[4][9] ) +INFO: [Synth 8-3886] merging instance 'yellowWinXOffset_reg[5][7]' (FDCE) to 'yellowWinXOffset_reg[5][8]' +INFO: [Synth 8-3886] merging instance 'yellowWinXOffset_reg[5][8]' (FDCE) to 'yellowWinXOffset_reg[5][9]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\yellowWinXOffset_reg[5][9] ) +INFO: [Synth 8-3886] merging instance 'redWinXOffset_reg[0][7]' (FDCE) to 'redWinXOffset_reg[0][8]' +INFO: [Synth 8-3886] merging instance 'redWinXOffset_reg[0][8]' (FDCE) to 'redWinXOffset_reg[0][9]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\redWinXOffset_reg[0][9] ) +INFO: [Synth 8-3886] merging instance 'redWinXOffset_reg[1][7]' (FDCE) to 'redWinXOffset_reg[1][8]' +INFO: [Synth 8-3886] merging instance 'redWinXOffset_reg[1][8]' (FDCE) to 'redWinXOffset_reg[1][9]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\redWinXOffset_reg[1][9] ) +INFO: [Synth 8-3886] merging instance 'redWinXOffset_reg[2][7]' (FDCE) to 'redWinXOffset_reg[2][8]' +INFO: [Synth 8-3886] merging instance 'redWinXOffset_reg[2][8]' (FDCE) to 'redWinXOffset_reg[2][9]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\redWinXOffset_reg[2][9] ) +INFO: [Synth 8-3886] merging instance 'redWinXOffset_reg[3][7]' (FDCE) to 'redWinXOffset_reg[3][8]' +INFO: [Synth 8-3886] merging instance 'redWinXOffset_reg[3][8]' (FDCE) to 'redWinXOffset_reg[3][9]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\redWinXOffset_reg[3][9] ) +INFO: [Synth 8-3886] merging instance 'redWinXOffset_reg[4][7]' (FDCE) to 'redWinXOffset_reg[4][8]' +INFO: [Synth 8-3886] merging instance 'redWinXOffset_reg[4][8]' (FDCE) to 'redWinXOffset_reg[4][9]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\redWinXOffset_reg[4][9] ) +INFO: [Synth 8-3886] merging instance 'redWinXOffset_reg[5][7]' (FDCE) to 'redWinXOffset_reg[5][8]' +INFO: [Synth 8-3886] merging instance 'redWinXOffset_reg[5][8]' (FDCE) to 'redWinXOffset_reg[5][9]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\redWinXOffset_reg[5][9] ) +INFO: [Synth 8-3886] merging instance 'redWinXOffset_reg[6][7]' (FDCE) to 'redWinXOffset_reg[6][8]' +INFO: [Synth 8-3886] merging instance 'redWinXOffset_reg[6][8]' (FDCE) to 'redWinXOffset_reg[6][9]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\redWinXOffset_reg[6][9] ) +INFO: [Synth 8-3886] merging instance 'yellowWinYOffset_reg[0][7]' (FDCE) to 'yellowWinXOffset_reg[0][7]' +INFO: [Synth 8-3886] merging instance 'yellowWinYOffset_reg[0][8]' (FDCE) to 'yellowWinXOffset_reg[0][7]' +INFO: [Synth 8-3886] merging instance 'yellowWinYOffset_reg[0][9]' (FDCE) to 'yellowWinXOffset_reg[0][7]' +INFO: [Synth 8-3886] merging instance 'yellowWinYOffset_reg[1][7]' (FDCE) to 'yellowWinYOffset_reg[1][8]' +INFO: [Synth 8-3886] merging instance 'yellowWinYOffset_reg[1][8]' (FDCE) to 'yellowWinYOffset_reg[1][9]' +INFO: [Synth 8-3886] merging instance 'yellowWinYOffset_reg[1][9]' (FDCE) to 'yellowWinXOffset_reg[1][7]' +INFO: [Synth 8-3886] merging instance 'yellowWinYOffset_reg[2][7]' (FDCE) to 'yellowWinXOffset_reg[2][7]' +INFO: [Synth 8-3886] merging instance 'yellowWinYOffset_reg[2][8]' (FDCE) to 'yellowWinXOffset_reg[2][7]' +INFO: [Synth 8-3886] merging instance 'yellowWinYOffset_reg[2][9]' (FDCE) to 'yellowWinXOffset_reg[2][7]' +INFO: [Synth 8-3886] merging instance 'yellowWinYOffset_reg[3][7]' (FDCE) to 'yellowWinXOffset_reg[3][7]' +INFO: [Synth 8-3886] merging instance 'yellowWinYOffset_reg[3][8]' (FDCE) to 'yellowWinXOffset_reg[3][7]' +INFO: [Synth 8-3886] merging instance 'yellowWinYOffset_reg[3][9]' (FDCE) to 'yellowWinXOffset_reg[3][7]' +INFO: [Synth 8-3886] merging instance 'yellowWinYOffset_reg[6][7]' (FDCE) to 'yellowWinXOffset_reg[6][7]' +INFO: [Synth 8-3886] merging instance 'yellowWinYOffset_reg[6][8]' (FDCE) to 'yellowWinXOffset_reg[6][7]' +INFO: [Synth 8-3886] merging instance 'yellowWinYOffset_reg[6][9]' (FDCE) to 'yellowWinXOffset_reg[6][7]' +INFO: [Synth 8-3886] merging instance 'yellowWinXOffset_reg[0][7]' (FDCE) to 'yellowWinXOffset_reg[0][8]' +INFO: [Synth 8-3886] merging instance 'yellowWinXOffset_reg[0][8]' (FDCE) to 'yellowWinXOffset_reg[0][9]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\yellowWinXOffset_reg[0][9] ) +INFO: [Synth 8-3886] merging instance 'yellowWinXOffset_reg[1][7]' (FDCE) to 'yellowWinXOffset_reg[1][8]' +INFO: [Synth 8-3886] merging instance 'yellowWinXOffset_reg[1][8]' (FDCE) to 'yellowWinXOffset_reg[1][9]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\yellowWinXOffset_reg[1][9] ) +INFO: [Synth 8-3886] merging instance 'yellowWinXOffset_reg[2][7]' (FDCE) to 'yellowWinXOffset_reg[2][8]' +INFO: [Synth 8-3886] merging instance 'yellowWinXOffset_reg[2][8]' (FDCE) to 'yellowWinXOffset_reg[2][9]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\yellowWinXOffset_reg[2][9] ) +INFO: [Synth 8-3886] merging instance 'yellowWinXOffset_reg[3][7]' (FDCE) to 'yellowWinXOffset_reg[3][8]' +INFO: [Synth 8-3886] merging instance 'yellowWinXOffset_reg[3][8]' (FDCE) to 'yellowWinXOffset_reg[3][9]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\yellowWinXOffset_reg[3][9] ) +INFO: [Synth 8-3886] merging instance 'yellowWinXOffset_reg[6][7]' (FDCE) to 'yellowWinXOffset_reg[6][8]' +INFO: [Synth 8-3886] merging instance 'yellowWinXOffset_reg[6][8]' (FDCE) to 'yellowWinXOffset_reg[6][9]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\yellowWinXOffset_reg[6][9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\redPieceXOffset_reg[0][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\redPieceXOffset_reg[1][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\redPieceXOffset_reg[2][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\redPieceXOffset_reg[3][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\redPieceXOffset_reg[4][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\redPieceXOffset_reg[5][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\redPieceXOffset_reg[6][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\redPieceXOffset_reg[7][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\redPieceXOffset_reg[8][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\redPieceXOffset_reg[9][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\redPieceXOffset_reg[10][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\redPieceXOffset_reg[11][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\redPieceXOffset_reg[12][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\redPieceXOffset_reg[13][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\redPieceXOffset_reg[15][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\redPieceXOffset_reg[16][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\redPieceXOffset_reg[17][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\redPieceXOffset_reg[19][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\yellowPieceXOffset_reg[0][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\yellowPieceXOffset_reg[1][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\yellowPieceXOffset_reg[2][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\yellowPieceXOffset_reg[3][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\yellowPieceXOffset_reg[5][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\yellowPieceXOffset_reg[6][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\yellowPieceXOffset_reg[7][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\yellowPieceXOffset_reg[8][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\yellowPieceXOffset_reg[9][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\yellowPieceXOffset_reg[10][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\yellowPieceXOffset_reg[11][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\yellowPieceXOffset_reg[12][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\yellowPieceXOffset_reg[13][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\yellowPieceXOffset_reg[14][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\yellowPieceXOffset_reg[15][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\yellowPieceXOffset_reg[16][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\yellowPieceXOffset_reg[18][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\yellowPieceXOffset_reg[19][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\yellowPieceXOffset_reg[20][0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (loop_done_reg) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\column_reg[0]_LDC ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\column_reg[1]_LDC ) +INFO: [Synth 8-5544] ROM "vgaRed" won't be mapped to Block RAM because address size (4) smaller than threshold (5) +INFO: [Synth 8-5544] ROM "vgaGrn" won't be mapped to Block RAM because address size (4) smaller than threshold (5) +INFO: [Synth 8-3886] merging instance 'bg_tile_gfx/paletteIndex_reg[0]' (FD) to 'bg_tile_gfx/paletteIndex_reg[1]' +INFO: [Synth 8-3886] merging instance 'bg_tile_gfx/paletteIndex_reg[1]' (FD) to 'bg_tile_gfx/paletteIndex_reg[2]' +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk2[0].yellow_piece_gfx /\paletteIndex_reg[0] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk2[1].yellow_piece_gfx /\paletteIndex_reg[0] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk2[2].yellow_piece_gfx /\paletteIndex_reg[0] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk2[3].yellow_piece_gfx /\paletteIndex_reg[0] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk2[4].yellow_piece_gfx /\paletteIndex_reg[0] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk2[5].yellow_piece_gfx /\paletteIndex_reg[0] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk2[6].yellow_piece_gfx /\paletteIndex_reg[0] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk2[7].yellow_piece_gfx /\paletteIndex_reg[0] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk2[8].yellow_piece_gfx /\paletteIndex_reg[0] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk2[9].yellow_piece_gfx /\paletteIndex_reg[0] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk2[10].yellow_piece_gfx /\paletteIndex_reg[0] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk2[11].yellow_piece_gfx /\paletteIndex_reg[0] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk2[12].yellow_piece_gfx /\paletteIndex_reg[0] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk2[13].yellow_piece_gfx /\paletteIndex_reg[0] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk2[14].yellow_piece_gfx /\paletteIndex_reg[0] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk2[15].yellow_piece_gfx /\paletteIndex_reg[0] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk2[16].yellow_piece_gfx /\paletteIndex_reg[0] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk2[17].yellow_piece_gfx /\paletteIndex_reg[0] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk2[18].yellow_piece_gfx /\paletteIndex_reg[0] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk2[19].yellow_piece_gfx /\paletteIndex_reg[0] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk2[20].yellow_piece_gfx /\paletteIndex_reg[0] ) +INFO: [Synth 8-3886] merging instance 'genblk1[0].red_piece_gfx/paletteIndex_reg[3]' (FD) to 'genblk1[0].red_piece_gfx/paletteIndex_reg[2]' +INFO: [Synth 8-3886] merging instance 'genblk1[1].red_piece_gfx/paletteIndex_reg[3]' (FD) to 'genblk1[1].red_piece_gfx/paletteIndex_reg[2]' +INFO: [Synth 8-3886] merging instance 'genblk1[2].red_piece_gfx/paletteIndex_reg[3]' (FD) to 'genblk1[2].red_piece_gfx/paletteIndex_reg[2]' +INFO: [Synth 8-3886] merging instance 'genblk1[3].red_piece_gfx/paletteIndex_reg[3]' (FD) to 'genblk1[3].red_piece_gfx/paletteIndex_reg[2]' +INFO: [Synth 8-3886] merging instance 'genblk1[4].red_piece_gfx/paletteIndex_reg[3]' (FD) to 'genblk1[4].red_piece_gfx/paletteIndex_reg[2]' +INFO: [Synth 8-3886] merging instance 'genblk1[5].red_piece_gfx/paletteIndex_reg[3]' (FD) to 'genblk1[5].red_piece_gfx/paletteIndex_reg[2]' +INFO: [Synth 8-3886] merging instance 'genblk1[6].red_piece_gfx/paletteIndex_reg[3]' (FD) to 'genblk1[6].red_piece_gfx/paletteIndex_reg[2]' +INFO: [Synth 8-3886] merging instance 'genblk1[7].red_piece_gfx/paletteIndex_reg[3]' (FD) to 'genblk1[7].red_piece_gfx/paletteIndex_reg[2]' +INFO: [Synth 8-3886] merging instance 'genblk1[8].red_piece_gfx/paletteIndex_reg[3]' (FD) to 'genblk1[8].red_piece_gfx/paletteIndex_reg[2]' +INFO: [Synth 8-3886] merging instance 'genblk1[9].red_piece_gfx/paletteIndex_reg[3]' (FD) to 'genblk1[9].red_piece_gfx/paletteIndex_reg[2]' +INFO: [Synth 8-3886] merging instance 'genblk1[10].red_piece_gfx/paletteIndex_reg[3]' (FD) to 'genblk1[10].red_piece_gfx/paletteIndex_reg[2]' +INFO: [Synth 8-3886] merging instance 'genblk1[11].red_piece_gfx/paletteIndex_reg[3]' (FD) to 'genblk1[11].red_piece_gfx/paletteIndex_reg[2]' +INFO: [Synth 8-3886] merging instance 'genblk1[12].red_piece_gfx/paletteIndex_reg[3]' (FD) to 'genblk1[12].red_piece_gfx/paletteIndex_reg[2]' +INFO: [Synth 8-3886] merging instance 'genblk1[13].red_piece_gfx/paletteIndex_reg[3]' (FD) to 'genblk1[13].red_piece_gfx/paletteIndex_reg[2]' +INFO: [Synth 8-3886] merging instance 'genblk1[14].red_piece_gfx/paletteIndex_reg[3]' (FD) to 'genblk1[14].red_piece_gfx/paletteIndex_reg[2]' +INFO: [Synth 8-3886] merging instance 'genblk1[15].red_piece_gfx/paletteIndex_reg[3]' (FD) to 'genblk1[15].red_piece_gfx/paletteIndex_reg[2]' +INFO: [Synth 8-3886] merging instance 'genblk1[16].red_piece_gfx/paletteIndex_reg[3]' (FD) to 'genblk1[16].red_piece_gfx/paletteIndex_reg[2]' +INFO: [Synth 8-3886] merging instance 'genblk1[17].red_piece_gfx/paletteIndex_reg[3]' (FD) to 'genblk1[17].red_piece_gfx/paletteIndex_reg[2]' +INFO: [Synth 8-3886] merging instance 'genblk1[18].red_piece_gfx/paletteIndex_reg[3]' (FD) to 'genblk1[18].red_piece_gfx/paletteIndex_reg[2]' +INFO: [Synth 8-3886] merging instance 'genblk1[19].red_piece_gfx/paletteIndex_reg[3]' (FD) to 'genblk1[19].red_piece_gfx/paletteIndex_reg[2]' +INFO: [Synth 8-3886] merging instance 'genblk1[20].red_piece_gfx/paletteIndex_reg[3]' (FD) to 'genblk1[20].red_piece_gfx/paletteIndex_reg[2]' +INFO: [Synth 8-3886] merging instance 'genblk2[0].yellow_piece_gfx/paletteIndex_reg[3]' (FD) to 'genblk2[0].yellow_piece_gfx/paletteIndex_reg[2]' +INFO: [Synth 8-3886] merging instance 'genblk2[1].yellow_piece_gfx/paletteIndex_reg[3]' (FD) to 'genblk2[1].yellow_piece_gfx/paletteIndex_reg[2]' +INFO: [Synth 8-3886] merging instance 'genblk2[2].yellow_piece_gfx/paletteIndex_reg[3]' (FD) to 'genblk2[2].yellow_piece_gfx/paletteIndex_reg[2]' +INFO: [Synth 8-3886] merging instance 'genblk2[3].yellow_piece_gfx/paletteIndex_reg[3]' (FD) to 'genblk2[3].yellow_piece_gfx/paletteIndex_reg[2]' +INFO: [Synth 8-3886] merging instance 'genblk2[4].yellow_piece_gfx/paletteIndex_reg[3]' (FD) to 'genblk2[4].yellow_piece_gfx/paletteIndex_reg[2]' +INFO: [Synth 8-3886] merging instance 'genblk2[5].yellow_piece_gfx/paletteIndex_reg[3]' (FD) to 'genblk2[5].yellow_piece_gfx/paletteIndex_reg[2]' +INFO: [Synth 8-3886] merging instance 'genblk2[6].yellow_piece_gfx/paletteIndex_reg[3]' (FD) to 'genblk2[6].yellow_piece_gfx/paletteIndex_reg[2]' +INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk1[0].red_piece_gfx /\paletteIndex_reg[2] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk1[1].red_piece_gfx /\paletteIndex_reg[2] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk1[2].red_piece_gfx /\paletteIndex_reg[2] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk1[3].red_piece_gfx /\paletteIndex_reg[2] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk1[4].red_piece_gfx /\paletteIndex_reg[2] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk1[5].red_piece_gfx /\paletteIndex_reg[2] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk1[6].red_piece_gfx /\paletteIndex_reg[2] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk1[7].red_piece_gfx /\paletteIndex_reg[2] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk1[8].red_piece_gfx /\paletteIndex_reg[2] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk1[9].red_piece_gfx /\paletteIndex_reg[2] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk1[10].red_piece_gfx /\paletteIndex_reg[2] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk1[11].red_piece_gfx /\paletteIndex_reg[2] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk1[12].red_piece_gfx /\paletteIndex_reg[2] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk1[13].red_piece_gfx /\paletteIndex_reg[2] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk1[14].red_piece_gfx /\paletteIndex_reg[2] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk1[15].red_piece_gfx /\paletteIndex_reg[2] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk1[16].red_piece_gfx /\paletteIndex_reg[2] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk1[17].red_piece_gfx /\paletteIndex_reg[2] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk1[18].red_piece_gfx /\paletteIndex_reg[2] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk1[19].red_piece_gfx /\paletteIndex_reg[2] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\genblk1[20].red_piece_gfx /\paletteIndex_reg[2] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (yellow_indicator_gfx/\paletteIndex_reg[0] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (yellow_wins_gfx/\paletteIndex_reg[0] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (yellows_turn_gfx/\paletteIndex_reg[0] ) +INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-3333] propagating constant 1 across sequential element (red_indicator_gfx/\paletteIndex_reg[2] ) +INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:02:12 ; elapsed = 00:05:23 . Memory (MB): peak = 2599.844 ; gain = 1623.266 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting @@ -399,31 +669,6 @@ ROM: Preliminary Mapping Report |tie_game | paletteIndex | 64x3 | LUT | |tie_game | paletteIndex | 64x3 | LUT | |tie_game | paletteIndex | 64x3 | LUT | -|logo | paletteIndex | 128x3 | LUT | -|logo | paletteIndex | 128x3 | LUT | -|logo | paletteIndex | 128x3 | LUT | -|logo | paletteIndex | 128x3 | LUT | -|logo | paletteIndex | 128x3 | LUT | -|logo | paletteIndex | 128x3 | LUT | -|logo | paletteIndex | 128x3 | LUT | -|logo | paletteIndex | 128x3 | LUT | -|logo | paletteIndex | 128x3 | LUT | -|logo | paletteIndex | 128x3 | LUT | -|board | paletteIndex | 256x4 | LUT | -|board | paletteIndex | 256x4 | LUT | -|board | paletteIndex | 256x4 | LUT | -|red_wins | paletteIndex | 64x2 | LUT | -|red_wins | paletteIndex | 64x2 | LUT | -|red_wins | paletteIndex | 64x2 | LUT | -|red_wins | paletteIndex | 64x2 | LUT | -|red_wins | paletteIndex | 64x2 | LUT | -|red_wins | paletteIndex | 64x2 | LUT | -|tie_game | paletteIndex | 64x3 | LUT | -|tie_game | paletteIndex | 64x3 | LUT | -|tie_game | paletteIndex | 64x3 | LUT | -|tie_game | paletteIndex | 64x3 | LUT | -|tie_game | paletteIndex | 64x3 | LUT | -|tie_game | paletteIndex | 64x3 | LUT | +------------+--------------+---------------+----------------+ --------------------------------------------------------------------------------- @@ -433,19 +678,19 @@ Finished ROM, RAM, DSP, Shift Register and Retiming Reporting Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:14 ; elapsed = 00:00:35 . Memory (MB): peak = 1661.754 ; gain = 684.277 +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:02:14 ; elapsed = 00:05:28 . Memory (MB): peak = 2599.844 ; gain = 1623.266 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:14 ; elapsed = 00:00:36 . Memory (MB): peak = 1661.754 ; gain = 684.277 +Finished Timing Optimization : Time (s): cpu = 00:02:16 ; elapsed = 00:05:34 . Memory (MB): peak = 2599.844 ; gain = 1623.266 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:14 ; elapsed = 00:00:36 . Memory (MB): peak = 1661.754 ; gain = 684.277 +Finished Technology Mapping : Time (s): cpu = 00:02:28 ; elapsed = 00:05:54 . Memory (MB): peak = 2599.844 ; gain = 1623.266 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion @@ -463,37 +708,37 @@ Start Final Netlist Cleanup Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:00:15 ; elapsed = 00:00:39 . Memory (MB): peak = 1661.754 ; gain = 684.277 +Finished IO Insertion : Time (s): cpu = 00:02:34 ; elapsed = 00:06:06 . Memory (MB): peak = 2599.844 ; gain = 1623.266 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:00:15 ; elapsed = 00:00:39 . Memory (MB): peak = 1661.754 ; gain = 684.277 +Finished Renaming Generated Instances : Time (s): cpu = 00:02:34 ; elapsed = 00:06:06 . Memory (MB): peak = 2599.844 ; gain = 1623.266 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:15 ; elapsed = 00:00:39 . Memory (MB): peak = 1661.754 ; gain = 684.277 +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:02:35 ; elapsed = 00:06:06 . Memory (MB): peak = 2599.844 ; gain = 1623.266 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:00:15 ; elapsed = 00:00:39 . Memory (MB): peak = 1661.754 ; gain = 684.277 +Finished Renaming Generated Ports : Time (s): cpu = 00:02:35 ; elapsed = 00:06:06 . Memory (MB): peak = 2599.844 ; gain = 1623.266 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:15 ; elapsed = 00:00:39 . Memory (MB): peak = 1661.754 ; gain = 684.277 +Finished Handling Custom Attributes : Time (s): cpu = 00:02:35 ; elapsed = 00:06:08 . Memory (MB): peak = 2599.844 ; gain = 1623.266 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:00:15 ; elapsed = 00:00:39 . Memory (MB): peak = 1661.754 ; gain = 684.277 +Finished Renaming Generated Nets : Time (s): cpu = 00:02:35 ; elapsed = 00:06:08 . Memory (MB): peak = 2599.844 ; gain = 1623.266 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report @@ -509,43 +754,49 @@ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ -|1 |BUFG | 2| -|2 |CARRY4 | 102| -|3 |LUT1 | 195| -|4 |LUT2 | 69| -|5 |LUT3 | 65| -|6 |LUT4 | 88| -|7 |LUT5 | 105| -|8 |LUT6 | 603| -|9 |MUXF7 | 16| -|10 |MUXF8 | 3| -|11 |FDRE | 218| -|12 |IBUF | 1| -|13 |OBUF | 14| +|1 |BUFG | 3| +|2 |CARRY4 | 1667| +|3 |LUT1 | 851| +|4 |LUT2 | 2641| +|5 |LUT3 | 3249| +|6 |LUT4 | 2736| +|7 |LUT5 | 3875| +|8 |LUT6 | 10502| +|9 |MUXF7 | 539| +|10 |MUXF8 | 76| +|11 |FDCE | 1463| +|12 |FDPE | 788| +|13 |FDRE | 281| +|14 |LDC | 420| +|15 |IBUF | 6| +|16 |OBUF | 14| +------+-------+------+ --------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:00:15 ; elapsed = 00:00:39 . Memory (MB): peak = 1661.754 ; gain = 684.277 +Finished Writing Synthesis Report : Time (s): cpu = 00:02:35 ; elapsed = 00:06:08 . Memory (MB): peak = 2599.844 ; gain = 1623.266 --------------------------------------------------------------------------------- -Synthesis finished with 0 errors, 0 critical warnings and 1 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:10 ; elapsed = 00:00:38 . Memory (MB): peak = 1661.754 ; gain = 621.055 -Synthesis Optimization Complete : Time (s): cpu = 00:00:15 ; elapsed = 00:00:39 . Memory (MB): peak = 1661.754 ; gain = 684.277 +Synthesis finished with 0 errors, 0 critical warnings and 2 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:01:24 ; elapsed = 00:05:27 . Memory (MB): peak = 2599.844 ; gain = 1436.816 +Synthesis Optimization Complete : Time (s): cpu = 00:02:35 ; elapsed = 00:06:08 . Memory (MB): peak = 2599.844 ; gain = 1623.266 INFO: [Project 1-571] Translating synthesized netlist -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 1661.754 ; gain = 0.000 -INFO: [Netlist 29-17] Analyzing 121 Unisim elements for replacement +Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.216 . Memory (MB): peak = 2599.844 ; gain = 0.000 +INFO: [Netlist 29-17] Analyzing 2702 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +WARNING: [Netlist 29-101] Netlist 'vga' is not ideal for floorplanning, since the cellview 'connect4_core_design' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1661.754 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 2599.844 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: -No Unisim elements were transformed. + A total of 420 instances were transformed. + LDC => LDCE: 420 instances -Synth Design complete | Checksum: 99d812a8 +Synth Design complete | Checksum: dcbcac8 INFO: [Common 17-83] Releasing license: Synthesis -96 Infos, 137 Warnings, 1 Critical Warnings and 0 Errors encountered. +310 Infos, 138 Warnings, 1 Critical Warnings and 0 Errors encountered. synth_design completed successfully -synth_design: Time (s): cpu = 00:00:17 ; elapsed = 00:00:42 . Memory (MB): peak = 1661.754 ; gain = 1091.055 +synth_design: Time (s): cpu = 00:02:38 ; elapsed = 00:06:16 . Memory (MB): peak = 2599.844 ; gain = 2031.355 INFO: [runtcl-6] Synthesis results are not added to the cache due to CRITICAL_WARNING -Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1661.754 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/Users/james/Documents/vga/vga.runs/synth_1/vga.dcp' has been generated. +Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.031 . Memory (MB): peak = 2599.844 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'C:/Users/james/Documents/fpga-connect4/vga.runs/synth_1/vga.dcp' has been generated. +write_checkpoint: Time (s): cpu = 00:00:02 ; elapsed = 00:00:06 . Memory (MB): peak = 2599.844 ; gain = 0.000 INFO: [runtcl-4] Executing : report_utilization -file vga_utilization_synth.rpt -pb vga_utilization_synth.pb -INFO: [Common 17-206] Exiting Vivado at Thu Apr 18 03:14:41 2024... +INFO: [Common 17-206] Exiting Vivado at Mon Apr 22 21:21:43 2024... diff --git a/vga.runs/synth_1/vga_utilization_synth.pb b/vga.runs/synth_1/vga_utilization_synth.pb index 4c5b4ef..e639df7 100644 Binary files a/vga.runs/synth_1/vga_utilization_synth.pb and b/vga.runs/synth_1/vga_utilization_synth.pb differ diff --git a/vga.runs/synth_1/vga_utilization_synth.rpt b/vga.runs/synth_1/vga_utilization_synth.rpt index b7e02ed..1475ece 100644 --- a/vga.runs/synth_1/vga_utilization_synth.rpt +++ b/vga.runs/synth_1/vga_utilization_synth.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 -| Date : Thu Apr 18 03:14:41 2024 +| Date : Mon Apr 22 21:21:43 2024 | Host : me running 64-bit major release (build 9200) | Command : report_utilization -file vga_utilization_synth.rpt -pb vga_utilization_synth.pb | Design : vga @@ -28,18 +28,18 @@ Table of Contents 1. Slice Logic -------------- -+-------------------------+------+-------+------------+-----------+-------+ -| Site Type | Used | Fixed | Prohibited | Available | Util% | -+-------------------------+------+-------+------------+-----------+-------+ -| Slice LUTs* | 1049 | 0 | 0 | 63400 | 1.65 | -| LUT as Logic | 1049 | 0 | 0 | 63400 | 1.65 | -| LUT as Memory | 0 | 0 | 0 | 19000 | 0.00 | -| Slice Registers | 218 | 0 | 0 | 126800 | 0.17 | -| Register as Flip Flop | 218 | 0 | 0 | 126800 | 0.17 | -| Register as Latch | 0 | 0 | 0 | 126800 | 0.00 | -| F7 Muxes | 16 | 0 | 0 | 31700 | 0.05 | -| F8 Muxes | 3 | 0 | 0 | 15850 | 0.02 | -+-------------------------+------+-------+------------+-----------+-------+ ++-------------------------+-------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-------------------------+-------+-------+------------+-----------+-------+ +| Slice LUTs* | 20362 | 0 | 0 | 63400 | 32.12 | +| LUT as Logic | 20362 | 0 | 0 | 63400 | 32.12 | +| LUT as Memory | 0 | 0 | 0 | 19000 | 0.00 | +| Slice Registers | 2952 | 0 | 0 | 126800 | 2.33 | +| Register as Flip Flop | 2532 | 0 | 0 | 126800 | 2.00 | +| Register as Latch | 420 | 0 | 0 | 126800 | 0.33 | +| F7 Muxes | 539 | 0 | 0 | 31700 | 1.70 | +| F8 Muxes | 76 | 0 | 0 | 15850 | 0.48 | ++-------------------------+-------+-------+------------+-----------+-------+ * Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. Warning! LUT value is adjusted to account for LUT combining. @@ -56,10 +56,10 @@ Warning! LUT value is adjusted to account for LUT combining. | 0 | _ | Set | - | | 0 | _ | Reset | - | | 0 | Yes | - | - | -| 0 | Yes | - | Set | -| 0 | Yes | - | Reset | +| 788 | Yes | - | Set | +| 1883 | Yes | - | Reset | | 0 | Yes | Set | - | -| 218 | Yes | Reset | - | +| 281 | Yes | Reset | - | +-------+--------------+-------------+--------------+ @@ -92,7 +92,7 @@ Warning! LUT value is adjusted to account for LUT combining. +-----------------------------+------+-------+------------+-----------+-------+ | Site Type | Used | Fixed | Prohibited | Available | Util% | +-----------------------------+------+-------+------------+-----------+-------+ -| Bonded IOB | 15 | 0 | 0 | 210 | 7.14 | +| Bonded IOB | 20 | 0 | 0 | 210 | 9.52 | | Bonded IPADs | 0 | 0 | 0 | 2 | 0.00 | | PHY_CONTROL | 0 | 0 | 0 | 6 | 0.00 | | PHASER_REF | 0 | 0 | 0 | 6 | 0.00 | @@ -114,7 +114,7 @@ Warning! LUT value is adjusted to account for LUT combining. +------------+------+-------+------------+-----------+-------+ | Site Type | Used | Fixed | Prohibited | Available | Util% | +------------+------+-------+------------+-----------+-------+ -| BUFGCTRL | 2 | 0 | 0 | 32 | 6.25 | +| BUFGCTRL | 3 | 0 | 0 | 32 | 9.38 | | BUFIO | 0 | 0 | 0 | 24 | 0.00 | | MMCME2_ADV | 0 | 0 | 0 | 6 | 0.00 | | PLLE2_ADV | 0 | 0 | 0 | 6 | 0.00 | @@ -145,23 +145,26 @@ Warning! LUT value is adjusted to account for LUT combining. 7. Primitives ------------- -+----------+------+---------------------+ -| Ref Name | Used | Functional Category | -+----------+------+---------------------+ -| LUT6 | 603 | LUT | -| FDRE | 218 | Flop & Latch | -| LUT1 | 195 | LUT | -| LUT5 | 105 | LUT | -| CARRY4 | 102 | CarryLogic | -| LUT4 | 88 | LUT | -| LUT2 | 69 | LUT | -| LUT3 | 65 | LUT | -| MUXF7 | 16 | MuxFx | -| OBUF | 14 | IO | -| MUXF8 | 3 | MuxFx | -| BUFG | 2 | Clock | -| IBUF | 1 | IO | -+----------+------+---------------------+ ++----------+-------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+-------+---------------------+ +| LUT6 | 10502 | LUT | +| LUT5 | 3875 | LUT | +| LUT3 | 3249 | LUT | +| LUT4 | 2736 | LUT | +| LUT2 | 2641 | LUT | +| CARRY4 | 1667 | CarryLogic | +| FDCE | 1463 | Flop & Latch | +| LUT1 | 851 | LUT | +| FDPE | 788 | Flop & Latch | +| MUXF7 | 539 | MuxFx | +| LDCE | 420 | Flop & Latch | +| FDRE | 281 | Flop & Latch | +| MUXF8 | 76 | MuxFx | +| OBUF | 14 | IO | +| IBUF | 6 | IO | +| BUFG | 3 | Clock | ++----------+-------+---------------------+ 8. Black Boxes diff --git a/vga.runs/synth_1/vivado.jou b/vga.runs/synth_1/vivado.jou index 47bcccf..51ab5cb 100644 --- a/vga.runs/synth_1/vivado.jou +++ b/vga.runs/synth_1/vivado.jou @@ -3,12 +3,12 @@ # SW Build 4029153 on Fri Oct 13 20:14:34 MDT 2023 # IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 # SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 -# Start of session at: Thu Apr 18 03:13:51 2024 -# Process ID: 40688 -# Current directory: C:/Users/james/Documents/vga/vga.runs/synth_1 +# Start of session at: Mon Apr 22 21:15:15 2024 +# Process ID: 36016 +# Current directory: C:/Users/james/Documents/fpga-connect4/vga.runs/synth_1 # Command line: vivado.exe -log vga.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source vga.tcl -# Log file: C:/Users/james/Documents/vga/vga.runs/synth_1/vga.vds -# Journal file: C:/Users/james/Documents/vga/vga.runs/synth_1\vivado.jou +# Log file: C:/Users/james/Documents/fpga-connect4/vga.runs/synth_1/vga.vds +# Journal file: C:/Users/james/Documents/fpga-connect4/vga.runs/synth_1\vivado.jou # Running On: me, OS: Windows, CPU Frequency: 2918 MHz, CPU Physical cores: 14, Host memory: 34016 MB #----------------------------------------------------------- source vga.tcl -notrace diff --git a/vga.runs/synth_1/vivado.pb b/vga.runs/synth_1/vivado.pb index 1070dcf..56e1e94 100644 Binary files a/vga.runs/synth_1/vivado.pb and b/vga.runs/synth_1/vivado.pb differ diff --git a/vga.srcs/constrs_1/new/vga.xdc b/vga.srcs/constrs_1/new/vga.xdc index 011ca84..53588c9 100644 --- a/vga.srcs/constrs_1/new/vga.xdc +++ b/vga.srcs/constrs_1/new/vga.xdc @@ -65,4 +65,13 @@ set_property PACKAGE_PIN M17 [get_ports BtnR] set_property IOSTANDARD LVCMOS33 [get_ports BtnR] #Bank = 14, Pin name = IO_L21P_T3_DQS_14, Sch name = BTND set_property PACKAGE_PIN P18 [get_ports BtnD] -set_property IOSTANDARD LVCMOS33 [get_ports BtnD] \ No newline at end of file +set_property IOSTANDARD LVCMOS33 [get_ports BtnD] + +set_property PACKAGE_PIN D8 [get_ports {vgaBlu[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlu[3]}] + +set_property PACKAGE_PIN V10 [get_ports {switch15Debug}] +set_property IOSTANDARD LVCMOS33 [get_ports {switch15Debug}] + +set_property PACKAGE_PIN C12 [get_ports {btnCPUReset}] +set_property IOSTANDARD LVCMOS33 [get_ports {btnCPUReset}] \ No newline at end of file diff --git a/vga.srcs/sources_1/new/TESTcore_design.v b/vga.srcs/sources_1/new/TESTcore_design.v index 72c7019..1245040 100644 --- a/vga.srcs/sources_1/new/TESTcore_design.v +++ b/vga.srcs/sources_1/new/TESTcore_design.v @@ -22,12 +22,12 @@ `timescale 1ns / 1ps -module TESTcore_design ( +module connect4_core_design ( input wire clk, // Clock signal input wire reset, // Reset signal input wire btn_left, // Left button input input wire btn_right, // Right button input - input wire btn_up, // Up button input (for dropping pieces) + input wire btn_up, // CENTER ~~Up~~ button input (for dropping pieces) output reg showLogo, output reg [9:0] boardYOffset, output reg showRedsTurn, @@ -43,7 +43,12 @@ module TESTcore_design ( output wire [209:0] FLAT__redPieceXOffset, output wire [209:0] FLAT__yellowPieceYOffset, output wire [209:0] FLAT__yellowPieceXOffset, - output reg showCornerBorderCheck, + output wire [69:0] FLAT__yellowWinYOffset, + output wire [69:0] FLAT__yellowWinXOffset, + output wire [69:0] FLAT__redWinYOffset, + output wire [69:0] FLAT__redWinXOffset, + output reg [6:0] showRedWinIndicator, + output reg [6:0] showYellowWinIndicator, output reg game_over ); @@ -53,6 +58,11 @@ reg [9:0] redPieceXOffset [20:0]; reg [9:0] yellowPieceYOffset [20:0]; reg [9:0] yellowPieceXOffset [20:0]; +reg [9:0] yellowWinYOffset [6:0]; +reg [9:0] yellowWinXOffset [6:0]; +reg [9:0] redWinYOffset [6:0]; +reg [9:0] redWinXOffset [6:0]; + reg [1:0] board [41:0]; // Board cells (42) reg [4:0] currRed; reg [4:0] currYellow; @@ -64,13 +74,27 @@ reg loop_done; reg update; reg current_player; +reg [4:0] redPieceYVelocity [20:0]; +reg [20:0] redPieceYVelocitySign; +reg [4:0] yellowPieceYVelocity [20:0]; +reg [20:0] yellowPieceYVelocitySign; + +// msb = 1 means yellow, msb = 0 means red +reg [2:0] redIndexToRow [20:0]; +reg [2:0] redIndexToCol [20:0]; +reg [2:0] yellowIndexToRow [20:0]; +reg [2:0] yellowIndexToCol [20:0]; + + assign FLAT__redPieceYOffset = {redPieceYOffset[20],redPieceYOffset[19],redPieceYOffset[18],redPieceYOffset[17],redPieceYOffset[16],redPieceYOffset[15],redPieceYOffset[14],redPieceYOffset[13],redPieceYOffset[12],redPieceYOffset[11],redPieceYOffset[10],redPieceYOffset[9],redPieceYOffset[8],redPieceYOffset[7],redPieceYOffset[6],redPieceYOffset[5],redPieceYOffset[4],redPieceYOffset[3],redPieceYOffset[2],redPieceYOffset[1],redPieceYOffset[0]}; assign FLAT__redPieceXOffset = {redPieceXOffset[20],redPieceXOffset[19],redPieceXOffset[18],redPieceXOffset[17],redPieceXOffset[16],redPieceXOffset[15],redPieceXOffset[14],redPieceXOffset[13],redPieceXOffset[12],redPieceXOffset[11],redPieceXOffset[10],redPieceXOffset[9],redPieceXOffset[8],redPieceXOffset[7],redPieceXOffset[6],redPieceXOffset[5],redPieceXOffset[4],redPieceXOffset[3],redPieceXOffset[2],redPieceXOffset[1],redPieceXOffset[0]}; assign FLAT__yellowPieceYOffset = {yellowPieceYOffset[20],yellowPieceYOffset[19],yellowPieceYOffset[18],yellowPieceYOffset[17],yellowPieceYOffset[16],yellowPieceYOffset[15],yellowPieceYOffset[14],yellowPieceYOffset[13],yellowPieceYOffset[12],yellowPieceYOffset[11],yellowPieceYOffset[10],yellowPieceYOffset[9],yellowPieceYOffset[8],yellowPieceYOffset[7],yellowPieceYOffset[6],yellowPieceYOffset[5],yellowPieceYOffset[4],yellowPieceYOffset[3],yellowPieceYOffset[2],yellowPieceYOffset[1],yellowPieceYOffset[0]}; assign FLAT__yellowPieceXOffset = {yellowPieceXOffset[20],yellowPieceXOffset[19],yellowPieceXOffset[18],yellowPieceXOffset[17],yellowPieceXOffset[16],yellowPieceXOffset[15],yellowPieceXOffset[14],yellowPieceXOffset[13],yellowPieceXOffset[12],yellowPieceXOffset[11],yellowPieceXOffset[10],yellowPieceXOffset[9],yellowPieceXOffset[8],yellowPieceXOffset[7],yellowPieceXOffset[6],yellowPieceXOffset[5],yellowPieceXOffset[4],yellowPieceXOffset[3],yellowPieceXOffset[2],yellowPieceXOffset[1],yellowPieceXOffset[0]}; - - +assign FLAT__yellowWinYOffset = {yellowWinYOffset[6],yellowWinYOffset[5],yellowWinYOffset[4],yellowWinYOffset[3],yellowWinYOffset[2],yellowWinYOffset[1],yellowWinYOffset[0]}; +assign FLAT__yellowWinXOffset = {yellowWinXOffset[6],yellowWinXOffset[5],yellowWinXOffset[4],yellowWinXOffset[3],yellowWinXOffset[2],yellowWinXOffset[1],yellowWinXOffset[0]}; +assign FLAT__redWinYOffset = {redWinYOffset[6],redWinYOffset[5],redWinYOffset[4],redWinYOffset[3],redWinYOffset[2],redWinYOffset[1],redWinYOffset[0]}; +assign FLAT__redWinXOffset = {redWinXOffset[6],redWinXOffset[5],redWinXOffset[4],redWinXOffset[3],redWinXOffset[2],redWinXOffset[1],redWinXOffset[0]}; localparam INI = 6'b000001, @@ -82,10 +106,30 @@ YELLOW_WIN = 6'b100000, animateLeft = 6'b100001, animateRight = 6'b100010, animateBoard = 6'b100100, -animatePiece = 6'b101000; +animatePiece = 6'b101000, +animateReset = 6'b110000; integer i; integer j; + + + +integer pieceAnimationTimer; +integer winIndicatorAnimationTimer; +integer animateResetTimer; + +localparam +pieceAnimateOffset0 = 10'd1, +pieceAnimateOffset1 = 10'd2, +pieceAnimateOffset2 = 10'd3, +pieceAnimateOffset3 = 10'd3, +pieceAnimateOffset4 = 10'd3, +pieceAnimateOffset5 = 10'd3, +pieceAnimateOffset6 = 10'd2, +pieceAnimateOffset7 = 10'd1; + + + always @(posedge clk, posedge reset) begin //initialization @@ -98,16 +142,31 @@ always @(posedge clk, posedge reset) redPieceXOffset[j] = 20; yellowPieceYOffset[j] = 0; yellowPieceXOffset[j] = 20; + redPieceYVelocity[j] = 0; + yellowPieceYVelocity[j] = 0; + redIndexToRow[j] = 3'b111; + redIndexToCol[j] = 3'b111; + yellowIndexToRow[j] = 3'b111; + yellowIndexToCol[j] = 3'b111; + end + redPieceYVelocitySign = 0; + yellowPieceYVelocitySign = 0; + for(j = 0; j < 7; j = j+1) begin + yellowWinYOffset[j] = 0; + yellowWinXOffset[j] = 0; + redWinYOffset[j] = 0; + redWinXOffset[j] = 0; + showRedWinIndicator = 0; + showYellowWinIndicator = 0; end - showCornerBorderCheck <= 1; - redIndicatorXOffset = 22; - yellowIndicatorXOffset = 22; + redIndicatorXOffset = 76; + yellowIndicatorXOffset = 76; currRed = 0; currYellow = 0; state <= INI; game_over = 0; row = 5; - column = 0; + column = 3; current_player = 0; //start w RED boardYOffset = 29; loop_done = 0; @@ -122,6 +181,11 @@ always @(posedge clk, posedge reset) showTieGame <=0 ; showRedsTurn <=0; showYellowsTurn <=0; + pieceAnimationTimer <= 0; + showRedWinIndicator <= 0; + showYellowWinIndicator <= 0; + winIndicatorAnimationTimer <= 0; + animateResetTimer <= 0; end else begin @@ -134,37 +198,88 @@ always @(posedge clk, posedge reset) redPieceXOffset[j] = 20; yellowPieceYOffset[j] = 0; yellowPieceXOffset[j] = 20; + redPieceYVelocity[j] = 0; + yellowPieceYVelocity[j] = 0; + redIndexToRow[j] = 3'b111; + redIndexToCol[j] = 3'b111; + yellowIndexToRow[j] = 3'b111; + yellowIndexToCol[j] = 3'b111; + end + redPieceYVelocitySign = 0; + yellowPieceYVelocitySign = 0; + for(j = 0; j < 7; j = j+1) begin + yellowWinYOffset[j] = 0; + yellowWinXOffset[j] = 0; + redWinYOffset[j] = 0; + redWinXOffset[j] = 0; + showRedWinIndicator = 0; + showYellowWinIndicator = 0; end currRed = 0; currYellow = 0; - redIndicatorXOffset = 22; - yellowIndicatorXOffset = 22; - showCornerBorderCheck <= 1; + redIndicatorXOffset = 76; + yellowIndicatorXOffset = 76; showLogo <= 1; showRedIndicator <= 0; showYellowIndicator <= 0; showRedWins <= 0; showYellowWins <=0; + current_player = 0; //start w RED + row = 5; + column = 3; showTieGame <=0 ; boardYOffset = 29; showRedsTurn <=0; showYellowsTurn <=0; + for (i = 0; i < 42; i = i + 1) begin + board[i] <= 0; // Reset board to empty + end if (btn_up) begin showRedIndicator <= 0; state <= animateBoard; //state <= RED_TURN; // Start the game with red end + winIndicatorAnimationTimer <= 0; end RED_TURN: begin // $display("red turn"); - showRedIndicator <= 1; showRedsTurn <= 1; showYellowsTurn <=0; - yellowIndicatorXOffset = 22; + yellowIndicatorXOffset = 76; showYellowIndicator <= 0; - if (btn_left) //move left + if(!update) begin + showRedIndicator <= 1; + end + + if (update) + begin + //check for win/ tie + if (check_win(row, column, current_player+1)) + begin + game_over =1; + state <= RED_WIN; + showYellowIndicator <=0; + showRedIndicator <=0; + end + else if (is_board_full(0)) + begin + state <= TIE; + showYellowIndicator <= 0; + showRedIndicator <= 0; + end + else + begin + column = 3; + state <= YELLOW_TURN; + current_player <= 1; + showYellowIndicator <=1; + showRedIndicator <=0; + end + update <=0; + end + else if (btn_left) //move left begin column <= (column == 0) ? 0 : column - 1; state <= animateLeft; @@ -185,6 +300,8 @@ always @(posedge clk, posedge reset) begin // $display("red r:%d, c:%d", row, column); board[r * 7 + column] = current_player+1; + redIndexToRow[currRed] = r; + redIndexToCol[currRed] = column; row = r; // $display("red piece board r:%d, c:%d, player:%d, val:%d", row, column, current_player, board[r * 7 + column]); loop_done = 1; @@ -196,48 +313,53 @@ always @(posedge clk, posedge reset) else begin loop_done = 0; - redPieceYOffset[currRed] <= 37; + redPieceYOffset[currRed] <= 0; redPieceXOffset[currRed] = 20+18*column; state <= animatePiece; end end - else if (update) - begin + + end + YELLOW_TURN: + begin + // $display ("yellow turn"); + showRedIndicator <= 0; + showRedsTurn <=0; + showYellowsTurn <= 1; + redIndicatorXOffset = 76; + if(!update) begin + showYellowIndicator <= 1; + end + + if (update) + begin + // row <= 5; //check for win/ tie if (check_win(row, column, current_player+1)) begin - game_over =1; - state <= RED_WIN; showYellowIndicator <=0; showRedIndicator <=0; + game_over =1; + state <= YELLOW_WIN; end else if (is_board_full(0)) begin + showYellowIndicator <=0; + showRedIndicator <=0; state <= TIE; - showYellowIndicator <= 0; - showRedIndicator <= 0; end else - begin - column = 0; - state <= YELLOW_TURN; - current_player <= 1; - showYellowIndicator <=1; - showRedIndicator <=0; + begin + column = 3; + state <= RED_TURN; + showYellowIndicator <=0; + showRedIndicator <=1; + current_player <= 0; end update <=0; end - end - YELLOW_TURN: - begin - // $display ("yellow turn"); - showRedIndicator <= 0; - showRedsTurn <=0; - showYellowsTurn <= 1; - redIndicatorXOffset = 22; - showYellowIndicator <= 1; - if (btn_left) //move left + else if (btn_left) //move left begin column <= (column == 0) ? 0 : column - 1; state <= animateLeft; @@ -257,6 +379,8 @@ always @(posedge clk, posedge reset) // $display("yellow r:%d, c:%d", row, column); if (board[r * 7 + column] == 0) begin board[r * 7 + column] = current_player+1; + yellowIndexToRow[currYellow] = r; + yellowIndexToCol[currYellow] = column; row = r; // $display("yellow piece board r:%d, c:%d, player:%d, val:%d", row, column, current_player, board[r * 7 + column]); loop_done = 1; @@ -267,39 +391,13 @@ always @(posedge clk, posedge reset) // $display("red piece row: %d", row); else begin - yellowPieceYOffset[currYellow] <= 37; + yellowPieceYOffset[currYellow] <= 0; yellowPieceXOffset[currYellow] = 20+18*column; state <= animatePiece; loop_done = 0; end end - else if (update) - begin - // row <= 5; - //check for win/ tie - if (check_win(row, column, current_player+1)) - begin - showYellowIndicator <=0; - showRedIndicator <=0; - game_over =1; - state <= YELLOW_WIN; - end - else if (is_board_full(0)) - begin - showYellowIndicator <=0; - showRedIndicator <=0; - state <= TIE; - end - else - begin - column = 0; - state <= RED_TURN; - showYellowIndicator <=0; - showRedIndicator <=1; - current_player <= 0; - end - update <=0; - end + end RED_WIN: begin @@ -309,10 +407,39 @@ always @(posedge clk, posedge reset) showYellowIndicator <= 0; showRedWins <= 1; game_over <= 1; - if (reset) + showRedWinIndicator = 0; + + winIndicatorAnimationTimer <= winIndicatorAnimationTimer+1; + if(winIndicatorAnimationTimer == 59) begin + winIndicatorAnimationTimer <= 0; + end + + begin: checkWinsRed + integer x; + integer y; + integer a; + a = 0; + for(x = 0; x < 7; x = x+1) begin + for(y = 0; y < 6; y = y+1) begin + if(check_win(y, x, 1) && board[y*7+x] == 1) begin + redWinXOffset[a] = 19+18*x; + redWinYOffset[a] = 24+15*y; + showRedWinIndicator[a] = 1; + a = a+1; + end + end + end + end + + if(winIndicatorAnimationTimer >= 30) begin + showRedWinIndicator = 0; + end + + if (btn_up) begin - state <= INI; + state <= animateReset; game_over <= 0; + showRedWinIndicator <= 0; end end YELLOW_WIN: @@ -323,10 +450,39 @@ always @(posedge clk, posedge reset) showRedIndicator <= 0; showYellowIndicator <= 0; game_over <= 1; - if (reset) + showYellowWinIndicator = 0; + + winIndicatorAnimationTimer <= winIndicatorAnimationTimer+1; + if(winIndicatorAnimationTimer == 59) begin + winIndicatorAnimationTimer <= 0; + end + + begin: checkWinsYellow + integer x; + integer y; + integer a; + a = 0; + for(x = 0; x < 7; x = x+1) begin + for(y = 0; y < 6; y = y+1) begin + if(check_win(y, x, 2) && board[y*7+x] == 2) begin + yellowWinXOffset[a] = 19+18*x; + yellowWinYOffset[a] = 24+15*y; + showYellowWinIndicator[a] = 1; + a = a+1; + end + end + end + end + + if(winIndicatorAnimationTimer >= 30) begin + showYellowWinIndicator = 0; + end + + if (btn_up) begin - state <= INI; + state <= animateReset; game_over <= 0; + showYellowWinIndicator <= 0; end end TIE: @@ -337,9 +493,9 @@ always @(posedge clk, posedge reset) showRedIndicator <= 0; showYellowIndicator <= 0; game_over <= 1; - if (reset) + if (btn_up) begin - state <= INI; + state <= animateReset; game_over <= 0; end end @@ -348,17 +504,67 @@ always @(posedge clk, posedge reset) // $display ("animate left"); if (current_player == 0) begin - if (redIndicatorXOffset > column * 18 + 22) - redIndicatorXOffset= redIndicatorXOffset-1; - else + if (pieceAnimationTimer < 8 && redIndicatorXOffset > column * 18 + 22) begin + case(pieceAnimationTimer) + 0: + redIndicatorXOffset = redIndicatorXOffset - pieceAnimateOffset0; + 1: + redIndicatorXOffset = redIndicatorXOffset - pieceAnimateOffset1; + 2: + redIndicatorXOffset = redIndicatorXOffset - pieceAnimateOffset2; + 3: + redIndicatorXOffset = redIndicatorXOffset - pieceAnimateOffset3; + 4: + redIndicatorXOffset = redIndicatorXOffset - pieceAnimateOffset4; + 5: + redIndicatorXOffset = redIndicatorXOffset - pieceAnimateOffset5; + 6: + redIndicatorXOffset = redIndicatorXOffset - pieceAnimateOffset6; + 7: + redIndicatorXOffset = redIndicatorXOffset - pieceAnimateOffset7; + endcase + pieceAnimationTimer = pieceAnimationTimer+1; + end + else begin + pieceAnimationTimer = 0; state <= RED_TURN; + end +// if (redIndicatorXOffset > column * 18 + 22) +// redIndicatorXOffset= redIndicatorXOffset-1; +// else +// state <= RED_TURN; end else begin - if (yellowIndicatorXOffset > column * 18 + 22) - yellowIndicatorXOffset=yellowIndicatorXOffset-1; - else + if (pieceAnimationTimer < 8 && yellowIndicatorXOffset > column * 18 + 22) begin + case(pieceAnimationTimer) + 0: + yellowIndicatorXOffset = yellowIndicatorXOffset - pieceAnimateOffset0; + 1: + yellowIndicatorXOffset = yellowIndicatorXOffset - pieceAnimateOffset1; + 2: + yellowIndicatorXOffset = yellowIndicatorXOffset - pieceAnimateOffset2; + 3: + yellowIndicatorXOffset = yellowIndicatorXOffset - pieceAnimateOffset3; + 4: + yellowIndicatorXOffset = yellowIndicatorXOffset - pieceAnimateOffset4; + 5: + yellowIndicatorXOffset = yellowIndicatorXOffset - pieceAnimateOffset5; + 6: + yellowIndicatorXOffset = yellowIndicatorXOffset - pieceAnimateOffset6; + 7: + yellowIndicatorXOffset = yellowIndicatorXOffset - pieceAnimateOffset7; + endcase + pieceAnimationTimer = pieceAnimationTimer+1; + end + else begin + pieceAnimationTimer = 0; state <= YELLOW_TURN; + end +// if (yellowIndicatorXOffset > column * 18 + 22) +// yellowIndicatorXOffset=yellowIndicatorXOffset-1; +// else +// state <= YELLOW_TURN; end end animateRight: @@ -366,17 +572,68 @@ always @(posedge clk, posedge reset) // $display ("animate right"); if (current_player == 0) begin - if (redIndicatorXOffset < column * 18 + 22) - redIndicatorXOffset = redIndicatorXOffset+1; - else - state <= RED_TURN; + if (pieceAnimationTimer < 8 && redIndicatorXOffset < column * 18 + 22) begin + case(pieceAnimationTimer) + 0: + redIndicatorXOffset = redIndicatorXOffset + pieceAnimateOffset0; + 1: + redIndicatorXOffset = redIndicatorXOffset + pieceAnimateOffset1; + 2: + redIndicatorXOffset = redIndicatorXOffset + pieceAnimateOffset2; + 3: + redIndicatorXOffset = redIndicatorXOffset + pieceAnimateOffset3; + 4: + redIndicatorXOffset = redIndicatorXOffset + pieceAnimateOffset4; + 5: + redIndicatorXOffset = redIndicatorXOffset + pieceAnimateOffset5; + 6: + redIndicatorXOffset = redIndicatorXOffset + pieceAnimateOffset6; + 7: + redIndicatorXOffset = redIndicatorXOffset + pieceAnimateOffset7; + endcase + pieceAnimationTimer = pieceAnimationTimer+1; + end + else begin + pieceAnimationTimer = 0; + state <= RED_TURN; + end +// if (redIndicatorXOffset < column * 18 + 22) +// redIndicatorXOffset = redIndicatorXOffset+1; +// else +// state <= RED_TURN; end else begin - if (yellowIndicatorXOffset < column * 18 + 22) - yellowIndicatorXOffset = yellowIndicatorXOffset+1; - else + if (pieceAnimationTimer < 8 && yellowIndicatorXOffset < column * 18 + 22) begin + case(pieceAnimationTimer) + 0: + yellowIndicatorXOffset = yellowIndicatorXOffset + pieceAnimateOffset0; + 1: + yellowIndicatorXOffset = yellowIndicatorXOffset + pieceAnimateOffset1; + 2: + yellowIndicatorXOffset = yellowIndicatorXOffset + pieceAnimateOffset2; + 3: + yellowIndicatorXOffset = yellowIndicatorXOffset + pieceAnimateOffset3; + 4: + yellowIndicatorXOffset = yellowIndicatorXOffset + pieceAnimateOffset4; + 5: + yellowIndicatorXOffset = yellowIndicatorXOffset + pieceAnimateOffset5; + 6: + yellowIndicatorXOffset = yellowIndicatorXOffset + pieceAnimateOffset6; + 7: + yellowIndicatorXOffset = yellowIndicatorXOffset + pieceAnimateOffset7; + endcase + pieceAnimationTimer = pieceAnimationTimer+1; + end + else begin + pieceAnimationTimer = 0; state <= YELLOW_TURN; + end + +// if (yellowIndicatorXOffset < column * 18 + 22) +// yellowIndicatorXOffset = yellowIndicatorXOffset+1; +// else +// state <= YELLOW_TURN; end end animateBoard: @@ -393,11 +650,46 @@ always @(posedge clk, posedge reset) // $display ("animate piece"); if (current_player == 0) begin + showRedIndicator = 0; redPieceXOffset[currRed] = 20+18*column; - if (redPieceYOffset[currRed] < 37 + row * 15) - redPieceYOffset[currRed]=redPieceYOffset[currRed] +1; - else - begin +// if (redPieceYOffset[currRed] < 37 + row * 15) +// redPieceYOffset[currRed]=redPieceYOffset[currRed]+1; +//// else +// redPieceXOffset[currRed] = 20+18*column; + + if (redPieceYOffset[currRed] < (37 + row * 15) || redPieceYVelocity[currRed] > 0) begin + + if(redPieceYVelocity[currRed] < 10 || redPieceYVelocitySign[currRed] == 1) begin + if(redPieceYVelocitySign[currRed] == 1) begin + redPieceYVelocity[currRed] = redPieceYVelocity[currRed]-1; + end + else begin + redPieceYVelocity[currRed] = redPieceYVelocity[currRed]+1; + end + if(redPieceYVelocitySign[currRed] == 1 && redPieceYVelocity[currRed] == 0) begin + redPieceYVelocitySign[currRed] = 0; + end + end + + if(redPieceYVelocitySign[currRed] == 0) begin + redPieceYOffset[currRed]=redPieceYOffset[currRed] + (redPieceYVelocity[currRed] >> 1); + end + else begin + redPieceYOffset[currRed]=redPieceYOffset[currRed] - (redPieceYVelocity[currRed] >> 1); + end + + if(redPieceYOffset[currRed] >= (37 + row * 15) && redPieceYVelocity[currRed] > 0) begin + redPieceYOffset[currRed] = 37 + row * 15; + redPieceYVelocitySign[currRed] = 1; + if(redPieceYVelocity[currRed] < 2) begin + redPieceYVelocity[currRed] = 0; + end + else begin + redPieceYVelocity[currRed] = redPieceYVelocity[currRed] - 2; + end + end + end + else begin update =1; state <= RED_TURN; @@ -405,28 +697,133 @@ always @(posedge clk, posedge reset) //reset all offsets // redPieceXOffset[currRed] = 22; // redPieceYOffset[currRed] = 37; + redPieceYVelocity[currRed] = 0; + redPieceYVelocitySign[currRed] = 0; currRed = currRed +1; - redIndicatorXOffset = 22; - yellowIndicatorXOffset = 22; + redIndicatorXOffset = 76; + yellowIndicatorXOffset = 76; end end else begin + showYellowIndicator = 0; yellowPieceXOffset[currYellow] = 20+18*column; - if (yellowPieceYOffset[currYellow] < 37 + row * 15) - yellowPieceYOffset[currYellow]=yellowPieceYOffset[currYellow]+1; - else - begin +// if (redPieceYOffset[currRed] < 37 + row * 15) +// redPieceYOffset[currRed]=redPieceYOffset[currRed]+1; +//// else +// redPieceXOffset[currRed] = 20+18*column; + + if (yellowPieceYOffset[currYellow] < (37 + row * 15) || yellowPieceYVelocity[currYellow] > 0) begin + + if(yellowPieceYVelocity[currYellow] < 10 || yellowPieceYVelocitySign[currYellow] == 1) begin + if(yellowPieceYVelocitySign[currYellow] == 1) begin + yellowPieceYVelocity[currYellow] = yellowPieceYVelocity[currYellow]-1; + end + else begin + yellowPieceYVelocity[currYellow] = yellowPieceYVelocity[currYellow]+1; + end + if(yellowPieceYVelocitySign[currYellow] == 1 && yellowPieceYVelocity[currYellow] == 0) begin + yellowPieceYVelocitySign[currYellow] = 0; + end + end + + if(yellowPieceYVelocitySign[currYellow] == 0) begin + yellowPieceYOffset[currYellow]=yellowPieceYOffset[currYellow] + (yellowPieceYVelocity[currYellow] >> 1); + end + else begin + yellowPieceYOffset[currYellow]=yellowPieceYOffset[currYellow] - (yellowPieceYVelocity[currYellow] >> 1); + end + + if(yellowPieceYOffset[currYellow] >= (37 + row * 15) && yellowPieceYVelocity[currYellow] > 0) begin + yellowPieceYOffset[currYellow] = 37 + row * 15; + yellowPieceYVelocitySign[currYellow] = 1; + if(yellowPieceYVelocity[currYellow] < 2) begin + yellowPieceYVelocity[currYellow] = 0; + end + else begin + yellowPieceYVelocity[currYellow] = yellowPieceYVelocity[currYellow] - 2; + end + end + end + else begin currYellow = currYellow + 1; update =1; + yellowPieceYVelocity[currYellow] = 0; + yellowPieceYVelocitySign[currYellow] = 0; state <= YELLOW_TURN; // column = 0; //reset all offsets - redIndicatorXOffset = 22; - yellowIndicatorXOffset = 22; + redIndicatorXOffset = 76; + yellowIndicatorXOffset = 76; + end + end + end + + animateReset: begin + animateResetTimer <= animateResetTimer+1; + showRedWins <= 0; + showYellowWins <= 0; + showTieGame <= 0; + + begin: animateResetPieces + integer i; + integer r; + integer c; + + for(i = 0; i < 21; i = i+1) begin + r = redIndexToRow[i]; + c = redIndexToCol[i]; + if(animateResetTimer >= 5*(5-r)+15*c && r != 3'b111 && c != 3'b111) begin + if(redPieceYOffset[i] < 520) begin + if(redPieceYVelocity[i] < 10) begin + redPieceYVelocity[i] = redPieceYVelocity[i]+1; + end + + redPieceYOffset[i]=redPieceYOffset[i] + (redPieceYVelocity[i] >> 1); + end + end + end + + for(i = 0; i < 21; i = i+1) begin + r = yellowIndexToRow[i]; + c = yellowIndexToCol[i]; + if(animateResetTimer >= 5*(5-r)+15*c && r != 3'b111 && c != 3'b111) begin + if(yellowPieceYOffset[i] < 520) begin + if(yellowPieceYVelocity[i] < 10) begin + yellowPieceYVelocity[i] = yellowPieceYVelocity[i]+1; + end + + yellowPieceYOffset[i]=yellowPieceYOffset[i] + (yellowPieceYVelocity[i] >> 1); + end end end + + + if(animateResetTimer >= 220 && boardYOffset < 29) begin + boardYOffset = boardYOffset+1; + end + end + + if(animateResetTimer >= 270) begin: animateResetReset + integer i; + for(i = 0; i < 21; i = i+1) begin + yellowPieceYVelocity[i] = 0; + yellowPieceYVelocitySign[i] = 0; + yellowIndexToRow[i] = 3'b111; + yellowIndexToCol[i] = 3'b111; + end + for(i = 0; i < 21; i = i+1) begin + redPieceYVelocity[i] = 0; + redPieceYVelocitySign[i] = 0; + redIndexToRow[i] = 3'b111; + redIndexToCol[i] = 3'b111; + end + + animateResetTimer <= 0; + + state <= INI; end + end endcase end end @@ -515,7 +912,6 @@ endmodule // output wire [209:0] FLAT__redPieceXOffset, // output wire [209:0] FLAT__yellowPieceYOffset, // output wire [209:0] FLAT__yellowPieceXOffset, -// output reg showCornerBorderCheck // ); // reg [9:0] redPieceYOffset [20:0]; // reg [9:0] redPieceXOffset [20:0]; @@ -531,7 +927,6 @@ endmodule // integer i; // always @(posedge clk) begin -// showCornerBorderCheck <= 1; // for(i = 0; i < 21; i = i+1) begin // redPieceXOffset[i] <= 20 + (i%7)*18; // redPieceYOffset[i] <= 37 + (i%6)*15; diff --git a/vga.srcs/sources_1/new/vga.v b/vga.srcs/sources_1/new/vga.v index 567ead1..c9d54f9 100644 --- a/vga.srcs/sources_1/new/vga.v +++ b/vga.srcs/sources_1/new/vga.v @@ -20,14 +20,14 @@ ////////////////////////////////////////////////////////////////////////////////// -module vga(sysClk, hSync, vSync, vgaRed, vgaGrn, vgaBlu, BtnL, BtnU, BtnD, BtnR, BtnC); +module vga(sysClk, hSync, vSync, vgaRed, vgaGrn, vgaBlu, BtnL, BtnU, BtnD, BtnR, BtnC, switch15Debug, btnCPUReset); input wire sysClk; output reg hSync; output reg vSync; output reg[3:0] vgaRed; output reg[3:0] vgaGrn; output reg[3:0] vgaBlu; - input BtnL, BtnU, BtnD, BtnR, BtnC; + input BtnL, BtnU, BtnD, BtnR, BtnC, switch15Debug, btnCPUReset; // create 25 MHz pixel clock for 480x600 video output reg pixClk; @@ -182,7 +182,7 @@ module vga(sysClk, hSync, vSync, vgaRed, vgaGrn, vgaBlu, BtnL, BtnU, BtnD, BtnR, //assign btn_left = BtnL; //assign btn_right = BtnR; //assign btn_up = BtnU; - assign reset = BtnC; + assign reset = ~btnCPUReset; // cpu reset is high at rest, low when pressed wire showLogo; wire [9:0] boardYOffset; wire showRedsTurn; @@ -200,7 +200,12 @@ module vga(sysClk, hSync, vSync, vgaRed, vgaGrn, vgaBlu, BtnL, BtnU, BtnD, BtnR, wire [9:0] yellowPieceYOffset [20:0]; wire [9:0] yellowPieceXOffset [20:0]; wire game_over; - wire showCornerBorderCheck; + wire [9:0] yellowWinYOffset [6:0]; + wire [9:0] yellowWinXOffset [6:0]; + wire [9:0] redWinYOffset [6:0]; + wire [9:0] redWinXOffset [6:0]; + wire [6:0] showRedWinIndicator; + wire [6:0] showYellowWinIndicator; // packing so we can actually pass 2d arrays to and from modules :/ @@ -217,14 +222,25 @@ module vga(sysClk, hSync, vSync, vgaRed, vgaGrn, vgaBlu, BtnL, BtnU, BtnD, BtnR, wire [209:0] FLAT__yellowPieceXOffset; assign {yellowPieceXOffset[20],yellowPieceXOffset[19],yellowPieceXOffset[18],yellowPieceXOffset[17],yellowPieceXOffset[16],yellowPieceXOffset[15],yellowPieceXOffset[14],yellowPieceXOffset[13],yellowPieceXOffset[12],yellowPieceXOffset[11],yellowPieceXOffset[10],yellowPieceXOffset[9],yellowPieceXOffset[8],yellowPieceXOffset[7],yellowPieceXOffset[6],yellowPieceXOffset[5],yellowPieceXOffset[4],yellowPieceXOffset[3],yellowPieceXOffset[2],yellowPieceXOffset[1],yellowPieceXOffset[0]} = FLAT__yellowPieceXOffset; + wire [69:0] FLAT__yellowWinYOffset; + assign {yellowWinYOffset[6],yellowWinYOffset[5],yellowWinYOffset[4],yellowWinYOffset[3],yellowWinYOffset[2],yellowWinYOffset[1],yellowWinYOffset[0]} = FLAT__yellowWinYOffset; + + wire [69:0] FLAT__yellowWinXOffset; + assign {yellowWinXOffset[6],yellowWinXOffset[5],yellowWinXOffset[4],yellowWinXOffset[3],yellowWinXOffset[2],yellowWinXOffset[1],yellowWinXOffset[0]} = FLAT__yellowWinXOffset; + + wire [69:0] FLAT__redWinYOffset; + assign {redWinYOffset[6],redWinYOffset[5],redWinYOffset[4],redWinYOffset[3],redWinYOffset[2],redWinYOffset[1],redWinYOffset[0]} = FLAT__redWinYOffset; + wire [69:0] FLAT__redWinXOffset; + assign {redWinXOffset[6],redWinXOffset[5],redWinXOffset[4],redWinXOffset[3],redWinXOffset[2],redWinXOffset[1],redWinXOffset[0]} = FLAT__redWinXOffset; + - TESTcore_design core_design( + connect4_core_design core_design( .clk(frameClk), .reset(reset), .btn_left(BtnL), .btn_right(BtnR), - .btn_up(BtnU), + .btn_up(BtnC), .showLogo(showLogo), .boardYOffset(boardYOffset), .showRedsTurn(showRedsTurn), @@ -241,7 +257,12 @@ module vga(sysClk, hSync, vSync, vgaRed, vgaGrn, vgaBlu, BtnL, BtnU, BtnD, BtnR, .FLAT__redPieceXOffset(FLAT__redPieceXOffset), .FLAT__yellowPieceYOffset(FLAT__yellowPieceYOffset), .FLAT__yellowPieceXOffset(FLAT__yellowPieceXOffset), - .showCornerBorderCheck(showCornerBorderCheck), + .FLAT__yellowWinYOffset(FLAT__yellowWinYOffset), + .FLAT__yellowWinXOffset(FLAT__yellowWinXOffset), + .FLAT__redWinYOffset(FLAT__redWinYOffset), + .FLAT__redWinXOffset(FLAT__redWinXOffset), + .showRedWinIndicator(showRedWinIndicator), + .showYellowWinIndicator(showYellowWinIndicator), .game_over(game_over) ); @@ -310,7 +331,28 @@ module vga(sysClk, hSync, vSync, vgaRed, vgaGrn, vgaBlu, BtnL, BtnU, BtnD, BtnR, endgenerate + genvar yellowWinI; + wire [3:0] yellowWinPI [6:0]; + wire yellowWinValid [6:0]; + generate + for(yellowWinI = 0; yellowWinI < 7; yellowWinI = yellowWinI+1) begin + yellow_win_highlight yellow_win_highlight_gfx(.clk(pixClk), .x((pixX >> 2) - yellowWinXOffset[yellowWinI]), .y((pixY >> 2) - yellowWinYOffset[yellowWinI]), .paletteIndex(yellowWinPI[yellowWinI]), .valid(yellowWinValid[yellowWinI])); + end + endgenerate + + + genvar redWinI; + wire [3:0] redWinPI [6:0]; + wire redWinValid [6:0]; + generate + for(redWinI = 0; redWinI < 7; redWinI = redWinI+1) begin + red_win_highlight red_win_highlight_gfx(.clk(pixClk), .x((pixX >> 2) - redWinXOffset[redWinI]), .y((pixY >> 2) - redWinYOffset[redWinI]), .paletteIndex(redWinPI[redWinI]), .valid(redWinValid[redWinI])); + end + endgenerate + + + reg [3:0] winIndicatorIndex; reg [3:0] frontIndex; reg [3:0] pieceIndex; reg [3:0] finalIndex; @@ -324,7 +366,20 @@ module vga(sysClk, hSync, vSync, vgaRed, vgaGrn, vgaBlu, BtnL, BtnU, BtnD, BtnR, else begin: pixel_block // front layer priority - if(cornerBorderCheckValid && showCornerBorderCheck) begin + winIndicatorIndex = 4'b1111; + for(pieceI = 0; pieceI < 7; pieceI = pieceI+1) begin + if(yellowWinValid[pieceI] && showYellowWinIndicator[pieceI]) begin + winIndicatorIndex = yellowWinPI[pieceI]; + end + end + for(pieceI = 0; pieceI < 7; pieceI = pieceI+1) begin + if(redWinValid[pieceI] && showRedWinIndicator[pieceI]) begin + winIndicatorIndex = redWinPI[pieceI]; + end + end + + // show debug outline only if switch15 is enabled + if(cornerBorderCheckValid && switch15Debug) begin frontIndex = cornerBorderCheckPI; end else if(logoValid && showLogo) begin @@ -370,7 +425,10 @@ module vga(sysClk, hSync, vSync, vgaRed, vgaGrn, vgaBlu, BtnL, BtnU, BtnD, BtnR, end end - if(frontIndex != 4'b1111) begin + if(winIndicatorIndex != 4'b1111) begin + finalIndex = winIndicatorIndex; + end + else if(frontIndex != 4'b1111) begin finalIndex = frontIndex; end else if(pieceIndex != 4'b1111) begin diff --git a/vga.srcs/utils_1/imports/synth_1/vga.dcp b/vga.srcs/utils_1/imports/synth_1/vga.dcp index 27506be..d3f2b97 100644 Binary files a/vga.srcs/utils_1/imports/synth_1/vga.dcp and b/vga.srcs/utils_1/imports/synth_1/vga.dcp differ diff --git a/vga.xpr b/vga.xpr index 7374475..e9a20ec 100644 --- a/vga.xpr +++ b/vga.xpr @@ -4,7 +4,7 @@ - +