Cleanup some doc and comments

doc/user_guide/_docs/A02-logical_signals.md

@@ -22,7 +22,7 @@ var bus = Logic(name: 'b', width: 8)
 
 You can access the current value of a signal using `value`.  You cannot access this as part of synthesizable ROHD code.  ROHD supports X and Z values and propogation.  If the signal is valid (no X or Z in it), you can also convert it to an `int` with `value.toInt()` (ROHD will throw an exception otherwise).  If the signal has more bits than a dart `int` (64 bits, usually), you need to use `value.toBigInt()` to get a `BigInt` (again, ROHD will throw an exception otherwise).
 
-The value of a `Logic` is of type [`LogicValue`](https://intel.github.io/rohd/rohd/LogicValue-class.html), with pre-defined constant bit values `x`, `z`, `one`, and `zero`.  `LogicValue` has a number of built-in logical operations (like &, |, ^, +, -, etc.).
+The value of a `Logic` is of type [`LogicValue`](https://intel.github.io/rohd/rohd/LogicValue-class.html), with pre-defined constant bit values `x`, `z`, `one`, and `zero`.  `LogicValue` has a number of built-in logical operations (like `&`, `|`, `^`, `+`, `-`, etc.).
 
 ```dart
 var x = Logic(width:2);

doc/user_guide/_docs/A20-logic-arrays.md

@@ -42,3 +42,7 @@ LogicArray(
 You can declare ports of `Module`s as being arrays (including with some dimensions "unpacked") using `addInputArray` and `addOutputArray`. Note that these do _not_ automatically do validation that the dimensions, element width, number of unpacked dimensions, etc. are equal between the port and the original signal. As long as the overall width matches, the assignment will be clean.
 
 Array ports in generated SystemVerilog will match dimensions (including unpacked) as specified when the port is created.
+
+## Elements of arrays
+
+To iterate through or access elements of a `LogicArray` (or bits of a simple `Logic`), use [`elements`](https://intel.github.io/rohd/rohd/Logic/elements.html).  Using the normal `[n]` accessors will return the `n`th bit regardless for `LogicArray` and `Logic` to maintain API consistency.

tool/generate_coverage.sh

@@ -1,14 +1,13 @@
 #!/bin/bash
 
-# Copyright (C) 2022 Intel Corporation
+# Copyright (C) 2022-2023 Intel Corporation
 # SPDX-License-Identifier: BSD-3-Clause
 #
 # generate_coverage.sh
 # Determines code coverage by tests and generates an HTML representation.
 #
 # 2022 May 5
 # Author: Max Korbel <[email protected]>
-#
 
 ### WARNING ###
 # The "x" option outputs all script commands. This allows you to track

tool/gh_actions/analyze_source.sh

@@ -8,7 +8,6 @@
 #
 # 2022 October 9
 # Author: Chykon
-#
 
 set -euo pipefail
 

tool/gh_actions/check_documentation.sh

@@ -8,7 +8,6 @@
 #
 # 2022 October 9
 # Author: Chykon
-#
 
 set -euo pipefail
 

tool/gh_actions/check_folder_tmp_test.sh

@@ -1,14 +1,13 @@
 #!/bin/bash
 
-# Copyright (C) 2022 Intel Corporation
+# Copyright (C) 2022-2023 Intel Corporation
 # SPDX-License-Identifier: BSD-3-Clause
 #
 # check_folder_tmp_test.sh
 # GitHub Actions step: Check folder - tmp_test.
 #
 # 2022 October 12
 # Author: Chykon
-#
 
 set -euo pipefail
 

tool/gh_actions/generate_documentation.sh

@@ -1,14 +1,13 @@
 #!/bin/bash
 
-# Copyright (C) 2022 Intel Corporation
+# Copyright (C) 2022-2023 Intel Corporation
 # SPDX-License-Identifier: BSD-3-Clause
 #
 # generate_documentation.sh
 # GitHub Actions step: Generate project documentation.
 #
 # 2022 October 10
 # Author: Chykon
-#
 
 set -euo pipefail
 

tool/gh_actions/install_dependencies.sh

@@ -1,14 +1,13 @@
 #!/bin/bash
 
-# Copyright (C) 2022 Intel Corporation
+# Copyright (C) 2022-2023 Intel Corporation
 # SPDX-License-Identifier: BSD-3-Clause
 #
 # install_dependencies.sh
 # GitHub Actions step: Install project dependencies.
 #
 # 2022 October 7
 # Author: Chykon
-#
 
 set -euo pipefail
 

tool/gh_actions/install_iverilog.sh

@@ -1,14 +1,13 @@
 #!/bin/bash
 
-# Copyright (C) 2022 Intel Corporation
+# Copyright (C) 2022-2023 Intel Corporation
 # SPDX-License-Identifier: BSD-3-Clause
 #
 # install_iverilog.sh
 # GitHub Actions step: Install software - Icarus Verilog.
 #
 # 2022 October 9
 # Author: Chykon
-#
 
 set -euo pipefail
 

tool/gh_actions/run_tests.sh

@@ -1,14 +1,13 @@
 #!/bin/bash
 
-# Copyright (C) 2022 Intel Corporation
+# Copyright (C) 2022-2023 Intel Corporation
 # SPDX-License-Identifier: BSD-3-Clause
 #
 # run_tests.sh
 # GitHub Actions step: Run project tests.
 #
 # 2022 October 10
 # Author: Chykon
-#
 
 set -euo pipefail
 

tool/gh_actions/verify_formatting.sh

@@ -1,14 +1,13 @@
 #!/bin/bash
 
-# Copyright (C) 2022 Intel Corporation
+# Copyright (C) 2022-2023 Intel Corporation
 # SPDX-License-Identifier: BSD-3-Clause
 #
 # verify_formatting.sh
 # GitHub Actions step: Verify project formatting.
 #
 # 2022 October 9
 # Author: Chykon
-#
 
 set -euo pipefail
 

tool/gh_codespaces/install_dart.sh

@@ -8,7 +8,6 @@
 #
 # 2023 February 5
 # Author: Chykon
-#
 
 set -euo pipefail
 

tool/gh_codespaces/run_setup.sh

@@ -8,7 +8,6 @@
 #
 # 2023 February 5
 # Author: Chykon
-#
 
 set -euo pipefail
 

tool/run_checks.sh

@@ -1,14 +1,13 @@
 #!/bin/bash
 
-# Copyright (C) 2022 Intel Corporation
+# Copyright (C) 2022-2023 Intel Corporation
 # SPDX-License-Identifier: BSD-3-Clause
 #
 # run_checks.sh
 # Run project checks.
 #
 # 2022 October 11
 # Author: Chykon
-#
 
 set -euo pipefail