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@@ -42,3 +42,5 @@ LogicArray( | |
You can declare ports of `Module`s as being arrays (including with some dimensions "unpacked") using `addInputArray` and `addOutputArray`. Note that these do _not_ automatically do validation that the dimensions, element width, number of unpacked dimensions, etc. are equal between the port and the original signal. As long as the overall width matches, the assignment will be clean. | ||
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Array ports in generated SystemVerilog will match dimensions (including unpacked) as specified when the port is created. | ||
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#TODO: Add .elements in here | ||
Check failure on line 46 in doc/user_guide/_docs/A20-logic-arrays.md GitHub Actions / Run ChecksNo space after hash on atx style heading
Check failure on line 46 in doc/user_guide/_docs/A20-logic-arrays.md GitHub Actions / Run ChecksFiles should end with a single newline character
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#!/bin/bash | ||
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# Copyright (C) 2022 Intel Corporation | ||
# Copyright (C) 2022-2023 Intel Corporation | ||
# SPDX-License-Identifier: BSD-3-Clause | ||
# | ||
# generate_coverage.sh | ||
# Determines code coverage by tests and generates an HTML representation. | ||
# | ||
# 2022 May 5 | ||
# Author: Max Korbel <[email protected]> | ||
# | ||
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### WARNING ### | ||
# The "x" option outputs all script commands. This allows you to track | ||
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# | ||
# 2022 October 9 | ||
# Author: Chykon | ||
# | ||
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set -euo pipefail | ||
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# | ||
# 2022 October 9 | ||
# Author: Chykon | ||
# | ||
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set -euo pipefail | ||
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# | ||
# 2023 February 5 | ||
# Author: Chykon | ||
# | ||
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set -euo pipefail | ||
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Original file line number | Diff line number | Diff line change |
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@@ -8,7 +8,6 @@ | |
# | ||
# 2023 February 5 | ||
# Author: Chykon | ||
# | ||
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set -euo pipefail | ||
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