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Cleanup some doc and comments
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mkorbel1 committed Sep 19, 2023
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2 changes: 1 addition & 1 deletion doc/user_guide/_docs/A02-logical_signals.md
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Expand Up @@ -22,7 +22,7 @@ var bus = Logic(name: 'b', width: 8)

You can access the current value of a signal using `value`. You cannot access this as part of synthesizable ROHD code. ROHD supports X and Z values and propogation. If the signal is valid (no X or Z in it), you can also convert it to an `int` with `value.toInt()` (ROHD will throw an exception otherwise). If the signal has more bits than a dart `int` (64 bits, usually), you need to use `value.toBigInt()` to get a `BigInt` (again, ROHD will throw an exception otherwise).

The value of a `Logic` is of type [`LogicValue`](https://intel.github.io/rohd/rohd/LogicValue-class.html), with pre-defined constant bit values `x`, `z`, `one`, and `zero`. `LogicValue` has a number of built-in logical operations (like &, |, ^, +, -, etc.).
The value of a `Logic` is of type [`LogicValue`](https://intel.github.io/rohd/rohd/LogicValue-class.html), with pre-defined constant bit values `x`, `z`, `one`, and `zero`. `LogicValue` has a number of built-in logical operations (like `&`, `|`, `^`, `+`, `-`, etc.).

```dart
var x = Logic(width:2);
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2 changes: 2 additions & 0 deletions doc/user_guide/_docs/A20-logic-arrays.md
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You can declare ports of `Module`s as being arrays (including with some dimensions "unpacked") using `addInputArray` and `addOutputArray`. Note that these do _not_ automatically do validation that the dimensions, element width, number of unpacked dimensions, etc. are equal between the port and the original signal. As long as the overall width matches, the assignment will be clean.

Array ports in generated SystemVerilog will match dimensions (including unpacked) as specified when the port is created.

#TODO: Add .elements in here

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doc/user_guide/_docs/A20-logic-arrays.md:46:1 MD018/no-missing-space-atx No space after hash on atx style heading [Context: "#TODO: Add .elements in here"] https://github.com/DavidAnson/markdownlint/blob/v0.29.0/doc/md018.md

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doc/user_guide/_docs/A20-logic-arrays.md:46:28 MD047/single-trailing-newline Files should end with a single newline character https://github.com/DavidAnson/markdownlint/blob/v0.29.0/doc/md047.md
3 changes: 1 addition & 2 deletions tool/generate_coverage.sh
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#!/bin/bash

# Copyright (C) 2022 Intel Corporation
# Copyright (C) 2022-2023 Intel Corporation
# SPDX-License-Identifier: BSD-3-Clause
#
# generate_coverage.sh
# Determines code coverage by tests and generates an HTML representation.
#
# 2022 May 5
# Author: Max Korbel <[email protected]>
#

### WARNING ###
# The "x" option outputs all script commands. This allows you to track
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1 change: 0 additions & 1 deletion tool/gh_actions/analyze_source.sh
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#
# 2022 October 9
# Author: Chykon
#

set -euo pipefail

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1 change: 0 additions & 1 deletion tool/gh_actions/check_documentation.sh
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#
# 2022 October 9
# Author: Chykon
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set -euo pipefail

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3 changes: 1 addition & 2 deletions tool/gh_actions/check_folder_tmp_test.sh
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#!/bin/bash

# Copyright (C) 2022 Intel Corporation
# Copyright (C) 2022-2023 Intel Corporation
# SPDX-License-Identifier: BSD-3-Clause
#
# check_folder_tmp_test.sh
# GitHub Actions step: Check folder - tmp_test.
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# 2022 October 12
# Author: Chykon
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3 changes: 1 addition & 2 deletions tool/gh_actions/generate_documentation.sh
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#!/bin/bash

# Copyright (C) 2022 Intel Corporation
# Copyright (C) 2022-2023 Intel Corporation
# SPDX-License-Identifier: BSD-3-Clause
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# generate_documentation.sh
# GitHub Actions step: Generate project documentation.
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# 2022 October 10
# Author: Chykon
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set -euo pipefail

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3 changes: 1 addition & 2 deletions tool/gh_actions/install_dependencies.sh
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#!/bin/bash

# Copyright (C) 2022 Intel Corporation
# Copyright (C) 2022-2023 Intel Corporation
# SPDX-License-Identifier: BSD-3-Clause
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# install_dependencies.sh
# GitHub Actions step: Install project dependencies.
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# 2022 October 7
# Author: Chykon
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set -euo pipefail

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3 changes: 1 addition & 2 deletions tool/gh_actions/install_iverilog.sh
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#!/bin/bash

# Copyright (C) 2022 Intel Corporation
# Copyright (C) 2022-2023 Intel Corporation
# SPDX-License-Identifier: BSD-3-Clause
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# install_iverilog.sh
# GitHub Actions step: Install software - Icarus Verilog.
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# 2022 October 9
# Author: Chykon
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3 changes: 1 addition & 2 deletions tool/gh_actions/run_tests.sh
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#!/bin/bash

# Copyright (C) 2022 Intel Corporation
# Copyright (C) 2022-2023 Intel Corporation
# SPDX-License-Identifier: BSD-3-Clause
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# run_tests.sh
# GitHub Actions step: Run project tests.
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# 2022 October 10
# Author: Chykon
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3 changes: 1 addition & 2 deletions tool/gh_actions/verify_formatting.sh
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#!/bin/bash

# Copyright (C) 2022 Intel Corporation
# Copyright (C) 2022-2023 Intel Corporation
# SPDX-License-Identifier: BSD-3-Clause
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# verify_formatting.sh
# GitHub Actions step: Verify project formatting.
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# 2022 October 9
# Author: Chykon
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1 change: 0 additions & 1 deletion tool/gh_codespaces/install_dart.sh
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# 2023 February 5
# Author: Chykon
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1 change: 0 additions & 1 deletion tool/gh_codespaces/run_setup.sh
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# 2023 February 5
# Author: Chykon
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set -euo pipefail

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3 changes: 1 addition & 2 deletions tool/run_checks.sh
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#!/bin/bash

# Copyright (C) 2022 Intel Corporation
# Copyright (C) 2022-2023 Intel Corporation
# SPDX-License-Identifier: BSD-3-Clause
#
# run_checks.sh
# Run project checks.
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# 2022 October 11
# Author: Chykon
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set -euo pipefail

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