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compressor with flopped output
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desmonddak committed Oct 30, 2024
1 parent 8b266d0 commit 13d4de4
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Showing 4 changed files with 102 additions and 3 deletions.
15 changes: 13 additions & 2 deletions lib/src/arithmetic/addend_compressor.dart
Original file line number Diff line number Diff line change
Expand Up @@ -170,8 +170,17 @@ class ColumnCompressor {
/// The partial product array to be compressed
final PartialProductArray pp;

/// The clk
Logic? clk;

/// Optional reset
Logic? reset;

/// Optional enable
Logic? enable;

/// Initialize a ColumnCompressor for a set of partial products
ColumnCompressor(this.pp) {
ColumnCompressor(this.pp, {this.clk, this.reset, this.enable}) {
columns = List.generate(pp.maxWidth(), (i) => ColumnQueue());

for (var row = 0; row < pp.rows; row++) {
Expand All @@ -197,7 +206,9 @@ class ColumnCompressor {
final colList = columns[col].toList();
if (row < colList.length) {
final value = colList[row].logic;
rowBits.add(value);

rowBits.add(
clk != null ? flop(clk!, value, reset: reset, en: enable) : value);
}
}
rowBits.addAll(List.filled(pp.rowShift[row], Const(0)));
Expand Down
80 changes: 80 additions & 0 deletions test/arithmetic/addend_compressor_test.dart
Original file line number Diff line number Diff line change
Expand Up @@ -7,6 +7,7 @@
// 2024 June 04
// Author: Desmond Kirkpatrick <[email protected]>

import 'dart:async';
import 'dart:io';
import 'dart:math';
import 'package:rohd/rohd.dart';
Expand All @@ -16,6 +17,38 @@ import 'package:rohd_hcl/src/arithmetic/evaluate_partial_product.dart';
import 'package:rohd_hcl/src/arithmetic/partial_product_sign_extend.dart';
import 'package:test/test.dart';

/// A simple module to test partial product generation and compression
class CompressorTestMod extends Module {
late final PartialProductGenerator pp;

late final ColumnCompressor compressor;

Logic get r0 => output('r0');

Logic get r1 => output('r1');

CompressorTestMod(Logic ia, Logic ib, RadixEncoder encoder, Logic? iclk,
{bool signed = true})
: super(name: 'compressor_test_mod') {
final a = addInput('a', ia, width: ia.width);
final b = addInput('b', ib, width: ib.width);
Logic? clk;
if (iclk != null) {
clk = addInput('clk', iclk);
}

pp = PartialProductGeneratorCompactRectSignExtension(a, b, encoder,
signed: signed);
compressor = ColumnCompressor(pp, clk: clk);
compressor.compress();
final r0 = addOutput('r0', width: compressor.columns.length);
final r1 = addOutput('r1', width: compressor.columns.length);

r0 <= compressor.extractRow(0);
r1 <= compressor.extractRow(1);
}
}

void testCompressionExhaustive(PartialProductGenerator pp) {
final widthX = pp.selector.multiplicand.width;
final widthY = pp.encoder.multiplier.width;
Expand Down Expand Up @@ -76,6 +109,9 @@ void testCompressionExhaustive(PartialProductGenerator pp) {
}

void main() {
tearDown(() async {
await Simulator.reset();
});
test('exhaustive compression evaluate: square radix-4, just CompactRect',
() async {
stdout.write('\n');
Expand Down Expand Up @@ -163,6 +199,50 @@ void main() {
}
});

test('single compressor evaluate flopped', () async {
final clk = SimpleClockGenerator(10).clk;
const widthX = 6;
const widthY = 6;
final a = Logic(name: 'a', width: widthX);
final b = Logic(name: 'b', width: widthY);

var av = 3;
const bv = 6;
for (final signed in [true]) {
var bA = signed
? BigInt.from(av).toSigned(widthX)
: BigInt.from(av).toUnsigned(widthX);
final bB = signed
? BigInt.from(bv).toSigned(widthY)
: BigInt.from(bv).toUnsigned(widthY);

// Set these so that printing inside module build will have Logic values
a.put(bA);
b.put(bB);
const radix = 2;
final encoder = RadixEncoder(radix);

final compressorTestMod = CompressorTestMod(a, b, encoder, clk);
await compressorTestMod.build();

unawaited(Simulator.run());

await clk.nextNegedge;
expect(compressorTestMod.compressor.evaluate().$1,
equals(BigInt.from(av * bv)));
av = 4;
bA = signed
? BigInt.from(av).toSigned(widthX)
: BigInt.from(bv).toUnsigned(widthX);
a.put(bA);
await clk.nextNegedge;
expect(compressorTestMod.compressor.evaluate().$1,
equals(BigInt.from(av * bv)));

await Simulator.endSimulation();
}
});

test('example multiplier', () async {
const widthX = 10;
const widthY = 10;
Expand Down
2 changes: 1 addition & 1 deletion test/arithmetic/divider_test.dart
Original file line number Diff line number Diff line change
Expand Up @@ -481,7 +481,7 @@ void main() {
await tb.divider.build();

// Attach a waveform dumper to the DUT
WaveDumper(tb.divider);
// WaveDumper(tb.divider);

// Set a maximum simulation time so it doesn't run forever
Simulator.setMaxSimTime(100000);
Expand Down
8 changes: 8 additions & 0 deletions test/arithmetic/parallel_prefix_operations_test.dart
Original file line number Diff line number Diff line change
Expand Up @@ -195,6 +195,14 @@ void main() {
}
}
});
test('simple priority encoder test', () {
final val = Logic(width: 5);
// ignore: cascade_invocations
val.put(3);
expect(ParallelPrefixPriorityEncoder(val).out.value.toInt(), equals(0));
expect(ParallelPrefixPriorityEncoder(val.reversed).out.value.toInt(),
equals(3));
});

// Note: all ParallelPrefixAdders are tested in adder_test.dart
}

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