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Original file line number | Diff line number | Diff line change |
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@@ -7,6 +7,7 @@ | |
// 2024 June 04 | ||
// Author: Desmond Kirkpatrick <[email protected]> | ||
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import 'dart:async'; | ||
import 'dart:io'; | ||
import 'dart:math'; | ||
import 'package:rohd/rohd.dart'; | ||
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@@ -16,6 +17,38 @@ import 'package:rohd_hcl/src/arithmetic/evaluate_partial_product.dart'; | |
import 'package:rohd_hcl/src/arithmetic/partial_product_sign_extend.dart'; | ||
import 'package:test/test.dart'; | ||
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/// A simple module to test partial product generation and compression | ||
class CompressorTestMod extends Module { | ||
late final PartialProductGenerator pp; | ||
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late final ColumnCompressor compressor; | ||
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Logic get r0 => output('r0'); | ||
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Logic get r1 => output('r1'); | ||
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CompressorTestMod(Logic ia, Logic ib, RadixEncoder encoder, Logic? iclk, | ||
{bool signed = true}) | ||
: super(name: 'compressor_test_mod') { | ||
final a = addInput('a', ia, width: ia.width); | ||
final b = addInput('b', ib, width: ib.width); | ||
Logic? clk; | ||
if (iclk != null) { | ||
clk = addInput('clk', iclk); | ||
} | ||
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pp = PartialProductGeneratorCompactRectSignExtension(a, b, encoder, | ||
signed: signed); | ||
compressor = ColumnCompressor(pp, clk: clk); | ||
compressor.compress(); | ||
final r0 = addOutput('r0', width: compressor.columns.length); | ||
final r1 = addOutput('r1', width: compressor.columns.length); | ||
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r0 <= compressor.extractRow(0); | ||
r1 <= compressor.extractRow(1); | ||
} | ||
} | ||
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void testCompressionExhaustive(PartialProductGenerator pp) { | ||
final widthX = pp.selector.multiplicand.width; | ||
final widthY = pp.encoder.multiplier.width; | ||
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@@ -76,6 +109,9 @@ void testCompressionExhaustive(PartialProductGenerator pp) { | |
} | ||
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void main() { | ||
tearDown(() async { | ||
await Simulator.reset(); | ||
}); | ||
test('exhaustive compression evaluate: square radix-4, just CompactRect', | ||
() async { | ||
stdout.write('\n'); | ||
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@@ -163,6 +199,50 @@ void main() { | |
} | ||
}); | ||
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test('single compressor evaluate flopped', () async { | ||
final clk = SimpleClockGenerator(10).clk; | ||
const widthX = 6; | ||
const widthY = 6; | ||
final a = Logic(name: 'a', width: widthX); | ||
final b = Logic(name: 'b', width: widthY); | ||
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var av = 3; | ||
const bv = 6; | ||
for (final signed in [true]) { | ||
var bA = signed | ||
? BigInt.from(av).toSigned(widthX) | ||
: BigInt.from(av).toUnsigned(widthX); | ||
final bB = signed | ||
? BigInt.from(bv).toSigned(widthY) | ||
: BigInt.from(bv).toUnsigned(widthY); | ||
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// Set these so that printing inside module build will have Logic values | ||
a.put(bA); | ||
b.put(bB); | ||
const radix = 2; | ||
final encoder = RadixEncoder(radix); | ||
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final compressorTestMod = CompressorTestMod(a, b, encoder, clk); | ||
await compressorTestMod.build(); | ||
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unawaited(Simulator.run()); | ||
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await clk.nextNegedge; | ||
expect(compressorTestMod.compressor.evaluate().$1, | ||
equals(BigInt.from(av * bv))); | ||
av = 4; | ||
bA = signed | ||
? BigInt.from(av).toSigned(widthX) | ||
: BigInt.from(bv).toUnsigned(widthX); | ||
a.put(bA); | ||
await clk.nextNegedge; | ||
expect(compressorTestMod.compressor.evaluate().$1, | ||
equals(BigInt.from(av * bv))); | ||
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await Simulator.endSimulation(); | ||
} | ||
}); | ||
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test('example multiplier', () async { | ||
const widthX = 10; | ||
const widthY = 10; | ||
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