From c321b7320c9c28aa8d817b65eba5cf7b7688ffbb Mon Sep 17 00:00:00 2001 From: "Harper, Jason M" Date: Wed, 18 Dec 2024 10:43:59 -0800 Subject: [PATCH] add AMD Turin CPU identifier --- internal/cpudb/cpu_defs.go | 1 + 1 file changed, 1 insertion(+) diff --git a/internal/cpudb/cpu_defs.go b/internal/cpudb/cpu_defs.go index 4ee0b9c..c2ee26a 100644 --- a/internal/cpudb/cpu_defs.go +++ b/internal/cpudb/cpu_defs.go @@ -54,6 +54,7 @@ var cpus = CPUDB{ {MicroArchitecture: "Milan", Family: "25", Model: "1", Stepping: "", Architecture: "x86_64", MemoryChannelCount: 8, LogicalThreadCount: 2, CacheWayCount: 0}, // Milan {MicroArchitecture: "Genoa", Family: "25", Model: "(1[6-9]|2[0-9]|3[01])", Stepping: "", Architecture: "x86_64", MemoryChannelCount: 12, LogicalThreadCount: 2, CacheWayCount: 0}, // Genoa, model 16-31 {MicroArchitecture: "Bergamo", Family: "25", Model: "(16[0-9]|17[0-5])", Stepping: "", Architecture: "x86_64", MemoryChannelCount: 12, LogicalThreadCount: 2, CacheWayCount: 0}, // Bergamo, model 160-175 + {MicroArchitecture: "Turin", Family: "26", Model: "2", Stepping: "", Architecture: "x86_64", MemoryChannelCount: 12, LogicalThreadCount: 2, CacheWayCount: 0}, // Turin // ARM CPUs {MicroArchitecture: "Neoverse N1", Family: "", Model: "1", Stepping: "r3p1", Architecture: "arm64", MemoryChannelCount: 8, LogicalThreadCount: 1, CacheWayCount: 0}, // AWS Graviton 2 {MicroArchitecture: "Neoverse V1", Family: "", Model: "1", Stepping: "r1p1", Architecture: "arm64", MemoryChannelCount: 8, LogicalThreadCount: 1, CacheWayCount: 0}, // AWS Graviton 3