diff --git a/dtb/make_dtb.sh b/dtb/make_dtb.sh index d930b0d..b891a3a 100644 --- a/dtb/make_dtb.sh +++ b/dtb/make_dtb.sh @@ -9,8 +9,8 @@ set -e # 5: invalid file hash main() { - local linux='https://cdn.kernel.org/pub/linux/kernel/v6.x/linux-6.5.7.tar.xz' - local lxsha='0d09ea448005c9cfe5383e4c72a872b39188b928f8c44e146b03b1b7851fbb8c' + local linux='https://git.kernel.org/torvalds/t/linux-6.6-rc6.tar.gz' + local lxsha='4fa3ebe1d789b6286e20cd5368c65094786b2a33722878645d04952382aded42' local lf="$(basename "$linux")" local lv="$(echo "$lf" | sed -nE 's/linux-(.*)\.tar\..z/\1/p')" diff --git a/dtb/patches/0001-riscv-dts-starfive-Add-mmc-nodes-on-VisionFive-2-boa.patch b/dtb/patches/0001-riscv-dts-starfive-Add-mmc-nodes-on-VisionFive-2-boa.patch deleted file mode 100644 index cd504d0..0000000 --- a/dtb/patches/0001-riscv-dts-starfive-Add-mmc-nodes-on-VisionFive-2-boa.patch +++ /dev/null @@ -1,228 +0,0 @@ -From 1e47deb63b79bf8d50b9f8743e8d213e127b7800 Mon Sep 17 00:00:00 2001 -From: John Clark -Date: Wed, 18 Oct 2023 12:50:52 +0000 -Subject: [PATCH 1/2] riscv: dts: starfive: Add mmc nodes on VisionFive 2 board - Add the mmc nodes for the StarFive JH7110 SoC. Set mmc0 node to emmc and set - mmc1 node to sd. - -Signed-off-by: Conor Dooley ---- - .../jh7110-starfive-visionfive-2.dtsi | 113 ++++++++++++++++++ - arch/riscv/boot/dts/starfive/jh7110.dtsi | 43 +++++++ - 2 files changed, 156 insertions(+) - -diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi -index fa0061e..f90599f 100644 ---- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi -+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi -@@ -15,6 +15,8 @@ - i2c2 = &i2c2; - i2c5 = &i2c5; - i2c6 = &i2c6; -+ mmc0 = &mmc0; -+ mmc1 = &mmc1; - serial0 = &uart0; - }; - -@@ -123,12 +125,28 @@ - #interrupt-cells = <1>; - - regulators { -+ vcc_3v3: dcdc1 { -+ regulator-boot-on; -+ regulator-always-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-name = "vcc_3v3"; -+ }; -+ - vdd_cpu: dcdc2 { - regulator-always-on; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1540000>; - regulator-name = "vdd-cpu"; - }; -+ -+ emmc_vdd: aldo4 { -+ regulator-boot-on; -+ regulator-always-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "emmc_vdd"; -+ }; - }; - }; - }; -@@ -143,6 +161,35 @@ - status = "okay"; - }; - -+&mmc0 { -+ max-frequency = <100000000>; -+ bus-width = <8>; -+ cap-mmc-highspeed; -+ mmc-ddr-1_8v; -+ mmc-hs200-1_8v; -+ non-removable; -+ cap-mmc-hw-reset; -+ post-power-on-delay-ms = <200>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&mmc0_pins>; -+ vmmc-supply = <&vcc_3v3>; -+ vqmmc-supply = <&emmc_vdd>; -+ status = "okay"; -+}; -+ -+&mmc1 { -+ max-frequency = <100000000>; -+ bus-width = <4>; -+ no-sdio; -+ no-mmc; -+ broken-cd; -+ cap-sd-highspeed; -+ post-power-on-delay-ms = <200>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&mmc1_pins>; -+ status = "okay"; -+}; -+ - &sysgpio { - i2c0_pins: i2c0-0 { - i2c-pins { -@@ -200,6 +247,72 @@ - }; - }; - -+ -+ mmc0_pins: mmc0-0 { -+ rst-pins { -+ pinmux = ; -+ bias-pull-up; -+ drive-strength = <12>; -+ input-disable; -+ input-schmitt-disable; -+ slew-rate = <0>; -+ }; -+ -+ mmc-pins { -+ pinmux = , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ ; -+ bias-pull-up; -+ drive-strength = <12>; -+ input-enable; -+ }; -+ }; -+ -+ mmc1_pins: mmc1-0 { -+ clk-pins { -+ pinmux = ; -+ bias-pull-up; -+ drive-strength = <12>; -+ input-disable; -+ input-schmitt-disable; -+ slew-rate = <0>; -+ }; -+ -+ mmc-pins { -+ pinmux = , -+ , -+ , -+ , -+ ; -+ bias-pull-up; -+ drive-strength = <12>; -+ input-enable; -+ input-schmitt-enable; -+ slew-rate = <0>; -+ }; -+ }; -+ - uart0_pins: uart0-0 { - tx-pins { - pinmux = ; - }; - -+ sys_syscon: syscon@13030000 { -+ compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd"; -+ reg = <0x0 0x13030000 0x0 0x1000>; -+ -+ pllclk: clock-controller { -+ compatible = "starfive,jh7110-pll"; -+ clocks = <&osc>; -+ #clock-cells = <1>; -+ }; -+ }; -+ - sysgpio: pinctrl@13040000 { - compatible = "starfive,jh7110-sys-pinctrl"; - reg = <0x0 0x13040000 0x0 0x10000>; -@@ -512,6 +523,38 @@ - <&syscrg JH7110_SYSRST_WDT_CORE>; - }; - -+ mmc0: mmc@16010000 { -+ compatible = "starfive,jh7110-mmc"; -+ reg = <0x0 0x16010000 0x0 0x10000>; -+ clocks = <&syscrg JH7110_SYSCLK_SDIO0_AHB>, -+ <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>; -+ clock-names = "biu","ciu"; -+ resets = <&syscrg JH7110_SYSRST_SDIO0_AHB>; -+ reset-names = "reset"; -+ interrupts = <74>; -+ fifo-depth = <32>; -+ fifo-watermark-aligned; -+ data-addr = <0>; -+ starfive,sysreg = <&sys_syscon 0x14 0x1a 0x7c000000>; -+ status = "disabled"; -+ }; -+ -+ mmc1: mmc@16020000 { -+ compatible = "starfive,jh7110-mmc"; -+ reg = <0x0 0x16020000 0x0 0x10000>; -+ clocks = <&syscrg JH7110_SYSCLK_SDIO1_AHB>, -+ <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>; -+ clock-names = "biu","ciu"; -+ resets = <&syscrg JH7110_SYSRST_SDIO1_AHB>; -+ reset-names = "reset"; -+ interrupts = <75>; -+ fifo-depth = <32>; -+ fifo-watermark-aligned; -+ data-addr = <0>; -+ starfive,sysreg = <&sys_syscon 0x9c 0x1 0x3e>; -+ status = "disabled"; -+ }; -+ - aoncrg: clock-controller@17000000 { - compatible = "starfive,jh7110-aoncrg"; - reg = <0x0 0x17000000 0x0 0x10000>; --- -2.40.1 - diff --git a/dtb/patches/0001-riscv-dts-starfive-visionfive-2-disable-qspi-tdm-and.patch b/dtb/patches/0001-riscv-dts-starfive-visionfive-2-disable-qspi-tdm-and.patch new file mode 100644 index 0000000..6d7d6d0 --- /dev/null +++ b/dtb/patches/0001-riscv-dts-starfive-visionfive-2-disable-qspi-tdm-and.patch @@ -0,0 +1,45 @@ +From 2fd2c6449c28d1b215acfe9ed42c2c040cfcb12b Mon Sep 17 00:00:00 2001 +From: John Clark +Date: Thu, 19 Oct 2023 17:28:25 +0000 +Subject: [PATCH 1/2] riscv: dts: starfive: visionfive 2: disable qspi, tdm, + and usb0 nodes + +Signed-off-by: John Clark +--- + .../boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +index 12ebe97..eadd6ca 100644 +--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi ++++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +@@ -235,7 +235,7 @@ + &qspi { + #address-cells = <1>; + #size-cells = <0>; +- status = "okay"; ++ status = "disabled"; + + nor_flash: flash@0 { + compatible = "jedec,spi-nor"; +@@ -502,7 +502,7 @@ + &tdm { + pinctrl-names = "default"; + pinctrl-0 = <&tdm_pins>; +- status = "okay"; ++ status = "disabled"; + }; + + &uart0 { +@@ -513,7 +513,7 @@ + + &usb0 { + dr_mode = "peripheral"; +- status = "okay"; ++ status = "disabled"; + }; + + &U74_1 { +-- +2.40.1 + diff --git a/dtb/patches/0002-iscv-dts-starfive-jh7110-remove-PLL-clocks-source-in.patch b/dtb/patches/0002-iscv-dts-starfive-jh7110-remove-PLL-clocks-source-in.patch new file mode 100644 index 0000000..0eb7cad --- /dev/null +++ b/dtb/patches/0002-iscv-dts-starfive-jh7110-remove-PLL-clocks-source-in.patch @@ -0,0 +1,37 @@ +From d8472de8b0a0cdc22d8d4b6d3ffbbefb9de28acf Mon Sep 17 00:00:00 2001 +From: John Clark +Date: Thu, 19 Oct 2023 17:36:51 +0000 +Subject: [PATCH 2/2] iscv: dts: starfive: jh7110: remove PLL clocks source in + SYSCRG node + +Signed-off-by: John Clark +--- + arch/riscv/boot/dts/starfive/jh7110.dtsi | 8 ++------ + 1 file changed, 2 insertions(+), 6 deletions(-) + +diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi +index e85464c..660b444 100644 +--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi ++++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi +@@ -774,16 +774,12 @@ + <&gmac1_rgmii_rxin>, + <&i2stx_bclk_ext>, <&i2stx_lrck_ext>, + <&i2srx_bclk_ext>, <&i2srx_lrck_ext>, +- <&tdm_ext>, <&mclk_ext>, +- <&pllclk JH7110_PLLCLK_PLL0_OUT>, +- <&pllclk JH7110_PLLCLK_PLL1_OUT>, +- <&pllclk JH7110_PLLCLK_PLL2_OUT>; ++ <&tdm_ext>, <&mclk_ext>; + clock-names = "osc", "gmac1_rmii_refin", + "gmac1_rgmii_rxin", + "i2stx_bclk_ext", "i2stx_lrck_ext", + "i2srx_bclk_ext", "i2srx_lrck_ext", +- "tdm_ext", "mclk_ext", +- "pll0_out", "pll1_out", "pll2_out"; ++ "tdm_ext", "mclk_ext"; + #clock-cells = <1>; + #reset-cells = <1>; + }; +-- +2.40.1 + diff --git a/dtb/patches/0002-riscv-dts-starfive-visionfive-2-Add-configuration-of.patch b/dtb/patches/0002-riscv-dts-starfive-visionfive-2-Add-configuration-of.patch deleted file mode 100644 index 67c7144..0000000 --- a/dtb/patches/0002-riscv-dts-starfive-visionfive-2-Add-configuration-of.patch +++ /dev/null @@ -1,213 +0,0 @@ -From a8a839e91ec4eba11170c45207fb7e967e7ddae3 Mon Sep 17 00:00:00 2001 -From: John Clark -Date: Wed, 18 Oct 2023 13:08:09 +0000 -Subject: [PATCH 2/2] riscv: dts: starfive: visionfive 2: Add configuration of - gmac and phy - -v1.3B: - v1.3B uses motorcomm YT8531(rgmii-id phy) x2, need delay and - inverse configurations. - The tx_clk of v1.3B uses an external clock and needs to be - switched to an external clock source. - -Signed-off-by: Conor Dooley ---- - .../jh7110-starfive-visionfive-2-v1.3b.dts | 31 ++++++++ - .../jh7110-starfive-visionfive-2.dtsi | 34 +++++++++ - arch/riscv/boot/dts/starfive/jh7110.dtsi | 75 +++++++++++++++++++ - 3 files changed, 140 insertions(+) - -diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts -index 9230cc3..d4ea4a2 100644 ---- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts -+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts -@@ -11,3 +11,34 @@ - model = "StarFive VisionFive 2 v1.3B"; - compatible = "starfive,visionfive-2-v1.3b", "starfive,jh7110"; - }; -+ -+&gmac0 { -+ starfive,tx-use-rgmii-clk; -+ assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>; -+ assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>; -+}; -+ -+&gmac1 { -+ starfive,tx-use-rgmii-clk; -+ assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>; -+ assigned-clock-parents = <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>; -+}; -+ -+&phy0 { -+ motorcomm,tx-clk-adj-enabled; -+ motorcomm,tx-clk-100-inverted; -+ motorcomm,tx-clk-1000-inverted; -+ motorcomm,rx-clk-drv-microamp = <3970>; -+ motorcomm,rx-data-drv-microamp = <2910>; -+ rx-internal-delay-ps = <1500>; -+ tx-internal-delay-ps = <1500>; -+}; -+ -+&phy1 { -+ motorcomm,tx-clk-adj-enabled; -+ motorcomm,tx-clk-100-inverted; -+ motorcomm,rx-clk-drv-microamp = <3970>; -+ motorcomm,rx-data-drv-microamp = <2910>; -+ rx-internal-delay-ps = <300>; -+ tx-internal-delay-ps = <0>; -+}; -diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi -index f90599f..06934cf 100644 ---- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi -+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi -@@ -11,6 +11,8 @@ - - / { - aliases { -+ ethernet0 = &gmac0; -+ ethernet1 = &gmac1; - i2c0 = &i2c0; - i2c2 = &i2c2; - i2c5 = &i2c5; -@@ -88,6 +90,38 @@ - clock-frequency = <49152000>; - }; - -+&gmac0 { -+ phy-handle = <&phy0>; -+ phy-mode = "rgmii-id"; -+ status = "okay"; -+ -+ mdio { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "snps,dwmac-mdio"; -+ -+ phy0: ethernet-phy@0 { -+ reg = <0>; -+ }; -+ }; -+}; -+ -+&gmac1 { -+ phy-handle = <&phy1>; -+ phy-mode = "rgmii-id"; -+ status = "okay"; -+ -+ mdio { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "snps,dwmac-mdio"; -+ -+ phy1: ethernet-phy@1 { -+ reg = <0>; -+ }; -+ }; -+}; -+ - &i2c0 { - clock-frequency = <100000>; - i2c-sda-hold-time-ns = <300>; -diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi -index cc80aa3..5b6fa03 100644 ---- a/arch/riscv/boot/dts/starfive/jh7110.dtsi -+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi -@@ -263,6 +263,13 @@ - #clock-cells = <0>; - }; - -+ stmmac_axi_setup: stmmac-axi-config { -+ snps,lpi_en; -+ snps,wr_osr_lmt = <15>; -+ snps,rd_osr_lmt = <15>; -+ snps,blen = <256 128 64 32 0 0 0>; -+ }; -+ - tdm_ext: tdm-ext-clock { - compatible = "fixed-clock"; - clock-output-names = "tdm_ext"; -@@ -555,6 +562,68 @@ - status = "disabled"; - }; - -+ gmac0: ethernet@16030000 { -+ compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20"; -+ reg = <0x0 0x16030000 0x0 0x10000>; -+ clocks = <&aoncrg JH7110_AONCLK_GMAC0_AXI>, -+ <&aoncrg JH7110_AONCLK_GMAC0_AHB>, -+ <&syscrg JH7110_SYSCLK_GMAC0_PTP>, -+ <&aoncrg JH7110_AONCLK_GMAC0_TX_INV>, -+ <&syscrg JH7110_SYSCLK_GMAC0_GTXC>; -+ clock-names = "stmmaceth", "pclk", "ptp_ref", -+ "tx", "gtx"; -+ resets = <&aoncrg JH7110_AONRST_GMAC0_AXI>, -+ <&aoncrg JH7110_AONRST_GMAC0_AHB>; -+ reset-names = "stmmaceth", "ahb"; -+ interrupts = <7>, <6>, <5>; -+ interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; -+ rx-fifo-depth = <2048>; -+ tx-fifo-depth = <2048>; -+ snps,multicast-filter-bins = <64>; -+ snps,perfect-filter-entries = <256>; -+ snps,fixed-burst; -+ snps,no-pbl-x8; -+ snps,force_thresh_dma_mode; -+ snps,axi-config = <&stmmac_axi_setup>; -+ snps,tso; -+ snps,en-tx-lpi-clockgating; -+ snps,txpbl = <16>; -+ snps,rxpbl = <16>; -+ starfive,syscon = <&aon_syscon 0xc 0x12>; -+ status = "disabled"; -+ }; -+ -+ gmac1: ethernet@16040000 { -+ compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20"; -+ reg = <0x0 0x16040000 0x0 0x10000>; -+ clocks = <&syscrg JH7110_SYSCLK_GMAC1_AXI>, -+ <&syscrg JH7110_SYSCLK_GMAC1_AHB>, -+ <&syscrg JH7110_SYSCLK_GMAC1_PTP>, -+ <&syscrg JH7110_SYSCLK_GMAC1_TX_INV>, -+ <&syscrg JH7110_SYSCLK_GMAC1_GTXC>; -+ clock-names = "stmmaceth", "pclk", "ptp_ref", -+ "tx", "gtx"; -+ resets = <&syscrg JH7110_SYSRST_GMAC1_AXI>, -+ <&syscrg JH7110_SYSRST_GMAC1_AHB>; -+ reset-names = "stmmaceth", "ahb"; -+ interrupts = <78>, <77>, <76>; -+ interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; -+ rx-fifo-depth = <2048>; -+ tx-fifo-depth = <2048>; -+ snps,multicast-filter-bins = <64>; -+ snps,perfect-filter-entries = <256>; -+ snps,fixed-burst; -+ snps,no-pbl-x8; -+ snps,force_thresh_dma_mode; -+ snps,axi-config = <&stmmac_axi_setup>; -+ snps,tso; -+ snps,en-tx-lpi-clockgating; -+ snps,txpbl = <16>; -+ snps,rxpbl = <16>; -+ starfive,syscon = <&sys_syscon 0x90 0x2>; -+ status = "disabled"; -+ }; -+ - aoncrg: clock-controller@17000000 { - compatible = "starfive,jh7110-aoncrg"; - reg = <0x0 0x17000000 0x0 0x10000>; -@@ -572,6 +641,12 @@ - #reset-cells = <1>; - }; - -+ aon_syscon: syscon@17010000 { -+ compatible = "starfive,jh7110-aon-syscon", "syscon"; -+ reg = <0x0 0x17010000 0x0 0x1000>; -+ #power-domain-cells = <1>; -+ }; -+ - aongpio: pinctrl@17020000 { - compatible = "starfive,jh7110-aon-pinctrl"; - reg = <0x0 0x17020000 0x0 0x10000>; --- -2.40.1 -