Releases: icedland/iced
Releases · icedland/iced
v1.11.3
v1.11.2
v1.11.1
v1.11.0
- Added Intel
FRED
andLKGS
instructions - Decoder and formatter perf improvements (Rust, see below)
Instruction
's memory displacement is now 64 bits (was 32 bits). This solves a couple of issues and will make creatingRIP
-relative memory operands much easier.- Use
MemoryDisplacement{32,64}
/memory_displacement{32,64}()
(deprecated old 32-bit members:MemoryDisplacement
/memory_displacement()
) - If it's an
EIP
/RIP
relative memory operand,MemoryDisplacement64
/memory_displacement64()
is now the absolute address (used to be an RIP-relative displacement) OpKind.Memory64
is deprecated since it's not used by iced (useOpKind.Memory
instead)MemoryOperand
's displacement argument is now ani64
(used to be ani32
)
- Use
- Added
Decoder::with_ip()
/Decoder.Create()
with an extraip
argument (Rust/.NET/Python)
Rust
FastFormatter
perf improvements:- The new generic
SpecializedFormatter<TraitOptions>
is 2x faster than the oldFastFormatter
code. see here FastFormatter
is nowtype FastFormatter = SpecializedFormatter<T>
(no breaking changes)
- The new generic
- Decoder perf improvements see here
- MSRV is now 1.41.0 (one year old Rust)
- Deprecated a few methods that could panic that I missed last time and added
try_*()
methods that return aResult<T, E>
- Added
Register::values()
(Credit: @tnballo) that returns an iterator that returns all enum values. Same associated method was also added to the other public enums. - All enums now implement
TryFrom<usize>
- Added
Instruction::op_kinds()
which returns all (0-5)OpKind
values
v1.10.0
- Added GMI instructions (some Zhaoxin CPUs)
- Added FPU flags (
C0
,C1
,C2
,C3
) toRflagsBits
- Added
Instruction.GetFpuStackIncrementInfo()
/Instruction.fpu_stack_increment_info()
to get the value added to FPUTOP
and whether it's written by the instruction - Rust: Added
UsedMemory.{try_,}virtual_address()
(Credit: @woodruffw) - .NET: Added
{UsedMemory,Instruction}.TryGetVirtualAddress()
- Rust: deprecated some methods that can panic and added
try_*()
methods that return aResult<T, E>
- Added Python bindings
v1.9.0
- Added new Intel instructions:
TDX
,Key Locker
,UINTR
,HRESET
,AVX-VNNI
- Added Cyrix/Geode instructions and Centaur
ALTINST
- Added more
OpCodeInfo
properties: cpl, mode (rm, v86, vmx, etc), tsx, serializing, vm exit and more. - Added
FastFormatter
with a masm-like syntax that can be used if formatting speed is more important than being able to re-assemble formatted instructions. It also uses less code (good if you're targeting wasm). - Added
Instruction.HasOpKind()
(Credit: @Symbai)
v1.8.0
- Added Intel
AMX
instructions, AMDVMGEXIT
andREX.W GETSEC
- Synced formatter output with latest gas/masm/nasm
- Updated AMD decoder (it doesn't support
REX.W CALL/JMP FAR [mem]
,REX.W LSS/LFS/LGS [mem]
), addUD0
(without a modrm byte). Use theAMD
decoder option, the olderAmdBranches
is now obsolete but does the same thing. - Intel removed
MPX
ISA in 2019.MPX
instructions are now disabled by default but can be enabled with theMPX
decoder option. - Added
Decoder.LastError
property, deprecatedInvalidNoMoreBytes
- Added
Assembler.db(byte[])
(Credit: @Symbai) - Added
try_virtual_address()
(Credit: @Ralith) - Added generator
--{in,ex}clude-cpuid <name>
command line options - .NET, Rust and JavaScript libs use the same version number
v1.7.0
- Supports new AMD instructions:
INVLPGB
,TLBSYNC
NegateConditionCode()
/ConditionCode()
now also supportLOOPE
/LOOPNE
- Added formatter options to override
Jcc
/SETcc
/CMOVcc
/LOOPcc
mnemonics (eg.JE
orJZ
) - Added
ShowUselessPrefixes
formatter option - Decoder now implements
IEnumerable<Instruction>
- Added a
Decoder.Create(bitness, byte[], options)
overload
v1.6.0
- Supports new Intel instructions:
SERIALIZE
,XSUSLDTRK
,XRESLDTRK
- Supports new AMD instructions:
PSMASH
,PVALIDATE
,RMPADJUST
,RMPUPDATE
- Added
PreferST0
formatter option (fadd st,st(3)
vsfadd st(0),st(3)
) - Added
Decoder.InvalidNoMoreBytes
which istrue
if the decoded instruction is invalid because there are no more bytes left. - Moved gas/masm/nasm-specific formatter options to the base options class
v1.5.0
Assembler
class was added (thanks to @xoofx for adding this feature!) which lets you easily add instructions with a syntax that looks like assembler, eg.c.imul(rcx, __[rdx*8+0x10], -10)
. It supports all instructions and all modes (16/32/64-bit). See the example in theREADME
for more info.- Removed
net35
tfm, addednetstandard2.1
tfm - Added
Instruction.HasSegmentPrefix
property - Added
Encoder.WriteByte()
- Enabling upper case disassembly doesn't allocate temp strings
- Added
OpCodeOperandKind.r{16,32,64}_reg_mem
formovdir64b/enqcmd{s,}
- Added
StreamCodeWriter
andStreamCodeReader
- FIX:
VZERO{UPPER,ALL}
don't touch regs 16-31 BlockEncoder.TryEncode()
signature got updated with aBlockEncoderResult
Instruction.GetInfo()/GetUsedRegisters()/GetUsedMemory()
were removed, and the docs never recommended using them. UseInstructionInfoFactory
instead.FormatterOperandOptions
is now a struct, used to be a flags enum.Instruction.Create()
methods now throw if the immediate value is invalid- Obsoleted
StringBuilderFormatterOutput
, useStringOutput
instead (shorter name!) - Renamed
FormatterOutputTextKind
->FormatterTextKind