From 0c1d84318f1d01cba24f46cf2f154f7e77cfa473 Mon Sep 17 00:00:00 2001 From: Andelf Date: Fri, 28 Jun 2024 11:56:22 +0800 Subject: [PATCH] chore: minor cleanup --- data/interrupts/HPM6E80.yaml | 16 +- svd/HPM64A0_svd.xml | 34201 --------------------------------- svd/HPM64G0_svd.xml | 34201 --------------------------------- 3 files changed, 8 insertions(+), 68410 deletions(-) delete mode 100644 svd/HPM64A0_svd.xml delete mode 100644 svd/HPM64G0_svd.xml diff --git a/data/interrupts/HPM6E80.yaml b/data/interrupts/HPM6E80.yaml index 79b9d77..11a51e1 100644 --- a/data/interrupts/HPM6E80.yaml +++ b/data/interrupts/HPM6E80.yaml @@ -108,10 +108,10 @@ RDC0: 107 RDC1: 108 SDM0: 109 SDM1: 110 -SEI0: 111 -SEI1: 112 -SEI2: 113 -SEI3: 114 +SEI_0: 111 +SEI_1: 112 +SEI_2: 113 +SEI_3: 114 MTG0: 115 MTG1: 116 VSC0: 117 @@ -125,10 +125,10 @@ TRGMUX1: 124 ENET0: 125 NTMR0: 126 USB0: 127 -TSW0: 128 -TSW1: 129 -TSW2: 130 -TSW3: 131 +TSW_0: 128 +TSW_1: 129 +TSW_2: 130 +TSW_3: 131 TSW_PTP_EVT: 132 ESC: 133 ESC_SYNC0: 134 diff --git a/svd/HPM64A0_svd.xml b/svd/HPM64A0_svd.xml deleted file mode 100644 index 1fea610..0000000 --- a/svd/HPM64A0_svd.xml +++ /dev/null @@ -1,34201 +0,0 @@ - - - HPMICRO - HPM64A0 - HPM6700 - 1.0 - HPM6700/HPM6400 device - - /* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - - - other - r0p0 - little - false - true - true - 7 - false - - - - 8 - 32 - 32 - read-write - 0x0 - 0xFFFFFFFF - - - - - FGPIO - FGPIO - GPIO - 0xc0000 - - 0x0 - 0x800 - registers - - - - 16 - 0x10 - gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz - DI[%s] - no description available - 0x0 - - VALUE - GPIO input value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - INPUT - GPIO input bus value, each bit represents a bus bit -0: low level presents on chip pin -1: high level presents on chip pin - 0 - 32 - read-only - - - - - - 16 - 0x10 - gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz - DO[%s] - no description available - 0x100 - - VALUE - GPIO output value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - SET - GPIO output set - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - CLEAR - GPIO output clear - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - TOGGLE - GPIO output toggle - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - - 16 - 0x10 - gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz - OE[%s] - no description available - 0x200 - - VALUE - GPIO direction value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - SET - GPIO direction set - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - CLEAR - GPIO direction clear - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - TOGGLE - GPIO direction toggle - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - - 16 - 0x10 - gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz - IF[%s] - no description available - 0x300 - - VALUE - GPIO interrupt flag value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_FLAG - GPIO interrupt flag, write 1 to clear this flag -0: no irq -1: irq pending - 0 - 32 - write-only - - - - - - 16 - 0x10 - gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz - IE[%s] - no description available - 0x400 - - VALUE - GPIO interrupt enable value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - SET - GPIO interrupt enable set - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - CLEAR - GPIO interrupt enable clear - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - TOGGLE - GPIO interrupt enable toggle - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - - 16 - 0x10 - gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz - PL[%s] - no description available - 0x500 - - VALUE - GPIO interrupt polarity value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - SET - GPIO interrupt polarity set - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - CLEAR - GPIO interrupt polarity clear - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - TOGGLE - GPIO interrupt polarity toggle - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - - 16 - 0x10 - gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz - TP[%s] - no description available - 0x600 - - VALUE - GPIO interrupt type value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - SET - GPIO interrupt type set - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - CLEAR - GPIO interrupt type clear - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - TOGGLE - GPIO interrupt type toggle - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - - 16 - 0x10 - gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz - AS[%s] - no description available - 0x700 - - VALUE - GPIO interrupt asynchronous value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - SET - GPIO interrupt asynchronous set - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - CLEAR - GPIO interrupt asynchronous clear - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - TOGGLE - GPIO interrupt asynchronous toggle - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - - - - GPIO0 - GPIO0 - GPIO - 0xf0000000 - - - GPIO1 - GPIO1 - GPIO - 0xf0004000 - - - PGPIO - PGPIO - GPIO - 0xf40dc000 - - - BGPIO - BGPIO - GPIO - 0xf5014000 - - - PLIC - PLIC - PLIC - 0xe4000000 - - 0x0 - 0x202000 - registers - - - - feature - Feature enable register - 0x0 - 32 - 0x00000000 - 0x00000003 - - - VECTORED - Vector mode enable -0: Disabled -1: Enabled - 1 - 1 - read-write - - - PREEMPT - Preemptive priority interrupt enable -0: Disabled -1: Enabled - 0 - 1 - read-write - - - - - 127 - 0x4 - PRIORITY1,PRIORITY2,PRIORITY3,PRIORITY4,PRIORITY5,PRIORITY6,PRIORITY7,PRIORITY8,PRIORITY9,PRIORITY10,PRIORITY11,PRIORITY12,PRIORITY13,PRIORITY14,PRIORITY15,PRIORITY16,PRIORITY17,PRIORITY18,PRIORITY19,PRIORITY20,PRIORITY21,PRIORITY22,PRIORITY23,PRIORITY24,PRIORITY25,PRIORITY26,PRIORITY27,PRIORITY28,PRIORITY29,PRIORITY30,PRIORITY31,PRIORITY32,PRIORITY33,PRIORITY34,PRIORITY35,PRIORITY36,PRIORITY37,PRIORITY38,PRIORITY39,PRIORITY40,PRIORITY41,PRIORITY42,PRIORITY43,PRIORITY44,PRIORITY45,PRIORITY46,PRIORITY47,PRIORITY48,PRIORITY49,PRIORITY50,PRIORITY51,PRIORITY52,PRIORITY53,PRIORITY54,PRIORITY55,PRIORITY56,PRIORITY57,PRIORITY58,PRIORITY59,PRIORITY60,PRIORITY61,PRIORITY62,PRIORITY63,PRIORITY64,PRIORITY65,PRIORITY66,PRIORITY67,PRIORITY68,PRIORITY69,PRIORITY70,PRIORITY71,PRIORITY72,PRIORITY73,PRIORITY74,PRIORITY75,PRIORITY76,PRIORITY77,PRIORITY78,PRIORITY79,PRIORITY80,PRIORITY81,PRIORITY82,PRIORITY83,PRIORITY84,PRIORITY85,PRIORITY86,PRIORITY87,PRIORITY88,PRIORITY89,PRIORITY90,PRIORITY91,PRIORITY92,PRIORITY93,PRIORITY94,PRIORITY95,PRIORITY96,PRIORITY97,PRIORITY98,PRIORITY99,PRIORITY100,PRIORITY101,PRIORITY102,PRIORITY103,PRIORITY104,PRIORITY105,PRIORITY106,PRIORITY107,PRIORITY108,PRIORITY109,PRIORITY110,PRIORITY111,PRIORITY112,PRIORITY113,PRIORITY114,PRIORITY115,PRIORITY116,PRIORITY117,PRIORITY118,PRIORITY119,PRIORITY120,PRIORITY121,PRIORITY122,PRIORITY123,PRIORITY124,PRIORITY125,PRIORITY126,PRIORITY127 - PRIORITY[%s] - no description available - 0x4 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - 4 - 0x4 - PENDING0,PENDING1,PENDING2,PENDING3 - PENDING[%s] - no description available - 0x1000 - 32 - 0x00000000 - 0xFFFFFFFF - - - INTERRUPT - The interrupt pending status of inpterrupt sources. Every interrupt source occupies 1 bit. - 0 - 32 - read-write - - - - - 4 - 0x4 - TRIGGER0,TRIGGER1,TRIGGER2,TRIGGER3 - TRIGGER[%s] - no description available - 0x1080 - 32 - 0x00000000 - 0xFFFFFFFF - - - INTERRUPT - The interrupt trigger type of interrupt sources. Every interrupt source occupies 1 bit. -0: Level-triggered interrupt -1: Edge-triggered interrupt - 0 - 32 - read-only - - - - - NUMBER - Number of supported interrupt sources and targets - 0x1100 - 32 - 0xFFFFFFFF - - - NUM_TARGET - The number of supported targets - 16 - 16 - read-only - - - NUM_INTERRUPT - The number of supported interrupt sources - 0 - 16 - read-only - - - - - INFO - Version and the maximum priority - 0x1104 - 32 - 0xFFFFFFFF - - - MAX_PRIORITY - The maximum priority supported - 16 - 16 - read-only - - - VERSION - The version of the PLIC design - 0 - 16 - read-only - - - - - 2 - 0x80 - target0,target1 - TARGETINT[%s] - no description available - 0x2000 - - 4 - 0x4 - INTEN0,INTEN1,INTEN2,INTEN3 - INTEN[%s] - no description available - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - INTERRUPT - The interrupt enable bit for interrupt. Every interrupt source occupies 1 bit. - 0 - 32 - read-write - - - - - - 2 - 0x1000 - target0,target1 - TARGETCONFIG[%s] - no description available - 0x200000 - - THRESHOLD - Target0 priority threshold - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - THRESHOLD - Interrupt priority threshold. - 0 - 32 - read-write - - - - - CLAIM - Target claim and complete - 0x4 - 32 - 0x00000000 - 0x000003FF - - - INTERRUPT_ID - On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed). - 0 - 10 - read-write - - - - - PPS - Preempted priority stack - 0x400 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRIORITY_PREEMPTED - Each bit indicates if the corresponding priority level has been preempted by a higher-priority interrupt. - 0 - 32 - read-write - - - - - - - - MCHTMR - MCHTMR - MCHTMR - 0xe6000000 - - 0x0 - 0x10 - registers - - - - MTIME - Machine Time - 0x0 - 64 - 0x0000000000020210 - 0xFFFFFFFFFFFFFFFF - - - MTIME - Machine time - 0 - 64 - read-write - - - - - MTIMECMP - Machine Time Compare - 0x8 - 64 - 0x0000000000020210 - 0xFFFFFFFFFFFFFFFF - - - MTIMECMP - Machine time compare - 0 - 64 - read-write - - - - - - - PLICSW - PLICSW - PLICSW - 0xe6400000 - - 0x1000 - 0x1ff008 - registers - - - - PENDING - Pending status - 0x1000 - 32 - 0x00000000 - 0x00000002 - - - INTERRUPT - writing 1 to trigger software interrupt - 1 - 1 - read-write - - - - - INTEN - Interrupt enable - 0x2000 - 32 - 0x00000000 - 0x00000001 - - - INTERRUPT - enable software interrupt - 0 - 1 - read-write - - - - - CLAIM - Claim and complete. - 0x200004 - 32 - 0x00000000 - 0x00000001 - - - INTERRUPT_ID - On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed). - 0 - 1 - read-write - - - - - - - GPIOM - GPIOM - GPIOM - 0xf0008000 - - 0x0 - 0x800 - registers - - - - 16 - 0x80 - gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz - ASSIGN[%s] - no description available - 0x0 - - 32 - 0x4 - PIN00,PIN01,PIN02,PIN03,PIN04,PIN05,PIN06,PIN07,PIN08,PIN09,PIN10,PIN11,PIN12,PIN13,PIN14,PIN15,PIN16,PIN17,PIN18,PIN19,PIN20,PIN21,PIN22,PIN23,PIN24,PIN25,PIN26,PIN27,PIN28,PIN29,PIN30,PIN31 - PIN[%s] - no description available - 0x0 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - - - - ADC0 - ADC0 - ADC12 - 0xf0010000 - - 0x0 - 0x1214 - registers - - - - 12 - 0x4 - trg0a,trg0b,trg0c,trg1a,trg1b,trg1c,trg2a,trg2b,trg2c,trg3a,trg3b,trg3c - CONFIG[%s] - no description available - 0x0 - 32 - 0x00000000 - 0xFF3F3F3F - - - TRIG_LEN - length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 - 30 - 2 - write-only - - - INTEN3 - interrupt enable for 4th conversion - 29 - 1 - read-write - - - CHAN3 - channel number for 4th conversion - 24 - 5 - read-write - - - INTEN2 - interrupt enable for 3rd conversion - 21 - 1 - read-write - - - CHAN2 - channel number for 3rd conversion - 16 - 5 - read-write - - - INTEN1 - interrupt enable for 2nd conversion - 13 - 1 - read-write - - - CHAN1 - channel number for 2nd conversion - 8 - 5 - read-write - - - INTEN0 - interrupt enable for 1st conversion - 5 - 1 - read-write - - - CHAN0 - channel number for 1st conversion - 0 - 5 - read-write - - - - - trg_dma_addr - No description available - 0x30 - 32 - 0x00000000 - 0xFFFFFFFC - - - TRG_DMA_ADDR - buffer start address for trigger queue, 192byte total, 16 bytes for each trigger (4 bytes for each conversion) - 2 - 30 - read-write - - - - - trg_sw_sta - No description available - 0x34 - 32 - 0x00000000 - 0x0000001F - - - TRG_SW_STA - SW trigger start bit, HW will clear it after all conversions(up to 4) finished. SW should make sure it's 0 before set it. - 4 - 1 - read-write - - - TRIG_SW_INDEX - which trigger for the SW trigger -0 for trig0a, 1 for trig0b… -3 for trig1a, …11 for trig3c - 0 - 4 - read-write - - - - - 19 - 0x4 - chn0,chn1,chn2,chn3,chn4,chn5,chn6,chn7,chn8,chn9,chn10,chn11,chn12,chn13,chn14,chn15,chn16,chn17,chn18 - BUS_RESULT[%s] - no description available - 0x400 - 32 - 0x00000000 - 0x0001FFF0 - - - VALID - set after conversion finished if wait_dis is set, cleared after software read. -The first time read with 0 will trigger one new conversion. -If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. -the result may not realtime if software read once and wait long time to read again - 16 - 1 - read-only - - - CHAN_RESULT - read this register will trigger one adc conversion. -If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result -If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long - 4 - 12 - read-only - - - - - buf_cfg0 - No description available - 0x500 - 32 - 0x00000000 - 0x00000001 - - - WAIT_DIS - set to disable read waiting, get result immediately but maybe not current conversion result. - 0 - 1 - read-write - - - - - seq_cfg0 - No description available - 0x800 - 32 - 0x00000000 - 0x80000F1F - - - CYCLE - current dma write cycle bit - 31 - 1 - read-only - - - SEQ_LEN - sequence queue length, 0 for one, 0xF for 16 - 8 - 4 - read-write - - - RESTART_EN - if set together with cont_en, HW will continue process the whole queue after trigger once. -If cont_en is 0, this bit is not used - 4 - 1 - read-write - - - CONT_EN - if set, HW will continue process the queue till end(seq_len) after trigger once - 3 - 1 - read-write - - - SW_TRIG - SW trigger, pulse signal, cleared by HW one cycle later - 2 - 1 - write-only - - - SW_TRIG_EN - set to enable SW trigger - 1 - 1 - read-write - - - HW_TRIG_EN - set to enable external HW trigger, only trigger on posedge - 0 - 1 - read-write - - - - - seq_dma_addr - No description available - 0x804 - 32 - 0x00000000 - 0xFFFFFFFC - - - TAR_ADDR - dma target address, should be 4-byte aligned - 2 - 30 - read-write - - - - - seq_wr_addr - No description available - 0x808 - 32 - 0x00000000 - 0x00000FFF - - - SEQ_WR_POINTER - HW update this field after each dma write, it indicate the next dma write pointer. -dma write address is (tar_addr+seq_wr_pointer)*4 - 0 - 12 - read-only - - - - - seq_dma_cfg - No description available - 0x80c - 32 - 0x00000000 - 0x0FFF3FFF - - - STOP_POS - if stop_en is set, SW is responsible to update this field to the next read point, HW should not write data to this point since it's not read out by SW yet - 16 - 12 - read-write - - - DMA_RST - set this bit will reset HW dma write pointer to seq_dma_addr, and set HW cycle bit to 1. dma is halted if this bit is set. -SW should clear all cycle bit in buffer to 0 before clear dma_rst - 13 - 1 - read-write - - - STOP_EN - set to stop dma if reach the stop_pos - 12 - 1 - read-write - - - BUF_LEN - dma buffer length, after write to (tar_addr[31:2]+buf_len)*4, the next dma address will be tar_addr[31:2]*4 -0 for 4byte; -0xFFF for 16kbyte. - 0 - 12 - read-write - - - - - 16 - 0x4 - cfg0,cfg1,cfg2,cfg3,cfg4,cfg5,cfg6,cfg7,cfg8,cfg9,cfg10,cfg11,cfg12,cfg13,cfg14,cfg15 - SEQ_QUE[%s] - no description available - 0x810 - 32 - 0x00000000 - 0x0000003F - - - SEQ_INT_EN - interrupt enable for current conversion - 5 - 1 - read-write - - - CHAN_NUM_4_0 - channel number for current conversion - 0 - 5 - read-write - - - - - 19 - 0x10 - chn0,chn1,chn2,chn3,chn4,chn5,chn6,chn7,chn8,chn9,chn10,chn11,chn12,chn13,chn14,chn15,chn16,chn17,chn18 - PRD_CFG[%s] - no description available - 0xc00 - - prd_cfg - No description available - 0x0 - 32 - 0x00000000 - 0x00001FFF - - - PRESCALE - 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx - 8 - 5 - read-write - - - PRD - conver period, with prescale. -Set to 0 means disable current channel - 0 - 8 - read-write - - - - - prd_thshd_cfg - No description available - 0x4 - 32 - 0x00000000 - 0xFFF0FFF0 - - - THSHDH - threshold high, assert interrupt(if enabled) if result exceed high or low. - 20 - 12 - read-write - - - THSHDL - threshold low - 4 - 12 - read-write - - - - - prd_result - No description available - 0x8 - 32 - 0x00000000 - 0x0000FFF0 - - - CHAN_RESULT - adc convert result, update after each valid conversion. -it may be updated period according to config, also may be updated due to other queue convert the same channel - 4 - 12 - read-only - - - - - - 19 - 0x4 - chn0,chn1,chn2,chn3,chn4,chn5,chn6,chn7,chn8,chn9,chn10,chn11,chn12,chn13,chn14,chn15,chn16,chn17,chn18 - SAMPLE_CFG[%s] - no description available - 0x1000 - 32 - 0x00000000 - 0x00001FFF - - - DIFF_SEL - set to 1 to select differential channel - 12 - 1 - read-write - - - SAMPLE_CLOCK_NUMBER_SHIFT - shift for sample_clock_number - 9 - 3 - read-write - - - SAMPLE_CLOCK_NUMBER - sample clock number, base on clock_period, default one period - 0 - 9 - read-write - - - - - conv_cfg1 - No description available - 0x1104 - 32 - 0x00000000 - 0x000001FF - - - CONVERT_CLOCK_NUMBER - convert clock numbers, set to 13 (0xD) for 12bit mode, which means convert need 14 adc clock cycles(based on clock after divider); -set to 11 for 10bit mode; set to 9 for 8bit mode; set to 7 or 6bit mode; -Ex: use 200MHz bus clock for adc, set sample_clock_number to 4, sample_clock_number_shift to 0, covert_clk_number to 13 for 12bit mode, clock_divder to 2, then each ADC conversion(plus sample) need 18(14 convert, 4 sample) cycles(66MHz). - 4 - 5 - read-write - - - CLOCK_DIVIDER - clock_period, N half clock cycle per half adc cycle -0 for same adc_clk and bus_clk, -1 for 1:2, -2 for 1:3, -... -15 for 1:16 -Note: set to 2 can genenerate 66.7MHz adc_clk at 200MHz bus_clk - 0 - 4 - read-write - - - - - adc_cfg0 - No description available - 0x1108 - 32 - 0x00000000 - 0xA0000000 - - - SEL_SYNC_AHB - set to 1 will enable sync AHB bus, to get better bus performance. -Adc_clk must to be set to same as bus clock at this mode - 31 - 1 - read-write - - - ADC_AHB_EN - set to 1 to enable ADC DMA to write data to soc memory bus, for trig queue and seq queue; - 29 - 1 - read-write - - - - - int_sts - No description available - 0x1110 - 32 - 0x00000000 - 0xFFE7FFFF - - - TRIG_CMPT - interrupt for one trigger conversion complete if enabled - 31 - 1 - read-write - - - TRIG_SW_CFLCT - No description available - 30 - 1 - read-write - - - TRIG_HW_CFLCT - No description available - 29 - 1 - read-write - - - READ_CFLCT - read conflict interrupt, set if wait_dis is set, one conversion is in progress, SW read another channel - 28 - 1 - read-write - - - SEQ_SW_CFLCT - sequence queue conflict interrupt, set if HW or SW trigger received during conversion - 27 - 1 - read-write - - - SEQ_HW_CFLCT - No description available - 26 - 1 - read-write - - - SEQ_DMAABT - dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set - 25 - 1 - read-write - - - SEQ_CMPT - the whole sequence complete interrupt - 24 - 1 - read-write - - - SEQ_CVC - one conversion complete in seq_queue if related seq_int_en is set - 23 - 1 - read-write - - - DMA_FIFO_FULL - No description available - 22 - 1 - read-write - - - AHB_ERR - set if got hresp=1 - 21 - 1 - read-write - - - WDOG - set if one chanel watch dog event triggered - 0 - 19 - read-write - - - - - int_en - No description available - 0x1114 - 32 - 0x00000000 - 0xFFE7FFFF - - - TRIG_CMPT - interrupt for one trigger conversion complete if enabled - 31 - 1 - read-write - - - TRIG_SW_CFLCT - No description available - 30 - 1 - read-write - - - TRIG_HW_CFLCT - No description available - 29 - 1 - read-write - - - READ_CFLCT - read conflict interrupt, set if wait_dis is set, one conversion is in progress, SW read another channel - 28 - 1 - read-write - - - SEQ_SW_CFLCT - sequence queue conflict interrupt, set if HW or SW trigger received during conversion - 27 - 1 - read-write - - - SEQ_HW_CFLCT - No description available - 26 - 1 - read-write - - - SEQ_DMAABT - dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set - 25 - 1 - read-write - - - SEQ_CMPT - the whole sequence complete interrupt - 24 - 1 - read-write - - - SEQ_CVC - one conversion complete in seq_queue if related seq_int_en is set - 23 - 1 - read-write - - - DMA_FIFO_FULL - DMA fifo full interrupt, user need to check clock frequency if it's set. - 22 - 1 - read-write - - - AHB_ERR - set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr - 21 - 1 - read-write - - - WDOG - set if one chanel watch dog event triggered - 0 - 19 - read-write - - - - - ana_ctrl0 - No description available - 0x1200 - 32 - 0x00000000 - 0x7F7F487E - - - CAL_VAL_DIFF - calibration value for differential mode - 24 - 7 - read-write - - - CAL_VAL_SE - calibration value for single-end mode - 16 - 7 - read-write - - - REARM_EN - set will insert one adc cycle rearm before sample, user need to increase one to sample_clock_number - 14 - 1 - read-write - - - SELRANGE_LDO - Defines the range for the LDO reference (vdd_soc) -selrange_ldo = 0: LDO reference dvdd or vref_ldo in range [0.81;0.99] -selrange_ldo = 1: LDO reference dvdd or vref_ldo in range [0.99;1.21] - 11 - 1 - read-write - - - ENLDO - set to enable adc LDO, need at least 20us for LDO to be stable. - 6 - 1 - read-write - - - ENADC - set to enable adc analog function. user need set it after LDO stable, or wait at least 20us after setting enldo, then set this bit. - 5 - 1 - read-write - - - RESETADC - set to 1 to reset adc analog; default high. - 4 - 1 - read-write - - - RESETCAL - set to 1 to reset calibration logic; default high. - 3 - 1 - read-write - - - STARTCAL - set to start the offset calibration cycle (Active H). user need to clear it after setting it. - 2 - 1 - read-write - - - LOADCAL - Signal that loads the offset calibration word into the internal registers (Active H) - 1 - 1 - read-write - - - - - ana_ctrl1 - No description available - 0x1204 - 32 - 0x00000000 - 0x000000C0 - - - SELRES - 11-12bit -10-10bit -01-8bit -00-6bit - 6 - 2 - read-write - - - - - ana_status - No description available - 0x1210 - 32 - 0x00000000 - 0x000000FF - - - CALON - Indicates if the ADC is in calibration mode (Active H). - 7 - 1 - read-write - - - CAL_OUT - No description available - 0 - 7 - read-write - - - - - - - ADC1 - ADC1 - ADC12 - 0xf0014000 - - - ADC2 - ADC2 - ADC12 - 0xf0018000 - - - ADC3 - ADC3 - ADC16 - 0xf001c000 - - 0x0 - 0x1464 - registers - - - - 12 - 0x4 - trg0a,trg0b,trg0c,trg1a,trg1b,trg1c,trg2a,trg2b,trg2c,trg3a,trg3b,trg3c - CONFIG[%s] - no description available - 0x0 - 32 - 0x00000000 - 0xFF3F3F3F - - - TRIG_LEN - length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 - 30 - 2 - write-only - - - INTEN3 - interrupt enable for 4th conversion - 29 - 1 - read-write - - - CHAN3 - channel number for 4th conversion - 24 - 5 - read-write - - - INTEN2 - interrupt enable for 3rd conversion - 21 - 1 - read-write - - - CHAN2 - channel number for 3rd conversion - 16 - 5 - read-write - - - INTEN1 - interrupt enable for 2nd conversion - 13 - 1 - read-write - - - CHAN1 - channel number for 2nd conversion - 8 - 5 - read-write - - - INTEN0 - interrupt enable for 1st conversion - 5 - 1 - read-write - - - CHAN0 - channel number for 1st conversion - 0 - 5 - read-write - - - - - trg_dma_addr - No description available - 0x30 - 32 - 0x00000000 - 0xFFFFFFFC - - - TRG_DMA_ADDR - buffer start address for trigger queue, 192byte total, 16 bytes for each trigger (4 bytes for each conversion) - 2 - 30 - read-write - - - - - trg_sw_sta - No description available - 0x34 - 32 - 0x00000000 - 0x0000001F - - - TRG_SW_STA - SW trigger start bit, HW will clear it after all conversions(up to 4) finished. SW should make sure it's 0 before set it. - 4 - 1 - read-write - - - TRIG_SW_INDEX - which trigger for the SW trigger -0 for trig0a, 1 for trig0b… -3 for trig1a, …11 for trig3c - 0 - 4 - read-write - - - - - 8 - 0x4 - chn0,chn1,chn2,chn3,chn4,chn5,chn6,chn7 - BUS_RESULT[%s] - no description available - 0x400 - 32 - 0x00000000 - 0x0001FFFF - - - VALID - set after conversion finished if wait_dis is set, cleared after software read. -The first time read with 0 will trigger one new conversion. -If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. -the result may not realtime if software read once and wait long time to read again - 16 - 1 - read-only - - - CHAN_RESULT - read this register will trigger one adc conversion. -If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result -If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long - 0 - 16 - read-only - - - - - buf_cfg0 - No description available - 0x500 - 32 - 0x00000000 - 0x00000001 - - - WAIT_DIS - set to disable read waiting, get result immediately but maybe not current conversion result. - 0 - 1 - read-write - - - - - seq_cfg0 - No description available - 0x800 - 32 - 0x00000000 - 0x80000F1F - - - CYCLE - current dma write cycle bit - 31 - 1 - read-only - - - SEQ_LEN - sequence queue length, 0 for one, 0xF for 16 - 8 - 4 - read-write - - - RESTART_EN - if set together with cont_en, HW will continue process the whole queue after trigger once. -If cont_en is 0, this bit is not used - 4 - 1 - read-write - - - CONT_EN - if set, HW will continue process the queue till end(seq_len) after trigger once - 3 - 1 - read-write - - - SW_TRIG - SW trigger, pulse signal, cleared by HW one cycle later - 2 - 1 - write-only - - - SW_TRIG_EN - set to enable SW trigger - 1 - 1 - read-write - - - HW_TRIG_EN - set to enable external HW trigger, only trigger on posedge - 0 - 1 - read-write - - - - - seq_dma_addr - No description available - 0x804 - 32 - 0x00000000 - 0xFFFFFFFC - - - TAR_ADDR - dma target address, should be 4-byte aligned - 2 - 30 - read-write - - - - - seq_dma_cfg - No description available - 0x80c - 32 - 0x00000000 - 0x0FFF3FFF - - - STOP_POS - if stop_en is set, SW is responsible to update this field to the next read point, HW should not write data to this point since it's not read out by SW yet - 16 - 12 - read-write - - - DMA_RST - set this bit will reset HW dma write pointer to seq_dma_addr, and set HW cycle bit to 1. dma is halted if this bit is set. -SW should clear all cycle bit in buffer to 0 before clear dma_rst - 13 - 1 - read-write - - - STOP_EN - set to stop dma if reach the stop_pos - 12 - 1 - read-write - - - BUF_LEN - dma buffer length, after write to (tar_addr[31:2]+buf_len)*4, the next dma address will be tar_addr[31:2]*4 -0 for 4byte; -0xFFF for 16kbyte. - 0 - 12 - read-write - - - - - 16 - 0x4 - cfg0,cfg1,cfg2,cfg3,cfg4,cfg5,cfg6,cfg7,cfg8,cfg9,cfg10,cfg11,cfg12,cfg13,cfg14,cfg15 - SEQ_QUE[%s] - no description available - 0x810 - 32 - 0x00000000 - 0x0000003F - - - SEQ_INT_EN - interrupt enable for current conversion - 5 - 1 - read-write - - - CHAN_NUM_4_0 - channel number for current conversion - 0 - 5 - read-write - - - - - 8 - 0x10 - chn0,chn1,chn2,chn3,chn4,chn5,chn6,chn7 - PRD_CFG[%s] - no description available - 0xc00 - - prd_cfg - No description available - 0x0 - 32 - 0x00000000 - 0x00001FFF - - - PRESCALE - 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx - 8 - 5 - read-write - - - PRD - conver period, with prescale. -Set to 0 means disable current channel - 0 - 8 - read-write - - - - - prd_thshd_cfg - No description available - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - THSHDH - threshold high, assert interrupt(if enabled) if result exceed high or low. - 16 - 16 - read-write - - - THSHDL - threshold low - 0 - 16 - read-write - - - - - prd_result - No description available - 0x8 - 32 - 0x00000000 - 0x0000FFFF - - - CHAN_RESULT - adc convert result, update after each valid conversion. -it may be updated period according to config, also may be updated due to other queue convert the same channel - 0 - 16 - read-only - - - - - - 8 - 0x4 - chn0,chn1,chn2,chn3,chn4,chn5,chn6,chn7 - SAMPLE_CFG[%s] - no description available - 0x1000 - 32 - 0x00000000 - 0x00000FFF - - - SAMPLE_CLOCK_NUMBER_SHIFT - shift for sample clock number - 9 - 3 - read-write - - - SAMPLE_CLOCK_NUMBER - sample clock number, base on clock_period, default one period - 0 - 9 - read-write - - - - - conv_cfg1 - No description available - 0x1104 - 32 - 0x00000000 - 0x000001FF - - - CONVERT_CLOCK_NUMBER - convert clock numbers, set to 21 (0x15) for 16bit mode, which means convert need 21 adc clock cycles(based on clock after divider); -user can use small value to get faster conversion, but less accuracy, need to config cov_end_cnt at adc16_config1 also. -Ex: use 200MHz bus clock for adc, set sample_clock_number to 4, sample_clock_number_shift to 0, covert_clk_number to 21 for 16bit mode, clock_divder to 3, then each ADC conversion(plus sample) need 25 cycles(50MHz). - 4 - 5 - read-write - - - CLOCK_DIVIDER - clock_period, N half clock cycle per half adc cycle -0 for same adc_clk and bus_clk, -1 for 1:2, -2 for 1:3, -... -15 for 1:16 -Note: set to 2 can genenerate 66.7MHz adc_clk at 200MHz bus_clk - 0 - 4 - read-write - - - - - adc_cfg0 - No description available - 0x1108 - 32 - 0x00000000 - 0xA0000001 - - - SEL_SYNC_AHB - set to 1 will enable sync AHB bus, to get better bus performance. -Adc_clk must to be set to same as bus clock at this mode - 31 - 1 - read-write - - - ADC_AHB_EN - set to 1 to enable ADC DMA to write data to soc memory bus, for trig queue and seq queue; - 29 - 1 - read-write - - - PORT3_REALTIME - set to enable trg queue stop other queues - 0 - 1 - read-write - - - - - int_sts - No description available - 0x1110 - 32 - 0x00000000 - 0xFFE0FFFF - - - TRIG_CMPT - interrupt for one trigger conversion complete if enabled - 31 - 1 - read-write - - - TRIG_SW_CFLCT - No description available - 30 - 1 - read-write - - - TRIG_HW_CFLCT - No description available - 29 - 1 - read-write - - - READ_CFLCT - read conflict interrupt, set if wait_dis is set, one conversion is in progress, SW read another channel - 28 - 1 - read-write - - - SEQ_SW_CFLCT - sequence queue conflict interrupt, set if HW or SW trigger received during conversion - 27 - 1 - read-write - - - SEQ_HW_CFLCT - No description available - 26 - 1 - read-write - - - SEQ_DMAABT - dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set - 25 - 1 - read-write - - - SEQ_CMPT - the whole sequence complete interrupt - 24 - 1 - read-write - - - SEQ_CVC - one conversion complete in seq_queue if related seq_int_en is set - 23 - 1 - read-write - - - DMA_FIFO_FULL - DMA fifo full interrupt, user need to check clock frequency if it's set. - 22 - 1 - read-write - - - AHB_ERR - set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr - 21 - 1 - read-write - - - WDOG - set if one chanel watch dog event triggered - 0 - 16 - read-write - - - - - int_en - No description available - 0x1114 - 32 - 0x00000000 - 0xFFE0FFFF - - - TRIG_CMPT - interrupt for one trigger conversion complete if enabled - 31 - 1 - read-write - - - TRIG_SW_CFLCT - No description available - 30 - 1 - read-write - - - TRIG_HW_CFLCT - No description available - 29 - 1 - read-write - - - READ_CFLCT - read conflict interrupt, set if wait_dis is set, one conversion is in progress, SW read another channel - 28 - 1 - read-write - - - SEQ_SW_CFLCT - sequence queue conflict interrupt, set if HW or SW trigger received during conversion - 27 - 1 - read-write - - - SEQ_HW_CFLCT - No description available - 26 - 1 - read-write - - - SEQ_DMAABT - dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set - 25 - 1 - read-write - - - SEQ_CMPT - the whole sequence complete interrupt - 24 - 1 - read-write - - - SEQ_CVC - one conversion complete in seq_queue if related seq_int_en is set - 23 - 1 - read-write - - - DMA_FIFO_FULL - DMA fifo full interrupt, user need to check clock frequency if it's set. - 22 - 1 - read-write - - - AHB_ERR - set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr - 21 - 1 - read-write - - - WDOG - set if one chanel watch dog event triggered - 0 - 16 - read-write - - - - - ana_ctrl0 - No description available - 0x1200 - 32 - 0x00000000 - 0x00001004 - - - ADC_CLK_ON - set to enable adc clock to analog, Software should set this bit before access to any adc16_* register. -MUST set clock_period to 0 or 1 for adc16 reg access - 12 - 1 - read-write - - - STARTCAL - set to start the offset calibration cycle (Active H). user need to clear it after setting it. - 2 - 1 - read-write - - - - - ana_status - No description available - 0x1210 - 32 - 0x00000000 - 0x00000080 - - - CALON - Indicates if the ADC is in calibration mode (Active H). - 7 - 1 - read-write - - - - - 34 - 0x2 - adc16_para00,adc16_para01,adc16_para02,adc16_para03,adc16_para04,adc16_para05,adc16_para06,adc16_para07,adc16_para08,adc16_para09,adc16_para10,adc16_para11,adc16_para12,adc16_para13,adc16_para14,adc16_para15,adc16_para16,adc16_para17,adc16_para18,adc16_para19,adc16_para20,adc16_para21,adc16_para22,adc16_para23,adc16_para24,adc16_para25,adc16_para26,adc16_para27,adc16_para28,adc16_para29,adc16_para30,adc16_para31,adc16_para32,adc16_para33 - ADC16_PARAMS[%s] - no description available - 0x1400 - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description available - 0 - 16 - read-write - - - - - adc16_config0 - No description available - 0x1444 - 32 - 0x00000000 - 0x03F07FFF - - - TEMPSNS_EN - set to enable temp sensor - 25 - 1 - read-write - - - REG_EN - set to enable regulator - 24 - 1 - read-write - - - BANDGAP_EN - set to enable bandgap. user should set reg_en and bandgap_en before use adc16. - 23 - 1 - read-write - - - CAL_AVG_CFG - for average the calibration result. -0- 1 loop; 1- 2 loops; 2- 4 loops; 3- 8 loops; -4- 16 loops; 5-32 loops; others reserved - 20 - 3 - read-write - - - PREEMPT_EN - set to enable preemption feature - 14 - 1 - read-write - - - CONV_PARAM - conversion parameter - 0 - 14 - read-write - - - - - adc16_config1 - No description available - 0x1460 - 32 - 0x00000000 - 0x00001F00 - - - COV_END_CNT - used for faster conversion, user can change it to get higher convert speed(but less accuracy). -should set to (21-convert_clock_number+1). - 8 - 5 - read-write - - - - - - - ACMP - ACMP - ACMP - 0xf0020000 - - 0x0 - 0x80 - registers - - - - 4 - 0x20 - chn0,chn1,chn2,chn3 - CHANNEL[%s] - no description available - 0x0 - - cfg - Configure Register - 0x0 - 32 - 0x00000000 - 0xFF7FFFFF - - - HYST - This bitfield configure the comparator hysteresis. -00: Hysteresis level 0 -01: Hysteresis level 1 -10: Hysteresis level 2 -11: Hysteresis level 3 - 30 - 2 - read-write - - - DACEN - This bit enable the comparator internal DAC -0: DAC disabled -1: DAC enabled - 29 - 1 - read-write - - - HPMODE - This bit enable the comparator high performance mode. -0: HP mode disabled -1: HP mode enabled - 28 - 1 - read-write - - - CMPEN - This bit enable the comparator. -0: ACMP disabled -1: ACMP enabled - 27 - 1 - read-write - - - MINSEL - PIN select, from pad_ai_acmp[7:1] and dac_out - 24 - 3 - read-write - - - PINSEL - MIN select, from pad_ai_acmp[7:1] and dac_out - 20 - 3 - read-write - - - CMPOEN - This bit enable the comparator output on pad. -0: ACMP output disabled -1: ACMP output enabled - 19 - 1 - read-write - - - FLTBYPS - This bit bypass the comparator output digital filter. -0: The ACMP output need pass digital filter -1: The ACMP output digital filter is bypassed. - 18 - 1 - read-write - - - WINEN - This bit enable the comparator window mode. -0: Window mode is disabled -1: Window mode is enabled - 17 - 1 - read-write - - - OPOL - The output polarity control bit. -0: The ACMP output remain un-changed. -1: The ACMP output is inverted. - 16 - 1 - read-write - - - FLTMODE - This bitfield define the ACMP output digital filter mode: -000-bypass -100-change immediately; -101-change after filter; -110-stalbe low; -111-stable high - 13 - 3 - read-write - - - SYNCEN - This bit enable the comparator output synchronization. -0: ACMP output not synchronized with ACMP clock. -1: ACMP output synchronized with ACMP clock. - 12 - 1 - read-write - - - FLTLEN - This bitfield define the ACMP output digital filter length. The unit is ACMP clock cycle. - 0 - 12 - read-write - - - - - daccfg - DAC configure register - 0x4 - 32 - 0x00000000 - 0x000000FF - - - DACCFG - 8bit DAC digital value output to analog block - 0 - 8 - read-write - - - - - sr - Status register - 0x10 - 32 - 0x00000000 - 0x00000003 - - - FEDGF - Output falling edge flag. Write 1 to clear this flag. - 1 - 1 - read-write - - - REDGF - Output rising edge flag. Write 1 to clear this flag. - 0 - 1 - read-write - - - - - irqen - Interrupt request enable register - 0x14 - 32 - 0x00000000 - 0x00000003 - - - FEDGEN - Output falling edge flag interrupt enable bit. - 1 - 1 - read-write - - - REDGEN - Output rising edge flag interrupt enable bit. - 0 - 1 - read-write - - - - - dmaen - DMA request enable register - 0x18 - 32 - 0x00000000 - 0x00000003 - - - FEDGEN - Output falling edge flag DMA request enable bit. - 1 - 1 - read-write - - - REDGEN - Output rising edge flag DMA request enable bit. - 0 - 1 - read-write - - - - - - - - SPI0 - SPI0 - SPI - 0xf0030000 - - 0x10 - 0x70 - registers - - - - TransFmt - Transfer Format Register - 0x10 - 32 - 0x00020780 - 0xFFFF1F9F - - - ADDRLEN - Address length in bytes -0x0: 1 byte -0x1: 2 bytes -0x2: 3 bytes -0x3: 4 bytes - 16 - 2 - read-write - - - DATALEN - The length of each data unit in bits -The actual bit number of a data unit is (DataLen + 1) - 8 - 5 - read-write - - - DATAMERGE - Enable Data Merge mode, which does automatic data split on write and data coalescing on read. -This bit only takes effect when DataLen = 0x7. Under Data Merge mode, each write to the Data Register will transmit all fourbytes of the write data; each read from the Data Register will retrieve four bytes of received data as a single word data. -When Data Merge mode is disabled, only the least (DataLen+1) significient bits of the Data Register are valid for read/write operations; no automatic data split/coalescing will be performed. - 7 - 1 - read-write - - - MOSIBIDIR - Bi-directional MOSI in regular (single) mode -0x0: MOSI is uni-directional signal in regular mode. -0x1: MOSI is bi-directional signal in regular mode. This bi-directional signal replaces the two - 4 - 1 - read-write - - - LSB - Transfer data with the least significant bit first -0x0: Most significant bit first -0x1: Least significant bit first - 3 - 1 - read-write - - - SLVMODE - SPI Master/Slave mode selection -0x0: Master mode -0x1: Slave mode - 2 - 1 - read-write - - - CPOL - SPI Clock Polarity -0x0: SCLK is LOW in the idle states -0x1: SCLK is HIGH in the idle states - 1 - 1 - read-write - - - CPHA - SPI Clock Phase -0x0: Sampling data at odd SCLK edges -0x1: Sampling data at even SCLK edges - 0 - 1 - read-write - - - - - TransCtrl - Transfer Control Register - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - SLVDATAONLY - Data-only mode (slave mode only) -0x0: Disable the data-only mode -0x1: Enable the data-only mode -Note: This mode only works in the uni-directional regular (single) mode so MOSIBiDir, DualQuad and TransMode should be set to 0. - 31 - 1 - read-write - - - CMDEN - SPI command phase enable (Master mode only) -0x0: Disable the command phase -0x1: Enable the command phase - 30 - 1 - read-write - - - ADDREN - SPI address phase enable (Master mode only) -0x0: Disable the address phase -0x1: Enable the address phase - 29 - 1 - read-write - - - ADDRFMT - SPI address phase format (Master mode only) -0x0: Address phase is the regular (single) mode -0x1: The format of the address phase is the same as the data phase (DualQuad). - 28 - 1 - read-write - - - TRANSMODE - Transfer mode -The transfer sequence could be -0x0: Write and read at the same time -0x1: Write only -0x2: Read only -0x3: Write, Read -0x4: Read, Write -0x5: Write, Dummy, Read -0x6: Read, Dummy, Write -0x7: None Data (must enable CmdEn or AddrEn in master mode) -0x8: Dummy, Write -0x9: Dummy, Read -0xa~0xf: Reserved - 24 - 4 - read-write - - - DUALQUAD - SPI data phase format -0x0: Regular (Single) mode -0x1: Dual I/O mode -0x2: Quad I/O mode -0x3: Reserved - 22 - 2 - read-write - - - TOKENEN - Token transfer enable (Master mode only) -Append a one-byte special token following the address phase for SPI read transfers. The value of the special token should be selected in TokenValue. -0x0: Disable the one-byte special token -0x1: Enable the one-byte special token - 21 - 1 - read-write - - - WRTRANCNT - Transfer count for write data -WrTranCnt indicates the number of units of data to be transmitted to the SPI bus from the Data Register. The actual transfer count is (WrTranCnt+1). -WrTranCnt only takes effect when TransMode is 0, 1, 3, 4, 5, 6 or 8. -The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. -For TransMode 0, WrTranCnt must be equal to RdTranCnt. - 12 - 9 - read-write - - - TOKENVALUE - Token value (Master mode only) -The value of the one-byte special token following the address phase for SPI read transfers. -0x0: token value = 0x00 -0x1: token value = 0x69 - 11 - 1 - read-write - - - DUMMYCNT - Dummy data count. The actual dummy count is (DummyCnt +1). -The number of dummy cycles on the SPI interface will be (DummyCnt+1)* ((DataLen+1)/SPI IO width) -The Data pins are put into the high impedance during the dummy data phase. -DummyCnt is only used for TransMode 5, 6, 8 and 9, which has dummy data phases. - 9 - 2 - read-write - - - RDTRANCNT - Transfer count for read data -RdTranCnt indicates the number of units of data to be received from SPI bus and stored to the Data Register. The actual received count is (RdTranCnt+1). -RdTransCnt only takes effect when TransMode is 0, 2, 3, 4, 5, 6 or 9. -The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. -For TransMode 0, WrTranCnt must equal RdTranCnt. - 0 - 9 - read-write - - - - - Cmd - Command Register - 0x24 - 32 - 0x00000000 - 0x000000FF - - - CMD - SPI Command - 0 - 8 - read-write - - - - - Addr - Address Register - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR - SPI Address -(Master mode only) - 0 - 32 - read-write - - - - - Data - Data Register - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - Data to transmit or the received data -For writes, data is enqueued to the TX FIFO. The least significant byte is always transmitted first. If the TX FIFO is full and the SPIActive bit of the status register is 1, the ready signal hready/pready will be deasserted to insert wait states to the transfer. -For reads, data is read and dequeued from the RX FIFO. The least significant byte is the first received byte. If the RX FIFO is empty and the SPIActive bit of the status register is 1, the ready signal hready/pready will be deasserted to insert wait states to the transfer. -The FIFOs decouple the speed of the SPI transfers and the software鈥檚 generation/consumption of data. When the TX FIFO is empty, SPI transfers will hold until more data is written to the TX FIFO; when the RX FIFO is full, SPI transfers will hold until there is more room in the RX FIFO. -If more data is written to the TX FIFO than the write transfer count (WrTranCnt), the remaining data will stay in the TX FIFO for the next transfer or until the TX FIFO is reset. - 0 - 32 - read-write - - - - - Ctrl - Control Register - 0x30 - 32 - 0x00000000 - 0x00FFFF1F - - - TXTHRES - Transmit (TX) FIFO Threshold -The TXFIFOInt interrupt or DMA request would be issued to replenish the TX FIFO when the TX data count is less than or equal to the TX FIFO threshold. - 16 - 8 - read-write - - - RXTHRES - Receive (RX) FIFO Threshold -The RXFIFOInt interrupt or DMA request would be issued for consuming the RX FIFO when the RX data count is more than or equal to the RX FIFO threshold. - 8 - 8 - read-write - - - TXDMAEN - TX DMA enable - 4 - 1 - read-write - - - RXDMAEN - RX DMA enable - 3 - 1 - read-write - - - TXFIFORST - Transmit FIFO reset -Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. - 2 - 1 - read-write - - - RXFIFORST - Receive FIFO reset -Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. - 1 - 1 - read-write - - - SPIRST - SPI reset -Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. - 0 - 1 - read-write - - - - - Status - Status Register - 0x34 - 32 - 0x00000000 - 0x33FFFF01 - - - TXNUM_7_6 - Number of valid entries in the Transmit FIFO - 28 - 2 - read-only - - - RXNUM_7_6 - Number of valid entries in the Receive FIFO - 24 - 2 - read-only - - - TXFULL - Transmit FIFO Full flag - 23 - 1 - read-only - - - TXEMPTY - Transmit FIFO Empty flag - 22 - 1 - read-only - - - TXNUM_5_0 - Number of valid entries in the Transmit FIFO - 16 - 6 - read-only - - - RXFULL - Receive FIFO Full flag - 15 - 1 - read-only - - - RXEMPTY - Receive FIFO Empty flag - 14 - 1 - read-only - - - RXNUM_5_0 - Number of valid entries in the Receive FIFO - 8 - 6 - read-only - - - SPIACTIVE - SPI register programming is in progress. -In master mode, SPIActive becomes 1 after the SPI command register is written and becomes 0 after the transfer is finished. -In slave mode, SPIActive becomes 1 after the SPI CS signal is asserted and becomes 0 after the SPI CS signal is deasserted. -Note that due to clock synchronization, it may take at most two spi_clock cycles for SPIActive to change when the corresponding condition happens. -Note this bit stays 0 when Direct IO Control or the memory-mapped interface is used. - 0 - 1 - read-only - - - - - IntrEn - Interrupt Enable Register - 0x38 - 32 - 0x00000000 - 0x0000003F - - - SLVCMDEN - Enable the Slave Command Interrupt. -Control whether interrupts are triggered whenever slave commands are received. -(Slave mode only) - 5 - 1 - read-write - - - ENDINTEN - Enable the End of SPI Transfer interrupt. -Control whether interrupts are triggered when SPI transfers end. -(In slave mode, end of read status transaction doesn鈥檛 trigger this interrupt.) - 4 - 1 - read-write - - - TXFIFOINTEN - Enable the SPI Transmit FIFO Threshold interrupt. -Control whether interrupts are triggered when the valid entries are less than or equal to the TX FIFO threshold. - 3 - 1 - read-write - - - RXFIFOINTEN - Enable the SPI Receive FIFO Threshold interrupt. -Control whether interrupts are triggered when the valid entries are greater than or equal to the RX FIFO threshold. - 2 - 1 - read-write - - - TXFIFOURINTEN - Enable the SPI Transmit FIFO Underrun interrupt. -Control whether interrupts are triggered when the Transmit FIFO run out of data. -(Slave mode only) - 1 - 1 - read-write - - - RXFIFOORINTEN - Enable the SPI Receive FIFO Overrun interrupt. -Control whether interrupts are triggered when the Receive FIFO overflows. -(Slave mode only) - 0 - 1 - read-write - - - - - IntrSt - Interrupt Status Register - 0x3c - 32 - 0x00000000 - 0x0000003F - - - SLVCMDINT - Slave Command Interrupt. -This bit is set when Slave Command interrupts occur. -(Slave mode only) - 5 - 1 - write-only - - - ENDINT - End of SPI Transfer interrupt. -This bit is set when End of SPI Transfer interrupts occur. - 4 - 1 - write-only - - - TXFIFOINT - TX FIFO Threshold interrupt. -This bit is set when TX FIFO Threshold interrupts occur. - 3 - 1 - write-only - - - RXFIFOINT - RX FIFO Threshold interrupt. -This bit is set when RX FIFO Threshold interrupts occur. - 2 - 1 - write-only - - - TXFIFOURINT - TX FIFO Underrun interrupt. -This bit is set when TX FIFO Underrun interrupts occur. -(Slave mode only) - 1 - 1 - write-only - - - RXFIFOORINT - RX FIFO Overrun interrupt. -This bit is set when RX FIFO Overrun interrupts occur. -(Slave mode only) - 0 - 1 - write-only - - - - - Timing - Interface Timing Register - 0x40 - 32 - 0x00000000 - 0x00003FFF - - - CS2SCLK - The minimum time between the edges of SPI CS and the edges of SCLK. -SCLK_period * (CS2SCLK + 1) / 2 - 12 - 2 - read-write - - - CSHT - The minimum time that SPI CS should stay HIGH. -SCLK_period * (CSHT + 1) / 2 - 8 - 4 - read-write - - - SCLK_DIV - The clock frequency ratio between the clock source and SPI interface SCLK. -SCLK_period = ((SCLK_DIV + 1) * 2) * (Period of the SPI clock source) -The SCLK_DIV value 0xff is a special value which indicates that the SCLK frequency should be the same as the spi_clock frequency. - 0 - 8 - read-write - - - - - SlvSt - Slave Status Register - 0x60 - 32 - 0x00000000 - 0x0007FFFF - - - UNDERRUN - Data underrun occurs in the last transaction - 18 - 1 - write-only - - - OVERRUN - Data overrun occurs in the last transaction - 17 - 1 - read-write - - - READY - Set this bit to indicate that the ATCSPI200 is ready for data transaction. -When an SPI transaction other than slave status-reading command ends, this bit will be cleared to 0. - 16 - 1 - read-write - - - USR_STATUS - User defined status flags - 0 - 16 - read-write - - - - - SlvDataCnt - Slave Data Count Register - 0x64 - 32 - 0x00000000 - 0x03FF03FF - - - WCNT - Slave transmitted data count - 16 - 10 - read-only - - - RCNT - Slave received data count - 0 - 10 - read-only - - - - - Config - Configuration Register - 0x7c - 32 - 0x00004311 - 0x000043FF - - - SLAVE - Support for SPI Slave mode - 14 - 1 - read-only - - - QUADSPI - Support for Quad I/O SPI - 9 - 1 - read-only - - - DUALSPI - Support for Dual I/O SPI - 8 - 1 - read-only - - - TXFIFOSIZE - Depth of TX FIFO -0x0: 2 words -0x1: 4 words -0x2: 8 words -0x3: 16 words -0x4: 32 words -0x5: 64 words -0x6: 128 words - 4 - 4 - read-only - - - RXFIFOSIZE - Depth of RX FIFO -0x0: 2 words -0x1: 4 words -0x2: 8 words -0x3: 16 words -0x4: 32 words -0x5: 64 words -0x6: 128 words - 0 - 4 - read-only - - - - - - - SPI1 - SPI1 - SPI - 0xf0034000 - - - SPI2 - SPI2 - SPI - 0xf0038000 - - - SPI3 - SPI3 - SPI - 0xf003c000 - - - UART0 - UART0 - UART - 0xf0040000 - - 0x10 - 0x30 - registers - - - - Cfg - Configuration Register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - FIFOSIZE - The depth of RXFIFO and TXFIFO -0: 16-byte FIFO -1: 32-byte FIFO -2: 64-byte FIFO -3: 128-byte FIFO - 0 - 2 - read-only - - - - - OSCR - Over Sample Control Register - 0x14 - 32 - 0x00000010 - 0x0000001F - - - OSC - Over-sample control -The value must be an even number; any odd value -writes to this field will be converted to an even value. -OSC=0: reserved -OSC<=8: The over-sample ratio is 8 -8 < OSC< 32: The over sample ratio is OSC - 0 - 5 - read-write - - - - - RBR - Receiver Buffer Register (when DLAB = 0) - UNION_20 - 0x20 - 32 - 0x00000000 - 0x000000FF - - - RBR - Receive data read port - 0 - 8 - read-only - - - - - THR - Transmitter Holding Register (when DLAB = 0) - UNION_20 - 0x20 - 32 - 0x00000000 - 0x000000FF - - - THR - Transmit data write port - 0 - 8 - write-only - - - - - DLL - Divisor Latch LSB (when DLAB = 1) - UNION_20 - 0x20 - 32 - 0x00000001 - 0x000000FF - - - DLL - Least significant byte of the Divisor Latch - 0 - 8 - read-write - - - - - IER - Interrupt Enable Register (when DLAB = 0) - UNION_24 - 0x24 - 32 - 0x00000000 - 0x0000000F - - - EMSI - Enable modem status interrupt -The interrupt asserts when the status of one of the -following occurs: -The status of modem_rin, modem_dcdn, -modem_dsrn or modem_ctsn (If the auto-cts mode is -disabled) has been changed. -If the auto-cts mode is enabled (MCR bit4 (AFE) = 1), -modem_ctsn would be used to control the transmitter. - 3 - 1 - read-write - - - ELSI - Enable receiver line status interrupt - 2 - 1 - read-write - - - ETHEI - Enable transmitter holding register interrupt - 1 - 1 - read-write - - - ERBI - Enable received data available interrupt and the -character timeout interrupt -0: Disable -1: Enable - 0 - 1 - read-write - - - - - DLM - Divisor Latch MSB (when DLAB = 1) - UNION_24 - 0x24 - 32 - 0x00000000 - 0x000000FF - - - DLM - Most significant byte of the Divisor Latch - 0 - 8 - read-write - - - - - IIR - Interrupt Identification Register - UNION_28 - 0x28 - 32 - 0x00000001 - 0x000000CF - - - FIFOED - FIFOs enabled -These two bits are 1 when bit 0 of the FIFO Control -Register (FIFOE) is set to 1. - 6 - 2 - read-only - - - INTRID - Interrupt ID, see IIR2 for detail decoding - 0 - 4 - read-only - - - - - FCR - FIFO Control Register - UNION_28 - 0x28 - 32 - 0x00000000 - 0x000000FF - - - RFIFOT - Receiver FIFO trigger level - 6 - 2 - write-only - - - TFIFOT - Transmitter FIFO trigger level - 4 - 2 - write-only - - - DMAE - DMA enable -0: Disable -1: Enable - 3 - 1 - write-only - - - TFIFORST - Transmitter FIFO reset -Write 1 to clear all bytes in the TXFIFO and resets its -counter. The Transmitter Shift Register is not cleared. -This bit will automatically be cleared. - 2 - 1 - write-only - - - RFIFORST - Receiver FIFO reset -Write 1 to clear all bytes in the RXFIFO and resets its -counter. The Receiver Shift Register is not cleared. -This bit will automatically be cleared. - 1 - 1 - write-only - - - FIFOE - FIFO enable -Write 1 to enable both the transmitter and receiver -FIFOs. -The FIFOs are reset when the value of this bit toggles. - 0 - 1 - write-only - - - - - LCR - Line Control Register - 0x2c - 32 - 0x00000000 - 0x000000FF - - - DLAB - Divisor latch access bit - 7 - 1 - read-write - - - BC - Break control - 6 - 1 - read-write - - - SPS - Stick parity -1: Parity bit is constant 0 or 1, depending on bit4 (EPS). -0: Disable the sticky bit parity. - 5 - 1 - read-write - - - EPS - Even parity select -1: Even parity (an even number of logic-1 is in the data -and parity bits) -0: Old parity. - 4 - 1 - read-write - - - PEN - Parity enable -When this bit is set, a parity bit is generated in -transmitted data before the first STOP bit and the parity -bit would be checked for the received data. - 3 - 1 - read-write - - - STB - Number of STOP bits -0: 1 bits -1: The number of STOP bit is based on the WLS setting -When WLS = 0, STOP bit is 1.5 bits -When WLS = 1, 2, 3, STOP bit is 2 bits - 2 - 1 - read-write - - - WLS - Word length setting -0: 5 bits -1: 6 bits -2: 7 bits -3: 8 bits - 0 - 2 - read-write - - - - - MCR - Modem Control Register ( - 0x30 - 32 - 0x00000000 - 0x00000032 - - - AFE - Auto flow control enable -0: Disable -1: The auto-CTS and auto-RTS setting is based on the -RTS bit setting: -When RTS = 0, auto-CTS only -When RTS = 1, auto-CTS and auto-RTS - 5 - 1 - read-write - - - LOOP - Enable loopback mode -0: Disable -1: Enable - 4 - 1 - read-write - - - RTS - Request to send -This bit controls the modem_rtsn output. -0: The modem_rtsn output signal will be driven HIGH -1: The modem_rtsn output signal will be driven LOW - 1 - 1 - read-write - - - - - LSR - Line Status Register - 0x34 - 32 - 0x00000000 - 0x000000FF - - - ERRF - Error in RXFIFO -In the FIFO mode, this bit is set when there is at least -one parity error, framing error, or line break -associated with data in the RXFIFO. It is cleared when -this register is read and there is no more error for the -rest of data in the RXFIFO. - 7 - 1 - read-only - - - TEMT - Transmitter empty -This bit is 1 when the THR (TXFIFO in the FIFO -mode) and the Transmitter Shift Register (TSR) are -both empty. Otherwise, it is zero. - 6 - 1 - read-only - - - THRE - Transmitter Holding Register empty -This bit is 1 when the THR (TXFIFO in the FIFO -mode) is empty. Otherwise, it is zero. -If the THRE interrupt is enabled, an interrupt is -triggered when THRE becomes 1. - 5 - 1 - read-only - - - LBREAK - Line break -This bit is set when the uart_sin input signal was held -LOWfor longer than the time for a full-word -transmission. A full-word transmission is the -transmission of the START, data, parity, and STOP -bits. It is cleared when this register is read. -In the FIFO mode, this bit indicates the line break for -the received data at the top of the RXFIFO. - 4 - 1 - read-only - - - FE - Framing error -This bit is set when the received STOP bit is not -HIGH. It is cleared when this register is read. -In the FIFO mode, this bit indicates the framing error -for the received data at the top of the RXFIFO. - 3 - 1 - read-only - - - PE - Parity error -This bit is set when the received parity does not match -with the parity selected in the LCR[5:4]. It is cleared -when this register is read. -In the FIFO mode, this bit indicates the parity error -for the received data at the top of the RXFIFO. - 2 - 1 - read-only - - - OE - Overrun error -This bit indicates that data in the Receiver Buffer -Register (RBR) is overrun. - 1 - 1 - read-only - - - DR - Data ready. -This bit is set when there are incoming received data -in the Receiver Buffer Register (RBR). It is cleared -when all of the received data are read. - 0 - 1 - read-only - - - - - MSR - Modem Status Register - 0x38 - 32 - 0x00000000 - 0x00000011 - - - CTS - Clear to send -0: The modem_ctsn input signal is HIGH. -1: The modem_ctsn input signal is LOW. - 4 - 1 - read-only - - - DCTS - Delta clear to send -This bit is set when the state of the modem_ctsn input -signal has been changed since the last time this -register is read. - 0 - 1 - read-only - - - - - GPR - GPR Register - 0x3c - 32 - 0x00000000 - 0x000000FF - - - DATA - A one-byte storage register - 0 - 8 - read-write - - - - - - - UART1 - UART1 - UART - 0xf0044000 - - - UART2 - UART2 - UART - 0xf0048000 - - - UART3 - UART3 - UART - 0xf004c000 - - - UART4 - UART4 - UART - 0xf0050000 - - - UART5 - UART5 - UART - 0xf0054000 - - - UART6 - UART6 - UART - 0xf0058000 - - - UART7 - UART7 - UART - 0xf005c000 - - - UART8 - UART8 - UART - 0xf0060000 - - - UART9 - UART9 - UART - 0xf0064000 - - - UART10 - UART10 - UART - 0xf0068000 - - - UART11 - UART11 - UART - 0xf006c000 - - - UART12 - UART12 - UART - 0xf0070000 - - - UART13 - UART13 - UART - 0xf0074000 - - - UART14 - UART14 - UART - 0xf0078000 - - - UART15 - UART15 - UART - 0xf007c000 - - - PUART - PUART - UART - 0xf40e4000 - - - CAN0 - CAN0 - CAN - 0xf0080000 - - 0x0 - 0xca - registers - - - - 20 - 0x4 - buf0,buf1,buf2,buf3,buf4,buf5,buf6,buf7,buf8,buf9,buf10,buf11,buf12,buf13,buf14,buf15,buf16,buf17,buf18,buf19 - RBUF[%s] - no description available - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - RBUF - receive buffer - 0 - 32 - read-write - - - - - 18 - 0x4 - buf0,buf1,buf2,buf3,buf4,buf5,buf6,buf7,buf8,buf9,buf10,buf11,buf12,buf13,buf14,buf15,buf16,buf17 - TBUF[%s] - no description available - 0x50 - 32 - 0x00000000 - 0xFFFFFFFF - - - TBUF - transmit buffer - 0 - 32 - read-write - - - - - 2 - 0x4 - wrd0,wrd1 - TTS[%s] - no description available - 0x98 - 32 - 0x00000000 - 0xFFFFFFFF - - - TTS_WRD0 - transmission time stamp, word 0, LSB 32bit - 0 - 32 - read-only - - - - - CMD_STA_CMD_CTRL - config, status, command and control bits - 0xa0 - 32 - 0x00900080 - 0xFBF3FFFF - - - SACK - Self-ACKnowledge -0 – no self-ACK -1 – self-ACK when LBME=1 - 31 - 1 - read-write - - - ROM - Receive buffer Overflow Mode -In case of a full RBUF when a new message is received, then ROM selects the following: -1 – The new message will not be stored. -0 – The oldest message will be overwritten. - 30 - 1 - read-write - - - ROV - Receive buffer OVerflow -1 – Overflow. At least one message is lost. -0 – No Overflow. -ROV is cleared by setting RREL=1. - 29 - 1 - read-only - - - RREL - Receive buffer RELease -The host controller has read the actual RB slot and releases it. Afterwards the CAN-CTRL -core points to the next RB slot. RSTAT gets updated. -1 – Release: The host has read the RB. -0 – No release - 28 - 1 - read-write - - - RBALL - Receive Buffer stores ALL data frames -0 – normal operation -1 – RB stores correct data frames as well as data frames with error - 27 - 1 - read-write - - - RSTAT - Receive buffer STATus -00 - empty -01 - > empty and < almost full (AFWL) -10 -  almost full (programmable threshold by AFWL) but not full and no overflow -11 - full (stays set in case of overflow – for overflow signaling see ROV) - 24 - 2 - read-only - - - FD_ISO - CAN FD ISO mode -0 - Bosch CAN FD (non-ISO) mode -1 - ISO CAN FD mode (ISO 11898-1:2015) -ISO CAN FD mode has a different CRC initialization value and an additional stuff bit count. -Both modes are incompatible and must not be mixed in one CAN network. -This bit has no impact to CAN 2.0B. -This bit is only writeable if RESET=1. - 23 - 1 - read-write - - - TSNEXT - Transmit buffer Secondary NEXT -0 - no action -1 - STB slot filled, select next slot. -After all frame bytes are written to the TBUF registers, the host controller has to set -TSNEXT to signal that this slot has been filled. Then the CAN-CTRL core connects the TBUF -registers to the next slot. Once a slot is marked as filled a transmission can be started -using TSONE or TSALL. -It is possible to set TSNEXT and TSONE or TSALL together in one write access. -TSNEXT has to be set by the host controller and is automatically reset by the CAN-CTRL -core immediately after it was set. -Setting TSNEXT is meaningless if TBSEL=0. In this case TSNEXT is ignored and -automatically cleared. It does not do any harm. -If all slots of the STB are filled, TSNEXT stays set until a slot becomes free. -TSNEXT has no meaning in TTCAN mode and is fixed to 0. - 22 - 1 - read-write - - - TSMODE - Transmit buffer Secondary operation MODE -0 - FIFO mode -1 - priority decision mode -In FIFO mode frames are transmitted in the order in that they are written into the STB. -In priority decision mode the frame with the highest priority in the STB is automatically -transmitted first. The ID of a frame is used for the priority decision. A lower ID means a -higher priority of a frame. A frame in the PTB has always the highest priority regardless of -the ID. -TSMODE shall be switched only if the STB if empty - 21 - 1 - read-write - - - TTTBM - TTCAN Transmit Buffer Mode -If TTEN=0 then TTTBM is ignored, otherwise the following is valid: -0 - separate PTB and STB, behavior defined by TSMODE -1 - full TTCAN support: buffer slots selectable by TBPTR and TTPTR -For event-driven CAN communication (TTEN=0), the system provides PTB and STB and -the behavior of the STB is defined by TSMODE. Then TTTBM is ignored. -For time-triggered CAN communication (TTEN=1) with full support of all features including -time-triggered transmissions, TTTBM=1 needs to be chosen. Then the all TB slots are -addressable using TTPTR and TBPTR. -For time-triggered CAN communication (TTEN=1) with only support of reception timestamps, TTTBM=0 can be chosen. Then the transmit buffer acts as in event-driven mode -and the behavior can be selected by TSMODE. -TTTBM shall be switched only if the TBUF is empty. - 20 - 1 - read-write - - - TSSTAT - Transmission Secondary STATus bits -If TTEN=0 or TTTBM=0: -00 – STB is empty -01 – STB is less than or equal to half full -10 – STB is more than half full -11 – STB is full -If the STB is disabled using STB_DISABLE, then TSSTAT=00. -If TTEN=1 and TTTBM=1: -00 – PTB and STB are empty -01 – PTB and STB are not empty and not full -11 – PTB and STB are full - 16 - 2 - read-only - - - TBSEL - Transmit Buffer Select -Selects the transmit buffer to be loaded with a message. Use the TBUF registers for -access. TBSEL needs to be stable all the time the TBUF registers are written and when -TSNEXT is set. -0 - PTB (high-priority buffer) -1 - STB -The bit will be reset to the hardware reset value if (TTEN=1 and TTTBM=1) - 15 - 1 - read-write - - - LOM - Listen Only Mode -0 - Disabled -1 - Enabled -LOM cannot be set if TPE, TSONE or TSALL is set. No transmission can be started if LOM -is enabled and LBME is disabled. -LOM=1 and LBME=0 disables all transmissions. -LOM=1 and LBME=1 disables the ACK for received frames and error frames, but enables -the transmission of own frames. - 14 - 1 - read-write - - - STBY - Transceiver Standby Mode -0 - Disabled -1 - Enabled -This register bit is connected to the output signal stby which can be used to control a -standby mode of a transceiver. -STBY cannot be set to 1 if TPE=1, TSONE=1 or TSALL=1. -If the host sets STBY to 0 then the host needs to wait for the time required by the -transceiver to start up before the host requests a new transmission. - 13 - 1 - read-write - - - TPE - Transmit Primary Enable -1 - Transmission enable for the message in the high-priority PTB -0 - No transmission for the PTB -If TPE is set, the message from the PTB will be transmitted at the next possible transmit -position. A started transmission from the STB will be completed before, but pending new -messages are delayed until the PTB message has been transmitted. -TPE stays set until the message has been transmitted successfully or it is aborted using -TPA. -The host controller can set TPE to 1 but can not reset it to 0. This would only be possible -using TPA and aborting the message. -The bit will be reset to the hardware reset value if RESET=1, STBY=1, (LOM=1 and -LBME=0) or (TTEN=1 and TTTBM=1). - 12 - 1 - read-write - - - TPA - Transmit Primary Abort -1 – Aborts a transmission from PTB which has been requested by TPE=1 but not -started yet. (The data bytes of the message remains in the PTB.) -0 – no abort -The bit has to be set by the host controller and will be reset by CAN-CTRL. Setting TPA -automatically de-asserts TPE. -The host controller can set TPA to 1 but can not reset it to 0. -During the short time while the CAN-CTRL core resets the bit, it cannot be set by the -host. -The bit will be reset to the hardware reset value if RESET=1 or (TTEN=1 and TTTBM=1). -TPA should not be set simultaneously with TPE. - 11 - 1 - read-write - - - TSONE - Transmit Secondary ONE frame -1 – Transmission enable of one in the STB. In FIFO mode this is the oldest message -and in priority mode this is the one with the highest priority. -TSONE in priority mode is difficult to handle, because it is not always clear which -message will be transmitted if new messages are written to the STB meanwhile. -The controller starts the transmission as soon as the bus becomes vacant and -no request of the PTB (bit TPE) is pending. -0 – No transmission for the STB. -TSONE stays set until the message has been transmitted successfully or it is aborted -using TSA. -The host controller can set TSONE to 1 but can not reset it to 0. This would only be -possible using TSA and aborting the message. -The bit will be reset to the hardware reset value if RESET=1, STBY=1, (LOM=1 and -LBME=0) or (TTEN=1 and TTTBM=1). - 10 - 1 - read-write - - - TSALL - Transmit Secondary ALL frames -1 – Transmission enable of all messages in the STB. -The controller starts the transmission as soon as the bus becomes vacant and -no request of the PTB (bit TPE) is pending. -0 – No transmission for the STB. -TSALL stays set until all messages have been transmitted successfully or they are aborted -using TSA. -The host controller can set TSALL to 1 but can not reset it to 0. This would only be -possible using TSA and aborting the messages. -The bit will be reset to the hardware reset value if RESET=1, STBY=1, (LOM=1 and -LBME=0) or (TTEN=1 and TTTBM=1). -If during a transmission the STB is loaded with a new frame then the new frame will be -transmitted too. In other words: a transmission initiated by TSALL is finished when the -STB becomes empty. - 9 - 1 - read-write - - - TSA - Transmit Secondary Abort -1 – Aborts a transmission from STB which has been requested but not started yet. -For a TSONE transmission, only one frame is aborted while for a TSALL -Transmission, all frames are aborted. -One or all message slots will be released which updates TSSTAT. -All aborted messages are lost because they are not accessible any more. -If in priority mode a TSONE transmission is aborted, then it is not clear which -frame will be aborted if new frames are written to the STB meanwhile. -0 – no abort -The bit has to be set by the host controller and will be reset by CAN-CTRL. Setting TSA,automatically de-asserts TSONE or TSALL respectively. -The host controller can set TSA to 1 but can not reset it to 0. -The bit will be reset to the hardware reset value if RESET=1. -TSA should not be set simultaneously with TSONE or TSALL. - 8 - 1 - read-write - - - RESET - RESET request bit -1 - The host controller performs a local reset of CAN-CTRL. -0 - no local reset of CAN-CTRLThe some register (e.g for node configuration) can only be modified if RESET=1. -Bit RESET forces several components to a reset state. -RESET is automatically set if the node enters “bus off” state. -Note that a CAN node will participate in CAN communication after RESET is switched to 0after 11 CAN bit times. -This delay is required by the CAN standard (bus idle time).If RESET is set to 1 and immediately set to 0, then it takes some time until RESET can beread as 0 and becomes inactive. -The reason is clock domain crossing from host to CAN clockdomain. RESET is held active as long as needed depending on the relation between host andCAN clock. - 7 - 1 - read-write - - - LBME - Loop Back Mode, External -0 - Disabled -1 - EnabledLBME should not be enabled while a transmission is active - 6 - 1 - read-write - - - LBMI - Loop Back Mode, Internal -0 - Disabled1 - EnabledLBMI should not be enabled while a transmission is active. - 5 - 1 - read-write - - - TPSS - Transmission Primary Single Shot mode for PTB -0 - Disabled -1 - Enabled - 4 - 1 - read-write - - - TSSS - Transmission Secondary Single Shot mode for STB -0 - Disabled -1 - Enabled - 3 - 1 - read-write - - - RACTIVE - Reception ACTIVE (Receive Status bit) -1 - The controller is currently receiving a frame. -0 - No receive activity. - 2 - 1 - read-only - - - TACTIVE - Transmission ACTIVE (Transmit Status bit) -1 - The controller is currently transmitting a frame. -0 - No transmit activity. - 1 - 1 - read-only - - - BUSOFF - Bus Off (Bus Status bit) -1 - The controller status is “bus off”. -0 - The controller status is “bus on”. -Writing a 1 to BUSOFF will reset TECNT and RECNT. This should be done only for debugging. -See Chapter 3.9.10.6 for details. - 0 - 1 - read-write - - - - - RTIE - Receive and Transmit Interrupt Enable Register RTIE - 0xa4 - 8 - 0xFE - 0xFF - - - RIE - Receive Interrupt Enable -0 – Disabled, 1 – Enabled - 7 - 1 - read-write - - - ROIE - RB Overrun Interrupt Enable -0 – Disabled, 1 – Enabled - 6 - 1 - read-write - - - RFIE - RB Full Interrupt Enable -0 – Disabled, 1 – Enabled - 5 - 1 - read-write - - - RAFIE - RB Almost Full Interrupt Enable -0 – Disabled, 1 – Enabled - 4 - 1 - read-write - - - TPIE - Transmission Primary Interrupt Enable -0 – Disabled, 1 – Enabled - 3 - 1 - read-write - - - TSIE - Transmission Secondary Interrupt Enable -0 – Disabled, 1 – Enabled - 2 - 1 - read-write - - - EIE - Error Interrupt Enable -0 – Disabled, 1 – Enabled - 1 - 1 - read-write - - - TSFF - If TTEN=0 or TTTBM=0: Transmit Secondary buffer Full Flag -1 - The STB is filled with the maximal number of messages. -0 - The STB is not filled with the maximal number of messages. -If the STB is disabled using STB_DISABLE, then TSFF=0. -If TTEN=1 and TTTBM=1: Transmit buffer Slot Full Flag -1 - The buffer slot selected by TBPTR is filled. -0 - The buffer slot selected by TBPTR is empty. - 0 - 1 - read-only - - - - - RTIF - Receive and Transmit Interrupt Flag Register RTIF (0xa5) - 0xa5 - 8 - 0x00 - 0xFF - - - RIF - Receive Interrupt Flag -1 - Data or a remote frame has been received and is available in the receive buffer. -0 - No frame has been received. - 7 - 1 - write-only - - - ROIF - RB Overrun Interrupt Flag -1 - At least one received message has been overwritten in the RB. -0 - No RB overwritten. -In case of an overrun both ROIF and RFIF will be set. - 6 - 1 - write-only - - - RFIF - RB Full Interrupt Flag -1 - All RBs are full. If no RB will be released until the next valid message is received, -the oldest message will be lost. -0 - The RB FIFO is not full. - 5 - 1 - write-only - - - RAFIF - RB Almost Full Interrupt Flag -1 - number of filled RB slots >= AFWL_i -0 - number of filled RB slots < AFWL_i - 4 - 1 - write-only - - - TPIF - Transmission Primary Interrupt Flag -1 - The requested transmission of the PTB has been successfully completed. -0 - No transmission of the PTB has been completed. -In TTCAN mode, TPIF will never be set. Then only TSIF is valid. - 3 - 1 - write-only - - - TSIF - Transmission Secondary Interrupt Flag -1 - The requested transmission of the STB has been successfully completed. -0 - No transmission of the STB has been completed successfully. -In TTCAN mode TSIF will signal all successful transmissions, regardless of storage location of -the message. - 2 - 1 - write-only - - - EIF - Error Interrupt Flag -1 - The border of the error warning limit has been crossed in either direction, -or the BUSOFF bit has been changed in either direction. -0 - There has been no change. - 1 - 1 - write-only - - - AIF - Abort Interrupt Flag -1 - After setting TPA or TSA the appropriated message(s) have been aborted. -It is recommended to not set both TPA and TSA simultaneously because both -source AIF. -0 - No abort has been executed. -The AIF does not have an associated enable register. - 0 - 1 - write-only - - - - - ERRINT - ERRor INTerrupt Enable and Flag Register ERRINT - 0xa6 - 8 - 0x00 - 0xFF - - - EWARN - Error WARNing limit reached -1 - One of the error counters RECNT or TECNT is equal or bigger than EWL0 - The values in both counters are less than EWL. - 7 - 1 - read-only - - - EPASS - Error Passive mode active -0 - not active (node is error active) -1 - active (node is error passive) - 6 - 1 - read-only - - - EPIE - Error Passive Interrupt Enable - 5 - 1 - read-write - - - EPIF - Error Passive Interrupt Flag. EPIF will be activated if the error status changes from error -active to error passive or vice versa and if this interrupt is enabled. - 4 - 1 - write-only - - - ALIE - Arbitration Lost Interrupt Enable - 3 - 1 - read-write - - - ALIF - Arbitration Lost Interrupt Flag - 2 - 1 - write-only - - - BEIE - Bus Error Interrupt Enable - 1 - 1 - read-write - - - BEIF - Bus Error Interrupt Flag - 0 - 1 - write-only - - - - - LIMIT - Warning Limits Register LIMIT - 0xa7 - 8 - 0x1B - 0xFF - - - AFWL - receive buffer Almost Full Warning Limit -AFWL defines the internal warning limit AFWL_i with being the number of availableRB slots. -AFWL_i is compared to the number of filled RB slots and triggers RAFIF if equal. Thevalid range of . -AFWL = 0 is meaningless and automatically treated as 0x1. (Note that AFWL is meant in this rule and not AFWL_i.) -AFWL_i > nRB is meaningless and automatically treated as nRB. -AFWL_i = nRB is a valid value, but note that RFIF also exists. - 4 - 4 - read-write - - - EWL - Programmable Error Warning Limit = (EWL+1)*8. Possible Limit values: 8, 16, … 128. -The value of EWL controls EIF. - 0 - 4 - read-write - - - - - S_PRESC - Bit Timing Register(Slow Speed) - 0xa8 - 32 - 0x01020203 - 0xFF7F7FFF - - - S_PRESC - Prescaler (slow speed) -The prescaler divides the system clock to get the time quanta clock tq_clk.Valid range PRESC=[0x00, 0xff] results in divider values 1 to 256. - 24 - 8 - read-write - - - S_SJW - Synchronization Jump Width (slow speed) -The Synchronization Jump Width is the maximum time forshortening or lengthening the Bit Time for resynchronization, where TQ is a timequanta. - 16 - 7 - read-write - - - S_SEG_2 - Bit Timing Segment 2 (slow speed) -Time after the sample point. - 8 - 7 - read-write - - - S_SEG_1 - Bit Timing Segment 1 (slow speed) -The sample point will be set to after start of bit time. - 0 - 8 - read-write - - - - - F_PRESC - Bit Timing Register(Fast Speed) - 0xac - 32 - 0x01020203 - 0xFF0F0F0F - - - F_PRESC - Prescaler (fast speed) -The prescaler divides the system clock to get the time quanta clock tq_clk.Valid range PRESC=[0x00, 0xff] results in divider values 1 to 256. - 24 - 8 - read-write - - - F_SJW - Synchronization Jump Width (fast speed) -The Synchronization Jump Width is the maximum time forshortening or lengthening the Bit Time for resynchronization, where TQ is a timequanta. - 16 - 4 - read-write - - - F_SEG_2 - Bit Timing Segment 2 (fast speed) -Time after the sample point - 8 - 4 - read-write - - - F_SEG_1 - Bit Timing Segment 1 (fast speed) -The sample point will be set to after start of bit time. - 0 - 4 - read-write - - - - - EALCAP - Error and Arbitration Lost Capture Register EALCAP - 0xb0 - 8 - 0x00 - 0xFF - - - KOER - Kind Of ERror (Error code) -000 - no error -001 - BIT ERROR -010 - FORM ERROR -011 - STUFF ERROR -100 - ACKNOWLEDGEMENT ERROR -101 - CRC ERROR -110 - OTHER ERROR(dominant bits after own error flag, received active Error Flag too long,dominant bit during Passive-Error-Flag after ACK error) -111 - not used -KOER is updated with each new error. Therefore it stays untouched when frames aresuccessfully transmitted or received. - 5 - 3 - read-only - - - ALC - Arbitration Lost Capture (bit position in the frame where the arbitration has been lost) - 0 - 5 - read-only - - - - - TDC - Transmitter Delay Compensation Register TDC - 0xb1 - 8 - 0x00 - 0xFF - - - TDCEN - Transmitter Delay Compensation ENable -TDC will be activated during the data phase of a CAN FD frame if BRS is active if TDCEN=1. - 7 - 1 - read-write - - - SSPOFF - Secondary Sample Point OFFset -The transmitter delay plus SSPOFF defines the time of the secondary sample point for TDC. -SSPOFF is given as a number of TQ. - 0 - 7 - read-write - - - - - RECNT - Error Counter Registers RECNT - 0xb2 - 8 - 0x00 - 0xFF - - - RECNT - Receive Error CouNT (number of errors during reception) -RECNT is incremented and decremented as defined in the CAN specification. -RECNT does not overflow. -If TXB=1, then the error counters are frozen. - 0 - 8 - read-only - - - - - TECNT - Error Counter Registers TECNT - 0xb3 - 8 - 0x00 - 0xFF - - - TECNT - Transmit Error CouNT (number of errors during transmission) -TECNT is incremented and decremented as defined in the CAN specification. -In case of the “bus off state” TECNT may overflow. -If TXB=1, then the error counters are frozen. - 0 - 8 - read-only - - - - - ACFCTRL - Acceptance Filter Control Register ACFCTRL - 0xb4 - 8 - 0x00 - 0x2F - - - SELMASK - SELect acceptance MASK -0 - Registers ACF_x point to acceptance code -1 - Registers ACF_x point to acceptance mask. -ACFADR selects one specific acceptance filter. - 5 - 1 - read-write - - - ACFADR - acceptance filter address -ACFADR points to a specific acceptance filter. -The selected filter is accessible using theregisters ACF_x. -Bit SELMASK selects between acceptance code and mask for theselected acceptance filter. -A value of ACFADR>ACF_NUMBER-1 is meaningless and automatically treated as value ACF_NUMBER-1. -ACF_NUMBER = 16. - 0 - 4 - read-write - - - - - TIMECFG - CiA 603 Time-Stamping TIMECFG - 0xb5 - 8 - 0x00 - 0x03 - - - TIMEPOS - TIME-stamping POSition -0 – SOF1 – EOF (see Chapter 7)TIMEPOS can only be changed if TIMEEN=0, but it is possible to modify TIMPOS withthe same write access that sets TIMEEN=1. - 1 - 1 - read-write - - - TIMEEN - TIME-stamping ENable -0 – disabled -1 – enabled - 0 - 1 - read-write - - - - - ACF_EN - Acceptance Filter Enable ACF_EN - 0xb6 - 16 - 0x0000 - 0xFFFF - - - ACF_EN - Acceptance filter Enable -1 - acceptance filter enabled -0 - acceptance filter disable -Each acceptance filter (AMASK / ACODE) can be individually enabled or disabled. -Disabled filters reject a message. Only enabled filters can accept a message if the -appropriate AMASK / ACODE configuration matches. - 0 - 16 - read-write - - - - - ACF - Acceptance CODE ACODE or ACMASK - 0xb8 - 32 - 0x00000000 - 0x7FFFFFFF - - - AIDEE - Acceptance mask IDE bit check enable -1 - acceptance filter accepts either standard or extended as defined by AIDE -0 - acceptance filter accepts both standard or extended frames -Only filter 0 is affected by the power-on reset. All other filters stay uninitialized. - 30 - 1 - read-write - - - AIDE - Acceptance mask IDE bit value -If AIDEE=1 then: -1 - acceptance filter accepts only extended frames -0 - acceptance filter accepts only standard frames -Only filter 0 is affected by the power-on reset. All other filters stay uninitialized. - 29 - 1 - read-write - - - CODE_MASK - Acceptance CODE -1 - ACC bit value to compare with ID bit of the received message -0 - ACC bit value to compare with ID bit of the received message -ACODE_x(10:0) will be used for extended frames. -ACODE_x(28:0) will be used for extended frames. -Only filter 0 is affected by the power-on reset. -Acceptance MASK(if SELMASK ==1 ) -1 - acceptance check for these bits of receive identifier disabled -0 - acceptance check for these bits of receive identifier enable -AMASK_x(10:0) will be used for extended frames. -AMASK_x(28:0) will be used for extended frames. -Disabled bits result in accepting the message. Therefore the default configuration after -reset for filter 0 accepts all messages. -Only filter 0 is affected by the power-on reset. - 0 - 29 - read-write - - - - - VER - Version Information VER - 0xbc - 16 - 0x0000 - 0xFFFF - - - VERSION - Version of CAN-CTRL, given as decimal value. VER_1 holds the major version and -VER_0 the minor version.Example: version 5x16N00S00 is represented by VER_1=5 and VER_0=16 - 0 - 16 - read-write - - - - - TBSLOT - TTCAN: TB Slot Pointer TBSLOT - 0xbe - 8 - 0x00 - 0xFF - - - TBE - set TB slot to “Empty” -1 - slot selected by TBPTR shall be marked as “empty” -0 - no actionTBE is automatically reset to 0 as soon as the slot is marked as empty and TSFF=0. -If atransmission from this slot is active, then TBE stays set as long as either the transmission completes or after a transmission error or arbitration loss the - transmissionis not active any more. -If both TBF and TBE are set, then TBE wins - 7 - 1 - read-write - - - TBF - set TB slot to “Filled” -1 - slot selected by TBPTR shall be marked as “filled” -0 - no actionTBF is automatically reset to 0 as soon as the slot is marked as filled and TSFF=1. -If both TBF and TBE are set, then TBE wins. - 6 - 1 - read-write - - - TBPTR - Pointer to a TB message slot. -0x00 - Pointer to the PTB -others - Pointer to a slot in the STB -The message slot pointed to by TBPTR is readable / writable using the TBUF registers. -Write access is only possible if TSFF=0. -Setting TBF to 1 marks the selected slot asfilled and setting TBE to 1 marks the selected slot as empty. -TBSEL and TSNEXT are unused in TTCAN mode and have no meaning. -TBPTR can only point to buffer slots, that exist in the hardware. -Unusable bits ofTBPTR are fixed to 0. -TBPTR is limited to the PTB and 63 STB slots. - More slots cannot be used in TTCANmode.If TBPTR is too big and points to a slot that is not available, then TBF and TBE arereset automatically and no action takes place. - 0 - 6 - read-write - - - - - TTCFG - TTCAN: Time Trigger Configuration TTCFG - 0xbf - 8 - 0x00 - 0xFF - - - WTIE - Watch Trigger Interrupt Enable - 7 - 1 - read-write - - - WTIF - Watch Trigger Interrupt Flag -WTIF will be set if the cycle count reaches the limited defined by TT_WTRIG and WTIE is set. - 6 - 1 - read-write - - - TEIF - Trigger Error Interrupt Flag -The conditions when TEIF will be set, are defined in Chapter 6.4. There is no bit toenable or disable the handling of TEIF - 5 - 1 - read-write - - - TTIE - Time Trigger Interrupt Enable -If TTIE is set, then TTIF will be set if the cycle time is equal to the trigger timeTT_TRIG. - 4 - 1 - read-write - - - TTIF - Time Trigger Interrupt Flag -TTIF will be set if TTIE is set and the cycle time is equal to the trigger time TT_TRIG. -Writing a one to TTIF resets it. Writing a zero has no impact.TTIF will be set only once. -If TT_TRIG gets not updated, then TTIF will be not setagain in the next basic cycle. - 3 - 1 - read-write - - - T_PRESC - TTCAN Timer PRESCaler -00b - 1 -01b - 2 -10b - 4 -11b - 8 -The TTCAN time base is a CAN bittime defined by S_PRES, S_SEG_1 and S_SEG_2.With T_PRESC an additional prescaling factor of 1, 2, 4 or 8 is defined. -T_PRESC can only be modified if TTEN=0, but it is possible to modify T_PRESC and setTTEN simultaneously with one write access. - 1 - 2 - read-write - - - TTEN - Time Trigger Enable -1 - TTCAN enabled, timer is running0 - disabled - 0 - 1 - read-write - - - - - REF_MSG - TTCAN: Reference Message REF_MSG - 0xc0 - 32 - 0x00000000 - 0x9FFFFFFF - - - REF_IDE - REFerence message IDE bit. - 31 - 1 - read-write - - - REF_MSG - REFerence message IDentifier. -If REF_IDE is -1 - REF_ID(28:0) is valid (extended ID) -0 - REF_ID(10:0) is valid (standard ID) -REF_ID is used in TTCAN mode to detect a reference message. This holds for time -slaves (reception) as well as for the time master (transmission). If the reference -message is detected and there are no errors, then the Sync_Mark of this frame will -become the Ref_Mark. -REF_ID(2:0) is not tested and therefore the appropriate register bits are forced to 0. -These bits are used for up to 8 potential time masters. -CAN-CTRL recognizes the reference message only by ID. The payload is not tested. -Additional note: A time master will transmit a reference message in the same way as a -normal frame. REF_ID is intended for detection of a successful transmission of a -reference message. - 0 - 29 - read-write - - - - - TRIG_CFG - TTCAN: Trigger Configuration TRIG_CFG - 0xc4 - 16 - 0x0000 - 0xF73F - - - TEW - Transmit Enable Window -For a single shot transmit trigger there is a time of up to 16 ticks of the cycle time -where the frame is allowed to start. TWE+1 defines the number of ticks. -TEW=0 is a valid setting and shortens the transmit enable window to 1 tick - 12 - 4 - read-write - - - TTYPE - Trigger Type -000b - Immediate Trigger for immediate transmission -001b - Time Trigger for receive triggers -010b - Single Shot Transmit Trigger for exclusive time windows -011b - Transmit Start Trigger for merged arbitrating time windows -100b - Transmit Stop Trigger for merged arbitrating time windows -others - no action -The time of the trigger is defined by TT_TRIG. TTPTR selects the TB slot for the -transmit triggers. See Chapter 6.4 for more details. - 8 - 3 - read-write - - - TTPTR - Transmit Trigger TB slot Pointer -If TTPTR is too big and points to a slot that is not available, then TEIF is set and no -new trigger can be activated after a write access to TT_TRIG_1. -If TTPTR points to an empty slot, then TEIF will be set at the moment, when the -trigger time is reached. - 0 - 6 - read-write - - - - - TT_TRIG - TTCAN: Trigger Time TT_TRIG - 0xc6 - 16 - 0x0000 - 0xFFFF - - - TT_TRIG - Trigger Time -TT_TRIG(15:0) defines the cycle time for a trigger. -For a transmission trigger theearliest point of transmission of the SOF of the appropriate frame will be TT_TRIG+1. - 0 - 16 - read-write - - - - - TT_WTRIG - TTCAN: Watch Trigger Time TT_WTRIG - 0xc8 - 16 - 0x0000 - 0xFFFF - - - TT_WTRIG - Watch Trigger Time -TT_WTRIG(15:0) defines the cycle time for a watch trigger. The initial watch trigger isthe maximum cycle time 0xffff. - 0 - 16 - read-write - - - - - - - CAN1 - CAN1 - CAN - 0xf0084000 - - - CAN2 - CAN2 - CAN - 0xf0088000 - - - CAN3 - CAN3 - CAN - 0xf008c000 - - - WDG0 - WDG0 - WDOG - 0xf0090000 - - 0x10 - 0x10 - registers - - - - CTRL - Control Register - 0x10 - 32 - 0x00000000 - 0x000007FF - - - RSTTIME - The time interval of the reset stage: -0: Clock period x 2^7 -1: Clock period x 2^8 -2: Clock period x 2^9 -3: Clock period x 2^10 -4: Clock period x 2^11 -5: Clock period x 2^12 -6: Clock period x 2^13 -7: Clock period x 2^14 - 8 - 3 - read-write - - - INTTIME - The timer interval of the interrupt stage: -0: Clock period x 2^6 -1: Clock period x 2^8 -2: Clock period x 2^10 -3: Clock period x 2^11 -4: Clock period x 2^12 -5: Clock period x 2^13 -6: Clock period x 2^14 -7: Clock period x 2^15 -8: Clock period x 2^17 -9: Clock period x 2^19 -10: Clock period x 2^21 -11: Clock period x 2^23 -12: Clock period x 2^25 -13: Clock period x 2^27 -14: Clock period x 2^29 -15: Clock period x 2^31 - 4 - 4 - read-write - - - RSTEN - Enable or disable the watchdog reset -0: Disable -1: Enable - 3 - 1 - read-write - - - INTEN - Enable or disable the watchdog interrupt -0: Disable -1: Enable - 2 - 1 - read-write - - - CLKSEL - Clock source of timer: -0: EXTCLK -1: PCLK - 1 - 1 - read-write - - - EN - Enable or disable the watchdog timer -0: Disable -1: Enable - 0 - 1 - read-write - - - - - Restart - Restart Register - 0x14 - 32 - 0x00000000 - 0x0000FFFF - - - RESTART - Write the magic number -ATCWDT200_RESTART_NUM to restart the -watchdog timer. - 0 - 16 - write-only - - - - - WrEn - Write Protection Register - 0x18 - 32 - 0x00000000 - 0x0000FFFF - - - WEN - Write the magic code to disable the write -protection of the Control Register and the -Restart Register. - 0 - 16 - write-only - - - - - St - Status Register - 0x1c - 32 - 0x00000000 - 0x00000001 - - - INTEXPIRED - The status of the watchdog interrupt timer -0: timer is not expired yet -1: timer is expired - 0 - 1 - write-only - - - - - - - WDG1 - WDG1 - WDOG - 0xf0094000 - - - WDG2 - WDG2 - WDOG - 0xf0098000 - - - WDG3 - WDG3 - WDOG - 0xf009c000 - - - PWDG - PWDG - WDOG - 0xf40e8000 - - - MBX0A - MBX0A - MBX - 0xf00a0000 - - 0x0 - 0x24 - registers - - - - CR - Command Registers - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - TXRESET - Reset TX Fifo and word. - 31 - 1 - read-write - - - BARCTL - Bus Access Response Control, when bit 15:14= -00: no bus error will be generated, no wait for fifo write when fifo full and no wait for word/fifo read when word message invalid or fifo empty; or when write to word/fifo message will be ignored. - 01: bus error will be generated when: 1, access invalid address; 2, write to ready only addr; 3, write to fulled fifo or valid message; 4, read from a emptied fifo/word message. -10: no error will be generated, but bus will wait when 1, write to fulled fifo/reg message; 2, read from a emptied fifo/reg message; write to word message will overwrite the existing reg value enven word message are still valid; read from invalid word message will read out last read out message data.happen. -11: reserved. - 14 - 2 - read-write - - - BEIE - Bus Error Interrupt Enable, will enable the interrupt for any bus error as described in the SR bit 13 to bit 8. -1, enable the bus access error interrupt. -0, disable the bus access error interrupt. - 8 - 1 - read-write - - - TFMAIE - TX FIFO message available interrupt enable. -1, enable the TX FIFO massage available interrupt. -0, disable the TX FIFO message available interrupt. - 7 - 1 - read-write - - - TFMEIE - TX FIFO message empty interrupt enable. -1, enable the TX FIFO massage empty interrupt. -0, disable the TX FIFO message empty interrupt. - 6 - 1 - read-write - - - RFMAIE - RX FIFO message available interrupt enable. -1, enable the RX FIFO massage available interrupt. -0, disable the RX FIFO message available interrupt. - 5 - 1 - read-write - - - RFMFIE - RX fifo message full interrupt enable. -1, enable the RX fifo message full interrupt. -0, disable the RX fifo message full interrupt. - 4 - 1 - read-write - - - TWMEIE - TX word message empty interrupt enable. -1, enable the TX word massage empty interrupt. -0, disable the TX word message empty interrupt. - 1 - 1 - read-write - - - RWMVIE - RX word message valid interrupt enable. -1, enable the RX word massage valid interrupt. -0, disable the RX word message valid interrupt. - 0 - 1 - read-write - - - - - SR - Status Registers - 0x4 - 32 - 0x000000E2 - 0xFFFF3FFF - - - RFVC - RX FIFO valid message count - 20 - 4 - read-only - - - TFEC - TX FIFO empty message word count - 16 - 4 - read-only - - - ERRRE - bus Error for read when rx word message are still invalid, this bit is W1C bit. -1, read from word message when the word message are still invalid will cause this error bit set. -0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - 13 - 1 - write-only - - - EWTRF - bus Error for write when tx word message are still valid, this bit is W1C bit. -1, write to word message when the word message are still valid will cause this error bit set. -0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - 12 - 1 - write-only - - - ERRFE - bus Error for read when rx fifo empty, this bit is W1C bit. -1, read from a empty rx fifo will cause this error bit set. -0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - 11 - 1 - write-only - - - EWTFF - bus Error for write when tx fifo full, this bit is W1C bit. -1, write to a fulled tx fifo will cause this error bit set. -0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - 10 - 1 - write-only - - - EAIVA - bus Error for Accessing Invalid Address; this bit is W1C bit. -1, read and write to invalid address in the bus of this block, will set this bit. -0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - 9 - 1 - write-only - - - EW2RO - bus Error for Write to Read Only address; this bit is W1C bit. -1, write to read only address happened in the bus of this block. -0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - 8 - 1 - write-only - - - TFMA - TX FIFO Message slot available, the 4x32 TX FIFO message buffer to the other core full, will not trigger any interrupt. -1, TXFIFO message buffer has slot available -0, no slot available (fifo full) - 7 - 1 - read-write - - - TFME - TX FIFO Message Empty, no any data in the message FIFO buffer from other core, will not trigger any interrupt.message from other core. -1, no any message data in TXFIFO from other core. -0, there are some data in the 4x32 TX FIFO from other core yet. - 6 - 1 - read-write - - - RFMA - RX FIFO Message Available, available data in the 4x32 TX FIFO message buffer to the other core, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. -1, no any data in the 4x32 TXFIFO message buffer. -0, there are some data in the the 4x32 TXFIFO message buffer already. - 5 - 1 - read-only - - - RFMF - RX FIFO Message Full, message from other core; will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. -1, the other core had written 4x32 message in the RXFIFO. -0, no 4x32 RX FIFO message from other core yet. - 4 - 1 - read-only - - - TWME - TX word message empty, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. -1, means this core had write word message to TXREG. -0, means no valid word message in the TXREG yet. - 1 - 1 - read-only - - - RWMV - RX word message valid, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. -1, the other core had written word message in the RXREG. -0, no valid word message yet in the RXREG. - 0 - 1 - read-only - - - - - TXREG - Transmit word message to other core. - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - TXREG - Transmit word message to other core. - 0 - 32 - write-only - - - - - RXREG - Receive word message from other core. - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - RXREG - Receive word message from other core. - 0 - 32 - read-only - - - - - 1 - 0x4 - TXFIFO0 - TXWRD[%s] - no description available - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - TXFIFO - TXFIFO for sending message to other core, FIFO size, 4x32 -can write one of the word address to push data to the FIFO; -can also use 4x32 burst write from 0x010 to push 4 words to the FIFO. - 0 - 32 - write-only - - - - - 1 - 0x4 - RXFIFO0 - RXWRD[%s] - no description available - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXFIFO - RXFIFO for receiving message from other core, FIFO size, 4x32 -can read one of the word address to pop data to the FIFO; -can also use 4x32 burst read from 0x020 to read 4 words from the FIFO. - 0 - 32 - read-only - - - - - - - MBX0B - MBX0B - MBX - 0xf00a4000 - - - MBX1A - MBX1A - MBX - 0xf00a8000 - - - MBX1B - MBX1B - MBX - 0xf00ac000 - - - PTPC - PTPC - PTPC - 0xf00b0000 - - 0x0 - 0x3004 - registers - - - - 2 - 0x1000 - 0,1 - PTPC[%s] - no description available - 0x0 - - Ctrl0 - Control Register 0 - 0x0 - 32 - 0x00000000 - 0x000003FF - - - SUBSEC_DIGITAL_ROLLOVER - Format for ns counter rollover, -1-digital, overflow time 1000000000/0x3B9ACA00 -0-binary, overflow time 0x7FFFFFFF - 9 - 1 - read-write - - - CAPT_SNAP_KEEP - set will keep capture snap till software read capt_snapl. -If this bit is set, software should read capt_snaph first to avoid wrong result. -If this bit is cleared, capture result will be updated at each capture event - 8 - 1 - read-write - - - CAPT_SNAP_POS_EN - set will use posege of input capture signal to latch timestamp value - 7 - 1 - read-write - - - CAPT_SNAP_NEG_EN - No description available - 6 - 1 - read-write - - - COMP_EN - set to enable compare, will be cleared by HW when compare event triggered - 4 - 1 - read-write - - - UPDATE_TIMER - update timer with +/- ts_updt, pulse, clear after set - 3 - 1 - write-only - - - INIT_TIMER - initial timer with ts_updt, pulse, clear after set - 2 - 1 - write-only - - - FINE_COARSE_SEL - 0: coarse update, ns counter add ss_incr[7:0] each clk -1: fine update, ns counter add ss_incr[7:0] each time addend counter overflow - 1 - 1 - read-write - - - TIMER_ENABLE - No description available - 0 - 1 - read-write - - - - - ctrl1 - Control Register 1 - 0x4 - 32 - 0x00000000 - 0x000000FF - - - SS_INCR - constant value used to add ns counter; -such as for 50MHz timer clock, set it to 8'd20 - 0 - 8 - read-write - - - - - timeh - timestamp high - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - TIMESTAMP_HIGH - No description available - 0 - 32 - read-only - - - - - timel - timestamp low - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - TIMESTAMP_LOW - No description available - 0 - 32 - read-only - - - - - ts_updth - timestamp update high - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - SEC_UPDATE - together with ts_updtl, used to initial or update timestamp - 0 - 32 - read-write - - - - - ts_updtl - timestamp update low - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADD_SUB - 1 for sub; 0 for add, used only at update - 31 - 1 - read-write - - - NS_UPDATE - No description available - 0 - 31 - read-write - - - - - addend - No description available - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDEND - used in fine update mode only - 0 - 32 - read-write - - - - - tarh - No description available - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - TARGET_TIME_HIGH - used for generate compare signal if enabled - 0 - 32 - read-write - - - - - tarl - No description available - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - TARGET_TIME_LOW - No description available - 0 - 32 - read-write - - - - - pps_ctrl - No description available - 0x2c - 32 - 0x00000000 - 0x0000000F - - - PPS_CTRL - No description available - 0 - 4 - read-write - - - - - capt_snaph - No description available - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPT_SNAP_HIGH - take snapshot for input capture signal, at pos or neg or both; -the result can be kept or updated at each event according to cfg0.bit8 - 0 - 32 - read-only - - - - - capt_snapl - No description available - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPT_SNAP_LOW - No description available - 0 - 32 - read-write - - - - - - time_sel - No description available - 0x2000 - 32 - 0x00000000 - 0x0000000F - - - CAN3_TIME_SEL - No description available - 3 - 1 - read-write - - - CAN2_TIME_SEL - No description available - 2 - 1 - read-write - - - CAN1_TIME_SEL - No description available - 1 - 1 - read-write - - - CAN0_TIME_SEL - set to use ptpc1 for canx -clr to use ptpc0 for canx - 0 - 1 - read-write - - - - - int_sts - No description available - 0x2004 - 32 - 0x00000000 - 0x00070007 - - - COMP_INT_STS1 - No description available - 18 - 1 - write-only - - - CAPTURE_INT_STS1 - No description available - 17 - 1 - write-only - - - PPS_INT_STS1 - No description available - 16 - 1 - write-only - - - COMP_INT_STS0 - No description available - 2 - 1 - write-only - - - CAPTURE_INT_STS0 - No description available - 1 - 1 - write-only - - - PPS_INT_STS0 - No description available - 0 - 1 - write-only - - - - - int_en - No description available - 0x2008 - 32 - 0x00000000 - 0x00070007 - - - COMP_INT_STS1 - No description available - 18 - 1 - read-write - - - CAPTURE_INT_STS1 - No description available - 17 - 1 - read-write - - - PPS_INT_STS1 - No description available - 16 - 1 - read-write - - - COMP_INT_STS0 - No description available - 2 - 1 - read-write - - - CAPTURE_INT_STS0 - No description available - 1 - 1 - read-write - - - PPS_INT_STS0 - No description available - 0 - 1 - read-write - - - - - ptpc_can_ts_sel - No description available - 0x3000 - 32 - 0x00000000 - 0xFFFFFF00 - - - TSU_TBIN3_SEL - No description available - 26 - 6 - read-write - - - TSU_TBIN2_SEL - No description available - 20 - 6 - read-write - - - TSU_TBIN1_SEL - No description available - 14 - 6 - read-write - - - TSU_TBIN0_SEL - No description available - 8 - 6 - read-write - - - - - - - DMAMUX - DMAMUX - DMAMUX - 0xf00c0000 - - 0x0 - 0x40 - registers - - - - 16 - 0x4 - HDMA_MUX0,HDMA_MUX1,HDMA_MUX2,HDMA_MUX3,HDMA_MUX4,HDMA_MUX5,HDMA_MUX6,HDMA_MUX7,XDMA_MUX0,XDMA_MUX1,XDMA_MUX2,XDMA_MUX3,XDMA_MUX4,XDMA_MUX5,XDMA_MUX6,XDMA_MUX7 - MUXCFG[%s] - no description available - 0x0 - 32 - 0x00000000 - 0x8000007F - - - ENABLE - DMA Mux Channel Enable -Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be -used to disable or reconfigure a DMA channel. -0b - DMA Mux channel is disabled -1b - DMA Mux channel is enabled - 31 - 1 - read-write - - - SOURCE - DMA Channel Source -Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" - 0 - 7 - read-write - - - - - - - HDMA - HDMA - DMA - 0xf00c4000 - - 0x10 - 0x130 - registers - - - - DMACfg - DMAC Configuration Register - 0x10 - 32 - 0x00000000 - 0xC3FFFFFF - - - CHAINXFR - Chain transfer -0x0: Chain transfer is not configured -0x1: Chain transfer is configured - 31 - 1 - read-only - - - REQSYNC - DMA request synchronization. The DMA request synchronization should be configured to avoid signal integrity problems when the request signal is not clocked by the system bus clock, which the DMA control logic operates in. If the request synchronization is not configured, the request signal is sampled directly without synchronization. -0x0: Request synchronization is not configured -0x1: Request synchronization is configured - 30 - 1 - read-only - - - DATAWIDTH - AXI bus data width -0x0: 32 bits -0x1: 64 bits -0x2: 128 bits -0x3: 256 bits - 24 - 2 - read-only - - - ADDRWIDTH - AXI bus address width -0x18: 24 bits -0x19: 25 bits -... -0x40: 64 bits -Others: Invalid - 17 - 7 - read-only - - - CORENUM - DMA core number -0x0: 1 core -0x1: 2 cores - 16 - 1 - read-only - - - BUSNUM - AXI bus interface number -0x0: 1 AXI bus -0x1: 2 AXI busses - 15 - 1 - read-only - - - REQNUM - Request/acknowledge pair number -0x0: 0 pair -0x1: 1 pair -0x2: 2 pairs -... -0x10: 16 pairs - 10 - 5 - read-only - - - FIFODEPTH - FIFO depth -0x4: 4 entries -0x8: 8 entries -0x10: 16 entries -0x20: 32 entries -Others: Invalid - 4 - 6 - read-only - - - CHANNELNUM - Channel number -0x1: 1 channel -0x2: 2 channels -... -0x8: 8 channels -Others: Invalid - 0 - 4 - read-only - - - - - DMACtrl - DMAC Control Register - 0x20 - 32 - 0x00000000 - 0x00000001 - - - RESET - Software reset control. Write 1 to this bit to reset the DMA core and disable all channels. -Note: The software reset may cause the in-completion of AXI transaction. - 0 - 1 - write-only - - - - - ChAbort - Channel Abort Register - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - CHABORT - Write 1 to bit n to abort channel n. The bits should only be set when the corresponding channels are enabled. Otherwise, the writes will be ignored for channels that are not enabled. (N: Number of channels) - 0 - 32 - write-only - - - - - IntStatus - Interrupt Status Register - 0x30 - 32 - 0x00000000 - 0x00FFFFFF - - - TC - The terminal count status, one bit per channel. The terminal count status is set when a channel transfer finishes without the abort or error event. -0x0: Channel n has no terminal count status -0x1: Channel n has terminal count status - 16 - 8 - write-only - - - ABORT - The abort status of channel, one bit per channel. The abort status is set when a channel transfer is aborted. -0x0: Channel n has no abort status -0x1: Channel n has abort status - 8 - 8 - write-only - - - ERROR - The error status, one bit per channel. The error status is set when a channel transfer encounters the following error events: -- Bus error -- Unaligned address -- Unaligned transfer width -- Reserved configuration -0x0: Channel n has no error status -0x1: Channel n has error status - 0 - 8 - write-only - - - - - ChEN - Channel Enable Register - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - CHEN - Alias of the Enable field of all ChnCtrl registers - 0 - 32 - read-only - - - - - 8 - 0x20 - ch0,ch1,ch2,ch3,ch4,ch5,ch6,ch7 - CHCTRL[%s] - no description available - 0x40 - - Ctrl - Channel n Control Register - 0x0 - 32 - 0x00000000 - 0xEFFFFFFF - - - SRCBUSINFIDX - Bus interface index that source data is read from -0x0: Data is read from bus interface 0 -0x1: Data is read from bus interface - 31 - 1 - read-write - - - DSTBUSINFIDX - Bus interface index that destination data is written to -0x0: Data is written to bus interface 0 -0x1: Data is written to bus interface 1 - 30 - 1 - read-write - - - PRIORITY - Channel priority level -0x0: Lower priority -0x1: Higher priority - 29 - 1 - read-write - - - SRCBURSTSIZE - Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. -The burst transfer byte number is (SrcBurstSize * SrcWidth). -0x0: 1 transfer -0x1: 2 transfers -0x2: 4 transfers -0x3: 8 transfers -0x4: 16 transfers -0x5: 32 transfers -0x6: 64 transfers -0x7: 128 transfers -0x8: 256 transfers -0x9:512 transfers -0xa: 1024 transfers -0xb-0xf: Reserved, setting this field with a reserved value triggers the error exception -for XDMA, the maximum allowed value is 0xa; for HDMA, the maximum allowed value is 0x7 - 24 - 4 - read-write - - - SRCWIDTH - Source transfer width -0x0: Byte transfer -0x1: Half-word transfer -0x2: Word transfer -0x3: Double word transfer -0x4: Quad word transfer -0x5: Eight word transfer -0x6-x7: Reserved, setting this field with a reserved value triggers the error exception -for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 - 21 - 3 - read-write - - - DSTWIDTH - Destination transfer width. -Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; otherwise the error event will be triggered. For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. -See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. -0x0: Byte transfer -0x1: Half-word transfer -0x2: Word transfer -0x3: Double word transfer -0x4: Quad word transfer -0x5: Eight word transfer -0x6-x7: Reserved, setting this field with a reserved value triggers the error exception -for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 - 18 - 3 - read-write - - - SRCMODE - Source DMA handshake mode -0x0: Normal mode -0x1: Handshake mode - 17 - 1 - read-write - - - DSTMODE - Destination DMA handshake mode -0x0: Normal mode -0x1: Handshake mode - 16 - 1 - read-write - - - SRCADDRCTRL - Source address control -0x0: Increment address -0x1: Decrement address -0x2: Fixed address -0x3: Reserved, setting the field with this value triggers the error exception - 14 - 2 - read-write - - - DSTADDRCTRL - Destination address control -0x0: Increment address -0x1: Decrement address -0x2: Fixed address -0x3: Reserved, setting the field with this value triggers the error exception - 12 - 2 - read-write - - - SRCREQSEL - Source DMA request select. Select the request/ack handshake pair that the source device is connected to. - 8 - 4 - read-write - - - DSTREQSEL - Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. - 4 - 4 - read-write - - - INTABTMASK - Channel abort interrupt mask -0x0: Allow the abort interrupt to be triggered -0x1: Disable the abort interrupt - 3 - 1 - read-write - - - INTERRMASK - Channel error interrupt mask -0x0: Allow the error interrupt to be triggered -0x1: Disable the error interrupt - 2 - 1 - read-write - - - INTTCMASK - Channel terminal count interrupt mask -0x0: Allow the terminal count interrupt to be triggered -0x1: Disable the terminal count interrupt - 1 - 1 - read-write - - - ENABLE - Channel enable bit -0x0: Disable -0x1: Enable - 0 - 1 - read-write - - - - - TranSize - Channel n Transfer Size Register - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - TRANSIZE - Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. -If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated. - 0 - 32 - read-write - - - - - SrcAddr - Channel n Source Address Low Part Register - 0x8 - 32 - 0x00000001 - 0xFFFFFFFF - - - SRCADDRL - Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. -This address must be aligned to the source transfer size; otherwise, an error event will be triggered. - 0 - 32 - read-write - - - - - SrcAddrH - Channel n Source Address High Part Register - 0xc - 32 - 0x00000001 - 0xFFFFFFFF - - - SRCADDRH - High part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. -This register exists only when the address bus width is wider than 32 bits. - 0 - 32 - read-write - - - - - DstAddr - Channel n Destination Address Low Part Register - 0x10 - 32 - 0x00000001 - 0xFFFFFFFF - - - DSTADDRL - Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. -This address must be aligned to the destination transfer size; otherwise the error event will be triggered. - 0 - 32 - read-write - - - - - DstAddrH - Channel n Destination Address High Part Register - 0x14 - 32 - 0x00000001 - 0xFFFFFFFF - - - DSTADDRH - High part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. -This address must be aligned to the destination transfer size; otherwise the error event will be triggered. -This register exists only when the address bus width is wider than 32 bits. - 0 - 32 - read-write - - - - - LLPointer - Channel n Linked List Pointer Low Part Register - 0x18 - 32 - 0x00000000 - 0xFFFFFFF9 - - - LLPOINTERL - Low part of the pointer to the next descriptor. The pointer must be double word aligned. - 3 - 29 - read-write - - - LLDBUSINFIDX - Bus interface index that the next descriptor is read from -0x0: The next descriptor is read from bus interface 0 - 0 - 1 - read-write - - - - - LLPointerH - Channel n Linked List Pointer High Part Register - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - LLPOINTERH - High part of the pointer to the next descriptor. -This register exists only when the address bus width is wider than 32 bits. - 0 - 32 - read-write - - - - - - - - XDMA - XDMA - DMA - 0xf3048000 - - - RNG - RNG - RNG - 0xf00c8000 - - 0x0 - 0x40 - registers - - - - CMD - Command Register - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SFTRST - Soft Reset, Perform a software reset of the RNG This bit is self-clearing. -0 Do not perform a software reset. -1 Software reset - 6 - 1 - read-write - - - CLRERR - Clear the Error, clear the errors in the ESR register and the RNG interrupt. This bit is self-clearing. -0 Do not clear the errors and the interrupt. -1 Clear the errors and the interrupt. - 5 - 1 - read-write - - - CLRINT - Clear the Interrupt, clear the RNG interrupt if an error is not present. This bit is self-clearing. -0 Do not clear the interrupt. -1 Clear the interrupt - 4 - 1 - read-write - - - GENSD - Generate Seed, when both ST and GS triggered, ST first and GS next. - 1 - 1 - read-write - - - SLFCHK - Self Test, when both ST and GS triggered, ST first and GS next. - 0 - 1 - read-write - - - - - CTRL - Control Register - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - MIRQERR - Mask Interrupt Request for Error - 6 - 1 - read-write - - - MIRQDN - Mask Interrupt Request for Done Event, asks the interrupts generated upon the completion of the seed and self-test modes. The status of these jobs can be viewed by: -• Reading the STA and viewing the seed done and the self-test done bits (STA[SDN, STDN]). -• Viewing the RNG_CMD for the generate-seed or the self-test bits (CMD[GS,ST]) being set, indicating that the operation is still taking place. - 5 - 1 - read-write - - - AUTRSD - Auto Reseed - 4 - 1 - read-write - - - FUFMOD - FIFO underflow response mode -00 Return all zeros and set the ESR[FUFE]. -01 Return all zeros and set the ESR[FUFE]. -10 Generate the bus transfer error -11 Generate the interrupt and return all zeros (overrides the CTRL[MASKERR]). - 0 - 2 - read-write - - - - - STA - Status Register - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - SCPF - Self Check Pass Fail - 21 - 3 - read-only - - - FUNCERR - Error was detected, check ESR register for details - 16 - 1 - read-only - - - FSIZE - Fifo Size, it is 5 in this design. - 12 - 4 - read-only - - - FRNNU - Fifo Level, Indicates the number of random words currently in the output FIFO - 8 - 4 - read-only - - - NSDDN - New seed done. - 6 - 1 - read-only - - - FSDDN - 1st Seed done -When "1", Indicates that the RNG generated the first seed. - 5 - 1 - read-only - - - SCDN - Self Check Done -Indicates whether Self Test is done or not. Can be cleared by the hardware reset or a new self test is -initiated by setting the CMD[ST]. -0 Self test not completed -1 Completed a self test since the last reset. - 4 - 1 - read-only - - - RSDREQ - Reseed needed -Indicates that the RNG needs to be reseeded. This is done by setting the CMD[GS], or -automatically if the CTRL[ARS] is set. - 3 - 1 - read-only - - - IDLE - Idle, the RNG is in the idle mode, and internal clocks are disabled, in this mode, access to the FIFO is allowed. Once the FIFO is empty, the RNGB fills the FIFO and then enters idle mode again. - 2 - 1 - read-only - - - BUSY - when 1, means the RNG engine is busy for seeding or random number generation, self test and so on. - 1 - 1 - read-only - - - - - ERR - Error Registers - 0xc - 32 - 0x00000000 - 0xFFFFFF3F - - - FUFE - FIFO access error(underflow) - 5 - 1 - read-only - - - SCKERR - Self-test error -Indicates that the RNG failed the most recent self test. This bit is sticky and can only be reset by a -hardware reset or by writing 1 to the CMD[CE] - 3 - 1 - read-only - - - - - FO2B - FIFO out to bus/cpu - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - FO2B - SW read the FIFO output. - 0 - 32 - read-only - - - - - 8 - 0x4 - FO2S0,FO2S1,FO2S2,FO2S3,FO2S4,FO2S5,FO2S6,FO2S7 - R2SK[%s] - no description available - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - FO2S0 - FIFO out to KMAN, will be SDP engine key. - 0 - 32 - read-only - - - - - - - KEYM - KEYM - KEYM - 0xf00cc000 - - 0x0 - 0x50 - registers - - - - 8 - 0x4 - SFK0,SFK1,SFK2,SFK3,SFK4,SFK5,SFK6,SFK7 - SOFTMKEY[%s] - no description available - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - KEY - software symmetric key -key will be scambled to 4 variants for software to use, and replicable on same chip. -scramble keys are chip different, and not replicable on different chip -must be write sequencely from 0 - 7, otherwise key value will be treated as all 0 - 0 - 32 - read-write - - - - - 8 - 0x4 - SPK0,SPK1,SPK2,SPK3,SPK4,SPK5,SPK6,SPK7 - SOFTPKEY[%s] - no description available - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - KEY - software asymmetric key -key is derived from scrambles of fuse private key, software input key, SRK, and system security status. -This key os read once, sencondary read will read out 0 - 0 - 32 - read-write - - - - - SEC_KEY_CTL - secure key generation - 0x40 - 32 - 0x00000000 - 0x80011117 - - - LOCK_SEC_CTL - block secure state key setting being changed - 31 - 1 - read-write - - - SK_VAL - session key valid -0: session key is all 0's and not usable -1: session key is valid - 16 - 1 - read-only - - - SMK_SEL - software symmetric key selection -0: use origin value in software symmetric key -1: use scramble version of software symmetric key - 12 - 1 - read-write - - - ZMK_SEL - batt symmetric key selection -0: use scramble version of software symmetric key -1: use origin value in software symmetric key - 8 - 1 - read-write - - - FMK_SEL - fuse symmetric key selection -0: use scramble version of fuse symmetric key -1: use alnertave scramble of fuse symmetric key - 4 - 1 - read-write - - - KEY_SEL - secure symmtric key synthesize setting, key is a XOR of following -bit0: fuse mk, 0: not selected, 1:selected -bit1: zmk from batt, 0: not selected, 1:selected -bit2: software key 0: not selected, 1:selected - 0 - 3 - read-write - - - - - NSC_KEY_CTL - non-secure key generation - 0x44 - 32 - 0x00000000 - 0x80011117 - - - LOCK_NSC_CTL - block non-secure state key setting being changed - 31 - 1 - read-write - - - SK_VAL - session key valid -0: session key is all 0's and not usable -1: session key is valid - 16 - 1 - read-only - - - SMK_SEL - software symmetric key selection -0: use scramble version of software symmetric key -1: use origin value in software symmetric key - 12 - 1 - read-write - - - ZMK_SEL - batt symmetric key selection -0: use scramble version of software symmetric key -1: use origin value in software symmetric key - 8 - 1 - read-write - - - FMK_SEL - fuse symmetric key selection -0: use scramble version of fuse symmetric key -1: use origin value in fuse symmetric key - 4 - 1 - read-write - - - KEY_SEL - non-secure symmtric key synthesize setting, key is a XOR of following -bit0: fuse mk, 0: not selected, 1:selected -bit1: zmk from batt, 0: not selected, 1:selected -bit2: software key 0: not selected, 1:selected - 0 - 3 - read-write - - - - - RNG - Random number interface behavior - 0x48 - 32 - 0x00000000 - 0x00010001 - - - BLOCK_RNG_XOR - block RNG_XOR bit from changing, if this bit is written to 1, it will hold 1 until next reset -0: RNG_XOR can be changed by software -1: RNG_XOR ignore software change from software - 16 - 1 - read-write - - - RNG_XOR - control how SFK is accepted from random number generator -0: SFK value replaced by random number input -1: SFK value exclusive or with random number input,this help generate random number using 2 rings inside RNG - 0 - 1 - read-write - - - - - READ_CONTROL - key read out control - 0x4c - 32 - 0x00000000 - 0x00010001 - - - BLOCK_PK_READ - asymmetric key readout control, if this bit is written to 1, it will hold 1 until next reset -0: key can be read out -1: key cannot be read out - 16 - 1 - read-write - - - BLOCK_SMK_READ - symmetric key readout control, if this bit is written to 1, it will hold 1 until next reset -0: key can be read out -1: key cannot be read out - 0 - 1 - read-write - - - - - - - I2S0 - I2S0 - I2S - 0xf0100000 - - 0x0 - 0x80 - registers - - - - CTRL - Control Register - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SFTRST_RX - software reset the RX module if asserted to be 1'b1. Self-clear. - 18 - 1 - read-write - - - SFTRST_TX - software reset the TX module if asserted to be 1'b1. Self-clear. - 17 - 1 - read-write - - - SFTRST_CLKGEN - software reset the CLK GEN module if asserted to be 1'b1. Self-clear. - 16 - 1 - read-write - - - TXDNIE - TX buffer data needed interrupt enable -0: TXE interrupt masked -1: TXE interrupt not masked. Used to generate an interrupt request when the TXE flag is set. - 15 - 1 - read-write - - - RXDAIE - RX buffer data available interrupt enable -0: RXNE interrupt masked -1: RXNE interrupt not masked. Used to generate an interrupt request when the RXNE flag is set. - 14 - 1 - read-write - - - ERRIE - Error interrupt enable -This bit controls the generation of an interrupt when an error condition (UD, OV) occurs. -0: Error interrupt is masked -1: Error interrupt is enabled - 13 - 1 - read-write - - - TX_DMA_EN - Asserted to use DMA, else to use interrupt - 12 - 1 - read-write - - - RX_DMA_EN - Asserted to use DMA, else to use interrupt - 11 - 1 - read-write - - - TXFIFOCLR - Self-clear - 10 - 1 - read-write - - - RXFIFOCLR - Self-clear - 9 - 1 - read-write - - - TX_EN - enable for each TX data pad - 5 - 4 - read-write - - - RX_EN - enable for each RX data pad - 1 - 4 - read-write - - - I2S_EN - enable for the module - 0 - 1 - read-write - - - - - RFIFO_FILLINGS - Rx FIFO Filling Level - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - RX3 - RX3 fifo fillings - 24 - 8 - read-only - - - RX2 - RX2 fifo fillings - 16 - 8 - read-only - - - RX1 - RX1 fifo fillings - 8 - 8 - read-only - - - RX0 - RX0 fifo fillings - 0 - 8 - read-only - - - - - TFIFO_FILLINGS - Tx FIFO Filling Level - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - TX3 - TX3 fifo fillings - 24 - 8 - read-only - - - TX2 - TX2 fifo fillings - 16 - 8 - read-only - - - TX1 - TX1 fifo fillings - 8 - 8 - read-only - - - TX0 - TX0 fifo fillings - 0 - 8 - read-only - - - - - FIFO_THRESH - TX/RX FIFO Threshold setting. - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - TX - TX fifo threshold to trigger STA[tx_dn]. When tx fifo filling is smaller than or equal to the threshold, assert the tx_dn flag. - 8 - 8 - read-write - - - RX - RX fifo threshold to trigger STA[rx_da]. When rx fifo filling is greater than or equal to the threshold, assert the rx_da flag. - 0 - 8 - read-write - - - - - STA - Status Registers - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - TX_UD - Asserted when tx fifo is underflow. Should be ANDed with CTRL[tx_en] the for correct value. Write 1 to any of these 4 bits will clear the underflow error. - 13 - 4 - write-only - - - RX_OV - Asserted when rx fifo is overflow. Write 1 to any of these 4 bits will clear the overflow error. - 9 - 4 - write-only - - - TX_DN - Asserted when tx fifo data are needed. - 5 - 4 - read-only - - - RX_DA - Asserted when rx fifo data are available. - 1 - 4 - read-only - - - - - 4 - 0x4 - DATA0,DATA1,DATA2,DATA3 - RXD[%s] - no description available - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - D - No description available - 0 - 32 - read-only - - - - - 4 - 0x4 - DATA0,DATA1,DATA2,DATA3 - TXD[%s] - no description available - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - D - No description available - 0 - 32 - write-only - - - - - CFGR - Configruation Regsiters - 0x50 - 32 - 0x40000000 - 0xFFFFFFFF - - - BCLK_GATEOFF - Gate off the bclk. Asserted to gate-off the BCLK. - 30 - 1 - read-write - - - BCLK_DIV - Linear prescaler to generate BCLK from MCLK. -BCLK_DIV [8:0] = 0: BCLK=No CLK. -BCLK_DIV [8:0] = 1: BCLK=MCLK/1 -BCLK_DIV [8:0] = n: BCLK=MCLK/(n). -Note: These bits should be configured when the I2S is disabled. It is used only when the I2S is in master mode. - 21 - 9 - read-write - - - INV_BCLK_OUT - Invert the BCLK before sending it out to pad. Only valid in BCLK master mode - 20 - 1 - read-write - - - INV_BCLK_IN - Invert the BCLK pad input before using it internally. Only valid in BCLK slave mode - 19 - 1 - read-write - - - INV_FCLK_OUT - Invert the FCLK before sending it out to pad. Only valid in FCLK master mode - 18 - 1 - read-write - - - INV_FCLK_IN - Invert the FCLK pad input before using it internally. Only valid in FCLK slave mode - 17 - 1 - read-write - - - INV_MCLK_OUT - Invert the MCLK before sending it out to pad. Only valid in MCLK master mode - 16 - 1 - read-write - - - INV_MCLK_IN - Invert the MCLK pad input before using it internally. Only valid in MCLK slave mode - 15 - 1 - read-write - - - BCLK_SEL_OP - asserted to use external clk source - 14 - 1 - read-write - - - FCLK_SEL_OP - asserted to use external clk source - 13 - 1 - read-write - - - MCK_SEL_OP - asserted to use external clk source - 12 - 1 - read-write - - - FRAME_EDGE - The start edge of a frame -0: Falling edge indicates a new frame (Just like standard I2S Philips standard) -1: Rising edge indicates a new frame - 11 - 1 - read-write - - - CH_MAX - CH_MAX[4:0] s the number of channels supported in TDM mode. When not in TDM mode, it must be set as 2. -It must be an even number, so CH_MAX[0] is always 0. -5'h2: 2 channels -5'h4: 4 channels -... -5‘h10: 16 channels (max) - 6 - 5 - read-write - - - TDM_EN - TDM mode -0: not TDM mode -1: TDM mode - 5 - 1 - read-write - - - STD - I2S standard selection -00: I2S Philips standard. -01: MSB justified standard (left justified) -10: LSB justified standard (right justified) -11: PCM standard -Note: For correct operation, these bits should be configured when the I2S is disabled. - 3 - 2 - read-write - - - DATSIZ - Data length to be transferred -00: 16-bit data length -01: 24-bit data length -10: 32-bit data length -11: Not allowed -Note: For correct operation, these bits should be configured when the I2S is disabled. - 1 - 2 - read-write - - - CHSIZ - Channel length (number of bits per audio channel) -0: 16-bit wide -1: 32-bit wide -The bit write operation has a meaning only if DATSIZ = 00 otherwise the channel length is fixed to 32-bit by hardware whatever the value filled in. -Note: For correct operation, this bit should be configured when the I2S is disabled. - 0 - 1 - read-write - - - - - MISC_CFGR - Misc configuration Registers - 0x58 - 32 - 0x00042000 - 0xFFFFEC01 - - - MCLK_GATEOFF - Gate off the mclk. This mclk is the output of a glitch prone mux, so every time to switch the mclk, the gate off clock should be asserted at first. After the clock is switched, de-assert this bit to ungate off the mclk. - 13 - 1 - read-write - - - MCLKOE - Master clock output to pad enable -0: Master clock output is disabled -1: Master clock output is enabled -Note: This bit should be configured when the I2S is disabled. It is used only when the I2S is in master mode. - 0 - 1 - read-write - - - - - 4 - 0x4 - DATA0,DATA1,DATA2,DATA3 - RXDSLOT[%s] - no description available - 0x60 - 32 - 0x0000FFFF - 0x0000FFFF - - - EN - No description available - 0 - 16 - read-write - - - - - 4 - 0x4 - DATA0,DATA1,DATA2,DATA3 - TXDSLOT[%s] - no description available - 0x70 - 32 - 0x0000FFFF - 0x0000FFFF - - - EN - No description available - 0 - 16 - read-write - - - - - - - I2S1 - I2S1 - I2S - 0xf0104000 - - - I2S2 - I2S2 - I2S - 0xf0108000 - - - I2S3 - I2S3 - I2S - 0xf010c000 - - - DAO - DAO - DAO - 0xf0110000 - - 0x0 - 0x1c - registers - - - - CTRL - Control Register - 0x0 - 32 - 0x00000000 - 0x000200FF - - - HPF_EN - Whether HPF is enabled. This HPF is used to filter out the DC part. - 17 - 1 - read-write - - - MONO - Asserted to let the left and right channel output the same value. - 7 - 1 - read-write - - - RIGHT_EN - Asserted to enable the right channel - 6 - 1 - read-write - - - LEFT_EN - Asserted to enable the left channel - 5 - 1 - read-write - - - REMAP - 1: Use remap pwm version. The remap version is a version that one pwm output is tied to zero when the input pcm signal is positive or negative -0: Don't use remap pwm version - 4 - 1 - read-write - - - INVERT - all the outputs are inverted before sending to pad - 3 - 1 - read-write - - - FALSE_LEVEL - the pad output in False run mode, or when the module is disabled -0: all low -1: all high -2: P-high, N-low -3. output is not enabled - 1 - 2 - read-write - - - FALSE_RUN - the module continues to consume data, but all the pads are constant, thus no audio out - 0 - 1 - read-write - - - - - CMD - Command Register - 0x8 - 32 - 0x00000000 - 0x00000003 - - - SFTRST - Self-clear - 1 - 1 - read-write - - - RUN - Enable this module to run. - 0 - 1 - read-write - - - - - RX_CFGR - Configuration Register - 0xc - 32 - 0x00000000 - 0x000007C0 - - - CH_MAX - CH_MAX[3:0] is the number if channels supported in TDM mode. When not in TDM mode, it must be set as 2. -It must be an even number, so CH_MAX[0] is always 0. -4'h2: 2 channels -4'h4: 4 channels -etc - 6 - 5 - read-write - - - - - RXSLT - RX Slot Control Register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - EN - Slot enable for the channels. - 0 - 32 - read-write - - - - - HPF_MA - HPF A Coef Register - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - COEF - Composite value of coef A of the Order-1 HPF - 0 - 32 - read-write - - - - - HPF_B - HPF B Coef Register - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - COEF - coef B of the Order-1 HPF - 0 - 32 - read-write - - - - - - - PDM - PDM - PDM - 0xf0114000 - - 0x0 - 0x34 - registers - - - - CTRL - Control Register - 0x0 - 32 - 0x00000000 - 0x809FF7FF - - - SFTRST - software reset the module. Self-clear. - 31 - 1 - read-write - - - SOF_FEDGE - asserted if the falling edge of the ref fclk from DAO is the start of a new frame. This is used to to align DAO feedback signal. - 23 - 1 - read-write - - - USE_COEF_RAM - Asserted to use Coef RAM instead of Coef ROM - 20 - 1 - read-write - - - FILT_CRX_ERR_IE - data accessed out of boundary error interruput enable. The error happens when the module cannot calculate the enough number of data in time. - 19 - 1 - read-write - - - OFIFO_OVFL_ERR_IE - output fifo overflow error interrupt enable - 18 - 1 - read-write - - - CIC_OVLD_ERR_IE - CIC overload error interrupt enable - 17 - 1 - read-write - - - CIC_SAT_ERR_IE - Error interrupt enable -This bit controls the generation of an interrupt when an error condition (CIC saturation) occurs. -0: Error interrupt is masked -1: Error interrupt is enabled - 16 - 1 - read-write - - - DEC_AFT_CIC - decimation rate after CIC. Now it is forced to be 3. - 12 - 4 - read-write - - - CAPT_DLY - Capture cycle delay>=0, should be less than PDM_CLK_HFDIV - 7 - 4 - read-write - - - PDM_CLK_HFDIV - The clock divider will work at least 4. -0: div-by-2, -1: div-by-4 -. . . -n: div-by-2*(n+1) - 3 - 4 - read-write - - - PDM_CLK_DIV_BYPASS - asserted to bypass the pdm clock divider - 2 - 1 - read-write - - - PDM_CLK_OE - pdm_clk_output_en - 1 - 1 - read-write - - - HPF_EN - pdm high pass filter enable. This order-1 HPF only applies to the PDM mic data. - 0 - 1 - read-write - - - - - CH_CTRL - Channel Control Register - 0x4 - 32 - 0x00000000 - 0x00FF03FF - - - CH_POL - Asserted to select PDM_CLK high level captured, otherwise to select PDM_CLK low level captured. - 16 - 8 - read-write - - - CH_EN - Asserted to enable the channel. -Ch8 & 9 are refs. -Ch0-7 are pdm mics. - 0 - 10 - read-write - - - - - ST - Status Register - 0x8 - 32 - 0x00000000 - 0x0000000F - - - FILT_CRX_ERR - data accessed out of boundary error - 3 - 1 - write-only - - - OFIFO_OVFL_ERR - output fifo overflow error. The reason may be sampling frequency mismatch, either fast or slow. - 2 - 1 - write-only - - - CIC_OVLD_ERR - CIC overload error. write 1 clear - 1 - 1 - write-only - - - CIC_SAT_ERR - CIC saturation. Write 1 clear - 0 - 1 - write-only - - - - - CH_CFG - Channel Configuration Register - 0xc - 32 - 0x00000000 - 0x000FFFFF - - - CH9_TYPE - No description available - 18 - 2 - read-write - - - CH8_TYPE - No description available - 16 - 2 - read-write - - - CH7_TYPE - No description available - 14 - 2 - read-write - - - CH6_TYPE - No description available - 12 - 2 - read-write - - - CH5_TYPE - No description available - 10 - 2 - read-write - - - CH4_TYPE - No description available - 8 - 2 - read-write - - - CH3_TYPE - No description available - 6 - 2 - read-write - - - CH2_TYPE - No description available - 4 - 2 - read-write - - - CH1_TYPE - No description available - 2 - 2 - read-write - - - CH0_TYPE - Type of Channel 0 -2'b00: dec-by-3 wiith filter type0 (CIC Compenstation+norm filter) -2'b01: dec-by-3 with filter type 1 (No CIC compenstation, only norm filter) - 0 - 2 - read-write - - - - - CIC_CFG - CIC configuration register - 0x10 - 32 - 0x00000000 - 0x0000FFFF - - - POST_SCALE - the shift value after CIC results. - 10 - 6 - read-write - - - SGD - Sigma_delta_order[1:0] -2'b00: 7 -2'b01: 6 -2'b10: 5 -Others: unused - 8 - 2 - read-write - - - CIC_DEC_RATIO - CIC decimation factor - 0 - 8 - read-write - - - - - CTRL_INBUF - In Buf Control Register - 0x14 - 32 - 0x00000000 - 0x3FFFFFFF - - - MAX_PTR - The buf size-1 for each channel - 22 - 8 - read-write - - - PITCH - The spacing between starting address of adjacent channels - 11 - 11 - read-write - - - START_ADDR - The starting address of channel 0 in filter data buffer - 0 - 11 - read-write - - - - - CTRL_FILT0 - Filter 0 Control Register - 0x18 - 32 - 0x00000000 - 0x0000FFFF - - - COEF_LEN_M0 - Coef length of filter type 2'b00 in coef memory - 8 - 8 - read-write - - - COEF_START_ADDR - Starting address of Coef of filter type 2'b00 in coef memory - 0 - 8 - read-write - - - - - CTRL_FILT1 - Filter 1 Control Register - 0x1c - 32 - 0x00000000 - 0x0000FFFF - - - COEF_LEN_M1 - Coef length of filter type 2'b01 in coef memory - 8 - 8 - read-write - - - COEF_START_ADDR - Starting address of Coef of filter type 2'b01 in coef memory - 0 - 8 - read-write - - - - - RUN - Run Register - 0x20 - 32 - 0x00000000 - 0x00000001 - - - PDM_EN - Asserted to enable the module - 0 - 1 - read-write - - - - - MEMAddr - Memory Access Address - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR - 0--0x0FFFFFFF: COEF_RAM -0x10000000--0x1FFFFFFF: DATA_RAM - 0 - 32 - read-write - - - - - MEMData - Memory Access Data - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - The data write-to/read-from buffer - 0 - 32 - read-write - - - - - HPF_MA - HPF A Coef Register - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - COEF - Composite value of coef A of the Order-1 HPF - 0 - 32 - read-write - - - - - HPF_B - HPF B Coef Register - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - COEF - coef B of the Order-1 HPF - 0 - 32 - read-write - - - - - - - PWM0 - PWM0 - PWM - 0xf0200000 - - 0x0 - 0x290 - registers - - - - unlk - Shadow registers unlock register - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHUNLK - write 0xB0382607 to unlock the shadow registers of register offset from 0x04 to 0x78, -otherwise the shadow registers can not be written. - 0 - 32 - read-write - - - - - sta - Counter start register - UNION_STA - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - XSTA - pwm timer counter extended start point, should back to this value after reach xrld - 28 - 4 - read-write - - - STA - pwm timer counter start value - sta/rld will be loaded from shadow register to work register at main counter reload time, or software write unlk.shunlk - 4 - 24 - read-write - - - - - rld - Counter reload register - UNION_RLD - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - XRLD - timeout counter extended reload point, counter will reload to xsta after reach this point - 28 - 4 - read-write - - - RLD - pwm timer counter reload value - 4 - 24 - read-write - - - - - 24 - 0x4 - 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23 - CMP[%s] - no description available - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - XCMP - extended counter compare value - 28 - 4 - read-write - - - CMP - clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, -and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. - 4 - 24 - read-write - - - CMPHLF - half clock counter compare value - 3 - 1 - read-write - - - CMPJIT - jitter counter compare value - 0 - 3 - read-write - - - - - frcmd - Force output mode register - 0x78 - 32 - 0x00000000 - 0x0000FFFF - - - FRCMD - 2bit for each PWM output channel (0-7); -00: force output 0 -01: force output 1 -10: output highz -11: no force - 0 - 16 - read-write - - - - - shlk - Shadow registers lock register - 0x7c - 32 - 0x00000000 - 0x80000000 - - - SHLK - write 1 to lock all shawdow register, write access is not permitted - 31 - 1 - read-write - - - - - 24 - 0x4 - 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23 - CHCFG[%s] - no description available - 0x80 - 32 - 0x00000000 - 0xFFFF0003 - - - CMPSELEND - assign the last comparator for this output channel - 24 - 5 - read-write - - - CMPSELBEG - assign the first comparator for this output channel - 16 - 5 - read-write - - - OUTPOL - output polarity, set to 1 will invert the output - 1 - 1 - read-write - - - - - gcr - Global control register - 0xf0 - 32 - 0x00000000 - 0xFDFFFFE7 - - - FAULTI3EN - 1- enable the internal fault input 3 - 31 - 1 - read-write - - - FAULTI2EN - 1- enable the internal fault input 2 - 30 - 1 - read-write - - - FAULTI1EN - 1- enable the internal fault input 1 - 29 - 1 - read-write - - - FAULTI0EN - 1- enable the internal fault input 0 - 28 - 1 - read-write - - - DEBUGFAULT - 1- enable debug mode output protection - 27 - 1 - read-write - - - FRCPOL - polarity of input pwm_force, -1- active low -0- active high - 26 - 1 - read-write - - - HWSHDWEDG - When hardware event is selected as shawdow register effective time and the select comparator is configured as input capture mode. -This bit assign its which edge is used as compare shadow register hardware load event. -1- Falling edge -0- Rising edge - 24 - 1 - read-write - - - CMPSHDWSEL - This bitfield select one of the comparators as hardware event time to load comparator shadow registers - 19 - 5 - read-write - - - FAULTRECEDG - When hardware load is selected as output fault recover trigger and the selected channel is capture mode. -This bit assign its effective edge of fault recover trigger. -1- Falling edge -0- Rising edge - 18 - 1 - read-write - - - FAULTRECHWSEL - Selec one of the 24 comparators as fault output recover trigger. - 13 - 5 - read-write - - - FAULTE1EN - 1- enable the external fault input 1 - 12 - 1 - read-write - - - FAULTE0EN - 1- enable the external fault input 0 - 11 - 1 - read-write - - - FAULTEXPOL - external fault polarity -1-active low -0-active high - 9 - 2 - read-write - - - RLDSYNCEN - 1- pwm timer counter reset to reload value (rld) by synci is enabled - 8 - 1 - read-write - - - CEN - 1- enable the pwm timer counter -0- stop the pwm timer counter - 7 - 1 - read-write - - - FAULTCLR - 1- Write 1 to clear the fault condition. The output will recover if FAULTRECTIME is set to 2b'11. -User should write 1 to this bit after the active FAULT signal de-assert and before it re-assert again. - 6 - 1 - read-write - - - XRLDSYNCEN - 1- pwm timer extended counter (xcnt) reset to extended reload value (xrld) by synci is enabled - 5 - 1 - read-write - - - FRCTIME - This bit field select the force effective time -00: force immediately -01: force at main counter reload time -10: force at FRCSYNCI -11: no force - 1 - 2 - write-only - - - SWFRC - 1- write 1 to enable software force, if the frcsrcsel is set to 0, force will take effect - 0 - 1 - read-write - - - - - shcr - Shadow register control register - 0xf4 - 32 - 0x00000000 - 0x00001FFF - - - FRCSHDWSEL - This bitfield select one of the comparators as hardware event time to load FRCMD shadow registers - 8 - 5 - read-write - - - CNTSHDWSEL - This bitfield select one of the comparators as hardware event time to load the counter related shadow registers (STA and RLD) - 3 - 5 - read-write - - - CNTSHDWUPT - This bitfield select when the counter related shadow registers (STA and RLD) will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. - The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 1 - 2 - read-write - - - SHLKEN - 1- enable shadow registers lock feature, -0- disable shadow registers lock, shlk bit will always be 0 - 0 - 1 - read-write - - - - - 24 - 0x4 - 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23 - CAPPOS[%s] - no description available - 0x100 - 32 - 0x00000000 - 0xFFFFFFF0 - - - CAPPOS - counter value captured at input posedge - 4 - 28 - read-only - - - - - cnt - Counter - 0x170 - 32 - 0x00000000 - 0xFFFFFFFF - - - XCNT - current extended counter value - 28 - 4 - read-only - - - CNT - current clock counter value - 4 - 24 - read-only - - - - - 24 - 0x4 - 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23 - CAPNEG[%s] - no description available - 0x180 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPNEG - counter value captured at input signal falling edge - 0 - 32 - read-only - - - - - cntcopy - Counter copy - 0x1f0 - 32 - 0x00000000 - 0xFFFFFFFF - - - XCNT - current extended counter value - 28 - 4 - read-only - - - CNT - current clock counter value - 4 - 24 - read-only - - - - - 8 - 0x4 - 0,1,2,3,4,5,6,7 - PWMCFG[%s] - no description available - 0x200 - 32 - 0x00000000 - 0x1FFFFFFF - - - OEN - PWM output enable -1- output is enabled -0- output is disabled - 28 - 1 - read-write - - - FRCSHDWUPT - This bitfield select when the FRCMD shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. - The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 26 - 2 - read-write - - - FAULTMODE - This bitfield defines the PWM output status when fault condition happen -00: force output 0 -01: force output 1 -1x: output highz - 24 - 2 - read-write - - - FAULTRECTIME - This bitfield select when to recover PWM output after fault condition removed. -00: immediately -01: after pwm timer counter reload time -10: after hardware event assert, user can select one of the comparators to generate this hardware event. - The comparator can be either output compare mode or input capture mode. -11: after software write faultclr bit in GCR register - 22 - 2 - read-write - - - FRCSRCSEL - Select sources for force output -0- force output is enabled when FRCI assert -1- force output is enabled by software write swfrc to 1 - 21 - 1 - read-write - - - PAIR - 1- PWM output is in pair mode. Note the two PWM outputs need to be both set to pair mode. -0- PWM output is in indepandent mode. - 20 - 1 - read-write - - - DEADAREA - This bitfield define the PWM pair deadarea length. The unit is 0.5 cycle. The minimum length of deadarea is 1 cycle. -Note: user should configure pair bit and this bitfield before PWM output is enabled. - 0 - 20 - read-write - - - - - sr - Status register - 0x220 - 32 - 0x00000000 - 0x0FFFFFFF - - - FAULTF - fault condition flag - 27 - 1 - write-only - - - XRLDF - extended reload flag, this flag set when xcnt count to xrld value or when SYNCI assert - 26 - 1 - write-only - - - HALFRLDF - half reload flag, this flag set when cnt count to rld/2 - 25 - 1 - write-only - - - RLDF - reload flag, this flag set when cnt count to rld value or when SYNCI assert - 24 - 1 - write-only - - - CMPFX - comparator output compare or input capture flag - 0 - 24 - write-only - - - - - irqen - Interrupt request enable register - 0x224 - 32 - 0x00000000 - 0x0FFFFFFF - - - FAULTIRQE - fault condition interrupt enable - 27 - 1 - read-write - - - XRLDIRQE - extended reload flag interrupt enable - 26 - 1 - read-write - - - HALFRLDIRQE - half reload flag interrupt enable - 25 - 1 - read-write - - - RLDIRQE - reload flag interrupt enable - 24 - 1 - read-write - - - CMPIRQEX - comparator output compare or input capture flag interrupt enable - 0 - 24 - read-write - - - - - dmaen - DMA request enable register - 0x22c - 32 - 0x00000000 - 0x0FFFFFFF - - - FAULTEN - fault condition DMA request enable - 27 - 1 - read-write - - - XRLDEN - extended reload flag DMA request enable - 26 - 1 - read-write - - - HALFRLDEN - half reload flag DMA request enable - 25 - 1 - read-write - - - RLDEN - reload flag DMA request enable - 24 - 1 - read-write - - - CMPENX - comparator output compare or input capture flag DMA request enable - 0 - 24 - read-write - - - - - 24 - 0x4 - cmpcfg0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23 - CMPCFG[%s] - no description available - 0x230 - 32 - 0x00000000 - 0x000000FF - - - XCNTCMPEN - This bitfield enable the comparator to compare xcmp with xcnt. - 4 - 4 - read-write - - - CMPSHDWUPT - This bitfield select when the comparator shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. - The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 2 - 2 - read-write - - - CMPMODE - comparator mode -0- output compare mode -1- input capture mode - 1 - 1 - read-write - - - - - - - PWM1 - PWM1 - PWM - 0xf0210000 - - - PWM2 - PWM2 - PWM - 0xf0220000 - - - PWM3 - PWM3 - PWM - 0xf0230000 - - - HALL0 - HALL0 - HALL - 0xf0204000 - - 0x0 - 0x88 - registers - - - - cr - Control Register - 0x0 - 32 - 0x00000000 - 0x8001083F - - - READ - 1- load ucnt, vcnt, wcnt and tmrcnt into their read registers. Hardware auto-clear; read as 0 - 31 - 1 - write-only - - - SNAPEN - 1- load ucnt, vcnt, wcnt and tmrcnt into their snap registers when snapi input assert - 11 - 1 - read-write - - - RSTCNT - set to reset all counter and related snapshots - 4 - 1 - read-write - - - - - phcfg - Phase configure register - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - DLYSEL - This bit select delay start time: -1- start counting delay after pre-trigger -0- start counting delay after u,v,w toggle - 31 - 1 - read-write - - - DLYCNT - delay clock cycles number - 0 - 24 - read-write - - - - - wdgcfg - Watchdog configure register - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - WDGEN - 1- enable wdog counter - 31 - 1 - read-write - - - WDGTO - watch dog timeout value - 0 - 31 - read-write - - - - - uvwcfg - U,V,W configure register - 0xc - 32 - 0x00000000 - 0x07FFFFFF - - - PRECNT - the clock cycle number which the pre flag will set before the next uvw transition - 0 - 24 - read-write - - - - - trgoen - Trigger output enable register - 0x10 - 32 - 0x00000000 - 0xFFE00000 - - - WDGEN - 1- enable trigger output when wdg flag set - 31 - 1 - read-write - - - PHUPTEN - 1- enable trigger output when phupt flag set - 30 - 1 - read-write - - - PHPREEN - 1- enable trigger output when phpre flag set - 29 - 1 - read-write - - - PHDLYEN - 1- enable trigger output when phdly flag set - 28 - 1 - read-write - - - UFEN - 1- enable trigger output when u flag set - 23 - 1 - read-write - - - VFEN - 1- enable trigger output when v flag set - 22 - 1 - read-write - - - WFEN - 1- enable trigger output when w flag set - 21 - 1 - read-write - - - - - readen - Read event enable register - 0x14 - 32 - 0x00000000 - 0xFFE00000 - - - WDGEN - 1- load counters to their read registers when wdg flag set - 31 - 1 - read-write - - - PHUPTEN - 1- load counters to their read registers when phupt flag set - 30 - 1 - read-write - - - PHPREEN - 1- load counters to their read registers when phpre flag set - 29 - 1 - read-write - - - PHDLYEN - 1- load counters to their read registers when phdly flag set - 28 - 1 - read-write - - - UFEN - 1- load counters to their read registers when u flag set - 23 - 1 - read-write - - - VFEN - 1- load counters to their read registers when v flag set - 22 - 1 - read-write - - - WFEN - 1- load counters to their read registers when w flag set - 21 - 1 - read-write - - - - - dmaen - DMA enable register - 0x24 - 32 - 0x00000000 - 0xFFE00000 - - - WDGEN - 1- generate dma request when wdg flag set - 31 - 1 - read-write - - - PHUPTEN - 1- generate dma request when phupt flag set - 30 - 1 - read-write - - - PHPREEN - 1- generate dma request when phpre flag set - 29 - 1 - read-write - - - PHDLYEN - 1- generate dma request when phdly flag set - 28 - 1 - read-write - - - UFEN - 1- generate dma request when u flag set - 23 - 1 - read-write - - - VFEN - 1- generate dma request when v flag set - 22 - 1 - read-write - - - WFEN - 1- generate dma request when w flag set - 21 - 1 - read-write - - - - - sr - Status register - 0x28 - 32 - 0x00000000 - 0xFFE00000 - - - WDGF - watchdog count timeout flag - 31 - 1 - read-write - - - PHUPTF - phase update flag, will set when any of u, v, w signal toggle - 30 - 1 - read-write - - - PHPREF - phase update pre flag, will set PRECNT cycles before any of u, v, w signal toggle - 29 - 1 - read-write - - - PHDLYF - phase update delay flag, will set DLYCNT cycles after any of u, v, w signal toggle or after the phpre flag depands on DLYSEL setting - 28 - 1 - read-write - - - UF - u flag, will set when u signal toggle - 23 - 1 - read-write - - - VF - v flag, will set when v signal toggle - 22 - 1 - read-write - - - WF - w flag, will set when w signal toggle - 21 - 1 - read-write - - - - - irqen - Interrupt request enable register - 0x2c - 32 - 0x00000000 - 0xFFE00000 - - - WDGIE - 1- generate interrupt request when wdg flag set - 31 - 1 - read-write - - - PHUPTIE - 1- generate interrupt request when phupt flag set - 30 - 1 - read-write - - - PHPREIE - 1- generate interrupt request when phpre flag set - 29 - 1 - read-write - - - PHDLYIE - 1- generate interrupt request when phdly flag set - 28 - 1 - read-write - - - UFIE - 1- generate interrupt request when u flag set - 23 - 1 - read-write - - - VFIE - 1- generate interrupt request when v flag set - 22 - 1 - read-write - - - WFIE - 1- generate interrupt request when w flag set - 21 - 1 - read-write - - - - - 4 - 0x10 - current,read,snap0,snap1 - COUNT[%s] - no description available - 0x30 - - w - W counter - 0x0 - 32 - 0x00000000 - 0x0FFFFFFF - - - WCNT - wcnt counter - 0 - 28 - read-only - - - - - v - V counter - 0x4 - 32 - 0x00000000 - 0xCFFFFFFF - - - VCNT - vcnt counter - 0 - 28 - read-only - - - - - u - U counter - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIR - 1- reverse rotation -0- forward rotation - 31 - 1 - read-only - - - USTAT - this bit indicate U state - 30 - 1 - read-only - - - VSTAT - this bit indicate V state - 29 - 1 - read-only - - - WSTAT - this bit indicate W state - 28 - 1 - read-only - - - UCNT - ucnt counter - 0 - 28 - read-only - - - - - tmr - Timer counter - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - TIMER - 32 bit free run timer - 0 - 32 - read-only - - - - - - 3 - 0x8 - u,v,w - HIS[%s] - no description available - 0x70 - - his0 - history register 0 - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - UHIS0 - copy of ucnt when u signal transition from 0 to 1 - 0 - 32 - read-only - - - - - his1 - history register 1 - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - UHIS1 - copy of ucnt when u signal transition from 1 to 0 - 0 - 32 - read-only - - - - - - - - HALL1 - HALL1 - HALL - 0xf0214000 - - - HALL2 - HALL2 - HALL - 0xf0224000 - - - HALL3 - HALL3 - HALL - 0xf0234000 - - - QEI0 - QEI0 - QEI - 0xf0208000 - - 0x0 - 0x80 - registers - - - - cr - Control register - 0x0 - 32 - 0x00000000 - 0x80077F3F - - - READ - 1- load phcnt, zcnt, spdcnt and tmrcnt into their read registers. Hardware auto-clear; read as 0 - 31 - 1 - write-only - - - HRSTSPD - 1- reset spdcnt when H assert - 18 - 1 - read-write - - - HRSTPH - 1- reset phcnt when H assert - 17 - 1 - read-write - - - HRSTZ - 1- reset zcnt when H assert - 16 - 1 - read-write - - - PAUSESPD - 1- pause spdcnt when PAUSE assert - 14 - 1 - read-write - - - PAUSEPH - 1- pause phcnt when PAUSE assert - 13 - 1 - read-write - - - PAUSEZ - 1- pause zcnt when PAUSE assert - 12 - 1 - read-write - - - HRDIR1 - 1- HOMEF will set at H rising edge when dir == 1 (negative rotation direction) - 11 - 1 - read-write - - - HRDIR0 - 1- HOMEF will set at H rising edge when dir == 0 (positive rotation direction) - 10 - 1 - read-write - - - HFDIR1 - 1- HOMEF will set at H falling edge when dir == 1 (negative rotation direction) - 9 - 1 - read-write - - - HFDIR0 - 1- HOMEF will set at H falling edge when dir == 1 (positive rotation direction) - 8 - 1 - read-write - - - SNAPEN - 1- load phcnt, zcnt, spdcnt and tmrcnt into their snap registers when snapi input assert - 5 - 1 - read-write - - - RSTCNT - 1- reset zcnt, spdcnt and tmrcnt to 0. reset phcnt to phidx - 4 - 1 - read-write - - - ENCTYP - 00-abz; 01-pd; 10-ud; 11-reserved - 0 - 2 - read-write - - - - - phcfg - Phase configure register - 0x4 - 32 - 0x00000000 - 0x007FFFFF - - - ZCNTCFG - 1- zcnt will increment when phcnt upcount to phmax, decrement when phcnt downcount to 0 -0- zcnt will increment or decrement when Z input assert - 22 - 1 - read-write - - - PHCALIZ - 1- phcnt will set to phidx when Z input assert - 21 - 1 - read-write - - - PHMAX - maximum phcnt number, phcnt will rollover to 0 when it upcount to phmax - 0 - 21 - read-write - - - - - wdgcfg - Watchdog configure register - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - WDGEN - 1- enable wdog counter - 31 - 1 - read-write - - - WDGTO - watch dog timeout value - 0 - 31 - read-write - - - - - phidx - Phase index register - 0xc - 32 - 0x00000000 - 0x001FFFFF - - - PHIDX - phcnt reset value, phcnt will reset to phidx when phcaliz set to 1 - 0 - 21 - read-write - - - - - trgoen - Tigger output enable register - 0x10 - 32 - 0x00000000 - 0xF0000000 - - - WDGFEN - 1- enable trigger output when wdg flag set - 31 - 1 - read-write - - - HOMEFEN - 1- enable trigger output when homef flag set - 30 - 1 - read-write - - - POSCMPFEN - 1- enable trigger output when poscmpf flag set - 29 - 1 - read-write - - - ZPHFEN - 1- enable trigger output when zphf flag set - 28 - 1 - read-write - - - - - readen - Read event enable register - 0x14 - 32 - 0x00000000 - 0xF0000000 - - - WDGFEN - 1- load counters to their read registers when wdg flag set - 31 - 1 - read-write - - - HOMEFEN - 1- load counters to their read registers when homef flag set - 30 - 1 - read-write - - - POSCMPFEN - 1- load counters to their read registers when poscmpf flag set - 29 - 1 - read-write - - - ZPHFEN - 1- load counters to their read registers when zphf flag set - 28 - 1 - read-write - - - - - zcmp - Z comparator - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - ZCMP - zcnt postion compare value - 0 - 32 - read-write - - - - - phcmp - Phase comparator - 0x1c - 32 - 0x00000000 - 0xE01FFFFF - - - ZCMPDIS - 1- postion compare not include zcnt - 31 - 1 - read-write - - - DIRCMPDIS - 1- postion compare not include rotation direction - 30 - 1 - read-write - - - DIRCMP - 0- position compare need positive rotation -1- position compare need negative rotation - 29 - 1 - read-write - - - PHCMP - phcnt position compare value - 0 - 21 - read-write - - - - - spdcmp - Speed comparator - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - SPDCMP - spdcnt position compare value - 0 - 32 - read-write - - - - - dmaen - DMA request enable register - 0x24 - 32 - 0x00000000 - 0xF0000000 - - - WDGFEN - 1- generate dma request when wdg flag set - 31 - 1 - read-write - - - HOMEFEN - 1- generate dma request when homef flag set - 30 - 1 - read-write - - - POSCMPFEN - 1- generate dma request when poscmpf flag set - 29 - 1 - read-write - - - ZPHFEN - 1- generate dma request when zphf flag set - 28 - 1 - read-write - - - - - sr - Status register - 0x28 - 32 - 0x00000000 - 0xF0000000 - - - WDGF - watchdog flag - 31 - 1 - read-write - - - HOMEF - home flag - 30 - 1 - read-write - - - POSCMPF - postion compare match flag - 29 - 1 - read-write - - - ZPHF - z input flag - 28 - 1 - read-write - - - - - irqen - Interrupt request register - 0x2c - 32 - 0x00000000 - 0xF0000000 - - - WDGIE - 1- generate interrupt when wdg flag set - 31 - 1 - read-write - - - HOMEIE - 1- generate interrupt when homef flag set - 30 - 1 - read-write - - - POSCMPIE - 1- generate interrupt when poscmpf flag set - 29 - 1 - read-write - - - ZPHIE - 1- generate interrupt when zphf flag set - 28 - 1 - read-write - - - - - 4 - 0x10 - current,read,snap0,snap1 - COUNT[%s] - no description available - 0x30 - - z - Z counter - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - ZCNT - zcnt value - 0 - 32 - read-write - - - - - ph - Phase counter - 0x4 - 32 - 0x00000000 - 0x461FFFFF - - - DIR - 1- reverse rotation -0- forward rotation - 30 - 1 - read-only - - - ASTAT - 1- a input is high -0- a input is low - 26 - 1 - read-only - - - BSTAT - 1- b input is high -0- b input is low - 25 - 1 - read-only - - - PHCNT - phcnt value - 0 - 21 - read-only - - - - - spd - Speed counter - 0x8 - 32 - 0x00000000 - 0xEFFFFFFF - - - DIR - 1- reverse rotation -0- forward rotation - 31 - 1 - read-only - - - ASTAT - 1- a input is high -0- a input is low - 30 - 1 - read-only - - - BSTAT - 1- b input is high -0- b input is low - 29 - 1 - read-write - - - SPDCNT - spdcnt value - 0 - 28 - read-only - - - - - tmr - Timer counter - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - TMRCNT - 32 bit free run timer - 0 - 32 - read-only - - - - - - 4 - 0x4 - spdhis0,spdhis1,spdhis2,spdhis3 - SPDHIS[%s] - no description available - 0x70 - 32 - 0x00000000 - 0xFFFFFFFF - - - SPDHIS0 - copy of spdcnt, load from spdcnt after any transition from a = low, b = low - 0 - 32 - read-only - - - - - - - QEI1 - QEI1 - QEI - 0xf0218000 - - - QEI2 - QEI2 - QEI - 0xf0228000 - - - QEI3 - QEI3 - QEI - 0xf0238000 - - - TRGM0 - TRGM0 - TRGM - 0xf020c000 - - 0x0 - 0x404 - registers - - - - 20 - 0x4 - PWM_IN0,PWM_IN1,PWM_IN2,PWM_IN3,PWM_IN4,PWM_IN5,PWM_IN6,PWM_IN7,TRGM_IN0,TRGM_IN1,TRGM_IN2,TRGM_IN3,TRGM_IN4,TRGM_IN5,TRGM_IN6,TRGM_IN7,TRGM_IN8,TRGM_IN9,TRGM_IN10,TRGM_IN11 - FILTCFG[%s] - no description available - 0x0 - 32 - 0x00000000 - 0x0001FFFF - - - OUTINV - 1- Filter will invert the output -0- Filter will not invert the output - 16 - 1 - read-write - - - MODE - This bitfields defines the filter mode -000-bypass; -100-rapid change mode; -101-delay filter mode; -110-stalbe low mode; -111-stable high mode - 13 - 3 - read-write - - - SYNCEN - set to enable sychronization input signal with TRGM clock - 12 - 1 - read-write - - - FILTLEN - This bitfields defines the filter counter length. - 0 - 12 - read-write - - - - - 64 - 0x4 - TRGM_OUT0,TRGM_OUT1,TRGM_OUT2,TRGM_OUT3,TRGM_OUT4,TRGM_OUT5,TRGM_OUT6,TRGM_OUT7,TRGM_OUT8,TRGM_OUT9,TRGM_OUT10,TRGM_OUT11,TRGM_OUTX0,TRGM_OUTX1,PWM_SYNCI,PWM_FRCI,PWM_FRCSYNCI,PWM_SHRLDSYNCI,PWM_FAULTI0,PWM_FAULTI1,PWM_FAULTI2,PWM_FAULTI3,PWM_IN8,PWM_IN9,PWM_IN10,PWM_IN11,PWM_IN12,PWM_IN13,PWM_IN14,PWM_IN15,PWM_IN16,PWM_IN17,PWM_IN18,PWM_IN19,PWM_IN20,PWM_IN21,PWM_IN22,PWM_IN23,QEI_A,QEI_B,QEI_Z,QEI_H,QEI_PAUSE,QEI_SNAPI,HALL_U,HALL_V,HALL_W,HALL_SNAPI,ADC0_STRGI,ADC1_STRGI,ADC2_STRGI,ADC3_STRGI,ADCx_PTRGI0A,ADCx_PTRGI0B,ADCx_PTRGI0C,GPTMRa_SYNCI,GPTMRa_IN2,GPTMRa_IN3,GPTMRb_SYNCI,GPTMRb_IN2,GPTMRb_IN3,CMPx_WIN,CAN_PTPC0_CAP,CAN_PTPC1_CAP - TRGOCFG[%s] - no description available - 0x100 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - 4 - 0x4 - 0,1,2,3 - DMACFG[%s] - no description available - 0x200 - 32 - 0x00000000 - 0x0000001F - - - DMASRCSEL - This field selects one of the DMA requests as the DMA request output. - 0 - 5 - read-write - - - - - GCR - General Control Register - 0x400 - 32 - 0x00000000 - 0x00000FFF - - - TRGOPEN - The bitfield enable the TRGM outputs. - 0 - 12 - read-write - - - - - - - TRGM1 - TRGM1 - TRGM - 0xf021c000 - - - TRGM2 - TRGM2 - TRGM - 0xf022c000 - - - TRGM3 - TRGM3 - TRGM - 0xf023c000 - - - SYNT - SYNT - SYNT - 0xf0240000 - - 0x0 - 0x30 - registers - - - - gcr - Global control register - 0x0 - 32 - 0x00000000 - 0x00000003 - - - CRST - 1- Reset counter - 1 - 1 - read-write - - - CEN - 1- Enable counter - 0 - 1 - read-write - - - - - rld - Counter reload register - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - RLD - counter reload value - 0 - 32 - read-write - - - - - cnt - Counter - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - CNT - counter - 0 - 32 - read-only - - - - - 4 - 0x4 - 0,1,2,3 - CMP[%s] - no description available - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - CMP - comparator value, the output will assert when counter count to this value - 0 - 32 - read-write - - - - - - - LCDC - LCDC - LCDC - 0xf1000000 - - 0x0 - 0x404 - registers - - - - CTRL - Control Register - 0x0 - 32 - 0x00000000 - 0xFFF0001F - - - SW_RST - Software reset, high active. When write 1 ,all internal logical will be reset. -0b - No action -1b - All LCDC internal registers are forced into their reset state. Interface registers are not affected. - 31 - 1 - read-write - - - DISP_ON - Display panel On/Off mode. -0b - Display Off. -1b - Display On. -Display can be set off at any time, but it can only be set on after VS_BLANK status is asserted. -So a good procedure to stop and turn on the display is: -1) clr VS_BLANK status -2) assert software reset -3) de-assert software reset -4) set display off -5) check VS_BLANK status until it is asserted, -6)reset the module, change settings -7) set display on - 30 - 1 - read-write - - - LINE_PATTERN - LCDIF line output order. -000b - RGB. -001b - RBG. -010b - GBR. -011b - GRB. -100b - BRG. -101b - BGR. - 27 - 3 - read-write - - - DISP_MODE - LCDIF operating mode. -00b - Normal mode. Panel content controlled by layer configuration. -01b - Test Mode1.(BGND Color Display) -10b - Test Mode2.(Column Color Bar) -11b - Test Mode3.(Row Color Bar) - 25 - 2 - read-write - - - BGDCL4CLR - background color for clear mode when the alpha channel is 0 - 24 - 1 - read-write - - - ARQOS - ARQOS for bus fabric arbitration - 20 - 4 - read-write - - - INV_PXDATA - Indicates if value at the output (pixel data output) needs to be negated. -0b - Output is to remain same as the data inside memory -1b - Output to be negated from the data inside memory - 4 - 1 - read-write - - - INV_PXCLK - Polarity change of Pixel Clock. -0b - LCDC outputs data on the rising edge, and Display samples data on the falling edge -1b - LCDC outputs data on the falling edge, Display samples data on the rising edge - 3 - 1 - read-write - - - INV_HREF - Polarity of HREF -0b - HREF signal active HIGH, indicating active pixel data -1b - HREF signal active LOW - 2 - 1 - read-write - - - INV_VSYNC - Polarity of VSYNC -0b - VSYNC signal active HIGH -1b - VSYNC signal active LOW - 1 - 1 - read-write - - - INV_HSYNC - Polarity of HSYNC -0b - HSYNC signal active HIGH -1b - HSYNC signal active LOW - 0 - 1 - read-write - - - - - BGND_CL - Background Color Register - 0x4 - 32 - 0x00000000 - 0x00FFFFFF - - - R - Red component of the default color displayed in the sectors where no layer is active. - 16 - 8 - read-write - - - G - Green component of the default color displayed in the sectors where no layer is active. - 8 - 8 - read-write - - - B - Blue component of the default color displayed in the sectors where no layer is active. - 0 - 8 - read-write - - - - - DISP_WN_SIZE - Display Window Size Register - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - Y - Sets the display size vertical resolution in pixels. - 16 - 12 - read-write - - - X - Sets the display size horizontal resolution in pixels. - 0 - 12 - read-write - - - - - HSYNC_PARA - HSYNC Config Register - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - FP - HSYNC front-porch pulse width (in pixel clock cycles). If zero, indicates no front-porch for HSYNC - 22 - 9 - read-write - - - BP - HSYNC back-porch pulse width (in pixel clock cycles). If zero, indicates no back-porch for HSYNC - 11 - 9 - read-write - - - PW - HSYNC active pulse width (in pixel clock cycles). Pulse width has a minimum value of 1. - 0 - 9 - read-write - - - - - VSYNC_PARA - VSYNC Config Register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - FP - VSYNC front-porch pulse width (in horizontal line cycles). If zero, means no front-porch for VSYNC - 22 - 9 - read-write - - - BP - VSYNC back-porch pulse width (in horizontal line cycles). If zero, means no back-porch for VSYNC - 11 - 9 - read-write - - - PW - VSYNC active pulse width (in horizontal line cycles). Pulse width has a minimum value of 1. - 0 - 9 - read-write - - - - - DMA_ST - DMA Status Register - 0x14 - 32 - 0x00000000 - 0xFFFFFF00 - - - DMA_ERR - plane n axi error. W1C. - 24 - 8 - write-only - - - DMA1_DONE - Plane n frame 1 dma done. W1C. - 16 - 8 - write-only - - - DMA0_DONE - Plane n frame 0 dma done. W1C. - 8 - 8 - write-only - - - - - ST - Status Register - 0x18 - 32 - 0x00000000 - 0x0000000F - - - URGENT_UNDERRUN - Asserted when the output buffer urgent underrun condition encountered - 3 - 1 - write-only - - - VS_BLANK - Asserted when in vertical blanking period. At the start of VSYNC - 2 - 1 - write-only - - - UNDERRUN - Asserted when the output buffer underrun condition encountered - 1 - 1 - write-only - - - VSYNC - Asserted when in vertical blanking period. At the end of VSYNC - 0 - 1 - write-only - - - - - INT_EN - Interrupt Enable Register - 0x1c - 32 - 0x00000000 - 0xFFFFFF0F - - - DMA_ERR - Interrupt enable for DMA error - 24 - 8 - read-write - - - DMA_DONE - Interrupt enable for DMA done - 16 - 8 - read-write - - - URGENT_UNDERRUN - Asserted when the output buffer urgent underrun condition encountered - 3 - 1 - read-write - - - VS_BLANK - Interrupt enable for start of sof - 2 - 1 - read-write - - - UNDERRUN - Interrupt enable for underrun - 1 - 1 - read-write - - - VSYNC - Interrupt enable for end of sof - 0 - 1 - read-write - - - - - TXFIFO - TX FIFO Register - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - THRSH - Threshold to start the lcd raster (0--0x7F) - 0 - 8 - read-write - - - - - 8 - 0x40 - 0,1,2,3,4,5,6,7 - LAYER[%s] - no description available - 0x200 - - LAYCTRL - Layer Control Register - 0x0 - 32 - 0x00000000 - 0x000FFFFD - - - PACK_DIR - The byte sequence of the 4 bytes in a 32-bit word. -1: {A0, A1, A2, A3} byte re-ordered. -0: {A3, A2, A1, A0} the normal case with no byte re-order - 19 - 1 - read-write - - - SHADOW_LOAD_EN - Shadow Load Enable -The SHADOW_LOAD_EN bit is written to 1 by software after all DMA control registers are written. If set to 1, shadowed control registers are updated to the active control registers on internal logical VSYNC of next frame. If set to 0, shadowed control registers are not loaded into the active control registers. The previous active control register settings will be used to process the next frame. Hardware will automatically clear this bit, when the shadow registers are loaded to the active control regsisters. - 16 - 1 - read-write - - - YUV_FORMAT - The YUV422 input format selection. -00b - The YVYU422 8bit sequence is U1,Y1,V1,Y2 -01b - The YVYU422 8bit sequence is V1,Y1,U1,Y2 -10b - The YVYU422 8bit sequence is Y1,U1,Y2,V1 -11b - The YVYU422 8bit sequence is Y1,V1,Y2,U1 -If not YUV422 mode, -FORMAT[0]: asserted to exchange sequence inside the bytes. Org [15:8]-->New[8:15], Org [7:0]-->New[0:7]. (First exchange) -FORMAT[1]: asserted to exchange the sequence of the odd and even 8 bits. Org Even [7:0]-->New[15:8], Org Odd [15:8]-->New[7:0]. (Second exchange) - 14 - 2 - read-write - - - PIXFORMAT - Layer encoding format (bit per pixel) -0000b - 1 bpp (pixel width must be multiples of 32), pixel sequence is from LSB to MSB in 32b word. -0001b - 2 bpp (pixel width must be multiples of 16), pixel sequence is from LSB to MSB in 32b word. -0010b - 4 bpp (pixel width must be multiples of 8), pixel sequence is from LSB to MSB in 32b word. -0011b - 8 bpp (pixel width must be multiples of 4), pixel sequence is from LSB to MSB in 32b word. -0100b - 16 bpp (RGB565), the low byte contains the full R component. -0111b - YCbCr422 (Only layer 0/1 can support this format), byte sequence determined by LAYCTRL[YUV_FORMAT] -1001b - 32 bpp (ARGB8888), byte sequence as B,G,R,A -1011b - Y8 (pixel width must be multiples of 4), byte sequence as Y1,Y2,Y3,Y4 - 10 - 4 - read-write - - - LOCALPHA_OP - The usage of the LOCALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) -0: the LOCALPHA[7:0] is invalid, use the alpha value from the data stream -1: the LOCALPHA[7:0] is used to override the alpha value in the data stream (useful when the data stream has no alpha info) -2: the LOCALPHA[7:0] is used to scale the alpha value from the data stream -Others: Reserved - 8 - 2 - read-write - - - INALPHA_OP - The usage of the INALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) -0: the INALPHA[7:0] is invalid, use the alpha value from previous pipeline -1: the INALPHA[7:0] is used to override the alpha value from previous pipeline. (useful when the corresponding data stream has no alpha info) -2: the INALPHA[7:0] is used to scale the alpha value from previous pipeline -Others: Reserved - 6 - 2 - read-write - - - AB_MODE - Alpha Blending Mode -0: SKBlendMode_Clear; -1: SKBlendMode_Src ; -2: SKBlendMode_Dst -3: SKBlendMode_SrcOver -4: SKBlendMode_DstOver -5: SKBlendMode_SrcIn -6: SKBlendMode_DstIn -7: SKBlendMode_SrcOut -8: SKBlendMode_DstOut -9: SKBlendMode_SrcATop -10: SKBlendMode_DstATop -11: SKBlendMode_Xor -12: SKBlendMode_Plus (The conventional blending mode) -13: SKBlendMode_Modulate -14: SRC org -15: DST org -Others: Reserved. - 2 - 4 - read-write - - - EN - Asserted when the layer is enabled. If this layer is not enabled, it means a bypassing plane. - 0 - 1 - read-write - - - - - ALPHAS - Layer Alpha Register - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCD - The system alpha value for the data stream of current layer stream (SRC) - 8 - 8 - read-write - - - IND - The system alpha value for the input stream from previous stage (DST) - 0 - 8 - read-write - - - - - LAYSIZE - Layer Size Register - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - HEIGHT - Height of the layer in pixels - 16 - 12 - read-write - - - WIDTH - Width of the layer in pixels (Note: not actual width-1) -The layer width must be in multiples of the number of pixels that can be stored in 32 bits, and therefore differs depending on color encoding. For example, if 2 bits per pixel format is used, then the layer width must be configured in multiples of 16. - 0 - 12 - read-write - - - - - LAYPOS - Layer Position Register - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - Y - The vertical position of top row of the layer, where 0 is the top row of the panel, positive values are below the top row of the panel. - 16 - 16 - read-write - - - X - The horizontal position of left-hand column of the layer, where 0 is the left-hand column of the panel, positive values are to the right the left-hand column of the panel. - 0 - 16 - read-write - - - - - START0 - Layer Buffer Pointer Register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR0 - Input buffer Start address 0 - 0 - 32 - read-write - - - - - LINECFG - Layer Bus Config Register - 0x18 - 32 - 0x00000000 - 0xE0FFFFFF - - - MPT_SIZE - Maximal Per Transfer Data Size: -0: 64 bytes -1: 128 bytes -2: 256 bytes -3: 512 bytes -4: 1024 bytes - 29 - 3 - read-write - - - MAX_OT - the number of outstanding axi read transactions. -If zero, it means max 8. - 21 - 3 - read-write - - - PITCH - Number of bytes between 2 vertically adjacent pixels in system memory. Byte granularity is supported, but SW should align to 64B boundary. - 0 - 16 - read-write - - - - - BG_CL - Layer Background Color Register - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - ARGB - ARGB8888. It is only useful in the last active stage in the pipeline. - 0 - 32 - read-write - - - - - CSC_COEF0 - Layer Color Space Conversion Config Register 0 - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - YCBCR_MODE - This bit changes the behavior when performing U/V converting. -0b - Converting YUV to RGB data -1b - Converting YCbCr to RGB data - 31 - 1 - read-write - - - ENABLE - Enable the CSC unit in the LCDC plane data path. -0b - The CSC is bypassed and the input pixels are RGB data already -1b - The CSC is enabled and the pixels will be converted to RGB data -This bit will be shadowed. - 30 - 1 - read-write - - - C0 - Two's compliment Y multiplier coefficient C0. YUV=0x100 (1.000) YCbCr=0x12A (1.164) - 18 - 11 - read-write - - - UV_OFFSET - Two's compliment phase offset implicit for CbCr data UV_OFFSET. Generally used for YCbCr to RGB conversion. -YCbCr=0x180, YUV=0x000 (typically -128 or 0x180 to indicate normalized -0.5 to 0.5 range). - 9 - 9 - read-write - - - Y_OFFSET - Two's compliment amplitude offset implicit in the Y data Y_OFFSET. For YUV, this is typically 0 and for YCbCr, this is -typically -16 (0x1F0). - 0 - 9 - read-write - - - - - CSC_COEF1 - Layer Color Space Conversion Config Register 1 - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - C1 - Two's compliment Red V/Cr multiplier coefficient C1. YUV=0x123 (1.140) YCbCr=0x198 (1.596). - 16 - 11 - read-write - - - C4 - Two's compliment Blue U/Cb multiplier coefficient C4. YUV=0x208 (2.032) YCbCr=0x204 (2.017). - 0 - 11 - read-write - - - - - CSC_COEF2 - Layer Color Space Conversion Config Register 2 - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - C2 - Two's compliment Green V/Cr multiplier coefficient C2. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813). - 16 - 11 - read-write - - - C3 - Two's compliment Green U/Cb multiplier coefficient C3. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392). - 0 - 11 - read-write - - - - - - CLUT_LOAD - Clut Load Control Register - 0x400 - 32 - 0x00000000 - 0x0000007F - - - SEL_NUM - Selected CLUT Number -The SEL_CLUT_NUM is used to select which plane's CLUT need to be updated. The hardware can only backup one CLUT setting and load, so the SEL_CLUT_NUM can't be changed when CLUT_LOAD[UPDATE_EN] is 1. -. 3'h0 - PLANE 0 -. 3'h1 - PLANE 1 -. ------ -. 3'h7 - PLANE 7 -CLUT 8 can be modified via APB even when display is on. -Currently CLUT for plane 0..7 cannot be modified via APB when display is on. Can only be updated via CLUT_LOAD[UPDATE_EN] bit. - 4 - 3 - read-write - - - UPDATE_EN - CLUT Update Enable -The bit is written to 1 when software want to update the Color Look Up Tables during display. -If set to 1, software update selected CLUT due to SEL_CLUT_NUM setting, the table will be copied from CLUT8 during vertical blanking period after SHADOW_LOAD_EN is set to 1. -If set to 0, software can update CLUT8 directly according to the CLUT memory map. -Hardware will automatically clear this bit when selected CLUT is updated according to SEL_CLUT_NUM. - 0 - 1 - read-write - - - - - - - CAM0 - CAM0 - CAM - 0xf1008000 - - 0x0 - 0x490 - registers - - - - CR1 - Control Register - 0x0 - 32 - 0x00000000 - 0xBF9AAFFF - - - COLOR_EXT - If asserted, will change the output color to ARGB8888 mode. Used by input color as RGB565, RGB888, YUV888, etc. -The byte sequence is B,G,R,A. Depends on correct CR2[ClrBitFormat] configuration. - 29 - 1 - read-write - - - INV_PIXCLK - invert pixclk pad input before it is used - 28 - 1 - read-write - - - INV_HSYNC - invert hsync pad input before it is used - 27 - 1 - read-write - - - INV_VSYNC - invert vsync pad input before it is used - 26 - 1 - read-write - - - SWAP16_EN - SWAP 16-Bit Enable. This bit enables the swapping of 16-bit data. Data is packed from 8-bit or 10-bit to 32-bit first (according to the setting of PACK_DIR) and then swapped as 16-bit words before being put into the RX FIFO. The action of the bit only affects the RX FIFO. -NOTE: Example of swapping enabled: -Data input to FIFO = 0x11223344 -Data in RX FIFO = 0x 33441122 -NOTE: Example of swapping disabled: -Data input to FIFO = 0x11223344 -Data in RX FIFO = 0x11223344 -0 Disable swapping -1 Enable swapping - 25 - 1 - read-write - - - PACK_DIR - Data Packing Direction. This bit Controls how 8-bit/10-bit image data is packed into 32-bit RX FIFO. -0 Pack from LSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x44332211 in RX FIFO. -1 Pack from MSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x11223344 in RX FIFO. - 24 - 1 - read-write - - - RESTART_BUSPTR - force to restart the bus pointer at the every end of the sof period, and at the same time, clr the fifo pointer - 23 - 1 - read-write - - - ASYNC_RXFIFO_CLR - ASynchronous Rx FIFO Clear. -When asserted, this bit clears RXFIFO immediately. -It will be auto-cleared. - 20 - 1 - read-write - - - SYNC_RXFIFO_CLR - Synchronous Rx FIFO Clear. -When asserted, this bit clears RXFIFO on every SOF. - 19 - 1 - read-write - - - SOF_INT_POL - SOF Interrupt Polarity. This bit controls the condition that generates an SOF interrupt. -0 SOF interrupt is generated on SOF falling edge -1 SOF interrupt is generated on SOF rising edge - 17 - 1 - read-write - - - INV_DATA - Invert Data Input. This bit enables or disables internal inverters on the data lines. -0 CAM_D data lines are directly applied to internal circuitry -1 CAM_D data lines are inverted before applied to internal circuitry - 15 - 1 - read-write - - - STORAGE_MODE - 00: Normal Mode (one plane mode) -01: Two Plane Mode (Y, UV plane) -10: Y-only Mode, byte sequence as Y0,Y1,Y2,Y3 -11: Binary Mode, bit sequence is from LSB to MSB when CR20[BIG_END]=0 - 10 - 2 - read-write - - - COLOR_FORMATS - input color formats: -0010b:24bit:RGB888 -0011b:24bit:RGB666 -0100b:16bit:RGB565 -0101b:16bit:RGB444 -0110b:16bit:RGB555 -0111b: 16bit: YCbCr422 (Y0 Cb Y1 Cr, each 8-bit) -YUV -YCrCb -Note: YUV420 is not supported. -1000b: 24bit: YUV444 - 3 - 4 - read-write - - - SENSOR_BIT_WIDTH - the bit width of the sensor -0: 8 bits -1: 10 bits -3:24bits -Others: Undefined - 0 - 3 - read-write - - - - - INT_EN - Interrupt Enable Register - 0x4 - 32 - 0x00000000 - 0xFFFFFF5F - - - ERR_CL_BWID_CFG_INT_EN - The unsupported color (color_formats[3:0]) and bitwidth (sensor_bit_width[2:0]) configuation interrupt enable - 13 - 1 - read-write - - - HIST_DONE_INT_EN - Enable hist done int - 12 - 1 - read-write - - - HRESP_ERR_EN - Hresponse Error Enable. This bit enables the hresponse error interrupt. -0 Disable hresponse error interrupt -1 Enable hresponse error interrupt - 11 - 1 - read-write - - - EOF_INT_EN - End-of-Frame Interrupt Enable. This bit enables and disables the EOF interrupt. -0 EOF interrupt is disabled. -1 EOF interrupt is generated when RX count value is reached. - 9 - 1 - read-write - - - RF_OR_INTEN - RxFIFO Overrun Interrupt Enable. This bit enables the RX FIFO overrun interrupt. -0 RxFIFO overrun interrupt is disabled -1 RxFIFO overrun interrupt is enabled - 6 - 1 - read-write - - - FB2_DMA_DONE_INTEN - Frame Buffer2 DMA Transfer Done Interrupt Enable. This bit enables the interrupt of Frame Buffer2 DMA -transfer done. -0 Frame Buffer2 DMA Transfer Done interrupt disable -1 Frame Buffer2 DMA Transfer Done interrupt enable - 3 - 1 - read-write - - - FB1_DMA_DONE_INTEN - Frame Buffer1 DMA Transfer Done Interrupt Enable. This bit enables the interrupt of Frame Buffer1 DMA -transfer done. -0 Frame Buffer1 DMA Transfer Done interrupt disable -1 Frame Buffer1 DMA Transfer Done interrupt enable - 2 - 1 - read-write - - - SOF_INT_EN - Start Of Frame (SOF) Interrupt Enable. This bit enables the SOF interrupt. -0 SOF interrupt disable -1 SOF interrupt enable - 0 - 1 - read-write - - - - - CR2 - Control 2 Register - 0x10 - 32 - 0x00000000 - 0xFFFF8FEF - - - FRMCNT_15_0 - Frame Counter. This is a 16-bit Frame Counter -(Wraps around automatically after reaching the maximum) - 16 - 16 - read-only - - - FRMCNT_RST - Frame Count Reset. Resets the Frame Counter. -0 Do not reset -1 Reset frame counter immediately - 15 - 1 - read-write - - - RXFF_LEVEL - RxFIFO Full Level. When the number of data in RxFIFO reaches this level, a RxFIFO full interrupt is generated, or an RXFIFO DMA request is sent. -000 4 Double words -001 8 Double words -010 16 Double words -011 24 Double words -100 32 Double words -101 48 Double words -110 64 Double words -111 96 Double words - 9 - 3 - read-write - - - DMA_REQ_EN_RFF - DMA Request Enable for RxFIFO. This bit enables the dma request from RxFIFO to the embedded DMA controller. -0 Disable the dma request -1 Enable the dma request. The UV Rx FIFO is only enabled to filling data in 2 plane mode. - 5 - 1 - read-write - - - CLRBITFORMAT - Input Byte & bit sequence same as OV5640, except for Raw mode. Used only for internal ARGB conversion. - 0 - 4 - read-write - - - - - STA - Status Register - 0x24 - 32 - 0x00000000 - 0xFFFFA7FC - - - ERR_CL_BWID_CFG - The unsupported color (color_formats[3:0]) and bitwidth (sensor_bit_width[2:0]) configuation found - 19 - 1 - write-only - - - HIST_DONE - hist cal done - 18 - 1 - write-only - - - RF_OR_INT - RxFIFO Overrun Interrupt Status. Indicates the overflow status of the RxFIFO register. (Cleared by writing -1) -0 RXFIFO has not overflowed. -1 RXFIFO has overflowed. - 13 - 1 - write-only - - - DMA_TSF_DONE_FB2 - DMA Transfer Done in Frame Buffer2. Indicates that the DMA transfer from RxFIFO to Frame Buffer2 is completed. It can trigger an interrupt if the corresponding enable bit is set in CAM_CR1. This bit can be cleared by by writing 1 or reflashing the RxFIFO dma controller in CAM_CR3. (Cleared by writing 1) -0 DMA transfer is not completed. -1 DMA transfer is completed. - 10 - 1 - write-only - - - DMA_TSF_DONE_FB1 - DMA Transfer Done in Frame Buffer1. Indicates that the DMA transfer from RxFIFO to Frame Buffer1 is completed. It can trigger an interrupt if the corresponding enable bit is set in CAM_CR1. This bit can be cleared by by writing 1 or reflashing the RxFIFO dma controller in CAM_CR3. (Cleared by writing 1) -0 DMA transfer is not completed. -1 DMA transfer is completed. - 9 - 1 - write-only - - - EOF_INT - End of Frame (EOF) Interrupt Status. Indicates when EOF is detected. (Cleared by writing 1) -0 EOF is not detected. -1 EOF is detected. - 7 - 1 - write-only - - - SOF_INT - Start of Frame Interrupt Status. Indicates when SOF is detected. (Cleared by writing 1) -0 SOF is not detected. -1 SOF is detected. - 6 - 1 - write-only - - - HRESP_ERR_INT - Hresponse Error Interrupt Status. Indicates that a hresponse error has been detected. (Cleared by writing -1) -0 No hresponse error. -1 Hresponse error is detected. - 2 - 1 - write-only - - - - - DMASA_FB1 - Pixel DMA Frame Buffer 1 Address - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - PTR - DMA Start Address in Frame Buffer1. Indicates the start address to write data. The embedded DMA controller will read data from RxFIFO and write it from this address through AHB bus. The address should be double words aligned. -In Two-Plane Mode, Y buffer1 - 2 - 30 - read-write - - - - - DMASA_FB2 - Pixel DMA Frame Buffer 2 Address - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - PTR - DMA Start Address in Frame Buffer2. Indicates the start address to write data. The embedded DMA controller will read data from RxFIFO and write it from this address through AHB bus. The address should be double words aligned. -In Two-Plane Mode, Y buffer2 - 2 - 30 - read-write - - - - - BUF_PARA - Buffer Parameters Register - 0x38 - 32 - 0x00000000 - 0xFFFFFFFF - - - LINEBSP_STRIDE - Line Blank Space Stride. Indicates the space between the end of line image storage and the start of a new line storage in the frame buffer. -The width of the line storage in frame buffer(in double words) minus the width of the image(in double words) is the stride. The stride should be double words aligned. The embedded DMA controller will skip the stride before starting to write the next row of the image. - 0 - 16 - read-write - - - - - IDEAL_WN_SIZE - Ideal Image Size Register - 0x3c - 32 - 0x00000000 - 0xFFFFFFFF - - - HEIGHT - Image Height. Indicates how many active pixels in a column of the image from the sensor. - 16 - 16 - read-write - - - WIDTH - Image Width. Indicates how many active pixels in a line of the image from the sensor. -The number of bytes to be transferred is re-calculated automatically in hardware based on cr1[color_ext] and cr1[store_mode]. Default value is 2*pixel number. -As the input data from the sensor is 8-bit/pixel format, the IMAGE_WIDTH should be a multiple of 8 pixels. - 0 - 16 - read-write - - - - - CR18 - Control CR18 Register - 0x4c - 32 - 0x00000000 - 0xFFFFE7BF - - - CAM_ENABLE - CAM global enable signal. Only when this bit is 1, CAM can start to receive the data and store to memory. - 31 - 1 - read-write - - - AWQOS - AWQOS for bus fabric arbitration - 7 - 4 - read-write - - - - - DMASA_UV1 - Pixel UV DMA Frame Buffer 1 Address - 0x50 - 32 - 0x00000000 - 0xFFFFFFFF - - - PTR - Two Plane UV Buffer Start Address 1 - 2 - 30 - read-write - - - - - DMASA_UV2 - Pixel UV DMA Frame Buffer 2 Address - 0x54 - 32 - 0x00000000 - 0xFFFFFFFF - - - PTR - Two Plane UV Buffer Start Address 2 - 2 - 30 - read-write - - - - - CR20 - Control CR20 Register - 0x58 - 32 - 0x00000000 - 0xFFFFFFFF - - - BINARY_EN - binary picture output enable - 31 - 1 - read-write - - - HISTOGRAM_EN - histogarm enable - 30 - 1 - read-write - - - BIG_END - Asserted when binary output is in big-endian type, which mean the right most data is at the LSBs. Take function only inside the 32-bit word. - 8 - 1 - read-write - - - THRESHOLD - Threshold to generate binary color. Bin 1 is output if the pixel is greater than the threshold. - 0 - 8 - read-write - - - - - CSC_COEF0 - Color Space Conversion Config Register 0 - 0x70 - 32 - 0x00000000 - 0xFFFFFFFF - - - YCBCR_MODE - This bit changes the behavior when performing U/V converting. -0b - Converting YUV to RGB data -1b - Converting YCbCr to RGB data - 31 - 1 - read-write - - - ENABLE - Enable the CSC unit -0b - The CSC is bypassed and the input pixels are RGB data already -1b - The CSC is enabled and the pixels will be converted to RGB data - 30 - 1 - read-write - - - C0 - Two's compliment Y multiplier coefficient. YUV=0x100 (1.000) YCbCr=0x12A (1.164) - 18 - 11 - read-write - - - UV_OFFSET - Two's compliment phase offset implicit for CbCr data. Generally used for YCbCr to RGB conversion. -YCbCr=0x180, YUV=0x000 (typically -128 or 0x180 to indicate normalized -0.5 to 0.5 range). - 9 - 9 - read-write - - - Y_OFFSET - Two's compliment amplitude offset implicit in the Y data. For YUV, this is typically 0 and for YCbCr, this is -typically -16 (0x1F0). - 0 - 9 - read-write - - - - - CSC_COEF1 - Color Space Conversion Config Register 1 - 0x74 - 32 - 0x00000000 - 0xFFFFFFFF - - - C1 - Two's compliment Red V/Cr multiplier coefficient. YUV=0x123 (1.140) YCbCr=0x198 (1.596). - 16 - 11 - read-write - - - C4 - Two's compliment Blue U/Cb multiplier coefficient. YUV=0x208 (2.032) YCbCr=0x204 (2.017). - 0 - 11 - read-write - - - - - CSC_COEF2 - Color Space Conversion Config Register 2 - 0x78 - 32 - 0x00000000 - 0xFFFFFFFF - - - C2 - Two's compliment Green V/Cr multiplier coefficient. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813). - 16 - 11 - read-write - - - C3 - Two's compliment Green U/Cb multiplier coefficient. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392). - 0 - 11 - read-write - - - - - CLRKEY_LOW - Low Color Key Register - 0x7c - 32 - 0x00000000 - 0xFFFFFFFF - - - LIMIT - Low range of color key applied to PS buffer. To disable PS colorkeying, set the low colorkey to 0xFFFFFF and the high colorkey to 0x000000. - 0 - 24 - read-write - - - - - CLRKEY_HIGH - High Color Key Register - 0x80 - 32 - 0x00000000 - 0xFFFFFFFF - - - LIMIT - Low range of color key applied to PS buffer. To disable PS colorkeying, set the low colorkey to 0xFFFFFF and the high colorkey to 0x000000. - 0 - 24 - read-write - - - - - 256 - 0x4 - DATA0,DATA1,DATA2,DATA3,DATA4,DATA5,DATA6,DATA7,DATA8,DATA9,DATA10,DATA11,DATA12,DATA13,DATA14,DATA15,DATA16,DATA17,DATA18,DATA19,DATA20,DATA21,DATA22,DATA23,DATA24,DATA25,DATA26,DATA27,DATA28,DATA29,DATA30,DATA31,DATA32,DATA33,DATA34,DATA35,DATA36,DATA37,DATA38,DATA39,DATA40,DATA41,DATA42,DATA43,DATA44,DATA45,DATA46,DATA47,DATA48,DATA49,DATA50,DATA51,DATA52,DATA53,DATA54,DATA55,DATA56,DATA57,DATA58,DATA59,DATA60,DATA61,DATA62,DATA63,DATA64,DATA65,DATA66,DATA67,DATA68,DATA69,DATA70,DATA71,DATA72,DATA73,DATA74,DATA75,DATA76,DATA77,DATA78,DATA79,DATA80,DATA81,DATA82,DATA83,DATA84,DATA85,DATA86,DATA87,DATA88,DATA89,DATA90,DATA91,DATA92,DATA93,DATA94,DATA95,DATA96,DATA97,DATA98,DATA99,DATA100,DATA101,DATA102,DATA103,DATA104,DATA105,DATA106,DATA107,DATA108,DATA109,DATA110,DATA111,DATA112,DATA113,DATA114,DATA115,DATA116,DATA117,DATA118,DATA119,DATA120,DATA121,DATA122,DATA123,DATA124,DATA125,DATA126,DATA127,DATA128,DATA129,DATA130,DATA131,DATA132,DATA133,DATA134,DATA135,DATA136,DATA137,DATA138,DATA139,DATA140,DATA141,DATA142,DATA143,DATA144,DATA145,DATA146,DATA147,DATA148,DATA149,DATA150,DATA151,DATA152,DATA153,DATA154,DATA155,DATA156,DATA157,DATA158,DATA159,DATA160,DATA161,DATA162,DATA163,DATA164,DATA165,DATA166,DATA167,DATA168,DATA169,DATA170,DATA171,DATA172,DATA173,DATA174,DATA175,DATA176,DATA177,DATA178,DATA179,DATA180,DATA181,DATA182,DATA183,DATA184,DATA185,DATA186,DATA187,DATA188,DATA189,DATA190,DATA191,DATA192,DATA193,DATA194,DATA195,DATA196,DATA197,DATA198,DATA199,DATA200,DATA201,DATA202,DATA203,DATA204,DATA205,DATA206,DATA207,DATA208,DATA209,DATA210,DATA211,DATA212,DATA213,DATA214,DATA215,DATA216,DATA217,DATA218,DATA219,DATA220,DATA221,DATA222,DATA223,DATA224,DATA225,DATA226,DATA227,DATA228,DATA229,DATA230,DATA231,DATA232,DATA233,DATA234,DATA235,DATA236,DATA237,DATA238,DATA239,DATA240,DATA241,DATA242,DATA243,DATA244,DATA245,DATA246,DATA247,DATA248,DATA249,DATA250,DATA251,DATA252,DATA253,DATA254,DATA255 - HISTOGRAM_FIFO[%s] - no description available - 0x90 - 32 - 0x00000000 - 0xFFFFFFFF - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - - - CAM1 - CAM1 - CAM - 0xf100c000 - - - PDMA - PDMA - PDMA - 0xf1010000 - - 0x0 - 0xc0 - registers - - - - CTRL - Control Register - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - ARQOS - QoS for AXI read bus - 19 - 4 - read-write - - - AWQOS - QoS for AXI write bus - 15 - 4 - read-write - - - PACK_DIR - Decide the byte sequence of the 32-bit output word {A3, A2, A1, A0}. The bit sequence ina byte is not changed. -2'b00: no change {A3, A2, A1, A0} -2'b01: {A2, A3, A0, A1} -2'b10: {A1, A0, A3, A2} -2'b11: {A0, A1, A2, A3} - 13 - 2 - read-write - - - AXIERR_IRQ_EN - Enable interrupt of AXI bus error - 12 - 1 - read-write - - - PDMA_DONE_IRQ_EN - Enable interrupt of PDMA_DONE - 11 - 1 - read-write - - - CLKGATE - Assert this bit to gate off clock when the module is not working. If reset to zero, the internal clock is always on. - 9 - 1 - read-write - - - IRQ_EN - Enable normal interrupt - 6 - 1 - read-write - - - BS16 - Asserted when the Block Size is 16x16, else 8x8 - 5 - 1 - read-write - - - P1_EN - Plane 1 Enable - 4 - 1 - read-write - - - P0_EN - Plane 0 Enable - 3 - 1 - read-write - - - PDMA_SFTRST - Software Reset. -Write 1 to clear PDMA internal logic. -Write 0 to exit software reset mode. - 1 - 1 - read-write - - - PDMA_EN - 1b - Enabled - 0 - 1 - read-write - - - - - STAT - Status Register - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - BLOCKY - Y block that is processing - 24 - 8 - read-only - - - BLOCKX - X block that is processing - 16 - 8 - read-only - - - PDMA_DONE - PDMA one image done - 9 - 1 - write-only - - - AXI_ERR_ID - AXI error ID - 5 - 4 - read-only - - - AXI_0_WRITE_ERR - AXI0 write err - 4 - 1 - write-only - - - AXI_1_READ_ERR - AXI1 read err - 3 - 1 - write-only - - - AXI_0_READ_ERR - AXI0 read err - 2 - 1 - write-only - - - IRQ - Asserted to indicate a IRQ event - 0 - 1 - read-only - - - - - OUT_CTRL - Out Layer Control Register - 0x8 - 32 - 0x00000000 - 0xFFFFFF3F - - - DSTALPHA - The destination (P1) system ALPHA value. - 24 - 8 - read-write - - - SRCALPHA - The source (P0) system ALPHA value. - 16 - 8 - read-write - - - DSTALPHA_OP - The usage of the DSTALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel embedded in the stream indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) -0: the DSTALPHA[7:0] is invalid, use the alpha value embedded in the stream -1: the DSTALPHA[7:0] is used to override the alpha value embedded in the stream. (useful when the corresponding data stream has no alpha info) -2: the DSTALPHA[7:0] is used to scale the alpha value embedded in the stream -Others: Reserved - 14 - 2 - read-write - - - SRCALPHA_OP - The usage of the SRCALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel embedded in the stream indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) -0: the SRCALPHA[7:0] is invalid, use the alpha value embedded in the stream -1: the SRCALPHA[7:0] is used to override the alpha value embedded in the stream . (useful when the corresponding data stream has no alpha info) -2: the SRCALPHA[7:0] is used to scale the alpha value embedded in the stream -Others: Reserved - 12 - 2 - read-write - - - ABLEND_MODE - Alpha Blending Mode -0: SKBlendMode_Clear (If PS1_CTRL[BKGNDCL4CLR] is asserted, use PS1_BKGRND color to fill the range determined by PS1, else fill the range determined by PS1 with zero); -1: SKBlendMode_Src ; -2: SKBlendMode_Dst -3: SKBlendMode_SrcOver -4: SKBlendMode_DstOver -5: SKBlendMode_SrcIn -6: SKBlendMode_DstIn -7: SKBlendMode_SrcOut -8: SKBlendMode_DstOut -9: SKBlendMode_SrcATop -10: SKBlendMode_DstATop -11: SKBlendMode_Xor -12: SKBlendMode_Plus (The conventional belding mode) -13: SKBlendMode_Modulate -14: SRC org -15: DST org -Others: Reserved. - 8 - 4 - read-write - - - FORMAT - Output buffer format. -0x0 ARGB8888 - 32-bit pixles, byte sequence as B,G,R,A -0xE RGB565 - 16-bit pixels, byte sequence as B,R -0x12 UYVY1P422 - 16-bit pixels (1-plane , byte sequence as U0,Y0,V0,Y1) - 0 - 6 - read-write - - - - - OUT_BUF - Output buffer address - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR - Current address pointer for the output frame buffer. The address can have any byte alignment. 64B alignment is recommended for optimal performance. - 0 - 32 - read-write - - - - - OUT_PITCH - Outlayer Pitch Register - 0x14 - 32 - 0x00000000 - 0x0000FFFF - - - BYTELEN - Indicates the number of bytes in memory between two vertically adjacent pixels. - 0 - 16 - read-write - - - - - OUT_LRC - Output Lower Right Corner Register - 0x18 - 32 - 0x00000000 - 0x3FFF3FFF - - - Y - This field indicates the lower right Y-coordinate (in pixels) of the output frame buffer. -The value is the height of the output image size. - 16 - 14 - read-write - - - X - This field indicates the lower right X-coordinate (in pixels) of the output frame buffer. -Should be the width of the output image size. - 0 - 14 - read-write - - - - - 2 - 0x8 - 0,1 - OUT_PS[%s] - no description available - 0x1c - - ULC - Layer Upper Left Corner Register - 0x0 - 32 - 0x00000000 - 0x3FFF3FFF - - - Y - This field indicates the upper left Y-coordinate (in pixels) of the processed surface in the output frame buffer. - 16 - 14 - read-write - - - X - This field indicates the upper left X-coordinate (in pixels) of the processed surface in the output frame buffer. - 0 - 14 - read-write - - - - - LRC - Layer Lower Right Corner Register - 0x4 - 32 - 0x00000000 - 0x3FFF3FFF - - - Y - This field indicates the lower right Y-coordinate (in pixels) of the processed surface in the output frame buffer. - 16 - 14 - read-write - - - X - This field indicates the lower right X-coordinate (in pixels) of the processed surface in the output frame buffer. - 0 - 14 - read-write - - - - - - 2 - 0x30 - 0,1 - PS[%s] - no description available - 0x30 - - CTRL - Layer Control Register - 0x0 - 32 - 0x00000000 - 0x001FFFFF - - - INB13_SWAP - Swap bit[31:24] and bit [15:8] before pack_dir operation. - 20 - 1 - read-write - - - PACK_DIR - Decide the byte sequence of the 32-bit word {A3, A2, A1, A0}. The bit sequence ina byte is not changed. -2'b00: no change {A3, A2, A1, A0} -2'b01: {A2, A3, A0, A1} -2'b10: {A1, A0, A3, A2} -2'b11: {A0, A1, A2, A3} - 18 - 2 - read-write - - - BKGCL4CLR - Enable to use background color for clear area - 17 - 1 - read-write - - - YCBCR_MODE - YCbCr mode or YUV mode - 16 - 1 - read-write - - - BYPASS - Asserted to bypass the CSC stage - 15 - 1 - read-write - - - VFLIP - Indicates that the input should be flipped vertically (effect applied before rotation). - 14 - 1 - read-write - - - HFLIP - Indicates that the input should be flipped horizontally (effect applied before rotation). - 13 - 1 - read-write - - - ROTATE - Indicates the clockwise rotation to be applied at the input buffer. The rotation effect is defined as occurring -after the FLIP_X and FLIP_Y permutation. -0x0 ROT_0 -0x1 ROT_90 -0x2 ROT_180 -0x3 ROT_270 - 11 - 2 - read-write - - - DECY - Verticle pre decimation filter control. -0x0 DISABLE - Disable pre-decimation filter. -0x1 DECY2 - Decimate PS by 2. -0x2 DECY4 - Decimate PS by 4. -0x3 DECY8 - Decimate PS by 8. - 9 - 2 - read-write - - - DECX - Horizontal pre decimation filter control. -0x0 DISABLE - Disable pre-decimation filter. -0x1 DECX2 - Decimate PS by 2. -0x2 DECX4 - Decimate PS by 4. -0x3 DECX8 - Decimate PS by 8. - 7 - 2 - read-write - - - HW_BYTE_SWAP - Swap bytes in half-words. For each 16 bit half-word, the two bytes will be swapped. - 6 - 1 - read-write - - - FORMAT - PS buffer format. To select between YUV and YCbCr formats, see bit 16 of this register. -0x0 ARGB888 - 32-bit pixels, byte sequence as B,G,R,A -0xE RGB565 - 16-bit pixels, byte sequence as B,R -0x13 YUYV1P422 - 16-bit pixels (1-plane byte sequence Y0,U0,Y1,V0 interleaved bytes) - 0 - 6 - read-write - - - - - BUF - Layer data buffer address - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR - Address pointer for the PS RGB or Y (luma) input buffer. - 0 - 32 - read-write - - - - - PITCH - Layer data pitch register - 0x10 - 32 - 0x00000000 - 0x0000FFFF - - - BYTELEN - Indicates the number of bytes in memory between two vertically adjacent pixels. - 0 - 16 - read-write - - - - - BKGD - Layer background color register - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - COLOR - Background color (in 32bpp format) for any pixels not within the scaled range of the picture, but within the buffer range specified by the PS ULC/LRC. The top 8-bit is the alpha channel. - 0 - 32 - read-write - - - - - SCALE - Layer scale register - 0x18 - 32 - 0x00000000 - 0x7FFF7FFF - - - Y - This is a two bit integer and 12 bit fractional representation (##.####_####_####) of the X scaling factor for the PS source buffer. The maximum value programmed should be 2 since scaling down by a factor greater than 2 is not supported with the bilinear filter. Decimation and the bilinear filter should be used together to achieve scaling by more than a factor of 2. - 16 - 15 - read-write - - - X - This is a two bit integer and 12 bit fractional representation (##.####_####_####) of the Y scaling factor for the PS source buffer. The maximum value programmed should be 2 since scaling down by a factor greater than 2 is not supported with the bilinear filter. Decimation and the bilinear filter should be used together to achieve scaling by more than a factor of 2. - 0 - 15 - read-write - - - - - OFFSET - Layer offset register - 0x1c - 32 - 0x00000000 - 0x0FFF0FFF - - - Y - This is a 12 bit fractional representation (0.####_####_####) of the Y scaling offset. This represents a fixed pixel offset which gets added to the scaled address to determine source data for the scaling engine. -It is applied after the decimation filter stage, and before the bilinear filter stage. - 16 - 12 - read-write - - - X - This is a 12 bit fractional representation (0.####_####_####) of the X scaling offset. This represents a fixed pixel offset which gets added to the scaled address to determine source data for the scaling engine. -It is applied after the decimation filter stage, and before the bilinear filter stage. - 0 - 12 - read-write - - - - - CLRKEY_LOW - Layer low color key register - 0x20 - 32 - 0x00000000 - 0x00FFFFFF - - - LIMIT - Low range of color key applied to PS buffer. To disable PS colorkeying, set the low colorkey to 0xFFFFFF and the high colorkey to 0x000000. - 0 - 24 - read-write - - - - - CLRKEY_HIGH - Layer high color key register - 0x24 - 32 - 0x00000000 - 0x00FFFFFF - - - LIMIT - High range of color key applied to PS buffer. To disable PS colorkeying, set the low colorkey to 0xFFFFFF and the high colorkey to 0x000000 - 0 - 24 - read-write - - - - - ORG - Layer original size register - 0x28 - 32 - 0x00000000 - 0x3FFF3FFF - - - HIGHT - The number of vertical pixels of the original frame (not -1) - 16 - 14 - read-write - - - WIDTH - The number of horizontal pixels of the original frame (not -1) - 0 - 14 - read-write - - - - - - YUV2RGB_COEF0 - YUV2RGB coefficients register 0 - 0xa0 - 32 - 0x00000000 - 0x1FFFFFFF - - - C0 - Two's compliment Y multiplier coefficient C0. YUV=0x100 (1.000) YCbCr=0x12A (1.164) - 18 - 11 - read-write - - - UV_OFFSET - Two's compliment phase offset implicit for CbCr data UV_OFFSET. Generally used for YCbCr to RGB conversion. -YCbCr=0x180, YUV=0x000 (typically -128 or 0x180 to indicate normalized -0.5 to 0.5 range). - 9 - 9 - read-write - - - Y_OFFSET - Two's compliment amplitude offset implicit in the Y data Y_OFFSET. For YUV, this is typically 0 and for YCbCr, this is -typically -16 (0x1F0). - 0 - 9 - read-write - - - - - YUV2RGB_COEF1 - YUV2RGB coefficients register 1 - 0xa4 - 32 - 0x00000000 - 0x07FF07FF - - - C1 - Two's compliment Red V/Cr multiplier coefficient C1. YUV=0x123 (1.140) YCbCr=0x198 (1.596). - 16 - 11 - read-write - - - C4 - Two's compliment Blue U/Cb multiplier coefficient C4. YUV=0x208 (2.032) YCbCr=0x204 (2.017). - 0 - 11 - read-write - - - - - YUV2RGB_COEF2 - YUV2RGB coefficients register 2 - 0xa8 - 32 - 0x00000000 - 0x07FF07FF - - - C2 - Two's compliment Green V/Cr multiplier coefficient C2. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813). - 16 - 11 - read-write - - - C3 - Two's compliment Green U/Cb multiplier coefficient C3. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392). - 0 - 11 - read-write - - - - - RGB2YUV_COEF0 - RGB2YUV coefficients register 0 - 0xac - 32 - 0x00000000 - 0xFFFFFFFF - - - YCBCR_MODE - Asserted to use YCrCb mode - 31 - 1 - read-write - - - ENABLE - Asserted to enable this RGB2YUV CSC stage - 30 - 1 - read-write - - - C0 - CSC parameters C0 - 18 - 11 - read-write - - - UV_OFFSET - CSC parameters UV_OFFSET - 9 - 9 - read-write - - - Y_OFFSET - CSC parameters Y_OFFSET - 0 - 9 - read-write - - - - - RGB2YUV_COEF1 - RGB2YUV coefficients register 1 - 0xb0 - 32 - 0x00000000 - 0x07FF07FF - - - C1 - CSC parameters C1 - 16 - 11 - read-write - - - C4 - CSC parameters C4 - 0 - 11 - read-write - - - - - RGB2YUV_COEF2 - RGB2YUV coefficients register 2 - 0xb4 - 32 - 0x00000000 - 0x07FF07FF - - - C2 - CSC parameters C2 - 16 - 11 - read-write - - - C3 - CSC parameters C3 - 0 - 11 - read-write - - - - - RGB2YUV_COEF3 - RGB2YUV coefficients register 3 - 0xb8 - 32 - 0x00000000 - 0x07FF07FF - - - C6 - CSC parameters C6 - 16 - 11 - read-write - - - C5 - CSC parameters C5 - 0 - 11 - read-write - - - - - RGB2YUV_COEF4 - RGB2YUV coefficients register 4 - 0xbc - 32 - 0x00000000 - 0x07FF07FF - - - C8 - CSC parameters C8 - 16 - 11 - read-write - - - C7 - CSC parameters C7 - 0 - 11 - read-write - - - - - - - JPEG - JPEG - JPEG - 0xf1014000 - - 0x0 - 0xa0 - registers - - - - InDMA_MISC - In DMA Misc Control Register - 0x0 - 32 - 0x00000000 - 0xFFFFFFFC - - - ARQOS - QoS for AXI read channel - 19 - 4 - read-write - - - MAX_OT - max_ot when input are RGB pixels. -For 16 bits per pixel, it can be set as 4. -For 32 bits per pixel, it will be set as 2. - 15 - 4 - read-write - - - INB13_SWAP - Swap bit[31:24] and bit [15:8] before pack dir operation. Only work for pixel data. - 14 - 1 - read-write - - - PACK_DIR - Decide the byte sequence of the 32-bit word {A3, A2, A1, A0}. The bit sequence in a byte is not changed. Only work for pixel data. -2'b00: no change {A3, A2, A1, A0} -2'b01: {A2, A3, A0, A1} -2'b10: {A1, A0, A3, A2} -2'b11: {A0, A1, A2, A3} - 12 - 2 - read-write - - - INDMA_RENEW - Renew In DMA. Default is to continue the write address counter when a new DMA request comes. Asserted to reset the write address counter. - 11 - 1 - read-write - - - NXT_IRQ_EN - In DMA Next Interrupt Enable - 10 - 1 - read-write - - - IN_DMA_DONE_IRQ_EN - In DMA Done enable - 9 - 1 - read-write - - - AXI_ERR_IRQ_EN - In DMA axi bus error inetrrupt enable - 8 - 1 - read-write - - - IRQ_EN - interrupt enable for all interrupt sources of In DMA module - 7 - 1 - read-write - - - IN_DMA_ID - 0: Pixel (In) -1: ECS (In) -2: Qmem -3: HuffEnc -4: HuffMin -5: HuffBase -6: HuffSymb - 4 - 3 - read-write - - - IN_DMA_REQ - Asserted to request DMA. Automatically clear after DMA is done. - 3 - 1 - read-write - - - INDMA2D - Asserted if In_DMA_ID=Pixel. - 2 - 1 - read-write - - - - - InDMABase - In DMA Buf Address - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR - Y plane (or Encoded Bit Plane) - 0 - 32 - read-write - - - - - InDMA_Ctrl0 - In DMA Buf Control 0 Register - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - TTLEN - Total length (Low 16 bits) in Bytes -1 for transfer when In_DMA_ID!=Pixel. - 16 - 16 - read-write - - - PITCH - Pitch between the starting point of Rows. Only active when In_DMA_ID=Pixel.. - 0 - 16 - read-write - - - - - InDMA_Ctrl1 - In DMA Buf Control 1 Register - 0x10 - 32 - 0x00000000 - 0x0000FFFF - - - ROWLEN - Total length (High 16 bits) in Bytes -1 for transfer. See reference in InDMA_Ctrl0[TTLEN] - 0 - 16 - read-write - - - - - INXT_CMD - In DMA Next Command Register - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR - The address pointing to the next command - 2 - 30 - read-write - - - OP_VALID - asserted if there is either a DATA DMA phase or NXTCMD phase. Automatically cleared. Will trigger the InDMA transfer if CFG[JPEG_EN] is 1. - 1 - 1 - read-write - - - EN - NXTCMD phase Enable Bit - 0 - 1 - read-write - - - - - OutDMA_MISC - Out DMA Misc Control Register - 0x20 - 32 - 0x00000000 - 0xFFFFFFFC - - - AWQOS - No description available - 14 - 4 - read-write - - - PACK_DIR - Decide the byte sequence of the 32-bit word {A3, A2, A1, A0}. The bit sequence in a byte is not changed. All outdma data are impacted. -2'b00: no change {A3, A2, A1, A0} (This is used for ecs stream) -2'b01: {A2, A3, A0, A1} -2'b10: {A1, A0, A3, A2} -2'b11: {A0, A1, A2, A3} - 12 - 2 - read-write - - - EN_OUTCNT - Enable output counter (unit as bytes) - 11 - 1 - read-write - - - INI_OUTCNT - Asserted to ini output counter - 10 - 1 - read-write - - - ADD_ODMA_ENDINGS - Add 0xFFD9 to the ending of the odma stream when all original image pixels are processed by the encoder module. - 9 - 1 - read-write - - - NXT_IRQ_EN - Out DMA Next Interrupt Enable - 8 - 1 - read-write - - - OUT_DMA_DONE_IRQ_EN - Out DMA Done interrupt Enable - 7 - 1 - read-write - - - AXI_ERR_IRQ_EN - Out DMA axi bus error inetrrupt enable - 6 - 1 - read-write - - - IRQ_EN - interrupt enable for all interrupt sources of Out DMA module - 5 - 1 - read-write - - - OUT_DMA_ID - 0: Pixel (Out) -1: ECS (Out) - 4 - 1 - read-write - - - OUT_DMA_REQ - Asserted to enable Out DMA request - 3 - 1 - read-write - - - OUTDMA2D - Asserted if Out_DMA_ID==Pixel - 2 - 1 - read-write - - - - - OutDMABase - Out DMA Buf Address - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR - Y plane (or Encoded Bit Plane) - 0 - 32 - read-write - - - - - OutDMA_Ctrl0 - Out DMA Buf Control 0 Register - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - TTLEN - Total length (Low 16 bits) in Bytes -1 for transfer when Out_DMA_ID!=Pixel. If Out_DMA_ID=ECS, it can be any value greater than the length of the ECS, for example, the number of encoded bytes. - 16 - 16 - read-write - - - PITCH - Pitch between the starting point of Rows when Out_DMA_ID==Pixel - 0 - 16 - read-write - - - - - OutDMA_Ctrl1 - Out DMA Buf Control 1 Register - 0x30 - 32 - 0x00000000 - 0x0000FFFF - - - ROWLEN - Total length (High 16 bits) in Bytes -1 for transfer. See reference in OutDMA_Ctrl0[TTLEN] - 0 - 16 - read-write - - - - - ONXT_CMD - Out DMA Next Command Register - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR - The address pointing to the next command - 2 - 30 - read-write - - - OP_VALID - asserted if there is either a DATA DMA phase or NXTCMD phase. Automatically cleared. Will trigger the OutDMA and NXTCMD phase transfer if CFG[JPEG_EN] is 1. - 1 - 1 - read-write - - - EN - NXTCMD phase Enable Bit - 0 - 1 - read-write - - - - - CFG - Configuration Register - 0x40 - 32 - 0x00000000 - 0xFFFFFFFF - - - JD_UVSWAP - Normally the default CbCr sequence is that Cb macro block coming before Cr macro blk. If Cr macro block is first, set this bit to 1'b1. This bit only impact the color space conversion from/to RGB. - 22 - 1 - read-write - - - CFG_IPATH_SEL - 2'b0:2-plane (Y- and UV- plane) or 1-plane (Y-only) as determined by the original data, byte sequence as Y0,Y1, or U,V -2'b01:ARGB8888, byte sequence as B,G,R,A -2'b10:RGB565, byte sequence as B,R -2'b11: YUV422H, byte sequence as Y0,U0,Y1,V0 - 20 - 2 - read-write - - - CODEC_OVER_IRQ_EN - The jpg endec process done interrupt enable - 19 - 1 - read-write - - - CODEC_RESTART_ERR_IRQ_EN - The jpg endec restart error interrupt enable - 18 - 1 - read-write - - - MEM_DEBUG_CLK_SEL - asserted to use APB clock, so that the memory contents could be read out through APB interface - 17 - 1 - read-write - - - CLKGATE - Assert this bit to gate off clock when the module is not working. If reset to zero, the internal clock is always on. - 9 - 1 - read-write - - - CFG_OPATH_SEL - 2'b0:2-plane (Y- and UV- plane) or 1-plane (Y-only) as determined by the original data, byte sequence as Y0,Y1, or U,V -2'b01:ARGB8888, byte sequence as B,G,R,A -2'b10:RGB565, byte sequence as R,B -2'b11: YUV422H1P, byte sequence as Y0,U0,Y1,V0 - 7 - 2 - read-write - - - JDATA_FORMAT - 3'b000: for 420, hy=2, vy=2, hc=1, vc=1 // 6 sub-blocks per MCU -3'b001: for 422h, hy=2, vy=1, hc=1, vc=1 // 4 sub-blocks per MCU -3'b010: for 422v, hy=1, vy=2, hc=1, vc=1 // 4 sub-blocks per MCU -3'b011: for 444, hy=1, vy=1, hc=1, vc=1 // 3 sub-blocks per MCU -3'b100: for 400, hy=2, vy=2, hc=0, vc=0 // 4 sub-blocks per MCU -Others: Undefined - 4 - 3 - read-write - - - JPEG_SFTRST - Software Reset - 3 - 1 - read-write - - - START - Asserted if to start a new encoder/decoder conversion. -It will at first stop the inner JPEG module, then reset it, and then re-run it. -It is a different mode from DMA phase mode. -It cannot be configured in the DMA chain descriptor. It should be configured by the core processor. -Auto clear. - 2 - 1 - read-write - - - MODE - 1: decoder, 0:encoder - 1 - 1 - read-write - - - JPEG_EN - 1b - Enabled - 0 - 1 - read-write - - - - - STAT - Status Register - 0x44 - 32 - 0x00000000 - 0xFFFFBFFE - - - BUSY - When 1 means that the module is busy doing conversion and data transfer. - 31 - 1 - read-only - - - AXI_ERR_ID - the axi err id - 10 - 4 - read-only - - - AXI_READ_ERR - in-dma axi bus error - 9 - 1 - read-only - - - AXI_WRITE_ERR - out-dma axi bus error - 8 - 1 - read-only - - - AXI_ERR - axi bus error - 7 - 1 - write-only - - - ONXT_IRQ - OutDMA next interrupt - 6 - 1 - write-only - - - INXT_IRQ - InDMA next interrupt - 5 - 1 - write-only - - - OUT_DMA_TRANSFER_DONE - OutDMA process done - 4 - 1 - write-only - - - IN_DMA_TRANSFER_DONE - InDMA process done - 3 - 1 - write-only - - - CODEC_OVER - Coding or decoding process is over. DMA is not included. -The module is completely not busy only when in_dma_transfer_done and out_dma_transfer_done, and codec_over are all asserted. - 2 - 1 - write-only - - - RESTART_MARKER_ERROR - codec restart marker error interrupt - 1 - 1 - write-only - - - - - Width - Image width register - 0x48 - 32 - 0x00000000 - 0xFFFFFFFF - - - IMG - Image Width (it is the max index of pixel counting from 0, assuming the top left pixel is indexed as [0,0]) - 0 - 16 - read-write - - - - - Height - Image height register - 0x4c - 32 - 0x00000000 - 0xFFFFFFFF - - - IMG - Image Height (it is the max index of pixel counting from 0, assuming the top left pixel is indexed as [0,0]) - 0 - 16 - read-write - - - - - BufAddr - Buf Access Addr - 0x50 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR - ADDR[31:28] denotes the buffer type: -0x2: Qmem -0x3: HuffEnc -0x4: HuffMin -0x5: HuffBase -0x6: HuffSymb -ADDR[27:0] is the address inside the buffer - 0 - 32 - read-write - - - - - BufData - Buf Access Data - 0x54 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - The data write-to/read-from buffer. -The n-th address read will be actually the data written for n-1 th address, and the actual stored location is n-1 th address. - 0 - 32 - read-write - - - - - OutDMACnt - Out DMA Bytes Counter - 0x58 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - The out DMA counter - 0 - 32 - read-only - - - - - CSC_COEF0 - YUV2RGB coefficients Register 0 - 0x5c - 32 - 0x00000000 - 0xFFFFFFFF - - - YCBCR_MODE - This bit changes the behavior when performing U/V converting. -0b - Converting YUV to RGB data -1b - Converting YCbCr to RGB data - 31 - 1 - read-write - - - ENABLE - Enable the CSC unit. -0b - The CSC is bypassed -1b - The CSC is enabled - 30 - 1 - read-write - - - C0 - Two's compliment Y multiplier coefficient C0. YUV=0x100 (1.000) YCbCr=0x12A (1.164) - 18 - 11 - read-write - - - UV_OFFSET - Two's compliment phase offset implicit for CbCr data UV_OFFSET. Generally used for YCbCr to RGB conversion. -YCbCr=0x180, YUV=0x000 (typically -128 or 0x180 to indicate normalized -0.5 to 0.5 range). - 9 - 9 - read-write - - - Y_OFFSET - Two's compliment amplitude offset implicit in the Y data Y_OFFSET. For YUV, this is typically 0 and for YCbCr, this is -typically -16 (0x1F0). - 0 - 9 - read-write - - - - - CSC_COEF1 - YUV2RGB coefficients Register 1 - 0x60 - 32 - 0x00000000 - 0xFFFFFFFF - - - C1 - Two's compliment Red V/Cr multiplier coefficient C1. YUV=0x123 (1.140) YCbCr=0x198 (1.596). - 16 - 11 - read-write - - - C4 - Two's compliment Blue U/Cb multiplier coefficient C4. YUV=0x208 (2.032) YCbCr=0x204 (2.017). - 0 - 11 - read-write - - - - - CSC_COEF2 - YUV2RGB coefficients Register 2 - 0x64 - 32 - 0x00000000 - 0xFFFFFFFF - - - C2 - Two's compliment Green V/Cr multiplier coefficient C2. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813). - 16 - 11 - read-write - - - C3 - Two's compliment Green U/Cb multiplier coefficient C3. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392). - 0 - 11 - read-write - - - - - RGB2YUV_COEF0 - RGB2YUV coefficients Register 0 - 0x68 - 32 - 0x00000000 - 0xFFFFFFFF - - - YCBCR_MODE - Asserted to use YCrCb mode. Must be assigned as 1. - 31 - 1 - read-write - - - ENABLE - Asserted to enable this RGB2YCbCr CSC stage - 30 - 1 - read-write - - - C0 - CSC parameters C0 - 18 - 11 - read-write - - - UV_OFFSET - CSC parameters UV_OFFSET - 9 - 9 - read-write - - - Y_OFFSET - CSC parameters Y_OFFSET - 0 - 9 - read-write - - - - - RGB2YUV_COEF1 - RGB2YUV coefficients Register 1 - 0x6c - 32 - 0x00000000 - 0xFFFFFFFF - - - C1 - CSC parameters C1 - 16 - 11 - read-write - - - C4 - CSC parameters C4 - 0 - 11 - read-write - - - - - RGB2YUV_COEF2 - RGB2YUV coefficients Register 2 - 0x70 - 32 - 0x00000000 - 0xFFFFFFFF - - - C2 - CSC parameters C2 - 16 - 11 - read-write - - - C3 - CSC parameters C3 - 0 - 11 - read-write - - - - - RGB2YUV_COEF3 - RGB2YUV coefficients Register 3 - 0x74 - 32 - 0x00000000 - 0xFFFFFFFF - - - C6 - CSC parameters C6 - 16 - 11 - read-write - - - C5 - CSC parameters C5 - 0 - 11 - read-write - - - - - RGB2YUV_COEF4 - RGB2YUV coefficients Register 4 - 0x78 - 32 - 0x00000000 - 0xFFFFFFFF - - - C8 - CSC parameters C8 - 16 - 11 - read-write - - - C7 - CSC parameters C7 - 0 - 11 - read-write - - - - - ImgReg1 - Image Control Register 1 - 0x84 - 32 - 0x00000000 - 0xFFFFFFF7 - - - RE - Encoder Use only. -Asseted to enable the Restart Marker processing. A Restart Marker is inserted in the outputted ECS (Entropy Coded Segment) every NRST+1 MCUs - 2 - 1 - read-write - - - NCOL - Ncol is the number of color components in the image data to process minus 1. For example, for a grayscale image Ncol=0, for an RGB image, Ncol=2 - 0 - 2 - read-write - - - - - ImgReg2 - Image Control Register 2 - 0x88 - 32 - 0x00000000 - 0xFFFFFFFF - - - NMCU - Encoder Use only. -The number of NMCU to be generated in encoder mode - 0 - 26 - read-write - - - - - ImgReg3 - Image Control Register 3 - 0x8c - 32 - 0x00000000 - 0xFFFFFFFF - - - NRST - Encoder use only. -It is the number of MCUs between two Restart Markers (if enabled) minus 1. The content of this register is ignored if the Re bit inregister 1 is not set. - 0 - 16 - read-write - - - - - 4 - 0x4 - Reg40,Reg41,Reg42,Reg43 - IMGREG[%s] - no description available - 0x90 - 32 - 0x00000000 - 0xFFFFFFFF - - - NBLOCK - Encoder use only. -The number of data units (8x8 blocks of data) of the color componet contained in the MCU minus 1. - 4 - 4 - read-write - - - QT - Encoder use only. -The selection of the quantization table. - 2 - 2 - read-write - - - HA - Encoder use only. -The selection of the Huffman table for the encoding of the AC coefficients in the data units belonging to the color component. - 1 - 1 - read-write - - - HD - Encoder use only. -The selection of the Huffman table for the encoding of the DC coefficients in the data units belonging to the color component. - 0 - 1 - read-write - - - - - - - ENET0 - ENET0 - ENET - 0xf2000000 - - 0x0 - 0x1058 - registers - - - - MACCFG - MAC Configuration Register - 0x0 - 32 - 0x00000000 - 0x7FFFFFFF - - - SARC - Source Address Insertion or Replacement Control - This field controls the source address insertion or replacement for all transmitted frames. -Bit 30 specifies which MAC Address register (0 or 1) is used for source address insertion or replacement based on the values of Bits [29:28]: -- 2'b0x: The input signals mti_sa_ctrl_i and ati_sa_ctrl_i control the SA field generation. -- 2'b10: - If Bit 30 is set to 0, the MAC inserts the content of the MAC Address 0 registers (registers 16 and 17) in the SA field of all transmitted frames. - - If Bit 30 is set to 1 and the Enable MAC Address Register 1 option is selected during core configuration, - the MAC inserts the content of the MAC Address 1 registers (registers 18 and 19) in the SA field of all transmitted frames. -- 2'b11: - If Bit 30 is set to 0, the MAC replaces the content of the MAC Address 0 registers (registers 16 and 17) in the SA field of all transmitted frames. - - If Bit 30 is set to 1 and the Enable MAC Address Register 1 option is selected during core configuration, - the MAC replaces the content of the MAC Address 1 registers (registers 18 and 19) in the SA field of all transmitted frames. -Note: - Changes to this field take effect only on the start of a frame. -If you write this register field when a frame is being transmitted, only the subsequent frame can use the updated value, -that is, the current frame does not use the updated value. -- These bits are reserved and RO when the Enable SA, VLAN, and CRC Insertion on TX feature is not selected during core configuration. - 28 - 3 - read-write - - - TWOKPE - IEEE 802.3as Support for 2K Packets - When set, the MAC considers all frames, with up to 2,000 bytes length, as normal packets. -When Bit 20 (JE) is not set, the MAC considers all received frames of size more than 2K bytes as Giant frames. -When this bit is reset and Bit 20 (JE) is not set, the MAC considers all received frames of size more than 1,518 bytes (1,522 bytes for tagged) as Giant frames. -When Bit 20 is set, setting this bit has no effect on Giant Frame status. - 27 - 1 - read-write - - - SFTERR - SMII Force Transmit Error - When set, this bit indicates to the PHY to force a transmit error in the SMII frame being transmitted. This bit is reserved if the SMII PHY port is not selected during core configuration. - 26 - 1 - read-write - - - CST - CRC Stripping for Type Frames - When this bit is set, the last 4 bytes (FCS) of all frames of Ether type (Length/Type field greater than or equal to 1,536) are stripped and dropped before forwarding the frame to the application. -This function is not valid when the IP Checksum Engine (Type 1) is enabled in the MAC receiver. This function is valid when Type 2 Checksum Offload Engine is enabled. - 25 - 1 - read-write - - - TC - Transmit Configuration in RGMII, SGMII, or SMII - When set, this bit enables the transmission of duplex mode, link speed, and link up or down information to the PHY in the RGMII, SMII, - or SGMII port. When this bit is reset, no such information is driven to the PHY. -This bit is reserved (and RO) if the RGMII, SMII, or SGMII PHY port is not selected during core configuration. - 24 - 1 - read-write - - - WD - Watchdog Disable - When this bit is set, the MAC disables the watchdog timer on the receiver. The MAC can receive frames of up to 16,383 bytes. - 23 - 1 - read-write - - - JD - Jabber Disable - When this bit is set, the MAC disables the jabber timer on the transmitter. The MAC can transfer frames of up to 16,383 bytes. -When this bit is reset, the MAC cuts off the transmitter if the application sends out more than 2,048 bytes of data (10,240 if JE is set high) during transmission. - 22 - 1 - read-write - - - BE - Frame Burst Enable - When this bit is set, the MAC allows frame bursting during transmission in the GMII half-duplex mode. This bit is reserved (and RO) in the 10/100 Mbps only or full-duplex-only configurations. - 21 - 1 - read-write - - - JE - Jumbo Frame Enable - When this bit is set, the MAC allows Jumbo frames of 9,018 bytes (9,022 bytes for VLAN tagged frames) without reporting a giant frame error in the receive frame status. - 20 - 1 - read-write - - - IFG - Inter-Frame Gap - These bits control the minimum IFG between frames during transmission. -- 000: 96 bit times -- 001: 88 bit times -- 010: 80 bit times - ... -- 111: 40 bit times In the half-duplex mode, the minimum IFG can be configured only for 64 bit times (IFG = 100). -Lower values are not considered. -In the 1000-Mbps mode, the minimum IFG supported is 64 bit times (and above) in the GMAC-CORE configuration and 80 bit times (and above) in other configurations. - When a JAM pattern is being transmitted because of backpressure activation, the MAC does not consider the minimum IFG. - 17 - 3 - read-write - - - DCRS - Disable Carrier Sense During Transmission - When set high, this bit makes the MAC transmitter ignore the (G)MII CRS signal during frame transmission in the half-duplex mode. - This request results in no errors generated because of Loss of Carrier or No Carrier during such transmission. -When this bit is low, the MAC transmitter generates such errors because of Carrier Sense and can even abort the transmissions. - 16 - 1 - read-write - - - PS - Port Select - This bit selects the Ethernet line speed. -- 0: For 1000 Mbps operations -- 1: For 10 or 100 Mbps operations In 10 or 100 Mbps operations, this bit, along with FES bit, selects the exact line speed. -In the 10/100 Mbps-only (always 1) or 1000 Mbps-only (always 0) configurations, this bit is read-only with the appropriate value. In default 10/100/1000 Mbps configuration, -this bit is R_W. The mac_portselect_o or mac_speed_o[1] signal reflects the value of this bit. - 15 - 1 - read-write - - - FES - Speed - This bit selects the speed in the MII, RMII, SMII, RGMII, SGMII, or RevMII interface: -- 0: 10 Mbps -- 1: 100 Mbps This bit is reserved (RO) by default and is enabled only when the parameter SPEED_SELECT = Enabled. -This bit generates link speed encoding when Bit 24 (TC) is set in the RGMII, SMII, or SGMII mode. -This bit is always enabled for RGMII, SGMII, SMII, or RevMII interface. -In configurations with RGMII, SGMII, SMII, or RevMII interface, this bit is driven as an output signal (mac_speed_o[0]) to reflect the value of this bit in the mac_speed_o signal. -In configurations with RMII, MII, or GMII interface, you can optionally drive this bit as an output signal (mac_speed_o[0]) to reflect its value in the mac_speed_o signal. - 14 - 1 - read-write - - - DO - Disable Receive Own - When this bit is set, the MAC disables the reception of frames when the phy_txen_o is asserted in the half-duplex mode. -When this bit is reset, the MAC receives all packets that are given by the PHY while transmitting. -This bit is not applicable if the MAC is operating in the full-duplex mode. This bit is reserved (RO with default value) if the MAC is configured for the full-duplex-only operation. - 13 - 1 - read-write - - - LM - Loopback Mode - When this bit is set, the MAC operates in the loopback mode at GMII or MII. -The (G)MII Receive clock input (clk_rx_i) is required for the loopback to work properly, because the Transmit clock is not looped-back internally. - 12 - 1 - read-write - - - DM - Duplex Mode - When this bit is set, the MAC operates in the full-duplex mode where it can transmit and receive simultaneously. - 11 - 1 - read-write - - - IPC - Checksum Offload -When this bit is set, the MAC calculates the 16-bit one’s complement of the one’s complement sum of all received Ethernet frame payloads. -It also checks whether the IPv4 Header checksum (assumed to be bytes 25–26 or 29–30 (VLAN-tagged) -of the received Ethernet frame) is correct for the received frame and gives the status in the receive status word. -The MAC also appends the 16-bit checksum calculated for the IP header datagram payload (bytes after the IPv4 header) -and appends it to the Ethernet frame transferred to the application (when Type 2 COE is deselected). -When this bit is reset, this function is disabled. -When Type 2 COE is selected, this bit, when set, enables the IPv4 header checksum checking and IPv4 or IPv6 TCP, UDP, or ICMP payload checksum checking. - 10 - 1 - read-write - - - DR - Disable Retry -When this bit is set, the MAC attempts only one transmission. -When a collision occurs on the GMII or MII interface, -the MAC ignores the current frame transmission and reports a Frame Abort with excessive collision error in the transmit frame status. -When this bit is reset, the MAC attempts retries based on the settings of the BL field (Bits [6:5]). - 9 - 1 - read-write - - - LUD - Link Up or Down - This bit indicates whether the link is up or down during the transmission of configuration in the RGMII, SGMII, or SMII interface: -- 0: Link Down -- 1: Link Up - 8 - 1 - read-write - - - ACS - Automatic Pad or CRC Stripping - When this bit is set, the MAC strips the Pad or FCS field on the incoming frames only if the value of the length field is less than 1,536 bytes. -All received frames with length field greater than or equal to 1,536 bytes are passed to the application without stripping the Pad or FCS field. -When this bit is reset, the MAC passes all incoming frames, without modifying them, to the Host. - 7 - 1 - read-write - - - BL - Back-Off Limit - The Back-Off limit determines the random integer number (r) of slot time delays - (4,096 bit times for 1000 Mbps and 512 bit times for 10/100 Mbps) for which the MAC waits before rescheduling a transmission attempt during retries after a collision. -This bit is applicable only in the half-duplex mode and is reserved (RO) in the full-duplex-only configuration. -- 00: k= min (n, 10) -- 01: k = min (n, 8) -- 10: k = min (n, 4) -- 11: k = min (n, 1) where n = retransmission attempt. The random integer r takes the value in the range 0 ≤ r < 2k - 5 - 2 - read-write - - - DC - Deferral Check - When this bit is set, the deferral check function is enabled in the MAC. -The MAC issues a Frame Abort status, along with the excessive deferral error bit set in the transmit frame status, -when the transmit state machine is deferred for more than 24,288 bit times in the 10 or 100 Mbps mode. - If the MAC is configured for 1000 Mbps operation or if the Jumbo frame mode is enabled in the 10 or 100 Mbps mode, - the threshold for deferral is 155,680 bits times. Deferral begins when the transmitter is ready to transmit, -but it is prevented because of an active carrier sense signal (CRS) on GMII or MII. The defer time is not cumulative. -For example, if the transmitter defers for 10,000 bit times because the CRS signal is active and then the CRS signal becomes inactive, -the transmitter transmits and collision happens. -Because of collision, the transmitter needs to back off and then defer again after back off completion. -In such a scenario, the deferral timer is reset to 0 and it is restarted. - 4 - 1 - read-write - - - TE - Transmitter Enable - When this bit is set, the transmit state machine of the MAC is enabled for transmission on the GMII or MII. When this bit is reset, - the MAC transmit state machine is disabled after the completion of the transmission of the current frame, and does not transmit any further frames. - 3 - 1 - read-write - - - RE - Receiver Enable - When this bit is set, the receiver state machine of the MAC is enabled for receiving frames from the GMII or MII. When this bit is reset, -the MAC receive state machine is disabled after the completion of the reception of the current frame, and does not receive any further frames from the GMII or MII. - 2 - 1 - read-write - - - PRELEN - Preamble Length for Transmit frames - These bits control the number of preamble bytes that are added to the beginning of every Transmit frame. - The preamble reduction occurs only when the MAC is operating in the full-duplex mode. -- 2'b00: 7 bytes of preamble -- 2'b01: 5 bytes of preamble -- 2'b10: 3 bytes of preamble -- 2'b11: Reserved - 0 - 2 - read-write - - - - - MACFF - MAC Frame Filter - 0x4 - 32 - 0x00000000 - 0x803087FF - - - RA - Receive All - When this bit is set, the MAC Receiver module passes all received frames, irrespective of whether they pass the address filter or not, to the Application. -The result of the SA or DA filtering is updated (pass or fail) in the corresponding bits in the Receive Status Word. When this bit is reset, -the Receiver module passes only those frames to the Application that pass the SA or DA address filter. - 31 - 1 - read-write - - - DNTU - Drop non-TCP/UDP over IP Frames - When set, this bit enables the MAC to drop the non-TCP or UDP over IP frames. The MAC forward only those frames that are processed by the Layer 4 filter. -When reset, this bit enables the MAC to forward all non-TCP or UDP over IP frames. - 21 - 1 - read-write - - - IPFE - Layer 3 and Layer 4 Filter Enable - When set, this bit enables the MAC to drop frames that do not match the enabled Layer 3 and Layer 4 filters. If Layer 3 or Layer 4 filters are not enabled for matching, -this bit does not have any effect. When reset, the MAC forwards all frames irrespective of the match status of the Layer 3 and Layer 4 fields. - 20 - 1 - read-write - - - VTFE - VLAN Tag Filter Enable - When set, this bit enables the MAC to drop VLAN tagged frames that do not match the VLAN Tag comparison. -When reset, the MAC forwards all frames irrespective of the match status of the VLAN Tag. - 15 - 1 - read-write - - - HPF - Hash or Perfect Filter - When this bit is set, it configures the address filter to pass a frame if it matches either the perfect filtering or the hash filtering as set by the HMC or HUC bits. -When this bit is low and the HUC or HMC bit is set, the frame is passed only if it matches the Hash filter. - 10 - 1 - read-write - - - SAF - Source Address Filter Enable - When this bit is set, the MAC compares the SA field of the received frames with the values programmed in the enabled SA registers. If the comparison fails, - the MAC drops the frame. When this bit is reset, the MAC forwards the received frame to the application with updated SAF bit of the Rx Status depending on the SA address comparison. - 9 - 1 - read-write - - - SAIF - SA Inverse Filtering -When this bit is set, the Address Check block operates in inverse filtering mode for the SA address comparison. The frames whose SA matches the SA registers are marked as failing the SA Address filter. -When this bit is reset, frames whose SA does not match the SA registers are marked as failing the SA Address filter. - 8 - 1 - read-write - - - PCF - Pass Control Frames - These bits control the forwarding of all control frames (including unicast and multicast Pause frames). -- 00: MAC filters all control frames from reaching the application. -- 01: MAC forwards all control frames except Pause frames to application even if they fail the Address filter. -- 10: MAC forwards all control frames to application even if they fail the Address Filter. -- 11: MAC forwards control frames that pass the Address Filter. -The following conditions should be true for the Pause frames processing: -- Condition 1: The MAC is in the full-duplex mode and flow control is enabled by setting Bit 2 (RFE) of Register 6 (Flow Control Register) to 1. -- Condition 2: The destination address (DA) of the received frame matches the special multicast address or the MAC Address 0 when Bit 3 (UP) of the Register 6 (Flow Control Register) is set. -- Condition 3: The Type field of the received frame is 0x8808 and the OPCODE field is 0x0001. -Note: This field should be set to 01 only when the Condition 1 is true, -that is, the MAC is programmed to operate in the full-duplex mode and the RFE bit is enabled. -Otherwise, the Pause frame filtering may be inconsistent. -When Condition 1 is false, the Pause frames are considered as generic control frames. -Therefore, to pass all control frames (including Pause frames) when the full-duplex mode and flow control is not enabled, -you should set the PCF field to 10 or 11 (as required by the application). - 6 - 2 - read-write - - - DBF - Disable Broadcast Frames - When this bit is set, the AFM module blocks all incoming broadcast frames. In addition, it overrides all other filter settings. -When this bit is reset, the AFM module passes all received broadcast frames. - 5 - 1 - read-write - - - PM - Pass All Multicast -When set, this bit indicates that all received frames with a multicast destination address (first bit in the destination address field is '1') are passed. -When reset, filtering of multicast frame depends on HMC bit. - 4 - 1 - read-write - - - DAIF - DA Inverse Filtering - When this bit is set, the Address Check block operates in inverse filtering mode for the DA address comparison for both unicast and multicast frames. -When reset, normal filtering of frames is performed. - 3 - 1 - read-write - - - HMC - Hash Multicast -When set, the MAC performs destination address filtering of received multicast frames according to the hash table. When reset, -the MAC performs a perfect destination address filtering for multicast frames, that is, it compares the DA field with the values programmed in DA registers. - 2 - 1 - read-write - - - HUC - Hash Unicast - When set, the MAC performs destination address filtering of unicast frames according to the hash table. -When reset, the MAC performs a perfect destination address filtering for unicast frames, that is, it compares the DA field with the values programmed in DA registers. - 1 - 1 - read-write - - - PR - Promiscuous Mode -When this bit is set, the Address Filter module passes all incoming frames irrespective of the destination or source address. - The SA or DA Filter Fails status bits of the Receive Status Word are always cleared when PR is set. - 0 - 1 - read-write - - - - - HASH_H - Hash Table High Register - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - HTH - Hash Table High - This field contains the upper 32 bits of the Hash table. - 0 - 32 - read-write - - - - - HASH_L - Hash Table Low Register - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - HTL - Hash Table Low - This field contains the lower 32 bits of the Hash table. - 0 - 32 - read-write - - - - - GMII_ADDR - GMII Address Register - 0x10 - 32 - 0x00000000 - 0x0000FFFF - - - PA - Physical Layer Address - This field indicates which of the 32 possible PHY devices are being accessed. For RevMII, this field gives the PHY Address of the RevMII module. - 11 - 5 - read-write - - - GR - GMII Register - These bits select the desired GMII register in the selected PHY device. For RevMII, these bits select the desired CSR register in the RevMII Registers set. - 6 - 5 - read-write - - - CR - CSR Clock Range - The CSR Clock Range selection determines the frequency of the MDC clock according to the CSR clock frequency used in your design. -The CSR clock corresponding to different GMAC configurations is given in Table 9-2 on page 564. -The suggested range of CSR clock frequency applicable for each value (when Bit[5] = 0) -ensures that the MDC clock is approximately between the frequency range 1.0 MHz–2.5 MHz. -- 0000: The CSR clock frequency is 60–100 MHz and the MDC clock frequency is CSR clock/42. -- 0001: The CSR clock frequency is 100–150 MHz and the MDC clock frequency is CSR clock/62. -- 0010: The CSR clock frequency is 20–35 MHz and the MDC clock frequency is CSR clock/16. -- 0011: The CSR clock frequency is 35–60 MHz and the MDC clock frequency is CSR clock/26. -- 0100: The CSR clock frequency is 150–250 MHz and the MDC clock frequency is CSR clock/102. -- 0101: The CSR clock frequency is 250–300 MHz and the MDC clock is CSR clock/124. -- 0110, 0111: Reserved -When Bit 5 is set, you can achieve higher frequency of the MDC clock than the frequency limit of 2.5 MHz (specified in the IEEE Std 802.3) and program a clock divider of lower value. -For example, -when CSR clock is of 100 MHz frequency and you program these bits as 1010, -then the resultant MDC clock is of 12.5 MHz which is outside the limit of IEEE 802.3 specified range. -Program the following values only if the interfacing chips support faster MDC clocks. -- 1000: CSR clock/4 -- 1001: CSR clock/6 -- 1010: CSR clock/8 -- 1011: CSR clock/10 -- 1100: CSR clock/12 -- 1101: CSR clock/14 -- 1110: CSR clock/16 -- 1111: CSR clock/18 These bits are not used for accessing RevMII. These bits are read-only if the RevMII interface is selected as single PHY interface. - 2 - 4 - read-write - - - GW - GMII Write - When set, this bit indicates to the PHY or RevMII that this is a Write operation using the GMII Data register. If this bit is not set, -it indicates that this is a Read operation, that is, placing the data in the GMII Data register. - 1 - 1 - read-write - - - GB - GMII Busy - This bit should read logic 0 before writing to Register 4 and Register 5. -During a PHY or RevMII register access, the software sets this bit to 1’b1 to indicate that a Read or Write access is in progress. - Register 5 is invalid until this bit is cleared by the MAC. -Therefore, Register 5 (GMII Data) should be kept valid until the MAC clears this bit during a PHY Write operation. -Similarly for a read operation, the contents of Register 5 are not valid until this bit is cleared. -The subsequent read or write operation should happen only after the previous operation is complete. -Because there is no acknowledgment from the PHY to MAC after a read or write operation is completed, -there is no change in the functionality of this bit even when the PHY is not present. - 0 - 1 - read-write - - - - - GMII_DATA - GMII Data Register - 0x14 - 32 - 0x00000000 - 0x0000FFFF - - - GD - GMII Data - This field contains the 16-bit data value read from the PHY or RevMII after a Management Read operation -or the 16-bit data value to be written to the PHY or RevMII before a Management Write operation. - 0 - 16 - read-write - - - - - FLOWCTRL - Flow Control Register - 0x18 - 32 - 0x00000000 - 0xFFFF00BF - - - PT - Pause Time - This field holds the value to be used in the Pause Time field in the transmit control frame. -If the Pause Time bits is configured to be double-synchronized to the (G)MII clock domain, - then consecutive writes to this register should be performed only after at least four clock cycles in the destination clock domain. - 16 - 16 - read-write - - - DZPQ - Disable Zero-Quanta Pause - When this bit is set, it disables the automatic generation of the Zero-Quanta Pause frames on the de-assertion of -the flow-control signal from the FIFO layer (MTL or external sideband flow control signal sbd_flowctrl_i/mti_flowctrl_i). -When this bit is reset, normal operation with automatic Zero-Quanta Pause frame generation is enabled. - 7 - 1 - read-write - - - PLT - Pause Low Threshold - This field configures the threshold of the Pause timer at which the input flow control signal mti_flowctrl_i (or sbd_flowctrl_i) is checked for automatic retransmission of the Pause frame. -The threshold values should be always less than the Pause Time configured in Bits[31:16]. - For example, if PT = 100H (256 slot-times), and PLT = 01, -then a second Pause frame is automatically transmitted if the mti_flowctrl_i signal is asserted at 228 (256 – 28) slot times after the first Pause frame is transmitted. -The following list provides the threshold values for different values: -- 00: The threshold is Pause time minus 4 slot times (PT – 4 slot times). -- 01: The threshold is Pause time minus 28 slot times (PT – 28 slot times). -- 10: The threshold is Pause time minus 144 slot times (PT – 144 slot times). -- 11: The threshold is Pause time minus 256 slot times (PT – 256 slot times). The slot time is defined as the time taken to transmit 512 bits (64 bytes) on the GMII or MII interface. - 4 - 2 - read-write - - - UP - Unicast Pause Frame Detect A pause frame is processed when it has the unique multicast address specified in the IEEE Std 802.3. -When this bit is set, the MAC can also detect Pause frames with unicast address of the station. -This unicast address should be as specified in the MAC Address0 High Register and MAC Address0 Low Register. -When this bit is reset, the MAC only detects Pause frames with unique multicast address. - 3 - 1 - read-write - - - RFE - Receive Flow Control Enable - When this bit is set, the MAC decodes the received Pause frame and disables its transmitter for a specified (Pause) time. When this bit is reset, the decode function of the Pause frame is disabled. - 2 - 1 - read-write - - - TFE - Transmit Flow Control Enable -In the full-duplex mode, when this bit is set, the MAC enables the flow control operation to transmit Pause frames. -When this bit is reset, the flow control operation in the MAC is disabled, and the MAC does not transmit any Pause frames. -In the half-duplex mode, when this bit is set, the MAC enables the backpressure operation. When this bit is reset, the backpressure feature is disabled. - 1 - 1 - read-write - - - FCB_BPA - Flow Control Busy or Backpressure Activate - This bit initiates a Pause frame in the full-duplex mode and activates the backpressure function in the half-duplex mode if the TFE bit is set. -In the full-duplex mode, this bit should be read as 1'b0 before writing to the Flow Control register. - To initiate a Pause frame, the Application must set this bit to 1'b1. -During a transfer of the Control Frame, this bit continues to be set to signify that a frame transmission is in progress. -After the completion of Pause frame transmission, the MAC resets this bit to 1'b0. -The Flow Control register should not be written to until this bit is cleared. In the half-duplex mode, -when this bit is set (and TFE is set), then backpressure is asserted by the MAC. -During backpressure, when the MAC receives a new frame, the transmitter starts sending a JAM pattern resulting in a collision. -This control register bit is logically ORed with the mti_flowctrl_i input signal for the backpressure function. -When the MAC is configured for the full-duplex mode, the BPA is automatically disabled. - 0 - 1 - read-write - - - - - VLAN_TAG - VLAN Tag Register - 0x1c - 32 - 0x00000000 - 0x000FFFFF - - - VTHM - VLAN Tag Hash Table Match Enable - When set, the most significant four bits of the VLAN tag’s CRC are used to index the content of Register 354 (VLAN Hash Table Register). -A value of 1 in the VLAN Hash Table register, corresponding to the index, indicates that the frame matched the VLAN hash table. -When Bit 16 (ETV) is set, the CRC of the 12-bit VLAN Identifier (VID) is used for comparison whereas when ETV is reset, -the CRC of the 16-bit VLAN tag is used for comparison. When reset, the VLAN Hash Match operation is not performed. - 19 - 1 - read-write - - - ESVL - Enable S-VLAN - When this bit is set, the MAC transmitter and receiver also consider the S-VLAN (Type = 0x88A8) frames as valid VLAN tagged frames. - 18 - 1 - read-write - - - VTIM - VLAN Tag Inverse Match Enable -When set, this bit enables the VLAN Tag inverse matching. The frames that do not have matching VLAN Tag are marked as matched. When reset, this bit enables the VLAN Tag perfect matching. - The frames with matched VLAN Tag are marked as matched. - 17 - 1 - read-write - - - ETV - Enable 12-Bit VLAN Tag Comparison - When this bit is set, a 12-bit VLAN identifier is used for comparing and filtering instead of the complete 16-bit VLAN tag. - Bits [11:0] of VLAN tag are compared with the corresponding field in the received VLAN-tagged frame. Similarly, when enabled, -only 12 bits of the VLAN tag in the received frame are used for hash-based VLAN filtering. -When this bit is reset, all 16 bits of the 15th and 16th bytes of the received VLAN frame are used for comparison and VLAN hash filtering. - 16 - 1 - read-write - - - VL - VLAN Tag Identifier for Receive Frames - This field contains the 802.1Q VLAN tag to identify the VLAN frames and is compared to the 15th and 16th bytes of the frames being received for VLAN frames. -The following list describes the bits of this field: - - Bits [15:13]: User Priority -- Bit 12: Canonical Format Indicator (CFI) or Drop Eligible Indicator (DEI) -- Bits[11:0]: VLAN tag’s VLAN Identifier (VID) field When the ETV bit is set, only the VID (Bits[11:0]) is used for comparison. - If VL (VL[11:0] if ETV is set) is all zeros, the MAC does not check the fifteenth and 16th bytes for VLAN tag comparison, - and declares all frames with a Type field value of 0x8100 or 0x88a8 as VLAN frames. - 0 - 16 - read-write - - - - - RWKFRMFILT - Remote Wake-Up Frame Filter Register - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - WKUPFRMFILT - This is the address through which the application writes or reads the remote wake-up frame filter registers (wkupfmfilter_reg). -The wkupfmfilter_reg register is a pointer to eight wkupfmfilter_reg registers. -The wkupfmfilter_reg register is loaded by sequentially loading the eight register values. -Eight sequential writes to this address (0x0028) write all wkupfmfilter_reg registers. - Similarly, eight sequential reads from this address (0x0028) read all wkupfmfilter_reg registers - 0 - 32 - read-write - - - - - PMT_CSR - PMT Control and Status Register - 0x2c - 32 - 0x00000000 - 0x9F000267 - - - RWKFILTRST - Remote Wake-Up Frame Filter Register Pointer Reset -When this bit is set, it resets the remote wake-up frame filter register pointer to 3’b000. It is automatically cleared after 1 clock cycle. - 31 - 1 - read-write - - - RWKPTR - Remote Wake-up FIFO Pointer -This field gives the current value (0 to 31) of the Remote Wake-up Frame filter register pointer. When the value of this pointer is equal to 7, 15, 23 or 31, -the contents of the Remote Wake-up Frame Filter Register are transferred to the clk_rx_i domain when a write occurs to that register. - The maximum value of the pointer is 7, 15, 23 and 31 respectively depending on the number of Remote Wakeup Filters selected during configuration. - 24 - 5 - read-write - - - GLBLUCAST - Global Unicast -When set, enables any unicast packet filtered by the MAC (DAF) address recognition to be a remote wake-up frame. - 9 - 1 - read-write - - - RWKPRCVD - Remote Wake-Up Frame Received -When set, this bit indicates the power management event is generated because of the reception of a remote wake-up frame. This bit is cleared by a Read into this register. - 6 - 1 - read-write - - - MGKPRCVD - Magic Packet Received -When set, this bit indicates that the power management event is generated because of the reception of a magic packet. This bit is cleared by a Read into this register. - 5 - 1 - read-write - - - RWKPKTEN - Remote Wake-Up Frame Enable -When set, enables generation of a power management event because of remote wake-up frame reception. - 2 - 1 - read-write - - - MGKPKTEN - Magic Packet Enable -When set, enables generation of a power management event because of magic packet reception. - 1 - 1 - read-write - - - PWRDWN - Power Down -When set, the MAC receiver drops all received frames until it receives the expected magic packet or remote wake-up frame. -This bit is then self-cleared and the power-down mode is disabled. -The Software can also clear this bit before the expected magic packet or remote wake-up frame is received. -The frames, received by the MAC after this bit is cleared, are forwarded to the application. -This bit must only be set when the Magic Packet Enable, Global Unicast, or Remote Wake-Upr Fame Enable bit is set high. -Note: You can gate-off the CSR clock during the power-down mode. -However, when the CSR clock is gated-off, you cannot perform any read or write operations on this register. Therefore, the Software cannot clear this bit. - 0 - 1 - read-write - - - - - LPI_CSR - LPI Control and Status Register - 0x30 - 32 - 0x00000000 - 0x000F030F - - - LPITXA - LPI TX Automate -This bit controls the behavior of the MAC when it is entering or coming out of the LPI mode on the transmit side. -This bit is not functional in the GMAC-CORE configuration in which the Tx clock gating is done during the LPI mode. If the LPITXA and LPIEN bits are set to 1, -the MAC enters the LPI mode only after all outstanding frames (in the core) and pending frames (in the application interface) have been transmitted. -The MAC comes out of the LPI mode when the application sends any frame for transmission or the application issues a TX FIFO Flush command. - In addition, the MAC automatically clears the LPIEN bit when it exits the LPI state. -If TX FIFO Flush is set in Bit 20 of Register 6 (Operation Mode Register), -when the MAC is in the LPI mode, the MAC exits the LPI mode. -When this bit is 0, the LPIEN bit directly controls behavior of the MAC when it is entering or coming out of the LPI mode. - 19 - 1 - read-write - - - PLSEN - PHY Link Status Enable -This bit enables the link status received on the RGMII, SGMII, or SMII receive paths to be used for activating the LPI LS TIMER. -When set, the MAC uses the link-status bits of Register 54 (SGMII/RGMII/SMII Control and Status Register) and Bit 17 (PLS) for the LPI LS Timer trigger. - When cleared, the MAC ignores the link-status bits of Register 54 and takes only the PLS bit. This bit is RO and reserved if you have not selected the RGMII, SGMII, or SMII PHY interface. - 18 - 1 - read-write - - - PLS - PHY Link Status -This bit indicates the link status of the PHY. The MAC Transmitter asserts the LPI pattern only when the link status is up (okay) at least for the time indicated by the LPI LS TIMER. -When set, the link is considered to be okay (up) and when reset, the link is considered to be down. - 17 - 1 - read-write - - - LPIEN - LPI Enable -When set, this bit instructs the MAC Transmitter to enter the LPI state. When reset, this bit instructs the MAC to exit the LPI state and resume normal transmission. -This bit is cleared when the LPITXA bit is set and the MAC exits the LPI state because of the arrival of a new packet for transmission. - 16 - 1 - read-write - - - RLPIST - Receive LPI State -When set, this bit indicates that the MAC is receiving the LPI pattern on the GMII or MII interface. - 9 - 1 - read-write - - - TLPIST - Transmit LPI State -When set, this bit indicates that the MAC is transmitting the LPI pattern on the GMII or MII interface. - 8 - 1 - read-write - - - RLPIEX - Receive LPI Exit -When set, this bit indicates that the MAC Receiver has stopped receiving the LPI pattern on the GMII or MII interface, exited the LPI state, and resumed the normal reception. -This bit is cleared by a read into this register. -Note: This bit may not get set if the MAC stops receiving the LPI pattern for a very short duration, such as, less than 3 clock cycles of CSR clock. - 3 - 1 - read-write - - - RLPIEN - Receive LPI Entry -When set, this bit indicates that the MAC Receiver has received an LPI pattern and entered the LPI state. This bit is cleared by a read into this register. -Note: This bit may not get set if the MAC stops receiving the LPI pattern for a very short duration, such as, less than 3 clock cycles of CSR clock. - 2 - 1 - read-write - - - TLPIEX - Transmit LPI Exit -When set, this bit indicates that the MAC transmitter has exited the LPI state after the user has cleared the LPIEN bit and the LPI TW Timer has expired. This bit is cleared by a read into this register. - 1 - 1 - read-write - - - TLPIEN - Transmit LPI Entry - When set, this bit indicates that the MAC Transmitter has entered the LPI state because of the setting of the LPIEN bit. This bit is cleared by a read into this register. - 0 - 1 - read-write - - - - - LPI_TCR - LPI Timers Control Register - 0x34 - 32 - 0x00000000 - 0x03FFFFFF - - - LST - LPI LS TIMER -This field specifies the minimum time (in milliseconds) for which the link status from the PHY should be up (OKAY) before the LPI pattern can be transmitted to the PHY. - The MAC does not transmit the LPI pattern even when the LPIEN bit is set unless the LPI LS Timer reaches the programmed terminal count. -The default value of the LPI LS Timer is 1000 (1 sec) as defined in the IEEE standard. - 16 - 10 - read-write - - - TWT - LPI TW TIMER -This field specifies the minimum time (in microseconds) for which the MAC waits after it stops transmitting - the LPI pattern to the PHY and before it resumes the normal transmission. -The TLPIEX status bit is set after the expiry of this timer. - 0 - 16 - read-write - - - - - INTR_STATUS - Interrupt Status Register - 0x38 - 32 - 0x00000000 - 0x00000EFF - - - GPIIS - GPI Interrupt Status -When the GPIO feature is enabled, this bit is set when any active event (LL or LH) occurs on the GPIS field (Bits [3:0]) - of Register 56 (General Purpose IO Register) and the corresponding GPIE bit is enabled. -This bit is cleared on reading lane 0 (GPIS) of Register 56 (General Purpose IO Register). - When the GPIO feature is not enabled, this bit is reserved. - 11 - 1 - read-only - - - LPIIS - LPI Interrupt Status -When the Energy Efficient Ethernet feature is enabled, this bit is set for any LPI state entry or exit in the MAC Transmitter or Receiver. -This bit is cleared on reading Bit 0 of Register 12 (LPI Control and Status Register). In all other modes, this bit is reserved. - 10 - 1 - read-only - - - TSIS - Timestamp Interrupt Status -When the Advanced Timestamp feature is enabled, this bit is set when any of the following conditions is true: -- The system time value equals or exceeds the value specified in the Target Time High and Low registers. -- There is an overflow in the seconds register. - - The Auxiliary snapshot trigger is asserted. This bit is cleared on reading Bit 0 of Register 458 (Timestamp Status Register). - 9 - 1 - read-only - - - MMCRXIPIS - MMC Receive Checksum Offload Interrupt Status -This bit is set high when an interrupt is generated in the MMC Receive Checksum Offload Interrupt Register. This bit is cleared when all the bits in this interrupt register are cleared. - 7 - 1 - read-only - - - MMCTXIS - MMC Transmit Interrupt Status -This bit is set high when an interrupt is generated in the MMC Transmit Interrupt Register. This bit is cleared when all the bits in this interrupt register are cleared. - 6 - 1 - read-only - - - MMCRXIS - MMC Receive Interrupt Status -This bit is set high when an interrupt is generated in the MMC Receive Interrupt Register. This bit is cleared when all the bits in this interrupt register are cleared. - 5 - 1 - read-only - - - MMCIS - MMC Interrupt Status -This bit is set high when any of the Bits [7:5] is set high and cleared only when all of these bits are low. - 4 - 1 - read-only - - - PMTIS - PMT Interrupt Status -This bit is set when a magic packet or remote wake-up frame is received in the power-down mode (see Bits 5 and 6 in the PMT Control and Status Register). -This bit is cleared when both Bits[6:5] are cleared because of a read operation to the PMT Control and Status register. - 3 - 1 - read-only - - - PCSANCIS - PCS Auto-Negotiation Complete -This bit is set when the Auto-negotiation is completed in the TBI, RTBI, or SGMII PHY interface (Bit 5 in Register 49 (AN Status Register)). -This bit is cleared when you perform a read operation to the AN Status register. - 2 - 1 - read-only - - - PCSLCHGIS - PCS Link Status Changed -This bit is set because of any change in Link Status in the TBI, RTBI, or SGMII PHY interface (Bit 2 in Register 49 (AN Status Register)). -This bit is cleared when you perform a read operation on the AN Status register. - 1 - 1 - read-only - - - RGSMIIIS - RGMII or SMII Interrupt Status -This bit is set because of any change in value of the Link Status of RGMII or SMII interface (Bit 3 in Register 54 (SGMII/RGMII/SMII Control and Status Register)). -This bit is cleared when you perform a read operation on the SGMII/RGMII/SMII Control and Status Register. - 0 - 1 - read-only - - - - - INTR_MASK - Interrupt Mask Register - 0x3c - 32 - 0x00000000 - 0x0000060F - - - LPIIM - LPI Interrupt Mask -When set, this bit disables the assertion of the interrupt signal because of the setting of the LPI Interrupt Status bit in Register 14 (Interrupt Status Register). - 10 - 1 - read-write - - - TSIM - Timestamp Interrupt Mask - When set, this bit disables the assertion of the interrupt signal because of the setting of Timestamp Interrupt Status bit in Register 14 (Interrupt Status Register). - 9 - 1 - read-write - - - PMTIM - PMT Interrupt Mask - When set, this bit disables the assertion of the interrupt signal because of the setting of PMT Interrupt Status bit in Register 14 (Interrupt Status Register). - 3 - 1 - read-write - - - PCSANCIM - PCS AN Completion Interrupt Mask -When set, this bit disables the assertion of the interrupt signal because of the setting of PCS Auto-negotiation complete bit in Register 14 (Interrupt Status Register). - 2 - 1 - read-write - - - PCSLCHGIM - PCS Link Status Interrupt Mask -When set, this bit disables the assertion of the interrupt signal because of the setting of the PCS Link-status changed bit in Register 14 (Interrupt Status Register). - 1 - 1 - read-write - - - RGSMIIIM - RGMII or SMII Interrupt Mask -When set, this bit disables the assertion of the interrupt signal because of the setting of the RGMII or SMII Interrupt Status bit in Register 14 (Interrupt Status Register). - 0 - 1 - read-write - - - - - MAC_ADDR_0_HIGH - MAC Address 0 High Register - 0x40 - 32 - 0x00000000 - 0x8000FFFF - - - AE - Address Enable - This bit is RO. The bit value is fixed at 1. - 31 - 1 - read-only - - - ADDRHI - MAC Address0 [47:32] - This field contains the upper 16 bits (47:32) of the first 6-byte MAC address. The MAC uses this field for filtering the received frames and inserting the MAC address in the Transmit Flow Control (Pause) Frames. - 0 - 16 - read-write - - - - - MAC_ADDR_0_LOW - MAC Address 0 Low Register - 0x44 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDRLO - MAC Address0 [31:0] - This field contains the lower 32 bits of the first 6-byte MAC address. This is used by the MAC for filtering the received frames and inserting the MAC address in the Transmit Flow Control (Pause) Frames. - 0 - 32 - read-write - - - - - 4 - 0x8 - 1,2,3,4 - MAC_ADDR[%s] - no description available - 0x48 - - HIGH - MAC Address High Register - 0x0 - 32 - 0x00000000 - 0xFF00FFFF - - - AE - Address Enable -When this bit is set, the address filter module uses the second MAC address for perfect filtering. When this bit is reset, the address filter module ignores the address for filtering. - 31 - 1 - read-write - - - SA - Source Address -When this bit is set, the MAC Address1[47:0] is used to compare with the SA fields of the received frame. When this bit is reset, the MAC Address1[47:0] is used to compare with the DA fields of the received frame. - 30 - 1 - read-write - - - MBC - Mask Byte Control -These bits are mask control bits for comparison of each of the MAC Address bytes. -When set high, the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. -Each bit controls the masking of the bytes as follows: -- Bit 29: Register 18[15:8] -- Bit 28: Register 18[7:0] -- Bit 27: Register 19[31:24] - -... -- Bit 24: Register 19[7:0] -You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address. - 24 - 6 - read-write - - - ADDRHI - MAC Address1 [47:32] -This field contains the upper 16 bits (47:32) of the second 6-byte MAC address. - 0 - 16 - read-write - - - - - LOW - MAC Address Low Register - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDRLO - MAC Address1 [31:0] -This field contains the lower 32 bits of the second 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process. - 0 - 32 - read-write - - - - - - XMII_CSR - SGMII/RGMII/SMII Control and Status Register - 0xd8 - 32 - 0x00000000 - 0x0000003F - - - FALSCARDET - False Carrier Detected - This bit indicates whether the SMII PHY detected false carrier (1'b1). This bit is reserved when the MAC is configured for the SGMII or RGMII PHY interface. - 5 - 1 - read-write - - - JABTO - Jabber Timeout - This bit indicates whether there is jabber timeout error (1'b1) in the received frame. This bit is reserved when the MAC is configured for the SGMII or RGMII PHY interface. - 4 - 1 - read-write - - - LNKSTS - Link Status - This bit indicates whether the link between the local PHY and the remote PHY is up or down. -It gives the status of the link between the SGMII of MAC and the SGMII of the local PHY. -The status bits are received from the local PHY during ANEG betweent he MAC and PHY on the SGMII link. - 3 - 1 - read-write - - - LNKSPEED - Link Speed - This bit indicates the current speed of the link: -- 00: 2.5 MHz -- 01: 25 MHz -- 10: 125 MHz Bit 2 is reserved when the MAC is configured for the SMII PHY interface. - 1 - 2 - read-write - - - LNKMOD - Link Mode - This bit indicates the current mode of operation of the link: -- 1’b0: Half-duplex mode -- 1’b1: Full-duplex mode - 0 - 1 - read-write - - - - - WDOG_WTO - Watchdog Timeout Register - 0xdc - 32 - 0x00000000 - 0x00013FFF - - - PWE - Programmable Watchdog Enable - When this bit is set and Bit 23 (WD) of Register 0 (MAC Configuration Register) is reset, -the WTO field (Bits[13:0]) is used as watchdog timeout for a received frame. -When this bit is cleared, the watchdog timeout for a received frame is controlled by the setting of Bit 23 (WD) and Bit 20 (JE) in Register 0 (MAC Configuration Register). - 16 - 1 - read-write - - - WTO - Watchdog Timeout -When Bit 16 (PWE) is set and Bit 23 (WD) of Register 0 (MAC Configuration Register) is reset, -this field is used as watchdog timeout for a received frame. - If the length of a received frame exceeds the value of this field, such frame is terminated and declared as an error frame. -Note: When Bit 16 (PWE) is set, the value in this field should be more than 1,522 (0x05F2). -Otherwise, the IEEE Std 802.3-specified valid tagged frames are declared as error frames and are dropped. - 0 - 14 - read-write - - - - - mmc_cntrl - MMC Control establishes the operating mode of MMC. - 0x100 - 32 - 0x00000000 - 0x0000013F - - - UCDBC - Update MMC Counters for Dropped Broadcast Frames -When set, the MAC updates all related MMC Counters for Broadcast frames that are dropped because of the setting of Bit 5 (DBF) of Register 1 (MAC Frame Filter). - When reset, the MMC Counters are not updated for dropped Broadcast frames. - 8 - 1 - read-write - - - CNTPRSTLVL - Full-Half Preset -When this bit is low and Bit 4 is set, all MMC counters get preset to almost-half value. All octet counters get preset to 0x7FFF_F800 (half -- 2KBytes) and all frame-counters gets preset to 0x7FFF_FFF0 (half -- 16). When this bit is high and Bit 4 is set, all MMC counters get preset to almost-full value. All octet counters get preset to 0xFFFF_F800 (full -- 2KBytes) and all frame-counters gets preset to 0xFFFF_FFF0 (full -- 16). For 16-bit counters, the almost-half preset values are 0x7800 and 0x7FF0 for the respective octet and frame counters. Similarly, the almost-full preset values for the 16-bit counters are 0xF800 and 0xFFF0. - 5 - 1 - read-write - - - CNTPRST - Counters Preset -When this bit is set, all counters are initialized or preset to almost full or almost half according to Bit 5. This bit is cleared automatically after 1 clock cycle. -This bit, along with Bit 5, is useful for debugging and testing the assertion of interrupts because of MMC counter becoming half-full or full. - 4 - 1 - read-write - - - CNTFREEZ - MMC Counter Freeze -When this bit is set, it freezes all MMC counters to their current value. -Until this bit is reset to 0, no MMC counter is updated because of any transmitted or received frame. - If any MMC counter is read with the Reset on Read bit set, then that counter is also cleared in this mode. - 3 - 1 - read-write - - - RSTONRD - Reset on Read -When this bit is set, the MMC counters are reset to zero after Read (self-clearing after reset). The counters are cleared when the least significant byte lane (Bits[7:0]) is read. - 2 - 1 - read-write - - - CNTSTOPRO - Counter Stop Rollover -When this bit is set, the counter does not roll over to zero after reaching the maximum value. - 1 - 1 - read-write - - - CNTRST - Counters Reset -When this bit is set, all counters are reset. This bit is cleared automatically after 1 clock cycle - 0 - 1 - read-write - - - - - mmc_intr_rx - MMC Receive Interrupt - 0x104 - 32 - 0x00000000 - 0x03FFFFFF - - - RXCTRLFIS - MMC Receive Control Frame Counter Interrupt Status -This bit is set when the rxctrlframes_g counter reaches half of the maximum value or the maximum value. - 25 - 1 - read-write - - - RXRCVERRFIS - MMC Receive Error Frame Counter Interrupt Status -This bit is set when the rxrcverror counter reaches half of the maximum value or the maximum value. - 24 - 1 - read-write - - - RXWDOGFIS - MMC Receive Watchdog Error Frame Counter Interrupt Status -This bit is set when the rxwatchdog error counter reaches half of the maximum value or the maximum value. - 23 - 1 - read-write - - - RXVLANGBFIS - MMC Receive VLAN Good Bad Frame Counter Interrupt Status -This bit is set when the rxvlanframes_gb counter reaches half of the maximum value or the maximum value. - 22 - 1 - read-write - - - RXFOVFIS - MMC Receive FIFO Overflow Frame Counter Interrupt Status -This bit is set when the rxfifooverflow counter reaches half of the maximum value or the maximum value. - 21 - 1 - read-write - - - RXPAUSFIS - MMC Receive Pause Frame Counter Interrupt Status -This bit is set when the rxpauseframes counter reaches half of the maximum value or the maximum value. - 20 - 1 - read-write - - - RXORANGEFIS - MMC Receive Out Of Range Error Frame Counter Interrupt Status. -This bit is set when the rxoutofrangetype counter reaches half of the maximum value or the maximum value. - 19 - 1 - read-write - - - RXLENERFIS - MMC Receive Length Error Frame Counter Interrupt Status -This bit is set when the rxlengtherror counter reaches half of the maximum value or the maximum value. - 18 - 1 - read-write - - - RXUCGFIS - MMC Receive Unicast Good Frame Counter Interrupt Status -This bit is set when the rxunicastframes_g counter reaches half of the maximum value or the maximum value. - 17 - 1 - read-write - - - RX1024TMAXOCTGBFIS - MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status. -This bit is set when the rx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. - 16 - 1 - read-write - - - RX512T1023OCTGBFIS - MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the rx512to1023octets_gb counter reaches half of the maximum value or the maximum value. - 15 - 1 - read-write - - - RX256T511OCTGBFIS - MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the rx256to511octets_gb counter reaches half of the maximum value or the maximum value. - 14 - 1 - read-write - - - RX128T255OCTGBFIS - MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the rx128to255octets_gb counter reaches half of the maximum value or the maximum value. - 13 - 1 - read-write - - - RX65T127OCTGBFIS - MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the rx65to127octets_gb counter reaches half of the maximum value or the maximum value. - 12 - 1 - read-write - - - RX64OCTGBFIS - MMC Receive 64 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the rx64octets_gb counter reaches half of the maximum value or the maximum value. - 11 - 1 - read-write - - - RXOSIZEGFIS - MMC Receive Oversize Good Frame Counter Interrupt Status -This bit is set when the rxoversize_g counter reaches half of the maximum value or the maximum value. - 10 - 1 - read-write - - - RXUSIZEGFIS - MMC Receive Undersize Good Frame Counter Interrupt Status -This bit is set when the rxundersize_g counter reaches half of the maximum value or the maximum value. - 9 - 1 - read-write - - - RXJABERFIS - MMC Receive Jabber Error Frame Counter Interrupt Status -This bit is set when the rxjabbererror counter reaches half of the maximum value or the maximum value. - 8 - 1 - read-write - - - RXRUNTFIS - MMC Receive Runt Frame Counter Interrupt Status -This bit is set when the rxrunterror counter reaches half of the maximum value or the maximum value. - 7 - 1 - read-write - - - RXALGNERFIS - MMC Receive Alignment Error Frame Counter Interrupt Status -This bit is set when the rxalignmenterror counter reaches half of the maximum value or the maximum value. - 6 - 1 - read-write - - - RXCRCERFIS - MMC Receive CRC Error Frame Counter Interrupt Status -This bit is set when the rxcrcerror counter reaches half of the maximum value or the maximum value. - 5 - 1 - read-write - - - RXMCGFIS - MMC Receive Multicast Good Frame Counter Interrupt Status -This bit is set when the rxmulticastframes_g counter reaches half of the maximum value or the maximum value. - 4 - 1 - read-write - - - RXBCGFIS - MMC Receive Broadcast Good Frame Counter Interrupt Status -This bit is set when the rxbroadcastframes_g counter reaches half of the maximum value or the maximum value. - 3 - 1 - read-write - - - RXGOCTIS - MMC Receive Good Octet Counter Interrupt Status -This bit is set when the rxoctetcount_g counter reaches half of the maximum value or the maximum value. - 2 - 1 - read-write - - - RXGBOCTIS - MMC Receive Good Bad Octet Counter Interrupt Status -This bit is set when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value. - 1 - 1 - read-write - - - RXGBFRMIS - MMC Receive Good Bad Frame Counter Interrupt Status -This bit is set when the rxframecount_gb counter reaches half of the maximum value or the maximum value. - 0 - 1 - read-write - - - - - mmc_intr_tx - MMC Transmit Interrupt - 0x108 - 32 - 0x00000000 - 0x03FFFFFF - - - TXOSIZEGFIS - MMC Transmit Oversize Good Frame Counter Interrupt Status -This bit is set when the txoversize_g counter reaches half of the maximum value or the maximum value. - 25 - 1 - read-write - - - TXVLANGFIS - MMC Transmit VLAN Good Frame Counter Interrupt Status -This bit is set when the txvlanframes_g counter reaches half of the maximum value or the maximum value. - 24 - 1 - read-write - - - TXPAUSFIS - MMC Transmit Pause Frame Counter Interrupt Status -This bit is set when the txpauseframeserror counter reaches half of the maximum value or the maximum value. - 23 - 1 - read-write - - - TXEXDEFFIS - MMC Transmit Excessive Deferral Frame Counter Interrupt Status -This bit is set when the txexcessdef counter reaches half of the maximum value or the maximum value. - 22 - 1 - read-write - - - TXGFRMIS - MMC Transmit Good Frame Counter Interrupt Status -This bit is set when the txframecount_g counter reaches half of the maximum value or the maximum value. - 21 - 1 - read-write - - - TXGOCTIS - MMC Transmit Good Octet Counter Interrupt Status -This bit is set when the txoctetcount_g counter reaches half of the maximum value or the maximum value. - 20 - 1 - read-write - - - TXCARERFIS - MMC Transmit Carrier Error Frame Counter Interrupt Status -This bit is set when the txcarriererror counter reaches half of the maximum value or the maximum value. - 19 - 1 - read-write - - - TXEXCOLFIS - MMC Transmit Excessive Collision Frame Counter Interrupt Status -This bit is set when the txexesscol counter reaches half of the maximum value or the maximum value. - 18 - 1 - read-write - - - TXLATCOLFIS - MMC Transmit Late Collision Frame Counter Interrupt Status -This bit is set when the txlatecol counter reaches half of the maximum value or the maximum value. - 17 - 1 - read-write - - - TXDEFFIS - MMC Transmit Deferred Frame Counter Interrupt Status -This bit is set when the txdeferred counter reaches half of the maximum value or the maximum value. - 16 - 1 - read-write - - - TXMCOLGFIS - MMC Transmit Multiple Collision Good Frame Counter Interrupt Status -This bit is set when the txmulticol_g counter reaches half of the maximum value or the maximum value. - 15 - 1 - read-write - - - TXSCOLGFIS - MMC Transmit Single Collision Good Frame Counter Interrupt Status -This bit is set when the txsinglecol_g counter reaches half of the maximum value or the maximum value. - 14 - 1 - read-write - - - TXUFLOWERFIS - MMC Transmit Underflow Error Frame Counter Interrupt Status -This bit is set when the txunderflowerror counter reaches half of the maximum value or the maximum value. - 13 - 1 - read-write - - - TXBCGBFIS - MMC Transmit Broadcast Good Bad Frame Counter Interrupt Status -This bit is set when the txbroadcastframes_gb counter reaches half of the maximum value or the maximum value. - 12 - 1 - read-write - - - TXMCGBFIS - MMC Transmit Multicast Good Bad Frame Counter Interrupt Status -The bit is set when the txmulticastframes_gb counter reaches half of the maximum value or the maximum value. - 11 - 1 - read-write - - - TXUCGBFIS - MMC Transmit Unicast Good Bad Frame Counter Interrupt Status -This bit is set when the txunicastframes_gb counter reaches half of the maximum value or the maximum value. - 10 - 1 - read-write - - - TX1024TMAXOCTGBFIS - MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status -This bit is set when the tx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. - 9 - 1 - read-write - - - TX512T1023OCTGBFIS - MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the tx512to1023octets_gb counter reaches half of the maximum value or the maximum value. - 8 - 1 - read-write - - - TX256T511OCTGBFIS - MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the tx256to511octets_gb counter reaches half of the maximum value or the maximum value. - 7 - 1 - read-write - - - TX128T255OCTGBFIS - MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the tx128to255octets_gb counter reaches half of the maximum value or the maximum value. - 6 - 1 - read-write - - - TX65T127OCTGBFIS - MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the tx65to127octets_gb counter reaches half the maximum value, and also when it reaches the maximum value. - 5 - 1 - read-write - - - TX64OCTGBFIS - MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the tx64octets_gb counter reaches half of the maximum value or the maximum value. - 4 - 1 - read-write - - - TXMCGFIS - MMC Transmit Multicast Good Frame Counter Interrupt Status -This bit is set when the txmulticastframes_g counter reaches half of the maximum value or the maximum value. - 3 - 1 - read-write - - - TXBCGFIS - MMC Transmit Broadcast Good Frame Counter Interrupt Status -This bit is set when the txbroadcastframes_g counter reaches half of the maximum value or the maximum value. - 2 - 1 - read-write - - - TXGBFRMIS - MMC Transmit Good Bad Frame Counter Interrupt Status -This bit is set when the txframecount_gb counter reaches half of the maximum value or the maximum value. - 1 - 1 - read-write - - - TXGBOCTIS - MMC Transmit Good Bad Octet Counter Interrupt Status -This bit is set when the txoctetcount_gb counter reaches half of the maximum value or the maximum value. - 0 - 1 - read-write - - - - - mmc_intr_mask_rx - MMC Receive Interrupt mask - 0x10c - 32 - 0x00000000 - 0x03FFFFFE - - - RXCTRLFIM - MMC Receive Control Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxctrlframes_g counter reaches half of the maximum value or the maximum value. - 25 - 1 - read-write - - - RXRCVERRFIM - MMC Receive Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxrcverror counter reaches half of the maximum value or the maximum value. - 24 - 1 - read-write - - - RXWDOGFIM - MMC Receive Watchdog Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxwatchdog counter reaches half of the maximum value or the maximum value. - 23 - 1 - read-write - - - RXVLANGBFIM - MMC Receive VLAN Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxvlanframes_gb counter reaches half of the maximum value or the maximum value. - 22 - 1 - read-write - - - RXFOVFIM - MMC Receive FIFO Overflow Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxfifooverflow counter reaches half of the maximum value or the maximum value. - 21 - 1 - read-write - - - RXPAUSFIM - MMC Receive Pause Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxpauseframes counter reaches half of the maximum value or the maximum value. - 20 - 1 - read-write - - - RXORANGEFIM - MMC Receive Out Of Range Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxoutofrangetype counter reaches half of the maximum value or the maximum value. - 19 - 1 - read-write - - - RXLENERFIM - MMC Receive Length Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxlengtherror counter reaches half of the maximum value or the maximum value. - 18 - 1 - read-write - - - RXUCGFIM - MMC Receive Unicast Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxunicastframes_g counter reaches half of the maximum value or the maximum value. - 17 - 1 - read-write - - - RX1024TMAXOCTGBFIM - MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask. -Setting this bit masks the interrupt when the rx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. - 16 - 1 - read-write - - - RX512T1023OCTGBFIM - MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rx512to1023octets_gb counter reaches half of the maximum value or the maximum value. - 15 - 1 - read-write - - - RX256T511OCTGBFIM - MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rx256to511octets_gb counter reaches half of the maximum value or the maximum value. - 14 - 1 - read-write - - - RX128T255OCTGBFIM - MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rx128to255octets_gb counter reaches half of the maximum value or the maximum value. - 13 - 1 - read-write - - - RX65T127OCTGBFIM - MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rx65to127octets_gb counter reaches half of the maximum value or the maximum value. - 12 - 1 - read-write - - - RX64OCTGBFIM - MMC Receive 64 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rx64octets_gb counter reaches half of the maximum value or the maximum value. - 11 - 1 - read-write - - - RXOSIZEGFIM - MMC Receive Oversize Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxoversize_g counter reaches half of the maximum value or the maximum value. - 10 - 1 - read-write - - - RXUSIZEGFIM - MMC Receive Undersize Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxundersize_g counter reaches half of the maximum value or the maximum value. - 9 - 1 - read-write - - - RXJABERFIM - MMC Receive Jabber Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxjabbererror counter reaches half of the maximum value or the maximum value. - 8 - 1 - read-write - - - RXRUNTFIM - MMC Receive Runt Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxrunterror counter reaches half of the maximum value or the maximum value. - 7 - 1 - read-write - - - RXALGNERFIM - MMC Receive Alignment Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxalignmenterror counter reaches half of the maximum value or the maximum value. - 6 - 1 - read-write - - - RXCRCERFIM - MMC Receive CRC Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxcrcerror counter reaches half of the maximum value or the maximum value. - 5 - 1 - read-write - - - RXMCGFIM - MMC Receive Multicast Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxmulticastframes_g counter reaches half of the maximum value or the maximum value. - 4 - 1 - read-write - - - RXBCGFIM - MMC Receive Broadcast Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxbroadcastframes_g counter reaches half of the maximum value or the maximum value. - 3 - 1 - read-write - - - RXGOCTIM - MMC Receive Good Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxoctetcount_g counter reaches half of the maximum value or the maximum value. - 2 - 1 - read-write - - - RXGBOCTIM - MMC Receive Good Bad Octet Counter Interrupt Mask. -Setting this bit masks the interrupt when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value. - 1 - 1 - read-write - - - - - mmc_intr_mask_tx - MMC Transmit Interrupt Mask - 0x110 - 32 - 0x00000000 - 0x03FFFFFF - - - TXOSIZEGFIM - MMC Transmit Oversize Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txoversize_g counter reaches half of the maximum value or the maximum value. - 25 - 1 - read-write - - - TXVLANGFIM - MMC Transmit VLAN Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txvlanframes_g counter reaches half of the maximum value or the maximum value. - 24 - 1 - read-write - - - TXPAUSFIM - MMC Transmit Pause Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txpauseframes counter reaches half of the maximum value or the maximum value. - 23 - 1 - read-write - - - TXEXDEFFIM - MMC Transmit Excessive Deferral Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txexcessdef counter reaches half of the maximum value or the maximum value. - 22 - 1 - read-write - - - TXGFRMIM - MMC Transmit Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txframecount_g counter reaches half of the maximum value or the maximum value. - 21 - 1 - read-write - - - TXGOCTIM - MMC Transmit Good Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the txoctetcount_g counter reaches half of the maximum value or the maximum value. - 20 - 1 - read-write - - - TXCARERFIM - MMC Transmit Carrier Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txcarriererror counter reaches half of the maximum value or the maximum value. - 19 - 1 - read-write - - - TXEXCOLFIM - MMC Transmit Excessive Collision Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txexcesscol counter reaches half of the maximum value or the maximum value. - 18 - 1 - read-write - - - TXLATCOLFIM - MMC Transmit Late Collision Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txlatecol counter reaches half of the maximum value or the maximum value. - 17 - 1 - read-write - - - TXDEFFIM - MMC Transmit Deferred Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txdeferred counter reaches half of the maximum value or the maximum value. - 16 - 1 - read-write - - - TXMCOLGFIM - MMC Transmit Multiple Collision Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txmulticol_g counter reaches half of the maximum value or the maximum value. - 15 - 1 - read-write - - - TXSCOLGFIM - MMC Transmit Single Collision Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txsinglecol_g counter reaches half of the maximum value or the maximum value. - 14 - 1 - read-write - - - TXUFLOWERFIM - MMC Transmit Underflow Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txunderflowerror counter reaches half of the maximum value or the maximum value. - 13 - 1 - read-write - - - TXBCGBFIM - MMC Transmit Broadcast Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txbroadcastframes_gb counter reaches half of the maximum value or the maximum value. - 12 - 1 - read-write - - - TXMCGBFIM - MMC Transmit Multicast Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txmulticastframes_gb counter reaches half of the maximum value or the maximum value. - 11 - 1 - read-write - - - TXUCGBFIM - MMC Transmit Unicast Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txunicastframes_gb counter reaches half of the maximum value or the maximum value. - 10 - 1 - read-write - - - TX1024TMAXOCTGBFIM - MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the tx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. - 9 - 1 - read-write - - - TX512T1023OCTGBFIM - MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the tx512to1023octets_gb counter reaches half of the maximum value or the maximum value. - 8 - 1 - read-write - - - TX256T511OCTGBFIM - MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the tx256to511octets_gb counter reaches half of the maximum value or the maximum value. - 7 - 1 - read-write - - - TX128T255OCTGBFIM - MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the tx128to255octets_gb counter reaches half of the maximum value or the maximum value. - 6 - 1 - read-write - - - TX65T127OCTGBFIM - MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the tx65to127octets_gb counter reaches half of the maximum value or the maximum value. - 5 - 1 - read-write - - - TX64OCTGBFIM - MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the tx64octets_gb counter reaches half of the maximum value or the maximum value. - 4 - 1 - read-write - - - TXMCGFIM - MMC Transmit Multicast Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txmulticastframes_g counter reaches half of the maximum value or the maximum value. - 3 - 1 - read-write - - - TXBCGFIM - MMC Transmit Broadcast Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txbroadcastframes_g counter reaches half of the maximum value or the maximum value. - 2 - 1 - read-write - - - TXGBFRMIM - MMC Transmit Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txframecount_gb counter reaches half of the maximum value or the maximum value. - 1 - 1 - read-write - - - TXGBOCTIM - MMC Transmit Good Bad Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the txoctetcount_gb counter reaches half of the maximum value or the maximum value. - 0 - 1 - read-write - - - - - tx64octets_gb - Number of good and bad frames transmitted with length 64 bytes, -exclusive of preamble and retried frames. - 0x124 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames transmitted with length 64 bytes, exclusive of preamble and retried frames. - 0 - 32 - read-write - - - - - tx65to127octets_gb - Number of good and bad frames transmitted with length between -65 and 127 (inclusive) bytes, exclusive of preamble and retried -frames. - 0x128 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames transmitted with length between 65 and 127 (inclusive) bytes, exclusive of preamble and retried frames. - 0 - 32 - read-write - - - - - tx128to255octets_gb - Number of good and bad frames transmitted with length between -128 and 255 (inclusive) bytes, exclusive of preamble and retried -frames. - 0x12c - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames transmitted with length between 128 and 255 (inclusive) bytes, exclusive of preamble and retried frames. - 0 - 32 - read-write - - - - - tx256to511octets_gb - Number of good and bad frames transmitted with length between -256 and 511 (inclusive) bytes, exclusive of preamble and retried -frames. - 0x130 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames transmitted with length between 256 and 511 (inclusive) bytes, exclusive of preamble and retried frames. - 0 - 32 - read-write - - - - - tx512to1023octets_gb - Number of good and bad frames transmitted with length between -512 and 1,023 (inclusive) bytes, exclusive of preamble and retried -frames. - 0x134 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames transmitted with length between 512 and 1,023 (inclusive) bytes, exclusive of preamble and retried frames. - 0 - 32 - read-write - - - - - tx1024tomaxoctets_gb - Number of good and bad frames transmitted with length between -1,024 and maxsize (inclusive) bytes, exclusive of preamble and -retried frames. - 0x138 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames transmitted with length between 1,024 and maxsize (inclusive) bytes, exclusive of preamble and retried frames. - 0 - 32 - read-write - - - - - rxframecount_gb - Number of good and bad frames received - 0x180 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames received. - 0 - 32 - read-write - - - - - mmc_ipc_intr_mask_rx - MMC IPC Receive Checksum Offload Interrupt Mask maintains -the mask for the interrupt generated from the receive IPC statistic -counters. - 0x200 - 32 - 0x00000000 - 0x3FFF3FFF - - - RXICMPEROIM - MMC Receive ICMP Error Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxicmp_err_octets counter reaches half of the maximum value or the maximum value. - 29 - 1 - read-write - - - RXICMPGOIM - MMC Receive ICMP Good Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxicmp_gd_octets counter reaches half of the maximum value or the maximum value. - 28 - 1 - read-write - - - RXTCPEROIM - MMC Receive TCP Error Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxtcp_err_octets counter reaches half of the maximum value or the maximum value. - 27 - 1 - read-write - - - RXTCPGOIM - MMC Receive TCP Good Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxtcp_gd_octets counter reaches half of the maximum value or the maximum value. - 26 - 1 - read-write - - - RXUDPEROIM - MMC Receive UDP Good Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxudp_err_octets counter reaches half of the maximum value or the maximum value. - 25 - 1 - read-write - - - RXUDPGOIM - MMC Receive IPV6 No Payload Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxudp_gd_octets counter reaches half of the maximum value or the maximum value. - 24 - 1 - read-write - - - RXIPV6NOPAYOIM - MMC Receive IPV6 Header Error Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv6_nopay_octets counter reaches half of the maximum value or the maximum value. - 23 - 1 - read-write - - - RXIPV6HEROIM - MMC Receive IPV6 Good Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum value. - 22 - 1 - read-write - - - RXIPV6GOIM - MMC Receive IPV6 Good Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv6_gd_octets counter reaches half of the maximum value or the maximum value. - 21 - 1 - read-write - - - RXIPV4UDSBLOIM - MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_udsbl_octets counter reaches half of the maximum value or the maximum value. - 20 - 1 - read-write - - - RXIPV4FRAGOIM - MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_frag_octets counter reaches half of the maximum value or the maximum value. - 19 - 1 - read-write - - - RXIPV4NOPAYOIM - MMC Receive IPV4 No Payload Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_nopay_octets counter reaches half of the maximum value or the maximum value. - 18 - 1 - read-write - - - RXIPV4HEROIM - MMC Receive IPV4 Header Error Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_hdrerr_octets counter reaches half of the maximum value or the maximum value. - 17 - 1 - read-write - - - RXIPV4GOIM - MMC Receive IPV4 Good Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_gd_octets counter reaches half of the maximum value or the maximum value. - 16 - 1 - read-write - - - RXICMPERFIM - MMC Receive ICMP Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxicmp_err_frms counter reaches half of the maximum value or the maximum value. - 13 - 1 - read-write - - - RXICMPGFIM - MMC Receive ICMP Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxicmp_gd_frms counter reaches half of the maximum value or the maximum value. - 12 - 1 - read-write - - - RXTCPERFIM - MMC Receive TCP Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxtcp_err_frms counter reaches half of the maximum value or the maximum value. - 11 - 1 - read-write - - - RXTCPGFIM - MMC Receive TCP Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxtcp_gd_frms counter reaches half of the maximum value or the maximum value. - 10 - 1 - read-write - - - RXUDPERFIM - MMC Receive UDP Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxudp_err_frms counter reaches half of the maximum value or the maximum value. - 9 - 1 - read-write - - - RXUDPGFIM - MMC Receive UDP Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxudp_gd_frms counter reaches half of the maximum value or the maximum value. - 8 - 1 - read-write - - - RXIPV6NOPAYFIM - MMC Receive IPV6 No Payload Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv6_nopay_frms counter reaches half of the maximum value or the maximum value. - 7 - 1 - read-write - - - RXIPV6HERFIM - MMC Receive IPV6 Header Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv6_hdrerr_frms counter reaches half of the maximum value or the maximum value. - 6 - 1 - read-write - - - RXIPV6GFIM - MMC Receive IPV6 Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv6_gd_frms counter reaches half of the maximum value or the maximum value. - 5 - 1 - read-write - - - RXIPV4UDSBLFIM - MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_udsbl_frms counter reaches half of the maximum value or the maximum value. - 4 - 1 - read-write - - - RXIPV4FRAGFIM - MMC Receive IPV4 Fragmented Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_frag_frms counter reaches half of the maximum value or the maximum value. - 3 - 1 - read-write - - - RXIPV4NOPAYFIM - MMC Receive IPV4 No Payload Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_nopay_frms counter reaches half of the maximum value or the maximum value. - 2 - 1 - read-write - - - RXIPV4HERFIM - MMC Receive IPV4 Header Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_hdrerr_frms counter reaches half of the maximum value or the maximum value. - 1 - 1 - read-write - - - RXIPV4GFIM - MMC Receive IPV4 Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_gd_frms counter reaches half of the maximum value or the maximum value. - 0 - 1 - read-write - - - - - mmc_ipc_intr_rx - MMC Receive Checksum Offload Interrupt maintains the interrupt -that the receive IPC statistic counters generate. See Table 4-25 -for further detail. - 0x208 - 32 - 0x00000000 - 0x3FFF3FFF - - - RXICMPEROIS - MMC Receive ICMP Error Octet Counter Interrupt Status -This bit is set when the rxicmp_err_octets counter reaches half of the maximum value or the maximum value. - 29 - 1 - read-write - - - RXICMPGOIS - MMC Receive ICMP Good Octet Counter Interrupt Status -This bit is set when the rxicmp_gd_octets counter reaches half of the maximum value or the maximum value. - 28 - 1 - read-write - - - RXTCPEROIS - MMC Receive TCP Error Octet Counter Interrupt Status -This bit is set when the rxtcp_err_octets counter reaches half of the maximum value or the maximum value. - 27 - 1 - read-write - - - RXTCPGOIS - MMC Receive TCP Good Octet Counter Interrupt Status -This bit is set when the rxtcp_gd_octets counter reaches half of the maximum value or the maximum value - 26 - 1 - read-write - - - RXUDPEROIS - MMC Receive UDP Error Octet Counter Interrupt Status -This bit is set when the rxudp_err_octets counter reaches half of the maximum value or the maximum value. - 25 - 1 - read-write - - - RXUDPGOIS - MMC Receive UDP Good Octet Counter Interrupt Status -This bit is set when the rxudp_gd_octets counter reaches half of the maximum value or the maximum value. - 24 - 1 - read-write - - - RXIPV6NOPAYOIS - MMC Receive IPV6 No Payload Octet Counter Interrupt Status -This bit is set when the rxipv6_nopay_octets counter reaches half of the maximum value or the maximum value. - 23 - 1 - read-write - - - RXIPV6HEROIS - MMC Receive IPV6 Header Error Octet Counter Interrupt Status -This bit is set when the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum value. - 22 - 1 - read-write - - - RXIPV6GOIS - MMC Receive IPV6 Good Octet Counter Interrupt Status -This bit is set when the rxipv6_gd_octets counter reaches half of the maximum value or the maximum value. - 21 - 1 - read-write - - - RXIPV4UDSBLOIS - MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status -This bit is set when the rxipv4_udsbl_octets counter reaches half of the maximum value or the maximum value. - 20 - 1 - read-write - - - RXIPV4FRAGOIS - MMC Receive IPV4 Fragmented Octet Counter Interrupt Status -This bit is set when the rxipv4_frag_octets counter reaches half of the maximum value or the maximum value. - 19 - 1 - read-write - - - RXIPV4NOPAYOIS - MMC Receive IPV4 No Payload Octet Counter Interrupt Status -This bit is set when the rxipv4_nopay_octets counter reaches half of the maximum value or the maximum value. - 18 - 1 - read-write - - - RXIPV4HEROIS - MMC Receive IPV4 Header Error Octet Counter Interrupt Status -This bit is set when the rxipv4_hdrerr_octets counter reaches half of the maximum value or the maximum value. - 17 - 1 - read-write - - - RXIPV4GOIS - MMC Receive IPV4 Good Octet Counter Interrupt Status -This bit is set when the rxipv4_gd_octets counter reaches half of the maximum value or the maximum value. - 16 - 1 - read-write - - - RXICMPERFIS - MMC Receive ICMP Error Frame Counter Interrupt Status -This bit is set when the rxicmp_err_frms counter reaches half of the maximum value or the maximum value. - 13 - 1 - read-write - - - RXICMPGFIS - MMC Receive ICMP Good Frame Counter Interrupt Status -This bit is set when the rxicmp_gd_frms counter reaches half of the maximum value or the maximum value. - 12 - 1 - read-write - - - RXTCPERFIS - MMC Receive TCP Error Frame Counter Interrupt Status -This bit is set when the rxtcp_err_frms counter reaches half of the maximum value or the maximum value. - 11 - 1 - read-write - - - RXTCPGFIS - MMC Receive TCP Good Frame Counter Interrupt Status -This bit is set when the rxtcp_gd_frms counter reaches half of the maximum value or the maximum value. - 10 - 1 - read-write - - - RXUDPERFIS - MMC Receive UDP Error Frame Counter Interrupt Status -This bit is set when the rxudp_err_frms counter reaches half of the maximum value or the maximum value. - 9 - 1 - read-write - - - RXUDPGFIS - MMC Receive UDP Good Frame Counter Interrupt Status -This bit is set when the rxudp_gd_frms counter reaches half of the maximum value or the maximum value. - 8 - 1 - read-write - - - RXIPV6NOPAYFIS - MMC Receive IPV6 No Payload Frame Counter Interrupt Status -This bit is set when the rxipv6_nopay_frms counter reaches half of the maximum value or the maximum value. - 7 - 1 - read-write - - - RXIPV6HERFIS - MMC Receive IPV6 Header Error Frame Counter Interrupt Status -This bit is set when the rxipv6_hdrerr_frms counter reaches half of the maximum value or the maximum value. - 6 - 1 - read-write - - - RXIPV6GFIS - MMC Receive IPV6 Good Frame Counter Interrupt Status -This bit is set when the rxipv6_gd_frms counter reaches half of the maximum value or the maximum value. - 5 - 1 - read-write - - - RXIPV4UDSBLFIS - MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Status -This bit is set when the rxipv4_udsbl_frms counter reaches half of the maximum value or the maximum value. - 4 - 1 - read-write - - - RXIPV4FRAGFIS - MMC Receive IPV4 Fragmented Frame Counter Interrupt Status -This bit is set when the rxipv4_frag_frms counter reaches half of the maximum value or the maximum value. - 3 - 1 - read-write - - - RXIPV4NOPAYFIS - MMC Receive IPV4 No Payload Frame Counter Interrupt Status -This bit is set when the rxipv4_nopay_frms counter reaches half of the maximum value or the maximum value. - 2 - 1 - read-write - - - RXIPV4HERFIS - MMC Receive IPV4 Header Error Frame Counter Interrupt Status -This bit is set when the rxipv4_hdrerr_frms counter reaches half of the maximum value or the maximum value. - 1 - 1 - read-write - - - RXIPV4GFIS - MMC Receive IPV4 Good Frame Counter Interrupt Status -This bit is set when the rxipv4_gd_frms counter reaches half of the maximum value or the maximum value. - 0 - 1 - read-write - - - - - rxipv4_gd_fms - Number of good IPv4 datagrams received with the TCP, UDP, or -ICMP payload - 0x210 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good IPv4 datagrams received with the TCP, UDP, or ICMP payload - 0 - 32 - read-write - - - - - 1 - 0x20 - 0 - L3_L4_CFG[%s] - no description available - 0x400 - - L3_L4_CTRL - Layer 3 and Layer 4 Control Register - 0x0 - 32 - 0x00000000 - 0x003DFFFD - - - L4DPIM0 - Layer 4 Destination Port Inverse Match Enable - When set, this bit indicates that the Layer 4 Destination Port number field is enabled for inverse matching. -When reset, this bit indicates that the Layer 4 Destination Port number field is enabled for perfect matching. - This bit is valid and applicable only when Bit 20 (L4DPM0) is set high. - 21 - 1 - read-write - - - L4DPM0 - Layer 4 Destination Port Match Enable - When set, this bit indicates that the Layer 4 Destination Port number field is enabled for matching. -When reset, the MAC ignores the Layer 4 Destination Port number field for matching. - 20 - 1 - read-write - - - L4SPIM0 - Layer 4 Source Port Inverse Match Enable -When set, this bit indicates that the Layer 4 Source Port number field is enabled for inverse matching. -When reset, this bit indicates that the Layer 4 Source Port number field is enabled for perfect matching. -This bit is valid and applicable only when Bit 18 (L4SPM0) is set high. - 19 - 1 - read-write - - - L4SPM0 - Layer 4 Source Port Match Enable -When set, this bit indicates that the Layer 4 Source Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Source Port number field for matching. - 18 - 1 - read-write - - - L4PEN0 - Layer 4 Protocol Enable -When set, this bit indicates that the Source and Destination Port number fields for UDP frames are used for matching. -When reset, this bit indicates that the Source and Destination Port number fields for TCP frames are used for matching. -The Layer 4 matching is done only when either L4SPM0 or L4DPM0 bit is set high. - 16 - 1 - read-write - - - L3HDBM0 - Layer 3 IP DA Higher Bits Match - IPv4 Frames: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 frames. The following list describes the values of this field: -- 0: No bits are masked. -- 1: LSb[0] is masked. -- 2: Two LSbs [1:0] are masked. - ... -- 31: All bits except MSb are masked. IPv6 Frames: Bits [12:11] of this field correspond to Bits [6:5] of L3HSBM0, -which indicate the number of lower bits of IP Source or Destination Address that are masked in the IPv6 frames. -The following list describes the concatenated values of the L3HDBM0[1:0] and L3HSBM0 bits: -- 0: No bits are masked. -- 1: LSb[0] is masked. -- 2: Two LSbs [1:0] are masked. - … -- 127: All bits except MSb are masked. This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. - 11 - 5 - read-write - - - L3HSBM0 - Layer 3 IP SA Higher Bits Match - IPv4 Frames: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 frames. The following list describes the values of this field: -- 0: No bits are masked. -- 1: LSb[0] is masked. -- 2: Two LSbs [1:0] are masked. - ... -- 31: All bits except MSb are masked. IPv6 Frames: This field contains Bits [4:0] of the field that indicates the number of higher bits of IP Source or Destination Address matched in the IPv6 frames. -This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. - 6 - 5 - read-write - - - L3DAIM0 - Layer 3 IP DA Inverse Match Enable -When set, this bit indicates that the Layer 3 IP Destination Address field is enabled for inverse matching. -When reset, this bit indicates that the Layer 3 IP Destination Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 4 (L3DAM0) is set high. - 5 - 1 - read-write - - - L3DAM0 - Layer 3 IP DA Match Enable -When set, this bit indicates that Layer 3 IP Destination Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Destination Address field for matching. -Note: When Bit 0 (L3PEN0) is set, you should set either this bit or Bit 2 (L3SAM0) because either IPv6 DA or SA can be checked for filtering. - 4 - 1 - read-write - - - L3SAIM0 - Layer 3 IP SA Inverse Match Enable -When set, this bit indicates that the Layer 3 IP Source Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Source Address field is enabled for perfect matching. -This bit is valid and applicable only when Bit 2 (L3SAM0) is set high. - 3 - 1 - read-write - - - L3SAM0 - Layer 3 IP SA Match Enable -When set, this bit indicates that the Layer 3 IP Source Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Source Address field for matching. - 2 - 1 - read-write - - - L3PEN0 - Layer 3 Protocol Enable - When set, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv6 frames. -When reset, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv4 frames. -The Layer 3 matching is done only when either L3SAM0 or L3DAM0 bit is set high. - 0 - 1 - read-write - - - - - L4_Addr - Layer 4 Address Register - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - L4DP0 - Layer 4 Destination Port Number Field -When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), -this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 frames. -When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), -this field contains the value to be matched with the UDP Destination Port Number field in the IPv4 or IPv6 frames. - 16 - 16 - read-write - - - L4SP0 - Layer 4 Source Port Number Field - When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), - this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 frames. -When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), -this field contains the value to be matched with the UDP Source Port Number field in the IPv4 or IPv6 frames. - 0 - 16 - read-write - - - - - L3_Addr_0 - Layer 3 Address 0 Register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - L3A00 - Layer 3 Address 0 Field - When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), -this field contains the value to be matched with Bits [31:0] of the IP Source Address field in the IPv6 frames. -When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), -this field contains the value to be matched with Bits [31:0] of the IP Destination Address field in the IPv6 frames. -When Bit 0 (L3PEN0) is reset and Bit 2 (L3SAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), -this field contains the value to be matched with the IP Source Address field in the IPv4 frames. - 0 - 32 - read-write - - - - - L3_Addr_1 - Layer 3 Address 1 Register - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - L3A10 - Layer 3 Address 1 Field - When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), -this field contains the value to be matched with Bits [63:32] of the IP Source Address field in the IPv6 frames. -When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), -this field contains the value to be matched with Bits [63:32] of the IP Destination Address field in the IPv6 frames. -When Bit 0 (L3PEN0) is reset and Bit 4 (L3DAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), - this field contains the value to be matched with the IP Destination Address field in the IPv4 frames. - 0 - 32 - read-write - - - - - L3_Addr_2 - Layer 3 Address 2 Register - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - L3A20 - Layer 3 Address 2 Field - When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), -this field contains the value to be matched with Bits [95:64] of the IP Source Address field in the IPv6 frames. -When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), -this field contains value to be matched with Bits [95:64] of the IP Destination Address field in the IPv6 frames. -When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. - 0 - 32 - read-write - - - - - L3_Addr_3 - Layer 3 Address 3 Register - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - L3A30 - Layer 3 Address 3 Field When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), -this field contains the value to be matched with Bits [127:96] of the IP Source Address field in the IPv6 frames. - When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), -this field contains the value to be matched with Bits [127:96] of the IP Destination Address field in the IPv6 frames. -When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. - 0 - 32 - read-write - - - - - - VLAN_TAG_INC_RPL - VLAN Tag Inclusion or Replacement Register - 0x584 - 32 - 0x00000000 - 0x000FFFFF - - - CSVL - C-VLAN or S-VLAN - When this bit is set, S-VLAN type (0x88A8) is inserted or replaced in the 13th and 14th bytes of transmitted frames. When this bit is reset, C-VLAN type (0x8100) is inserted or replaced in the transmitted frames. - 19 - 1 - read-write - - - VLP - VLAN Priority Control -When this bit is set, the control Bits [17:16] are used for VLAN deletion, insertion, or replacement. When this bit is reset, the mti_vlan_ctrl_i control input is used, and Bits [17:16] are ignored. - 18 - 1 - read-write - - - VLC - VLAN Tag Control in Transmit Frames -- 2’b00: No VLAN tag deletion, insertion, or replacement -- 2’b01: VLAN tag deletion The MAC removes the VLAN type (bytes 13 and 14) and VLAN tag (bytes 15 and 16) of all transmitted frames with VLAN tags. -- 2’b10: VLAN tag insertion The MAC inserts VLT in bytes 15 and 16 of the frame after inserting the Type value (0x8100/0x88a8) in bytes 13 and 14. -This operation is performed on all transmitted frames, irrespective of whether they already have a VLAN tag. -- 2’b11: VLAN tag replacement The MAC replaces VLT in bytes 15 and 16 of all VLAN-type transmitted frames (Bytes 13 and 14 are 0x8100/0x88a8). -Note: Changes to this field take effect only on the start of a frame. -If you write this register field when a frame is being transmitted, only the subsequent frame can use the updated value, that is, the current frame does not use the updated value. - 16 - 2 - read-write - - - VLT - VLAN Tag for Transmit Frames - This field contains the value of the VLAN tag to be inserted or replaced. The value must only be changed when the transmit lines are inactive or during the initialization phase. - Bits[15:13] are the User Priority, Bit 12 is the CFI/DEI, and Bits[11:0] are the VLAN tag’s VID field. - 0 - 16 - read-write - - - - - VLAN_HASH - VLAN Hash Table Register - 0x588 - 32 - 0x00000000 - 0x0000FFFF - - - VLHT - VLAN Hash Table - This field contains the 16-bit VLAN Hash Table. - 0 - 16 - read-write - - - - - TS_CTRL - Timestamp Control Register - 0x700 - 32 - 0x00000000 - 0x1F07FF3F - - - ATSEN3 - Auxiliary Snapshot 3 Enable -This field controls capturing the Auxiliary Snapshot Trigger 3. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[3] input is enabled. When this bit is reset, the events on this input are ignored. -This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration or the selected number in the Number of IEEE 1588 Auxiliary Snapshot Inputs option is less than four. - 28 - 1 - read-write - - - ATSEN2 - Auxiliary Snapshot 2 Enable -This field controls capturing the Auxiliary Snapshot Trigger 2. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[2] input is enabled. When this bit is reset, the events on this input are ignored. -This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration or the selected number in the Number of IEEE 1588 Auxiliary Snapshot Inputs option is less than three. - 27 - 1 - read-write - - - ATSEN1 - Auxiliary Snapshot 1 Enable -This field controls capturing the Auxiliary Snapshot Trigger 1. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[1] input is enabled. When this bit is reset, the events on this input are ignored. -This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration or the selected number in the Number of IEEE 1588 Auxiliary Snapshot Inputs option is less than two. - 26 - 1 - read-write - - - ATSEN0 - Auxiliary Snapshot 0 Enable -This field controls capturing the Auxiliary Snapshot Trigger 0. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[0] input is enabled. When this bit is reset, the events on this input are ignored. - 25 - 1 - read-write - - - ATSFC - Auxiliary Snapshot FIFO Clear -When set, it resets the pointers of the Auxiliary Snapshot FIFO. This bit is cleared when the pointers are reset and the FIFO is empty. When this bit is high, auxiliary snapshots get stored in the FIFO. -This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration. - 24 - 1 - read-write - - - TSENMACADDR - Enable MAC address for PTP Frame Filtering -When set, the DA MAC address (that matches any MAC Address register) is used to filter the PTP frames when PTP is directly sent over Ethernet. - 18 - 1 - read-write - - - SNAPTYPSEL - Select PTP packets for Taking Snapshots - These bits along with Bits 15 and 14 decide the set of PTP packet types for which snapshot needs to be taken. - 16 - 2 - read-write - - - TSMSTRENA - Enable Snapshot for Messages Relevant to Master -When set, the snapshot is taken only for the messages relevant to the master node. Otherwise, the snapshot is taken for the messages relevant to the slave node. - 15 - 1 - read-write - - - TSEVNTENA - Enable Timestamp Snapshot for Event Messages -When set, the timestamp snapshot is taken only for event messages (SYNC, Delay_Req, Pdelay_Req, or Pdelay_Resp). When reset, the snapshot is taken for all messages except Announce, Management, and Signaling. - 14 - 1 - read-write - - - TSIPV4ENA - Enable Processing of PTP Frames Sent over IPv4-UDP - When set, the MAC receiver processes the PTP packets encapsulated in UDP over IPv4 packets. When this bit is clear, the MAC ignores the PTP transported over UDP-IPv4 packets. This bit is set by default. - 13 - 1 - read-write - - - TSIPV6ENA - Enable Processing of PTP Frames Sent over IPv6-UDP -When set, the MAC receiver processes PTP packets encapsulated in UDP over IPv6 packets. When this bit is clear, the MAC ignores the PTP transported over UDP-IPv6 packets. - 12 - 1 - read-write - - - TSIPENA - Enable Processing of PTP over Ethernet Frames -When set, the MAC receiver processes the PTP packets encapsulated directly in the Ethernet frames. When this bit is clear, the MAC ignores the PTP over Ethernet packets - 11 - 1 - read-write - - - TSVER2ENA - Enable PTP packet Processing for Version 2 Format -When set, the PTP packets are processed using the 1588 version 2 format. Otherwise, the PTP packets are processed using the version 1 format. - 10 - 1 - read-write - - - TSCTRLSSR - Timestamp Digital or Binary Rollover Control -When set, the Timestamp Low register rolls over after 0x3B9A_C9FF value (that is, 1 nanosecond accuracy) and increments the timestamp (High) seconds. - When reset, the rollover value of sub-second register is 0x7FFF_FFFF. -The sub-second increment has to be programmed correctly depending on the PTP reference clock frequency and the value of this bit. - 9 - 1 - read-write - - - TSENALL - Enable Timestamp for All Frames -When set, the timestamp snapshot is enabled for all frames received by the MAC. - 8 - 1 - read-write - - - TSADDREG - Addend Reg Update -When set, the content of the Timestamp Addend register is updated in the PTP block for fine correction. This is cleared when the update is completed. -This register bit should be zero before setting it. - 5 - 1 - read-write - - - TSTRIG - Timestamp Interrupt Trigger Enable -When set, the timestamp interrupt is generated when the System Time becomes greater than the value written in the Target Time register. -This bit is reset after the generation of the Timestamp Trigger Interrupt. - 4 - 1 - read-write - - - TSUPDT - Timestamp Update -When set, the system time is updated (added or subtracted) with the value specified in Register 452 (System Time – Seconds Update Register) -and Register 453 (System Time – Nanoseconds Update Register). This bit should be read zero before updating it. -This bit is reset when the update is completed in hardware. The “Timestamp Higher Word” register (if enabled during core configuration) is not updated. - 3 - 1 - read-write - - - TSINIT - Timestamp Initialize -When set, the system time is initialized (overwritten) with the value specified in the Register 452 (System Time – Seconds Update Register) -and Register 453 (System Time – Nanoseconds Update Register). This bit should be read zero before updating it. -This bit is reset when the initialization is complete. -The “Timestamp Higher Word” register (if enabled during core configuration) can only be initialized. - 2 - 1 - read-write - - - TSCFUPDT - Timestamp Fine or Coarse Update -When set, this bit indicates that the system times update should be done using the fine update method. When reset, it indicates the system timestamp update should be done using the Coarse method. - 1 - 1 - read-write - - - TSENA - Timestamp Enable -When set, the timestamp is added for the transmit and receive frames. When disabled, timestamp is not added for the transmit and receive frames and the Timestamp Generator is also suspended. -You need to initialize the Timestamp (system time) after enabling this mode. On the receive side, the MAC processes the 1588 frames only if this bit is set. - 0 - 1 - read-write - - - - - SUB_SEC_INCR - Sub-Second Increment Register - 0x704 - 32 - 0x00000000 - 0x000000FF - - - SSINC - Sub-second Increment Value -The value programmed in this field is accumulated every clock cycle (of clk_ptp_i) with the contents of the sub-second register. -For example, when PTP clock is 50 MHz (period is 20 ns), you should program 20 (0x14) -when the System Time- Nanoseconds register has an accuracy of 1 ns [Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register)]. -When TSCTRLSSR is clear, the Nanoseconds register has a resolution of ~0.465ns. -In this case, you should program a value of 43 (0x2B) that is derived by 20ns/0.465. - 0 - 8 - read-write - - - - - SYST_SEC - System Time - Seconds Register - 0x708 - 32 - 0x00000000 - 0xFFFFFFFF - - - TSS - Timestamp Second - The value in this field indicates the current value in seconds of the System Time maintained by the MAC. - 0 - 32 - read-only - - - - - SYST_NSEC - System Time - Nanoseconds Register - 0x70c - 32 - 0x00000000 - 0x7FFFFFFF - - - TSSS - Timestamp Sub Seconds - The value in this field has the sub second representation of time, with an accuracy of 0.46 ns. -When Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register), each bit represents 1 ns and the maximum value is 0x3B9A_C9FF, after which it rolls-over to zero. - 0 - 31 - read-only - - - - - SYST_SEC_UPD - System Time - Seconds Update Register - 0x710 - 32 - 0x00000000 - 0xFFFFFFFF - - - TSS - Timestamp Second - The value in this field indicates the time in seconds to be initialized or added to the system time. - 0 - 32 - read-write - - - - - SYST_NSEC_UPD - System Time - Nanoseconds Update Register - 0x714 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDSUB - Add or Subtract Time - When this bit is set, the time value is subtracted with the contents of the update register. When this bit is reset, the time value is added with the contents of the update register. - 31 - 1 - read-write - - - TSSS - Timestamp Sub Seconds -The value in this field has the sub second representation of time, with an accuracy of 0.46 ns. -When Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register), each bit represents 1 ns and the programmed value should not exceed 0x3B9A_C9FF. - 0 - 31 - read-write - - - - - TS_ADDEND - Timestamp Addend Register - 0x718 - 32 - 0x00000000 - 0xFFFFFFFF - - - TSAR - Timestamp Addend Register -This field indicates the 32-bit time value to be added to the Accumulator register to achieve time synchronization. - 0 - 32 - read-write - - - - - TGTTM_SEC - Target Time Seconds Register - 0x71c - 32 - 0x00000000 - 0xFFFFFFFF - - - TSTR - Target Time Seconds Register - This register stores the time in seconds. -When the timestamp value matches or exceeds both Target Timestamp registers, -then based on Bits [6:5] of Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). - 0 - 32 - read-write - - - - - TGTTM_NSEC - Target Time Nanoseconds Register - 0x720 - 32 - 0x00000000 - 0xFFFFFFFF - - - TRGTBUSY - Target Time Register Busy - The MAC sets this bit when the PPSCMD field (Bit [3:0]) in Register 459 (PPS Control Register) is programmed to 010 or 011. -Programming the PPSCMD field to 010 or 011, instructs the MAC to synchronize the Target Time Registers to the PTP clock domain. -The MAC clears this bit after synchronizing the Target Time Registers to the PTP clock domain -The application must not update the Target Time Registers when this bit is read as 1. -Otherwise, the synchronization of the previous programmed time gets corrupted. This bit is reserved when the Enable Flexible Pulse-Per-Second Output feature is not selected. - 31 - 1 - read-write - - - TTSLO - Target Timestamp Low Register -This register stores the time in (signed) nanoseconds. -When the value of the timestamp matches the both Target Timestamp registers, -then based on the TRGTMODSEL0 field (Bits [6:5]) in Register 459 (PPS Control Register), -the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). -This value should not exceed 0x3B9A_C9FF when Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register). -The actual start or stop time of the PPS signal output may have an error margin up to one unit of sub-second increment value. - 0 - 31 - read-write - - - - - SYSTM_H_SEC - System Time - Higher Word Seconds Register - 0x724 - 32 - 0x00000000 - 0x0000FFFF - - - TSHWR - Timestamp Higher Word Register -This field contains the most significant 16-bits of the timestamp seconds value. This register is optional and can be selected using the Enable IEEE 1588 Higher Word Register option during core configuration. -The register is directly written to initialize the value. This register is incremented when there is an overflow from the 32-bits of the System Time - Seconds register. - 0 - 16 - read-write - - - - - TS_STATUS - Timestamp Status Register - 0x728 - 32 - 0x00000000 - 0x3F0F03FF - - - ATSNS - Number of Auxiliary Timestamp Snapshots -This field indicates the number of Snapshots available in the FIFO. A value equal to the selected depth of FIFO (4, 8, or 16) indicates that the Auxiliary Snapshot FIFO is full. -These bits are cleared (to 00000) when the Auxiliary snapshot FIFO clear bit is set. -This bit is valid only if the Add IEEE 1588 Auxiliary Snapshot option is selected during core configuration. - 25 - 5 - read-only - - - ATSSTM - Auxiliary Timestamp Snapshot Trigger Missed - This bit is set when the Auxiliary timestamp snapshot FIFO is full and external trigger was set. -This indicates that the latest snapshot is not stored in the FIFO. This bit is valid only if the Add IEEE 1588 Auxiliary Snapshot option is selected during core configuration. - 24 - 1 - read-only - - - ATSSTN - Auxiliary Timestamp Snapshot Trigger Identifier -These bits identify the Auxiliary trigger inputs for which the timestamp available in the Auxiliary Snapshot Register is applicable. -When more than one bit is set at the same time, it means that corresponding auxiliary triggers were sampled at the same clock. -These bits are applicable only if the number of Auxiliary snapshots is more than one. -One bit is assigned for each trigger as shown in the following list: -- Bit 16: Auxiliary trigger 0 -- Bit 17: Auxiliary trigger 1 -- Bit 18: Auxiliary trigger 2 -- Bit 19: Auxiliary trigger 3 - The software can read this register to find the triggers that are set when the timestamp is taken. - 16 - 4 - read-only - - - TSTRGTERR3 - Timestamp Target Time Error -This bit is set when the target time, being programmed in Register 496 and Register 497, is already elapsed. This bit is cleared when read by the application. - 9 - 1 - read-only - - - TSTARGT3 - Timestamp Target Time Reached for Target Time PPS3 -When set, this bit indicates that the value of system time is greater than or equal to the value specified in Register 496 (PPS3 Target Time High Register) and Register 497 (PPS3 Target Time Low Register). - 8 - 1 - read-only - - - TSTRGTERR2 - No description available - 7 - 1 - read-only - - - TSTARGT2 - No description available - 6 - 1 - read-only - - - TSTRGTERR1 - No description available - 5 - 1 - read-only - - - TSTARGT1 - No description available - 4 - 1 - read-only - - - TSTRGTERR - No description available - 3 - 1 - read-only - - - AUXTSTRIG - No description available - 2 - 1 - read-only - - - TSTARGT - No description available - 1 - 1 - read-only - - - TSSOVF - No description available - 0 - 1 - read-only - - - - - PPS_CTRL - PPS Control Register - 0x72c - 32 - 0x00000000 - 0x6767677F - - - TRGTMODSEL3 - Target Time Register Mode for PPS3 Output -This field indicates the Target Time registers (register 496 and 497) mode for PPS3 output signal. This field is similar to the TRGTMODSEL0 field. - 29 - 2 - read-write - - - PPSCMD3 - Flexible PPS3 Output Control -This field controls the flexible PPS3 output (ptp_pps_o[3]) signal. This field is similar to PPSCMD0[2:0] in functionality. - 24 - 3 - write-only - - - TRGTMODSEL2 - Target Time Register Mode for PPS2 Output -This field indicates the Target Time registers (register 488 and 489) mode for PPS2 output signal. This field is similar to the TRGTMODSEL0 field. - 21 - 2 - read-write - - - PPSCMD2 - Flexible PPS2 Output Control -This field controls the flexible PPS2 output (ptp_pps_o[2]) signal. This field is similar to PPSCMD0[2:0] in functionality. - 16 - 3 - write-only - - - TRGTMODSEL1 - Target Time Register Mode for PPS1 Output -This field indicates the Target Time registers (register 480 and 481) mode for PPS1 output signal. This field is similar to the TRGTMODSEL0 field. - 13 - 2 - read-write - - - PPSCMD1 - Flexible PPS1 Output Control -This field controls the flexible PPS1 output (ptp_pps_o[1]) signal. This field is similar to PPSCMD0[2:0] in functionality. - 8 - 3 - write-only - - - TRGTMODSEL0 - Target Time Register Mode for PPS0 Output - This field indicates the Target Time registers (register 455 and 456) mode for PPS0 output signal: -- 00: Indicates that the Target Time registers are programmed only for generating the interrupt event. -- 01: Reserved -- 10: Indicates that the Target Time registers are programmed for generating the interrupt event and starting or stopping the generation of the PPS0 output signal. -- 11: Indicates that the Target Time registers are programmed only for starting or stopping the generation of the PPS0 output signal. No interrupt is asserted. - 5 - 2 - read-write - - - PPSEN0 - Flexible PPS Output Mode Enable -When set low, Bits [3:0] function as PPSCTRL (backward compatible). When set high, Bits[3:0] function as PPSCMD. - 4 - 1 - read-write - - - PPSCTRLCMD0 - PPSCTRL0: PPS0 Output Frequency Control -This field controls the frequency of the PPS0 output (ptp_pps_o[0]) signal. -The default value of PPSCTRL is 0000, and the PPS output is 1 pulse (of width clk_ptp_i) every second. -For other values of PPSCTRL, the PPS output becomes a generated clock of following frequencies: -- 0001: The binary rollover is 2 Hz, and the digital rollover is 1 Hz. -- 0010: The binary rollover is 4 Hz, and the digital rollover is 2 Hz. -- 0011: The binary rollover is 8 Hz, and the digital rollover is 4 Hz. -- 0100: The binary rollover is 16 Hz, and the digital rollover is 8 Hz. - ... -- 1111: The binary rollover is 32.768 KHz, and the digital rollover is 16.384 KHz. -Note: In the binary rollover mode, the PPS output (ptp_pps_o) has a duty cycle of 50 percent with these frequencies. -In the digital rollover mode, the PPS output frequency is an average number. -The actual clock is of different frequency that gets synchronized every second. For example: -- When PPSCTRL = 0001, the PPS (1 Hz) has a low period of 537 ms and a high period of 463 ms -- When PPSCTRL = 0010, the PPS (2 Hz) is a sequence of: - - One clock of 50 percent duty cycle and 537 ms period - - Second clock of 463 ms period (268 ms low and 195 ms high) -- When PPSCTRL = 0011, the PPS (4 Hz) is a sequence of: - - Three clocks of 50 percent duty cycle and 268 ms period - - Fourth clock of 195 ms period (134 ms low and 61 ms high) -PPSCMD0: Flexible PPS0 Output Control -0000: No Command -0001: START Single Pulse -This command generates single pulse rising at the start point defined in -Target Time Registers and of a duration defined -in the PPS0 Width Register. -0010: START Pulse Train -This command generates the train of pulses rising at the start point -defined in the Target Time Registers and of a duration defined in the -PPS0 Width Register and repeated at interval defined in the PPS -Interval Register. By default, the PPS pulse train is free-running unless -stopped by ‘STOP Pulse train at time’ or ‘STOP Pulse Train -immediately’ commands. -0011: Cancel START -This command cancels the START Single Pulse and START Pulse Train -commands if the system time has not crossed the programmed start -time. -0100: STOP Pulse train at time -This command stops the train of pulses initiated by the START Pulse -Train command (PPSCMD = 0010) after the time programmed in the -Target Time registers elapses. -0101: STOP Pulse Train immediately -This command immediately stops the train of pulses initiated by the -START Pulse Train command (PPSCMD = 0010). -0110: Cancel STOP Pulse train -This command cancels the STOP pulse train at time command if the -programmed stop time has not elapsed. The PPS pulse train becomes -free-running on the successful execution of this command. -0111-1111: Reserved -Note: These bits get cleared automatically - 0 - 4 - read-write - - - - - AUX_TS_NSEC - Auxiliary Timestamp - Nanoseconds Register - 0x730 - 32 - 0x00000000 - 0x7FFFFFFF - - - AUXTSLO - Contains the lower 31 bits (nano-seconds field) of the auxiliary timestamp. - 0 - 31 - read-only - - - - - AUX_TS_SEC - Auxiliary Timestamp - Seconds Register - 0x734 - 32 - 0x00000000 - 0xFFFFFFFF - - - AUXTSHI - Contains the lower 32 bits of the Seconds field of the auxiliary timestamp. - 0 - 32 - read-only - - - - - PPS0_INTERVAL - PPS Interval Register - 0x760 - 32 - 0x00000000 - 0xFFFFFFFF - - - PPSINT - PPS0 Output Signal Interval -These bits store the interval between the rising edges of PPS0 signal output in terms of units of sub-second increment value. -You need to program one value less than the required interval. -For example, if the PTP reference clock is 50 MHz (period of 20ns), -and desired interval between rising edges of PPS0 signal output is 100ns - (that is, five units of sub-second increment value), then you should program value 4 (5 – 1) in this register. - 0 - 32 - read-write - - - - - PPS0_WIDTH - PPS Width Register - 0x764 - 32 - 0x00000000 - 0xFFFFFFFF - - - PPSWIDTH - PPS0 Output Signal Width -These bits store the width between the rising edge and corresponding falling edge of the PPS0 signal output in terms of units of sub-second increment value. -You need to program one value less than the required interval. -For example, if PTP reference clock is 50 MHz (period of 20ns), -and desired width between the rising and corresponding falling edges of PPS0 signal output is 80ns - (that is, four units of sub-second increment value), then you should program value 3 (4 – 1) in this register. - 0 - 32 - read-write - - - - - 3 - 0x20 - 1,2,3 - PPS[%s] - no description available - 0x780 - - TGTTM_SEC - PPS Target Time Seconds Register - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - TSTRH1 - PPS1 Target Time Seconds Register -This register stores the time in seconds. -When the timestamp value matches or exceeds both Target Timestamp registers, -then based on Bits [14:13], TRGTMODSEL1, of Register 459 (PPS Control Register), -the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). - 0 - 32 - read-write - - - - - TGTTM_NSEC - PPS Target Time Nanoseconds Register - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - TRGTBUSY1 - PPS1 Target Time Register Busy -The MAC sets this bit when the PPSCMD1 field (Bits [10:8]) in Register 459 (PPS Control Register) is programmed to 010 or 011. -Programming the PPSCMD1 field to 010 or 011 instructs the MAC to synchronize the Target Time Registers to the PTP clock domain. -The MAC clears this bit after synchronizing the Target Time Registers to the PTP clock domain -The application must not update the Targeers wht Time Registen this bit is read as 1. -Otherwise, the synchronization of the previous programmed time gets corrupted. - 31 - 1 - read-write - - - TTSL1 - Target Time Low for PPS1 Register -This register stores the time in (signed) nanoseconds. -When the value of the timestamp matches the both Target Timestamp registers, -then based on the TRGTMODSEL1 field (Bits [14:13]) in Register 459 (PPS Control Register), - the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). - This value should not exceed 0x3B9A_C9FF when Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register). -The actual start or stop time of the PPS signal output may have an error margin up to one unit of sub-second increment value. - 0 - 31 - read-write - - - - - INTERVAL - PPS Interval Register - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - PPSINT - PPS1 Output Signal Interval -These bits store the interval between the rising edges of PPS1 signal output in terms of units of sub-second increment value. -You need to program one value less than the required interval. For example, if the PTP reference clock is 50 MHz (period of 20ns), - and desired interval between rising edges of PPS1 signal output is 100ns (that is, five units of sub-second increment value), -then you should program value 4 (5 – 1) in this register. - 0 - 32 - read-write - - - - - WIDTH - PPS Width Register - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - PPSWIDTH - PPS1 Output Signal Width -These bits store the width between the rising edge and corresponding falling edge of the PPS1 signal output in terms of units of sub-second increment value. -You need to program one value less than the required interval. For example, - if PTP reference clock is 50 MHz (period of 20ns), -and desired width between the rising and corresponding falling edges of PPS1 signal output is 80ns (that is, four units of sub-second increment value), -then you should program value 3 (4 – 1) in this register. - 0 - 32 - read-write - - - - - - DMA_BUS_MODE - Bus Mode Register - 0x1000 - 32 - 0x00000000 - 0xBFFFFFFF - - - RIB - Rebuild INCRx Burst -When this bit is set high and the AHB master gets an EBT (Retry, Split, or Losing bus grant), - the AHB master interface rebuilds the pending beats of any burst transfer initiated with INCRx. -The AHB master interface rebuilds the beats with a combination of specified bursts with INCRx and SINGLE. -By default, the AHB master interface rebuilds pending beats of an EBT with an unspecified (INCR) burst. - 31 - 1 - read-write - - - PRWG - Channel Priority -Weights This field sets the priority weights for Channel 0 during the round-robin arbitration between the DMA channels for the system bus. -- 00: The priority weight is 1. -- 01: The priority weight is 2. -- 10: The priority weight is 3. -- 11: The priority weight is 4. This field is present in all DWC_gmac configurations except GMAC-AXI when you select the AV feature. Otherwise, this field is reserved and read-only (RO). - 28 - 2 - read-write - - - TXPR - Transmit Priority -When set, this bit indicates that the transmit DMA has higher priority than the receive DMA during arbitration for the system-side bus. In the GMAC-AXI configuration, this bit is reserved and read-only (RO). - 27 - 1 - read-write - - - MB - Mixed Burst -When this bit is set high and the FB bit is low, the AHB master interface starts all bursts of length more than 16 with INCR (undefined burst), -whereas it reverts to fixed burst transfers (INCRx and SINGLE) for burst length of 16 and less. - 26 - 1 - read-write - - - AAL - Address-Aligned Beats -When this bit is set high and the FB bit is equal to 1, -the AHB or AXI interface generates all bursts aligned to the start address LS bits. If the FB bit is equal to 0, - the first burst (accessing the start address of data buffer) is not aligned, but subsequent bursts are aligned to the address. - 25 - 1 - read-write - - - PBLX8 - PBLx8 Mode -When set high, this bit multiplies the programmed PBL value (Bits [22:17] and Bits[13:8]) eight times. -Therefore, the DMA transfers the data in 8, 16, 32, 64, 128, and 256 beats depending on the PBL value. - 24 - 1 - read-write - - - USP - Use Separate PBL -When set high, this bit configures the Rx DMA to use the value configured in Bits [22:17] as PBL. -The PBL value in Bits [13:8] is applicable only to the Tx DMA operations. -When reset to low, the PBL value in Bits [13:8] is applicable for both DMA engines. - 23 - 1 - read-write - - - RPBL - Rx DMA PBL -This field indicates the maximum number of beats to be transferred in one Rx DMA transaction. -This is the maximum value that is used in a single block Read or Write. -The Rx DMA always attempts to burst as specified in the RPBL bit each time it starts a Burst transfer on the host bus. - You can program RPBL with values of 1, 2, 4, 8, 16, and 32. Any other value results in undefined behavior. -This field is valid and applicable only when USP is set high. - 17 - 6 - read-write - - - FB - Fixed Burst - This bit controls whether the AHB or AXI master interface performs fixed burst transfers or not. -When set, the AHB interface uses only SINGLE, INCR4, INCR8, or INCR16 during start of the normal burst transfers. -When reset, the AHB or AXI interface uses SINGLE and INCR burst transfer operations. - 16 - 1 - read-write - - - PR - Priority Ratio - These bits control the priority ratio in the weighted round-robin arbitration between the Rx DMA and Tx DMA. - These bits are valid only when Bit 1 (DA) is reset. The priority ratio is Rx:Tx or Tx:Rx depending on whether Bit 27 (TXPR) is reset or set. -- 00: The Priority Ratio is 1:1. -- 01: The Priority Ratio is 2:1. -- 10: The Priority Ratio is 3:1. -- 11: The Priority Ratio is 4:1. - 14 - 2 - read-write - - - PBL - Programmable Burst Length -These bits indicate the maximum number of beats to be transferred in one DMA transaction. -This is the maximum value that is used in a single block Read or Write. -The DMA always attempts to burst as specified in PBL each time it starts a Burst transfer on the host bus. -PBL can be programmed with permissible values of 1, 2, 4, 8, 16, and 32. -Any other value results in undefined behavior. When USP is set high, this PBL value is applicable only for Tx DMA transactions. -If the number of beats to be transferred is more than 32, then perform the following steps: 1. Set the PBLx8 mode. 2. Set the PBL. - 8 - 6 - read-write - - - ATDS - Alternate Descriptor Size -When set, the size of the alternate descriptor (described in “Alternate or Enhanced Descriptors” on page 545) increases to 32 bytes (8 DWORDS). -This is required when the Advanced Timestamp feature or the IPC Full Checksum Offload Engine (Type 2) is enabled in the receiver. -The enhanced descriptor is not required if the Advanced Timestamp and IPC Full Checksum Offload Engine (Type 2) features are not enabled. - In such case, you can use the 16 bytes descriptor to save 4 bytes of memory. -This bit is present only when you select the Alternate Descriptor feature and any one of the following features during core configuration: -- Advanced Timestamp feature - IPC Full Checksum Offload Engine (Type 2) feature Otherwise, this bit is reserved and is read-only. -When reset, the descriptor size reverts back to 4 DWORDs (16 bytes). - 7 - 1 - read-write - - - DSL - Descriptor Skip Length -This bit specifies the number of Word, Dword, or Lword (depending on the 32-bit, 64-bit, or 128-bit bus) to skip between two unchained descriptors. -The address skipping starts from the end of current descriptor to the start of next descriptor. -When the DSL value is equal to zero, the descriptor table is taken as contiguous by the DMA in Ring mode. - 2 - 5 - read-write - - - DA - DMA Arbitration Scheme -This bit specifies the arbitration scheme between the transmit and receive paths of Channel 0. -- 0: Weighted round-robin with Rx:Tx or Tx:Rx The priority between the paths is according to the priority specified in Bits [15:14] (PR) and priority weights specified in Bit 27 (TXPR). -- 1: Fixed priority The transmit path has priority over receive path when Bit 27 (TXPR) is set. Otherwise, receive path has priority over the transmit path. - 1 - 1 - read-write - - - SWR - Software Reset - When this bit is set, the MAC DMA Controller resets the logic and all internal registers of the MAC. -It is cleared automatically after the reset operation is complete in all of the DWC_gmac clock domains. -Before reprogramming any register of the DWC_gmac, you should read a zero (0) value in this bit. -Note: - The Software reset function is driven only by this bit. -Bit 0 of Register 64 (Channel 1 Bus Mode Register) or Register 128 (Channel 2 Bus Mode Register) has no impact on the Software reset function. -- The reset operation is completed only when all resets in all active clock domains are de-asserted. -Therefore, it is essential that all PHY inputs clocks (applicable for the selected PHY interface) are present for the software reset completion. -The time to complete the software reset operation depends on the frequency of the slowest active clock. - 0 - 1 - read-write - - - - - DMA_TX_POLL_DEMAND - Transmit Poll Demand Register - 0x1004 - 32 - 0x00000000 - 0xFFFFFFFF - - - TPD - Transmit Poll Demand -When these bits are written with any value, -the DMA reads the current descriptor to which the Register 18 (Current Host Transmit Descriptor Register) is pointing. - If that descriptor is not available (owned by the Host), -the transmission returns to the Suspend state and Bit 2 (TU) of Register 5 (Status Register) is asserted. -If the descriptor is available, the transmission resumes. - 0 - 32 - read-write - - - - - DMA_RX_POLL_DEMAND - Receive Poll Demand Register - 0x1008 - 32 - 0x00000000 - 0xFFFFFFFF - - - RPD - Receive Poll Demand -When these bits are written with any value, -the DMA reads the current descriptor to which the Register 19 (Current Host Receive Descriptor Register) is pointing. - If that descriptor is not available (owned by the Host), -the reception returns to the Suspended state and Bit 7 (RU) of Register 5 (Status Register) is asserted. -If the descriptor is available, the Rx DMA returns to the active state. - 0 - 32 - read-write - - - - - DMA_RX_DESC_LIST_ADDR - Receive Descriptor List Address Register - 0x100c - 32 - 0x00000000 - 0xFFFFFFFF - - - RDESLA - Start of Receive List -This field contains the base address of the first descriptor in the Receive Descriptor list. -The LSB bits (1:0, 2:0, or 3:0) for 32-bit, 64-bit, or 128-bit bus width are ignored and internally taken as all-zero by the DMA. Therefore, these LSB bits are read-only (RO). - 0 - 32 - read-write - - - - - DMA_TX_DESC_LIST_ADDR - Transmit Descriptor List Address Register - 0x1010 - 32 - 0x00000000 - 0xFFFFFFFF - - - TDESLA - Start of Transmit List -This field contains the base address of the first descriptor in the Transmit Descriptor list. -The LSB bits (1:0, 2:0, 3:0) for 32-bit, 64-bit, or 128-bit bus width are ignored and are internally taken as all-zero by the DMA. Therefore, these LSB bits are read-only (RO). - 0 - 32 - read-write - - - - - DMA_STATUS - Status Register - 0x1014 - 32 - 0x00000000 - 0x7FFFE7FF - - - GLPII - GLPII: GMAC LPI Interrupt (for Channel 0) -This bit indicates an interrupt event in the LPI logic of the MAC. -To reset this bit to 1'b0, the software must read the corresponding registers in the DWC_gmac to get the exact cause of the interrupt and clear its source. -Note: GLPII status is given only in Channel 0 DMA register and is applicable only when the Energy Efficient Ethernet feature is enabled. Otherwise, this bit is reserved. -When this bit is high, the interrupt signal from the MAC (sbd_intr_o) is high. --or- GTMSI: GMAC TMS Interrupt (for Channel 1 and Channel 2) This bit indicates an interrupt event in the traffic manager and scheduler logic of DWC_gmac. -To reset this bit, the software must read the corresponding registers (Channel Status Register) to get the exact cause of the interrupt and clear its source. -Note: GTMSI status is given only in Channel 1 and Channel 2 DMA register when the AV feature is enabled and corresponding additional transmit channels are present. -Otherwise, this bit is reserved. When this bit is high, the interrupt signal from the MAC (sbd_intr_o) is high. - 30 - 1 - read-write - - - TTI - Timestamp Trigger Interrupt -This bit indicates an interrupt event in the Timestamp Generator block of the DWC_gmac. -The software must read the corresponding registers in the DWC_gmac to get the exact cause of the interrupt and clear its source to reset this bit to 1'b0. - When this bit is high, the interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high. -This bit is applicable only when the IEEE 1588 Timestamp feature is enabled. Otherwise, this bit is reserved. - 29 - 1 - read-write - - - GPI - GMAC PMT Interrupt -This bit indicates an interrupt event in the PMT module of the DWC_gmac. - The software must read the PMT Control and Status Register in the MAC to get the exact cause of interrupt and clear its source to reset this bit to 1’b0. -The interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high when this bit is high. -This bit is applicable only when the Power Management feature is enabled. -Otherwise, this bit is reserved. Note: The GPI and pmt_intr_o interrupts are generated in different clock domains. - 28 - 1 - read-write - - - GMI - GMAC MMC Interrupt - This bit reflects an interrupt event in the MMC module of the DWC_gmac. -The software must read the corresponding registers in the DWC_gmac -to get the exact cause of the interrupt and clear the source of interrupt to make this bit as 1’b0. -The interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high when this bit is high. -This bit is applicable only when the MAC Management Counters (MMC) are enabled. Otherwise, this bit is reserved. - 27 - 1 - read-write - - - GLI - GMAC Line Interface Interrupt -When set, this bit reflects any of the following interrupt events in the DWC_gmac interfaces (if present and enabled in your configuration): -- PCS (TBI, RTBI, or SGMII): Link change or auto-negotiation complete event -- SMII or RGMII: Link change event - General Purpose Input Status (GPIS): - Any LL or LH event on the gpi_i input ports To identify the exact cause of the interrupt, - the software must first read Bit 11 and Bits[2:0] of Register 14 (Interrupt Status Register) and then to clear the source of interrupt (which also clears the GLI interrupt), - read any of the following corresponding registers: -- PCS (TBI, RTBI, or SGMII): Register 49 (AN Status Register) -- SMII or RGMII: Register 54 (SGMII/RGMII/SMII Control and Status Register) -- General Purpose Input (GPI): Register 56 (General Purpose IO Register) The interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high when this bit is high. - 26 - 1 - read-write - - - EB - Error Bits -This field indicates the type of error that caused a Bus Error, for example, error response on the AHB or AXI interface. - This field is valid only when Bit 13 (FBI) is set. This field does not generate an interrupt. -- 0 0 0: Error during Rx DMA Write Data Transfer -- 0 1 1: Error during Tx DMA Read Data Transfer -- 1 0 0: Error during Rx DMA Descriptor Write Access -- 1 0 1: Error during Tx DMA Descriptor Write Access -- 1 1 0: Error during Rx DMA Descriptor Read Access -- 1 1 1: Error during Tx DMA Descriptor Read Access Note: 001 and 010 are reserved. - 23 - 3 - read-write - - - TS - Transmit Process State -This field indicates the Transmit DMA FSM state. This field does not generate an interrupt. -- 3’b000: Stopped; Reset or Stop Transmit Command issued -- 3’b001: Running; Fetching Transmit Transfer Descriptor -- 3’b010: Running; Waiting for status -- 3’b011: Running; Reading Data from host memory buffer and queuing it to transmit buffer (Tx FIFO) -- 3’b100: TIME_STAMP write state -- 3’b101: Reserved for future use -- 3’b110: Suspended; Transmit Descriptor Unavailable or Transmit Buffer Underflow -- 3’b111: Running; Closing Transmit Descriptor - 20 - 3 - read-write - - - RS - Receive Process State -This field indicates the Receive DMA FSM state. This field does not generate an interrupt. -- 3’b000: Stopped: Reset or Stop Receive Command issued -- 3’b001: Running: Fetching Receive Transfer Descriptor -- 3’b010: Reserved for future use -- 3’b011: Running: Waiting for receive packet -- 3’b100: Suspended: Receive Descriptor Unavailable -- 3’b101: Running: Closing Receive Descriptor -- 3’b110: TIME_STAMP write state -- 3’b111: Running: Transferring the receive packet data from receive buffer to host memory - 17 - 3 - read-write - - - NIS - Normal Interrupt Summary -Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in -Register 7 (Interrupt Enable Register): -- Register 5[0]: Transmit Interrupt -- Register 5[2]: Transmit Buffer Unavailable -- Register 5[6]: Receive Interrupt -- Register 5[14]: Early Receive Interrupt Only unmasked bits - (interrupts for which interrupt enable is set in Register 7) affect the Normal Interrupt Summary bit. - This is a sticky bit and must be cleared (by writing 1 to this bit) each time a corresponding bit, which causes NIS to be set, is cleared. - 16 - 1 - read-write - - - AIS - Abnormal Interrupt Summary -Abnormal Interrupt Summary bit value is the logical OR of the following -when the corresponding interrupt bits are enabled in Register 7 (Interrupt Enable Register): -- Register 5[1]: Transmit Process Stopped -- Register 5[3]: Transmit Jabber Timeout -- Register 5[4]: Receive FIFO Overflow -- Register 5[5]: Transmit Underflow -- Register 5[7]: Receive Buffer Unavailable -- Register 5[8]: Receive Process Stopped -- Register 5[9]: Receive Watchdog Timeout -- Register 5[10]: Early Transmit Interrupt -- Register 5[13]: Fatal Bus Error Only unmasked bits affect the Abnormal Interrupt Summary bit. -This is a sticky bit and must be cleared (by writing 1 to this bit) each time a corresponding bit, which causes AIS to be set, is cleared. - 15 - 1 - read-write - - - ERI - Early Receive Interrupt -This bit indicates that the DMA filled the first data buffer of the packet. This bit is cleared when the software writes 1 to this bit or Bit 6 (RI) of this register is set (whichever occurs earlier). - 14 - 1 - read-write - - - FBI - Fatal Bus Error Interrupt -This bit indicates that a bus error occurred, as described in Bits [25:23]. When this bit is set, the corresponding DMA engine disables all of its bus accesses. - 13 - 1 - read-write - - - ETI - Early Transmit Interrupt -This bit indicates that the frame to be transmitted is fully transferred to the MTL Transmit FIFO. - 10 - 1 - read-write - - - RWT - Receive Watchdog Timeout -When set, this bit indicates that the Receive Watchdog Timer expired while receiving the current frame and the current frame is truncated after the watchdog timeout. - 9 - 1 - read-write - - - RPS - Receive Process Stopped -This bit is asserted when the Receive Process enters the Stopped state. - 8 - 1 - read-write - - - RU - Receive Buffer Unavailable -This bit indicates that the host owns the Next Descriptor in the Receive List and the DMA cannot acquire it. -The Receive Process is suspended. To resume processing Receive descriptors, - the host should change the ownership of the descriptor and issue a Receive Poll Demand command. - If no Receive Poll Demand is issued, the Receive Process resumes when the next recognized incoming frame is received. -This bit is set only when the previous Receive Descriptor is owned by the DMA. - 7 - 1 - read-write - - - RI - Receive Interrupt -This bit indicates that the frame reception is complete. -When reception is complete, the Bit 31 of RDES1 (Disable Interrupt on Completion) is reset in the last Descriptor, -and the specific frame status information is updated in the descriptor. -The reception remains in the Running state. - 6 - 1 - read-write - - - UNF - Transmit Underflow -This bit indicates that the Transmit Buffer had an Underflow during frame transmission. Transmission is suspended and an Underflow Error TDES0[1] is set. - 5 - 1 - read-write - - - OVF - Receive Overflow -This bit indicates that the Receive Buffer had an Overflow during frame reception. If the partial frame is transferred to the application, the overflow status is set in RDES0[11]. - 4 - 1 - read-write - - - TJT - Transmit Jabber Timeout -This bit indicates that the Transmit Jabber Timer expired, which happens when the frame size exceeds 2,048 (10,240 bytes when the Jumbo frame is enabled). -When the Jabber Timeout occurs, the transmission process is aborted and placed in the Stopped state. This causes the Transmit Jabber Timeout TDES0[14] flag to assert. - 3 - 1 - read-write - - - TU - Transmit Buffer Unavailable -This bit indicates that the host owns the Next Descriptor in the Transmit List and the DMA cannot acquire it. Transmission is suspended. Bits[22:20] explain the Transmit Process state transitions. -To resume processing Transmit descriptors, the host should change the ownership of the descriptor by setting TDES0[31] and then issue a Transmit Poll Demand command. - 2 - 1 - read-write - - - TPS - Transmit Process Stopped -This bit is set when the transmission is stopped. - 1 - 1 - read-write - - - TI - Transmit Interrupt -This bit indicates that the frame transmission is complete. When transmission is complete, Bit 31 (OWN) of TDES0 is reset, and the specific frame status information is updated in the descriptor. - 0 - 1 - read-write - - - - - DMA_OP_MODE - Operation Mode Register - 0x1018 - 32 - 0x00000000 - 0x13F1FFFE - - - DT - Disable Dropping of TCP/IP Checksum Error Frames -When this bit is set, the MAC does not drop the frames which only have errors detected by the Receive Checksum Offload engine. - Such frames do not have any errors (including FCS error) in the Ethernet frame received by the MAC but have errors only in the encapsulated payload. -When this bit is reset, all error frames are dropped if the FEF bit is reset. If the IPC Full Checksum Offload Engine (Type 2) is disabled, this bit is reserved (RO with value 1'b0). - 28 - 1 - read-write - - - RSF - Receive Store and Forward -When this bit is set, the MTL reads a frame from the Rx FIFO only after the complete frame has been written to it, ignoring the RTC bits. - When this bit is reset, the Rx FIFO operates in the cut-through mode, subject to the threshold specified by the RTC bits. - 25 - 1 - read-write - - - DFF - Disable Flushing of Received Frames -When this bit is set, the Rx DMA does not flush any frames because of the unavailability of receive descriptors or buffers as it does normally when this bit is reset. (See “Receive Process Suspended” on page 83.) - 24 - 1 - read-write - - - RFA_2 - MSB of Threshold for Activating Flow Control -If the DWC_gmac is configured for an Rx FIFO size of 8 KB or more, -this bit (when set) provides additional threshold levels for activating the flow control in both half-duplex and full-duplex modes. -This bit (as Most Significant Bit), along with the RFA (Bits [10:9]), gives the following thresholds for activating flow control: -- 100: Full minus 5 KB, that is, FULL — 5 KB -- 101: Full minus 6 KB, that is, FULL — 6 KB -- 110: Full minus 7 KB, that is, FULL — 7 KB -- 111: Reserved This bit is reserved (and RO) if the Rx FIFO is 4 KB or less deep. - 23 - 1 - read-write - - - RFD_2 - MSB of Threshold for Deactivating Flow Control -If the DWC_gmac is configured for Rx FIFO size of 8 KB or more, - this bit (when set) provides additional threshold levels for deactivating the flow control in both half-duplex and full-duplex modes. - This bit (as Most Significant Bit) along with the RFD (Bits [12:11]) gives the following thresholds for deactivating flow control: -- 100: Full minus 5 KB, that is, FULL — 5 KB -- 101: Full minus 6 KB, that is, FULL — 6 KB -- 110: Full minus 7 KB, that is, FULL — 7 KB -- 111: Reserved This bit is reserved (and RO) if the Rx FIFO is 4 KB or less deep. - 22 - 1 - read-write - - - TSF - Transmit Store and Forward -When this bit is set, transmission starts when a full frame resides in the MTL Transmit FIFO. -When this bit is set, the TTC values specified in Bits [16:14] are ignored. -This bit should be changed only when the transmission is stopped. - 21 - 1 - read-write - - - FTF - Flush Transmit FIFO -When this bit is set, the transmit FIFO controller logic is reset to its default values and thus all data in the Tx FIFO is lost or flushed. -This bit is cleared internally when the flushing operation is complete. -The Operation Mode register should not be written to until this bit is cleared. -The data which is already accepted by the MAC transmitter is not flushed. -It is scheduled for transmission and results in underflow and runt frame transmission. - 20 - 1 - read-write - - - TTC - Transmit Threshold Control -These bits control the threshold level of the MTL Transmit FIFO. - Transmission starts when the frame size within the MTL Transmit FIFO is larger than the threshold. -In addition, full frames with a length less than the threshold are also transmitted. - These bits are used only when Bit 21 (TSF) is reset. -- 000: 64 -- 001: 128 -- 010: 192 -- 011: 256 -- 100: 40 -- 101: 32 -- 110: 24 -- 111: 16 - 14 - 3 - read-write - - - ST - Start or Stop Transmission Command -When this bit is set, transmission is placed in the Running state, and the DMA checks the Transmit List at the current position for a frame to be transmitted. -Descriptor acquisition is attempted either from the current position in the list, -which is the Transmit List Base Address set by Register 4 (Transmit Descriptor List Address Register), -or from the position retained when transmission was stopped previously. - If the DMA does not own the current descriptor, -transmission enters the Suspended state and Bit 2 (Transmit Buffer Unavailable) of Register 5 (Status Register) is set. -The Start Transmission command is effective only when transmission is stopped. -If the command is issued before setting Register 4 (Transmit Descriptor List Address Register), - then the DMA behavior is unpredictable. When this bit is reset, -the transmission process is placed in the Stopped state after completing the transmission of the current frame. -The Next Descriptor position in the Transmit List is saved, -and it becomes the current position when transmission is restarted. -To change the list address, you need to program Register 4 (Transmit Descriptor List Address Register) with a new value when this bit is reset. -The new value is considered when this bit is set again. -The stop transmission command is effective only when the transmission of the current frame is complete or the transmission is in the Suspended state. - 13 - 1 - read-write - - - RFD - Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (Fill-level of Rx FIFO) at which the flow control is de-asserted after activation. -- 00: Full minus 1 KB, that is, FULL — 1 KB -- 01: Full minus 2 KB, that is, FULL — 2 KB -- 10: Full minus 3 KB, that is, FULL — 3 KB -- 11: Full minus 4 KB, that is, FULL — 4 KB -The de-assertion is effective only after flow control is asserted. - If the Rx FIFO is 8 KB or more, an additional Bit (RFD_2) is used for more threshold levels as described in Bit 22. -These bits are reserved and read-only when the Rx FIFO depth is less than 4 KB. - 11 - 2 - read-write - - - RFA - Threshold for Activating Flow Control (in half-duplex and full-duplex modes) -These bits control the threshold (Fill level of Rx FIFO) at which the flow control is activated. -- 00: Full minus 1 KB, that is, FULL—1KB. -- 01: Full minus 2 KB, that is, FULL—2KB. -- 10: Full minus 3 KB, that is, FULL—3KB. -- 11: Full minus 4 KB, that is, FULL—4KB. -These values are applicable only to Rx FIFOs of 4 KB or more and when Bit 8 (EFC) is set high. If the Rx FIFO is 8 KB or more, -an additional Bit (RFA_2) is used for more threshold levels as described in Bit 23. -These bits are reserved and read-only when the depth of Rx FIFO is less than 4 KB. -Note: When FIFO size is exactly 4 KB, although the DWC_gmac allows you to program the value of these bits to 11, -the software should not program these bits to 2'b11. The value 2'b11 means flow control on FIFO empty condition - 9 - 2 - read-write - - - EFC - Enable HW Flow Control -When this bit is set, the flow control signal operation based on the fill-level of Rx FIFO is enabled. -When reset, the flow control operation is disabled. - This bit is not used (reserved and always reset) when the Rx FIFO is less than 4 KB. - 8 - 1 - read-write - - - FEF - Forward Error Frames -When this bit is reset, the Rx FIFO drops frames with error status (CRC error, collision error, GMII_ER, giant frame, watchdog timeout, or overflow). -However, if the start byte (write) pointer of a frame is already transferred to the read controller side (in Threshold mode), -then the frame is not dropped. In the GMAC-MTL configuration in which the Frame Length FIFO is also enabled during core configuration, -the Rx FIFO drops the error frames if that frame's start byte is not transferred (output) on the ARI bus. -When the FEF bit is set, all frames except runt error frames are forwarded to the DMA. -If the Bit 25 (RSF) is set and the Rx FIFO overflows when a partial frame is written, -then the frame is dropped irrespective of the FEF bit setting. -However, if the Bit 25 (RSF) is reset and the Rx FIFO overflows when a partial frame is written, then a partial frame may be forwarded to the DMA. -Note: When FEF bit is reset, the giant frames are dropped if the giant frame status is given in Rx Status (in Table 8-6 or Table 8-23) in the following configurations: -- The IP checksum engine (Type 1) and full checksum offload engine (Type 2) are not selected. - - The advanced timestamp feature is not selected but the extended status is selected. -The extended status is available with the following features: -- L3-L4 filter in GMAC-CORE or GMAC-MTL configurations -- Full checksum offload engine (Type 2) with enhanced descriptor format in the GMAC-DMA, GMAC-AHB, or GMAC-AXI configurations. - 7 - 1 - read-write - - - FUF - Forward Undersized Good Frames -When set, the Rx FIFO forwards Undersized frames (that is, frames with no Error and length less than 64 bytes) including pad-bytes and CRC -When reset, the Rx FIFO drops all frames of less than 64 bytes, unless a frame is already transferred because of the lower value of Receive Threshold, for example, RTC = 01. - 6 - 1 - read-write - - - DGF - Drop Giant Frames -When set, the MAC drops the received giant frames in the Rx FIFO, -that is, frames that are larger than the computed giant frame limit. -When reset, the MAC does not drop the giant frames in the Rx FIFO. -Note: This bit is available in the following configurations in which the giant frame status is not provided in Rx status and giant frames are not dropped by default: -- Configurations in which IP Checksum Offload (Type 1) is selected in Rx -- Configurations in which the IPC Full Checksum Offload Engine (Type 2) is selected in Rx with normal descriptor format -- Configurations in which the Advanced Timestamp feature is selected In all other configurations, this bit is not used (reserved and always reset). - 5 - 1 - read-write - - - RTC - Receive Threshold Control -These two bits control the threshold level of the MTL Receive FIFO. -Transfer (request) to DMA starts when the frame size within the MTL Receive FIFO is larger than the threshold. -In addition, full frames with length less than the threshold are automatically transferred. -The value of 11 is not applicable if the configured Receive FIFO size is 128 bytes. -These bits are valid only when the RSF bit is zero, and are ignored when the RSF bit is set to 1. -- 00: 64 -- 01: 32 -- 10: 96 -- 11: 128 - 3 - 2 - read-write - - - OSF - Operate on Second Frame -When this bit is set, it instructs the DMA to process the second frame of the Transmit data even before the status for the first frame is obtained. - 2 - 1 - read-write - - - SR - Start or Stop Receive -When this bit is set, the Receive process is placed in the Running state. -The DMA attempts to acquire the descriptor from the Receive list and processes the incoming frames. -The descriptor acquisition is attempted from the current position in the list, -which is the address set by the Register 3 (Receive Descriptor List Address Register) or the position retained when the Receive process was previously stopped. -If the DMA does not own the descriptor, reception is suspended and Bit 7 (Receive Buffer Unavailable) of Register 5 (Status Register) is set. -The Start Receive command is effective only when the reception has stopped. - If the command is issued before setting Register 3 (Receive Descriptor List Address Register), the DMA behavior is unpredictable. -When this bit is cleared, the Rx DMA operation is stopped after the transfer of the current frame. -The next descriptor position in the Receive list is saved and becomes the current position after the Receive process is restarted. -The Stop Receive command is effective only when the Receive process is in either the Running (waiting for receive packet) or in the Suspended state. - 1 - 1 - read-write - - - - - DMA_INTR_EN - Interrupt Enable Register - 0x101c - 32 - 0x00000000 - 0x0001E7FF - - - NIE - Normal Interrupt Summary Enable -When this bit is set, normal interrupt summary is enabled. -When this bit is reset, normal interrupt summary is disabled. -This bit enables the following interrupts in Register 5 (Status Register): - - Register 5[0]: Transmit Interrupt -- Register 5[2]: Transmit Buffer Unavailable -- Register 5[6]: Receive Interrupt - - Register 5[14]: Early Receive Interrupt - 16 - 1 - read-write - - - AIE - Abnormal Interrupt Summary Enable -When this bit is set, abnormal interrupt summary is enabled. -When this bit is reset, the abnormal interrupt summary is disabled. -This bit enables the following interrupts in Register 5 (Status Register): -- Register 5[1]: Transmit Process Stopped -- Register 5[3]: Transmit Jabber Timeout -- Register 5[4]: Receive Overflow -- Register 5[5]: Transmit Underflow -- Register 5[7]: Receive Buffer Unavailable -- Register 5[8]: Receive Process Stopped -- Register 5[9]: Receive Watchdog Timeout -- Register 5[10]: Early Transmit Interrupt - - Register 5[13]: Fatal Bus Error - 15 - 1 - read-write - - - ERE - Early Receive Interrupt Enable -When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Early Receive Interrupt is enabled. When this bit is reset, the Early Receive Interrupt is disabled. - 14 - 1 - read-write - - - FBE - Fatal Bus Error Enable -When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Fatal Bus Error Interrupt is enabled. When this bit is reset, the Fatal Bus Error Enable Interrupt is disabled. - 13 - 1 - read-write - - - ETE - Early Transmit Interrupt Enable -When this bit is set with an Abnormal Interrupt Summary Enable (Bit 15), the Early Transmit Interrupt is enabled. When this bit is reset, the Early Transmit Interrupt is disabled. - 10 - 1 - read-write - - - RWE - Receive Watchdog Timeout Enable -When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Watchdog Timeout Interrupt is enabled. When this bit is reset, the Receive Watchdog Timeout Interrupt is disabled. - 9 - 1 - read-write - - - RSE - Receive Stopped Enable -When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Stopped Interrupt is enabled. When this bit is reset, the Receive Stopped Interrupt is disabled. - 8 - 1 - read-write - - - RUE - Receive Buffer Unavailable Enable -When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Buffer Unavailable Interrupt is enabled. When this bit is reset, the Receive Buffer Unavailable Interrupt is disabled. - 7 - 1 - read-write - - - RIE - Receive Interrupt Enable -When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Receive Interrupt is enabled. When this bit is reset, the Receive Interrupt is disabled. - 6 - 1 - read-write - - - UNE - Underflow Interrupt Enable -When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmit Underflow Interrupt is enabled. When this bit is reset, the Underflow Interrupt is disabled. - 5 - 1 - read-write - - - OVE - Overflow Interrupt Enable -When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Overflow Interrupt is enabled. When this bit is reset, the Overflow Interrupt is disabled. - 4 - 1 - read-write - - - TJE - Transmit Jabber Timeout Enable -When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmit Jabber Timeout Interrupt is enabled. When this bit is reset, the Transmit Jabber Timeout Interrupt is disabled. - 3 - 1 - read-write - - - TUE - Transmit Buffer Unavailable Enable -When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Transmit Buffer Unavailable Interrupt is enabled. When this bit is reset, the Transmit Buffer Unavailable Interrupt is disabled. - 2 - 1 - read-write - - - TSE - Transmit Stopped Enable -When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmission Stopped Interrupt is enabled. When this bit is reset, the Transmission Stopped Interrupt is disabled. - 1 - 1 - read-write - - - TIE - Transmit Interrupt Enable -When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Transmit Interrupt is enabled. When this bit is reset, the Transmit Interrupt is disabled. - 0 - 1 - read-write - - - - - DMA_MISS_OVF_CNT - Missed Frame And Buffer Overflow Counter Register - 0x1020 - 32 - 0x00000000 - 0x1FFFFFFF - - - ONFCNTOVF - Overflow Bit for FIFO Overflow Counter -This bit is set every time the Overflow Frame Counter (Bits[27:17]) overflows, -that is, the Rx FIFO overflows with the overflow frame counter at maximum value. -In such a scenario, the overflow frame counter is reset to all-zeros and this bit indicates that the rollover happened. - 28 - 1 - read-write - - - OVFFRMCNT - Overflow Frame Counter -This field indicates the number of frames missed by the application. This counter is incremented each time the MTL FIFO overflows. The counter is cleared when this register is read with mci_be_i[2] at 1’b1. - 17 - 11 - read-write - - - MISCNTOVF - Overflow Bit for Missed Frame Counter -This bit is set every time Missed Frame Counter (Bits[15:0]) overflows, -that is, the DMA discards an incoming frame because of the Host Receive Buffer being unavailable with the missed frame counter at maximum value. In such a scenario, - the Missed frame counter is reset to all-zeros and this bit indicates that the rollover happened. - 16 - 1 - read-write - - - MISFRMCNT - Missed Frame Counter -This field indicates the number of frames missed by the controller because of the Host Receive Buffer being unavailable. -This counter is incremented each time the DMA discards an incoming frame. The counter is cleared when this register is read with mci_be_i[0] at 1’b1. - 0 - 16 - read-write - - - - - DMA_RX_INTR_WDOG - Receive Interrupt Watchdog Timer Register - 0x1024 - 32 - 0x00000000 - 0x000000FF - - - RIWT - RI Watchdog Timer Count -This bit indicates the number of system clock cycles multiplied by 256 for which the watchdog timer is set. -The watchdog timer gets triggered with the programmed value after the Rx DMA completes the transfer -of a frame for which the RI status bit is not set because of the setting in the corresponding descriptor RDES1[31]. -When the watchdog timer runs out, the RI bit is set and the timer is stopped. -The watchdog timer is reset when the RI bit is set high because of automatic setting of RI as per RDES1[31] of any received frame. - 0 - 8 - read-write - - - - - DMA_AXI_MODE - AXI Bus Mode Register - 0x1028 - 32 - 0x00000000 - 0xC0FF30FF - - - EN_LPI - Enable Low Power Interface (LPI) -When set to 1, this bit enables the LPI mode supported by the GMAC-AXI configuration and accepts the LPI request from the AXI System Clock controller. -When set to 0, this bit disables the LPI mode and always denies the LPI request from the AXI System Clock controller. - 31 - 1 - read-write - - - LPI_XIT_FRM - Unlock on Magic Packet or Remote Wake-Up Frame -When set to 1, this bit enables the GMAC-AXI to come out of the LPI mode only when the magic packet or remote wake-up frame is received. -When set to 0, this bit enables the GMAC-AXI to come out of LPI mode when any frame is received. - 30 - 1 - read-write - - - WR_OSR_LMT - AXI Maximum Write Outstanding Request Limit -This value limits the maximum outstanding request on the AXI write interface. -Maximum outstanding requests = WR_OSR_LMT+1 Note: - Bit 22 is reserved if AXI_GM_MAX_WR_REQUESTS = 4. - Bit 23 bit is reserved if AXI_GM_MAX_WR_REQUESTS != 16. - 20 - 4 - read-write - - - RD_OSR_LMT - AXI Maximum Read Outstanding Request Limit -This value limits the maximum outstanding request on the AXI read interface. -Maximum outstanding requests = RD_OSR_LMT+1 Note: - Bit 18 is reserved if AXI_GM_MAX_RD_REQUESTS = 4. - Bit 19 is reserved if AXI_GM_MAX_RD_REQUESTS != 16. - 16 - 4 - read-write - - - ONEKBBE - 1 KB Boundary Crossing Enable for the GMAC-AXI Master -When set, the GMAC-AXI master performs burst transfers that do not cross 1 KB boundary. -When reset, the GMAC-AXI master performs burst transfers that do not cross 4 KB boundary. - 13 - 1 - read-write - - - AXI_AAL - Address-Aligned Beats -This bit is read-only bit and reflects the Bit 25 (AAL) of Register 0 (Bus Mode Register). -When this bit is set to 1, the GMAC-AXI performs address-aligned burst transfers on both read and write channels. - 12 - 1 - read-write - - - BLEN256 - AXI Burst Length 256 -When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 256 on the AXI master interface. -This bit is present only when the configuration parameter AXI_BL is set to 256. Otherwise, this bit is reserved and is read-only (RO). - 7 - 1 - read-write - - - BLEN128 - AXI Burst Length 128 -When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 128 on the AXI master interface. -This bit is present only when the configuration parameter AXI_BL is set to 128 or more. Otherwise, this bit is reserved and is read-only (RO). - 6 - 1 - read-write - - - BLEN64 - AXI Burst Length 64 -When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 64 on the AXI master interface. -This bit is present only when the configuration parameter AXI_BL is set to 64 or more. Otherwise, this bit is reserved and is read-only (RO). - 5 - 1 - read-write - - - BLEN32 - AXI Burst Length 32 -When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 32 on the AXI master interface. -This bit is present only when the configuration parameter AXI_BL is set to 32 or more. Otherwise, this bit is reserved and is read-only (RO). - 4 - 1 - read-write - - - BLEN16 - AXI Burst Length 16 -When this bit is set to 1 or UNDEF is set to 1, the GMAC-AXI is allowed to select a burst length of 16 on the AXI master interface. - 3 - 1 - read-write - - - BLEN8 - AXI Burst Length 8 -When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 8 on the AXI master interface. -Setting this bit has no effect when UNDEF is set to 1. - 2 - 1 - read-write - - - BLEN4 - AXI Burst Length 4 -When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 4 on the AXI master interface. -Setting this bit has no effect when UNDEF is set to 1. - 1 - 1 - read-write - - - UNDEF - AXI Undefined Burst Length -This bit is read-only bit and indicates the complement (invert) value of Bit 16 (FB) in Register 0 (Bus Mode Register). -- When this bit is set to 1, the GMAC-AXI is allowed to perform any burst length equal to or below the maximum allowed burst length programmed in Bits[7:3]. -- When this bit is set to 0, the GMAC-AXI is allowed to perform only fixed burst lengths as indicated by BLEN256, BLEN128, BLEN64, BLEN32, BLEN16, BLEN8, or BLEN4, or a burst length of 1. -If UNDEF is set and none of the BLEN bits is set, then GMAC-AXI is allowed to perform a burst length of 16. - 0 - 1 - read-write - - - - - DMA_BUS_STATUS - AHB or AXI Status Register - 0x102c - 32 - 0x00000000 - 0x00000003 - - - AXIRDSTS - AXI Master Read Channel Status -When high, it indicates that AXI master's read channel is active and transferring data. - 1 - 1 - read-write - - - AXWHSTS - AXI Master Write Channel or AHB Master Status -When high, it indicates that AXI master's write channel is active and transferring data in the GMAC-AXI configuration. In the GMAC-AHB configuration, - it indicates that the AHB master interface FSMs are in the non-idle state. - 0 - 1 - read-write - - - - - DMA_CURR_HOST_TX_DESC - Current Host Transmit Descriptor Register - 0x1048 - 32 - 0x00000000 - 0xFFFFFFFF - - - CURTDESAPTR - Host Transmit Descriptor Address Pointer -Cleared on Reset. Pointer updated by the DMA during operation. - 0 - 32 - read-write - - - - - DMA_CURR_HOST_RX_DESC - Current Host Receive Descriptor Register - 0x104c - 32 - 0x00000000 - 0xFFFFFFFF - - - CURRDESAPTR - Host Receive Descriptor Address Pointer -Cleared on Reset. Pointer updated by the DMA during operation. - 0 - 32 - read-write - - - - - DMA_CURR_HOST_TX_BUF - Current Host Transmit Buffer Address Register - 0x1050 - 32 - 0x00000000 - 0xFFFFFFFF - - - CURTBUFAPTR - Host Transmit Buffer Address Pointer -Cleared on Reset. Pointer updated by the DMA during operation. - 0 - 32 - read-write - - - - - DMA_CURR_HOST_RX_BUF - Current Host Receive Buffer Address Register - 0x1054 - 32 - 0x00000000 - 0xFFFFFFFF - - - CURRBUFAPTR - Host Receive Buffer Address Pointer -Cleared on Reset. Pointer updated by the DMA during operation. - 0 - 32 - read-write - - - - - - - ENET1 - ENET1 - ENET - 0xf2004000 - - - NTMR0 - NTMR0 - GPTMR - 0xf2010000 - - 0x0 - 0x20c - registers - - - - 4 - 0x40 - ch0,ch1,ch2,ch3 - CHANNEL[%s] - no description available - 0x0 - - CR - Control Register - 0x0 - 32 - 0x00000000 - 0x80007FFF - - - CNTUPT - 1- update counter to new value as CNTUPTVAL -This bit will be auto cleared after 1 cycle - 31 - 1 - write-only - - - CNTRST - 1- reset counter - 14 - 1 - read-write - - - SYNCFLW - 1- enable this channel to reset counter to reload(RLD) together with its previous channel. -This bit is not valid for channel 0. - 13 - 1 - read-write - - - SYNCIFEN - 1- SYNCI is valid on its falling edge - 12 - 1 - read-write - - - SYNCIREN - 1- SYNCI is valid on its rising edge - 11 - 1 - read-write - - - CEN - 1- counter enable - 10 - 1 - read-write - - - CMPINIT - Output compare initial poliarity -1- The channel output initial level is high -0- The channel output initial level is low -User should set this bit before set CMPEN to 1. - 9 - 1 - read-write - - - CMPEN - 1- Enable the channel output compare function. The output signal can be generated per comparator (CMPx) settings. - 8 - 1 - read-write - - - DMASEL - select one of DMA request: -00- CMP0 flag -01- CMP1 flag -10- Input signal toggle captured -11- RLD flag, counter reload; - 6 - 2 - read-write - - - DMAEN - 1- enable dma - 5 - 1 - read-write - - - SWSYNCIEN - 1- enable software sync. When this bit is set, counter will reset to RLD when swsynct bit is set - 4 - 1 - read-write - - - DBGPAUSE - 1- counter will pause if chip is in debug mode - 3 - 1 - read-write - - - CAPMODE - This bitfield define the input capture mode -100: width measure mode, timer will calculate the input signal period and duty cycle -011: capture at both rising edge and falling edge -010: capture at falling edge -001: capture at rising edge -000: No capture - 0 - 3 - read-write - - - - - 2 - 0x4 - CMP0,CMP1 - CMP[%s] - no description available - 0x4 - 32 - 0xFFFFFFF0 - 0xFFFFFFFF - - - CMP - compare value 0 - 0 - 32 - read-write - - - - - RLD - Reload register - 0xc - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - RLD - reload value - 0 - 32 - read-write - - - - - CNTUPTVAL - Counter update value register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - CNTUPTVAL - counter will be set to this value when software write cntupt bit in CR - 0 - 32 - read-write - - - - - CAPPOS - Capture rising edge register - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPPOS - This register contains the counter value captured at input signal rising edge - 0 - 32 - read-only - - - - - CAPNEG - Capture falling edge register - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPNEG - This register contains the counter value captured at input signal falling edge - 0 - 32 - read-only - - - - - CAPPRD - PWM period measure register - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPPRD - This register contains the input signal period when channel is configured to input capture measure mode. - 0 - 32 - read-only - - - - - CAPDTY - PWM duty cycle measure register - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - MEAS_HIGH - This register contains the input signal duty cycle when channel is configured to input capture measure mode. - 0 - 32 - read-only - - - - - CNT - Counter - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - COUNTER - 32 bit counter value - 0 - 32 - read-only - - - - - - SR - Status register - 0x200 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH3CMP1F - channel 3 compare value 1 match flag - 15 - 1 - write-only - - - CH3CMP0F - channel 3 compare value 1 match flag - 14 - 1 - write-only - - - CH3CAPF - channel 3 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. - 13 - 1 - write-only - - - CH3RLDF - channel 3 counter reload flag - 12 - 1 - write-only - - - CH2CMP1F - channel 2 compare value 1 match flag - 11 - 1 - write-only - - - CH2CMP0F - channel 2 compare value 1 match flag - 10 - 1 - write-only - - - CH2CAPF - channel 2 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. - 9 - 1 - write-only - - - CH2RLDF - channel 2 counter reload flag - 8 - 1 - write-only - - - CH1CMP1F - channel 1 compare value 1 match flag - 7 - 1 - write-only - - - CH1CMP0F - channel 1 compare value 1 match flag - 6 - 1 - write-only - - - CH1CAPF - channel 1 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. - 5 - 1 - write-only - - - CH1RLDF - channel 1 counter reload flag - 4 - 1 - write-only - - - CH0CMP1F - channel 1 compare value 1 match flag - 3 - 1 - write-only - - - CH0CMP0F - channel 1 compare value 1 match flag - 2 - 1 - write-only - - - CH0CAPF - channel 1 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. - 1 - 1 - write-only - - - CH0RLDF - channel 1 counter reload flag - 0 - 1 - write-only - - - - - IRQEN - Interrupt request enable register - 0x204 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH3CMP1EN - 1- generate interrupt request when ch3cmp1f flag is set - 15 - 1 - read-write - - - CH3CMP0EN - 1- generate interrupt request when ch3cmp0f flag is set - 14 - 1 - read-write - - - CH3CAPEN - 1- generate interrupt request when ch3capf flag is set - 13 - 1 - read-write - - - CH3RLDEN - 1- generate interrupt request when ch3rldf flag is set - 12 - 1 - read-write - - - CH2CMP1EN - 1- generate interrupt request when ch2cmp1f flag is set - 11 - 1 - read-write - - - CH2CMP0EN - 1- generate interrupt request when ch2cmp0f flag is set - 10 - 1 - read-write - - - CH2CAPEN - 1- generate interrupt request when ch2capf flag is set - 9 - 1 - read-write - - - CH2RLDEN - 1- generate interrupt request when ch2rldf flag is set - 8 - 1 - read-write - - - CH1CMP1EN - 1- generate interrupt request when ch1cmp1f flag is set - 7 - 1 - read-write - - - CH1CMP0EN - 1- generate interrupt request when ch1cmp0f flag is set - 6 - 1 - read-write - - - CH1CAPEN - 1- generate interrupt request when ch1capf flag is set - 5 - 1 - read-write - - - CH1RLDEN - 1- generate interrupt request when ch1rldf flag is set - 4 - 1 - read-write - - - CH0CMP1EN - 1- generate interrupt request when ch0cmp1f flag is set - 3 - 1 - read-write - - - CH0CMP0EN - 1- generate interrupt request when ch0cmp0f flag is set - 2 - 1 - read-write - - - CH0CAPEN - 1- generate interrupt request when ch0capf flag is set - 1 - 1 - read-write - - - CH0RLDEN - 1- generate interrupt request when ch0rldf flag is set - 0 - 1 - read-write - - - - - GCR - Global control register - 0x208 - 32 - 0x00000000 - 0x0000000F - - - SWSYNCT - set this bitfield to trigger software counter sync event - 0 - 4 - read-write - - - - - - - NTMR1 - NTMR1 - GPTMR - 0xf2014000 - - - GPTMR0 - GPTMR0 - GPTMR - 0xf3000000 - - - GPTMR1 - GPTMR1 - GPTMR - 0xf3004000 - - - GPTMR2 - GPTMR2 - GPTMR - 0xf3008000 - - - GPTMR3 - GPTMR3 - GPTMR - 0xf300c000 - - - GPTMR4 - GPTMR4 - GPTMR - 0xf3010000 - - - GPTMR5 - GPTMR5 - GPTMR - 0xf3014000 - - - GPTMR6 - GPTMR6 - GPTMR - 0xf3018000 - - - GPTMR7 - GPTMR7 - GPTMR - 0xf301c000 - - - PTMR - PTMR - GPTMR - 0xf40e0000 - - - USB0 - USB0 - USB - 0xf2020000 - - 0x80 - 0x1a8 - registers - - - - GPTIMER0LD - General Purpose Timer #0 Load Register - 0x80 - 32 - 0x00000000 - 0x00FFFFFF - - - GPTLD - GPTLD -General Purpose Timer Load Value -These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. -This value represents the time in microseconds minus 1 for the timer duration. -Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. -NOTE: Max value is 0xFFFFFF or 16.777215 seconds. - 0 - 24 - read-write - - - - - GPTIMER0CTRL - General Purpose Timer #0 Controller Register - 0x84 - 32 - 0x00000000 - 0xC1FFFFFF - - - GPTRUN - GPTRUN -General Purpose Timer Run -GPTCNT bits are not effected when setting or clearing this bit. -0 - Stop counting -1 - Run - 31 - 1 - read-write - - - GPTRST - GPTRST -General Purpose Timer Reset -0 - No action -1 - Load counter value from GPTLD bits in n_GPTIMER0LD - 30 - 1 - write-only - - - GPTMODE - GPTMODE -General Purpose Timer Mode -In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is -reset by software; -In repeat mode, the timer will count down to zero, generate an interrupt and automatically reload the -counter value from GPTLD bits to start again. -0 - One Shot Mode -1 - Repeat Mode - 24 - 1 - read-write - - - GPTCNT - GPTCNT -General Purpose Timer Counter. -This field is the count value of the countdown timer. - 0 - 24 - read-only - - - - - GPTIMER1LD - General Purpose Timer #1 Load Register - 0x88 - 32 - 0x00000000 - 0x00FFFFFF - - - GPTLD - GPTLD -General Purpose Timer Load Value -These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. -This value represents the time in microseconds minus 1 for the timer duration. -Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. -NOTE: Max value is 0xFFFFFF or 16.777215 seconds. - 0 - 24 - read-write - - - - - GPTIMER1CTRL - General Purpose Timer #1 Controller Register - 0x8c - 32 - 0x00000000 - 0xC1FFFFFF - - - GPTRUN - GPTRUN -General Purpose Timer Run -GPTCNT bits are not effected when setting or clearing this bit. -0 - Stop counting -1 - Run - 31 - 1 - read-write - - - GPTRST - GPTRST -General Purpose Timer Reset -0 - No action -1 - Load counter value from GPTLD bits in USB_n_GPTIMER1LD - 30 - 1 - write-only - - - GPTMODE - GPTMODE -General Purpose Timer Mode -In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is -reset by software. In repeat mode, the timer will count down to zero, generate an interrupt and -automatically reload the counter value from GPTLD bits to start again. -0 - One Shot Mode -1 - Repeat Mode - 24 - 1 - read-write - - - GPTCNT - GPTCNT -General Purpose Timer Counter. -This field is the count value of the countdown timer. - 0 - 24 - read-only - - - - - SBUSCFG - System Bus Config Register - 0x90 - 32 - 0x00000000 - 0x00000007 - - - AHBBRST - AHBBRST -AHB master interface Burst configuration -These bits control AHB master transfer type sequence (or priority). -NOTE: This register overrides n_BURSTSIZE register when its value is not zero. -000 - Incremental burst of unspecified length only -001 - INCR4 burst, then single transfer -010 - INCR8 burst, INCR4 burst, then single transfer -011 - INCR16 burst, INCR8 burst, INCR4 burst, then single transfer -100 - Reserved, don't use -101 - INCR4 burst, then incremental burst of unspecified length -110 - INCR8 burst, INCR4 burst, then incremental burst of unspecified length -111 - INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length - 0 - 3 - read-write - - - - - USBCMD - USB Command Register - 0x140 - 32 - 0x00080000 - 0x00FFEB7F - - - ITC - ITC -Interrupt Threshold Control -Read/Write. -The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. -ITC contains the maximum interrupt interval measured in micro-frames. Valid values are -shown below. -Value Maximum Interrupt Interval -00000000 - Immediate (no threshold) -00000001 - 1 micro-frame -00000010 - 2 micro-frames -00000100 - 4 micro-frames -00001000 - 8 micro-frames -00010000 - 16 micro-frames -00100000 - 32 micro-frames -01000000 - 64 micro-frames - 16 - 8 - read-write - - - FS_2 - FS_2 -Frame List Size - (Read/Write or Read Only). [host mode only] -This field is Read/Write only if Programmable Frame List Flag in the HCCPARAMS registers is set to one. -This field specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. -NOTE: This field is made up from USBCMD bits 15, 3 and 2. -Value Meaning -0b000 - 1024 elements (4096 bytes) Default value -0b001 - 512 elements (2048 bytes) -0b010 - 256 elements (1024 bytes) -0b011 - 128 elements (512 bytes) -0b100 - 64 elements (256 bytes) -0b101 - 32 elements (128 bytes) -0b110 - 16 elements (64 bytes) -0b111 - 8 elements (32 bytes) - 15 - 1 - read-write - - - ATDTW - ATDTW -Add dTD TripWire - Read/Write. [device mode only] -This bit is used as a semaphore to ensure proper addition of a new dTD to an active (primed) endpoint's -linked list. This bit is set and cleared by software. -This bit would also be cleared by hardware when state machine is hazard region for which adding a dTD -to a primed endpoint may go unrecognized. - 14 - 1 - read-write - - - SUTW - SUTW -Setup TripWire - Read/Write. [device mode only] -This bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted. -If the setup lockout mode is off (SLOM bit in USB core register n_USBMODE, see USBMODE ) then -there is a hazard when new setup data arrives while the DCD is copying the setup data payload -from the QH for a previous setup packet. This bit is set and cleared by software. -This bit would also be cleared by hardware when a hazard detected. - 13 - 1 - read-write - - - ASPE - ASPE -Asynchronous Schedule Park Mode Enable - Read/Write. -If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this bit defaults to a 1h and is R/W. -Otherwise the bit must be a zero and is RO. Software uses this bit to enable or disable Park mode. -When this bit is one, Park mode is enabled. When this bit is a zero, Park mode is disabled. -NOTE: ASPE bit reset value: '0b' for OTG controller . - 11 - 1 - read-write - - - ASP - ASP -Asynchronous Schedule Park Mode Count - Read/Write. -If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this field defaults to 3h and is R/W. Otherwise it defaults to zero and is Read-Only. -It contains a count of the number of successive transactions the host controller is allowed to -execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. -Valid values are 1h to 3h. Software must not write a zero to this bit when Park Mode Enable is a one as this will result in undefined behavior. -This field is set to 3h in all controller core. - 8 - 2 - read-write - - - IAA - IAA -Interrupt on Async Advance Doorbell - Read/Write. -This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. Software must write a 1 to this bit to ring the doorbell. -When the host controller has evicted all appropriate cached schedule states, -it sets the Interrupt on Async Advance status bit in the USBSTS register. -If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold. -The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one. -Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results. -This bit is only used in host mode. Writing a one to this bit when device mode is selected will have undefined results. - 6 - 1 - read-write - - - ASE - ASE -Asynchronous Schedule Enable - Read/Write. Default 0b. -This bit controls whether the host controller skips processing the Asynchronous Schedule. -Only the host controller uses this bit. -Values Meaning -0 - Do not process the Asynchronous Schedule. -1 - Use the ASYNCLISTADDR register to access the Asynchronous Schedule. - 5 - 1 - read-write - - - PSE - PSE -Periodic Schedule Enable- Read/Write. Default 0b. -This bit controls whether the host controller skips processing the Periodic Schedule. -Only the host controller uses this bit. -Values Meaning -0 - Do not process the Periodic Schedule -1 - Use the PERIODICLISTBASE register to access the Periodic Schedule. - 4 - 1 - read-write - - - FS_1 - FS_1 -See description at bit 15 - 2 - 2 - read-write - - - RST - RST -Controller Reset (RESET) - Read/Write. Software uses this bit to reset the controller. -This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register. -Host operation mode: -When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. -Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. -Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. -Attempting to reset an actively running host controller will result in undefined behavior. -Device operation mode: -When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. -Writing a one to this bit when the device is in the attached state is not recommended, because the effect on an attached host is undefined. -In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0. - 1 - 1 - read-write - - - RS - RS -Run/Stop (RS) - Read/Write. Default 0b. 1=Run. 0=Stop. -Host operation mode: -When set to '1b', the Controller proceeds with the execution of the schedule. The Controller continues execution as long as this bit is set to a one. -When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. -The HC Halted bit in the status register indicates when the Controller has finished the transaction and has entered the stopped state. -Software should not write a one to this field unless the controller is in the Halted state (that is, HCHalted in the USBSTS register is a one). -Device operation mode: -Writing a one to this bit will cause the controller to enable a pull-up on D+ and initiate an attach event. -This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. -Software should use this bit to prevent an attach event before the controller has been properly initialized. Writing a 0 to this will cause a detach event. - 0 - 1 - read-write - - - - - USBSTS - USB Status Register - 0x144 - 32 - 0x00000000 - 0x030DF1FF - - - TI1 - TI1 -General Purpose Timer Interrupt 1(GPTINT1)--R/WC. -This bit is set when the counter in the GPTIMER1CTRL register transitions to zero, writing a one to this -bit will clear it. - 25 - 1 - read-write - - - TI0 - TI0 -General Purpose Timer Interrupt 0(GPTINT0)--R/WC. -This bit is set when the counter in the GPTIMER0CTRL register transitions to zero, writing a one to this -bit clears it. - 24 - 1 - read-write - - - UPI - USB Host Periodic Interrupt – RWC. Default = 0b. -This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction -where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. -This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. -A short packet is when the actual number of bytes received was less than expected. -This bit is not used by the device controller and will always be zero. - 19 - 1 - read-write - - - UAI - USB Host Asynchronous Interrupt – RWC. Default = 0b. -This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction -where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set AND the TD was from the asynchronous schedule. -This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. -A short packet is when the actual number of bytes received was less than expected. -This bit is not used by the device controller and will always be zero - 18 - 1 - read-write - - - NAKI - NAKI -NAK Interrupt Bit--RO. -This bit is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and -corresponding TX/RX Endpoint NAK Enable bit are set. This bit is automatically cleared by hardware -when all Enabled TX/RX Endpoint NAK bits are cleared. - 16 - 1 - read-only - - - AS - AS -Asynchronous Schedule Status - Read Only. -This bit reports the current real status of the Asynchronous Schedule. When set to zero the asynchronous schedule status is disabled and if set to one the status is enabled. -The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. -When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (1) or disabled (0). -Only used in the host operation mode. - 15 - 1 - read-only - - - PS - PS -Periodic Schedule Status - Read Only. -This bit reports the current real status of the Periodic Schedule. When set to zero the periodic schedule is disabled, and if set to one the status is enabled. -The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. -When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (1) or disabled (0). -Only used in the host operation mode. - 14 - 1 - read-only - - - RCL - RCL -Reclamation - Read Only. -This is a read-only status bit used to detect an empty asynchronous schedule. -Only used in the host operation mode. - 13 - 1 - read-only - - - HCH - HCH -HCHaIted - Read Only. -This bit is a zero whenever the Run/Stop bit is a one. - The Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, - either by software or by the Controller hardware (for example, an internal error). -Only used in the host operation mode. -Default value is '0b' for OTG core . -This is because OTG core is not operating as host in default. Please see CM bit in USB_n_USBMODE -register. -NOTE: HCH bit reset value: '0b' for OTG controller core . - 12 - 1 - read-only - - - SLI - SLI -DCSuspend - R/WC. -When a controller enters a suspend state from an active state, this bit will be set to a one. The device controller clears the bit upon exiting from a suspend state. -Only used in device operation mode. - 8 - 1 - read-write - - - SRI - SRI -SOF Received - R/WC. -When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. -When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. -Therefore, this bit will be set roughly every 1ms in device FS mode and every 125ms in HS mode and will be synchronized to the actual SOF that is received. -Because the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp. -In host mode, this bit will be set every 125us and can be used by host controller driver as a time base. -Software writes a 1 to this bit to clear it. - 7 - 1 - read-write - - - URI - URI -USB Reset Received - R/WC. -When the device controller detects a USB Reset and enters the default state, this bit will be set to a one. -Software can write a 1 to this bit to clear the USB Reset Received status bit. -Only used in device operation mode. - 6 - 1 - read-write - - - AAI - AAI -Interrupt on Async Advance - R/WC. -System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule -by writing a one to the Interrupt on Async Advance Doorbell bit in the n_USBCMD register. This status bit indicates the assertion of that interrupt source. -Only used in host operation mode. - 5 - 1 - read-write - - - SEI - System Error – RWC. Default = 0b. -In the BVCI implementation of the USBHS core, this bit is not used, and will always be cleared to '0b'. -In the AMBA implementation, this bit will be set to '1b' when an Error response is seen by the master interface (HRESP[1:0]=ERROR) - 4 - 1 - read-write - - - FRI - FRI -Frame List Rollover - R/WC. -The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to -zero. The exact value at which the rollover occurs depends on the frame list size. For example. If the -frame list size (as programmed in the Frame List Size field of the USB_n_USBCMD register) is 1024, the -Frame Index Register rolls over every time FRINDEX [13] toggles. Similarly, if the size is 512, the Host -Controller sets this bit to a one every time FHINDEX [12] toggles. -Only used in host operation mode. - 3 - 1 - read-write - - - PCI - PCI -Port Change Detect - R/WC. -The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, -or the Force Port Resume bit is set as the result of a J-K transition on the suspended port. -The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. -When the port controller exits the full or high-speed operation states due to Reset or Suspend events, -the notification mechanisms are the USB Reset Received bit and the DCSuspend bits Respectively. - 2 - 1 - read-write - - - UEI - UEI -USB Error Interrupt (USBERRINT) - R/WC. -When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. -This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. - 1 - 1 - read-write - - - UI - UI -USB Interrupt (USBINT) - R/WC. -This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB -transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. -This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when -the actual number of bytes received was less than the expected number of bytes. - 0 - 1 - read-write - - - - - USBINTR - Interrupt Enable Register - 0x148 - 32 - 0x00000000 - 0x030D01FF - - - TIE1 - TIE1 -General Purpose Timer #1 Interrupt Enable -When this bit is one and the TI1 bit in n_USBSTS register is a one the controller will issue an interrupt. - 25 - 1 - read-write - - - TIE0 - TIE0 -General Purpose Timer #0 Interrupt Enable -When this bit is one and the TI0 bit in n_USBSTS register is a one the controller will issue an interrupt. - 24 - 1 - read-write - - - UPIE - UPIE -USB Host Periodic Interrupt Enable -When this bit is one, and the UPI bit in the n_USBSTS register is one, host controller will issue an -interrupt at the next interrupt threshold. - 19 - 1 - read-write - - - UAIE - UAIE -USB Host Asynchronous Interrupt Enable -When this bit is one, and the UAI bit in the n_USBSTS register is one, host controller will issue an -interrupt at the next interrupt threshold. - 18 - 1 - read-write - - - NAKE - NAKE -NAK Interrupt Enable -When this bit is one and the NAKI bit in n_USBSTS register is a one the controller will issue an interrupt. - 16 - 1 - read-only - - - SLE - SLE -Sleep Interrupt Enable -When this bit is one and the SLI bit in n_n_USBSTS register is a one the controller will issue an interrupt. -Only used in device operation mode. - 8 - 1 - read-write - - - SRE - SRE -SOF Received Interrupt Enable -When this bit is one and the SRI bit in n_USBSTS register is a one the controller will issue an interrupt. - 7 - 1 - read-write - - - URE - URE -USB Reset Interrupt Enable -When this bit is one and the URI bit in n_USBSTS register is a one the controller will issue an interrupt. -Only used in device operation mode. - 6 - 1 - read-write - - - AAE - AAE -Async Advance Interrupt Enable -When this bit is one and the AAI bit in n_USBSTS register is a one the controller will issue an interrupt. -Only used in host operation mode. - 5 - 1 - read-write - - - SEE - SEE -System Error Interrupt Enable -When this bit is one and the SEI bit in n_USBSTS register is a one the controller will issue an interrupt. -Only used in host operation mode. - 4 - 1 - read-write - - - FRE - FRE -Frame List Rollover Interrupt Enable -When this bit is one and the FRI bit in n_USBSTS register is a one the controller will issue an interrupt. -Only used in host operation mode. - 3 - 1 - read-write - - - PCE - PCE -Port Change Detect Interrupt Enable -When this bit is one and the PCI bit in n_USBSTS register is a one the controller will issue an interrupt. - 2 - 1 - read-write - - - UEE - UEE -USB Error Interrupt Enable -When this bit is one and the UEI bit in n_USBSTS register is a one the controller will issue an interrupt. - 1 - 1 - read-write - - - UE - UE -USB Interrupt Enable -When this bit is one and the UI bit in n_USBSTS register is a one the controller will issue an interrupt. - 0 - 1 - read-write - - - - - FRINDEX - USB Frame Index Register - 0x14c - 32 - 0x00000000 - 0x00003FFF - - - FRINDEX - FRINDEX -Frame Index. -The value, in this register, increments at the end of each time frame (micro-frame). Bits [N: 3] are used for the Frame List current index. -This means that each location of the frame list is accessed 8 times (frames or micro-frames) before moving to the next index. -The following illustrates values of N based on the value of the Frame List Size field in the USBCMD register, when used in host mode. -USBCMD [Frame List Size] Number Elements N -In device mode the value is the current frame number of the last frame transmitted. It is not used as an index. -In either mode bits 2:0 indicate the current microframe. -The bit field values description below is represented as (Frame List Size) Number Elements N. -00000000000000 - (1024) 12 -00000000000001 - (512) 11 -00000000000010 - (256) 10 -00000000000011 - (128) 9 -00000000000100 - (64) 8 -00000000000101 - (32) 7 -00000000000110 - (16) 6 -00000000000111 - (8) 5 - 0 - 14 - read-write - - - - - DEVICEADDR - Device Address Register - UNION_154 - 0x154 - 32 - 0x00000000 - 0xFF000000 - - - USBADR - USBADR -Device Address. -These bits correspond to the USB device address - 25 - 7 - read-write - - - USBADRA - USBADRA -Device Address Advance. Default=0. -When this bit is '0', any writes to USBADR are instantaneous. - When this bit is written to a '1' at the same time or before USBADR is written, the write to the USBADR field is staged and held in a hidden register. -After an IN occurs on endpoint 0 and is ACKed, USBADR will be loaded from the holding register. -Hardware will automatically clear this bit on the following conditions: -1) IN is ACKed to endpoint 0. (USBADR is updated from staging register). -2) OUT/SETUP occur to endpoint 0. (USBADR is not updated). -3) Device Reset occurs (USBADR is reset to 0). -NOTE: After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. -This mechanism will ensure this specification is met when the DCD can not write of the device address within 2ms from the SET_ADDRESS status phase. -If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), -the USBADR will be programmed instantly at the correct time and meet the 2ms USB requirement. - 24 - 1 - read-write - - - - - PERIODICLISTBASE - Frame List Base Address Register - UNION_154 - 0x154 - 32 - 0x00000000 - 0xFFFFF000 - - - BASEADR - BASEADR -Base Address (Low). -These bits correspond to memory address signals [31:12], respectively. -Only used by the host controller. - 12 - 20 - read-write - - - - - ASYNCLISTADDR - Next Asynch. Address Register - UNION_158 - 0x158 - 32 - 0x00000000 - 0xFFFFFFE0 - - - ASYBASE - ASYBASE -Link Pointer Low (LPL). -These bits correspond to memory address signals [31:5], respectively. This field may only reference a -Queue Head (QH). -Only used by the host controller. - 5 - 27 - read-write - - - - - ENDPTLISTADDR - Endpoint List Address Register - UNION_158 - 0x158 - 32 - 0x00000000 - 0xFFFFF800 - - - EPBASE - EPBASE -Endpoint List Pointer(Low). These bits correspond to memory address signals [31:11], respectively. -This field will reference a list of up to 32 Queue Head (QH) (that is, one queue head per endpoint & direction). - 11 - 21 - read-write - - - - - BURSTSIZE - Programmable Burst Size Register - 0x160 - 32 - 0x00000000 - 0x0000FFFF - - - TXPBURST - TXPBURST -Programmable TX Burst Size. -Default value is determined by TXBURST bits in n_HWTXBUF. -This register represents the maximum length of a the burst in 32-bit words while moving data from system -memory to the USB bus. - 8 - 8 - read-write - - - RXPBURST - RXPBURST -Programmable RX Burst Size. -Default value is determined by TXBURST bits in n_HWRXBUF. -This register represents the maximum length of a the burst in 32-bit words while moving data from the -USB bus to system memory. - 0 - 8 - read-write - - - - - TXFILLTUNING - TX FIFO Fill Tuning Register - 0x164 - 32 - 0x00000000 - 0x003F1F7F - - - TXFIFOTHRES - TXFIFOTHRES -FIFO Burst Threshold. (Read/Write) -This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. -The minimum value is 2 and this value should be a low as possible to maximize USB performance. -A higher value can be used in systems with unpredictable latency and/or insufficient bandwidth -where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory. -This value is ignored if the Stream Disable bit in USB_n_USBMODE register is set. - 16 - 6 - read-write - - - TXSCHHEALTH - TXSCHHEALTH -Scheduler Health Counter. (Read/Write To Clear) -Table continues on the next page -This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES -before running out of time to send the packet before the next Start-Of-Frame. -This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. -Writing to this register will clear the counter and this counter will max. at 31. - 8 - 5 - read-write - - - TXSCHOH - TXSCHOH -Scheduler Overhead. (Read/Write) [Default = 0] -This register adds an additional fixed offset to the schedule time estimator described above as Tff. -As an approximation, the value chosen for this register should limit the number of back-off events captured -in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. -Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization. -The time unit represented in this register is 1.267us when a device is connected in High-Speed Mode. -The time unit represented in this register is 6.333us when a device is connected in Low/Full Speed Mode. -Default value is '08h' for OTG controller core . - 0 - 7 - read-write - - - - - ENDPTNAK - Endpoint NAK Register - 0x178 - 32 - 0x00000000 - 0xFFFFFFFF - - - EPTN - EPTN -TX Endpoint NAK - R/WC. -Each TX endpoint has 1 bit in this field. The bit is set when the -device sends a NAK handshake on a received IN token for the corresponding endpoint. -Bit [N] - Endpoint #[N], N is 0-7 - 16 - 16 - read-write - - - EPRN - EPRN -RX Endpoint NAK - R/WC. -Each RX endpoint has 1 bit in this field. The bit is set when the -device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. -Bit [N] - Endpoint #[N], N is 0-7 - 0 - 16 - read-write - - - - - ENDPTNAKEN - Endpoint NAK Enable Register - 0x17c - 32 - 0x00000000 - 0xFFFFFFFF - - - EPTNE - EPTNE -TX Endpoint NAK Enable - R/W. -Each bit is an enable bit for the corresponding TX Endpoint NAK bit. If this bit is set and the -corresponding TX Endpoint NAK bit is set, the NAK Interrupt bit is set. -Bit [N] - Endpoint #[N], N is 0-7 - 16 - 16 - read-write - - - EPRNE - EPRNE -RX Endpoint NAK Enable - R/W. -Each bit is an enable bit for the corresponding RX Endpoint NAK bit. If this bit is set and the -corresponding RX Endpoint NAK bit is set, the NAK Interrupt bit is set. -Bit [N] - Endpoint #[N], N is 0-7 - 0 - 16 - read-write - - - - - PORTSC1 - Port Status & Control - 0x184 - 32 - 0x00000000 - 0x3DFF1FFF - - - STS - STS -Serial Transceiver Select -1 Serial Interface Engine is selected -0 Parallel Interface signals is selected -Serial Interface Engine can be used in combination with UTMI+/ULPI physical interface to provide FS/LS signaling instead of the parallel interface signals. -When this bit is set '1b', serial interface engine will be used instead of parallel interface signals. - 29 - 1 - read-write - - - PTW - PTW -Parallel Transceiver Width -This bit has no effect if serial interface engine is used. -0 - Select the 8-bit UTMI interface [60MHz] -1 - Select the 16-bit UTMI interface [30MHz] - 28 - 1 - read-write - - - PSPD - PSPD -Port Speed - Read Only. -This register field indicates the speed at which the port is operating. -00 - Full Speed -01 - Low Speed -10 - High Speed -11 - Undefined - 26 - 2 - read-only - - - PFSC - PFSC -Port Force Full Speed Connect - Read/Write. Default = 0b. -When this bit is set to '1b', the port will be forced to only connect at Full Speed, It disables the chirp -sequence that allows the port to identify itself as High Speed. -0 - Normal operation -1 - Forced to full speed - 24 - 1 - read-write - - - PHCD - PHCD -PHY Low Power Suspend - Clock Disable (PLPSCD) - Read/Write. Default = 0b. -When this bit is set to '1b', the PHY clock is disabled. Reading this bit will indicate the status of the PHY -clock. -NOTE: The PHY clock cannot be disabled if it is being used as the system clock. -In device mode, The PHY can be put into Low Power Suspend when the device is not running (USBCMD -Run/Stop=0b) or the host has signalled suspend (PORTSC1 SUSPEND=1b). PHY Low power suspend -will be cleared automatically when the host initials resume. Before forcing a resume from the device, the -device controller driver must clear this bit. -In host mode, the PHY can be put into Low Power Suspend when the downstream device has been put -into suspend mode or when no downstream device is connected. Low power suspend is completely -under the control of software. -0 - Enable PHY clock -1 - Disable PHY clock - 23 - 1 - read-write - - - WKOC - WKOC -Wake on Over-current Enable (WKOC_E) - Read/Write. Default = 0b. -Writing this bit to a one enables the port to be sensitive to over-current conditions as wake-up events. -This field is zero if Port Power(PORTSC1) is zero. - 22 - 1 - read-write - - - WKDC - WKDC -Wake on Disconnect Enable (WKDSCNNT_E) - Read/Write. Default=0b. Writing this bit to a one enables -the port to be sensitive to device disconnects as wake-up events. -This field is zero if Port Power(PORTSC1) is zero or in device mode. - 21 - 1 - read-write - - - WKCN - WKCN -Wake on Connect Enable (WKCNNT_E) - Read/Write. Default=0b. -Writing this bit to a one enables the port to be sensitive to device connects as wake-up events. -This field is zero if Port Power(PORTSC1) is zero or in device mode. - 20 - 1 - read-write - - - PTC - PTC -Port Test Control - Read/Write. Default = 0000b. -Refer to Port Test Mode for the operational model for using these test modes and the USB Specification Revision 2.0, Chapter 7 for details on each test mode. -The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. -Writing the PTC field to any of the FORCE_ENABLE_{HS/FS/LS} values will force the port into the connected and enabled state at the selected speed. -Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. -NOTE: Low speed operations are not supported as a peripheral device. -Any other value than zero indicates that the port is operating in test mode. -Value Specific Test -0000 - TEST_MODE_DISABLE -0001 - J_STATE -0010 - K_STATE -0011 - SE0 (host) / NAK (device) -0100 - Packet -0101 - FORCE_ENABLE_HS -0110 - FORCE_ENABLE_FS -0111 - FORCE_ENABLE_LS -1000-1111 - Reserved - 16 - 4 - read-write - - - PP - PP -Port Power (PP)-Read/Write or Read Only. -The function of this bit depends on the value of the Port Power Switching (PPC) field in the HCSPARAMS register. The behavior is as follows: -PPC -PP Operation -0 -1b Read Only - Host controller does not have port power control switches. Each port is hard-wired to power. -1 -1b/0b - Read/Write. OTG controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on). -When power is not available on a port (that is, PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. -When an over-current condition is detected on a powered port and PPC is a one, -the PP bit in each affected port may be transitional by the host controller driver from a one to a zero (removing power from the port). -This feature is implemented in all controller cores (PPC = 1). - 12 - 1 - read-write - - - LS - LS -Line Status-Read Only. These bits reflect the current logical levels of the D+ (bit 11) and D- (bit 10) signal -lines. -In host mode, the use of linestate by the host controller driver is not necessary (unlike EHCI), because -the port controller state machine and the port routing manage the connection of LS and FS. -In device mode, the use of linestate by the device controller driver is not necessary. -The encoding of the bits are: -Bits [11:10] Meaning -00 - SE0 -01 - K-state -10 - J-state -11 - Undefined - 10 - 2 - read-only - - - HSP - HSP -High-Speed Port - Read Only. Default = 0b. -When the bit is one, the host/device connected to the port is in high-speed mode and if set to zero, the -host/device connected to the port is not in a high-speed mode. -NOTE: HSP is redundant with PSPD(bit 27, 26) but remained for compatibility. - 9 - 1 - read-only - - - PR - PR -Port Reset - Read/Write or Read Only. Default = 0b. -In Host Mode: Read/Write. 1=Port is in Reset. 0=Port is not in Reset. Default 0. -When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. -This bit will automatically change to zero after the reset sequence is complete. -This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timed in the driver. -In Device Mode: This bit is a read only status bit. Device reset from the USB bus is also indicated in the USBSTS register. - 8 - 1 - read-write - - - SUSP - SUSP -Suspend - Read/Write or Read Only. Default = 0b. -1=Port in suspend state. 0=Port not in suspend state. -In Host Mode: Read/Write. -Port Enabled Bit and Suspend bit of this register define the port states as follows: -Bits [Port Enabled, Suspend] Port State -0x Disable -10 Enable -11 Suspend -When in suspend state, downstream propagation of data is blocked on this port, except for port reset. -The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. -In the suspend state, the port is sensitive to resume detection. -Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB. -The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. The host controller ignores a write of zero to this bit. -If host software sets this bit to a one when the port is not enabled (that is, Port enabled bit is a zero) the results are undefined. -This field is zero if Port Power(PORTSC1) is zero in host mode. -In Device Mode: Read Only. -In device mode this bit is a read only status bit. - 7 - 1 - read-write - - - FPR - FPR -Force Port Resume -Read/Write. 1= Resume detected/driven on port. 0=No resume (K-state) detected driven on port. Default = 0. -In Host Mode: -Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one if a J-to-K transition is detected while the port is in the Suspend state. -When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. -This bit will automatically change to zero after the resume sequence is complete. -This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the resume duration is timed in the driver. -Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. -The resume signaling (Full-speed 'K') is driven on the port as long as this bit remains a one. This bit will remain a one until the port has switched to the high-speed idle. -Writing a zero has no effect because the port controller will time the resume operation, clear the bit the port control state switches to HS or FS idle. -This field is zero if Port Power(PORTSC1) is zero in host mode. -This bit is not-EHCI compatible. -In Device mode: -After the device has been in Suspend State for 5ms or more, software must set this bit to one to drive resume signaling before clearing. -The Device Controller will set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. -The bit will be cleared when the device returns to normal operation. - Also, when this bit wil be cleared because a K-to-J transition detected, the Port Change Detect bit in the USBSTS register is also set to one. - 6 - 1 - read-write - - - OCC - OCC -Over-current Change-R/WC. Default=0. -This bit is set '1b' by hardware when there is a change to Over-current Active. Software can clear this bit by writing a one to this bit position. - 5 - 1 - read-write - - - OCA - OCA -Over-current Active-Read Only. Default 0. -This bit will automatically transition from one to zero when the over current condition is removed. -0 - This port does not have an over-current condition. -1 - This port currently has an over-current condition - 4 - 1 - read-only - - - PEC - PEC -Port Enable/Disable Change-R/WC. 1=Port enabled/disabled status has changed. 0=No change. Default = 0. -In Host Mode: -For the root hub, this bit is set to a one only when a port is disabled due to disconnect on the port or -due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). -Software clears this by writing a one to it. -This field is zero if Port Power(PORTSC1) is zero. -In Device mode: -The device port is always enabled, so this bit is always '0b'. - 3 - 1 - read-write - - - PE - PE -Port Enabled/Disabled-Read/Write. 1=Enable. 0=Disable. Default 0. -In Host Mode: -Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. -Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. -Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. -When the port is disabled, (0b) downstream propagation of data is blocked except for reset. -This field is zero if Port Power(PORTSC1) is zero in host mode. -In Device Mode: -The device port is always enabled, so this bit is always '1b'. - 2 - 1 - read-write - - - CSC - CSC -Connect Status Change-R/WC. 1 =Change in Current Connect Status. 0=No change. Default 0. -In Host Mode: -Indicates a change has occurred in the port's Current Connect Status. -The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. -For example, the insertion status changes twice before system software has cleared the changed condition, -hub hardware will be 'setting' an already-set bit (that is, the bit will remain set). Software clears this bit by writing a one to it. -This field is zero if Port Power(PORTSC1) is zero in host mode. -In Device Mode: -This bit is undefined in device controller mode. - 1 - 1 - read-write - - - CCS - CCS -Current Connect Status-Read Only. -In Host Mode: -1=Device is present on port. 0=No device is present. Default = 0. -This value reflects the current state of the port, and may not correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set. -This field is zero if Port Power(PORTSC1) is zero in host mode. -In Device Mode: -1=Attached. 0=Not Attached. Default=0. -A one indicates that the device successfully attached and is operating in either high speed or full speed as indicated by the High Speed Port bit in this register. -A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. -It does not state the device being disconnected or Suspended. - 0 - 1 - read-write - - - - - OTGSC - On-The-Go Status & control Register - 0x1a4 - 32 - 0x00000000 - 0x07070723 - - - ASVIE - ASVIE -A Session Valid Interrupt Enable - Read/Write. - 26 - 1 - read-write - - - AVVIE - AVVIE -A VBus Valid Interrupt Enable - Read/Write. -Setting this bit enables the A VBus valid interrupt. - 25 - 1 - read-write - - - IDIE - IDIE -USB ID Interrupt Enable - Read/Write. -Setting this bit enables the USB ID interrupt. - 24 - 1 - read-write - - - ASVIS - ASVIS -A Session Valid Interrupt Status - Read/Write to Clear. -This bit is set when VBus has either risen above or fallen below the A session valid threshold. -Software must write a one to clear this bit. - 18 - 1 - read-write - - - AVVIS - AVVIS -A VBus Valid Interrupt Status - Read/Write to Clear. -This bit is set when VBus has either risen above or fallen below the VBus valid threshold on an A device. -Software must write a one to clear this bit. - 17 - 1 - read-write - - - IDIS - IDIS -USB ID Interrupt Status - Read/Write. -This bit is set when a change on the ID input has been detected. -Software must write a one to clear this bit. - 16 - 1 - read-write - - - ASV - ASV -A Session Valid - Read Only. -Indicates VBus is above the A session valid threshold. - 10 - 1 - read-only - - - AVV - AVV -A VBus Valid - Read Only. -Indicates VBus is above the A VBus valid threshold. - 9 - 1 - read-only - - - ID - ID -USB ID - Read Only. -0 = A device, 1 = B device - 8 - 1 - read-only - - - IDPU - IDPU -ID Pullup - Read/Write -This bit provide control over the ID pull-up resistor; 0 = off, 1 = on [default]. When this bit is 0, the ID input -will not be sampled. - 5 - 1 - read-write - - - VC - VC -VBUS Charge - Read/Write. -Setting this bit causes the VBus line to be charged. This is used for VBus pulsing during SRP. - 1 - 1 - read-write - - - VD - VD -VBUS_Discharge - Read/Write. -Setting this bit causes VBus to discharge through a resistor. - 0 - 1 - read-write - - - - - USBMODE - USB Device Mode Register - 0x1a8 - 32 - 0x00000000 - 0x0000001F - - - SDIS - SDIS -Stream Disable Mode. (0 - Inactive [default]; 1 - Active) -Device Mode: Setting to a '1' disables double priming on both RX and TX for low bandwidth systems. -This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. -Note: In High Speed Mode, all packets received are responded to with a NYET handshake when stream disable is active. -Host Mode: Setting to a '1' ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems -where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the TX latency is filled to capacity before the packet is launched onto the USB. -NOTE: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING and TXTTFILLTUNING [MPH Only] to characterize the adjustments needed for -the scheduler when using this feature. -NOTE: The use of this feature substantially limits of the overall USB performance that can be achieved. - 4 - 1 - read-write - - - SLOM - SLOM -Setup Lockout Mode. In device mode, this bit controls behavior of the setup lock mechanism. See Control Endpoint Operation Model . -0 - Setup Lockouts On (default); -1 - Setup Lockouts Off. DCD requires use of Setup Data Buffer Tripwire in USBCMD. - 3 - 1 - read-write - - - ES - ES -Endian Select - Read/Write. This bit can change the byte alignment of the transfer buffers to match the -host microprocessor. The bit fields in the microprocessor interface and the data structures are unaffected -by the value of this bit because they are based upon the 32-bit word. -Bit Meaning -0 - Little Endian [Default] -1 - Big Endian - 2 - 1 - read-write - - - CM - CM -Controller Mode - R/WO. Controller mode is defaulted to the proper mode for host only and device only -implementations. For those designs that contain both host & device capability, the controller defaults to -an idle state and needs to be initialized to the desired operating mode after reset. For combination host/ -device controllers, this register can only be written once after reset. If it is necessary to switch modes, -software must reset the controller by writing to the RESET bit in the USBCMD register before -reprogramming this register. -For OTG controller core, reset value is '00b'. -00 - Idle [Default for combination host/device] -01 - Reserved -10 - Device Controller [Default for device only controller] -11 - Host Controller [Default for host only controller] - 0 - 2 - read-write - - - - - ENDPTSETUPSTAT - Endpoint Setup Status Register - 0x1ac - 32 - 0x00000000 - 0x0000FFFF - - - ENDPTSETUPSTAT - ENDPTSETUPSTAT -Setup Endpoint Status. For every setup transaction that is received, a corresponding bit in this register is set to one. -Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. -The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lock out mechanism is engaged. -This register is only used in device mode. - 0 - 16 - read-write - - - - - ENDPTPRIME - Endpoint Prime Register - 0x1b0 - 32 - 0x00000000 - 0xFFFFFFFF - - - PETB - PETB -Prime Endpoint Transmit Buffer - R/WS. For each endpoint a corresponding bit is used to request that a -buffer is prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. -Software should write a one to the corresponding bit when posting a new transfer descriptor to an -endpoint queue head. Hardware automatically uses this bit to begin parsing for a new transfer descriptor -from the queue head and prepare a transmit buffer. Hardware clears this bit when the associated -endpoint(s) is (are) successfully primed. -NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD -is retired, and the dQH is updated. -PETB[N] - Endpoint #N, N is in 0..7 - 16 - 16 - read-write - - - PERB - PERB -Prime Endpoint Receive Buffer - R/WS. For each endpoint, a corresponding bit is used to request a buffer prepare for a receive operation for when a USB host initiates a USB OUT transaction. -Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint queue head. -Hardware automatically uses this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. -Hardware clears this bit when the associated endpoint(s) is (are) successfully primed. -NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD -is retired, and the dQH is updated. -PERB[N] - Endpoint #N, N is in 0..7 - 0 - 16 - read-write - - - - - ENDPTFLUSH - Endpoint Flush Register - 0x1b4 - 32 - 0x00000000 - 0xFFFFFFFF - - - FETB - FETB -Flush Endpoint Transmit Buffer - R/WS. Writing one to a bit(s) in this register causes the associated endpoint(s) to clear any primed buffers. -If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. -Hardware clears this register after the endpoint flush operation is successful. -FETB[N] - Endpoint #N, N is in 0..7 - 16 - 16 - read-write - - - FERB - FERB -Flush Endpoint Receive Buffer - R/WS. Writing one to a bit(s) causes the associated endpoint(s) to clear any primed buffers. - If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. -Hardware clears this register after the endpoint flush operation is successful. -FERB[N] - Endpoint #N, N is in 0..7 - 0 - 16 - read-write - - - - - ENDPTSTAT - Endpoint Status Register - 0x1b8 - 32 - 0x00000000 - 0xFFFFFFFF - - - ETBR - ETBR -Endpoint Transmit Buffer Ready -- Read Only. One bit for each endpoint indicates status of the respective endpoint buffer. -This bit is set to one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. -There is always a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. -This delay time varies based upon the current USB traffic and the number of bits set in the ENDPRIME register. -Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. -NOTE: These bits are momentarily cleared by hardware during hardware endpoint re-priming operations when a dTD is retired, and the dQH is updated. -ETBR[N] - Endpoint #N, N is in 0..7 - 16 - 16 - read-only - - - ERBR - ERBR -Endpoint Receive Buffer Ready -- Read Only. One bit for each endpoint indicates status of the respective -endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a -corresponding bit in the ENDPRIME register. There is always a delay between setting a bit in the -ENDPRIME register and endpoint indicating ready. This delay time varies based upon the current USB -traffic and the number of bits set in the ENDPRIME register. Buffer ready is cleared by USB reset, by the -USB DMA system, or through the ENDPTFLUSH register. -NOTE: These bits are momentarily cleared by hardware during hardware endpoint re-priming operations -when a dTD is retired, and the dQH is updated. -ERBR[N] - Endpoint #N, N is in 0..7 - 0 - 16 - read-only - - - - - ENDPTCOMPLETE - Endpoint Complete Register - 0x1bc - 32 - 0x00000000 - 0xFFFFFFFF - - - ETCE - ETCE -Endpoint Transmit Complete Event - R/WC. Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. -If the corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the USBINT . Writing one clears the corresponding bit in this register. -ETCE[N] - Endpoint #N, N is in 0..7 - 16 - 16 - read-write - - - ERCE - ERCE -Endpoint Receive Complete Event - RW/C. Each bit indicates a received event (OUT/SETUP) occurred -and software should read the corresponding endpoint queue to determine the transfer status. If the -corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the -USBINT . Writing one clears the corresponding bit in this register. -ERCE[N] - Endpoint #N, N is in 0..7 - 0 - 16 - read-write - - - - - 8 - 0x4 - ENDPTCTRL0,ENDPTCTRL1,ENDPTCTRL2,ENDPTCTRL3,ENDPTCTRL4,ENDPTCTRL5,ENDPTCTRL6,ENDPTCTRL7 - ENDPTCTRL[%s] - no description available - 0x1c0 - 32 - 0x00000000 - 0x00CD00CD - - - TXE - TXE -TX Endpoint Enable -0 Disabled [Default] -1 Enabled -An Endpoint should be enabled only after it has been configured. - 23 - 1 - read-write - - - TXR - TXR -TX Data Toggle Reset (WS) -Write 1 - Reset PID Sequence -Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order -to synchronize the data PID's between the Host and device. - 22 - 1 - write-only - - - TXT - TXT -TX Endpoint Type - Read/Write -00 Control -01 Isochronous -10 Bulk -11 Interrupt - 18 - 2 - read-write - - - TXS - TXS -TX Endpoint Stall - Read/Write -0 End Point OK -1 End Point Stalled -This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured -as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. -Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. -This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. -NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. -In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: -continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. - 16 - 1 - read-write - - - RXE - RXE -RX Endpoint Enable -0 Disabled [Default] -1 Enabled -An Endpoint should be enabled only after it has been configured. - 7 - 1 - read-write - - - RXR - RXR -RX Data Toggle Reset (WS) -Write 1 - Reset PID Sequence -Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order -to synchronize the data PID's between the host and device. - 6 - 1 - write-only - - - RXT - RXT -RX Endpoint Type - Read/Write -00 Control -01 Isochronous -10 Bulk -11 Interrupt - 2 - 2 - read-write - - - RXS - RXS -RX Endpoint Stall - Read/Write -0 End Point OK. [Default] -1 End Point Stalled -This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control -Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit -is cleared. -Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This -control will continue to STALL until this bit is either cleared by software or automatically cleared as above -for control endpoints. -NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the -ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it -is unlikely the DCD software will observe this delay. However, should the DCD observe that the -stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit -until it is set or until a new setup has been received by checking the associated endptsetupstat -Bit. - 0 - 1 - read-write - - - - - OTG_CTRL0 - No description available - 0x200 - 32 - 0x00000000 - 0x020B3F90 - - - OTG_WKDPDMCHG_EN - No description available - 25 - 1 - read-write - - - AUTORESUME_EN - No description available - 19 - 1 - read-write - - - OTG_VBUS_WAKEUP_EN - No description available - 17 - 1 - read-write - - - OTG_ID_WAKEUP_EN - No description available - 16 - 1 - read-write - - - OTG_VBUS_SOURCE_SEL - No description available - 13 - 1 - read-write - - - OTG_UTMI_SUSPENDM_SW - default 0 for naneng usbphy - 12 - 1 - read-write - - - OTG_UTMI_RESET_SW - default 1 for naneng usbphy - 11 - 1 - read-write - - - OTG_WAKEUP_INT_ENABLE - No description available - 10 - 1 - read-write - - - OTG_POWER_MASK - No description available - 9 - 1 - read-write - - - OTG_OVER_CUR_POL - No description available - 8 - 1 - read-write - - - OTG_OVER_CUR_DIS - No description available - 7 - 1 - read-write - - - SER_MODE_SUSPEND_EN - for naneng usbphy, only switch to serial mode when suspend - 4 - 1 - read-write - - - - - PHY_CTRL0 - No description available - 0x210 - 32 - 0x00000000 - 0x02007007 - - - GPIO_ID_SEL_N - No description available - 25 - 1 - read-write - - - ID_DIG_OVERRIDE - No description available - 14 - 1 - read-write - - - SESS_VALID_OVERRIDE - No description available - 13 - 1 - read-write - - - VBUS_VALID_OVERRIDE - No description available - 12 - 1 - read-write - - - ID_DIG_OVERRIDE_EN - No description available - 2 - 1 - read-write - - - SESS_VALID_OVERRIDE_EN - No description available - 1 - 1 - read-write - - - VBUS_VALID_OVERRIDE_EN - No description available - 0 - 1 - read-write - - - - - PHY_CTRL1 - No description available - 0x214 - 32 - 0x00000000 - 0x00100002 - - - UTMI_CFG_RST_N - No description available - 20 - 1 - read-write - - - UTMI_OTG_SUSPENDM - OTG suspend, not utmi_suspendm - 1 - 1 - read-write - - - - - TOP_STATUS - No description available - 0x220 - 32 - 0x00000000 - 0x80000000 - - - WAKEUP_INT_STATUS - No description available - 31 - 1 - read-write - - - - - PHY_STATUS - No description available - 0x224 - 32 - 0x00000000 - 0x800000F5 - - - UTMI_CLK_VALID - No description available - 31 - 1 - read-write - - - LINE_STATE - No description available - 6 - 2 - read-write - - - HOST_DISCONNECT - No description available - 5 - 1 - read-write - - - ID_DIG - No description available - 4 - 1 - read-write - - - UTMI_SESS_VALID - No description available - 2 - 1 - read-write - - - VBUS_VALID - No description available - 0 - 1 - read-write - - - - - - - USB1 - USB1 - USB - 0xf2024000 - - - SDXC0 - SDXC0 - SDXC - 0xf2030000 - - 0x0 - 0x548 - registers - - - - SDMASA - No description available - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - BLOCKCNT_SDMASA - 32-bit Block Count (SDMA System Address) -- SDMA System Address (Host Version 4 Enable = 0): This register contains the system memory address for an SDMA transfer in the 32-bit addressing mode. -When the Host Controller stops an SDMA transfer, this register points to the system address of the next contiguous data position. -It can be accessed only if no transaction is executing. Reading this register during data transfers may -return an invalid value. -- 32-bit Block Count (Host Version 4 Enable = 1): From the Host Controller Version 4.10 specification, this register is redefined as 32-bit Block Count. -The Host Controller decrements the block count of this register for every block transfer and the data transfer stops when the count reaches zero. -This register must be accessed when no transaction is executing. Reading this register during data transfers may return invalid value. -Following are the values for BLOCKCNT_SDMASA: -- 0xFFFF_FFFF: 4G - 1 Block -- -- 0x0000_0002: 2 Blocks -- 0x0000_0001: 1 Block -- 0x0000_0000: Stop Count -Note: -- For Host Version 4 Enable = 0, the Host driver does not program the system address in this register while operating in ADMA mode. -The system address must be programmed in the ADMA System Address register. -- For Host Version 4 Enable = 0, the Host driver programs a non-zero 32-bit block count value in this register when Auto CMD23 is enabled for non-DMA and ADMA modes. -Auto CMD23 cannot be used with SDMA. -- This register must be programmed with a non-zero value for data transfer if the 32-bit Block count register is used instead of the 16-bit Block count register. - 0 - 32 - read-write - - - - - BLK_ATTR - No description available - 0x4 - 32 - 0x00020210 - 0xFFFF7FFF - - - BLOCK_CNT - 16-bit Block Count -- If the Host Version 4 Enable bit is set 0 or the 16-bit Block Count register is set to non-zero, the 16-bit Block Count register is selected. -- If the Host Version 4 Enable bit is set 1 and the 16-bit Block Count register is set to zero, the 32-bit Block Count register is selected. -Following are the values for BLOCK_CNT: -- 0x0: Stop Count -- 0x1: 1 Block -- 0x2: 2 Blocks -- . -- 0xFFFF: 65535 Blocks -Note: For Host Version 4 Enable = 0, this register must be set to 0000h before programming the 32-bit block count register when Auto CMD23 is enabled for non-DMA and ADMA modes. - 16 - 16 - read-write - - - SDMA_BUF_BDARY - SDMA Buffer Boundary -These bits specify the size of contiguous buffer in system memory. -The SDMA transfer waits at every boundary specified by these fields and the Host Controller generates the DMA interrupt to request the Host Driver to update the SDMA System Address register. -Values: -- 0x0 (BYTES_4K): 4K bytes SDMA Buffer Boundary -- 0x1 (BYTES_8K): 8K bytes SDMA Buffer Boundary -- 0x2 (BYTES_16K): 16K bytes SDMA Buffer Boundary -- 0x3 (BYTES_32K): 32K bytes SDMA Buffer Boundary -- 0x4 (BYTES_64K): 64K bytes SDMA Buffer Boundary -- 0x5 (BYTES_128K): 128K bytes SDMA Buffer Boundary -- 0x6 (BYTES_256K): 256K bytes SDMA Buffer Boundary -- 0x7 (BYTES_512K): 512K bytes SDMA Buffer Boundary - 12 - 3 - read-write - - - XFER_BLOCK_SIZE - Transfer Block Size -These bits specify the block size of data transfers. In case of memory, it is set to 512 bytes. It can be accessed only if no transaction is executing. -Read operations during transfers may return an invalid value, and write operations are ignored. Following are the values for XFER_BLOCK_SIZE: -- 0x1: 1 byte -- 0x2: 2 bytes -- 0x3: 3 bytes -- . -- 0x1FF: 511 byte -- 0x200: 512 byt es -- . -- 0x800: 2048 bytes -Note: This register must be programmed with a non-zero value for data transfer. - 0 - 12 - read-write - - - - - CMD_ARG - No description available - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - ARGUMNET - Command Argument -These bits specify the SD/eMMC command argument that is specified in bits 39-8 of the Command format. - 0 - 32 - read-write - - - - - CMD_XFER - No description available - 0xc - 32 - 0x00000000 - 0x3FFF01FF - - - CMD_INDEX - Command Index -These bits are set to the command number that is specified in bits 45-40 of the Command Format. - 24 - 6 - read-write - - - CMD_TYPE - Command Type -These bits indicate the command type. -Note: While issuing Abort CMD using CMD12/CMD52 or reset CMD using CMD0/CMD52, CMD_TYPE field shall be set to 0x3. -Values: -0x3 (ABORT_CMD): Abort -0x2 (RESUME_CMD): Resume -0x1 (SUSPEND_CMD): Suspend -0x0 (NORMAL_CMD): Normal - 22 - 2 - read-write - - - DATA_PRESENT_SEL - Data Present Select -This bit is set to 1 to indicate that data is present and that the data is transferred using the DAT line. This bit is set to 0 in the following instances: -Command using the CMD line -Command with no data transfer but using busy signal on the DAT[0] line -Resume Command -Values: -0x0 (NO_DATA): No Data Present -0x1 (DATA): Data Present - 21 - 1 - read-write - - - CMD_IDX_CHK_ENABLE - Command Index Check Enable -This bit enables the Host Controller to check the index field in the response to verify if it has the same value as the command index. -If the value is not the same, it is reported as a Command Index error. -Note: -Index Check enable must be set to 0 for the command with no response, R2 response, R3 response and R4 response. -For the tuning command, this bit must always be set to enable the index check. -Values: -0x0 (DISABLED): Disable -0x1 (ENABLED): Enable - 20 - 1 - read-write - - - CMD_CRC_CHK_ENABLE - Command CRC Check Enable -This bit enables the Host Controller to check the CRC field in the response. If an error is detected, it is reported as a Command CRC error. -Note: -CRC Check enable must be set to 0 for the command with no response, R3 response, and R4 response. -For the tuning command, this bit must always be set to 1 to enable the CRC check. -Values: -0x0 (DISABLED): Disable -0x1 (ENABLED): Enable - 19 - 1 - read-write - - - SUB_CMD_FLAG - Sub Command Flag -This bit distinguishes between a main command and a sub command. -Values: -0x0 (MAIN): Main Command -0x1 (SUB): Sub Command - 18 - 1 - read-write - - - RESP_TYPE_SELECT - Response Type Select -This bit indicates the type of response expected from the card. -Values: -0x0 (NO_RESP): No Response -0x1 (RESP_LEN_136): Response Length 136 -0x2 (RESP_LEN_48): Response Length 48 -0x3 (RESP_LEN_48B): Response Length 48; Check Busy after response - 16 - 2 - read-write - - - RESP_INT_DISABLE - Response Interrupt Disable -The Host Controller supports response check function to avoid overhead of response error check by the Host driver. -Response types of only R1 and R5 can be checked by the Controller. -If Host Driver checks the response error, set this bit to 0 and wait for Command Complete Interrupt and then check the response register. -If the Host Controller checks the response error, set this bit to 1 and set the Response Error Check Enable bit to 1. -The Command Complete Interrupt is disabled by this bit regardless of the Command Complete Signal Enable. -Note: During tuning (when the Execute Tuning bit in the Host Control2 register is set), the Command Complete Interrupt is not generated irrespective of the Response Interrupt Disable setting. -Values: -- 0x0 (ENABLED): Response Interrupt is enabled -- 0x1 (DISABLED): Response Interrupt is disabled - 8 - 1 - read-write - - - RESP_ERR_CHK_ENABLE - Response Error Check Enable -The Host Controller supports response check function to avoid overhead of response error check by Host driver. Response types of only R1 and R5 can be checked by the Controller. -If the Host Controller checks the response error, set this bit to 1 and set Response Interrupt Disable to 1. If an error is detected, the Response Error interrupt is generated in the Error Interrupt Status register. -Note: -- Response error check must not be enabled for any response type other than R1 and R5. -- Response check must not be enabled for the tuning command. -Values: -- 0x0 (DISABLED): Response Error Check is disabled -- 0x1 (ENABLED): Response Error Check is enabled - 7 - 1 - read-write - - - RESP_TYPE - Response Type R1/R5 -This bit selects either R1 or R5 as a response type when the Response Error Check is selected. -Error statuses checked in R1: -OUT_OF_RANGE -ADDRESS_ERROR -BLOCK_LEN_ERROR -WP_VIOLATION -CARD_IS_LOCKED -COM_CRC_ERROR -CARD_ECC_FAILED -CC_ERROR -ERROR -Response Flags checked in R5: -COM_CRC_ERROR -ERROR -FUNCTION_NUMBER -OUT_OF_RANGE -Values: -0x0 (RESP_R1): R1 (Memory) -0x1 (RESP_R5): R5 (SDIO) - 6 - 1 - read-write - - - MULTI_BLK_SEL - Multi/Single Block Select -This bit is set when issuing multiple-block transfer commands using the DAT line. If this bit is set to 0, it is not necessary to set the Block Count register. -Values: -0x0 (SINGLE): Single Block -0x1 (MULTI): Multiple Block - 5 - 1 - read-write - - - DATA_XFER_DIR - Data Transfer Direction Select -This bit defines the direction of DAT line data transfers. -This bit is set to 1 by the Host Driver to transfer data from the SD/eMMC card to the Host Controller and it is set to 0 for all other commands. -Values: -0x1 (READ): Read (Card to Host) -0x0 (WRITE): Write (Host to Card) - 4 - 1 - read-write - - - AUTO_CMD_ENABLE - Auto Command Enable -This field determines use of Auto Command functions. -Note: In SDIO, this field must be set as 00b (Auto Command Disabled). -Values: -0x0 (AUTO_CMD_DISABLED): Auto Command Disabled -0x1 (AUTO_CMD12_ENABLED): Auto CMD12 Enable -0x2 (AUTO_CMD23_ENABLED): Auto CMD23 Enable -0x3 (AUTO_CMD_AUTO_SEL): Auto CMD Auto Sel - 2 - 2 - read-write - - - BLOCK_COUNT_ENABLE - Block Count Enable -This bit is used to enable the Block Count register, which is relevant for multiple block transfers. -If this bit is set to 0, the Block Count register is disabled, which is useful in executing an infinite transfer. -The Host Driver must set this bit to 0 when ADMA is used. -Values: -0x1 (ENABLED): Enable -0x0 (DISABLED): Disable - 1 - 1 - read-write - - - DMA_ENABLE - DMA Enable -This bit enables the DMA functionality. If this bit is set to 1, a DMA operation begins when the Host Driver writes to the Command register. -You can select one of the DMA modes by using DMA Select in the Host Control 1 register. -Values: -0x1 (ENABLED): DMA Data transfer -0x0 (DISABLED): No data transfer or Non-DMA data transfer - 0 - 1 - read-write - - - - - 4 - 0x4 - RESP01,RESP23,RESP45,RESP67 - RESP[%s] - no description available - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - RESP01 - Command Response -These bits reflect 39-8 bits of SD/eMMC Response Field. -Note: For Auto CMD, the 32-bit response (bits 39-8 of the Response Field) is updated in the RESP[RESP67] register. - 0 - 32 - read-only - - - - - BUF_DATA - No description available - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - BUF_DATA - Buffer Data -These bits enable access to the Host Controller packet buffer. - 0 - 32 - read-write - - - - - PSTATE - No description available - 0x24 - 32 - 0x00000000 - 0x19FF0FFF - - - SUB_CMD_STAT - Sub Command Status -This bit is used to distinguish between a main command and a sub command status. -Values: -0x0 (FALSE): Main Command Status -0x1 (TRUE): Sub Command Status - 28 - 1 - read-only - - - CMD_ISSUE_ERR - Command Not Issued by Error -This bit is set if a command cannot be issued after setting the command register due to an error except the Auto CMD12 error. -Values: -0x0 (FALSE): No error for issuing a command -0x1 (TRUE): Command cannot be issued - 27 - 1 - read-only - - - CMD_LINE_LVL - Command-Line Signal Level -This bit is used to check the CMD line level to recover from errors and for debugging. These bits reflect the value of the sd_cmd_in signal. - 24 - 1 - read-only - - - DAT_3_0 - DAT[3:0] Line Signal Level -This bit is used to check the DAT line level to recover from errors and for debugging. These bits reflect the value of the sd_dat_in (lower nibble) signal. - 20 - 4 - read-only - - - WR_PROTECT_SW_LVL - Write Protect Switch Pin Level -This bit is supported only for memory and combo cards. This bit reflects the synchronized value of the card_write_prot signal. -Values: -0x0 (FALSE): Write protected -0x1 (TRUE): Write enabled - 19 - 1 - read-only - - - CARD_DETECT_PIN_LEVEL - Card Detect Pin Level -This bit reflects the inverse synchronized value of the card_detect_n signal. -Values: -0x0 (FALSE): No card present -0x1 (TRUE): Card Present - 18 - 1 - read-only - - - CARD_STABLE - Card Stable -This bit indicates the stability of the Card Detect Pin Level. A card is not detected if this bit is set to 1 and the value of the CARD_INSERTED bit is 0. -Values: -0x0 (FALSE): Reset or Debouncing -0x1 (TRUE): No Card or Inserted - 17 - 1 - read-only - - - CARD_INSERTED - Card Inserted -This bit indicates whether a card has been inserted. The Host Controller debounces this signal so that Host Driver need not wait for it to stabilize. -Values: -0x0 (FALSE): Reset, Debouncing, or No card -0x1 (TRUE): Card Inserted - 16 - 1 - read-only - - - BUF_RD_ENABLE - Buffer Read Enable -This bit is used for non-DMA transfers. This bit is set if valid data exists in the Host buffer. -Values: -0x0 (DISABLED): Read disable -0x1 (ENABLED): Read enable - 11 - 1 - read-only - - - BUF_WR_ENABLE - Buffer Write Enable -This bit is used for non-DMA transfers. This bit is set if space is available for writing data. -Values: -0x0 (DISABLED): Write disable -0x1 (ENABLED): Write enable - 10 - 1 - read-only - - - RD_XFER_ACTIVE - Read Transfer Active -This bit indicates whether a read transfer is active for SD/eMMC mode. -Values: -0x0 (INACTIVE): No valid data -0x1 (ACTIVE): Transferring data - 9 - 1 - read-only - - - WR_XFER_ACTIVE - Write Transfer Active -This status indicates whether a write transfer is active for SD/eMMC mode. -Values: -0x0 (INACTIVE): No valid data -0x1 (ACTIVE): Transferring data - 8 - 1 - read-only - - - DAT_7_4 - DAT[7:4] Line Signal Level -This bit is used to check the DAT line level to recover from errors and for debugging. These bits reflect the value of the sd_dat_in (upper nibble) signal. - 4 - 4 - read-only - - - RE_TUNE_REQ - Re-Tuning Request -SDXC does not generate retuning request. The software must maintain the Retuning timer. - 3 - 1 - read-only - - - DAT_LINE_ACTIVE - DAT Line Active ( -This bit indicates whether one of the DAT lines on the SD/eMMC bus is in use. -In the case of read transactions, this bit indicates whether a read transfer is executing on the SD/eMMC bus. -In the case of write transactions, this bit indicates whether a write transfer is executing on the SD/eMMC bus. -For a command with busy, this status indicates whether the command executing busy is executing on an SD or eMMC bus. -Values: -0x0 (INACTIVE): DAT Line Inactive -0x1 (ACTIVE): DAT Line Active - 2 - 1 - read-only - - - DAT_INHIBIT - Command Inhibit (DAT) -This bit is generated if either DAT line active or Read transfer active is set to 1. -If this bit is set to 0, it indicates that the Host Controller can issue subsequent SD/eMMC commands. -Values: -0x0 (READY): Can issue command which used DAT line -0x1 (NOT_READY): Cannot issue command which used DAT line - 1 - 1 - read-only - - - CMD_INHIBIT - Command Inhibit (CMD) -This bit indicates the following : -If this bit is set to 0, it indicates that the CMD line is not in use and the Host controller can issue an SD/eMMC command using the CMD line. -This bit is set when the command register is written. This bit is cleared when the command response is received. -This bit is not cleared by the response of auto CMD12/23 but cleared by the response of read/write command. -Values: -0x0 (READY): Host Controller is ready to issue a command -0x1 (NOT_READY): Host Controller is not ready to issue a command - 0 - 1 - read-only - - - - - PROT_CTRL - No description available - 0x28 - 32 - 0x00000000 - 0x070F0F3E - - - CARD_REMOVAL - Wakeup Event Enable on SD Card Removal -This bit enables wakeup event through Card Removal assertion in the Normal Interrupt Status register. -For the SDIO card, Wake Up Support (FN_WUS) in the Card Information Structure (CIS) register does not affect this bit. -Values: -0x0 (DISABLED): Disable -0x1 (ENABLED): Enable - 26 - 1 - read-write - - - CARD_INSERT - Wakeup Event Enable on SD Card Insertion -This bit enables wakeup event through Card Insertion assertion in the Normal Interrupt Status register. -FN_WUS (Wake Up Support) in CIS does not affect this bit. -Values: -0x0 (DISABLED): Disable -0x1 (ENABLED): Enable - 25 - 1 - read-write - - - CARD_INT - Wakeup Event Enable on Card Interrupt -This bit enables wakeup event through a Card Interrupt assertion in the Normal Interrupt Status register. -This bit can be set to 1 if FN_WUS (Wake Up Support) in CIS is set to 1. -Values: -0x0 (DISABLED): Disable -0x1 (ENABLED): Enable - 24 - 1 - read-write - - - INT_AT_BGAP - Interrupt At Block Gap -This bit is valid only in the 4-bit mode of an SDIO card and is used to select a sample point in the interrupt cycle. -Setting to 1 enables interrupt detection at the block gap for a multiple block transfer. -Values: -0x0 (DISABLE): Disabled -0x1 (ENABLE): Enabled - 19 - 1 - read-write - - - RD_WAIT_CTRL - Read Wait Control -This bit is used to enable the read wait protocol to stop read data using DAT[2] line if the card supports read wait. -Otherwise, the Host Controller has to stop the card clock to hold the read data. In UHS-II mode, Read Wait is disabled. -Values: -0x0 (DISABLE): Disable Read Wait Control -0x1 (ENABLE): Enable Read Wait Control - 18 - 1 - read-write - - - CONTINUE_REQ - Continue Request -This bit is used to restart the transaction, which was stopped using the Stop At Block Gap Request. -The Host Controller automatically clears this bit when the transaction restarts. -If stop at block gap request is set to 1, any write to this bit is ignored. -Values: -0x0 (NO_AFFECT): No Affect -0x1 (RESTART): Restart - 17 - 1 - read-write - - - STOP_BG_REQ - Stop At Block Gap Request -This bit is used to stop executing read and write transactions at the next block gap for non-DMA, SDMA, and ADMA transfers. -Values: -0x0 (XFER): Transfer -0x1 (STOP): Stop - 16 - 1 - read-write - - - SD_BUS_VOL_VDD1 - SD Bus Voltage Select for VDD1/eMMC Bus Voltage Select for VDD -These bits enable the Host Driver to select the voltage level for an SD/eMMC card. -Before setting this register, the Host Driver checks the Voltage Support bits in the Capabilities register. -If an unsupported voltage is selected, the Host System does not supply the SD Bus voltage. -The value set in this field is available on the SDXC output signal (sd_vdd1_sel), which is used by the voltage switching circuitry. -SD Bus Voltage Select options: -0x7 : 3.3V(Typical) -0x6 : 3.0V(Typical) -0x5 : 1.8V(Typical) for Embedded -0x4 : 0x0 - Reserved -eMMC Bus Voltage Select options: -0x7 : 3.3V(Typical) -0x6 : 1.8V(Typical) -0x5 : 1.2V(Typical) -0x4 : 0x0 - Reserved -Values: -0x7 (V_3_3): 3.3V (Typ.) -0x6 (V_3_0): 3.0V (Typ.) -0x5 (V_1_8): 1.8V (Typ.) for Embedded -0x4 (RSVD4): Reserved -0x3 (RSVD3): Reserved -0x2 (RSVD2): Reserved -0x1 (RSVD1): Reserved -0x0 (RSVD0): Reserved - 9 - 3 - read-write - - - SD_BUS_PWR_VDD1 - SD Bus Power for VDD1 -This bit enables VDD1 power of the card. -This setting is available on the sd_vdd1_on output of SDXC so that it can be used to control the VDD1 power supply of the card. -Before setting this bit, the SD Host Driver sets the SD Bus Voltage Select bit. If the Host Controller detects a No Card state, this bit is cleared. -In SD mode, if this bit is cleared, the Host Controller stops the SD Clock by clearing the SD_CLK_EN bit in the SYS_CTRL register. -Values: -0x0 (OFF): Power off -0x1 (ON): Power on - 8 - 1 - read-write - - - EXT_DAT_XFER - Extended Data Transfer Width -This bit controls 8-bit bus width mode of embedded device. -Values: -0x1 (EIGHT_BIT): 8-bit Bus Width -0x0 (DEFAULT): Bus Width is selected by the Data Transfer Width - 5 - 1 - read-write - - - DMA_SEL - DMA Select -This field is used to select the DMA type. -When Host Version 4 Enable is 1 in Host Control 2 register: -0x0 : SDMA is selected -0x1 : Reserved -0x2 : ADMA2 is selected -0x3 : ADMA2 or ADMA3 is selected -When Host Version 4 Enable is 0 in Host Control 2 register: -0x0 : SDMA is selected -0x1 : Reserved -0x2 : 32-bit Address ADMA2 is selected -0x3 : 64-bit Address ADMA2 is selected -Values: -0x0 (SDMA): SDMA is selected -0x1 (RSVD_BIT): Reserved -0x2 (ADMA2): ADMA2 is selected -0x3 (ADMA2_3): ADMA2 or ADMA3 is selected - 3 - 2 - read-write - - - HIGH_SPEED_EN - High Speed Enable -this bit is used to determine the selection of preset value for High Speed mode. -Before setting this bit, the Host Driver checks the High Speed Support in the Capabilities register. -Note: SDXC always outputs the sd_cmd_out and sd_dat_out lines at the rising edge of cclk_tx clock irrespective of this bit. -Values: -0x1 (HIGH_SPEED): High Speed mode -0x0 (NORMAL_SPEED): Normal Speed mode - 2 - 1 - read-write - - - DAT_XFER_WIDTH - Data Transfer Width -For SD/eMMC mode,this bit selects the data transfer width of the Host Controller. -The Host Driver sets it to match the data width of the SD/eMMC card. In UHS-II mode, this bit is irrelevant. -Values: -0x1 (FOUR_BIT): 4-bit mode -0x0 (ONE_BIT): 1-bit mode - 1 - 1 - read-write - - - - - SYS_CTRL - No description available - 0x2c - 32 - 0x00000000 - 0x070FFFEF - - - SW_RST_DAT - Software Reset For DAT line -This bit is used in SD/eMMC mode and it resets only a part of the data circuit and the DMA circuit is also reset. -The following registers and bits are cleared by this bit: -Buffer Data Port register --Buffer is cleared and initialized. -Present state register --Buffer Read Enable --Buffer Write Enable --Read Transfer Active --Write Transfer Active --DAT Line Active --Command Inhibit (DAT) -Block Gap Control register --Continue Request --Stop At Block Gap Request -Normal Interrupt status register --Buffer Read Ready --Buffer Write Ready --DMA Interrupt --Block Gap Event --Transfer Complete -In UHS-II mode, this bit shall be set to 0 -Values: -0x0 (FALSE): Work -0x1 (TRUE): Reset - 26 - 1 - read-write - - - SW_RST_CMD - Software Reset For CMD line -This bit resets only a part of the command circuit to be able to issue a command. -It bit is also used to initialize a UHS-II command circuit. -This reset is effective only for a command issuing circuit (including response error statuses related to Command Inhibit (CMD) control) and does not affect the data transfer circuit. -Host Controller can continue data transfer even after this reset is executed while handling subcommand-response errors. -The following registers and bits are cleared by this bit: -Present State register : Command Inhibit (CMD) bit -Normal Interrupt Status register : Command Complete bit -Error Interrupt Status : Response error statuses related to Command Inhibit (CMD) bit -Values: -0x0 (FALSE): Work -0x1 (TRUE): Reset - 25 - 1 - read-write - - - SW_RST_ALL - Software Reset For All -This reset affects the entire Host Controller except for the card detection circuit. -During its initialization, the Host Driver sets this bit to 1 to reset the Host Controller. -All registers are reset except the capabilities register. -If this bit is set to 1, the Host Driver must issue reset command and reinitialize the card. -Values: -0x0 (FALSE): Work -0x1 (TRUE): Reset - 24 - 1 - read-write - - - TOUT_CNT - Data Timeout Counter Value. -This value determines the interval by which DAT line timeouts are detected. -The Timeout clock frequency is generated by dividing the base clock TMCLK value by this value. -When setting this register, prevent inadvertent timeout events by clearing the Data Timeout Error Status Enable (in the Error Interrupt Status Enable register). -The values for these bits are: -0xF : Reserved -0xE : TMCLK x 2^27 -......... -0x1 : TMCLK x 2^14 -0x0 : TMCLK x 2^13 -Note: During a boot operating in an eMMC mode, an application must configure the boot data timeout value (approximately 1 sec) in this bit. - 16 - 4 - read-write - - - FREQ_SEL - SDCLK/RCLK Frequency Select -These bits are used to select the frequency of the SDCLK signal. -These bits depend on setting of Preset Value Enable in the Host Control 2 register. -If Preset Value Enable = 0, these bits are set by the Host Driver. -If Preset Value Enable = 1, these bits are automatically set to a value specified in one of the Preset Value register. -The value is reflected on the lower 8-bit of the card_clk_freq_selsignal. -10-bit Divided Clock Mode: -0x3FF : 1/2046 Divided clock -.......... -N : 1/2N Divided Clock -.......... -0x002 : 1/4 Divided Clock -0x001 : 1/2 Divided Clock -0x000 : Base clock (10MHz - 255 MHz) -Programmable Clock Mode : Enables the Host System to select a fine grain SD clock frequency: -0x3FF : Base clock * M /1024 -.......... -N-1 : Base clock * M /N -.......... -0x002 : Base clock * M /3 -0x001 : Base clock * M /2 -0x000 : Base clock * M - 8 - 8 - read-write - - - UPPER_FREQ_SEL - These bits specify the upper 2 bits of 10-bit SDCLK/RCLK Frequency Select control. -The value is reflected on the upper 2 bits of the card_clk_freq_sel signal. - 6 - 2 - read-write - - - CLK_GEN_SELECT - Clock Generator Select -This bit is used to select the clock generator mode in SDCLK/RCLK Frequency Select. -If Preset Value Enable = 0, this bit is set by the Host Driver. -If Preset Value Enable = 1, this bit is automatically set to a value specified in one of the Preset Value registers. -The value is reflected on the card_clk_gen_sel signal. -Values: -0x0 (FALSE): Divided Clock Mode -0x1 (TRUE): Programmable Clock Mode - 5 - 1 - read-write - - - PLL_ENABLE - PLL Enable -This bit is used to activate the PLL (applicable when Host Version 4 Enable = 1). -When Host Version 4 Enable = 0, INTERNAL_CLK_EN bit may be used to activate PLL. The value is reflected on the card_clk_en signal. -Note: If this bit is not used to to active the PLL when Host Version 4 Enable = 1, it is recommended to set this bit to '1' . -Values: -0x0 (FALSE): PLL is in low power mode -0x1 (TRUE): PLL is enabled - 3 - 1 - read-write - - - SD_CLK_EN - SD/eMMC Clock Enable -This bit stops the SDCLK or RCLK when set to 0. -The SDCLK/RCLK Frequency Select bit can be changed when this bit is set to 0. -The value is reflected on the clk2card_on pin. -Values: -0x0 (FALSE): Disable providing SDCLK/RCLK -0x1 (TRUE): Enable providing SDCLK/RCLK - 2 - 1 - read-write - - - INTERNAL_CLK_STABLE - Internal Clock Stable -This bit enables the Host Driver to check the clock stability twice after the Internal Clock Enable bit is set and after the PLL Enable bit is set. -This bit reflects the synchronized value of the intclk_stable signal after the Internal Clock Enable bit is set to 1, -and also reflects the synchronized value of the card_clk_stable signal after the PLL Enable bit is set to 1. -Values: -0x0 (FALSE): Not Ready -0x1 (TRUE): Ready - 1 - 1 - read-write - - - INTERNAL_CLK_EN - Internal Clock Enable -This bit is set to 0 when the Host Driver is not using the Host Controller or the Host Controller awaits a wakeup interrupt. -The Host Controller must stop its internal clock to enter a very low power state. -However, registers can still be read and written to. The value is reflected on the intclk_en signal. -Note: If this bit is not used to control the internal clock (base clock and master clock), it is recommended to set this bit to '1' . -Values: -0x0 (FALSE): Stop -0x1 (TRUE): Oscillate - 0 - 1 - read-write - - - - - INT_STAT - No description available - 0x30 - 32 - 0x00000000 - 0x1FFFF1FF - - - BOOT_ACK_ERR - Boot Acknowledgment Error -This bit is set when there is a timeout for boot acknowledgement or when detecting boot ack status having a value other than 010. This is applicable only when boot acknowledgement is expected in eMMC mode. -In SD/UHS-II mode, this bit is irrelevant. - 28 - 1 - read-write - - - RESP_ERR - Response Error -Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver during DMA execution. -If Response Error Check Enable is set to 1 in the Transfer Mode register, Host Controller Checks R1 or R5 response. If an error is detected in a response, this bit is set to 1.This is applicable in SD/eMMC mode. -Values: -0x0 (FALSE): No error -0x1 (TRUE): Error - 27 - 1 - read-write - - - TUNING_ERR - Tuning Error -This bit is set when an unrecoverable error is detected in a tuning circuit except during the tuning procedure -(occurrence of an error during tuning procedure is indicated by Sampling Clock Select in the Host Control 2 register). -By detecting Tuning Error, Host Driver needs to abort a command executing and perform tuning. -To reset tuning circuit, Sampling Clock Select is set to 0 before executing tuning procedure. -The Tuning Error is higher priority than the other error interrupts generated during data transfer. -By detecting Tuning Error, the Host Driver must discard data transferred by a current read/write command and retry data transfer after the Host Controller retrieved from the tuning circuit error. -This is applicable in SD/eMMC mode. -Values: -0x0 (FALSE): No error -0x1 (TRUE): Error - 26 - 1 - read-write - - - ADMA_ERR - ADMA Error -This bit is set when the Host Controller detects error during ADMA-based data transfer. The error could be due to following reasons: -Error response received from System bus (Master I/F) -ADMA3,ADMA2 Descriptors invalid -CQE Task or Transfer descriptors invalid -When the error occurs, the state of the ADMA is saved in the ADMA Error Status register. -In eMMC CQE mode: -The Host Controller generates this Interrupt when it detects an invalid descriptor data (Valid=0) at the ST_FDS state. -ADMA Error State in the ADMA Error Status indicates that an error has occurred in ST_FDS state. -The Host Driver may find that Valid bit is not set at the error descriptor. -Values: -0x0 (FALSE): No error -0x1 (TRUE): Error - 25 - 1 - read-write - - - AUTO_CMD_ERR - Auto CMD Error -This error status is used by Auto CMD12 and Auto CMD23 in SD/eMMC mode. -This bit is set when detecting that any of the bits D00 to D05 in Auto CMD Error Status register has changed from 0 to 1. -D07 is effective in case of Auto CMD12. Auto CMD Error Status register is valid while this bit is set to 1 and may be cleared by clearing of this bit. -Values: -0x0 (FALSE): No error -0x1 (TRUE): Error - 24 - 1 - read-write - - - CUR_LMT_ERR - Current Limit Error -By setting the SD Bus Power bit in the Power Control register, the Host Controller is requested to supply power for the SD Bus. -If the Host Controller supports the Current Limit function, it can be protected from an illegal card by stopping power supply to the card in which case this bit indicates a failure status. -A reading of 1 for this bit means that the Host Controller is not supplying power to the SD card due to some failure. -A reading of 0 for this bit means that the Host Controller is supplying power and no error has occurred. -The Host Controller may require some sampling time to detect the current limit. -SDXC Host Controller does not support this function, this bit is always set to 0. -Values: -0x0 (FALSE): No error -0x1 (TRUE): Power Fail - 23 - 1 - read-write - - - DATA_END_BIT_ERR - Data End Bit Error -This error occurs in SD/eMMC mode either when detecting 0 at the end bit position of read data that uses the DAT line or at the end bit position of the CRC status. -Values: -0x0 (FALSE): No error -0x1 (TRUE): Error - 22 - 1 - read-write - - - DATA_CRC_ERR - Data CRC Error -This error occurs in SD/eMMC mode when detecting CRC error when transferring read data which uses the DAT line, -when detecting the Write CRC status having a value of other than 010 or when write CRC status timeout. -Values: -0x0 (FALSE): No error -0x1 (TRUE): Error - 21 - 1 - read-write - - - DATA_TOUT_ERR - Data Timeout Error -This bit is set in SD/eMMC mode when detecting one of the following timeout conditions: -Busy timeout for R1b, R5b type -Busy timeout after Write CRC status -Write CRC Status timeout -Read Data timeout -Values: -0x0 (FALSE): No error -0x1 (TRUE): Time out - 20 - 1 - read-write - - - CMD_IDX_ERR - Command Index Error -This bit is set if a Command Index error occurs in the command respons in SD/eMMC mode. -Values: -0x0 (FALSE): No error -0x1 (TRUE): Error - 19 - 1 - read-write - - - CMD_END_BIT_ERR - Command End Bit Error -This bit is set when detecting that the end bit of a command response is 0 in SD/eMMC mode. -Values: -0x0 (FALSE): No error -0x1 (TRUE): End Bit error generated - 18 - 1 - read-write - - - CMD_CRC_ERR - Command CRC Error -Command CRC Error is generated in SD/eMMC mode for following two cases. -If a response is returned and the Command Timeout Error is set to 0 (indicating no timeout), this bit is set to 1 when detecting a CRC error in the command response. -The Host Controller detects a CMD line conflict by monitoring the CMD line when a command is issued. -If the Host Controller drives the CMD line to 1 level, -but detects 0 level on the CMD line at the next SD clock edge, then the Host Controller aborts the command (stop driving CMD line) and set this bit to 1. -The Command Timeout Error is also set to 1 to distinguish a CMD line conflict. -Values: -0x0 (FALSE): No error -0x1 (TRUE): CRC error generated - 17 - 1 - read-write - - - CMD_TOUT_ERR - Command Timeout Error -In SD/eMMC Mode,this bit is set only if no response is returned within 64 SD clock cycles from the end bit of the command. -If the Host Controller detects a CMD line conflict, along with Command CRC Error bit, this bit is set to 1, without waiting for 64 SD/eMMC card clock cycles. -Values: -0x0 (FALSE): No error -0x1 (TRUE): Time out - 16 - 1 - read-write - - - ERR_INTERRUPT - Error Interrupt -If any of the bits in the Error Interrupt Status register are set, then this bit is set. -Values: -0x0 (FALSE): No Error -0x1 (TRUE): Error - 15 - 1 - read-only - - - CQE_EVENT - Command Queuing Event -This status is set if Command Queuing/Crypto related event has occurred in eMMC/SD mode. Read CQHCI's CQIS/CRNQIS register for more details. -Values: -0x0 (FALSE): No Event -0x1 (TRUE): Command Queuing Event is detected - 14 - 1 - read-write - - - FX_EVENT - FX Event -This status is set when R[14] of response register is set to 1 and Response Type R1/R5 is set to 0 in Transfer Mode register. This interrupt is used with response check function. -Values: -0x0 (FALSE): No Event -0x1 (TRUE): FX Event is detected - 13 - 1 - read-only - - - RE_TUNE_EVENT - Re-tuning Event -This bit is set if the Re-Tuning Request changes from 0 to 1. Re-Tuning request is not supported. - 12 - 1 - read-only - - - CARD_INTERRUPT - Card Interrupt -This bit reflects the synchronized value of: -DAT[1] Interrupt Input for SD Mode -DAT[2] Interrupt Input for UHS-II Mode -Values: -0x0 (FALSE): No Card Interrupt -0x1 (TRUE): Generate Card Interrupt - 8 - 1 - read-only - - - CARD_REMOVAL - Card Removal -This bit is set if the Card Inserted in the Present State register changes from 1 to 0. -Values: -0x0 (FALSE): Card state stable or Debouncing -0x1 (TRUE): Card Removed - 7 - 1 - read-write - - - CARD_INSERTION - Card Insertion -This bit is set if the Card Inserted in the Present State register changes from 0 to 1. -Values: -0x0 (FALSE): Card state stable or Debouncing -0x1 (TRUE): Card Inserted - 6 - 1 - read-write - - - BUF_RD_READY - Buffer Read Ready -This bit is set if the Buffer Read Enable changes from 0 to 1. -Values: -0x0 (FALSE): Not ready to read buffer -0x1 (TRUE): Ready to read buffer - 5 - 1 - read-write - - - BUF_WR_READY - Buffer Write Ready -This bit is set if the Buffer Write Enable changes from 0 to 1. -Values: -0x0 (FALSE): Not ready to write buffer -0x1 (TRUE): Ready to write buffer - 4 - 1 - read-write - - - DMA_INTERRUPT - DMA Interrupt -This bit is set if the Host Controller detects the SDMA Buffer Boundary during transfer. -In case of ADMA, by setting the Int field in the descriptor table, the Host controller generates this interrupt. -This interrupt is not generated after a Transfer Complete. -Values: -0x0 (FALSE): No DMA Interrupt -0x1 (TRUE): DMA Interrupt is generated - 3 - 1 - read-write - - - BGAP_EVENT - Block Gap Event -This bit is set when both read/write transaction is stopped at block gap due to a Stop at Block Gap Request. -Values: -0x0 (FALSE): No Block Gap Event -0x1 (TRUE): Transaction stopped at block gap - 2 - 1 - read-write - - - XFER_COMPLETE - Transfer Complete -This bit is set when a read/write transfer and a command with status busy is completed. -Values: -0x0 (FALSE): Not complete -0x1 (TRUE): Command execution is completed - 1 - 1 - read-write - - - CMD_COMPLETE - Command Complete -In an SD/eMMC Mode, this bit is set when the end bit of a response except for Auto CMD12 and Auto CMD23. -This interrupt is not generated when the Response Interrupt Disable in Transfer Mode Register is set to 1. -Values: -0x0 (FALSE): No command complete -0x1 (TRUE): Command Complete - 0 - 1 - read-write - - - - - INT_STAT_EN - No description available - 0x34 - 32 - 0x00000000 - 0x1FFF71FF - - - BOOT_ACK_ERR_STAT_EN - Boot Acknowledgment Error (eMMC Mode only) -Setting this bit to 1 enables setting of Boot Acknowledgment Error in Error Interrupt Status register (INT_STAT). -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 28 - 1 - read-write - - - RESP_ERR_STAT_EN - Response Error Status Enable (SD Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 27 - 1 - read-write - - - TUNING_ERR_STAT_EN - Tuning Error Status Enable (UHS-I Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 26 - 1 - read-write - - - ADMA_ERR_STAT_EN - ADMA Error Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 25 - 1 - read-write - - - AUTO_CMD_ERR_STAT_EN - Auto CMD Error Status Enable (SD/eMMC Mode only). -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 24 - 1 - read-write - - - CUR_LMT_ERR_STAT_EN - Current Limit Error Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 23 - 1 - read-write - - - DATA_END_BIT_ERR_STAT_EN - Data End Bit Error Status Enable (SD/eMMC Mode only). -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 22 - 1 - read-write - - - DATA_CRC_ERR_STAT_EN - Data CRC Error Status Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 21 - 1 - read-write - - - DATA_TOUT_ERR_STAT_EN - Data Timeout Error Status Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 20 - 1 - read-write - - - CMD_IDX_ERR_STAT_EN - Command Index Error Status Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 19 - 1 - read-write - - - CMD_END_BIT_ERR_STAT_EN - Command End Bit Error Status Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 18 - 1 - read-write - - - CMD_CRC_ERR_STAT_EN - Command CRC Error Status Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 17 - 1 - read-write - - - CMD_TOUT_ERR_STAT_EN - Command Timeout Error Status Enable (SD/eMMC Mode only). -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 16 - 1 - read-write - - - CQE_EVENT_STAT_EN - CQE Event Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 14 - 1 - read-write - - - FX_EVENT_STAT_EN - FX Event Status Enable -This bit is added from Version 4.10. -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 13 - 1 - read-write - - - RE_TUNE_EVENT_STAT_EN - Re-Tuning Event (UHS-I only) Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 12 - 1 - read-write - - - CARD_INTERRUPT_STAT_EN - Card Interrupt Status Enable -If this bit is set to 0, the Host Controller clears the interrupt request to the System. -The Card Interrupt detection is stopped when this bit is cleared and restarted when this bit is set to 1. -The Host Driver may clear the Card Interrupt Status Enable before servicing the Card Interrupt and may set this bit again after all interrupt requests from the card are cleared to prevent inadvertent interrupts. -By setting this bit to 0, interrupt input must be masked by implementation so that the interrupt input is not affected by external signal in any state (for example, floating). -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 8 - 1 - read-write - - - CARD_REMOVAL_STAT_EN - Card Removal Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 7 - 1 - read-write - - - CARD_INSERTION_STAT_EN - Card Insertion Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 6 - 1 - read-write - - - BUF_RD_READY_STAT_EN - Buffer Read Ready Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 5 - 1 - read-write - - - BUF_WR_READY_STAT_EN - Buffer Write Ready Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 4 - 1 - read-write - - - DMA_INTERRUPT_STAT_EN - DMA Interrupt Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 3 - 1 - read-write - - - BGAP_EVENT_STAT_EN - Block Gap Event Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 2 - 1 - read-write - - - XFER_COMPLETE_STAT_EN - Transfer Complete Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 1 - 1 - read-write - - - CMD_COMPLETE_STAT_EN - Command Complete Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 0 - 1 - read-write - - - - - INT_SIGNAL_EN - No description available - 0x38 - 32 - 0x00000000 - 0x1FFF71FF - - - BOOT_ACK_ERR_SIGNAL_EN - Boot Acknowledgment Error (eMMC Mode only). -Setting this bit to 1 enables generating interrupt signal when Boot Acknowledgment Error in Error Interrupt Status register is set. -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 28 - 1 - read-write - - - RESP_ERR_SIGNAL_EN - Response Error Signal Enable (SD Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 27 - 1 - read-write - - - TUNING_ERR_SIGNAL_EN - Tuning Error Signal Enable (UHS-I Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 26 - 1 - read-write - - - ADMA_ERR_SIGNAL_EN - ADMA Error Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 25 - 1 - read-write - - - AUTO_CMD_ERR_SIGNAL_EN - Auto CMD Error Signal Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 24 - 1 - read-write - - - CUR_LMT_ERR_SIGNAL_EN - Current Limit Error Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 23 - 1 - read-write - - - DATA_END_BIT_ERR_SIGNAL_EN - Data End Bit Error Signal Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 22 - 1 - read-write - - - DATA_CRC_ERR_SIGNAL_EN - Data CRC Error Signal Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 21 - 1 - read-write - - - DATA_TOUT_ERR_SIGNAL_EN - Data Timeout Error Signal Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 20 - 1 - read-write - - - CMD_IDX_ERR_SIGNAL_EN - Command Index Error Signal Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): No error -0x1 (TRUE): Error - 19 - 1 - read-write - - - CMD_END_BIT_ERR_SIGNAL_EN - Command End Bit Error Signal Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 18 - 1 - read-write - - - CMD_CRC_ERR_SIGNAL_EN - Command CRC Error Signal Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 17 - 1 - read-write - - - CMD_TOUT_ERR_SIGNAL_EN - Command Timeout Error Signal Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 16 - 1 - read-write - - - CQE_EVENT_SIGNAL_EN - Command Queuing Engine Event Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 14 - 1 - read-write - - - FX_EVENT_SIGNAL_EN - FX Event Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 13 - 1 - read-write - - - RE_TUNE_EVENT_SIGNAL_EN - Re-Tuning Event (UHS-I only) Signal Enable. -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 12 - 1 - read-write - - - CARD_INTERRUPT_SIGNAL_EN - Card Interrupt Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 8 - 1 - read-write - - - CARD_REMOVAL_SIGNAL_EN - Card Removal Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 7 - 1 - read-write - - - CARD_INSERTION_SIGNAL_EN - Card Insertion Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 6 - 1 - read-write - - - BUF_RD_READY_SIGNAL_EN - Buffer Read Ready Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 5 - 1 - read-write - - - BUF_WR_READY_SIGNAL_EN - Buffer Write Ready Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 4 - 1 - read-write - - - DMA_INTERRUPT_SIGNAL_EN - DMA Interrupt Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 3 - 1 - read-write - - - BGAP_EVENT_SIGNAL_EN - Block Gap Event Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 2 - 1 - read-write - - - XFER_COMPLETE_SIGNAL_EN - Transfer Complete Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 1 - 1 - read-write - - - CMD_COMPLETE_SIGNAL_EN - Command Complete Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 0 - 1 - read-write - - - - - AC_HOST_CTRL - No description available - 0x3c - 32 - 0x00000000 - 0xDCCF00BF - - - PRESET_VAL_ENABLE - Preset Value Enable -This bit enables automatic selection of SDCLK frequency and Driver strength Preset Value registers. -When Preset Value Enable is set, SDCLK frequency generation (Frequency Select and Clock Generator Select) and the driver strength selection are performed by the controller. -These values are selected from set of Preset Value registers based on selected speed mode. -Values: -0x0 (FALSE): SDCLK and Driver Strength are controlled by Host Driver -0x1 (TRUE): Automatic Selection by Preset Value are Enabled - 31 - 1 - read-write - - - ASYNC_INT_ENABLE - Asynchronous Interrupt Enable -This bit can be set if a card supports asynchronous interrupts and Asynchronous Interrupt Support is set to 1 in the Capabilities register. -Values: -0x0 (FALSE): Disabled -0x1 (TRUE): Enabled - 30 - 1 - read-write - - - HOST_VER4_ENABLE - Host Version 4 Enable -This bit selects either Version 3.00 compatible mode or Version 4 mode. -Functions of following fields are modified for Host Version 4 mode: -SDMA Address: SDMA uses ADMA System Address (05Fh-058h) instead of SDMA System Address register (003h-000h) -ADMA2/ADMA3 selection: ADMA3 is selected by DMA select in Host Control 1 register -64-bit ADMA Descriptor Size: 128-bit descriptor is used instead of 96-bit descriptor when 64-bit Addressing is set to 1 -Selection of 32-bit/64-bit System Addressing: Either 32-bit or 64-bit system addressing is selected by 64-bit Addressing bit in this register -32-bit Block Count: SDMA System Address register (003h-000h) is modified to 32-bit Block Count register -Note: It is recommended not to program ADMA3 Integrated Descriptor Address registers, -UHS-II registers and Command Queuing registers (if applicable) while operating in Host version less than 4 mode (Host Version 4 Enable = 0). -Values: -0x0 (FALSE): Version 3.00 compatible mode -0x1 (TRUE): Version 4 mode - 28 - 1 - read-write - - - CMD23_ENABLE - CMD23 Enable -If the card supports CMD23, this bit is set to 1. This bit is used to select Auto CMD23 or Auto CMD12 for ADMA3 data transfer. -Values: -0x0 (FALSE): Auto CMD23 is disabled -0x1 (TRUE): Auto CMD23 is enabled - 27 - 1 - read-write - - - ADMA2_LEN_MODE - ADMA2 Length Mode -This bit selects ADMA2 Length mode to be either 16-bit or 26-bit. -Values: -0x0 (FALSE): 16-bit Data Length Mode -0x1 (TRUE): 26-bit Data Length Mode - 26 - 1 - read-write - - - SAMPLE_CLK_SEL - Sampling Clock Select -This bit is used by the Host Controller to select the sampling clock in SD/eMMC mode to receive CMD and DAT. -This bit is set by the tuning procedure and is valid after the completion of tuning (when Execute Tuning is cleared). -Setting this bit to 1 means that tuning is completed successfully and setting this bit to 0 means that tuning has failed. -The value is reflected on the sample_cclk_sel pin. -Values: -0x0 (FALSE): Fixed clock is used to sample data -0x1 (TRUE): Tuned clock is used to sample data - 23 - 1 - read-write - - - EXEC_TUNING - Execute Tuning -This bit is set to 1 to start the tuning procedure in UHS-I/eMMC speed modes and this bit is automatically cleared when tuning procedure is completed. -Values: -0x0 (FALSE): Not Tuned or Tuning completed -0x1 (TRUE): Execute Tuning - 22 - 1 - read-write - - - SIGNALING_EN - 1.8V Signaling Enable -This bit controls voltage regulator for I/O cell in UHS-I/eMMC speed modes. -Setting this bit from 0 to 1 starts changing the signal voltage from 3.3V to 1.8V. -Host Controller clears this bit if switching to 1.8 signaling fails. The value is reflected on the uhs1_swvolt_en pin. -Note: This bit must be set for all UHS-I speed modes (SDR12/SDR25/SDR50/SDR104/DDR50). -Values: -0x0 (V_3_3): 3.3V Signalling -0x1 (V_1_8): 1.8V Signalling - 19 - 1 - read-write - - - UHS_MODE_SEL - UHS Mode/eMMC Speed Mode Select -These bits are used to select UHS mode in the SD mode of operation. In eMMC mode, these bits are used to select eMMC Speed mode. -UHS Mode (SD/UHS-II mode only): -0x0 (SDR12): SDR12/Legacy -0x1 (SDR25): SDR25/High Speed SDR -0x2 (SDR50): SDR50 -0x3 (SDR104): SDR104/HS200 -0x4 (DDR50): DDR50/High Speed DDR -0x5 (RSVD5): Reserved -0x6 (RSVD6): Reserved -0x7 (UHS2): UHS-II/HS400 -eMMC Speed Mode (eMMC mode only): -0x0: Legacy -0x1: High Speed SDR -0x2: Reserved -0x3: HS200 -0x4: High Speed DDR -0x5: Reserved -0x6: Reserved -0x7: HS400 - 16 - 3 - read-write - - - CMD_NOT_ISSUED_AUTO_CMD12 - Command Not Issued By Auto CMD12 Error -If this bit is set to 1, CMD_wo_DAT is not executed due to an Auto CMD12 Error (D04-D01) in this register. -This bit is set to 0 when Auto CMD Error is generated by Auto CMD23. -Values: -0x1 (TRUE): Not Issued -0x0 (FALSE): No Error - 7 - 1 - read-only - - - AUTO_CMD_RESP_ERR - Auto CMD Response Error -This bit is set when Response Error Check Enable in the Transfer Mode register is set to 1 and an error is detected in R1 response of either Auto CMD12 or CMD13. -This status is ignored if any bit between D00 to D04 is set to 1. -Values: -0x1 (TRUE): Error -0x0 (FALSE): No Error - 5 - 1 - read-only - - - AUTO_CMD_IDX_ERR - Auto CMD Index Error -This bit is set if the command index error occurs in response to a command. -Values: -0x1 (TRUE): Error -0x0 (FALSE): No Error - 4 - 1 - read-only - - - AUTO_CMD_EBIT_ERR - Auto CMD End Bit Error -This bit is set when detecting that the end bit of command response is 0. -Values: -0x1 (TRUE): End Bit Error Generated -0x0 (FALSE): No Error - 3 - 1 - read-only - - - AUTO_CMD_CRC_ERR - Auto CMD CRC Error -This bit is set when detecting a CRC error in the command response. -Values: -0x1 (TRUE): CRC Error Generated -0x0 (FALSE): No Error - 2 - 1 - read-only - - - AUTO_CMD_TOUT_ERR - Auto CMD Timeout Error -This bit is set if no response is returned with 64 SDCLK cycles from the end bit of the command. -If this bit is set to 1, error status bits (D04-D01) are meaningless. -Values: -0x1 (TRUE): Time out -0x0 (FALSE): No Error - 1 - 1 - read-only - - - AUTO_CMD12_NOT_EXEC - Auto CMD12 Not Executed -If multiple memory block data transfer is not started due to a command error, this bit is not set because it is not necessary to issue an Auto CMD12. -Setting this bit to 1 means that the Host Controller cannot issue Auto CMD12 to stop multiple memory block data transfer, due to some error. - If this bit is set to 1, error status bits (D04-D01) is meaningless. -This bit is set to 0 when Auto CMD Error is generated by Auto CMD23. -Values: -0x1 (TRUE): Not Executed -0x0 (FALSE): Executed - 0 - 1 - read-only - - - - - CAPABILITIES1 - No description available - 0x40 - 32 - 0x00000000 - 0xE7EFFFBF - - - SLOT_TYPE_R - Slot Type -These bits indicate usage of a slot by a specific Host System. -Values: -0x0 (REMOVABLE_SLOT): Removable Card Slot -0x1 (EMBEDDED_SLOT): Embedded Slot for one Device -0x2 (SHARED_SLOT): Shared Bus Slot (SD mode) -0x3 (UHS2_EMBEDDED_SLOT): UHS-II Multiple Embedded Devices - 30 - 2 - read-only - - - ASYNC_INT_SUPPORT - Asynchronous Interrupt Support (SD Mode only) -Values: -0x0 (FALSE): Asynchronous Interrupt Not Supported -0x1 (TRUE): Asynchronous Interrupt Supported - 29 - 1 - read-only - - - VOLT_18 - Voltage Support for 1.8V -Values: -0x0 (FALSE): 1.8V Not Supported -0x1 (TRUE): 1.8V Supported - 26 - 1 - read-only - - - VOLT_30 - Voltage Support for SD 3.0V or Embedded 1.2V -Values: -0x0 (FALSE): SD 3.0V or Embedded 1.2V Not Supported -0x1 (TRUE): SD 3.0V or Embedded Supported - 25 - 1 - read-only - - - VOLT_33 - Voltage Support for 3.3V -Values: -0x0 (FALSE): 3.3V Not Supported -0x1 (TRUE): 3.3V Supported - 24 - 1 - read-only - - - SUS_RES_SUPPORT - Suspense/Resume Support -This bit indicates whether the Host Controller supports Suspend/Resume functionality. -If this bit is 0, the Host Driver does not issue either Suspend or Resume commands because the Suspend and Resume mechanism is not supported. -Values: -0x0 (FALSE): Not Supported -0x1 (TRUE): Supported - 23 - 1 - read-only - - - SDMA_SUPPORT - SDMA Support -This bit indicates whether the Host Controller is capable of using SDMA to transfer data between the system memory and the Host Controller directly. -Values: -0x0 (FALSE): SDMA not Supported -0x1 (TRUE): SDMA Supported - 22 - 1 - read-only - - - HIGH_SPEED_SUPPORT - High Speed Support -This bit indicates whether the Host Controller and the Host System supports High Speed mode and they can supply the SD Clock frequency from 25 MHz to 50 MHz. -Values: -0x0 (FALSE): High Speed not Supported -0x1 (TRUE): High Speed Supported - 21 - 1 - read-only - - - ADMA2_SUPPORT - ADMA2 Support -This bit indicates whether the Host Controller is capable of using ADMA2. -Values: -0x0 (FALSE): ADMA2 not Supported -0x1 (TRUE): ADMA2 Supported - 19 - 1 - read-only - - - EMBEDDED_8_BIT - 8-bit Support for Embedded Device -This bit indicates whether the Host Controller is capable of using an 8-bit bus width mode. This bit is not effective when the Slot Type is set to 10b. -Values: -0x0 (FALSE): 8-bit Bus Width not Supported -0x1 (TRUE): 8-bit Bus Width Supported - 18 - 1 - read-only - - - MAX_BLK_LEN - Maximum Block Length -This bit indicates the maximum block size that the Host driver can read and write to the buffer in the Host Controller. -The buffer transfers this block size without wait cycles. The transfer block length is always 512 bytes for the SD Memory irrespective of this bit -Values: -0x0 (ZERO): 512 Byte -0x1 (ONE): 1024 Byte -0x2 (TWO): 2048 Byte -0x3 (THREE): Reserved - 16 - 2 - read-only - - - BASE_CLK_FREQ - Base Clock Frequency for SD clock -These bits indicate the base (maximum) clock frequency for the SD Clock. The definition of these bits depend on the Host Controller Version. -6-Bit Base Clock Frequency: This mode is supported by the Host Controller version 1.00 and 2.00. -The upper 2 bits are not effective and are always 0. The unit values are 1 MHz. The supported clock range is 10 MHz to 63 MHz. --0x00 : Get information through another method --0x01 : 1 MHz --0x02 : 2 MHz --............. --0x3F : 63 MHz --0x40-0xFF : Not Supported -8-Bit Base Clock Frequency: This mode is supported by the Host Controller version 3.00. The unit values are 1 MHz. The supported clock range is 10 MHz to 255 MHz. --0x00 : Get information through another method --0x01 : 1 MHz --0x02 : 2 MHz --............ --0xFF : 255 MHz -If the frequency is 16.5 MHz, the larger value is set to 0001001b (17 MHz) because the Host Driver uses this value to calculate the clock divider value and it does not exceed the upper limit of the SD Clock frequency. -If these bits are all 0, the Host system has to get information using a different method. - 8 - 8 - read-only - - - TOUT_CLK_UNIT - Timeout Clock Unit -This bit shows the unit of base clock frequency used to detect Data TImeout Error. -Values: -0x0 (KHZ): KHz -0x1 (MHZ): MHz - 7 - 1 - read-only - - - TOUT_CLK_FREQ - Timeout Clock Frequency -This bit shows the base clock frequency used to detect Data Timeout Error. The Timeout Clock unit defines the unit of timeout clock frequency. It can be KHz or MHz. -0x00 : Get information through another method -0x01 : 1KHz / 1MHz -0x02 : 2KHz / 2MHz -0x03 : 3KHz / 3MHz - ........... -0x3F : 63KHz / 63MHz - 0 - 6 - read-only - - - - - CAPABILITIES2 - No description available - 0x44 - 32 - 0x00000000 - 0x18FFEF7F - - - VDD2_18V_SUPPORT - 1.8V VDD2 Support -This bit indicates support of VDD2 for the Host System. -0x0 (FALSE): 1.8V VDD2 is not Supported -0x1 (TRUE): 1.8V VDD2 is Supported - 28 - 1 - read-only - - - ADMA3_SUPPORT - ADMA3 Support -This bit indicates whether the Host Controller is capable of using ADMA3. -Values: -0x0 (FALSE): ADMA3 not Supported -0x1 (TRUE): ADMA3 Supported - 27 - 1 - read-only - - - CLK_MUL - Clock Multiplier -These bits indicate the clock multiplier of the programmable clock generator. Setting these bits to 0 means that the Host Controller does not support a programmable clock generator. -0x0: Clock Multiplier is not Supported -0x1: Clock Multiplier M = 2 -0x2: Clock Multiplier M = 3 - ......... -0xFF: Clock Multiplier M = 256 - 16 - 8 - read-only - - - RE_TUNING_MODES - Re-Tuning Modes (UHS-I only) -These bits select the re-tuning method and limit the maximum data length. -Values: -0x0 (MODE1): Timer -0x1 (MODE2): Timer and Re-Tuning Request (Not supported) -0x2 (MODE3): Auto Re-Tuning (for transfer) -0x3 (RSVD_MODE): Reserved - 14 - 2 - read-only - - - USE_TUNING_SDR50 - Use Tuning for SDR50 (UHS-I only) -Values: -0x0 (ZERO): SDR50 does not require tuning -0x1 (ONE): SDR50 requires tuning - 13 - 1 - read-only - - - RETUNE_CNT - Timer Count for Re-Tuning (UHS-I only) -0x0: Re-Tuning Timer disabled -0x1: 1 seconds -0x2: 2 seconds -0x3: 4 seconds - ........ -0xB: 1024 seconds -0xC: Reserved -0xD: Reserved -0xE: Reserved -0xF: Get information from other source - 8 - 4 - read-only - - - DRV_TYPED - Driver Type D Support (UHS-I only) -This bit indicates support of Driver Type D for 1.8 Signaling. -Values: -0x0 (FALSE): Driver Type D is not supported -0x1 (TRUE): Driver Type D is supported - 6 - 1 - read-only - - - DRV_TYPEC - Driver Type C Support (UHS-I only) -This bit indicates support of Driver Type C for 1.8 Signaling. -Values: -0x0 (FALSE): Driver Type C is not supported -0x1 (TRUE): Driver Type C is supported - 5 - 1 - read-only - - - DRV_TYPEA - Driver Type A Support (UHS-I only) -This bit indicates support of Driver Type A for 1.8 Signaling. -Values: -0x0 (FALSE): Driver Type A is not supported -0x1 (TRUE): Driver Type A is supported - 4 - 1 - read-only - - - UHS2_SUPPORT - UHS-II Support (UHS-II only) -This bit indicates whether Host Controller supports UHS-II. -Values: -0x0 (FALSE): UHS-II is not supported -0x1 (TRUE): UHS-II is supported - 3 - 1 - read-only - - - DDR50_SUPPORT - DDR50 Support (UHS-I only) -Values: -0x0 (FALSE): DDR50 is not supported -0x1 (TRUE): DDR50 is supported - 2 - 1 - read-only - - - SDR104_SUPPORT - SDR104 Support (UHS-I only) -This bit mentions that SDR104 requires tuning. -Values: -0x0 (FALSE): SDR104 is not supported -0x1 (TRUE): SDR104 is supported - 1 - 1 - read-only - - - SDR50_SUPPORT - SDR50 Support (UHS-I only) -This bit indicates that SDR50 is supported. The bit 13 (USE_TUNING_SDR50) indicates whether SDR50 requires tuning or not. -Values: -0x0 (FALSE): SDR50 is not supported -0x1 (TRUE): SDR50 is supported - 0 - 1 - read-only - - - - - CURR_CAPABILITIES1 - No description available - 0x48 - 32 - 0x00000000 - 0x00FFFFFF - - - MAX_CUR_18V - Maximum Current for 1.8V -This bit specifies the Maximum Current for 1.8V VDD1 power supply for the card. -0: Get information through another method -1: 4mA -2: 8mA -3: 13mA -....... -255: 1020mA - 16 - 8 - read-only - - - MAX_CUR_30V - Maximum Current for 3.0V -This bit specifies the Maximum Current for 3.0V VDD1 power supply for the card. -0: Get information through another method -1: 4mA -2: 8mA -3: 13mA -....... -255: 1020mA - 8 - 8 - read-only - - - MAX_CUR_33V - Maximum Current for 3.3V -This bit specifies the Maximum Current for 3.3V VDD1 power supply for the card. -0: Get information through another method -1: 4mA -2: 8mA -3: 13mA -....... -255: 1020mA - 0 - 8 - read-only - - - - - CURR_CAPABILITIES2 - No description available - 0x4c - 32 - 0x00000000 - 0x000000FF - - - MAX_CUR_VDD2_18V - Maximum Current for 1.8V VDD2 -This bit specifies the Maximum Current for 1.8V VDD2 power supply for the UHS-II card. -0: Get information through another method -1: 4mA -2: 8mA -3: 13mA -....... -255: 1020mA - 0 - 8 - read-only - - - - - FORCE_EVENT - No description available - 0x50 - 32 - 0x00000000 - 0x1FFF00BF - - - FORCE_BOOT_ACK_ERR - Force Event for Boot Ack error -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Boot ack Error Status is set - 28 - 1 - write-only - - - FORCE_RESP_ERR - Force Event for Response Error (SD Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Response Error Status is set - 27 - 1 - write-only - - - FORCE_TUNING_ERR - Force Event for Tuning Error (UHS-I Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Tuning Error Status is set - 26 - 1 - write-only - - - FORCE_ADMA_ERR - Force Event for ADMA Error -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): ADMA Error Status is set - 25 - 1 - write-only - - - FORCE_AUTO_CMD_ERR - Force Event for Auto CMD Error (SD/eMMC Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Auto CMD Error Status is set - 24 - 1 - write-only - - - FORCE_CUR_LMT_ERR - Force Event for Current Limit Error -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Current Limit Error Status is set - 23 - 1 - write-only - - - FORCE_DATA_END_BIT_ERR - Force Event for Data End Bit Error (SD/eMMC Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Data End Bit Error Status is set - 22 - 1 - write-only - - - FORCE_DATA_CRC_ERR - Force Event for Data CRC Error (SD/eMMC Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Data CRC Error Status is set - 21 - 1 - write-only - - - FORCE_DATA_TOUT_ERR - Force Event for Data Timeout Error (SD/eMMC Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Data Timeout Error Status is set - 20 - 1 - write-only - - - FORCE_CMD_IDX_ERR - Force Event for Command Index Error (SD/eMMC Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Command Index Error Status is set - 19 - 1 - write-only - - - FORCE_CMD_END_BIT_ERR - Force Event for Command End Bit Error (SD/eMMC Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Command End Bit Error Status is set - 18 - 1 - write-only - - - FORCE_CMD_CRC_ERR - Force Event for Command CRC Error (SD/eMMC Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Command CRC Error Status is set - 17 - 1 - write-only - - - FORCE_CMD_TOUT_ERR - Force Event for Command Timeout Error (SD/eMMC Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Command Timeout Error Status is set - 16 - 1 - write-only - - - FORCE_CMD_NOT_ISSUED_AUTO_CMD12 - Force Event for Command Not Issued By Auto CMD12 Error -Values: -0x1 (TRUE): Command Not Issued By Auto CMD12 Error Status is set -0x0 (FALSE): Not Affected - 7 - 1 - write-only - - - FORCE_AUTO_CMD_RESP_ERR - Force Event for Auto CMD Response Error -Values: -0x1 (TRUE): Auto CMD Response Error Status is set -0x0 (FALSE): Not Affected - 5 - 1 - write-only - - - FORCE_AUTO_CMD_IDX_ERR - Force Event for Auto CMD Index Error -Values: -0x1 (TRUE): Auto CMD Index Error Status is set -0x0 (FALSE): Not Affected - 4 - 1 - write-only - - - FORCE_AUTO_CMD_EBIT_ERR - Force Event for Auto CMD End Bit Error -Values: -0x1 (TRUE): Auto CMD End Bit Error Status is set -0x0 (FALSE): Not Affected - 3 - 1 - write-only - - - FORCE_AUTO_CMD_CRC_ERR - Force Event for Auto CMD CRC Error -Values: -0x1 (TRUE): Auto CMD CRC Error Status is set -0x0 (FALSE): Not Affected - 2 - 1 - write-only - - - FORCE_AUTO_CMD_TOUT_ERR - Force Event for Auto CMD Timeout Error -Values: -0x1 (TRUE): Auto CMD Timeout Error Status is set -0x0 (FALSE): Not Affected - 1 - 1 - write-only - - - FORCE_AUTO_CMD12_NOT_EXEC - Force Event for Auto CMD12 Not Executed -Values: -0x1 (TRUE): Auto CMD12 Not Executed Status is set -0x0 (FALSE): Not Affected - 0 - 1 - write-only - - - - - ADMA_ERR_STAT - No description available - 0x54 - 32 - 0x00000000 - 0x00000007 - - - ADMA_LEN_ERR - ADMA Length Mismatch Error States -This error occurs in the following instances: -While the Block Count Enable is being set, the total data length specified by the Descriptor table is different from that specified by the Block Count and Block Length -When the total data length cannot be divided by the block length -Values: -0x0 (NO_ERR): No Error -0x1 (ERROR): Error - 2 - 1 - read-only - - - ADMA_ERR_STATES - ADMA Error States -These bits indicate the state of ADMA when an error occurs during ADMA data transfer. -Values: -0x0 (ST_STOP): Stop DMA - SYS_ADR register points to a location next to the error descriptor -0x1 (ST_FDS): Fetch Descriptor - SYS_ADR register points to the error descriptor -0x2 (UNUSED): Never set this state -0x3 (ST_TFR): Transfer Data - SYS_ADR register points to a location next to the error descriptor - 0 - 2 - read-only - - - - - ADMA_SYS_ADDR - No description available - 0x58 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADMA_SA - ADMA System Address -These bits indicate the lower 32 bits of the ADMA system address. -SDMA: If Host Version 4 Enable is set to 1, this register stores the system address of the data location -ADMA2: This register stores the byte address of the executing command of the descriptor table -ADMA3: This register is set by ADMA3. ADMA2 increments the address of this register that points to the next line, every time a Descriptor line is fetched. - 0 - 32 - read-write - - - - - 11 - 0x2 - INIT,DS,HS,SDR12,SDR25,SDR50,SDR104,DDR50,rsv8,rsv9,UHS2 - PRESET[%s] - no description available - 0x60 - 16 - 0x0000 - 0x07FF - - - CLK_GEN_SEL_VAL - Clock Generator Select Value -This bit is effective when the Host Controller supports a programmable clock generator. -Values: -0x0 (FALSE): Host Controller Ver2.0 Compatible Clock Generator -0x1 (PROG): Programmable Clock Generator - 10 - 1 - read-only - - - FREQ_SEL_VAL - SDCLK/RCLK Frequency Select Value -10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System. - 0 - 10 - read-only - - - - - ADMA_ID_ADDR - No description available - 0x78 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADMA_ID_ADDR - ADMA Integrated Descriptor Address -These bits indicate the lower 32-bit of the ADMA Integrated Descriptor address. -The start address of Integrated Descriptor is set to these register bits. -The ADMA3 fetches one Descriptor Address and increments these bits to indicate the next Descriptor address. - 0 - 32 - read-write - - - - - P_EMBEDDED_CNTRL - No description available - 0xe6 - 16 - 0x0000 - 0x0FFF - - - REG_OFFSET_ADDR - Offset Address of Embedded Control register. - 0 - 12 - read-only - - - - - P_VENDOR_SPECIFIC_AREA - No description available - 0xe8 - 16 - 0x0000 - 0x0FFF - - - REG_OFFSET_ADDR - Base offset Address for Vendor-Specific registers. - 0 - 12 - read-only - - - - - P_VENDOR2_SPECIFIC_AREA - No description available - 0xea - 16 - 0x0000 - 0xFFFF - - - REG_OFFSET_ADDR - Base offset Address for Command Queuing registers. - 0 - 16 - read-only - - - - - SLOT_INTR_STATUS - No description available - 0xfc - 16 - 0x0000 - 0x00FF - - - INTR_SLOT - Interrupt signal for each Slot -These status bits indicate the logical OR of Interrupt signal and Wakeup signal for each slot. -A maximum of 8 slots can be defined. If one interrupt signal is associated with multiple slots, the Host Driver can identify the interrupt that is generated by reading these bits. - By a power on reset or by setting Software Reset For All bit, the interrupt signals are de-asserted and this status reads 00h. -Bit 00: Slot 1 -Bit 01: Slot 2 -Bit 02: Slot 3 -.......... -.......... -Bit 07: Slot 8 -Note: MSHC Host Controller support single card slot. This register shall always return 0. - 0 - 8 - read-only - - - - - CQVER - No description available - 0x180 - 32 - 0x00000000 - 0x00000FFF - - - EMMC_VER_MAHOR - This bit indicates the eMMC major version (1st digit left of decimal point) in BCD format. - 8 - 4 - read-only - - - EMMC_VER_MINOR - This bit indicates the eMMC minor version (1st digit right of decimal point) in BCD format. - 4 - 4 - read-only - - - EMMC_VER_SUFFIX - This bit indicates the eMMC version suffix (2nd digit right of decimal point) in BCD format. - 0 - 4 - read-only - - - - - CQCAP - No description available - 0x184 - 32 - 0x00000000 - 0x1000F3FF - - - CRYPTO_SUPPORT - Crypto Support -This bit indicates whether the Host Controller supports cryptographic operations. -Values: -0x0 (FALSE): Crypto not Supported -0x1 (TRUE): Crypto Supported - 28 - 1 - read-only - - - ITCFMUL - Internal Timer Clock Frequency Multiplier (ITCFMUL) -This field indicates the frequency of the clock used for interrupt coalescing timer and for determining the SQS -polling period. See ITCFVAL definition for details. Values 0x5 to 0xF are reserved. -Values: -0x0 (CLK_1KHz): 1KHz clock -0x1 (CLK_10KHz): 10KHz clock -0x2 (CLK_100KHz): 100KHz clock -0x3 (CLK_1MHz): 1MHz clock -0x4 (CLK_10MHz): 10MHz clock - 12 - 4 - read-only - - - ITCFVAL - Internal Timer Clock Frequency Value (ITCFVAL) -This field scales the frequency of the timer clock provided by ITCFMUL. The Final clock frequency of actual timer clock is calculated as ITCFVAL* ITCFMUL. - 0 - 10 - read-only - - - - - CQCFG - No description available - 0x188 - 32 - 0x00000000 - 0x00001101 - - - DCMD_EN - This bit indicates to the hardware whether the Task -Descriptor in slot #31 of the TDL is a data transfer descriptor or a direct-command descriptor. CQE uses this bit when a task is issued in slot #31, to determine how to decode the Task Descriptor. -Values: -0x1 (SLOT31_DCMD_ENABLE): Task descriptor in slot #31 is a DCMD Task Descriptor -0x0 (SLOT31_DCMD_DISABLE): Task descriptor in slot #31 is a data Transfer Task Descriptor - 12 - 1 - read-write - - - TASK_DESC_SIZE - Bit Value Description -This bit indicates the size of task descriptor used in host memory. This bit can only be configured when Command Queuing Enable bit is 0 (command queuing is disabled). -Values: -0x1 (TASK_DESC_128b): Task descriptor size is 128 bits -0x0 (TASK_DESC_64b): Task descriptor size is 64 bit - 8 - 1 - read-write - - - CQ_EN - No description available - 0 - 1 - read-write - - - - - CQCTL - No description available - 0x18c - 32 - 0x00000000 - 0x00000101 - - - CLR_ALL_TASKS - Clear all tasks -This bit can only be written when the controller is halted. This bit does not clear tasks in the device. The software has to use the CMDQ_TASK_MGMT command to clear device's queue. -Values: -0x1 (CLEAR_ALL_TASKS): Clears all the tasks in the controller -0x0 (NO_EFFECT): Programming 0 has no effect - 8 - 1 - read-write - - - HALT - Halt request and resume -Values: -0x1 (HALT_CQE): Software writes 1 to this bit when it wants to acquire software control over the eMMC bus and to disable CQE from issuing command on the bus. -For example, issuing a Discard Task command (CMDQ_TASK_MGMT). -When the software writes 1, CQE completes the ongoing task (if any in progress). -After the task is completed and the CQE is in idle state, CQE does not issue new commands and indicates to the software by setting this bit to 1. -The software can poll on this bit until it is set to 1 and only then send commands on the eMMC bus. -0x0 (RESUME_CQE): Software writes 0 to this bit to exit from the halt state and resume CQE activity - 0 - 1 - read-write - - - - - CQIS - No description available - 0x190 - 32 - 0x00000000 - 0x0000000F - - - TCL - Task cleared interrupt -This status bit is asserted (if CQISE.TCL_STE=1) when a task clear operation is completed by CQE. -The completed task clear operation is either an individual task clear (by writing CQTCLR) or clearing of all tasks (by writing CQCTL). -A value of 1 clears this status bit. -Values: -0x1 (SET): TCL Interrupt is set -0x0 (NOTSET): TCL Interrupt is not set - 3 - 1 - read-write - - - RED - Response error detected interrupt -This status bit is asserted (if CQISE.RED_STE=1) when a response is received with an error bit set in the device status -field. Configure the CQRMEM register to identify device status bit fields that may trigger an interrupt and that are masked. -A value of 1 clears this status bit. -Values: -0x1 (SET): RED Interrupt is set -0x0 (NOTSET): RED Interrupt is not set - 2 - 1 - read-write - - - TCC - Task complete interrupt -This status bit is asserted (if CQISE.TCC_STE=1) when at least one of the following conditions are met: -A task is completed and the INT bit is set in its Task Descriptor -Interrupt caused by Interrupt Coalescing logic due to timeout -Interrupt Coalescing logic reached the configured threshold -A value of 1 clears this status bit - 1 - 1 - read-write - - - HAC - Halt complete interrupt -This status bit is asserted (only if CQISE.HAC_STE=1) when halt bit in the CQCTL register transitions from 0 to 1 indicating that the host controller has completed its current ongoing task and has entered halt state. -A value of 1 clears this status bit. -Values: -0x1 (SET): HAC Interrupt is set -0x0 (NOTSET): HAC Interrupt is not set - 0 - 1 - read-write - - - - - CQISE - No description available - 0x194 - 32 - 0x00000000 - 0x0000000F - - - TCL_STE - Task cleared interrupt status enable -Values: -0x1 (INT_STS_ENABLE): CQIS.TCL is set when its interrupt condition is active -0x0 (INT_STS_DISABLE): CQIS.TCL is disabled - 3 - 1 - read-write - - - RED_STE - Response error detected interrupt status enable -Values: -0x1 (INT_STS_ENABLE): CQIS.RED is set when its interrupt condition is active -0x0 (INT_STS_DISABLE): CQIS.RED is disabled - 2 - 1 - read-write - - - TCC_STE - Task complete interrupt status enable -Values: -0x1 (INT_STS_ENABLE): CQIS.TCC is set when its interrupt condition is active -0x0 (INT_STS_DISABLE): CQIS.TCC is disabled - 1 - 1 - read-write - - - HAC_STE - Halt complete interrupt status enable -Values: -0x1 (INT_STS_ENABLE): CQIS.HAC is set when its interrupt condition is active -0x0 (INT_STS_DISABLE): CQIS.HAC is disabled - 0 - 1 - read-write - - - - - CQISGE - No description available - 0x198 - 32 - 0x00000000 - 0x0000000F - - - TCL_SGE - Task cleared interrupt signal enable -Values: -0x1 (INT_SIG_ENABLE): CQIS.TCL interrupt signal generation is active -0x0 (INT_SIG_DISABLE): CQIS.TCL interrupt signal generation is disabled - 3 - 1 - read-write - - - RED_SGE - Response error detected interrupt signal enable -Values: -0x1 (INT_SIG_ENABLE): CQIS.RED interrupt signal generation is active -0x0 (INT_SIG_DISABLE): CQIS.RED interrupt signal generation is disabled - 2 - 1 - read-write - - - TCC_SGE - Task complete interrupt signal enable -Values: -0x1 (INT_SIG_ENABLE): CQIS.TCC interrupt signal generation is active -0x0 (INT_SIG_DISABLE): CQIS.TCC interrupt signal generation is disabled - 1 - 1 - read-write - - - HAC_SGE - Halt complete interrupt signal enable -Values: -0x1 (INT_SIG_ENABLE): CQIS.HAC interrupt signal generation is active -0x0 (INT_SIG_DISABLE): CQIS.HAC interrupt signal generation is disabled - 0 - 1 - read-write - - - - - CQIC - No description available - 0x19c - 32 - 0x00000000 - 0x80119FFF - - - INTC_EN - Interrupt Coalescing Enable Bit -Values: -0x1 (ENABLE_INT_COALESCING): Interrupt coalescing mechanism is active. Interrupts are counted and timed, and coalesced interrupts are generated -0x0 (DISABLE_INT_COALESCING): Interrupt coalescing mechanism is disabled (Default) - 31 - 1 - read-write - - - INTC_STAT - Interrupt Coalescing Status Bit -This bit indicates to the software whether any tasks (with INT=0) have completed and counted towards interrupt -coalescing (that is, this is set if and only if INTC counter > 0). -Values: -0x1 (INTC_ATLEAST1_COMP): At least one INT0 task completion has been counted (INTC counter > 0) -0x0 (INTC_NO_TASK_COMP): INT0 Task completions have not occurred since last counter reset (INTC counter == 0) - 20 - 1 - read-only - - - INTC_RST - Counter and Timer Reset -When host driver writes 1, the interrupt coalescing timer and counter are reset. -Values: -0x1 (ASSERT_INTC_RESET): Interrupt coalescing timer and counter are reset -0x0 (NO_EFFECT): No Effect - 16 - 1 - write-only - - - INTC_TH_WEN - Interrupt Coalescing Counter Threshold Write Enable -When software writes 1 to this bit, the value INTC_TH is updated with the contents written on the same cycle. -Values: -0x1 (WEN_SET): Sets INTC_TH_WEN -0x0 (WEN_CLR): Clears INTC_TH_WEN - 15 - 1 - write-only - - - INTC_TH - Interrupt Coalescing Counter Threshold filed -Software uses this field to configure the number of task completions (only tasks with INT=0 in the Task Descriptor), which are required in order to generate an interrupt. -Counter Operation: As data transfer tasks with INT=0 complete, they are counted by CQE. -The counter is reset by software during the interrupt service routine. -The counter stops counting when it reaches the value configured in INTC_TH, and generates interrupt. -0x0: Interrupt coalescing feature disabled -0x1: Interrupt coalescing interrupt generated after 1 task when INT=0 completes -0x2: Interrupt coalescing interrupt generated after 2 tasks when INT=0 completes -........ -0x1f: Interrupt coalescing interrupt generated after 31 tasks when INT=0 completes -To write to this field, the INTC_TH_WEN bit must be set during the same write operation. - 8 - 5 - write-only - - - TOUT_VAL_WEN - When software writes 1 to this bit, the value TOUT_VAL is updated with the contents written on the same cycle. -Values: -0x1 (WEN_SET): Sets TOUT_VAL_WEN -0x0 (WEN_CLR): clears TOUT_VAL_WEN - 7 - 1 - write-only - - - TOUT_VAL - Interrupt Coalescing Timeout Value -Software uses this field to configure the maximum time allowed between the completion of a task on the bus and the generation of an interrupt. -Timer Operation: The timer is reset by software during the interrupt service routine. -It starts running when the first data transfer task with INT=0 is completed, after the timer was reset. -When the timer reaches the value configured in ICTOVAL field, it generates an interrupt and stops. -The timer's unit is equal to 1024 clock periods of the clock whose frequency is specified in the Internal Timer Clock Frequency field CQCAP register. -0x0: Timer is disabled. Timeout-based interrupt is not generated -0x1: Timeout on 01x1024 cycles of timer clock frequency -0x2: Timeout on 02x1024 cycles of timer clock frequency -........ -0x7f: Timeout on 127x1024 cycles of timer clock frequency -In order to write to this field, the TOUT_VAL_WEN bit must -be set at the same write operation. - 0 - 7 - read-write - - - - - CQTDLBA - No description available - 0x1a0 - 32 - 0x00000000 - 0xFFFFFFFF - - - TDLBA - This register stores the LSB bits (31:0) of the byte address of the head of the Task Descriptor List in system memory. -The size of the task descriptor list is 32 * (Task Descriptor size + Transfer Descriptor size) as configured by the host driver. -This address is set on 1 KB boundary. The lower 10 bits of this register are set to 0 by the software and are ignored by CQE - 0 - 32 - read-write - - - - - CQTDBR - No description available - 0x1a8 - 32 - 0x00000000 - 0xFFFFFFFF - - - DBR - The software configures TDLBA and TDLBAU, and enable -CQE in CQCFG before using this register. -Writing 1 to bit n of this register triggers CQE to start processing the task encoded in slot n of the TDL. -Writing 0 by the software does not have any impact on the hardware, and does not change the value of the register bit. -CQE always processes tasks according to the order submitted to the list by CQTDBR write transactions. -CQE processes Data Transfer tasks by reading the Task Descriptor and sending QUEUED_TASK_PARAMS (CMD44) and QUEUED_TASK_ADDRESS (CMD45) commands to -the device. CQE processes DCMD tasks (in slot #31, when enabled) by reading the Task Descriptor, and generating the command encoded by its index and argument. -The corresponding bit is cleared to 0 by CQE in one of the following events: -A task execution is completed (with success or error). -The task is cleared using CQTCLR register. -All tasks are cleared using CQCTL register. -CQE is disabled using CQCFG register. -Software may initiate multiple tasks at the same time (batch submission) by writing 1 to multiple bits of this register in the same transaction. -In the case of batch submission, CQE processes the tasks in order of the task index, starting with the lowest index. -If one or more tasks in the batch are marked with QBR, the ordering of execution is based on said processing order. - 0 - 32 - read-write - - - - - CQTCN - No description available - 0x1ac - 32 - 0x00000000 - 0xFFFFFFFF - - - TCN - Task Completion Notification -Each of the 32 bits are bit mapped to the 32 tasks. -Bit-N(1): Task-N has completed execution (with success or errors) -Bit-N(0): Task-N has not completed, could be pending or not submitted. -On task completion, software may read this register to know tasks that have completed. After reading this register, -software may clear the relevant bit fields by writing 1 to the corresponding bits. - 0 - 32 - read-write - - - - - CQDQS - No description available - 0x1b0 - 32 - 0x00000000 - 0xFFFFFFFF - - - DQS - Device Queue Status -Each of the 32 bits are bit mapped to the 32 tasks. -Bit-N(1): Device has marked task N as ready for execution -Bit-N(0): Task-N is not ready for execution. This task could be pending in device or not submitted. -Host controller updates this register with response of the Device Queue Status command. - 0 - 32 - read-write - - - - - CQDPT - No description available - 0x1b4 - 32 - 0x00000000 - 0xFFFFFFFF - - - DPT - Device-Pending Tasks -Each of the 32 bits are bit mapped to the 32 tasks. -Bit-N(1): Task-N has been successfully queued into the device and is awaiting execution -Bit-N(0): Task-N is not yet queued. -Bit n of this register is set if and only if QUEUED_TASK_PARAMS (CMD44) and QUEUED_TASK_ADDRESS (CMD45) were sent for this specific task and if this task has not been executed. -The controller sets this bit after receiving a successful response for CMD45. CQE clears this bit after the task has completed execution. -Software reads this register in the task-discard procedure to determine if the task is queued in the device - 0 - 32 - read-write - - - - - CQTCLR - No description available - 0x1b8 - 32 - 0x00000000 - 0xFFFFFFFF - - - TCLR - Writing 1 to bit n of this register orders CQE to clear a task that the software has previously issued. -This bit can only be written when CQE is in Halt state as indicated in CQCFG register Halt bit. -When software writes 1 to a bit in this register, CQE updates the value to 1, and starts clearing the data structures related to the task. -CQE clears the bit fields (sets a value of 0) in CQTCLR and in CQTDBR once the clear operation is complete. -Software must poll on the CQTCLR until it is leared to verify that a clear operation was done. - 0 - 32 - read-write - - - - - CQSSC1 - No description available - 0x1c0 - 32 - 0x00000000 - 0x000FFFFF - - - SQSCMD_BLK_CNT - This field indicates when SQS CMD is sent while data transfer is in progress. -A value of 'n' indicates that CQE sends status command on the CMD line, during the transfer of data block BLOCK_CNTn, on the data lines, where BLOCK_CNT is the number of blocks in the current transaction. -0x0: SEND_QUEUE_STATUS (CMD13) command is not sent during the transaction. Instead, it is sent only when the data lines are idle. -0x1: SEND_QUEUE_STATUS command is to be sent during the last block of the transaction. -0x2: SEND_QUEUE_STATUS command when last 2 blocks are pending. -0x3: SEND_QUEUE_STATUS command when last 3 blocks are pending. -........ -0xf: SEND_QUEUE_STATUS command when last 15 blocks are pending. -Should be programmed only when CQCFG.CQ_EN is 0 - 16 - 4 - read-write - - - SQSCMD_IDLE_TMR - This field configures the polling period to be used when using periodic SEND_QUEUE_STATUS (CMD13) polling. -Periodic polling is used when tasks are pending in the device, but no data transfer is in progress. -When a SEND_QUEUE_STATUS response indicates that no task is ready for execution, CQE counts the configured time until it issues the next SEND_QUEUE_STATUS. -Timer units are clock periods of the clock whose frequency is specified in the Internal Timer Clock Frequency field CQCAP register. -The minimum value is 0001h (1 clock period) and the maximum value is FFFFh (65535 clock periods). -For example, a CQCAP field value of 0 indicates a 19.2 MHz clock frequency (period = 52.08 ns). -If the setting in CQSSC1.CIT is 1000h, the calculated polling period is 4096*52.08 ns= 213.33 us. -Should be programmed only when CQCFG.CQ_EN is '0' - 0 - 16 - read-write - - - - - CQSSC2 - No description available - 0x1c4 - 32 - 0x00000000 - 0x0000FFFF - - - SQSCMD_RCA - This field provides CQE with the contents of the 16-bit RCA field in SEND_QUEUE_STATUS (CMD13) command argument. -CQE copies this field to bits 31:16 of the argument when transmitting SEND_ QUEUE_STATUS (CMD13) command. - 0 - 16 - read-write - - - - - CQCRDCT - No description available - 0x1c8 - 32 - 0x00000000 - 0xFFFFFFFF - - - DCMD_RESP - This register contains the response of the command generated by the last direct command (DCMD) task that was sent. -Contents of this register are valid only after bit 31 of CQTDBR register is cleared by the controller. - 0 - 32 - read-only - - - - - CQRMEM - No description available - 0x1d0 - 32 - 0x00000000 - 0xFFFFFFFF - - - RESP_ERR_MASK - The bits of this field are bit mapped to the device response. -This bit is used as an interrupt mask on the device status filed that is received in R1/R1b responses. -1: When a R1/R1b response is received, with a bit i in the device status set, a RED interrupt is generated. -0: When a R1/R1b response is received, bit i in the device status is ignored. -The reset value of this register is set to trigger an interrupt on all "Error" type bits in the device status. -Note: Responses to CMD13 (SQS) encode the QSR so that they are ignored by this logic. - 0 - 32 - read-write - - - - - CQTERRI - No description available - 0x1d4 - 32 - 0x00000000 - 0x1F3F9F3F - - - TRANS_ERR_TASKID - This field captures the ID of the task that was executed and whose data transfer has errors. - 24 - 5 - read-only - - - TRANS_ERR_CMD_INDX - This field captures the index of the command that was executed and whose data transfer has errors. - 16 - 6 - read-only - - - RESP_ERR_FIELDS_VALID - This bit is updated when an error is detected while a command transaction was in progress. -Values: -0x1 (SET): Response-related error is detected. Check contents of RESP_ERR_TASKID and RESP_ERR_CMD_INDX fields -0x0 (NOT_SET): Ignore contents of RESP_ERR_TASKID and RESP_ERR_CMD_INDX - 15 - 1 - read-only - - - RESP_ERR_TASKID - This field captures the ID of the task which was executed on the command line when the error occurred. - 8 - 5 - read-only - - - RESP_ERR_CMD_INDX - This field captures the index of the command that was executed on the command line when the error occurred - 0 - 6 - read-only - - - - - CQCRI - No description available - 0x1d8 - 32 - 0x00000000 - 0x0000003F - - - CMD_RESP_INDX - Last Command Response index -This field stores the index of the last received command response. Controller updates the value every time a command response is received - 0 - 6 - read-only - - - - - CQCRA - No description available - 0x1dc - 32 - 0x00000000 - 0xFFFFFFFF - - - CMD_RESP_ARG - Last Command Response argument -This field stores the argument of the last received command response. Controller updates the value every time a command response is received. - 0 - 32 - read-only - - - - - MSHC_VER_ID - No description available - 0x500 - 32 - 0x00000000 - 0xFFFFFFFF - - - VER_ID - No description available - 0 - 32 - read-only - - - - - MSHC_VER_TYPE - No description available - 0x504 - 32 - 0x00000000 - 0xFFFFFFFF - - - VER_TYPE - No description available - 0 - 32 - read-only - - - - - EMMC_BOOT_CTRL - No description available - 0x52c - 32 - 0x00000000 - 0xF181070F - - - BOOT_TOUT_CNT - Boot Ack Timeout Counter Value. -This value determines the interval by which boot ack timeout (50 ms) is detected when boot ack is expected during boot operation. -0xF : Reserved -0xE : TMCLK x 2^27 - ............ -0x1 : TMCLK x 2^14 -0x0 : TMCLK x 2^13 - 28 - 4 - read-write - - - BOOT_ACK_ENABLE - Boot Acknowledge Enable -When this bit set, SDXC checks for boot acknowledge start pattern of 0-1-0 during boot operation. This bit is applicable for both mandatory and alternate boot mode. -Values: -0x1 (TRUE): Boot Ack enable -0x0 (FALSE): Boot Ack disable - 24 - 1 - read-write - - - VALIDATE_BOOT - Validate Mandatory Boot Enable bit -This bit is used to validate the MAN_BOOT_EN bit. -Values: -0x1 (TRUE): Validate Mandatory boot enable bit -0x0 (FALSE): Ignore Mandatory boot Enable bit - 23 - 1 - write-only - - - MAN_BOOT_EN - Mandatory Boot Enable -This bit is used to initiate the mandatory boot operation. The application sets this bit along with VALIDATE_BOOT bit. -Writing 0 is ignored. The SDXC clears this bit after the boot transfer is completed or terminated. -Values: -0x1 (MAN_BOOT_EN): Mandatory boot enable -0x0 (MAN_BOOT_DIS): Mandatory boot disable - 16 - 1 - read-write - - - CQE_PREFETCH_DISABLE - Enable or Disable CQE's PREFETCH feature -This field allows Software to disable CQE's data prefetch feature when set to 1. -Values: -0x0 (PREFETCH_ENABLE): CQE can Prefetch data for sucessive WRITE transfers and pipeline sucessive READ transfers -0x1 (PREFETCH_DISABLE): Prefetch for WRITE and Pipeline for READ are disabled - 10 - 1 - read-write - - - CQE_ALGO_SEL - Scheduler algorithm selected for execution -This bit selects the Algorithm used for selecting one of the many ready tasks for execution. -Values: -0x0 (PRI_REORDER_PLUS_FCFS): Priority based reordering with FCFS to resolve equal priority tasks -0x1 (FCFS_ONLY): First come First serve, in the order of DBR rings - 9 - 1 - read-write - - - ENH_STROBE_ENABLE - Enhanced Strobe Enable -This bit instructs SDXC to sample the CMD line using data strobe for HS400 mode. -Values: -0x1 (ENH_STB_FOR_CMD): CMD line is sampled using data strobe for HS400 mode -0x0 (NO_STB_FOR_CMD): CMD line is sampled using cclk_rx for HS400 mode - 8 - 1 - read-write - - - EMMC_RST_N_OE - Output Enable control for EMMC Device Reset signal PAD -control. -This field drived sd_rst_n_oe output of SDXC -Values: -0x1 (ENABLE): sd_rst_n_oe is 1 -0x0 (DISABLE): sd_rst_n_oe is 0 - 3 - 1 - read-write - - - EMMC_RST_N - EMMC Device Reset signal control. -This register field controls the sd_rst_n output of SDXC -Values: -0x1 (RST_DEASSERT): Reset to eMMC device is deasserted -0x0 (RST_ASSERT): Reset to eMMC device asserted (active low) - 2 - 1 - read-write - - - DISABLE_DATA_CRC_CHK - Disable Data CRC Check -This bit controls masking of CRC16 error for Card Write in eMMC mode. -This is useful in bus testing (CMD19) for an eMMC device. In bus testing, an eMMC card does not send CRC status for a block, -which may generate CRC error. This CRC error can be masked using this bit during bus testing. -Values: -0x1 (DISABLE): DATA CRC check is disabled -0x0 (ENABLE): DATA CRC check is enabled - 1 - 1 - read-write - - - CARD_IS_EMMC - eMMC Card present -This bit indicates the type of card connected. An application program this bit based on the card connected to SDXC. -Values: -0x1 (EMMC_CARD): Card connected to SDXC is an eMMC card -0x0 (NON_EMMC_CARD): Card connected to SDXCis a non-eMMC card - 0 - 1 - read-write - - - - - AUTO_TUNING_CTRL - No description available - 0x540 - 32 - 0x00000000 - 0x7F1F0F1F - - - SWIN_TH_VAL - Sampling window threshold value setting -The maximum value that can be set here depends on the length of delayline used for tuning. A delayLine with 32 taps -can use values from 0x0 to 0x1F. -This field is valid only when SWIN_TH_EN is '1'. Should be programmed only when SAMPLE_CLK_SEL is '0' -0x0 : Threshold values is 0x1, windows of length 1 tap and above can be selected as sampling window. -0x1 : Threshold values is 0x2, windows of length 2 taps and above can be selected as sampling window. -0x2 : Threshold values is 0x1, windows of length 3 taps and above can be selected as sampling window. -........ -0x1F : Threshold values is 0x1, windows of length 32 taps and above can be selected as sampling window. - 24 - 7 - read-write - - - POST_CHANGE_DLY - Time taken for phase switching and stable clock output. -Specifies the maximum time (in terms of cclk cycles) that the delay line can take to switch its output phase after a change in tuning_cclk_sel or autotuning_cclk_sel. -Values: -0x0 (LATENCY_LT_1): Less than 1-cycle latency -0x1 (LATENCY_LT_2): Less than 2-cycle latency -0x2 (LATENCY_LT_3): Less than 3-cycle latency -0x3 (LATENCY_LT_4): Less than 4-cycle latency - 19 - 2 - read-write - - - PRE_CHANGE_DLY - Maximum Latency specification between cclk_tx and cclk_rx. -Values: -0x0 (LATENCY_LT_1): Less than 1-cycle latency -0x1 (LATENCY_LT_2): Less than 2-cycle latency -0x2 (LATENCY_LT_3): Less than 3-cycle latency -0x3 (LATENCY_LT_4): Less than 4-cycle latency - 17 - 2 - read-write - - - TUNE_CLK_STOP_EN - Clock stopping control for Tuning and auto-tuning circuit. -When enabled, clock gate control output of SDXC (clk2card_on) is pulled low before changing phase select codes on tuning_cclk_sel and autotuning_cclk_sel. -This effectively stops the Device/Card clock, cclk_rx and also drift_cclk_rx. Changing phase code when clocks are stopped ensures glitch free phase switching. - Set this bit to 0 if the PHY or delayline can guarantee glitch free switching. -Values: -0x1 (ENABLE_CLK_STOPPING): Clocks stopped during phase code change -0x0 (DISABLE_CLK_STOPPING): Clocks not stopped. PHY ensures glitch free phase switching - 16 - 1 - read-write - - - WIN_EDGE_SEL - This field sets the phase for Left and Right edges for drift monitoring. [Left edge offset + Right edge offset] must not be less than total taps of delayLine. -0x0: User selection disabled. Tuning calculated edges are used. -0x1: Right edge Phase is center + 2 stages, Left edge Phase is center - 2 stages. -0x2: Right edge Phase is center + 3 stages, Left edge Phase is center - 3 stagess -... -0xF: Right edge Phase is center + 16 stages, Left edge Phase is center - 16 stages. - 8 - 4 - read-write - - - SW_TUNE_EN - This fields enables software-managed tuning flow. -Values: -0x1 (SW_TUNING_ENABLE): Software-managed tuning enabled. AUTO_TUNING_STAT.CENTER_PH_CODE Field is now writable. -0x0 (SW_TUNING_DISABLE): Software-managed tuning disabled - 4 - 1 - read-write - - - RPT_TUNE_ERR - Framing errors are not generated when executing tuning. -This debug bit allows users to report these errors. -Values: -0x1 (DEBUG_ERRORS): Debug mode for reporting framing errors -0x0 (ERRORS_DISABLED): Default mode where as per SDXC no errors are reported. - 3 - 1 - read-write - - - SWIN_TH_EN - Sampling window Threshold enable -Selects the tuning mode -Field should be programmed only when SAMPLE_CLK_SEL is '0' -Values: -0x1 (THRESHOLD_MODE): Tuning engine selects the first complete sampling window that meets the threshold -set by SWIN_TH_VAL field -0x0 (LARGEST_WIN_MODE): Tuning engine sweeps all taps and settles at the largest window - 2 - 1 - read-write - - - CI_SEL - Selects the interval when the corrected center phase select code can be driven on tuning_cclk_sel output. -Values: -0x0 (WHEN_IN_BLK_GAP): Driven in block gap interval -0x1 (WHEN_IN_IDLE): Driven at the end of the transfer - 1 - 1 - read-write - - - AT_EN - Setting this bit enables Auto tuning engine. This bit is enabled by default when core is configured with mode3 retuning support. -Clear this bit to 0 when core is configured to have Mode3 re-tuning but SW wishes to disable mode3 retuning. -This field should be programmed only when SYS_CTRL.SD_CLK_EN is 0. -Values: -0x1 (AT_ENABLE): AutoTuning is enabled -0x0 (AT_DISABLE): AutoTuning is disabled - 0 - 1 - read-write - - - - - AUTO_TUNING_STAT - No description available - 0x544 - 32 - 0x00000000 - 0x00FFFFFF - - - L_EDGE_PH_CODE - Left Edge Phase code. Reading this field returns the phase code value used by Auto-tuning engine to sample data on Left edge of sampling window. - 16 - 8 - read-only - - - R_EDGE_PH_CODE - Right Edge Phase code. Reading this field returns the phase code value used by Auto-tuning engine to sample data on Right edge of sampling window. - 8 - 8 - read-only - - - CENTER_PH_CODE - Centered Phase code. Reading this field returns the current value on tuning_cclk_sel output. Setting AUTO_TUNING_CTRL.SW_TUNE_EN enables software to write to this field and its contents are reflected on tuning_cclk_sel - 0 - 8 - read-write - - - - - - - SDXC1 - SDXC1 - SDXC - 0xf2034000 - - - CONCTL - CONCTL - CONCTL - 0xf2040000 - - 0x0 - 0x18 - registers - - - - ctrl0 - No description available - 0x0 - 32 - 0x00000000 - 0xFF0FFFFF - - - ENET1_RXCLK_DLY_SEL - No description available - 15 - 5 - read-write - - - ENET1_TXCLK_DLY_SEL - No description available - 10 - 5 - read-write - - - ENET0_RXCLK_DLY_SEL - No description available - 5 - 5 - read-write - - - ENET0_TXCLK_DLY_SEL - No description available - 0 - 5 - read-write - - - - - ctrl2 - No description available - 0x8 - 32 - 0x00000000 - 0x2008F400 - - - ENET0_LPI_IRQ_EN - ENET0 LPI IRQ Enable - 29 - 1 - read-write - - - ENET0_REFCLK_OE - No description available - 19 - 1 - read-write - - - ENET0_PHY_INTF_SEL - 000:Reserved -001:RGMII -100:RMII -111:Reserved - 13 - 3 - read-write - - - ENET0_FLOWCTRL - No description available - 12 - 1 - read-write - - - ENET0_RMII_TXCLK_SEL - default to use internal clk. -set from pad， two option here: - internal 50MHz clock out to pad then in; - use external clock; - 10 - 1 - read-write - - - - - ctrl3 - No description available - 0xc - 32 - 0x00000000 - 0x2008F400 - - - ENET1_LPI_IRQ_EN - ENET1 LPI Interrupt Enable - 29 - 1 - read-write - - - ENET1_REFCLK_OE - No description available - 19 - 1 - read-write - - - ENET1_PHY_INTF_SEL - No description available - 13 - 3 - read-write - - - ENET1_FLOWCTRL - No description available - 12 - 1 - read-write - - - ENET1_RMII_TXCLK_SEL - No description available - 10 - 1 - read-write - - - - - ctrl4 - No description available - 0x10 - 32 - 0x00000000 - 0xDFFFF800 - - - SDXC0_SYS_IRQ_EN - system irq enable - 31 - 1 - read-write - - - SDXC0_WKP_IRQ_EN - wakeup irq enable - 30 - 1 - read-write - - - SDXC0_CARDCLK_INV_EN - card clock inverter enable - 28 - 1 - read-write - - - SDXC0_GPR_TUNING_CARD_CLK_SEL - for card clock DLL, default 0 - 23 - 5 - read-write - - - SDXC0_GPR_TUNING_STROBE_SEL - for strobe DLL, default 7taps(1ns) - 18 - 5 - read-write - - - SDXC0_GPR_STROBE_IN_ENABLE - enable strobe clock, maybe used when update strobe DLL - 17 - 1 - read-write - - - SDXC0_GPR_CCLK_RX_DLY_SW_SEL - No description available - 12 - 5 - read-write - - - SDXC0_GPR_CCLK_RX_DLY_SW_FORCE - force use sw DLL config - 11 - 1 - read-write - - - - - ctrl5 - No description available - 0x14 - 32 - 0x00000000 - 0xDFFFF800 - - - SDXC1_SYS_IRQ_EN - system irq enable - 31 - 1 - read-write - - - SDXC1_WKP_IRQ_EN - wakeup irq enable - 30 - 1 - read-write - - - SDXC1_CARDCLK_INV_EN - card clock inverter enable - 28 - 1 - read-write - - - SDXC1_GPR_TUNING_CARD_CLK_SEL - No description available - 23 - 5 - read-write - - - SDXC1_GPR_TUNING_STROBE_SEL - No description available - 18 - 5 - read-write - - - SDXC1_GPR_STROBE_IN_ENABLE - No description available - 17 - 1 - read-write - - - SDXC1_GPR_CCLK_RX_DLY_SW_SEL - No description available - 12 - 5 - read-write - - - SDXC1_GPR_CCLK_RX_DLY_SW_FORCE - No description available - 11 - 1 - read-write - - - - - - - I2C0 - I2C0 - I2C - 0xf3020000 - - 0x4 - 0x30 - registers - - - - Cfg - Configuration Register - 0x10 - 32 - 0x00000001 - 0xFFFFFFFF - - - FIFOSIZE - FIFO Size: -0: 2 bytes -1: 4 bytes -2: 8 bytes -3: 16 bytes - 0 - 2 - read-only - - - - - IntEn - Interrupt Enable Register - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - CMPL - Set to enable the Completion Interrupt. -Master: interrupts when a transaction is issued from this master and completed without losing the bus arbitration. -Slave: interrupts when a transaction addressing the controller is completed. - 9 - 1 - read-write - - - BYTERECV - Set to enable the Byte Receive Interrupt. -Interrupts when a byte of data is received -Auto-ACK will be disabled if this interrupt is enabled, that is, the software needs to ACK/NACK the received byte manually. - 8 - 1 - read-write - - - BYTETRANS - Set to enable the Byte Transmit Interrupt. -Interrupts when a byte of data is transmitted. - 7 - 1 - read-write - - - START - Set to enable the START Condition Interrupt. -Interrupts when a START condition/repeated START condition is detected. - 6 - 1 - read-write - - - STOP - Set to enable the STOP Condition Interrupt -Interrupts when a STOP condition is detected. - 5 - 1 - read-write - - - ARBLOSE - Set to enable the Arbitration Lose Interrupt. -Master: interrupts when the controller loses the bus arbitration -Slave: not available in this mode. - 4 - 1 - read-write - - - ADDRHIT - Set to enable the Address Hit Interrupt. -Master: interrupts when the addressed slave returned an ACK. -Slave: interrupts when the controller is addressed. - 3 - 1 - read-write - - - FIFOHALF - Set to enable the FIFO Half Interrupt. -Receiver: Interrupts when the FIFO is half-empty, i.e, there is >= 1/2 entries in the FIFO. -Transmitter: Interrupts when the FIFO is half-empty, i.e. there is <= 1/2 entries in the FIFO. -This interrupt depends on the transaction direction; don’t enable this interrupt unless the transfer direction is determined, otherwise unintended interrupts may be triggered. - 2 - 1 - read-write - - - FIFOFULL - Set to enable the FIFO Full Interrupt. -Interrupts when the FIFO is full. - 1 - 1 - read-write - - - FIFOEMPTY - Set to enabled the FIFO Empty Interrupt -Interrupts when the FIFO is empty. - 0 - 1 - read-write - - - - - Status - Status Register - 0x18 - 32 - 0x00000001 - 0xFFFFFFFF - - - LINESDA - Indicates the current status of the SDA line on the bus -1: high -0: low - 14 - 1 - read-only - - - LINESCL - Indicates the current status of the SCL line on the bus -1: high -0: low - 13 - 1 - read-only - - - GENCALL - Indicates that the address of the current transaction is a general call address: -1: General call -0: Not general call - 12 - 1 - read-only - - - BUSBUSY - Indicates that the bus is busy -The bus is busy when a START condition is on bus and it ends when a STOP condition is seen on bus -1: Busy -0: Not busy - 11 - 1 - read-only - - - ACK - Indicates the type of the last received/transmitted acknowledgement bit: -1: ACK -0: NACK - 10 - 1 - read-only - - - CMPL - Transaction Completion -Master: Indicates that a transaction has been issued from this master and completed without losing the bus arbitration -Slave: Indicates that a transaction addressing the controller has been completed. This status bit must be cleared to receive the next transaction; otherwise, the next incoming transaction will be blocked. - 9 - 1 - write-only - - - BYTERECV - Indicates that a byte of data has been received. - 8 - 1 - write-only - - - BYTETRANS - Indicates that a byte of data has been transmitted. - 7 - 1 - write-only - - - START - Indicates that a START Condition or a repeated START condition has been transmitted/received. - 6 - 1 - write-only - - - STOP - Indicates that a STOP Condition has been transmitted/received. - 5 - 1 - write-only - - - ARBLOSE - Indicates that the controller has lost the bus arbitration. - 4 - 1 - write-only - - - ADDRHIT - Master: indicates that a slave has responded to the transaction. -Slave: indicates that a transaction is targeting the controller (including the General Call). - 3 - 1 - write-only - - - FIFOHALF - Transmitter: Indicates that the FIFO is half-empty. - 2 - 1 - read-only - - - FIFOFULL - Indicates that the FIFO is full. - 1 - 1 - read-only - - - FIFOEMPTY - Indicates that the FIFO is empty. - 0 - 1 - read-only - - - - - Addr - Address Register - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR - The slave address. -For 7-bit addressing mode, the most significant 3 bits are ignored and only the least-significant 7 bits of Addr are valid - 0 - 10 - read-write - - - - - Data - Data Register - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - Write this register to put one byte of data to the FIFO. -Read this register to get one byte of data from the FIFO. - 0 - 8 - read-write - - - - - Ctrl - Control Register - 0x24 - 32 - 0x00001E00 - 0x000F9FFF - - - PHASE_START - Enable this bit to send a START condition at the beginning of transaction. -Master mode only. - 12 - 1 - read-write - - - PHASE_ADDR - Enable this bit to send the address after START condition. -Master mode only. - 11 - 1 - read-write - - - PHASE_DATA - Enable this bit to send the data after Address phase. -Master mode only. - 10 - 1 - read-write - - - PHASE_STOP - Enable this bit to send a STOP condition at the end of a transaction. -Master mode only. - 9 - 1 - read-write - - - DIR - Transaction direction -Master: Set this bit to determine the direction for the next transaction. -0: Transmitter -1: Receiver -Slave: The direction of the last received transaction. -0: Receiver -1: Transmitter - 8 - 1 - read-write - - - DATACNT - Data counts in bytes. -Master: The number of bytes to transmit/receive. 0 means max length. DataCnt will be decreased by one for each byte transmitted/received. -Slave: the meaning of DataCnt depends on the DMA mode: -If DMA is not enabled, DataCnt is the number of bytes transmitted/received from the bus master. It is reset to 0 when the controller is addressed and then increased by one for each byte of data transmitted/received. -If DMA is enabled, DataCnt is the number of bytes to transmit/receive. It will not be reset to 0 when the slave is addressed and it will be decreased by one for each byte of data transmitted/received. - 0 - 8 - read-write - - - - - Cmd - Command Register - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - CMD - Write this register with the following values to perform the corresponding actions: -0x0: no action -0x1: issue a data transaction (Master only) -0x2: respond with an ACK to the received byte -0x3: respond with a NACK to the received byte -0x4: clear the FIFO -0x5: reset the I2C controller (abort current transaction, set the SDA and SCL line to the open-drain mode, reset the Status Register and the Interrupt Enable Register, and empty the FIFO) -When issuing a data transaction by writing 0x1 to this register, the CMD field stays at 0x1 for the duration of the entire transaction, and it is only cleared to 0x0 after when the transaction has completed or when the controller loses the arbitration. -Note: No transaction will be issued by the controller when all phases (Start, Address, Data and Stop) are disabled. - 0 - 3 - read-write - - - - - Setup - Setup Register - 0x2c - 32 - 0x05252100 - 0xFFFFFFFF - - - T_SUDAT - T_SUDAT defines the data setup time before releasing the SCL. -Setup time = (2 * tpclk) + (2 + T_SP + T_SUDAT) * tpclk* (TPM+1) -tpclk = PCLK period -TPM = The multiplier value in Timing Parameter Multiplier Register - 24 - 5 - read-write - - - T_SP - T_SP defines the pulse width of spikes that must be suppressed by the input filter. -Pulse width = T_SP * tpclk* (TPM+1) - 21 - 3 - read-write - - - T_HDDAT - T_HDDAT defines the data hold time after SCL goes LOW -Hold time = (2 * tpclk) + (2 + T_SP + T_HDDAT) * tpclk* (TPM+1) - 16 - 5 - read-write - - - T_SCLRADIO - The LOW period of the generated SCL clock is defined by the combination of T_SCLRatio and T_SCLHi values. When T_SCLRatio = 0, the LOW period is equal to HIGH period. When T_SCLRatio = 1, the LOW period is roughly two times of HIGH period. -SCL LOW period = (2 * tpclk) + (2 + T_SP + T_SCLHi * ratio) * tpclk * (TPM+1) -1: ratio = 2 -0: ratio = 1 -This field is only valid when the controller is in the master mode. - 13 - 1 - read-write - - - T_SCLHI - The HIGH period of generated SCL clock is defined by T_SCLHi. -SCL HIGH period = (2 * tpclk) + (2 + T_SP + T_SCLHi) * tpclk* (TPM+1) -The T_SCLHi value must be greater than T_SP and T_HDDAT values. -This field is only valid when the controller is in the master mode. - 4 - 9 - read-write - - - DMAEN - Enable the direct memory access mode data transfer. -1: Enable -0: Disable - 3 - 1 - read-write - - - MASTER - Configure this device as a master or a slave. -1: Master mode -0: Slave mode - 2 - 1 - read-write - - - ADDRESSING - I2C addressing mode: -1: 10-bit addressing mode -0: 7-bit addressing mode - 1 - 1 - read-write - - - IICEN - Enable the I2C controller. -1: Enable -0: Disable - 0 - 1 - read-write - - - - - TPM - I2C Timing Paramater Multiplier - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - TPM - A multiplication value for I2C timing parameters. All the timing parameters in the Setup Register are multiplied by (TPM+1). - 0 - 5 - read-write - - - - - - - I2C1 - I2C1 - I2C - 0xf3024000 - - - I2C2 - I2C2 - I2C - 0xf3028000 - - - I2C3 - I2C3 - I2C - 0xf302c000 - - - SDP - SDP - SDP - 0xf304c000 - - 0x0 - 0x60 - registers - - - - SDPCR - SDP control register - 0x0 - 32 - 0x30000000 - 0xFFFE0001 - - - SFTRST - soft reset. -Write 1 then 0, to reset the SDP block. - 31 - 1 - read-write - - - CLKGAT - Clock Gate for the SDP main logic. -Write to 1 will clock gate for most logic of the SDP block, dynamic power saving when not use SDP block. - 30 - 1 - read-write - - - CIPDIS - Cipher Disable, read the info, whether the CIPHER features is besing disable in this chip or not. -1, Cipher is disabled in this chip. -0, Cipher is enabled in this chip. - 29 - 1 - read-only - - - HASDIS - HASH Disable, read the info, whether the HASH features is besing disable in this chip or not. -1, HASH is disabled in this chip. -0, HASH is enabled in this chip. - 28 - 1 - read-only - - - CIPHEN - Cipher Enablement, controlled by SW. -1, Cipher is Enabled. -0, Cipher is Disabled. - 23 - 1 - read-write - - - HASHEN - HASH Enablement, controlled by SW. -1, HASH is Enabled. -0, HASH is Disabled. - 22 - 1 - read-write - - - MCPEN - Memory Copy Enablement, controlled by SW. -1, Memory copy is Enabled. -0, Memory copy is Disabled. - 21 - 1 - read-write - - - CONFEN - Constant Fill to memory, controlled by SW. -1, Constant fill is Enabled. -0, Constant fill is Disabled. - 20 - 1 - read-write - - - DCRPDI - Decryption Disable bit, Write to 1 to disable the decryption. - 19 - 1 - read-write - - - TSTPKT0IRQ - Test purpose for interrupt when Packet counter reachs "0", but CHAIN=1 in the current packet. - 17 - 1 - read-write - - - INTEN - Interrupt Enablement, controlled by SW. -1, SDP interrupt is enabled. -0, SDP interrupt is disabled. - 0 - 1 - read-write - - - - - MODCTRL - Mod control register. - 0x4 - 32 - 0x00000000 - 0xFFFFF7FF - - - AESALG - AES algorithem selection. -0x0 = AES 128; -0x1 = AES 256; -0x8 = SM4； -Others, reserved. - 28 - 4 - read-write - - - AESMOD - AES mode selection. -0x0 = ECB; -0x1 = CBC; -Others, reserved. - 24 - 4 - read-write - - - AESKS - AES Key Selection. -These regisgers are being used to select the AES key that stored in the 16x128 key ram of the SDP, or select the key from the OTP. Detail as following: -0x00: key from the 16x128, this is the key read address, valid for AES128; AES256 will use 128 bit from this address and 128 bit key from next address as 256 bit AES key. -0x01: key from the 16x128, this is the key read address, valid for AES128, not valid for AES286. -.... -0x0E: key from the 16x128, this is the key read address, valid for AES128; AES256 will use 128 from this add and 128 from next add for the AES key. -0x0F: key from the 16x128, this is the key read address, valid for AES128, not valid for AES286. -0x20: kman_sk0[127:0] from the key manager for AES128; AES256 will use kman_sk0[255:0] as AES key. -0x21: kman_sk0[255:128] from the key manager for AES128; not valid for AES256. -0x22: kman_sk1[127:0] from the key manager for AES128; AES256 will use kman_sk1[255:0] as AES key. -0x23: kman_sk1[255:128] from the key manager for AES128; not valid for AES256. -0x24: kman_sk2[127:0] from the key manager for AES128; AES256 will use kman_sk2[255:0] as AES key. -0x25: kman_sk2[255:128] from the key manager for AES128; not valid for AES256. -0x26: kman_sk3[127:0] from the key manager for AES128; AES256 will use kman_sk3[255:0] as AES key. -0x27: kman_sk3[255:128] from the key manager for AES128; not valid for AES256. -0x30: exip0_key[127:0] from OTP for AES128; AES256 will use exip0_key[255:0] as AES key. -0x31: exip0_key[255:128] from OTP for AES128; not valid for AES256. -0x32: exip1_key[127:0] from OTP for AES128; AES256 will use exip1_key[255:0] as AES key. -0x33: exip1_key[255:128] from OTP for AES128; not valid for AES256. -Other values, reserved. - 18 - 6 - read-write - - - AESDIR - AES direction -1x1, AES Decryption -1x0, AES Encryption. - 16 - 1 - read-write - - - HASALG - HASH Algorithem selection. -0x0 SHA1 — -0x1 CRC32 — -0x2 SHA256 — - 12 - 4 - read-write - - - HASCHK - HASH Check Enable Bit. -1x1, HASH check need, hash result will compare with the HASHRSLT 0-7 registers; -1x0, HASH check is not enabled, HASHRSLT0-7 store the HASH result. -For SHA1, will use HASHRSLT0-3 words, and HASH 256 will use HASH0-7 words. - 10 - 1 - read-write - - - HASOUT - When hashing is enabled, this bit controls the input or output data of the AES engine is hashed. -0 INPUT HASH -1 OUTPUT HASH - 9 - 1 - read-write - - - DINSWP - Decide whether the SDP byteswaps the input data (big-endian data); -When all bits are set, the data is assumed to be in the big-endian format - 4 - 2 - read-write - - - DOUTSWP - Decide whether the SDP byteswaps the output data (big-endian data); When all bits are set, the data is assumed to be in the big-endian format - 2 - 2 - read-write - - - KEYSWP - Decide whether the SDP byteswaps the Key (big-endian data). -When all bits are set, the data is assumed to be in the big-endian format - 0 - 2 - read-write - - - - - PKTCNT - packet counter registers. - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - CNTVAL - This read-only field shows the current (instantaneous) value of the packet counter - 16 - 8 - read-only - - - CNTINCR - The value written to this field is added to the spacket count. - 0 - 8 - read-write - - - - - STA - Status Registers - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - TAG - packet tag. - 24 - 8 - read-only - - - IRQ - interrupt Request, requested when error happen, or when packet processing done, packet counter reach to zero. - 23 - 1 - write-only - - - CHN1PKT0 - the chain buffer "chain" bit is "1", while packet counter is "0", now, waiting for new buffer data. - 20 - 1 - write-only - - - AESBSY - AES Busy - 19 - 1 - read-only - - - HASBSY - Hashing Busy - 18 - 1 - read-only - - - PKTCNT0 - Packet Counter registers reachs to ZERO now. - 17 - 1 - write-only - - - PKTDON - Packet processing done, will trigger this itnerrrupt when the "PKTINT" bit set in the packet control word. - 16 - 1 - write-only - - - ERRSET - Working mode setup error. - 5 - 1 - write-only - - - ERRPKT - Packet head access error, or status update error. - 4 - 1 - write-only - - - ERRSRC - Source Buffer Access Error - 3 - 1 - write-only - - - ERRDST - Destination Buffer Error - 2 - 1 - write-only - - - ERRHAS - Hashing Check Error - 1 - 1 - write-only - - - ERRCHAIN - buffer chain error happen when packet's CHAIN bit=0, but the Packet counter is still not zero. - 0 - 1 - write-only - - - - - KEYADDR - Key Address - 0x10 - 32 - 0x00000040 - 0xFFFFFFFF - - - INDEX - To write a key to the SDP KEY RAM, the software must first write the desired key index/subword to this register. -Key index pointer. The valid indices are 0-[number_keys]. -In the SDP, there is a 16x128 key ram can store 16 AES128 keys or 8 AES 256 Keys; this index is for addressing the 16 128-bit key addresses. - 16 - 8 - read-write - - - SUBWRD - Key subword pointer. The valid indices are 0-3. After each write to the key data register, this field -increments; To write a key, the software must first write the desired key index/subword to this register. - 0 - 2 - read-write - - - - - KEYDAT - Key Data - 0x14 - 32 - 0x00000030 - 0xFFFFFFFF - - - KEYDAT - This register provides the write access to the key/key subword specified by the key index register. -Writing this location updates the selected subword for the key located at the index -specified by the key index register. The write also triggers the SUBWORD field of the -KEY register to increment to the next higher word in the key - 0 - 32 - read-write - - - - - 4 - 0x4 - CIPHIV0,CIPHIV1,CIPHIV2,CIPHIV3 - CIPHIV[%s] - no description available - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - CIPHIV - cipher initialization vector. - 0 - 32 - read-write - - - - - 8 - 0x4 - HASWRD0,HASWRD1,HASWRD2,HASWRD3,HASWRD4,HASWRD5,HASWRD6,HASWRD7 - HASWRD[%s] - no description available - 0x28 - 32 - 0x00000030 - 0xFFFFFFFF - - - HASWRD - Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. -If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. - 0 - 32 - read-write - - - - - CMDPTR - Command Pointer - 0x48 - 32 - 0x00000000 - 0xFFFFFFFF - - - CMDPTR - current command addresses the register points to the multiword -descriptor that is to be executed (or is currently being executed) - 0 - 32 - read-write - - - - - NPKTPTR - Next Packet Address Pointer - 0x4c - 32 - 0x00000000 - 0xFFFFFFFF - - - NPKTPTR - Next Packet Address Pointer - 0 - 32 - read-write - - - - - PKTCTL - Packet Control Registers - 0x50 - 32 - 0x00000000 - 0xFFFFFFFF - - - PKTTAG - packet tag - 24 - 8 - read-write - - - CIPHIV - Load Initial Vector for the AES in this packet. - 6 - 1 - read-write - - - HASFNL - Hash Termination packet - 5 - 1 - read-write - - - HASINI - Hash Initialization packat - 4 - 1 - read-write - - - CHAIN - whether the next command pointer register must be loaded into the channel's current descriptor -pointer. - 3 - 1 - read-write - - - DCRSEMA - whether the channel's semaphore must be decremented at the end of the current operation. -When the semaphore reaches a value of zero, no more operations are issued from the channel. - 2 - 1 - read-write - - - PKTINT - Reflects whether the channel must issue an interrupt upon the completion of the packet - 1 - 1 - read-write - - - - - PKTSRC - Packet Memory Source Address - 0x54 - 32 - 0x00000000 - 0xFFFFFFFF - - - PKTSRC - Packet Memory Source Address - 0 - 32 - read-write - - - - - PKTDST - Packet Memory Destination Address - 0x58 - 32 - 0x00000000 - 0xFFFFFFFF - - - PKTDST - Packet Memory Destination Address - 0 - 32 - read-write - - - - - PKTBUF - Packet buffer size. - 0x5c - 32 - 0x00000000 - 0xFFFFFFFF - - - PKTBUF - No description available - 0 - 32 - read-write - - - - - - - FEMC - FEMC - FEMC - 0xf3050000 - - 0x0 - 0x154 - registers - - - - CTRL - Control Register - 0x0 - 32 - 0x00000000 - 0x1FFF0007 - - - BTO - Bus timeout cycles -AXI Bus timeout cycle is as following (255*(2^BTO)): -00000b - 255*1 -00001-11110b - 255*2 - 255*2^30 -11111b - 255*2^31 - 24 - 5 - read-write - - - CTO - Command Execution timeout cycles -When Command Execution time exceed this timeout cycles, IPCMDERR or AXICMDERR interrupt is -generated. When CTO is set to zero, timeout cycle is 256*1024 cycle. otherwisee timeout cycle is -CTO*1024 cycle. - 16 - 8 - read-write - - - DQS - DQS (read strobe) mode -0b - Dummy read strobe loopbacked internally -1b - Dummy read strobe loopbacked from DQS pad - 2 - 1 - read-write - - - DIS - Module Disable -0b - Module enabled -1b - Module disabled - 1 - 1 - read-write - - - RST - Software Reset -Reset all internal logic in SEMC except configuration register - 0 - 1 - read-write - - - - - IOCTRL - IO Mux Control Register - 0x4 - 32 - 0x00000000 - 0x000000F0 - - - IO_CSX - IO_CSX output selection -0001b - SDRAM CS1 -0110b - SRAM CE# - 4 - 4 - read-write - - - - - BMW0 - Bus (AXI) Weight Control Register 0 - 0x8 - 32 - 0x00000000 - 0x00FFFFFF - - - RWS - Weight of slave hit with Read/Write Switch. This weight score is valid when queue command's slave is -same as current executing command with read/write operation switch. - 16 - 8 - read-write - - - SH - Weight of Slave Hit without read/write switch. This weight score is valid when queue command's slave is -same as current executing command without read/write operation switch. - 8 - 8 - read-write - - - AGE - Weight of AGE calculation. Each command in queue has an age signal to indicate its wait period. It is -multiplied by WAGE to get weight score. - 4 - 4 - read-write - - - QOS - Weight of QOS calculation. AXI bus access has AxQOS signal set, which is used as a priority indicator -for the associated write or read transaction. A higher value indicates a higher priority transaction. AxQOS -is multiplied by WQOS to get weight score. - 0 - 4 - read-write - - - - - BMW1 - Bus (AXI) Weight Control Register 1 - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - BR - Weight of Bank Rotation. This weight score is valid when queue command's bank is not same as current -executing command. - 24 - 8 - read-write - - - RWS - Weight of slave hit with Read/Write Switch. This weight score is valid when queue command's slave is -same as current executing command with read/write operation switch. - 16 - 8 - read-write - - - PH - Weight of Slave Hit without read/write switch. This weight score is valid when queue command's slave is -same as current executing command without read/write operation switch. - 8 - 8 - read-write - - - AGE - Weight of AGE calculation. Each command in queue has an age signal to indicate its wait period. It is -multiplied by WAGE to get weight score. - 4 - 4 - read-write - - - QOS - Weight of QOS calculation. AXI bus access has AxQOS signal set, which is used as a priority indicator -for the associated write or read transaction. A higher value indicates a higher priority transaction. AxQOS -is multiplied by WQOS to get weight score. - 0 - 4 - read-write - - - - - 7 - 0x4 - BASE0,BASE1,rsv2,rsv3,rsv4,rsv5,BASE6 - BR[%s] - no description available - 0x10 - 32 - 0x00000000 - 0xFFFFF03F - - - BASE - Base Address -This field determines high position 20 bits of SoC level Base Address. SoC level Base Address low -position 12 bits are all zero. - 12 - 20 - read-write - - - SIZE - Memory size -00000b - 4KB -00001b - 8KB -00010b - 16KB -00011b - 32KB -00100b - 64KB -00101b - 128KB -00110b - 256KB -00111b - 512KB -01000b - 1MB -01001b - 2MB -01010b - 4MB -01011b - 8MB -01100b - 16MB -01101b - 32MB -01110b - 64MB -01111b - 128MB -10000b - 256MB -10001b - 512MB -10010b - 1GB -10011b - 2GB -10100-11111b - 4GB - 1 - 5 - read-write - - - VLD - Valid - 0 - 1 - read-write - - - - - INTEN - Interrupt Enable Register - 0x38 - 32 - 0x00000000 - 0x0000000F - - - AXIBUSERR - AXI BUS error interrupt enable -0b - Interrupt is disabled -1b - Interrupt is enabled - 3 - 1 - read-write - - - AXICMDERR - AXI command error interrupt enable -0b - Interrupt is disabled -1b - Interrupt is enabled - 2 - 1 - read-write - - - IPCMDERR - IP command error interrupt enable -0b - Interrupt is disabled -1b - Interrupt is enabled - 1 - 1 - read-write - - - IPCMDDONE - IP command done interrupt enable -0b - Interrupt is disabled -1b - Interrupt is enabled - 0 - 1 - read-write - - - - - INTR - Interrupt Status Register - 0x3c - 32 - 0x00000000 - 0x0000000F - - - AXIBUSERR - AXI bus error interrupt -AXI Bus error interrupt is generated in following cases: -• AXI address is invalid -• AXI 8-bit or 16-bit WRAP write/read - 3 - 1 - write-only - - - AXICMDERR - AXI command error interrupt -AXI command error interrupt is generated when AXI command execution timeout. - 2 - 1 - write-only - - - IPCMDERR - IP command error done interrupt -IP command error interrupt is generated in following case: -• IP Command Address target invalid device space -• IP Command Code unsupported -• IP Command triggered when previous command - 1 - 1 - write-only - - - IPCMDDONE - IP command normal done interrupt - 0 - 1 - write-only - - - - - SDRCTRL0 - SDRAM Control Register 0 - 0x40 - 32 - 0x00000000 - 0x00004FFB - - - BANK2 - 2 Bank selection bit -0b - SDRAM device has 4 banks. -1b - SDRAM device has 2 banks. - 14 - 1 - read-write - - - CAS - CAS Latency -00b - 1 -01b - 1 -10b - 2 -11b - 3 - 10 - 2 - read-write - - - COL - Column address bit number -00b - 12 bit -01b - 11 bit -10b - 10 bit -11b - 9 bit - 8 - 2 - read-write - - - COL8 - Column 8 selection bit -0b - Column address bit number is decided by COL field. -1b - Column address bit number is 8. COL field is ignored. - 7 - 1 - read-write - - - BURSTLEN - Burst Length -000b - 1 -001b - 2 -010b - 4 -011b - 8 -100b - 8 -101b - 8 -110b - 8 -111b - 8 - 4 - 3 - read-write - - - HIGHBAND - high band select -0: use data[15:0] for 16bit SDRAM; -1: use data[31:16] for 16bit SDRAM; -only used when Port Size is 16bit(PORTSZ=01b) - 3 - 1 - read-write - - - PORTSZ - Port Size -00b - 8bit -01b - 16bit -10b - 32bit - 0 - 2 - read-write - - - - - SDRCTRL1 - SDRAM Control Register 1 - 0x44 - 32 - 0x00000000 - 0x00FFFFFF - - - ACT2PRE - ACT to Precharge minimum time -It is promised ACT2PRE+1 clock cycles delay between ACTIVE command to PRECHARGE/PRECHARGE_ALL command. - 20 - 4 - read-write - - - CKEOFF - CKE OFF minimum time -It is promised clock suspend last at leat CKEOFF+1 clock cycles. - 16 - 4 - read-write - - - WRC - Write recovery time -It is promised WRC+1 clock cycles delay between WRITE command to PRECHARGE/PRECHARGE_ALL command. This could help to meet tWR timing requirement by SDRAM device. - 13 - 3 - read-write - - - RFRC - Refresh recovery time -It is promised RFRC+1 clock cycles delay between REFRESH command to ACTIVE command. Thiscould help to meet tRFC timing requirement by SDRAM device. - 8 - 5 - read-write - - - ACT2RW - ACT to Read/Write wait time -It is promised ACT2RW+1 clock cycles delay between ACTIVE command to READ/WRITE command.This could help to meet tRCD timing requirement by SDRAM device. - 4 - 4 - read-write - - - PRE2ACT - PRECHARGE to ACT/Refresh wait time -It is promised PRE2ACT+1 clock cycles delay between PRECHARGE/PRECHARGE_ALL commandto ACTIVE/REFRESH command. This could help to meet tRP timing requirement by SDRAM device. - 0 - 4 - read-write - - - - - SDRCTRL2 - SDRAM Control Register 2 - 0x48 - 32 - 0x00000000 - 0xFFFFFFFF - - - ITO - SDRAM Idle timeout -It closes all opened pages if the SDRAM idle time lasts more than idle timeout period. SDRAM is -considered idle when there is no AXI Bus transfer and no SDRAM command pending. -00000000b - IDLE timeout period is 256*Prescale period. -00000001-11111111b - IDLE timeout period is ITO*Prescale period. - 24 - 8 - read-write - - - ACT2ACT - ACT to ACT wait time -It is promised ACT2ACT+1 clock cycles delay between ACTIVE command to ACTIVE command. This -could help to meet tRRD timing requirement by SDRAM device. - 16 - 8 - read-write - - - REF2REF - Refresh to Refresh wait time -It is promised REF2REF+1 clock cycles delay between REFRESH command to REFRESH command. -This could help to meet tRFC timing requirement by SDRAM device. - 8 - 8 - read-write - - - SRRC - Self Refresh Recovery time -It is promised SRRC+1 clock cycles delay between Self-REFRESH command to any command. - 0 - 8 - read-write - - - - - SDRCTRL3 - SDRAM Control Register 3 - 0x4c - 32 - 0x00000000 - 0xFFFFFF0F - - - UT - Refresh urgent threshold -Internal refresh request is generated on every Refresh period. Before internal request timer count up to -urgent request threshold, the refresh request is considered as normal refresh request. Normal refresh -request is handled in lower priority than any pending AXI command or IP command to SDRAM device. -When internal request timer count up to this urgent threshold, refresh request is considered as urgent -refresh request. Urgent refresh request is handled in higher priority than any pending AXI command or IP -command to SDRAM device. -NOTE: When urgent threshold is no less than refresh period, refresh request is always considered as -urgent refresh request. -Refresh urgent threshold is as follwoing: -00000000b - 256*Prescaler period -00000001-11111111b - UT*Prescaler period - 24 - 8 - read-write - - - RT - Refresh timer period -Refresh timer period is as following: -00000000b - 256*Prescaler period -00000001-11111111b - RT*Prescaler period - 16 - 8 - read-write - - - PRESCALE - Prescaler timer period -Prescaler timer period is as following: -00000000b - 256*16 clock cycles -00000001-11111111b - PRESCALE*16 clock cycles - 8 - 8 - read-write - - - REBL - Refresh burst length -It could send multiple Auto-Refresh command in one burst when REBL is set to non-zero. The -number of Auto-Refresh command cycle sent to all SDRAM device in one refresh period is as following. -000b - 1 -001b - 2 -010b - 3 -011b - 4 -100b - 5 -101b - 6 -110b - 7 -111b - 8 - 1 - 3 - read-write - - - REN - Refresh enable - 0 - 1 - read-write - - - - - SRCTRL0 - SRAM control register 0 - 0x70 - 32 - 0x00000000 - 0x00000F01 - - - ADVH - ADV hold state -0b - ADV is high during address hold state -1b - ADV is low during address hold state - 11 - 1 - read-write - - - ADVP - ADV polarity -0b - ADV is active low -1b - ADV is active high - 10 - 1 - read-write - - - ADM - address data mode -00b - address and data MUX mode -11b - address and data non-MUX mode - 8 - 2 - read-write - - - PORTSZ - port size -0b - 8bit -1b - 16bit - 0 - 1 - read-write - - - - - SRCTRL1 - SRAM control register 1 - 0x74 - 32 - 0x00000000 - 0xFFFFFFFF - - - OEH - OE high time, is OEH+1 clock cycles - 28 - 4 - read-write - - - OEL - OE low time, is OEL+1 clock cycles - 24 - 4 - read-write - - - WEH - WE high time, is WEH+1 clock cycles - 20 - 4 - read-write - - - WEL - WE low time, is WEL+1 clock cycles - 16 - 4 - read-write - - - AH - Address hold time, is AH+1 clock cycles - 12 - 4 - read-write - - - AS - Address setup time, is AS+1 clock cycles - 8 - 4 - read-write - - - CEH - Chip enable hold time, is CEH+1 clock cycles - 4 - 4 - read-write - - - CES - Chip enable setup time, is CES+1 clock cycles - 0 - 4 - read-write - - - - - SADDR - IP Command Control Register 0 - 0x90 - 32 - 0x00000000 - 0xFFFFFFFF - - - SA - Slave address - 0 - 32 - read-write - - - - - DATSZ - IP Command Control Register 1 - 0x94 - 32 - 0x00000000 - 0x00000007 - - - DATSZ - Data Size in Byte -When IP command is not a write/read operation, DATSZ field would be ignored. -000b - 4 -001b - 1 -010b - 2 -011b - 3 -100b - 4 -101b - 4 -110b - 4 -111b - 4 - 0 - 3 - read-write - - - - - BYTEMSK - IP Command Control Register 2 - 0x98 - 32 - 0x00000000 - 0x0000000F - - - BM3 - Byte Mask for Byte 3 (IPTXD bit 31:24) -0b - Byte Unmasked -1b - Byte Masked - 3 - 1 - read-write - - - BM2 - Byte Mask for Byte 2 (IPTXD bit 23:16) -0b - Byte Unmasked -1b - Byte Masked - 2 - 1 - read-write - - - BM1 - Byte Mask for Byte 1 (IPTXD bit 15:8) -0b - Byte Unmasked -1b - Byte Masked - 1 - 1 - read-write - - - BM0 - Byte Mask for Byte 0 (IPTXD bit 7:0) -0b - Byte Unmasked -1b - Byte Masked - 0 - 1 - read-write - - - - - IPCMD - IP Command Register - 0x9c - 32 - 0x00000000 - 0xFFFFFFFF - - - KEY - This field should be written with 0x5AA5 when trigging an IP command for all device types. The memory -device is selected by BRx settings and IPCR0 registers. - 16 - 16 - write-only - - - CMD - SDRAM Commands: -• 0x8: READ -• 0x9: WRITE -• 0xA: MODESET -• 0xB: ACTIVE -• 0xC: AUTO REFRESH -• 0xD: SELF REFRESH -• 0xE: PRECHARGE -• 0xF: PRECHARGE ALL -• Others: RSVD -NOTE: SELF REFRESH is sent to all SDRAM devices because they shared same CLK pin. - 0 - 16 - read-write - - - - - IPTX - TX DATA Register - 0xa0 - 32 - 0x00000000 - 0xFFFFFFFF - - - DAT - Data - 0 - 32 - read-write - - - - - IPRX - RX DATA Register - 0xb0 - 32 - 0x00000000 - 0xFFFFFFFF - - - DAT - Data - 0 - 32 - read-write - - - - - STAT0 - Status Register 0 - 0xc0 - 32 - 0x00000000 - 0x00000001 - - - IDLE - Indicating whether it is in IDLE state. -When IDLE=1, it is in IDLE state. There is no pending AXI command in internal queue and no -pending device access. - 0 - 1 - read-only - - - - - DLYCFG - Delay Line Config Register - 0x150 - 32 - 0x00000000 - 0x0000203F - - - OE - delay clock output enable, should be set after setting DLYEN and DLYSEL - 13 - 1 - read-write - - - DLYSEL - delay line select, 0 for 1 cell, 31 for all 32 cells - 1 - 5 - read-write - - - DLYEN - delay line enable - 0 - 1 - read-write - - - - - - - SYSCTL - SYSCTL - SYSCTL - 0xf4000000 - - 0x0 - 0x3000 - registers - - - - 350 - 0x4 - cpu0_core,cpu0_subsys,rsv2,rsv3,rsv4,rsv5,rsv6,rsv7,cpu1_core,cpx1_subsys,rsv10,rsv11,rsv12,rsv13,rsv14,rsv15,rsv16,rsv17,rsv18,rsv19,rsv20,pow_con,pow_vis,pow_cpu0,pow_cpu1,rst_soc,rst_con,rst_vis,rst_cpu0,rst_cpu1,rsv30,rsv31,clk_src_xtal,clk_src_pll0,clk_src_pll0clk0,clk_src_pll1,clk_src_pll1clk0,clk_src_pll1clk1,clk_src_pll2,clk_src_pll2clk0,clk_src_pll2clk1,clk_src_pll3,clk_src_pll3clk0,clk_src_pll4,clk_src_pll4clk0,rsv45,rsv46,rsv47,rsv48,rsv49,rsv50,rsv51,rsv52,rsv53,rsv54,rsv55,rsv56,rsv57,rsv58,rsv59,rsv60,rsv61,rsv62,rsv63,clk_top_cpu0,clk_top_mchtmr0,clk_top_cpu1,clk_top_mchtmr1,clk_top_axi,clk_top_conn,clk_top_vis,clk_top_ahb,clk_top_femc,clk_top_xpi0,clk_top_xpi1,clk_top_gptmr0,clk_top_gptmr1,clk_top_gptmr2,clk_top_gptmr3,clk_top_gptmr4,clk_top_gptmr5,clk_top_gptmr6,clk_top_gptmr7,clk_top_uart0,clk_top_uart1,clk_top_uart2,clk_top_uart3,clk_top_uart4,clk_top_uart5,clk_top_uart6,clk_top_uart7,clk_top_uart8,clk_top_uart9,clk_top_uart10,clk_top_uart11,clk_top_uart12,clk_top_uart13,clk_top_uart14,clk_top_uart15,clk_top_i2c0,clk_top_i2c1,clk_top_i2c2,clk_top_i2c3,clk_top_spi0,clk_top_spi1,clk_top_spi2,clk_top_spi3,clk_top_can0,clk_top_can1,clk_top_can2,clk_top_can3,clk_top_ptpc,clk_top_ana0,clk_top_ana1,clk_top_ana2,clk_top_aud0,clk_top_aud1,clk_top_aud2,clk_top_lcdc,clk_top_cam0,clk_top_cam1,clk_top_enet0,clk_top_enet1,clk_top_ptp0,clk_top_ptp1,clk_top_ref0,clk_top_ref1,clk_top_ntmr0,clk_top_ntmr1,clk_top_sdxc0,clk_top_sdxc1,rsv131,rsv132,rsv133,rsv134,rsv135,rsv136,rsv137,rsv138,rsv139,rsv140,rsv141,rsv142,rsv143,rsv144,rsv145,rsv146,rsv147,rsv148,rsv149,rsv150,rsv151,rsv152,rsv153,rsv154,rsv155,rsv156,rsv157,rsv158,rsv159,rsv160,rsv161,rsv162,rsv163,rsv164,rsv165,rsv166,rsv167,rsv168,rsv169,rsv170,rsv171,rsv172,rsv173,rsv174,rsv175,rsv176,rsv177,rsv178,rsv179,rsv180,rsv181,rsv182,rsv183,rsv184,rsv185,rsv186,rsv187,rsv188,rsv189,rsv190,rsv191,clk_top_adc0,clk_top_adc1,clk_top_adc2,clk_top_adc3,clk_top_i2s0,clk_top_i2s1,clk_top_i2s2,clk_top_i2s3,rsv200,rsv201,rsv202,rsv203,rsv204,rsv205,rsv206,rsv207,rsv208,rsv209,rsv210,rsv211,rsv212,rsv213,rsv214,rsv215,rsv216,rsv217,rsv218,rsv219,rsv220,rsv221,rsv222,rsv223,rsv224,rsv225,rsv226,rsv227,rsv228,rsv229,rsv230,rsv231,rsv232,rsv233,rsv234,rsv235,rsv236,rsv237,rsv238,rsv239,rsv240,rsv241,rsv242,rsv243,rsv244,rsv245,rsv246,rsv247,rsv248,rsv249,rsv250,rsv251,rsv252,rsv253,rsv254,rsv255,ahbapb_bus,axi_bus,conn_bus,vis_bus,femc,rom,lmm0,lmm1,mchtmr0,mchtmr1,axi_sram0,axi_sram1,xpi0,xpi1,sdp,rng,keym,hdma,xdma,gpio,mbx0,mbx1,wdg0,wdg1,wdg2,wdg3,gptmr0,gptmr1,gptmr2,gptmr3,gptmr4,gptmr5,gptmr6,gptmr7,uart0,uart1,uart2,uart3,uart4,uart5,uart6,uart7,uart8,uart9,uart10,uart11,uart12,uart13,uart14,uart15,i2c0,i2c1,i2c2,i2c3,spi0,spi1,spi2,spi3,can0,can1,can2,can3,ptpc,adc0,adc1,adc2,adc3,acmp,i2s0,i2s1,i2s2,i2s3,pdm,dao,synt,mot0,mot1,mot2,mot3,lcdc,cam0,cam1,jpeg,pdma,enet0,enet1,ntmr0,ntmr1,sdxc0,sdxc1,usb0,usb1,ref0,ref1 - RESOURCE[%s] - no description available - 0x0 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - 3 - 0x10 - 0,1,2 - GROUP0[%s] - no description available - 0x800 - - VALUE - Goup setting - 0x0 - 32 - 0x00000023 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral -0: peripheral is not needed -1: periphera is needed - 0 - 32 - read-write - - - - - SET - Goup setting - 0x4 - 32 - 0x00000023 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral -0: peripheral is not needed -1: periphera is needed - 0 - 32 - read-write - - - - - CLEAR - Goup setting - 0x8 - 32 - 0x00000023 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral -0: peripheral is not needed -1: periphera is needed - 0 - 32 - read-write - - - - - TOGGLE - Goup setting - 0xc - 32 - 0x00000023 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral -0: peripheral is not needed -1: periphera is needed - 0 - 32 - read-write - - - - - - 3 - 0x10 - 0,1,2 - GROUP1[%s] - no description available - 0x840 - - VALUE - Goup setting - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral -0: peripheral is not needed -1: periphera is needed - 0 - 32 - read-write - - - - - SET - Goup setting - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral -0: peripheral is not needed -1: periphera is needed - 0 - 32 - read-write - - - - - CLEAR - Goup setting - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral -0: peripheral is not needed -1: periphera is needed - 0 - 32 - read-write - - - - - TOGGLE - Goup setting - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral -0: peripheral is not needed -1: periphera is needed - 0 - 32 - read-write - - - - - - 2 - 0x10 - cpu0,cpu1 - AFFILIATE[%s] - no description available - 0x900 - - VALUE - Affiliate of Group - 0x0 - 32 - 0x00000001 - 0x0000000F - - - LINK - Affiliate groups of cpu0 -bit0: cpu0 depends on logic node0 -bit1: cpu0 depends on logic node1 -bit2: cpu0 depends on logic node2 -bit3: cpu0 depends on logic node3 - 0 - 4 - read-write - - - - - SET - Affiliate of Group - 0x4 - 32 - 0x00000001 - 0x0000000F - - - LINK - Affiliate groups of cpu0 -bit0: cpu0 depends on logic node0 -bit1: cpu0 depends on logic node1 -bit2: cpu0 depends on logic node2 -bit3: cpu0 depends on logic node3 - 0 - 4 - read-write - - - - - CLEAR - Affiliate of Group - 0x8 - 32 - 0x00000001 - 0x0000000F - - - LINK - Affiliate groups of cpu0 -bit0: cpu0 depends on logic node0 -bit1: cpu0 depends on logic node1 -bit2: cpu0 depends on logic node2 -bit3: cpu0 depends on logic node3 - 0 - 4 - read-write - - - - - TOGGLE - Affiliate of Group - 0xc - 32 - 0x00000001 - 0x0000000F - - - LINK - Affiliate groups of cpu0 -bit0: cpu0 depends on logic node0 -bit1: cpu0 depends on logic node1 -bit2: cpu0 depends on logic node2 -bit3: cpu0 depends on logic node3 - 0 - 4 - read-write - - - - - - 2 - 0x10 - cpu0,cpu1 - RETENTION[%s] - no description available - 0x920 - - VALUE - Retention Control - 0x0 - 32 - 0x0000000F - 0x0003FFFF - - - LINK - retention setting while system sleep, each bit represents a resource -bit0: soc_pow -bit1: soc_rst -bit2: cpu0_pow -bit3: cpu0_rst -bit4: cpu1_pow -bit5: cpu1_rst -bit6: con_pow -bit7: con_rst -bit8: vis_pow -bit9: vis_rst -bit10: xtal -bit11: pll0 -bit12: pll1 -bit13: pll2 -bit14: pll3 -bit15: pll4 - 0 - 18 - read-write - - - - - SET - Retention Control - 0x4 - 32 - 0x0000000F - 0x0003FFFF - - - LINK - retention setting while system sleep - 0 - 18 - read-write - - - - - CLEAR - Retention Control - 0x8 - 32 - 0x0000000F - 0x0003FFFF - - - LINK - retention setting while system sleep - 0 - 18 - read-write - - - - - TOGGLE - Retention Control - 0xc - 32 - 0x0000000F - 0x0003FFFF - - - LINK - retention setting while system sleep - 0 - 18 - read-write - - - - - - 4 - 0x10 - cpu0,cpu1,con,vis - POWER[%s] - no description available - 0x1000 - - status - Power Setting - 0x0 - 32 - 0x80000000 - 0xC0001100 - - - FLAG - flag represents power cycle happened from last clear of this bit -0: power domain did not edurance power cycle since last clear of this bit -1: power domain enduranced power cycle since last clear of this bit - 31 - 1 - read-write - - - FLAG_WAKE - flag represents wakeup power cycle happened from last clear of this bit -0: power domain did not edurance wakeup power cycle since last clear of this bit -1: power domain enduranced wakeup power cycle since last clear of this bit - 30 - 1 - read-write - - - LF_DISABLE - low fanout power switch disable -0: low fanout power switches are turned on -1: low fanout power switches are truned off - 12 - 1 - read-only - - - LF_ACK - low fanout power switch feedback -0: low fanout power switches are turned on -1: low fanout power switches are truned off - 8 - 1 - read-only - - - - - lf_wait - Power Setting - 0x4 - 32 - 0x00000255 - 0x000FFFFF - - - WAIT - wait time for low fan out power switch turn on, default value is 255 -0: 0 clock cycle -1: 1 clock cycles -. . . -clock cycles count on 24MHz - 0 - 20 - read-write - - - - - off_wait - Power Setting - 0xc - 32 - 0x00000015 - 0x000FFFFF - - - WAIT - wait time for power switch turn off, default value is 15 -0: 0 clock cycle -1: 1 clock cycles -. . . -clock cycles count on 24MHz - 0 - 20 - read-write - - - - - - 5 - 0x10 - soc,con,vis,cpu0,cpu1 - RESET[%s] - no description available - 0x1400 - - control - Reset Setting - 0x0 - 32 - 0x80000000 - 0xC0000011 - - - FLAG - flag represents reset happened from last clear of this bit -0: domain did not edurance reset cycle since last clear of this bit -1: domain enduranced reset cycle since last clear of this bit - 31 - 1 - read-write - - - FLAG_WAKE - flag represents wakeup reset happened from last clear of this bit -0: domain did not edurance wakeup reset cycle since last clear of this bit -1: domain enduranced wakeup reset cycle since last clear of this bit - 30 - 1 - read-write - - - HOLD - perform reset and hold in reset, until ths bit cleared by software -0: reset is released for function -1: reset is assert and hold - 4 - 1 - read-write - - - RESET - perform reset and release imediately -0: reset is released -1 reset is asserted and will release automatically - 0 - 1 - read-write - - - - - config - Reset Setting - 0x4 - 32 - 0x00643203 - 0x00FFFFFF - - - PRE_WAIT - wait cycle numbers before assert reset -0: wait 0 cycle -1: wait 1 cycles -. . . -Note, clock cycle is base on 24M - 16 - 8 - read-write - - - RSTCLK_NUM - reset clock number(must be even number) -0: 0 cycle -1: 0 cycles -2: 2 cycles -3: 2 cycles -. . . -Note, clock cycle is base on 24M - 8 - 8 - read-write - - - POST_WAIT - time guard band for reset release -0: wait 0 cycle -1: wait 1 cycles -. . . -Note, clock cycle is base on 24M - 0 - 8 - read-write - - - - - counter - Reset Setting - 0xc - 32 - 0x00000000 - 0x000FFFFF - - - COUNTER - self clear trigger counter, reset triggered when counter value is 1, write 0 will cancel reset -0: wait 0 cycle -1: wait 1 cycles -. . . -Note, clock cycle is base on 24M - 0 - 20 - read-write - - - - - - 67 - 0x4 - clk_top_cpu0,clk_top_mchtmr0,clk_top_cpu1,clk_top_mchtmr,clk_top_axi,clk_top_conn,clk_top_vis,clk_top_ahb,clk_top_femc,clk_top_xpi0,clk_top_xpi1,clk_top_gptmr0,clk_top_gptmr1,clk_top_gptmr2,clk_top_gptmr3,clk_top_gptmr4,clk_top_gptmr5,clk_top_gptmr6,clk_top_gptmr7,clk_top_uart0,clk_top_uart1,clk_top_uart2,clk_top_uart3,clk_top_uart4,clk_top_uart5,clk_top_uart6,clk_top_uart7,clk_top_uart8,clk_top_uart9,clk_top_uart10,clk_top_uart11,clk_top_uart12,clk_top_uart13,clk_top_uart14,clk_top_uart15,clk_top_i2c0,clk_top_i2c1,clk_top_i2c2,clk_top_i2c3,clk_top_spi0,clk_top_spi1,clk_top_spi2,clk_top_spi3,clk_top_can0,clk_top_can1,clk_top_can2,clk_top_can3,clk_top_ptpc,clk_top_ana0,clk_top_ana1,clk_top_ana2,clk_top_aud0,clk_top_aud1,clk_top_aud2,clk_top_lcdc,clk_top_cam0,clk_top_cam1,clk_top_enet0,clk_top_enet1,clk_top_ptp0,clk_top_ptp1,clk_top_ref0,clk_top_ref1,clk_top_ntmr0,clk_top_ntmr1,clk_top_sdxc0,clk_top_sdxc1 - CLOCK[%s] - no description available - 0x1800 - 32 - 0x00000000 - 0xC0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0:osc0_clk0 -1:pll0_clk0 -2:pll1_clk0 -3:pll1_clk1 -4:pll2_clk0 -5:pll2_clk1 -6:pll3_clk0 -7:pll4_clk0 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by1 -1: divider by 2 -2 divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - 4 - 0x4 - clk_top_adc0,clk_top_adc1,clk_top_adc2,clk_top_adc3 - ADCCLK[%s] - no description available - 0x1c00 - 32 - 0x00000000 - 0xC0000700 - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0: ahb clock -1: adc clock 0 -2: adc clock 1 -3: adc clock 2 - 8 - 3 - read-write - - - - - 4 - 0x4 - clk_top_i2s0,clk_top_i2s1,clk_top_i2s2,clk_top_i2s3 - I2SCLK[%s] - no description available - 0x1c10 - 32 - 0x00000000 - 0xC0000700 - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0: ahb clock -1: i2s clock 0 -2: i2s clock 1 -3: i2s clock 2 - 8 - 3 - read-write - - - - - global00 - Clock senario - 0x2000 - 32 - 0x00000000 - 0x0000000F - - - PRESET - global clock override request -bit0: override to preset0 -bit1: override to preset1 -bit2: override to preset2 -bit3: override to preset3 - 0 - 4 - read-write - - - - - 4 - 0x20 - slice0,slice1,slice2,slice3 - MONITOR[%s] - no description available - 0x2400 - - control - Clock measure and monitor control - 0x0 - 32 - 0x00000000 - 0x89FFD7FF - - - VALID - result is ready for read -0: not ready -1: result is ready - 31 - 1 - read-write - - - DIV_BUSY - divider is applying new setting - 27 - 1 - read-only - - - OUTEN - enable clock output - 24 - 1 - read-write - - - DIV - output divider - 16 - 8 - read-write - - - HIGH - clock frequency higher than upper limit - 15 - 1 - read-write - - - LOW - clock frequency lower than lower limit - 14 - 1 - read-write - - - START - start measurement - 12 - 1 - read-write - - - MODE - work mode, -0: register value will be compared to measurement -1: upper and lower value will be recordered in register - 10 - 1 - read-write - - - ACCURACY - measurement accuracy, -0: resolution is 1kHz -1: resolution is 1Hz - 9 - 1 - read-write - - - REFERENCE - reference clock selection, -0: 32k -1: 24M - 8 - 1 - read-write - - - SELECTION - clock measurement selection - 0 - 8 - read-write - - - - - current - Clock measure result - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - FREQUENCY - self updating measure result - 0 - 32 - read-only - - - - - low_limit - Clock lower limit - 0x8 - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - FREQUENCY - lower frequency - 0 - 32 - read-write - - - - - high_limit - Clock upper limit - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - FREQUENCY - upper frequency - 0 - 32 - read-write - - - - - - 2 - 0x400 - cpu0,cpu1 - CPU[%s] - no description available - 0x2800 - - LP - No description available - 0x0 - 32 - 0x00001200 - 0xFF013703 - - - WAKE_CNT - CPU0 wake up counter, counter saturated at 255, write 0x00 to clear - 24 - 8 - read-write - - - HALT - halt request for CPU0, -0: CPU0 will start to execute after reset or receive wakeup request -1: CPU0 will not start after reset, or wakeup after WFI - 16 - 1 - read-write - - - WAKE - CPU0 is waking up -0: CPU0 wake up not asserted -1: CPU0 wake up asserted - 13 - 1 - read-only - - - EXEC - CPU0 is executing -0: CPU0 is not executing -1: CPU0 is executing - 12 - 1 - read-only - - - WAKE_FLAG - CPU0 wakeup flag, indicate a wakeup event got active, write 1 to clear this bit -0: CPU0 wakeup not happened -1: CPU0 wakeup happened - 10 - 1 - read-write - - - SLEEP_FLAG - CPU0 sleep flag, indicate a sleep event got active, write 1 to clear this bit -0: CPU0 sleep not happened -1: CPU0 sleep happened - 9 - 1 - read-write - - - RESET_FLAG - CPU0 reset flag, indicate a reset event got active, write 1 to clear this bit -0: CPU0 sleep not happened -1: CPU0 sleep happened - 8 - 1 - read-write - - - MODE - Low power mode, system behavior after WFI -00: CPU clock stop after WFI -01: System enter low power mode after WFI -10: Keep running after WFI -11: reserved - 0 - 2 - read-write - - - - - LOCK - No description available - 0x4 - 32 - 0x00000002 - 0x0000FFFE - - - GPR - Lock bit for CPU_DATA0 to CPU_DATA13, once set, this bit will not clear untile next reset - 2 - 14 - read-write - - - LOCK - Lock bit for CPU_LOCK - 1 - 1 - read-write - - - - - 14 - 0x4 - GPR0,GPR1,GPR2,GPR3,GPR4,GPR5,GPR6,GPR7,GPR8,GPR9,GPR10,GPR11,GPR12,GPR13 - GPR[%s] - no description available - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - register for software to handle resume, can save resume address or status - 0 - 32 - read-write - - - - - 8 - 0x4 - STATUS0,STATUS1,STATUS2,STATUS3,STATUS4,STATUS5,STATUS6,STATUS7 - WAKEUP_STATUS[%s] - no description available - 0x40 - 32 - 0x00000000 - 0xFFFFFFFF - - - STATUS - IRQ values - 0 - 32 - read-only - - - - - 8 - 0x4 - ENABLE0,ENABLE1,ENABLE2,ENABLE3,ENABLE4,ENABLE5,ENABLE6,ENABLE7 - WAKEUP_ENABLE[%s] - no description available - 0x80 - 32 - 0x00000000 - 0xFFFFFFFF - - - ENABLE - IRQ wakeup enable - 0 - 32 - read-write - - - - - - - - IOC - IOC - IOC - 0xf4040000 - - 0x0 - 0xf60 - registers - - - - 492 - 0x8 - pa00,pa01,pa02,pa03,pa04,pa05,pa06,pa07,pa08,pa09,pa10,pa11,pa12,pa13,pa14,pa15,pa16,pa17,pa18,pa19,pa20,pa21,pa22,pa23,pa24,pa25,pa26,pa27,pa28,pa29,pa30,pa31,pb00,pb01,pb02,pb03,pb04,pb05,pb06,pb07,pb08,pb09,pb10,pb11,pb12,pb13,pb14,pb15,pb16,pb17,pb18,pb19,pb20,pb21,pb22,pb23,pb24,pb25,pb26,pb27,pb28,pb29,pb30,pb31,pc00,pc01,pc02,pc03,pc04,pc05,pc06,pc07,pc08,pc09,pc10,pc11,pc12,pc13,pc14,pc15,pc16,pc17,pc18,pc19,pc20,pc21,pc22,pc23,pc24,pc25,pc26,pc27,pc28,pc29,pc30,pc31,pd00,pd01,pd02,pd03,pd04,pd05,pd06,pd07,pd08,pd09,pd10,pd11,pd12,pd13,pd14,pd15,pd16,pd17,pd18,pd19,pd20,pd21,pd22,pd23,pd24,pd25,pd26,pd27,pd28,pd29,pd30,pd31,pe00,pe01,pe02,pe03,pe04,pe05,pe06,pe07,pe08,pe09,pe10,pe11,pe12,pe13,pe14,pe15,pe16,pe17,pe18,pe19,pe20,pe21,pe22,pe23,pe24,pe25,pe26,pe27,pe28,pe29,pe30,pe31,pf00,pf01,pf02,pf03,pf04,pf05,pf06,pf07,pf08,pf09,pf10,rsv171,rsv172,rsv173,rsv174,rsv175,rsv176,rsv177,rsv178,rsv179,rsv180,rsv181,rsv182,rsv183,rsv184,rsv185,rsv186,rsv187,rsv188,rsv189,rsv190,rsv191,rsv192,rsv193,rsv194,rsv195,rsv196,rsv197,rsv198,rsv199,rsv200,rsv201,rsv202,rsv203,rsv204,rsv205,rsv206,rsv207,rsv208,rsv209,rsv210,rsv211,rsv212,rsv213,rsv214,rsv215,rsv216,rsv217,rsv218,rsv219,rsv220,rsv221,rsv222,rsv223,rsv224,rsv225,rsv226,rsv227,rsv228,rsv229,rsv230,rsv231,rsv232,rsv233,rsv234,rsv235,rsv236,rsv237,rsv238,rsv239,rsv240,rsv241,rsv242,rsv243,rsv244,rsv245,rsv246,rsv247,rsv248,rsv249,rsv250,rsv251,rsv252,rsv253,rsv254,rsv255,rsv256,rsv257,rsv258,rsv259,rsv260,rsv261,rsv262,rsv263,rsv264,rsv265,rsv266,rsv267,rsv268,rsv269,rsv270,rsv271,rsv272,rsv273,rsv274,rsv275,rsv276,rsv277,rsv278,rsv279,rsv280,rsv281,rsv282,rsv283,rsv284,rsv285,rsv286,rsv287,rsv288,rsv289,rsv290,rsv291,rsv292,rsv293,rsv294,rsv295,rsv296,rsv297,rsv298,rsv299,rsv300,rsv301,rsv302,rsv303,rsv304,rsv305,rsv306,rsv307,rsv308,rsv309,rsv310,rsv311,rsv312,rsv313,rsv314,rsv315,rsv316,rsv317,rsv318,rsv319,rsv320,rsv321,rsv322,rsv323,rsv324,rsv325,rsv326,rsv327,rsv328,rsv329,rsv330,rsv331,rsv332,rsv333,rsv334,rsv335,rsv336,rsv337,rsv338,rsv339,rsv340,rsv341,rsv342,rsv343,rsv344,rsv345,rsv346,rsv347,rsv348,rsv349,rsv350,rsv351,rsv352,rsv353,rsv354,rsv355,rsv356,rsv357,rsv358,rsv359,rsv360,rsv361,rsv362,rsv363,rsv364,rsv365,rsv366,rsv367,rsv368,rsv369,rsv370,rsv371,rsv372,rsv373,rsv374,rsv375,rsv376,rsv377,rsv378,rsv379,rsv380,rsv381,rsv382,rsv383,rsv384,rsv385,rsv386,rsv387,rsv388,rsv389,rsv390,rsv391,rsv392,rsv393,rsv394,rsv395,rsv396,rsv397,rsv398,rsv399,rsv400,rsv401,rsv402,rsv403,rsv404,rsv405,rsv406,rsv407,rsv408,rsv409,rsv410,rsv411,rsv412,rsv413,rsv414,rsv415,px00,px01,px02,px03,px04,px05,px06,px07,px08,px09,px10,px11,rsv428,rsv429,rsv430,rsv431,rsv432,rsv433,rsv434,rsv435,rsv436,rsv437,rsv438,rsv439,rsv440,rsv441,rsv442,rsv443,rsv444,rsv445,rsv446,rsv447,py00,py01,py02,py03,py04,py05,py06,py07,py08,py09,py10,py11,rsv460,rsv461,rsv462,rsv463,rsv464,rsv465,rsv466,rsv467,rsv468,rsv469,rsv470,rsv471,rsv472,rsv473,rsv474,rsv475,rsv476,rsv477,rsv478,rsv479,pz00,pz01,pz02,pz03,pz04,pz05,pz06,pz07,pz08,pz09,pz10,pz11 - PAD[%s] - no description available - 0x0 - - FUNC_CTL - ALT SELECT - 0x0 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_CTL - PAD SETTINGS - 0x4 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only available in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - - - - PIOC - PIOC - IOC - 0xf40d8000 - - - BIOC - BIOC - IOC - 0xf5010000 - - - OTPSHW - OTPSHW - OTP - 0xf4080000 - - 0x0 - 0xc08 - registers - - - - 128 - 0x4 - SHADOW000,SHADOW001,SHADOW002,SHADOW003,SHADOW004,SHADOW005,SHADOW006,SHADOW007,SHADOW008,SHADOW009,SHADOW010,SHADOW011,SHADOW012,SHADOW013,SHADOW014,SHADOW015,SHADOW016,SHADOW017,SHADOW018,SHADOW019,SHADOW020,SHADOW021,SHADOW022,SHADOW023,SHADOW024,SHADOW025,SHADOW026,SHADOW027,SHADOW028,SHADOW029,SHADOW030,SHADOW031,SHADOW032,SHADOW033,SHADOW034,SHADOW035,SHADOW036,SHADOW037,SHADOW038,SHADOW039,SHADOW040,SHADOW041,SHADOW042,SHADOW043,SHADOW044,SHADOW045,SHADOW046,SHADOW047,SHADOW048,SHADOW049,SHADOW050,SHADOW051,SHADOW052,SHADOW053,SHADOW054,SHADOW055,SHADOW056,SHADOW057,SHADOW058,SHADOW059,SHADOW060,SHADOW061,SHADOW062,SHADOW063,SHADOW064,SHADOW065,SHADOW066,SHADOW067,SHADOW068,SHADOW069,SHADOW070,SHADOW071,SHADOW072,SHADOW073,SHADOW074,SHADOW075,SHADOW076,SHADOW077,SHADOW078,SHADOW079,SHADOW080,SHADOW081,SHADOW082,SHADOW083,SHADOW084,SHADOW085,SHADOW086,SHADOW087,SHADOW088,SHADOW089,SHADOW090,SHADOW091,SHADOW092,SHADOW093,SHADOW094,SHADOW095,SHADOW096,SHADOW097,SHADOW098,SHADOW099,SHADOW100,SHADOW101,SHADOW102,SHADOW103,SHADOW104,SHADOW105,SHADOW106,SHADOW107,SHADOW108,SHADOW109,SHADOW110,SHADOW111,SHADOW112,SHADOW113,SHADOW114,SHADOW115,SHADOW116,SHADOW117,SHADOW118,SHADOW119,SHADOW120,SHADOW121,SHADOW122,SHADOW123,SHADOW124,SHADOW125,SHADOW126,SHADOW127 - SHADOW[%s] - no description available - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - 8 - 0x4 - LOCK00,LOCK01,LOCK02,LOCK03,LOCK04,LOCK05,LOCK06,LOCK07 - SHADOW_LOCK[%s] - no description available - 0x200 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK - lock for pmic part shadow registers, 2 bits per 32 bit word, lock behavior is different between different fuse types -00: not locked -01: soft locked -10: not locked, and cannot lock in furture -11: double locked - 0 - 32 - read-write - - - - - 128 - 0x4 - FUSE000,FUSE001,FUSE002,FUSE003,FUSE004,FUSE005,FUSE006,FUSE007,FUSE008,FUSE009,FUSE010,FUSE011,FUSE012,FUSE013,FUSE014,FUSE015,FUSE016,FUSE017,FUSE018,FUSE019,FUSE020,FUSE021,FUSE022,FUSE023,FUSE024,FUSE025,FUSE026,FUSE027,FUSE028,FUSE029,FUSE030,FUSE031,FUSE032,FUSE033,FUSE034,FUSE035,FUSE036,FUSE037,FUSE038,FUSE039,FUSE040,FUSE041,FUSE042,FUSE043,FUSE044,FUSE045,FUSE046,FUSE047,FUSE048,FUSE049,FUSE050,FUSE051,FUSE052,FUSE053,FUSE054,FUSE055,FUSE056,FUSE057,FUSE058,FUSE059,FUSE060,FUSE061,FUSE062,FUSE063,FUSE064,FUSE065,FUSE066,FUSE067,FUSE068,FUSE069,FUSE070,FUSE071,FUSE072,FUSE073,FUSE074,FUSE075,FUSE076,FUSE077,FUSE078,FUSE079,FUSE080,FUSE081,FUSE082,FUSE083,FUSE084,FUSE085,FUSE086,FUSE087,FUSE088,FUSE089,FUSE090,FUSE091,FUSE092,FUSE093,FUSE094,FUSE095,FUSE096,FUSE097,FUSE098,FUSE099,FUSE100,FUSE101,FUSE102,FUSE103,FUSE104,FUSE105,FUSE106,FUSE107,FUSE108,FUSE109,FUSE110,FUSE111,FUSE112,FUSE113,FUSE114,FUSE115,FUSE116,FUSE117,FUSE118,FUSE119,FUSE120,FUSE121,FUSE122,FUSE123,FUSE124,FUSE125,FUSE126,FUSE127 - FUSE[%s] - no description available - 0x400 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - 8 - 0x4 - LOCK00,LOCK01,LOCK02,LOCK03,LOCK04,LOCK05,LOCK06,LOCK07 - FUSE_LOCK[%s] - no description available - 0x600 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK - lock for fuse array, 2 bits per 32 bit word, lock behavior is different between different fuse types -00: not locked -01: soft locked -10: not locked, and cannot lock in furture -11: double locked - 0 - 32 - read-write - - - - - UNLOCK - UNLOCK - 0x800 - 32 - 0x00000000 - 0xFFFFFFFF - - - UNLOCK - unlock word for fuse array operation -write "OPEN" to unlock fuse array, write any other value will lock write to fuse. -Please make sure 24M crystal is running and 2.5V LDO working properly - 0 - 32 - read-write - - - - - DATA - DATA - 0x804 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - data register for non-blocking access -this register hold dat read from fuse array or data to by programmed to fuse array - 0 - 32 - read-write - - - - - ADDR - ADDR - 0x808 - 32 - 0x00000000 - 0x0000007F - - - ADDR - word address to be read or write - 0 - 7 - read-write - - - - - CMD - CMD - 0x80c - 32 - 0x00000000 - 0xFFFFFFFF - - - CMD - command to access fure array -"BLOW" will update fuse word at ADDR to value hold in DATA -"READ" will fetch fuse value in at ADDR to DATA register - 0 - 32 - read-write - - - - - LOAD_REQ - LOAD Request - 0xa00 - 32 - 0x00000007 - 0x0000000F - - - REQUEST - reload request for 4 regions -bit0: region0 -bit1: region1 -bit2: region2 -bit3: region3 - 0 - 4 - read-write - - - - - LOAD_COMP - LOAD complete - 0xa04 - 32 - 0x00000007 - 0x0000000F - - - COMPLETE - reload complete sign for 4 regions -bit0: region 0 -bit1: region1 -bit2: region2 -bit3: region3 - 0 - 4 - read-write - - - - - 4 - 0x4 - LOAD_REGION0,LOAD_REGION1,LOAD_REGION2,LOAD_REGION3 - REGION[%s] - no description available - 0xa20 - 32 - 0x00000800 - 0x00007F7F - - - STOP - stop address of load region, fuse word at end address will NOT be reloaded -region0: fixed at 8 -region1: fixed at 16 -region2: fixed at 0, -region3: usrer configurable - 8 - 7 - read-write - - - START - start address of load region, fuse word at start address will be reloaded -region0: fixed at 0 -region1: fixed at 8 -region2: fixed at 16, -region3: usrer configurable - 0 - 7 - read-write - - - - - INT_FLAG - interrupt flag - 0xc00 - 32 - 0x00000000 - 0x00000007 - - - WRITE - fuse write flag, write 1 to clear -0: fuse is not written or writing -1: value in DATA register is programmed into fuse - 2 - 1 - read-write - - - READ - fuse read flag, write 1 to clear -0: fuse is not read or reading -1: fuse value is put in DATA register - 1 - 1 - read-write - - - LOAD - fuse load flag, write 1 to clear -0: fuse is not loaded or loading -1: fuse loaded - 0 - 1 - read-write - - - - - INT_EN - interrupt enable - 0xc04 - 32 - 0x00000000 - 0x00000007 - - - WRITE - fuse write interrupt enable -0: fuse write interrupt is not enable -1: fuse write interrupt is enable - 2 - 1 - read-write - - - READ - fuse read interrupt enable -0: fuse read interrupt is not enable -1: fuse read interrupt is enable - 1 - 1 - read-write - - - LOAD - fuse load interrupt enable -0: fuse load interrupt is not enable -1: fuse load interrupt is enable - 0 - 1 - read-write - - - - - - - OTP - OTP - OTP - 0xf40c8000 - - - PPOR - PPOR - PPOR - 0xf40c0000 - - 0x0 - 0x20 - registers - - - - RESET_FLAG - flag indicate reset source - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - FLAG - reset reason of last hard reset, write 1 to clear each bit -0: brownout -1: temperature(not available) -2: resetpin(not available) -4: debug reset -5: jtag reset -8: cpu0 lockup(not available) -9: cpu1 lockup(not available) -10: cpu0 request(not available) -11: cpu1 request(not available) -16: watch dog 0 -17: watch dog 1 -18: watch dog 2 -19: watch dog 3 -20: pmic watch dog -31: software - 0 - 32 - write-only - - - - - RESET_STATUS - reset source status - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - STATUS - current status of reset sources -0: brownout -1: temperature(not available) -2: resetpin(not available) -4: debug reset -5: jtag reset -8: cpu0 lockup(not available) -9: cpu1 lockup(not available) -10: cpu0 request(not available) -11: cpu1 request(not available) -16: watch dog 0 -17: watch dog 1 -18: watch dog 2 -19: watch dog 3 -20: pmic watch dog -31: software - 0 - 32 - read-write - - - - - RESET_HOLD - reset hold attribute - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - STATUS - hold arrtibute, when set, SOC keep in reset status until reset source release, or, reset will be released after SOC enter reset status -0: brownout -1: temperature(not available) -2: resetpin(not available) -4: debug reset -5: jtag reset -8: cpu0 lockup(not available) -9: cpu1 lockup(not available) -10: cpu0 request(not available) -11: cpu1 request(not available) -16: watch dog 0 -17: watch dog 1 -18: watch dog 2 -19: watch dog 3 -20: pmic watch dog -31: software - 0 - 32 - read-write - - - - - RESET_ENABLE - reset source enable - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - ENABLE - enable of reset sources -0: brownout -1: temperature(not available) -2: resetpin(not available) -4: debug reset -5: jtag reset -8: cpu0 lockup(not available) -9: cpu1 lockup(not available) -10: cpu0 request(not available) -11: cpu1 request(not available) -16: watch dog 0 -17: watch dog 1 -18: watch dog 2 -19: watch dog 3 -20: pmic watch dog -31: software - 0 - 32 - read-write - - - - - RESET_HOT - reset type triggered by reset - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - TYPE - reset type of reset sources, 0 for cold/warm reset, all system control setting cleared including clock, ioc; 1 for hot reset, system control, ioc setting kept, peripheral setting cleared. -0: brownout -1: temperature(not available) -2: resetpin(not available) -4: debug reset -5: jtag reset -8: cpu0 lockup(not available) -9: cpu1 lockup(not available) -10: cpu0 request(not available) -11: cpu1 request(not available) -16: watch dog 0 -17: watch dog 1 -18: watch dog 2 -19: watch dog 3 -20: pmic watch dog -31: software - 0 - 32 - read-write - - - - - RESET_COLD - reset type attribute - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - FLAG - perform cold or warm reset of chip, 0 for warm reset, fuse value and debug connection preserved; 1 for cold reset, fuse value reloaded and debug connection corrupted. This bit is ignored when hot reset selected -0: brownout -1: temperature(not available) -2: resetpin(not available) -4: debug reset -5: jtag reset -8: cpu0 lockup(not available) -9: cpu1 lockup(not available) -10: cpu0 request(not available) -11: cpu1 request(not available) -16: watch dog 0 -17: watch dog 1 -18: watch dog 2 -19: watch dog 3 -20: pmic watch dog -31: software - 0 - 32 - read-write - - - - - SOFTWARE_RESET - Software reset counter - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - COUNTER - counter decrease in 24MHz and stop at 0, trigger reset when value reach 2, software can write 0 to cancel reset - 0 - 32 - read-write - - - - - - - PCFG - PCFG - PCFG - 0xf40c4000 - - 0x0 - 0x70 - registers - - - - BANDGAP - BANGGAP control - 0x0 - 32 - 0x00101010 - 0x831F1F1F - - - VBG_TRIMMED - Bandgap trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value -0: bandgap is not trimmed -1: bandgap is trimmed - 31 - 1 - read-write - - - LOWPOWER_MODE - Banggap work in low power mode, banggap function limited -0: banggap works in normal mode -1: banggap works in low power mode - 25 - 1 - read-write - - - POWER_SAVE - Banggap work in power save mode, banggap function normally -0: banggap works in high performance mode -1: banggap works in power saving mode - 24 - 1 - read-write - - - VBG_1P0_TRIM - Banggap 1.0V output trim value - 16 - 5 - read-write - - - VBG_P65_TRIM - Banggap 1.0V output trim value - 8 - 5 - read-write - - - VBG_P50_TRIM - Banggap 1.0V output trim value - 0 - 5 - read-write - - - - - LDO1P1 - 1V LDO config - 0x4 - 32 - 0x0000044C - 0x00000FFF - - - VOLT - LDO output voltage in mV, value valid through 700-1320, , step 20mV. Hardware select voltage no less than target if not on valid steps, with maximum 1320mV. -700: 700mV -720: 720mV -. . . -1320:1320mV - 0 - 12 - read-write - - - - - LDO2P5 - 2.5V LDO config - 0x8 - 32 - 0x000009C4 - 0x10010FFF - - - READY - Ready flag, will set 1ms after enabled or voltage change -0: LDO is not ready for use -1: LDO is ready - 28 - 1 - read-only - - - ENABLE - LDO enable -0: turn off LDO -1: turn on LDO - 16 - 1 - read-write - - - VOLT - LDO output voltage in mV, value valid through 2125-2900, step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 2900mV. -2125: 2125mV -2150: 2150mV -. . . -2900:2900mV - 0 - 12 - read-write - - - - - DCDC_MODE - DCDC mode select - 0x10 - 32 - 0x00B010B0 - 0x10070FFF - - - READY - Ready flag -0: DCDC is applying new change -1: DCDC is ready - 28 - 1 - read-only - - - MODE - DCDC work mode -XX0: turn off -001: basic mode -011: generic mode -101: automatic mode -111: expert mode - 16 - 3 - read-write - - - VOLT - DCDC voltage in mV in normal mode, value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. -600: 600mV -625: 625mV -. . . -1375:1375mV - 0 - 12 - read-write - - - - - DCDC_LPMODE - DCDC low power mode - 0x14 - 32 - 0x00B010B0 - 0x00000FFF - - - STBY_VOLT - DCDC voltage in mV in standby mode, , value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. -600: 600mV -625: 625mV -. . . -1375:1375mV - 0 - 12 - read-write - - - - - DCDC_PROT - DCDC protection - 0x18 - 32 - 0x00000000 - 0x11818191 - - - ILIMIT_LP - over current setting for low power mode -0:250mA -1:200mA - 28 - 1 - read-write - - - OVERLOAD_LP - over current in low power mode -0: current is below setting -1: overcurrent happened in low power mode - 24 - 1 - read-only - - - DISABLE_POWER_LOSS - disable power loss protection -0: power loss protection enabled, DCDC shuts down when power loss -1: power loss protection disabled, DCDC try working after power voltage drop - 23 - 1 - read-write - - - POWER_LOSS_FLAG - power loss -0: input power is good -1: input power is too low - 16 - 1 - read-only - - - DISABLE_OVERVOLTAGE - output over voltage protection -0: protection enabled, DCDC will shut down is output voltage is unexpected high -1: protection disabled, DCDC continue to adjust output voltage - 15 - 1 - read-write - - - OVERVOLT_FLAG - output over voltage flag -0: output is normal -1: output is unexpected high - 8 - 1 - read-only - - - DISABLE_SHORT - disable output short circuit protection -0: short circuits protection enabled, DCDC shut down if short circuit on output detected -1: short circuit protection disabled - 7 - 1 - read-write - - - SHORT_CURRENT - short circuit current setting -0: 2.0A, -1: 1.3A - 4 - 1 - read-write - - - SHORT_FLAG - short circuit flag -0: current is within limit -1: short circuits detected - 0 - 1 - read-only - - - - - DCDC_CURRENT - DCDC current estimation - 0x1c - 32 - 0x00000000 - 0x0000811F - - - ESTI_EN - enable current measure - 15 - 1 - read-write - - - VALID - Current level valid -0: data is invalid -1: data is valid - 8 - 1 - read-only - - - LEVEL - DCDC current level, current level is num * 50mA - 0 - 5 - read-only - - - - - DCDC_ADVMODE - DCDC advance setting - 0x20 - 32 - 0x00EF1C6E - 0x073F006F - - - EN_RCSCALE - Enable RC scale - 24 - 3 - read-write - - - DC_C - Loop C number - 20 - 2 - read-write - - - DC_R - Loop R number - 16 - 4 - read-write - - - EN_FF_DET - enable feed forward detect -0: feed forward detect is disabled -1: feed forward detect is enabled - 6 - 1 - read-write - - - EN_FF_LOOP - enable feed forward loop -0: feed forward loop is disabled -1: feed forward loop is enabled - 5 - 1 - read-write - - - EN_DCM_EXIT - avoid over voltage -0: stay in DCM mode when voltage excess -1: change to CCM mode when voltage excess - 3 - 1 - read-write - - - EN_SKIP - enable skip on narrow pulse -0: do not skip narrow pulse -1: skip narrow pulse - 2 - 1 - read-write - - - EN_IDLE - enable skip when voltage is higher than threshold -0: do not skip -1: skip if voltage is excess - 1 - 1 - read-write - - - EN_DCM - DCM mode -0: CCM mode -1: DCM mode - 0 - 1 - read-write - - - - - DCDC_ADVPARAM - DCDC advance parameter - 0x24 - 32 - 0x00EF1C6E - 0x00007F7F - - - MIN_DUT - minimum duty cycle - 8 - 7 - read-write - - - MAX_DUT - maximum duty cycle - 0 - 7 - read-write - - - - - DCDC_MISC - DCDC misc parameter - 0x28 - 32 - 0x00070100 - 0x13170317 - - - EN_HYST - hysteres enable - 28 - 1 - read-write - - - HYST_SIGN - hysteres sign - 25 - 1 - read-write - - - HYST_THRS - hysteres threshold - 24 - 1 - read-write - - - RC_SCALE - Loop RC scale threshold - 20 - 1 - read-write - - - DC_FF - Loop feed forward number - 16 - 3 - read-write - - - OL_THRE - overload for threshold for lod power mode - 8 - 2 - read-write - - - OL_HYST - current hysteres range -0: 12.5mV -1: 25mV - 4 - 1 - read-write - - - DELAY - enable delay -0: delay disabled, -1: delay enabled - 2 - 1 - read-write - - - CLK_SEL - clock selection -0: select DCDC internal oscillator -1: select RC24M oscillator - 1 - 1 - read-write - - - EN_STEP - enable stepping in voltage change -0: stepping disabled, -1: steping enabled - 0 - 1 - read-write - - - - - DCDC_DEBUG - DCDC Debug - 0x2c - 32 - 0x00005DBF - 0x000FFFFF - - - UPDATE_TIME - DCDC voltage change time in 24M clock cycles, default value is 1mS - 0 - 20 - read-write - - - - - DCDC_START_TIME - DCDC ramp time - 0x30 - 32 - 0x0001193F - 0x000FFFFF - - - START_TIME - Start delay for DCDC to turn on, in 24M clock cycles, default value is 3mS - 0 - 20 - read-write - - - - - DCDC_RESUME_TIME - DCDC resume time - 0x34 - 32 - 0x00008C9F - 0x000FFFFF - - - RESUME_TIME - Resume delay for DCDC to recover from low power mode, in 24M clock cycles, default value is 1.5mS - 0 - 20 - read-write - - - - - POWER_TRAP - SOC power trap - 0x40 - 32 - 0x00000000 - 0x80010001 - - - TRIGGERED - Low power trap status, thit bit will set when power related low power flow triggered, write 1 to clear this flag. -0: low power trap is not triggered -1: low power trap triggered - 31 - 1 - read-write - - - RETENTION - DCDC enter standby mode, which will reduce voltage for memory content retention -0: Shutdown DCDC -1: reduce DCDC voltage - 16 - 1 - read-write - - - TRAP - Enable trap of SOC power supply, trap is used to hold SOC in low power mode for DCDC to enter further low power mode, this bit will self-clear when power related low pwer flow triggered -0: trap not enabled, pmic side low power function disabled -1: trap enabled, STOP operation leads to PMIC low power flow if SOC is not retentioned. - 0 - 1 - read-write - - - - - WAKE_CAUSE - Wake up source - 0x44 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAUSE - wake up cause, each bit represents one wake up source, write 1 to clear the register bit -0: wake up source is not active during last wakeup -1: wake up source is active furing last wakeup -bit 0: pmic_enable -bit 1: debug wakeup -bit 4: fuse interrupt -bit 7: UART interrupt -bit 8: TMR interrupt -bit 9: WDG interrupt -bit10: GPIO in PMIC interrupt -bit11: Security monitor interrupt -bit12: Security in PMIC event -bit16: Security violation in BATT -bit17: GPIO in BATT interrupt -bit18: BATT Button interrupt -bit19: RTC alarm interrupt - 0 - 32 - read-write - - - - - WAKE_MASK - Wake up mask - 0x48 - 32 - 0x00000000 - 0xFFFFFFFF - - - MASK - mask for wake up sources, each bit represents one wakeup source -0: allow source to wake up system -1: disallow source to wakeup system -bit 0: pmic_enable -bit 1: debug wakeup -bit 4: fuse interrupt -bit 7: UART interrupt -bit 8: TMR interrupt -bit 9: WDG interrupt -bit10: GPIO in PMIC interrupt -bit11: Security monitor interrupt -bit12: Security in PMIC event -bit16: Security violation in BATT -bit17: GPIO in BATT interrupt -bit18: BATT Button interrupt -bit19: RTC alarm interrupt - 0 - 32 - read-write - - - - - SCG_CTRL - Clock gate control in PMIC - 0x4c - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - SCG - control whether clock being gated during PMIC low power flow, 2 bits for each peripheral -00,01: reserved -10: clock is always off -11: clock is always on -bit0-1: fuse -bit2-3: sram -bit4-5: vad -bit6-7:gpio -bit8-9:ioc -bit10-11: timer -bit12-13:wdog -bit14-15:uart -bit16-17:debug - 0 - 32 - read-write - - - - - DEBUG_STOP - Debug stop config - 0x50 - 32 - 0x00000001 - 0x00000003 - - - CPU1 - Stop peripheral when CPU1 enter debug mode -0: peripheral keep running when CPU1 in debug mode -1: peripheral enter debug mode when CPU1 enter debug - 1 - 1 - read-write - - - CPU0 - Stop peripheral when CPU0 enter debug mode -0: peripheral keep running when CPU0 in debug mode -1: peripheral enter debug mode when CPU0 enter debug - 0 - 1 - read-write - - - - - RC24M - RC 24M config - 0x60 - 32 - 0x00000316 - 0x8000071F - - - RC_TRIMMED - RC24M trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value -0: RC is not trimmed -1: RC is trimmed - 31 - 1 - read-write - - - TRIM_C - Coarse trim for RC24M, bigger value means faster - 8 - 3 - read-write - - - TRIM_F - Fine trim for RC24M, bigger value means faster - 0 - 5 - read-write - - - - - RC24M_TRACK - RC 24M track mode - 0x64 - 32 - 0x00000000 - 0x00010011 - - - SEL24M - Select track reference -0: select 32K as reference -1: select 24M XTAL as reference - 16 - 1 - read-write - - - RETURN - Retrun default value when XTAL loss -0: remain last tracking value -1: switch to default value - 4 - 1 - read-write - - - TRACK - track mode -0: RC24M free running -1: track RC24M to external XTAL - 0 - 1 - read-write - - - - - TRACK_TARGET - RC 24M track target - 0x68 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRE_DIV - Divider for reference source - 16 - 16 - read-write - - - TARGET - Target frequency multiplier of divided source - 0 - 16 - read-write - - - - - STATUS - RC 24M track status - 0x6c - 32 - 0x00000000 - 0x0011871F - - - SEL32K - track is using XTAL32K -0: track is not using XTAL32K -1: track is using XTAL32K - 20 - 1 - read-only - - - SEL24M - track is using XTAL24M -0: track is not using XTAL24M -1: track is using XTAL24M - 16 - 1 - read-only - - - EN_TRIM - default value takes effect -0: default value is invalid -1: default value is valid - 15 - 1 - read-only - - - TRIM_C - default coarse trim value - 8 - 3 - read-only - - - TRIM_F - default fine trim value - 0 - 5 - read-only - - - - - - - PSEC - PSEC - PSEC - 0xf40cc000 - - 0x0 - 0x18 - registers - - - - SECURE_STATE - Secure state - 0x0 - 32 - 0x00000000 - 0x000300F0 - - - ALLOW_NSC - Non-secure state allow -0: system is not healthy to enter non-secure state, request to enter non-secure state will cause a fail state -1: system is healthy to enter non-secure state - 17 - 1 - read-only - - - ALLOW_SEC - Secure state allow -0: system is not healthy to enter secure state, request to enter non-secure state will cause a fail state -1: system is healthy to enter secure state - 16 - 1 - read-only - - - PMIC_FAIL - PMIC secure state one hot indicator -0: secure state is not in fail state -1: secure state is in fail state - 7 - 1 - read-write - - - PMIC_NSC - PMIC secure state one hot indicator -0: secure state is not in non-secure state -1: secure state is in non-secure state - 6 - 1 - read-write - - - PMIC_SEC - PMIC secure state one hot indicator -0: secure state is not in secure state -1: secure state is in secure state - 5 - 1 - read-write - - - PMIC_INS - PMIC secure state one hot indicator -0: secure state is not in inspect state -1: secure state is in inspect state - 4 - 1 - read-write - - - - - SECURE_STATE_CONFIG - secure state configuration - 0x4 - 32 - 0x00000000 - 0x00000009 - - - LOCK - Lock bit of allow restart setting, once locked, lock bit itself and configuration register will keep value until next reset -0: not locked, register can be modified -1: register locked, write access to the register is ignored - 3 - 1 - read-write - - - ALLOW_RESTART - allow secure state restart from fail state -0: restart is not allowed, only hardware reset can recover secure state -1: software is allowed to switch to inspect state from fail state - 0 - 1 - read-write - - - - - VIOLATION_CONFIG - Security violation config - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK_NSC - Lock bit non-secure violation setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified -1: register locked, write access to the configuration is ignored - 31 - 1 - read-write - - - NSC_VIO_CFG - configuration of non-secure state violations, each bit represents one security event -0: event is not a security violation -1: event is a security violation - 16 - 15 - read-write - - - LOCK_SEC - Lock bit secure violation setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified -1: register locked, write access to the configuration is ignored - 15 - 1 - read-write - - - SEC_VIO_CFG - configuration of secure state violations, each bit represents one security event -0: event is not a security violation -1: event is a security violation - 0 - 15 - read-write - - - - - ESCALATE_CONFIG - Escalate behavior on security event - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK_NSC - Lock bit non-secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified -1: register locked, write access to the configuration is ignored - 31 - 1 - read-write - - - NSC_VIO_CFG - configuration of non-secure state escalates, each bit represents one security event -0: event is not a security escalate -1: event is a security escalate - 16 - 15 - read-write - - - LOCK_SEC - Lock bit secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified -1: register locked, write access to the configuration is ignored - 15 - 1 - read-write - - - SEC_VIO_CFG - configuration of secure state escalates, each bit represents one security event -0: event is not a security escalate -1: event is a security escalate - 0 - 15 - read-write - - - - - EVENT - Event and escalate status - 0x10 - 32 - 0x00000000 - 0xFFFF000C - - - EVENT - local event statue, each bit represents one security event - 16 - 16 - read-only - - - PMIC_ESC_NSC - PMIC is escalating non-secure event - 3 - 1 - read-only - - - PMIC_ESC_SEC - PMIC is escalting secure event - 2 - 1 - read-only - - - - - LIFECYCLE - Lifecycle - 0x14 - 32 - 0x00000000 - 0x000000FF - - - LIFECYCLE - lifecycle status, -bit7: lifecycle_debate, -bit6: lifecycle_scribe, -bit5: lifecycle_no_ret, -bit4: lifecycle_return, -bit3: lifecycle_secure, -bit2: lifecycle_nonsec, -bit1: lifecycle_create, -bit0: lifecycle_unknow - 0 - 8 - read-only - - - - - - - PMON - PMON - PMON - 0xf40d0000 - - 0x0 - 0x48 - registers - - - - 4 - 0x8 - glitch0,glitch1,clock0,clock1 - MONITOR[%s] - no description available - 0x0 - - CONTROL - Glitch and clock monitor control - 0x0 - 32 - 0x00000000 - 0x00000011 - - - ACTIVE - select glitch works in active mode or passve mode. -0: passive mode, depends on power glitch destroy DFF value -1: active mode, check glitch by DFF chain - 4 - 1 - read-write - - - ENABLE - enable glitch detector -0: detector disabled -1: detector enabled - 0 - 1 - read-write - - - - - STATUS - Glitch and clock monitor status - 0x4 - 32 - 0x00000000 - 0x00000001 - - - FLAG - flag for glitch detected, write 1 to clear this flag -0: glitch not detected -1: glitch detected - 0 - 1 - read-write - - - - - - IRQ_FLAG - No description available - 0x40 - 32 - 0x00000000 - 0x0000000F - - - FLAG - interrupt flag, each bit represents for one monitor, write 1 to clear interrupt flag -0: no monitor interrupt -1: monitor interrupt happened - 0 - 4 - read-write - - - - - IRQ_ENABLE - No description available - 0x44 - 32 - 0x00000000 - 0x0000000F - - - ENABLE - interrupt enable, each bit represents for one monitor -0: monitor interrupt disabled -1: monitor interrupt enabled - 0 - 4 - read-write - - - - - - - PGPR - PGPR - PGPR - 0xf40d4000 - - 0x0 - 0x40 - registers - - - - PMIC_GPR00 - Generic control - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR01 - Generic control - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR02 - Generic control - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR03 - Generic control - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR04 - Generic control - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR05 - Generic control - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR06 - Generic control - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR07 - Generic control - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR08 - Generic control - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR09 - Generic control - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR10 - Generic control - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR11 - Generic control - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR12 - Generic control - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR13 - Generic control - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR14 - Generic control - 0x38 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR15 - Generic control - 0x3c - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - - - VAD - VAD - VAD - 0xf40ec000 - - 0x0 - 0xa4 - registers - - - - CTRL - Control Register - 0x0 - 32 - 0x00000000 - 0x0FF7FBFF - - - CAPT_DLY - Capture cycle delay>=0, should be less than PDM_CLK_HFDIV - 24 - 4 - read-write - - - PDM_CLK_HFDIV - The clock divider will work at least 4. -0: div-by-2, -1: div-by-4 -. . . -n: div-by-2*(n+1) - 20 - 4 - read-write - - - VAD_IE - VAD event interrupt enable - 18 - 1 - read-write - - - OFIFO_AV_IE - OFIFO data available interrupt enable - 17 - 1 - read-write - - - MEMBUF_EMPTY_IE - Buf empty interrupt enable - 16 - 1 - read-write - - - OFIFO_OVFL_ERR_IE - OFIFO overflow error interrupt enable - 15 - 1 - read-write - - - IIR_OVLD_ERR_IE - IIR overload error interrupt enable - 14 - 1 - read-write - - - IIR_OVFL_ERR_IE - IIR overflow error interrupt enable - 13 - 1 - read-write - - - CIC_OVLD_ERR_IE - CIC overload Interrupt Enable - 12 - 1 - read-write - - - CIC_SAT_ERR_IE - CIC saturation Interrupt Enable - 11 - 1 - read-write - - - MEMBUF_DISABLE - asserted to disable membuf - 9 - 1 - read-write - - - FIFO_THRSH - OFIFO threshold to generate ofifo_av (when fillings >= threshold) (fifo size: max 16 items, 16*32bits) - 5 - 4 - read-write - - - PDM_CLK_DIV_BYPASS - asserted to bypass the pdm clock divider - 4 - 1 - read-write - - - PDM_CLK_OE - pdm_clk_output_en - 3 - 1 - read-write - - - CH_POL - Asserted to select PDM_CLK high level captured, otherwise to select PDM_CLK low level captured. - 1 - 2 - read-write - - - CHNUM - the number of channels to be stored in buffer. Asserted to enable 2 channels. - 0 - 1 - read-write - - - - - FILTCTRL - Filter Control Register - 0x4 - 32 - 0x00000000 - 0x000007FF - - - DECRATIO - the decimation ratio of iir after CIC -1 -2: means dec-by-3 - 8 - 3 - read-write - - - IIR_SLOT_EN - IIR slot enable - 0 - 8 - read-write - - - - - DEC_CTRL0 - Decision Control Register 0 - 0x8 - 32 - 0x00000000 - 0xFFFF03FF - - - NOISE_TOL - the value of amplitude for noise determination when calculationg ZCR - 16 - 16 - read-write - - - BLK_CFG - asserted to have 3 sub-blocks, otherwise to have 2 sub-blocks - 9 - 1 - read-write - - - SUBBLK_LEN - length of sub-block - 0 - 9 - read-write - - - - - DEC_CTRL1 - Decision Control Register 1 - 0xc - 32 - 0x00000000 - 0x003FFFFF - - - ZCR_HIGH - ZCR high limit - 11 - 11 - read-write - - - ZCR_LOW - ZCR low limit - 0 - 11 - read-write - - - - - DEC_CTRL2 - Decision Control Register 2 - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - AMP_HIGH - amplitude high limit - 16 - 16 - read-write - - - AMP_LOW - amplitude low limit - 0 - 16 - read-write - - - - - ST - Status - 0x18 - 32 - 0x00000000 - 0x000000FF - - - VAD - VAD event found - 7 - 1 - write-only - - - OFIFO_AV - OFIFO data available - 6 - 1 - read-only - - - MEMBUF_EMPTY - Buf empty - 5 - 1 - write-only - - - OFIFO_OVFL - OFIFO overflow - 4 - 1 - write-only - - - IIR_OVLD - IIR overloading - 3 - 1 - write-only - - - IIR_OVFL - IIR oberflow - 2 - 1 - write-only - - - CIC_OVLD_ERR - CIC overload - 1 - 1 - write-only - - - CIC_SAT_ERR - CIC saturation - 0 - 1 - write-only - - - - - OFIFO - Out FIFO - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - D - The PCM data. -When there is only one channel, the samples are from Ch0, and the 2 samples in the 32-bits are: bit [31:16]: the samples earlier in time ([T-1]). Bit [15:0]: the samples later in time ([T]). -When there is two channels, the samples in the 32-bits are: bit [31:16]: the samples belong to Ch 1 (when ch_pol[1:0]==2, the data is captured at the positive part of the pdm clk). bit [15:0]: the samples belong to Ch 0 (when ch_pol[1:0]==2, the data is captured at the negtive part of the pdm clk). - 0 - 32 - read-write - - - - - RUN - Run Command Register - 0x20 - 32 - 0x00000000 - 0x00000003 - - - SFTRST - software reset. Self-clear - 1 - 1 - read-write - - - VAD_EN - module enable - 0 - 1 - read-write - - - - - OFIFO_CTRL - Out FIFO Control Register - 0x24 - 32 - 0x00000000 - 0x00000001 - - - EN - Asserted to enable OFIFO - 0 - 1 - read-write - - - - - CIC_CFG - CIC Configuration Register - 0x28 - 32 - 0x00000000 - 0x0000FC00 - - - POST_SCALE - the shift value after CIC results. - 10 - 6 - read-write - - - - - 1 - 0x4 - STE_ACT - COEF[%s] - no description available - 0xa0 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - The current detected short time energy - 0 - 32 - read-only - - - - - - - PLLCTL - PLLCTL - PLLCTL - 0xf4100000 - - 0x0 - 0x300 - registers - - - - XTAL - Crystal control and status - 0x0 - 32 - 0x00000000 - 0x300FFFFF - - - RESPONSE - Crystal oscillator status -0: Oscillator is not stable -1: Oscillator is stable for use - 29 - 1 - read-only - - - ENABLE - Crystal oscillator enable status -0: Oscillator is off -1: Oscillator is on - 28 - 1 - read-only - - - RAMP_TIME - Rampup time of XTAL oscillator in cycles of IRC24M clock -0: 0 cycle -1: 1 cycle -2: 2 cycle -1048575: 1048575 cycles - 0 - 20 - read-write - - - - - 5 - 0x80 - pll0,pll1,pll2,pll3,pll4 - PLL[%s] - no description available - 0x80 - - CFG0 - PLLx config0 - 0x0 - 32 - 0x00140460 - 0xBF77FFE8 - - - SS_RSTPTR - reset pointer, for sscg, lock when lock_en[31]&~pll_ana_pd&~pll_lock_comb - 31 - 1 - read-write - - - REFDIV - refclk diverder, lock when lock_en[24]&~pll_ana_pd - 24 - 6 - read-write - - - POSTDIV1 - lock when lock_en[20]&~pll_ana_pd - 20 - 3 - read-write - - - SS_SPREAD - lock when lock_en[14]&~pll_ana_pd - 14 - 5 - read-write - - - SS_DIVVAL - sscg divval, lock when lock_en[8]&~pll_ana_pd - 8 - 6 - read-write - - - SS_DOWNSPREAD - Downspread control -1’b0 –> Center-Spread -1’b1 –> Downspread - 7 - 1 - read-write - - - SS_RESET - No description available - 6 - 1 - read-write - - - SS_DISABLE_SSCG - No description available - 5 - 1 - read-write - - - DSMPD - 1: int mode; 0: frac mode - 3 - 1 - read-write - - - - - CFG1 - PLLx config1 - 0x4 - 32 - 0x80000000 - 0x86008000 - - - PLLCTRL_HW_EN - 1: hardware controll PLL settings, software can update register, but result unknown; suggested only update fbdiv and frac value -0: full software control PLL settings - 31 - 1 - read-write - - - CLKEN_SW - the clock enable used to gate pll output, should be set after lock, and clear before power down pll. -pll_clock_enable = pllctrl_hw_en ? (pll_lock_comb & enable & pll_clk_enable_chg) : clken_sw; - 26 - 1 - read-write - - - PLLPD_SW - pll power down. -pll_ana_pd = pllctrl_hw_en ? (pll_pd_soc|pll_pd_chg) : pllpd_sw; -pll_pd_soc is just delay of soc enable, for soc to control pll on/off; -pll_pd_chg is used to power down pll when div_chg_mode is 1, if software update pll parameter(fbdiv or frac), pll_ctrl will power down pll, update parameter, then power up pll. response to soc will not de-asserted at this sequence - 25 - 1 - read-write - - - LOCK_CNT_CFG - used to wait lock if set larger than lock time; -default 1500 24M cycle if refdiv is 1, 4500 cycle if refdiv is 3 - 15 - 1 - read-write - - - - - CFG2 - PLLx config2 - 0x8 - 32 - 0x00000000 - 0x00000FFF - - - FBDIV_INT - fbdiv used in int mode - 0 - 12 - read-write - - - - - FREQ - PLLx frac mode frequency adjust - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - FRAC - PLL output frequency is : -Fout = Fref/refdiv*(fbdiv + frac/2^24)/postdiv1 -for default refdiv=1 and postdiv1=1, 24MHz refclk -Fout is 24*fbdiv in int mode -if frac is set to 0x800000, Fout is 24*(fbdiv+0.5) -Fout is 24*fbdiv in int mode -if frac is set to 0x200000, Fout is 24*(fbdiv+0.125) - 8 - 24 - read-write - - - FBDIV_FRAC - fbdiv used in frac mode - 0 - 8 - read-write - - - - - LOCK - PLLx lock control - 0x10 - 32 - 0x00000000 - 0x81104100 - - - LOCK_SS_RSTPTR - lock bit of field ss_rstptr -0: field is open foe software to change -1: field is locked, not changeable - 31 - 1 - read-write - - - LOCK_REFDIV - lock bit of field refdiv -0: field is open foe software to change -1: field is locked, not changeable - 24 - 1 - read-write - - - LOCK_POSTDIV1 - lock bit of field postdiv1 -0: field is open foe software to change -1: field is locked, not changeable - 20 - 1 - read-write - - - LOCK_SS_SPEAD - lock bit of field ss_spead -0: field is open foe software to change -1: field is locked, not changeable - 14 - 1 - read-write - - - LOCK_SS_DIVVAL - lock bit of field ss_divval -0: field is open foe software to change -1: field is locked, not changeable - 8 - 1 - read-write - - - - - STATUS - PLLx status - 0x20 - 32 - 0x00000000 - 0x08000007 - - - ENABLE - enable from SYSCTL block - 27 - 1 - read-only - - - RESPONSE - response to SYSCTL, PLL is power down when both enable and response are 0. - 2 - 1 - read-only - - - PLL_LOCK_COMB - No description available - 1 - 1 - read-only - - - PLL_LOCK_SYNC - No description available - 0 - 1 - read-only - - - - - DIV0 - PLLx divider0 control - 0x40 - 32 - 0x00000000 - 0xB00000FF - - - BUSY - Busy flag -0: divider is working -1: divider is changing status - 31 - 1 - read-only - - - RESPONSE - Crystal oscillator status -0: Oscillator is not stable -1: Oscillator is stable for use - 29 - 1 - read-only - - - ENABLE - Crystal oscillator enable status -0: Oscillator is off -1: Oscillator is on - 28 - 1 - read-only - - - DIV - Divider -0: divide by 1 -1: divide by2 -. . . -255: divide by 256 - 0 - 8 - read-write - - - - - DIV1 - PLLx divider1 control - 0x44 - 32 - 0x00000000 - 0xB00000FF - - - BUSY - Busy flag -0: divider is working -1: divider is changing status - 31 - 1 - read-only - - - RESPONSE - Crystal oscillator status -0: Oscillator is not stable -1: Oscillator is stable for use - 29 - 1 - read-only - - - ENABLE - Crystal oscillator enable status -0: Oscillator is off -1: Oscillator is on - 28 - 1 - read-only - - - DIV - Divider -0: divide by 1 -1: divide by2 -. . . -255: divide by 256 - 0 - 8 - read-write - - - - - - - - BPOR - BPOR - BPOR - 0xf5004000 - - 0x0 - 0x10 - registers - - - - POR_CAUSE - Power on cause - 0x0 - 32 - 0x00000000 - 0x0000001F - - - CAUSE - Power on cause, each bit represnts one cause, write 1 to clear each bit -bit0: wakeup button -bit1: security violation -bit2: RTC alarm 0 -bit3: RTC alarm 1 -bit4: GPIO - 0 - 5 - read-write - - - - - POR_SELECT - Power on select - 0x4 - 32 - 0x00000000 - 0x0000001F - - - SELECT - Power on cause select, each bit represnts one cause, value 1 enables corresponding cause -bit0: wakeup button -bit1: security violation -bit2: RTC alarm 0 -bit3: RTC alarm 1 -bit4: GPIO - 0 - 5 - read-write - - - - - POR_CONFIG - Power on reset config - 0x8 - 32 - 0x00000000 - 0x00000001 - - - RETENTION - retention battery domain setting -0: battery reset on reset pin reset happen -1: battery domain retention when reset pin reset happen - 0 - 1 - read-write - - - - - POR_CONTROL - Power down control - 0xc - 32 - 0x00000000 - 0x0000FFFF - - - COUNTER - Chip power down counter, counter decreasing if value is not 0, power down of chip happens on counter value is 1 - 0 - 16 - read-write - - - - - - - BCFG - BCFG - BCFG - 0xf5008000 - - 0x0 - 0x14 - registers - - - - VBG_CFG - Bandgap config - 0x0 - 32 - 0x00000000 - 0x831F1F1F - - - VBG_TRIMMED - Bandgap trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value -0: bandgap is not trimmed -1: bandgap is trimmed - 31 - 1 - read-write - - - LP_MODE - Bandgap works in low power mode -0: not in low power mode -1: bandgap work in low power mode - 25 - 1 - read-write - - - POWER_SAVE - Bandgap works in power save mode -0: not in power save mode -1: bandgap work in power save mode - 24 - 1 - read-write - - - VBG_1P0 - Bandgap 1.0V output trim - 16 - 5 - read-write - - - VBG_P65 - Bandgap 0.65V output trim - 8 - 5 - read-write - - - VBG_P50 - Bandgap 0.50V output trim - 0 - 5 - read-write - - - - - LDO_CFG - LDO config - 0x4 - 32 - 0x00010000 - 0x03370FFF - - - RES_TRIM - Resistor trim - 24 - 2 - read-write - - - CP_TRIM - Capacitor trim - 20 - 2 - read-write - - - EN_SL - enable selfload, this bit helps improve LDO performance when current less than 200nA -0: self load disabled -1: selfload enabled - 18 - 1 - read-write - - - DIS_PD - disable pull down resistor, enable pull down may lead to more power but better response -0: pulldown resistor enabled -1: pulldown resistor disabled - 17 - 1 - read-write - - - ENABLE - LDO enable -0: LDO is disabled -1: LDO is enabled - 16 - 1 - read-write - - - VOLT - LDO voltage setting in mV, valid range through 600mV to 1100mV, step 20mV. Hardware select voltage no less than target if not on valid steps, with maximum 1100mV. -600: 600mV -620: 620mV -. . . -1100:1100mV - 0 - 12 - read-write - - - - - IRC32K_CFG - On-chip 32k oscillator config - 0x8 - 32 - 0x00000000 - 0x80C001FF - - - IRC_TRIMMED - IRC32K trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value -0: irc is not trimmed -1: irc is trimmed - 31 - 1 - read-write - - - CAPEX7_TRIM - IRC32K bit 7 - 23 - 1 - read-write - - - CAPEX6_TRIM - IRC32K bit 6 - 22 - 1 - read-write - - - CAP_TRIM - capacitor trim bits - 0 - 9 - read-write - - - - - XTAL32K_CFG - XTAL 32K config - 0xc - 32 - 0x00000000 - 0x00001313 - - - HYST_EN - crystal 32k hysteres enable - 12 - 1 - read-write - - - GMSEL - crystal 32k gm selection - 8 - 2 - read-write - - - CFG - crystal 32k config - 4 - 1 - read-write - - - AMP - crystal 32k amplifier - 0 - 2 - read-write - - - - - CLK_CFG - Clock config - 0x10 - 32 - 0x00000000 - 0x10010010 - - - XTAL_SEL - crystal selected - 28 - 1 - read-only - - - KEEP_IRC - force irc32k run - 16 - 1 - read-write - - - FORCE_XTAL - force switch to crystal - 4 - 1 - read-write - - - - - - - BUTN - BUTN - BUTN - 0xf500c000 - - 0x0 - 0xc - registers - - - - BTN_STATUS - Button status - 0x0 - 32 - 0x00000000 - 0x77770FFF - - - XWCLICK - wake button click status when power button held, write 1 to clear flag -bit0: clicked -bit1: double clicked -bit2: tripple clicked - 28 - 3 - read-write - - - WCLICK - wake button click status, write 1 to clear flag -bit0: clicked -bit1: double clicked -bit2: tripple clicked - 24 - 3 - read-write - - - XPCLICK - power button click status when wake button held, write 1 to clear flag -bit0: clicked -bit1: double clicked -bit2: tripple clicked - 20 - 3 - read-write - - - PCLICK - power button click status, write 1 to clear flag -bit0: clicked -bit1: double clicked -bit2: tripple clicked - 16 - 3 - read-write - - - DBTN - Dual button press status, write 1 to clear flag -bit0: button pressed -bit1: button confirmd -bit2: button long pressed -bit3: button long long pressed - 8 - 4 - read-write - - - WBTN - Wake button press status, write 1 to clear flag -bit0: button pressed -bit1: button confirmd -bit2: button long pressed -bit3: button long long pressed - 4 - 4 - read-write - - - PBTN - Power button press status, write 1 to clear flag -bit0: button pressed -bit1: button confirmd -bit2: button long pressed -bit3: button long long pressed - 0 - 4 - read-write - - - - - BTN_IRQ_MASK - Button interrupt mask - 0x4 - 32 - 0x00000000 - 0x77770FFF - - - XWCLICK - wake button click status when power button held interrupt enable -bit0: clicked -bit1: double clicked -bit2: tripple clicked - 28 - 3 - read-write - - - WCLICK - wake button click interrupt enable -bit0: clicked -bit1: double clicked -bit2: tripple clicked - 24 - 3 - read-write - - - XPCLICK - power button click status when wake button held interrupt enable -bit0: clicked -bit1: double clicked -bit2: tripple clicked - 20 - 3 - read-write - - - PCLICK - power button click interrupt enable -bit0: clicked -bit1: double clicked -bit2: tripple clicked - 16 - 3 - read-write - - - DBTN - Dual button press interrupt enable -bit0: button pressed -bit1: button confirmd -bit2: button long pressed -bit3: button long long pressed - 8 - 4 - read-write - - - WBTN - Wake button press interrupt enable -bit0: button pressed -bit1: button confirmd -bit2: button long pressed -bit3: button long long pressed - 4 - 4 - read-write - - - PBTN - Power button press interrupt enable -bit0: button pressed -bit1: button confirmd -bit2: button long pressed -bit3: button long long pressed - 0 - 4 - read-write - - - - - LED_INTENSE - Debounce setting - 0x8 - 32 - 0x00000000 - 0x000F000F - - - RLED - Rbutton brightness 0 - 16 - 4 - read-write - - - PLED - Pbutton brightness 0 - 0 - 4 - read-write - - - - - - - BGPR - BGPR - BGPR - 0xf5018000 - - 0x0 - 0x20 - registers - - - - 8 - 0x4 - 0,1,2,3,4,5,6,7 - GPR[%s] - no description available - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - Generic control - 0 - 32 - read-write - - - - - - - RTCSHW - RTCSHW - RTC - 0xf501c000 - - 0x0 - 0x28 - registers - - - - SECOND - Second counter - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SECOND - second counter - 0 - 32 - read-write - - - - - SUBSEC - Sub-second counter - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - SUBSEC - sub second counter - 0 - 32 - read-only - - - - - SEC_SNAP - Second counter snap shot - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - SEC_SNAP - second snap shot, write to take snap shot - 0 - 32 - read-write - - - - - SUB_SNAP - Sub-second counter snap shot - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - SUB_SNAP - sub second snap shot, write to take snap shot - 0 - 32 - read-write - - - - - ALARM0 - RTC alarm0 - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - ALARM - Alarm time for second counter, on each alarm match, alarm increase ALARM0_INC - 0 - 32 - read-write - - - - - ALARM0_INC - Alarm0 incremental - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - INCREASE - adder when ARLAM0 happen, helps to create periodical alarm - 0 - 32 - read-write - - - - - ALARM1 - RTC alarm1 - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - ALARM - Alarm time for second counter, on each alarm match, alarm increase ALARM0_INC - 0 - 32 - read-write - - - - - ALARM1_INC - Alarm1 incremental - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - INCREASE - adder when ARLAM0 happen, helps to create periodical alarm - 0 - 32 - read-write - - - - - ALARM_FLAG - RTC alarm flag - 0x20 - 32 - 0x00000000 - 0x00000003 - - - ALARM1 - alarm1 happen - 1 - 1 - read-write - - - ALARM0 - alarm0 happen - 0 - 1 - read-write - - - - - ALARM_EN - RTC alarm enable - 0x24 - 32 - 0x00000000 - 0x00000003 - - - ENABLE1 - alarm1 mask -0: alarm1 disabled -1: alarm1 enabled - 1 - 1 - read-write - - - ENABLE0 - alarm0 mask -0: alarm0 disabled -1: alarm0 enabled - 0 - 1 - read-write - - - - - - - RTC - RTC - RTC - 0xf5044000 - - - BSEC - BSEC - BSEC - 0xf5040000 - - 0x0 - 0x14 - registers - - - - SECURE_STATE - Secure state - 0x0 - 32 - 0x00000000 - 0x0003000F - - - ALLOW_NSC - Non-secure state allow -0: system is not healthy to enter non-secure state, request to enter non-secure state will cause a fail state -1: system is healthy to enter non-secure state - 17 - 1 - read-only - - - ALLOW_SEC - Secure state allow -0: system is not healthy to enter secure state, request to enter non-secure state will cause a fail state -1: system is healthy to enter secure state - 16 - 1 - read-only - - - BATT_FAIL - BATT secure state one hot indicator -0: secure state is not in fail state -1: secure state is in fail state - 3 - 1 - read-write - - - BATT_NSC - BATT secure state one hot indicator -0: secure state is not in non-secure state -1: secure state is in non-secure state - 2 - 1 - read-write - - - BATT_SEC - BATT secure state one hot indicator -0: secure state is not in secure state -1: secure state is in secure state - 1 - 1 - read-write - - - BATT_INS - BATT secure state one hot indicator -0: secure state is not in inspect state -1: secure state is in inspect state - 0 - 1 - read-write - - - - - SECURE_STATE_CONFIG - secure state configuration - 0x4 - 32 - 0x00000000 - 0x00000009 - - - LOCK - Lock bit of allow restart setting, once locked, lock bit itself and configuration register will keep value until next reset -0: not locked, register can be modified -1: register locked, write access to the register is ignored - 3 - 1 - read-write - - - ALLOW_RESTART - allow secure state restart from fail state -0: restart is not allowed, only hardware reset can recover secure state -1: software is allowed to switch to inspect state from fail state - 0 - 1 - read-write - - - - - VIOLATION_CONFIG - Security violation config - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK_NSC - Lock bit non-secure violation setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified -1: register locked, write access to the configuration is ignored - 31 - 1 - read-write - - - NSC_VIO_CFG - configuration of non-secure state violations, each bit represents one security event -0: event is not a security violation -1: event is a security violation - 16 - 15 - read-write - - - LOCK_SEC - Lock bit secure violation setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified -1: register locked, write access to the configuration is ignored - 15 - 1 - read-write - - - SEC_VIO_CFG - configuration of secure state violations, each bit represents one security event -0: event is not a security violation -1: event is a security violation - 0 - 15 - read-write - - - - - ESCALATE_CONFIG - Escalate behavior on security event - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK_NSC - Lock bit non-secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified -1: register locked, write access to the configuration is ignored - 31 - 1 - read-write - - - NSC_VIO_CFG - configuration of non-secure state escalates, each bit represents one security event -0: event is not a security escalate -1: event is a security escalate - 16 - 15 - read-write - - - LOCK_SEC - Lock bit secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified1: register locked, write access to the configuration is ignored - 15 - 1 - read-write - - - SEC_VIO_CFG - configuration of secure state escalates, each bit represents one security event -0: event is not a security escalate -1: event is a security escalate - 0 - 15 - read-write - - - - - EVENT - Event and escalate status - 0x10 - 32 - 0x00000000 - 0xFFFF0003 - - - EVENT - local event statue, each bit represents one security event - 16 - 16 - read-only - - - BATT_ESC_NSC - BATT is escalating non-secure event - 1 - 1 - read-only - - - BATT_ESC_SEC - BATT is escalting ssecure event - 0 - 1 - read-only - - - - - - - BKEY - BKEY - BKEY - 0xf5048000 - - 0x0 - 0x4c - registers - - - - 2 - 0x20 - 0,1 - KEY[%s] - no description available - 0x0 - - 8 - 0x4 - 0,1,2,3,4,5,6,7 - DATA[%s] - no description available - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - security key data - 0 - 32 - read-write - - - - - - 2 - 0x4 - KEY0,KEY1 - ECC[%s] - no description available - 0x40 - 32 - 0x00000000 - 0xC000FFFF - - - WLOCK - write lock to key0 -0: write enable -1: write ignored - 31 - 1 - read-write - - - RLOCK - read lock to key0 -0: key read enable -1: key always read as 0 - 30 - 1 - read-write - - - ECC - Parity check bits for key0 - 0 - 16 - read-write - - - - - SELECT - Key selection - 0x48 - 32 - 0x00000000 - 0x00000001 - - - SELECT - select key, key0 treated as secure key, in non-scure mode, only key1 can be selected -0: select key0 in secure mode, key1 in non-secure mode -1: select key1 in secure or nonsecure mode - 0 - 1 - read-write - - - - - - - BMON - BMON - BMON - 0xf504c000 - - 0x0 - 0x20 - registers - - - - 2 - 0x10 - glitch0,clock0 - MONITOR[%s] - no description available - 0x0 - - CONTROL - Glitch and clock monitor control - 0x0 - 32 - 0x00000000 - 0x00000011 - - - ACTIVE - select glitch works in active mode or passve mode. -0: passive mode, depends on power glitch destroy DFF value -1: active mode, check glitch by DFF chain - 4 - 1 - read-write - - - ENABLE - enable glitch detector -0: detector disabled -1: detector enabled - 0 - 1 - read-write - - - - - STATUS - Glitch and clock monitor status - 0x4 - 32 - 0x00000000 - 0x00000001 - - - FLAG - flag for glitch detected, write 1 to clear this flag -0: glitch not detected -1: glitch detected - 0 - 1 - read-write - - - - - - - - TAMP - TAMP - TAMP - 0xf5050000 - - 0x0 - 0x88 - registers - - - - 6 - 0x10 - tamp0,tamp1,tamp2,tamp3,tamp4,tamp5 - TAMP[%s] - no description available - 0x0 - - CONTROL - Tamper n control - 0x0 - 32 - 0x00000000 - 0x801F03F7 - - - LOCK - lock tamper setting -0: tamper setting can be changed -1: tamper setting will last to next battery domain power cycle - 31 - 1 - read-write - - - BYPASS - bypass tamper violation filter -0: filter applied -1: filter not used - 20 - 1 - read-write - - - FILTER - filter length -0: 1 cycle -1: 2 cycle -15: 65526 cycle - 16 - 4 - read-write - - - VALUE - pin value for passive tamper - 8 - 2 - read-write - - - SPEED - tamper speed selection, (2^SPEED) changes per second -0: 1 shift per second -1: 2 shifts per second -. . . -15: 32768 shifts per second - 4 - 4 - read-write - - - RECOVER - tamper will recover itself if tamper LFSR goes wrong -0: tamper will not recover -1: tamper will recover - 2 - 1 - read-write - - - ACTIVE - select active or passive tamper -0: passive tamper -1: active tamper - 1 - 1 - read-write - - - ENABLE - enable tamper -0: tamper disableed -1: tamper enabled - 0 - 1 - read-write - - - - - POLY - Tamper n Polynomial of LFSR - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - POLY - tamper LFSR polyminal, this is a write once register, once write content is locked, and readout value is "1" - 0 - 32 - read-write - - - - - LFSR - Tamper n LFSR shift register - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - LFSR - LFSR for active tamper, write only register, always read 0 - 0 - 32 - write-only - - - - - - TAMP_FLAG - Tamper flag - 0x80 - 32 - 0x00000000 - 0x00000FFF - - - FLAG - tamper flag, each bit represents one tamper pin, write 1 to clear the flag -Note, clear can only be cleared when tamper disappeared - 0 - 12 - read-write - - - - - IRQ_EN - Tamper interrupt enable - 0x84 - 32 - 0x00000000 - 0x80000FFF - - - LOCK - lock bit for IRQ enable -0: enable bits can be changed -1: enable bits hold until next battery domain power cycle - 31 - 1 - read-write - - - IRQ_EN - interrupt enable, each bit represents one tamper pin -0: interrupt disabled -1: interrupt enabled - 0 - 12 - read-write - - - - - - - MONO - MONO - MONO - 0xf5054000 - - 0x0 - 0x8 - registers - - - - MONOL - Low part of monotonic counter - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - COUNTER - low part of monotonica counter, write to this counter will cause counter increase by 1 - 0 - 32 - read-write - - - - - MONOH - High part of monotonic counter - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - EPOCH - Fuse value for high part of monotonica - 16 - 16 - read-write - - - COUNTER - high part of monotonica counter, write to this counter will cause counter increase by 1 if low part overflow - 0 - 16 - read-write - - - - - - - diff --git a/svd/HPM64G0_svd.xml b/svd/HPM64G0_svd.xml deleted file mode 100644 index a66aa6c..0000000 --- a/svd/HPM64G0_svd.xml +++ /dev/null @@ -1,34201 +0,0 @@ - - - HPMICRO - HPM64G0 - HPM6700 - 1.0 - HPM6700/HPM6400 device - - /* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - - - other - r0p0 - little - false - true - true - 7 - false - - - - 8 - 32 - 32 - read-write - 0x0 - 0xFFFFFFFF - - - - - FGPIO - FGPIO - GPIO - 0xc0000 - - 0x0 - 0x800 - registers - - - - 16 - 0x10 - gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz - DI[%s] - no description available - 0x0 - - VALUE - GPIO input value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - INPUT - GPIO input bus value, each bit represents a bus bit -0: low level presents on chip pin -1: high level presents on chip pin - 0 - 32 - read-only - - - - - - 16 - 0x10 - gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz - DO[%s] - no description available - 0x100 - - VALUE - GPIO output value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - SET - GPIO output set - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - CLEAR - GPIO output clear - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - TOGGLE - GPIO output toggle - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - - 16 - 0x10 - gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz - OE[%s] - no description available - 0x200 - - VALUE - GPIO direction value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - SET - GPIO direction set - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - CLEAR - GPIO direction clear - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - TOGGLE - GPIO direction toggle - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - - 16 - 0x10 - gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz - IF[%s] - no description available - 0x300 - - VALUE - GPIO interrupt flag value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_FLAG - GPIO interrupt flag, write 1 to clear this flag -0: no irq -1: irq pending - 0 - 32 - write-only - - - - - - 16 - 0x10 - gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz - IE[%s] - no description available - 0x400 - - VALUE - GPIO interrupt enable value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - SET - GPIO interrupt enable set - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - CLEAR - GPIO interrupt enable clear - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - TOGGLE - GPIO interrupt enable toggle - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - - 16 - 0x10 - gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz - PL[%s] - no description available - 0x500 - - VALUE - GPIO interrupt polarity value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - SET - GPIO interrupt polarity set - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - CLEAR - GPIO interrupt polarity clear - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - TOGGLE - GPIO interrupt polarity toggle - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - - 16 - 0x10 - gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz - TP[%s] - no description available - 0x600 - - VALUE - GPIO interrupt type value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - SET - GPIO interrupt type set - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - CLEAR - GPIO interrupt type clear - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - TOGGLE - GPIO interrupt type toggle - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - - 16 - 0x10 - gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz - AS[%s] - no description available - 0x700 - - VALUE - GPIO interrupt asynchronous value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - SET - GPIO interrupt asynchronous set - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - CLEAR - GPIO interrupt asynchronous clear - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - TOGGLE - GPIO interrupt asynchronous toggle - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - - - - GPIO0 - GPIO0 - GPIO - 0xf0000000 - - - GPIO1 - GPIO1 - GPIO - 0xf0004000 - - - PGPIO - PGPIO - GPIO - 0xf40dc000 - - - BGPIO - BGPIO - GPIO - 0xf5014000 - - - PLIC - PLIC - PLIC - 0xe4000000 - - 0x0 - 0x202000 - registers - - - - feature - Feature enable register - 0x0 - 32 - 0x00000000 - 0x00000003 - - - VECTORED - Vector mode enable -0: Disabled -1: Enabled - 1 - 1 - read-write - - - PREEMPT - Preemptive priority interrupt enable -0: Disabled -1: Enabled - 0 - 1 - read-write - - - - - 127 - 0x4 - PRIORITY1,PRIORITY2,PRIORITY3,PRIORITY4,PRIORITY5,PRIORITY6,PRIORITY7,PRIORITY8,PRIORITY9,PRIORITY10,PRIORITY11,PRIORITY12,PRIORITY13,PRIORITY14,PRIORITY15,PRIORITY16,PRIORITY17,PRIORITY18,PRIORITY19,PRIORITY20,PRIORITY21,PRIORITY22,PRIORITY23,PRIORITY24,PRIORITY25,PRIORITY26,PRIORITY27,PRIORITY28,PRIORITY29,PRIORITY30,PRIORITY31,PRIORITY32,PRIORITY33,PRIORITY34,PRIORITY35,PRIORITY36,PRIORITY37,PRIORITY38,PRIORITY39,PRIORITY40,PRIORITY41,PRIORITY42,PRIORITY43,PRIORITY44,PRIORITY45,PRIORITY46,PRIORITY47,PRIORITY48,PRIORITY49,PRIORITY50,PRIORITY51,PRIORITY52,PRIORITY53,PRIORITY54,PRIORITY55,PRIORITY56,PRIORITY57,PRIORITY58,PRIORITY59,PRIORITY60,PRIORITY61,PRIORITY62,PRIORITY63,PRIORITY64,PRIORITY65,PRIORITY66,PRIORITY67,PRIORITY68,PRIORITY69,PRIORITY70,PRIORITY71,PRIORITY72,PRIORITY73,PRIORITY74,PRIORITY75,PRIORITY76,PRIORITY77,PRIORITY78,PRIORITY79,PRIORITY80,PRIORITY81,PRIORITY82,PRIORITY83,PRIORITY84,PRIORITY85,PRIORITY86,PRIORITY87,PRIORITY88,PRIORITY89,PRIORITY90,PRIORITY91,PRIORITY92,PRIORITY93,PRIORITY94,PRIORITY95,PRIORITY96,PRIORITY97,PRIORITY98,PRIORITY99,PRIORITY100,PRIORITY101,PRIORITY102,PRIORITY103,PRIORITY104,PRIORITY105,PRIORITY106,PRIORITY107,PRIORITY108,PRIORITY109,PRIORITY110,PRIORITY111,PRIORITY112,PRIORITY113,PRIORITY114,PRIORITY115,PRIORITY116,PRIORITY117,PRIORITY118,PRIORITY119,PRIORITY120,PRIORITY121,PRIORITY122,PRIORITY123,PRIORITY124,PRIORITY125,PRIORITY126,PRIORITY127 - PRIORITY[%s] - no description available - 0x4 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - 4 - 0x4 - PENDING0,PENDING1,PENDING2,PENDING3 - PENDING[%s] - no description available - 0x1000 - 32 - 0x00000000 - 0xFFFFFFFF - - - INTERRUPT - The interrupt pending status of inpterrupt sources. Every interrupt source occupies 1 bit. - 0 - 32 - read-write - - - - - 4 - 0x4 - TRIGGER0,TRIGGER1,TRIGGER2,TRIGGER3 - TRIGGER[%s] - no description available - 0x1080 - 32 - 0x00000000 - 0xFFFFFFFF - - - INTERRUPT - The interrupt trigger type of interrupt sources. Every interrupt source occupies 1 bit. -0: Level-triggered interrupt -1: Edge-triggered interrupt - 0 - 32 - read-only - - - - - NUMBER - Number of supported interrupt sources and targets - 0x1100 - 32 - 0xFFFFFFFF - - - NUM_TARGET - The number of supported targets - 16 - 16 - read-only - - - NUM_INTERRUPT - The number of supported interrupt sources - 0 - 16 - read-only - - - - - INFO - Version and the maximum priority - 0x1104 - 32 - 0xFFFFFFFF - - - MAX_PRIORITY - The maximum priority supported - 16 - 16 - read-only - - - VERSION - The version of the PLIC design - 0 - 16 - read-only - - - - - 2 - 0x80 - target0,target1 - TARGETINT[%s] - no description available - 0x2000 - - 4 - 0x4 - INTEN0,INTEN1,INTEN2,INTEN3 - INTEN[%s] - no description available - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - INTERRUPT - The interrupt enable bit for interrupt. Every interrupt source occupies 1 bit. - 0 - 32 - read-write - - - - - - 2 - 0x1000 - target0,target1 - TARGETCONFIG[%s] - no description available - 0x200000 - - THRESHOLD - Target0 priority threshold - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - THRESHOLD - Interrupt priority threshold. - 0 - 32 - read-write - - - - - CLAIM - Target claim and complete - 0x4 - 32 - 0x00000000 - 0x000003FF - - - INTERRUPT_ID - On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed). - 0 - 10 - read-write - - - - - PPS - Preempted priority stack - 0x400 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRIORITY_PREEMPTED - Each bit indicates if the corresponding priority level has been preempted by a higher-priority interrupt. - 0 - 32 - read-write - - - - - - - - MCHTMR - MCHTMR - MCHTMR - 0xe6000000 - - 0x0 - 0x10 - registers - - - - MTIME - Machine Time - 0x0 - 64 - 0x0000000000020210 - 0xFFFFFFFFFFFFFFFF - - - MTIME - Machine time - 0 - 64 - read-write - - - - - MTIMECMP - Machine Time Compare - 0x8 - 64 - 0x0000000000020210 - 0xFFFFFFFFFFFFFFFF - - - MTIMECMP - Machine time compare - 0 - 64 - read-write - - - - - - - PLICSW - PLICSW - PLICSW - 0xe6400000 - - 0x1000 - 0x1ff008 - registers - - - - PENDING - Pending status - 0x1000 - 32 - 0x00000000 - 0x00000002 - - - INTERRUPT - writing 1 to trigger software interrupt - 1 - 1 - read-write - - - - - INTEN - Interrupt enable - 0x2000 - 32 - 0x00000000 - 0x00000001 - - - INTERRUPT - enable software interrupt - 0 - 1 - read-write - - - - - CLAIM - Claim and complete. - 0x200004 - 32 - 0x00000000 - 0x00000001 - - - INTERRUPT_ID - On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed). - 0 - 1 - read-write - - - - - - - GPIOM - GPIOM - GPIOM - 0xf0008000 - - 0x0 - 0x800 - registers - - - - 16 - 0x80 - gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz - ASSIGN[%s] - no description available - 0x0 - - 32 - 0x4 - PIN00,PIN01,PIN02,PIN03,PIN04,PIN05,PIN06,PIN07,PIN08,PIN09,PIN10,PIN11,PIN12,PIN13,PIN14,PIN15,PIN16,PIN17,PIN18,PIN19,PIN20,PIN21,PIN22,PIN23,PIN24,PIN25,PIN26,PIN27,PIN28,PIN29,PIN30,PIN31 - PIN[%s] - no description available - 0x0 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - - - - ADC0 - ADC0 - ADC12 - 0xf0010000 - - 0x0 - 0x1214 - registers - - - - 12 - 0x4 - trg0a,trg0b,trg0c,trg1a,trg1b,trg1c,trg2a,trg2b,trg2c,trg3a,trg3b,trg3c - CONFIG[%s] - no description available - 0x0 - 32 - 0x00000000 - 0xFF3F3F3F - - - TRIG_LEN - length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 - 30 - 2 - write-only - - - INTEN3 - interrupt enable for 4th conversion - 29 - 1 - read-write - - - CHAN3 - channel number for 4th conversion - 24 - 5 - read-write - - - INTEN2 - interrupt enable for 3rd conversion - 21 - 1 - read-write - - - CHAN2 - channel number for 3rd conversion - 16 - 5 - read-write - - - INTEN1 - interrupt enable for 2nd conversion - 13 - 1 - read-write - - - CHAN1 - channel number for 2nd conversion - 8 - 5 - read-write - - - INTEN0 - interrupt enable for 1st conversion - 5 - 1 - read-write - - - CHAN0 - channel number for 1st conversion - 0 - 5 - read-write - - - - - trg_dma_addr - No description available - 0x30 - 32 - 0x00000000 - 0xFFFFFFFC - - - TRG_DMA_ADDR - buffer start address for trigger queue, 192byte total, 16 bytes for each trigger (4 bytes for each conversion) - 2 - 30 - read-write - - - - - trg_sw_sta - No description available - 0x34 - 32 - 0x00000000 - 0x0000001F - - - TRG_SW_STA - SW trigger start bit, HW will clear it after all conversions(up to 4) finished. SW should make sure it's 0 before set it. - 4 - 1 - read-write - - - TRIG_SW_INDEX - which trigger for the SW trigger -0 for trig0a, 1 for trig0b… -3 for trig1a, …11 for trig3c - 0 - 4 - read-write - - - - - 19 - 0x4 - chn0,chn1,chn2,chn3,chn4,chn5,chn6,chn7,chn8,chn9,chn10,chn11,chn12,chn13,chn14,chn15,chn16,chn17,chn18 - BUS_RESULT[%s] - no description available - 0x400 - 32 - 0x00000000 - 0x0001FFF0 - - - VALID - set after conversion finished if wait_dis is set, cleared after software read. -The first time read with 0 will trigger one new conversion. -If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. -the result may not realtime if software read once and wait long time to read again - 16 - 1 - read-only - - - CHAN_RESULT - read this register will trigger one adc conversion. -If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result -If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long - 4 - 12 - read-only - - - - - buf_cfg0 - No description available - 0x500 - 32 - 0x00000000 - 0x00000001 - - - WAIT_DIS - set to disable read waiting, get result immediately but maybe not current conversion result. - 0 - 1 - read-write - - - - - seq_cfg0 - No description available - 0x800 - 32 - 0x00000000 - 0x80000F1F - - - CYCLE - current dma write cycle bit - 31 - 1 - read-only - - - SEQ_LEN - sequence queue length, 0 for one, 0xF for 16 - 8 - 4 - read-write - - - RESTART_EN - if set together with cont_en, HW will continue process the whole queue after trigger once. -If cont_en is 0, this bit is not used - 4 - 1 - read-write - - - CONT_EN - if set, HW will continue process the queue till end(seq_len) after trigger once - 3 - 1 - read-write - - - SW_TRIG - SW trigger, pulse signal, cleared by HW one cycle later - 2 - 1 - write-only - - - SW_TRIG_EN - set to enable SW trigger - 1 - 1 - read-write - - - HW_TRIG_EN - set to enable external HW trigger, only trigger on posedge - 0 - 1 - read-write - - - - - seq_dma_addr - No description available - 0x804 - 32 - 0x00000000 - 0xFFFFFFFC - - - TAR_ADDR - dma target address, should be 4-byte aligned - 2 - 30 - read-write - - - - - seq_wr_addr - No description available - 0x808 - 32 - 0x00000000 - 0x00000FFF - - - SEQ_WR_POINTER - HW update this field after each dma write, it indicate the next dma write pointer. -dma write address is (tar_addr+seq_wr_pointer)*4 - 0 - 12 - read-only - - - - - seq_dma_cfg - No description available - 0x80c - 32 - 0x00000000 - 0x0FFF3FFF - - - STOP_POS - if stop_en is set, SW is responsible to update this field to the next read point, HW should not write data to this point since it's not read out by SW yet - 16 - 12 - read-write - - - DMA_RST - set this bit will reset HW dma write pointer to seq_dma_addr, and set HW cycle bit to 1. dma is halted if this bit is set. -SW should clear all cycle bit in buffer to 0 before clear dma_rst - 13 - 1 - read-write - - - STOP_EN - set to stop dma if reach the stop_pos - 12 - 1 - read-write - - - BUF_LEN - dma buffer length, after write to (tar_addr[31:2]+buf_len)*4, the next dma address will be tar_addr[31:2]*4 -0 for 4byte; -0xFFF for 16kbyte. - 0 - 12 - read-write - - - - - 16 - 0x4 - cfg0,cfg1,cfg2,cfg3,cfg4,cfg5,cfg6,cfg7,cfg8,cfg9,cfg10,cfg11,cfg12,cfg13,cfg14,cfg15 - SEQ_QUE[%s] - no description available - 0x810 - 32 - 0x00000000 - 0x0000003F - - - SEQ_INT_EN - interrupt enable for current conversion - 5 - 1 - read-write - - - CHAN_NUM_4_0 - channel number for current conversion - 0 - 5 - read-write - - - - - 19 - 0x10 - chn0,chn1,chn2,chn3,chn4,chn5,chn6,chn7,chn8,chn9,chn10,chn11,chn12,chn13,chn14,chn15,chn16,chn17,chn18 - PRD_CFG[%s] - no description available - 0xc00 - - prd_cfg - No description available - 0x0 - 32 - 0x00000000 - 0x00001FFF - - - PRESCALE - 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx - 8 - 5 - read-write - - - PRD - conver period, with prescale. -Set to 0 means disable current channel - 0 - 8 - read-write - - - - - prd_thshd_cfg - No description available - 0x4 - 32 - 0x00000000 - 0xFFF0FFF0 - - - THSHDH - threshold high, assert interrupt(if enabled) if result exceed high or low. - 20 - 12 - read-write - - - THSHDL - threshold low - 4 - 12 - read-write - - - - - prd_result - No description available - 0x8 - 32 - 0x00000000 - 0x0000FFF0 - - - CHAN_RESULT - adc convert result, update after each valid conversion. -it may be updated period according to config, also may be updated due to other queue convert the same channel - 4 - 12 - read-only - - - - - - 19 - 0x4 - chn0,chn1,chn2,chn3,chn4,chn5,chn6,chn7,chn8,chn9,chn10,chn11,chn12,chn13,chn14,chn15,chn16,chn17,chn18 - SAMPLE_CFG[%s] - no description available - 0x1000 - 32 - 0x00000000 - 0x00001FFF - - - DIFF_SEL - set to 1 to select differential channel - 12 - 1 - read-write - - - SAMPLE_CLOCK_NUMBER_SHIFT - shift for sample_clock_number - 9 - 3 - read-write - - - SAMPLE_CLOCK_NUMBER - sample clock number, base on clock_period, default one period - 0 - 9 - read-write - - - - - conv_cfg1 - No description available - 0x1104 - 32 - 0x00000000 - 0x000001FF - - - CONVERT_CLOCK_NUMBER - convert clock numbers, set to 13 (0xD) for 12bit mode, which means convert need 14 adc clock cycles(based on clock after divider); -set to 11 for 10bit mode; set to 9 for 8bit mode; set to 7 or 6bit mode; -Ex: use 200MHz bus clock for adc, set sample_clock_number to 4, sample_clock_number_shift to 0, covert_clk_number to 13 for 12bit mode, clock_divder to 2, then each ADC conversion(plus sample) need 18(14 convert, 4 sample) cycles(66MHz). - 4 - 5 - read-write - - - CLOCK_DIVIDER - clock_period, N half clock cycle per half adc cycle -0 for same adc_clk and bus_clk, -1 for 1:2, -2 for 1:3, -... -15 for 1:16 -Note: set to 2 can genenerate 66.7MHz adc_clk at 200MHz bus_clk - 0 - 4 - read-write - - - - - adc_cfg0 - No description available - 0x1108 - 32 - 0x00000000 - 0xA0000000 - - - SEL_SYNC_AHB - set to 1 will enable sync AHB bus, to get better bus performance. -Adc_clk must to be set to same as bus clock at this mode - 31 - 1 - read-write - - - ADC_AHB_EN - set to 1 to enable ADC DMA to write data to soc memory bus, for trig queue and seq queue; - 29 - 1 - read-write - - - - - int_sts - No description available - 0x1110 - 32 - 0x00000000 - 0xFFE7FFFF - - - TRIG_CMPT - interrupt for one trigger conversion complete if enabled - 31 - 1 - read-write - - - TRIG_SW_CFLCT - No description available - 30 - 1 - read-write - - - TRIG_HW_CFLCT - No description available - 29 - 1 - read-write - - - READ_CFLCT - read conflict interrupt, set if wait_dis is set, one conversion is in progress, SW read another channel - 28 - 1 - read-write - - - SEQ_SW_CFLCT - sequence queue conflict interrupt, set if HW or SW trigger received during conversion - 27 - 1 - read-write - - - SEQ_HW_CFLCT - No description available - 26 - 1 - read-write - - - SEQ_DMAABT - dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set - 25 - 1 - read-write - - - SEQ_CMPT - the whole sequence complete interrupt - 24 - 1 - read-write - - - SEQ_CVC - one conversion complete in seq_queue if related seq_int_en is set - 23 - 1 - read-write - - - DMA_FIFO_FULL - No description available - 22 - 1 - read-write - - - AHB_ERR - set if got hresp=1 - 21 - 1 - read-write - - - WDOG - set if one chanel watch dog event triggered - 0 - 19 - read-write - - - - - int_en - No description available - 0x1114 - 32 - 0x00000000 - 0xFFE7FFFF - - - TRIG_CMPT - interrupt for one trigger conversion complete if enabled - 31 - 1 - read-write - - - TRIG_SW_CFLCT - No description available - 30 - 1 - read-write - - - TRIG_HW_CFLCT - No description available - 29 - 1 - read-write - - - READ_CFLCT - read conflict interrupt, set if wait_dis is set, one conversion is in progress, SW read another channel - 28 - 1 - read-write - - - SEQ_SW_CFLCT - sequence queue conflict interrupt, set if HW or SW trigger received during conversion - 27 - 1 - read-write - - - SEQ_HW_CFLCT - No description available - 26 - 1 - read-write - - - SEQ_DMAABT - dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set - 25 - 1 - read-write - - - SEQ_CMPT - the whole sequence complete interrupt - 24 - 1 - read-write - - - SEQ_CVC - one conversion complete in seq_queue if related seq_int_en is set - 23 - 1 - read-write - - - DMA_FIFO_FULL - DMA fifo full interrupt, user need to check clock frequency if it's set. - 22 - 1 - read-write - - - AHB_ERR - set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr - 21 - 1 - read-write - - - WDOG - set if one chanel watch dog event triggered - 0 - 19 - read-write - - - - - ana_ctrl0 - No description available - 0x1200 - 32 - 0x00000000 - 0x7F7F487E - - - CAL_VAL_DIFF - calibration value for differential mode - 24 - 7 - read-write - - - CAL_VAL_SE - calibration value for single-end mode - 16 - 7 - read-write - - - REARM_EN - set will insert one adc cycle rearm before sample, user need to increase one to sample_clock_number - 14 - 1 - read-write - - - SELRANGE_LDO - Defines the range for the LDO reference (vdd_soc) -selrange_ldo = 0: LDO reference dvdd or vref_ldo in range [0.81;0.99] -selrange_ldo = 1: LDO reference dvdd or vref_ldo in range [0.99;1.21] - 11 - 1 - read-write - - - ENLDO - set to enable adc LDO, need at least 20us for LDO to be stable. - 6 - 1 - read-write - - - ENADC - set to enable adc analog function. user need set it after LDO stable, or wait at least 20us after setting enldo, then set this bit. - 5 - 1 - read-write - - - RESETADC - set to 1 to reset adc analog; default high. - 4 - 1 - read-write - - - RESETCAL - set to 1 to reset calibration logic; default high. - 3 - 1 - read-write - - - STARTCAL - set to start the offset calibration cycle (Active H). user need to clear it after setting it. - 2 - 1 - read-write - - - LOADCAL - Signal that loads the offset calibration word into the internal registers (Active H) - 1 - 1 - read-write - - - - - ana_ctrl1 - No description available - 0x1204 - 32 - 0x00000000 - 0x000000C0 - - - SELRES - 11-12bit -10-10bit -01-8bit -00-6bit - 6 - 2 - read-write - - - - - ana_status - No description available - 0x1210 - 32 - 0x00000000 - 0x000000FF - - - CALON - Indicates if the ADC is in calibration mode (Active H). - 7 - 1 - read-write - - - CAL_OUT - No description available - 0 - 7 - read-write - - - - - - - ADC1 - ADC1 - ADC12 - 0xf0014000 - - - ADC2 - ADC2 - ADC12 - 0xf0018000 - - - ADC3 - ADC3 - ADC16 - 0xf001c000 - - 0x0 - 0x1464 - registers - - - - 12 - 0x4 - trg0a,trg0b,trg0c,trg1a,trg1b,trg1c,trg2a,trg2b,trg2c,trg3a,trg3b,trg3c - CONFIG[%s] - no description available - 0x0 - 32 - 0x00000000 - 0xFF3F3F3F - - - TRIG_LEN - length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 - 30 - 2 - write-only - - - INTEN3 - interrupt enable for 4th conversion - 29 - 1 - read-write - - - CHAN3 - channel number for 4th conversion - 24 - 5 - read-write - - - INTEN2 - interrupt enable for 3rd conversion - 21 - 1 - read-write - - - CHAN2 - channel number for 3rd conversion - 16 - 5 - read-write - - - INTEN1 - interrupt enable for 2nd conversion - 13 - 1 - read-write - - - CHAN1 - channel number for 2nd conversion - 8 - 5 - read-write - - - INTEN0 - interrupt enable for 1st conversion - 5 - 1 - read-write - - - CHAN0 - channel number for 1st conversion - 0 - 5 - read-write - - - - - trg_dma_addr - No description available - 0x30 - 32 - 0x00000000 - 0xFFFFFFFC - - - TRG_DMA_ADDR - buffer start address for trigger queue, 192byte total, 16 bytes for each trigger (4 bytes for each conversion) - 2 - 30 - read-write - - - - - trg_sw_sta - No description available - 0x34 - 32 - 0x00000000 - 0x0000001F - - - TRG_SW_STA - SW trigger start bit, HW will clear it after all conversions(up to 4) finished. SW should make sure it's 0 before set it. - 4 - 1 - read-write - - - TRIG_SW_INDEX - which trigger for the SW trigger -0 for trig0a, 1 for trig0b… -3 for trig1a, …11 for trig3c - 0 - 4 - read-write - - - - - 8 - 0x4 - chn0,chn1,chn2,chn3,chn4,chn5,chn6,chn7 - BUS_RESULT[%s] - no description available - 0x400 - 32 - 0x00000000 - 0x0001FFFF - - - VALID - set after conversion finished if wait_dis is set, cleared after software read. -The first time read with 0 will trigger one new conversion. -If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. -the result may not realtime if software read once and wait long time to read again - 16 - 1 - read-only - - - CHAN_RESULT - read this register will trigger one adc conversion. -If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result -If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long - 0 - 16 - read-only - - - - - buf_cfg0 - No description available - 0x500 - 32 - 0x00000000 - 0x00000001 - - - WAIT_DIS - set to disable read waiting, get result immediately but maybe not current conversion result. - 0 - 1 - read-write - - - - - seq_cfg0 - No description available - 0x800 - 32 - 0x00000000 - 0x80000F1F - - - CYCLE - current dma write cycle bit - 31 - 1 - read-only - - - SEQ_LEN - sequence queue length, 0 for one, 0xF for 16 - 8 - 4 - read-write - - - RESTART_EN - if set together with cont_en, HW will continue process the whole queue after trigger once. -If cont_en is 0, this bit is not used - 4 - 1 - read-write - - - CONT_EN - if set, HW will continue process the queue till end(seq_len) after trigger once - 3 - 1 - read-write - - - SW_TRIG - SW trigger, pulse signal, cleared by HW one cycle later - 2 - 1 - write-only - - - SW_TRIG_EN - set to enable SW trigger - 1 - 1 - read-write - - - HW_TRIG_EN - set to enable external HW trigger, only trigger on posedge - 0 - 1 - read-write - - - - - seq_dma_addr - No description available - 0x804 - 32 - 0x00000000 - 0xFFFFFFFC - - - TAR_ADDR - dma target address, should be 4-byte aligned - 2 - 30 - read-write - - - - - seq_dma_cfg - No description available - 0x80c - 32 - 0x00000000 - 0x0FFF3FFF - - - STOP_POS - if stop_en is set, SW is responsible to update this field to the next read point, HW should not write data to this point since it's not read out by SW yet - 16 - 12 - read-write - - - DMA_RST - set this bit will reset HW dma write pointer to seq_dma_addr, and set HW cycle bit to 1. dma is halted if this bit is set. -SW should clear all cycle bit in buffer to 0 before clear dma_rst - 13 - 1 - read-write - - - STOP_EN - set to stop dma if reach the stop_pos - 12 - 1 - read-write - - - BUF_LEN - dma buffer length, after write to (tar_addr[31:2]+buf_len)*4, the next dma address will be tar_addr[31:2]*4 -0 for 4byte; -0xFFF for 16kbyte. - 0 - 12 - read-write - - - - - 16 - 0x4 - cfg0,cfg1,cfg2,cfg3,cfg4,cfg5,cfg6,cfg7,cfg8,cfg9,cfg10,cfg11,cfg12,cfg13,cfg14,cfg15 - SEQ_QUE[%s] - no description available - 0x810 - 32 - 0x00000000 - 0x0000003F - - - SEQ_INT_EN - interrupt enable for current conversion - 5 - 1 - read-write - - - CHAN_NUM_4_0 - channel number for current conversion - 0 - 5 - read-write - - - - - 8 - 0x10 - chn0,chn1,chn2,chn3,chn4,chn5,chn6,chn7 - PRD_CFG[%s] - no description available - 0xc00 - - prd_cfg - No description available - 0x0 - 32 - 0x00000000 - 0x00001FFF - - - PRESCALE - 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx - 8 - 5 - read-write - - - PRD - conver period, with prescale. -Set to 0 means disable current channel - 0 - 8 - read-write - - - - - prd_thshd_cfg - No description available - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - THSHDH - threshold high, assert interrupt(if enabled) if result exceed high or low. - 16 - 16 - read-write - - - THSHDL - threshold low - 0 - 16 - read-write - - - - - prd_result - No description available - 0x8 - 32 - 0x00000000 - 0x0000FFFF - - - CHAN_RESULT - adc convert result, update after each valid conversion. -it may be updated period according to config, also may be updated due to other queue convert the same channel - 0 - 16 - read-only - - - - - - 8 - 0x4 - chn0,chn1,chn2,chn3,chn4,chn5,chn6,chn7 - SAMPLE_CFG[%s] - no description available - 0x1000 - 32 - 0x00000000 - 0x00000FFF - - - SAMPLE_CLOCK_NUMBER_SHIFT - shift for sample clock number - 9 - 3 - read-write - - - SAMPLE_CLOCK_NUMBER - sample clock number, base on clock_period, default one period - 0 - 9 - read-write - - - - - conv_cfg1 - No description available - 0x1104 - 32 - 0x00000000 - 0x000001FF - - - CONVERT_CLOCK_NUMBER - convert clock numbers, set to 21 (0x15) for 16bit mode, which means convert need 21 adc clock cycles(based on clock after divider); -user can use small value to get faster conversion, but less accuracy, need to config cov_end_cnt at adc16_config1 also. -Ex: use 200MHz bus clock for adc, set sample_clock_number to 4, sample_clock_number_shift to 0, covert_clk_number to 21 for 16bit mode, clock_divder to 3, then each ADC conversion(plus sample) need 25 cycles(50MHz). - 4 - 5 - read-write - - - CLOCK_DIVIDER - clock_period, N half clock cycle per half adc cycle -0 for same adc_clk and bus_clk, -1 for 1:2, -2 for 1:3, -... -15 for 1:16 -Note: set to 2 can genenerate 66.7MHz adc_clk at 200MHz bus_clk - 0 - 4 - read-write - - - - - adc_cfg0 - No description available - 0x1108 - 32 - 0x00000000 - 0xA0000001 - - - SEL_SYNC_AHB - set to 1 will enable sync AHB bus, to get better bus performance. -Adc_clk must to be set to same as bus clock at this mode - 31 - 1 - read-write - - - ADC_AHB_EN - set to 1 to enable ADC DMA to write data to soc memory bus, for trig queue and seq queue; - 29 - 1 - read-write - - - PORT3_REALTIME - set to enable trg queue stop other queues - 0 - 1 - read-write - - - - - int_sts - No description available - 0x1110 - 32 - 0x00000000 - 0xFFE0FFFF - - - TRIG_CMPT - interrupt for one trigger conversion complete if enabled - 31 - 1 - read-write - - - TRIG_SW_CFLCT - No description available - 30 - 1 - read-write - - - TRIG_HW_CFLCT - No description available - 29 - 1 - read-write - - - READ_CFLCT - read conflict interrupt, set if wait_dis is set, one conversion is in progress, SW read another channel - 28 - 1 - read-write - - - SEQ_SW_CFLCT - sequence queue conflict interrupt, set if HW or SW trigger received during conversion - 27 - 1 - read-write - - - SEQ_HW_CFLCT - No description available - 26 - 1 - read-write - - - SEQ_DMAABT - dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set - 25 - 1 - read-write - - - SEQ_CMPT - the whole sequence complete interrupt - 24 - 1 - read-write - - - SEQ_CVC - one conversion complete in seq_queue if related seq_int_en is set - 23 - 1 - read-write - - - DMA_FIFO_FULL - DMA fifo full interrupt, user need to check clock frequency if it's set. - 22 - 1 - read-write - - - AHB_ERR - set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr - 21 - 1 - read-write - - - WDOG - set if one chanel watch dog event triggered - 0 - 16 - read-write - - - - - int_en - No description available - 0x1114 - 32 - 0x00000000 - 0xFFE0FFFF - - - TRIG_CMPT - interrupt for one trigger conversion complete if enabled - 31 - 1 - read-write - - - TRIG_SW_CFLCT - No description available - 30 - 1 - read-write - - - TRIG_HW_CFLCT - No description available - 29 - 1 - read-write - - - READ_CFLCT - read conflict interrupt, set if wait_dis is set, one conversion is in progress, SW read another channel - 28 - 1 - read-write - - - SEQ_SW_CFLCT - sequence queue conflict interrupt, set if HW or SW trigger received during conversion - 27 - 1 - read-write - - - SEQ_HW_CFLCT - No description available - 26 - 1 - read-write - - - SEQ_DMAABT - dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set - 25 - 1 - read-write - - - SEQ_CMPT - the whole sequence complete interrupt - 24 - 1 - read-write - - - SEQ_CVC - one conversion complete in seq_queue if related seq_int_en is set - 23 - 1 - read-write - - - DMA_FIFO_FULL - DMA fifo full interrupt, user need to check clock frequency if it's set. - 22 - 1 - read-write - - - AHB_ERR - set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr - 21 - 1 - read-write - - - WDOG - set if one chanel watch dog event triggered - 0 - 16 - read-write - - - - - ana_ctrl0 - No description available - 0x1200 - 32 - 0x00000000 - 0x00001004 - - - ADC_CLK_ON - set to enable adc clock to analog, Software should set this bit before access to any adc16_* register. -MUST set clock_period to 0 or 1 for adc16 reg access - 12 - 1 - read-write - - - STARTCAL - set to start the offset calibration cycle (Active H). user need to clear it after setting it. - 2 - 1 - read-write - - - - - ana_status - No description available - 0x1210 - 32 - 0x00000000 - 0x00000080 - - - CALON - Indicates if the ADC is in calibration mode (Active H). - 7 - 1 - read-write - - - - - 34 - 0x2 - adc16_para00,adc16_para01,adc16_para02,adc16_para03,adc16_para04,adc16_para05,adc16_para06,adc16_para07,adc16_para08,adc16_para09,adc16_para10,adc16_para11,adc16_para12,adc16_para13,adc16_para14,adc16_para15,adc16_para16,adc16_para17,adc16_para18,adc16_para19,adc16_para20,adc16_para21,adc16_para22,adc16_para23,adc16_para24,adc16_para25,adc16_para26,adc16_para27,adc16_para28,adc16_para29,adc16_para30,adc16_para31,adc16_para32,adc16_para33 - ADC16_PARAMS[%s] - no description available - 0x1400 - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description available - 0 - 16 - read-write - - - - - adc16_config0 - No description available - 0x1444 - 32 - 0x00000000 - 0x03F07FFF - - - TEMPSNS_EN - set to enable temp sensor - 25 - 1 - read-write - - - REG_EN - set to enable regulator - 24 - 1 - read-write - - - BANDGAP_EN - set to enable bandgap. user should set reg_en and bandgap_en before use adc16. - 23 - 1 - read-write - - - CAL_AVG_CFG - for average the calibration result. -0- 1 loop; 1- 2 loops; 2- 4 loops; 3- 8 loops; -4- 16 loops; 5-32 loops; others reserved - 20 - 3 - read-write - - - PREEMPT_EN - set to enable preemption feature - 14 - 1 - read-write - - - CONV_PARAM - conversion parameter - 0 - 14 - read-write - - - - - adc16_config1 - No description available - 0x1460 - 32 - 0x00000000 - 0x00001F00 - - - COV_END_CNT - used for faster conversion, user can change it to get higher convert speed(but less accuracy). -should set to (21-convert_clock_number+1). - 8 - 5 - read-write - - - - - - - ACMP - ACMP - ACMP - 0xf0020000 - - 0x0 - 0x80 - registers - - - - 4 - 0x20 - chn0,chn1,chn2,chn3 - CHANNEL[%s] - no description available - 0x0 - - cfg - Configure Register - 0x0 - 32 - 0x00000000 - 0xFF7FFFFF - - - HYST - This bitfield configure the comparator hysteresis. -00: Hysteresis level 0 -01: Hysteresis level 1 -10: Hysteresis level 2 -11: Hysteresis level 3 - 30 - 2 - read-write - - - DACEN - This bit enable the comparator internal DAC -0: DAC disabled -1: DAC enabled - 29 - 1 - read-write - - - HPMODE - This bit enable the comparator high performance mode. -0: HP mode disabled -1: HP mode enabled - 28 - 1 - read-write - - - CMPEN - This bit enable the comparator. -0: ACMP disabled -1: ACMP enabled - 27 - 1 - read-write - - - MINSEL - PIN select, from pad_ai_acmp[7:1] and dac_out - 24 - 3 - read-write - - - PINSEL - MIN select, from pad_ai_acmp[7:1] and dac_out - 20 - 3 - read-write - - - CMPOEN - This bit enable the comparator output on pad. -0: ACMP output disabled -1: ACMP output enabled - 19 - 1 - read-write - - - FLTBYPS - This bit bypass the comparator output digital filter. -0: The ACMP output need pass digital filter -1: The ACMP output digital filter is bypassed. - 18 - 1 - read-write - - - WINEN - This bit enable the comparator window mode. -0: Window mode is disabled -1: Window mode is enabled - 17 - 1 - read-write - - - OPOL - The output polarity control bit. -0: The ACMP output remain un-changed. -1: The ACMP output is inverted. - 16 - 1 - read-write - - - FLTMODE - This bitfield define the ACMP output digital filter mode: -000-bypass -100-change immediately; -101-change after filter; -110-stalbe low; -111-stable high - 13 - 3 - read-write - - - SYNCEN - This bit enable the comparator output synchronization. -0: ACMP output not synchronized with ACMP clock. -1: ACMP output synchronized with ACMP clock. - 12 - 1 - read-write - - - FLTLEN - This bitfield define the ACMP output digital filter length. The unit is ACMP clock cycle. - 0 - 12 - read-write - - - - - daccfg - DAC configure register - 0x4 - 32 - 0x00000000 - 0x000000FF - - - DACCFG - 8bit DAC digital value output to analog block - 0 - 8 - read-write - - - - - sr - Status register - 0x10 - 32 - 0x00000000 - 0x00000003 - - - FEDGF - Output falling edge flag. Write 1 to clear this flag. - 1 - 1 - read-write - - - REDGF - Output rising edge flag. Write 1 to clear this flag. - 0 - 1 - read-write - - - - - irqen - Interrupt request enable register - 0x14 - 32 - 0x00000000 - 0x00000003 - - - FEDGEN - Output falling edge flag interrupt enable bit. - 1 - 1 - read-write - - - REDGEN - Output rising edge flag interrupt enable bit. - 0 - 1 - read-write - - - - - dmaen - DMA request enable register - 0x18 - 32 - 0x00000000 - 0x00000003 - - - FEDGEN - Output falling edge flag DMA request enable bit. - 1 - 1 - read-write - - - REDGEN - Output rising edge flag DMA request enable bit. - 0 - 1 - read-write - - - - - - - - SPI0 - SPI0 - SPI - 0xf0030000 - - 0x10 - 0x70 - registers - - - - TransFmt - Transfer Format Register - 0x10 - 32 - 0x00020780 - 0xFFFF1F9F - - - ADDRLEN - Address length in bytes -0x0: 1 byte -0x1: 2 bytes -0x2: 3 bytes -0x3: 4 bytes - 16 - 2 - read-write - - - DATALEN - The length of each data unit in bits -The actual bit number of a data unit is (DataLen + 1) - 8 - 5 - read-write - - - DATAMERGE - Enable Data Merge mode, which does automatic data split on write and data coalescing on read. -This bit only takes effect when DataLen = 0x7. Under Data Merge mode, each write to the Data Register will transmit all fourbytes of the write data; each read from the Data Register will retrieve four bytes of received data as a single word data. -When Data Merge mode is disabled, only the least (DataLen+1) significient bits of the Data Register are valid for read/write operations; no automatic data split/coalescing will be performed. - 7 - 1 - read-write - - - MOSIBIDIR - Bi-directional MOSI in regular (single) mode -0x0: MOSI is uni-directional signal in regular mode. -0x1: MOSI is bi-directional signal in regular mode. This bi-directional signal replaces the two - 4 - 1 - read-write - - - LSB - Transfer data with the least significant bit first -0x0: Most significant bit first -0x1: Least significant bit first - 3 - 1 - read-write - - - SLVMODE - SPI Master/Slave mode selection -0x0: Master mode -0x1: Slave mode - 2 - 1 - read-write - - - CPOL - SPI Clock Polarity -0x0: SCLK is LOW in the idle states -0x1: SCLK is HIGH in the idle states - 1 - 1 - read-write - - - CPHA - SPI Clock Phase -0x0: Sampling data at odd SCLK edges -0x1: Sampling data at even SCLK edges - 0 - 1 - read-write - - - - - TransCtrl - Transfer Control Register - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - SLVDATAONLY - Data-only mode (slave mode only) -0x0: Disable the data-only mode -0x1: Enable the data-only mode -Note: This mode only works in the uni-directional regular (single) mode so MOSIBiDir, DualQuad and TransMode should be set to 0. - 31 - 1 - read-write - - - CMDEN - SPI command phase enable (Master mode only) -0x0: Disable the command phase -0x1: Enable the command phase - 30 - 1 - read-write - - - ADDREN - SPI address phase enable (Master mode only) -0x0: Disable the address phase -0x1: Enable the address phase - 29 - 1 - read-write - - - ADDRFMT - SPI address phase format (Master mode only) -0x0: Address phase is the regular (single) mode -0x1: The format of the address phase is the same as the data phase (DualQuad). - 28 - 1 - read-write - - - TRANSMODE - Transfer mode -The transfer sequence could be -0x0: Write and read at the same time -0x1: Write only -0x2: Read only -0x3: Write, Read -0x4: Read, Write -0x5: Write, Dummy, Read -0x6: Read, Dummy, Write -0x7: None Data (must enable CmdEn or AddrEn in master mode) -0x8: Dummy, Write -0x9: Dummy, Read -0xa~0xf: Reserved - 24 - 4 - read-write - - - DUALQUAD - SPI data phase format -0x0: Regular (Single) mode -0x1: Dual I/O mode -0x2: Quad I/O mode -0x3: Reserved - 22 - 2 - read-write - - - TOKENEN - Token transfer enable (Master mode only) -Append a one-byte special token following the address phase for SPI read transfers. The value of the special token should be selected in TokenValue. -0x0: Disable the one-byte special token -0x1: Enable the one-byte special token - 21 - 1 - read-write - - - WRTRANCNT - Transfer count for write data -WrTranCnt indicates the number of units of data to be transmitted to the SPI bus from the Data Register. The actual transfer count is (WrTranCnt+1). -WrTranCnt only takes effect when TransMode is 0, 1, 3, 4, 5, 6 or 8. -The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. -For TransMode 0, WrTranCnt must be equal to RdTranCnt. - 12 - 9 - read-write - - - TOKENVALUE - Token value (Master mode only) -The value of the one-byte special token following the address phase for SPI read transfers. -0x0: token value = 0x00 -0x1: token value = 0x69 - 11 - 1 - read-write - - - DUMMYCNT - Dummy data count. The actual dummy count is (DummyCnt +1). -The number of dummy cycles on the SPI interface will be (DummyCnt+1)* ((DataLen+1)/SPI IO width) -The Data pins are put into the high impedance during the dummy data phase. -DummyCnt is only used for TransMode 5, 6, 8 and 9, which has dummy data phases. - 9 - 2 - read-write - - - RDTRANCNT - Transfer count for read data -RdTranCnt indicates the number of units of data to be received from SPI bus and stored to the Data Register. The actual received count is (RdTranCnt+1). -RdTransCnt only takes effect when TransMode is 0, 2, 3, 4, 5, 6 or 9. -The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. -For TransMode 0, WrTranCnt must equal RdTranCnt. - 0 - 9 - read-write - - - - - Cmd - Command Register - 0x24 - 32 - 0x00000000 - 0x000000FF - - - CMD - SPI Command - 0 - 8 - read-write - - - - - Addr - Address Register - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR - SPI Address -(Master mode only) - 0 - 32 - read-write - - - - - Data - Data Register - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - Data to transmit or the received data -For writes, data is enqueued to the TX FIFO. The least significant byte is always transmitted first. If the TX FIFO is full and the SPIActive bit of the status register is 1, the ready signal hready/pready will be deasserted to insert wait states to the transfer. -For reads, data is read and dequeued from the RX FIFO. The least significant byte is the first received byte. If the RX FIFO is empty and the SPIActive bit of the status register is 1, the ready signal hready/pready will be deasserted to insert wait states to the transfer. -The FIFOs decouple the speed of the SPI transfers and the software鈥檚 generation/consumption of data. When the TX FIFO is empty, SPI transfers will hold until more data is written to the TX FIFO; when the RX FIFO is full, SPI transfers will hold until there is more room in the RX FIFO. -If more data is written to the TX FIFO than the write transfer count (WrTranCnt), the remaining data will stay in the TX FIFO for the next transfer or until the TX FIFO is reset. - 0 - 32 - read-write - - - - - Ctrl - Control Register - 0x30 - 32 - 0x00000000 - 0x00FFFF1F - - - TXTHRES - Transmit (TX) FIFO Threshold -The TXFIFOInt interrupt or DMA request would be issued to replenish the TX FIFO when the TX data count is less than or equal to the TX FIFO threshold. - 16 - 8 - read-write - - - RXTHRES - Receive (RX) FIFO Threshold -The RXFIFOInt interrupt or DMA request would be issued for consuming the RX FIFO when the RX data count is more than or equal to the RX FIFO threshold. - 8 - 8 - read-write - - - TXDMAEN - TX DMA enable - 4 - 1 - read-write - - - RXDMAEN - RX DMA enable - 3 - 1 - read-write - - - TXFIFORST - Transmit FIFO reset -Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. - 2 - 1 - read-write - - - RXFIFORST - Receive FIFO reset -Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. - 1 - 1 - read-write - - - SPIRST - SPI reset -Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. - 0 - 1 - read-write - - - - - Status - Status Register - 0x34 - 32 - 0x00000000 - 0x33FFFF01 - - - TXNUM_7_6 - Number of valid entries in the Transmit FIFO - 28 - 2 - read-only - - - RXNUM_7_6 - Number of valid entries in the Receive FIFO - 24 - 2 - read-only - - - TXFULL - Transmit FIFO Full flag - 23 - 1 - read-only - - - TXEMPTY - Transmit FIFO Empty flag - 22 - 1 - read-only - - - TXNUM_5_0 - Number of valid entries in the Transmit FIFO - 16 - 6 - read-only - - - RXFULL - Receive FIFO Full flag - 15 - 1 - read-only - - - RXEMPTY - Receive FIFO Empty flag - 14 - 1 - read-only - - - RXNUM_5_0 - Number of valid entries in the Receive FIFO - 8 - 6 - read-only - - - SPIACTIVE - SPI register programming is in progress. -In master mode, SPIActive becomes 1 after the SPI command register is written and becomes 0 after the transfer is finished. -In slave mode, SPIActive becomes 1 after the SPI CS signal is asserted and becomes 0 after the SPI CS signal is deasserted. -Note that due to clock synchronization, it may take at most two spi_clock cycles for SPIActive to change when the corresponding condition happens. -Note this bit stays 0 when Direct IO Control or the memory-mapped interface is used. - 0 - 1 - read-only - - - - - IntrEn - Interrupt Enable Register - 0x38 - 32 - 0x00000000 - 0x0000003F - - - SLVCMDEN - Enable the Slave Command Interrupt. -Control whether interrupts are triggered whenever slave commands are received. -(Slave mode only) - 5 - 1 - read-write - - - ENDINTEN - Enable the End of SPI Transfer interrupt. -Control whether interrupts are triggered when SPI transfers end. -(In slave mode, end of read status transaction doesn鈥檛 trigger this interrupt.) - 4 - 1 - read-write - - - TXFIFOINTEN - Enable the SPI Transmit FIFO Threshold interrupt. -Control whether interrupts are triggered when the valid entries are less than or equal to the TX FIFO threshold. - 3 - 1 - read-write - - - RXFIFOINTEN - Enable the SPI Receive FIFO Threshold interrupt. -Control whether interrupts are triggered when the valid entries are greater than or equal to the RX FIFO threshold. - 2 - 1 - read-write - - - TXFIFOURINTEN - Enable the SPI Transmit FIFO Underrun interrupt. -Control whether interrupts are triggered when the Transmit FIFO run out of data. -(Slave mode only) - 1 - 1 - read-write - - - RXFIFOORINTEN - Enable the SPI Receive FIFO Overrun interrupt. -Control whether interrupts are triggered when the Receive FIFO overflows. -(Slave mode only) - 0 - 1 - read-write - - - - - IntrSt - Interrupt Status Register - 0x3c - 32 - 0x00000000 - 0x0000003F - - - SLVCMDINT - Slave Command Interrupt. -This bit is set when Slave Command interrupts occur. -(Slave mode only) - 5 - 1 - write-only - - - ENDINT - End of SPI Transfer interrupt. -This bit is set when End of SPI Transfer interrupts occur. - 4 - 1 - write-only - - - TXFIFOINT - TX FIFO Threshold interrupt. -This bit is set when TX FIFO Threshold interrupts occur. - 3 - 1 - write-only - - - RXFIFOINT - RX FIFO Threshold interrupt. -This bit is set when RX FIFO Threshold interrupts occur. - 2 - 1 - write-only - - - TXFIFOURINT - TX FIFO Underrun interrupt. -This bit is set when TX FIFO Underrun interrupts occur. -(Slave mode only) - 1 - 1 - write-only - - - RXFIFOORINT - RX FIFO Overrun interrupt. -This bit is set when RX FIFO Overrun interrupts occur. -(Slave mode only) - 0 - 1 - write-only - - - - - Timing - Interface Timing Register - 0x40 - 32 - 0x00000000 - 0x00003FFF - - - CS2SCLK - The minimum time between the edges of SPI CS and the edges of SCLK. -SCLK_period * (CS2SCLK + 1) / 2 - 12 - 2 - read-write - - - CSHT - The minimum time that SPI CS should stay HIGH. -SCLK_period * (CSHT + 1) / 2 - 8 - 4 - read-write - - - SCLK_DIV - The clock frequency ratio between the clock source and SPI interface SCLK. -SCLK_period = ((SCLK_DIV + 1) * 2) * (Period of the SPI clock source) -The SCLK_DIV value 0xff is a special value which indicates that the SCLK frequency should be the same as the spi_clock frequency. - 0 - 8 - read-write - - - - - SlvSt - Slave Status Register - 0x60 - 32 - 0x00000000 - 0x0007FFFF - - - UNDERRUN - Data underrun occurs in the last transaction - 18 - 1 - write-only - - - OVERRUN - Data overrun occurs in the last transaction - 17 - 1 - read-write - - - READY - Set this bit to indicate that the ATCSPI200 is ready for data transaction. -When an SPI transaction other than slave status-reading command ends, this bit will be cleared to 0. - 16 - 1 - read-write - - - USR_STATUS - User defined status flags - 0 - 16 - read-write - - - - - SlvDataCnt - Slave Data Count Register - 0x64 - 32 - 0x00000000 - 0x03FF03FF - - - WCNT - Slave transmitted data count - 16 - 10 - read-only - - - RCNT - Slave received data count - 0 - 10 - read-only - - - - - Config - Configuration Register - 0x7c - 32 - 0x00004311 - 0x000043FF - - - SLAVE - Support for SPI Slave mode - 14 - 1 - read-only - - - QUADSPI - Support for Quad I/O SPI - 9 - 1 - read-only - - - DUALSPI - Support for Dual I/O SPI - 8 - 1 - read-only - - - TXFIFOSIZE - Depth of TX FIFO -0x0: 2 words -0x1: 4 words -0x2: 8 words -0x3: 16 words -0x4: 32 words -0x5: 64 words -0x6: 128 words - 4 - 4 - read-only - - - RXFIFOSIZE - Depth of RX FIFO -0x0: 2 words -0x1: 4 words -0x2: 8 words -0x3: 16 words -0x4: 32 words -0x5: 64 words -0x6: 128 words - 0 - 4 - read-only - - - - - - - SPI1 - SPI1 - SPI - 0xf0034000 - - - SPI2 - SPI2 - SPI - 0xf0038000 - - - SPI3 - SPI3 - SPI - 0xf003c000 - - - UART0 - UART0 - UART - 0xf0040000 - - 0x10 - 0x30 - registers - - - - Cfg - Configuration Register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - FIFOSIZE - The depth of RXFIFO and TXFIFO -0: 16-byte FIFO -1: 32-byte FIFO -2: 64-byte FIFO -3: 128-byte FIFO - 0 - 2 - read-only - - - - - OSCR - Over Sample Control Register - 0x14 - 32 - 0x00000010 - 0x0000001F - - - OSC - Over-sample control -The value must be an even number; any odd value -writes to this field will be converted to an even value. -OSC=0: reserved -OSC<=8: The over-sample ratio is 8 -8 < OSC< 32: The over sample ratio is OSC - 0 - 5 - read-write - - - - - RBR - Receiver Buffer Register (when DLAB = 0) - UNION_20 - 0x20 - 32 - 0x00000000 - 0x000000FF - - - RBR - Receive data read port - 0 - 8 - read-only - - - - - THR - Transmitter Holding Register (when DLAB = 0) - UNION_20 - 0x20 - 32 - 0x00000000 - 0x000000FF - - - THR - Transmit data write port - 0 - 8 - write-only - - - - - DLL - Divisor Latch LSB (when DLAB = 1) - UNION_20 - 0x20 - 32 - 0x00000001 - 0x000000FF - - - DLL - Least significant byte of the Divisor Latch - 0 - 8 - read-write - - - - - IER - Interrupt Enable Register (when DLAB = 0) - UNION_24 - 0x24 - 32 - 0x00000000 - 0x0000000F - - - EMSI - Enable modem status interrupt -The interrupt asserts when the status of one of the -following occurs: -The status of modem_rin, modem_dcdn, -modem_dsrn or modem_ctsn (If the auto-cts mode is -disabled) has been changed. -If the auto-cts mode is enabled (MCR bit4 (AFE) = 1), -modem_ctsn would be used to control the transmitter. - 3 - 1 - read-write - - - ELSI - Enable receiver line status interrupt - 2 - 1 - read-write - - - ETHEI - Enable transmitter holding register interrupt - 1 - 1 - read-write - - - ERBI - Enable received data available interrupt and the -character timeout interrupt -0: Disable -1: Enable - 0 - 1 - read-write - - - - - DLM - Divisor Latch MSB (when DLAB = 1) - UNION_24 - 0x24 - 32 - 0x00000000 - 0x000000FF - - - DLM - Most significant byte of the Divisor Latch - 0 - 8 - read-write - - - - - IIR - Interrupt Identification Register - UNION_28 - 0x28 - 32 - 0x00000001 - 0x000000CF - - - FIFOED - FIFOs enabled -These two bits are 1 when bit 0 of the FIFO Control -Register (FIFOE) is set to 1. - 6 - 2 - read-only - - - INTRID - Interrupt ID, see IIR2 for detail decoding - 0 - 4 - read-only - - - - - FCR - FIFO Control Register - UNION_28 - 0x28 - 32 - 0x00000000 - 0x000000FF - - - RFIFOT - Receiver FIFO trigger level - 6 - 2 - write-only - - - TFIFOT - Transmitter FIFO trigger level - 4 - 2 - write-only - - - DMAE - DMA enable -0: Disable -1: Enable - 3 - 1 - write-only - - - TFIFORST - Transmitter FIFO reset -Write 1 to clear all bytes in the TXFIFO and resets its -counter. The Transmitter Shift Register is not cleared. -This bit will automatically be cleared. - 2 - 1 - write-only - - - RFIFORST - Receiver FIFO reset -Write 1 to clear all bytes in the RXFIFO and resets its -counter. The Receiver Shift Register is not cleared. -This bit will automatically be cleared. - 1 - 1 - write-only - - - FIFOE - FIFO enable -Write 1 to enable both the transmitter and receiver -FIFOs. -The FIFOs are reset when the value of this bit toggles. - 0 - 1 - write-only - - - - - LCR - Line Control Register - 0x2c - 32 - 0x00000000 - 0x000000FF - - - DLAB - Divisor latch access bit - 7 - 1 - read-write - - - BC - Break control - 6 - 1 - read-write - - - SPS - Stick parity -1: Parity bit is constant 0 or 1, depending on bit4 (EPS). -0: Disable the sticky bit parity. - 5 - 1 - read-write - - - EPS - Even parity select -1: Even parity (an even number of logic-1 is in the data -and parity bits) -0: Old parity. - 4 - 1 - read-write - - - PEN - Parity enable -When this bit is set, a parity bit is generated in -transmitted data before the first STOP bit and the parity -bit would be checked for the received data. - 3 - 1 - read-write - - - STB - Number of STOP bits -0: 1 bits -1: The number of STOP bit is based on the WLS setting -When WLS = 0, STOP bit is 1.5 bits -When WLS = 1, 2, 3, STOP bit is 2 bits - 2 - 1 - read-write - - - WLS - Word length setting -0: 5 bits -1: 6 bits -2: 7 bits -3: 8 bits - 0 - 2 - read-write - - - - - MCR - Modem Control Register ( - 0x30 - 32 - 0x00000000 - 0x00000032 - - - AFE - Auto flow control enable -0: Disable -1: The auto-CTS and auto-RTS setting is based on the -RTS bit setting: -When RTS = 0, auto-CTS only -When RTS = 1, auto-CTS and auto-RTS - 5 - 1 - read-write - - - LOOP - Enable loopback mode -0: Disable -1: Enable - 4 - 1 - read-write - - - RTS - Request to send -This bit controls the modem_rtsn output. -0: The modem_rtsn output signal will be driven HIGH -1: The modem_rtsn output signal will be driven LOW - 1 - 1 - read-write - - - - - LSR - Line Status Register - 0x34 - 32 - 0x00000000 - 0x000000FF - - - ERRF - Error in RXFIFO -In the FIFO mode, this bit is set when there is at least -one parity error, framing error, or line break -associated with data in the RXFIFO. It is cleared when -this register is read and there is no more error for the -rest of data in the RXFIFO. - 7 - 1 - read-only - - - TEMT - Transmitter empty -This bit is 1 when the THR (TXFIFO in the FIFO -mode) and the Transmitter Shift Register (TSR) are -both empty. Otherwise, it is zero. - 6 - 1 - read-only - - - THRE - Transmitter Holding Register empty -This bit is 1 when the THR (TXFIFO in the FIFO -mode) is empty. Otherwise, it is zero. -If the THRE interrupt is enabled, an interrupt is -triggered when THRE becomes 1. - 5 - 1 - read-only - - - LBREAK - Line break -This bit is set when the uart_sin input signal was held -LOWfor longer than the time for a full-word -transmission. A full-word transmission is the -transmission of the START, data, parity, and STOP -bits. It is cleared when this register is read. -In the FIFO mode, this bit indicates the line break for -the received data at the top of the RXFIFO. - 4 - 1 - read-only - - - FE - Framing error -This bit is set when the received STOP bit is not -HIGH. It is cleared when this register is read. -In the FIFO mode, this bit indicates the framing error -for the received data at the top of the RXFIFO. - 3 - 1 - read-only - - - PE - Parity error -This bit is set when the received parity does not match -with the parity selected in the LCR[5:4]. It is cleared -when this register is read. -In the FIFO mode, this bit indicates the parity error -for the received data at the top of the RXFIFO. - 2 - 1 - read-only - - - OE - Overrun error -This bit indicates that data in the Receiver Buffer -Register (RBR) is overrun. - 1 - 1 - read-only - - - DR - Data ready. -This bit is set when there are incoming received data -in the Receiver Buffer Register (RBR). It is cleared -when all of the received data are read. - 0 - 1 - read-only - - - - - MSR - Modem Status Register - 0x38 - 32 - 0x00000000 - 0x00000011 - - - CTS - Clear to send -0: The modem_ctsn input signal is HIGH. -1: The modem_ctsn input signal is LOW. - 4 - 1 - read-only - - - DCTS - Delta clear to send -This bit is set when the state of the modem_ctsn input -signal has been changed since the last time this -register is read. - 0 - 1 - read-only - - - - - GPR - GPR Register - 0x3c - 32 - 0x00000000 - 0x000000FF - - - DATA - A one-byte storage register - 0 - 8 - read-write - - - - - - - UART1 - UART1 - UART - 0xf0044000 - - - UART2 - UART2 - UART - 0xf0048000 - - - UART3 - UART3 - UART - 0xf004c000 - - - UART4 - UART4 - UART - 0xf0050000 - - - UART5 - UART5 - UART - 0xf0054000 - - - UART6 - UART6 - UART - 0xf0058000 - - - UART7 - UART7 - UART - 0xf005c000 - - - UART8 - UART8 - UART - 0xf0060000 - - - UART9 - UART9 - UART - 0xf0064000 - - - UART10 - UART10 - UART - 0xf0068000 - - - UART11 - UART11 - UART - 0xf006c000 - - - UART12 - UART12 - UART - 0xf0070000 - - - UART13 - UART13 - UART - 0xf0074000 - - - UART14 - UART14 - UART - 0xf0078000 - - - UART15 - UART15 - UART - 0xf007c000 - - - PUART - PUART - UART - 0xf40e4000 - - - CAN0 - CAN0 - CAN - 0xf0080000 - - 0x0 - 0xca - registers - - - - 20 - 0x4 - buf0,buf1,buf2,buf3,buf4,buf5,buf6,buf7,buf8,buf9,buf10,buf11,buf12,buf13,buf14,buf15,buf16,buf17,buf18,buf19 - RBUF[%s] - no description available - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - RBUF - receive buffer - 0 - 32 - read-write - - - - - 18 - 0x4 - buf0,buf1,buf2,buf3,buf4,buf5,buf6,buf7,buf8,buf9,buf10,buf11,buf12,buf13,buf14,buf15,buf16,buf17 - TBUF[%s] - no description available - 0x50 - 32 - 0x00000000 - 0xFFFFFFFF - - - TBUF - transmit buffer - 0 - 32 - read-write - - - - - 2 - 0x4 - wrd0,wrd1 - TTS[%s] - no description available - 0x98 - 32 - 0x00000000 - 0xFFFFFFFF - - - TTS_WRD0 - transmission time stamp, word 0, LSB 32bit - 0 - 32 - read-only - - - - - CMD_STA_CMD_CTRL - config, status, command and control bits - 0xa0 - 32 - 0x00900080 - 0xFBF3FFFF - - - SACK - Self-ACKnowledge -0 – no self-ACK -1 – self-ACK when LBME=1 - 31 - 1 - read-write - - - ROM - Receive buffer Overflow Mode -In case of a full RBUF when a new message is received, then ROM selects the following: -1 – The new message will not be stored. -0 – The oldest message will be overwritten. - 30 - 1 - read-write - - - ROV - Receive buffer OVerflow -1 – Overflow. At least one message is lost. -0 – No Overflow. -ROV is cleared by setting RREL=1. - 29 - 1 - read-only - - - RREL - Receive buffer RELease -The host controller has read the actual RB slot and releases it. Afterwards the CAN-CTRL -core points to the next RB slot. RSTAT gets updated. -1 – Release: The host has read the RB. -0 – No release - 28 - 1 - read-write - - - RBALL - Receive Buffer stores ALL data frames -0 – normal operation -1 – RB stores correct data frames as well as data frames with error - 27 - 1 - read-write - - - RSTAT - Receive buffer STATus -00 - empty -01 - > empty and < almost full (AFWL) -10 -  almost full (programmable threshold by AFWL) but not full and no overflow -11 - full (stays set in case of overflow – for overflow signaling see ROV) - 24 - 2 - read-only - - - FD_ISO - CAN FD ISO mode -0 - Bosch CAN FD (non-ISO) mode -1 - ISO CAN FD mode (ISO 11898-1:2015) -ISO CAN FD mode has a different CRC initialization value and an additional stuff bit count. -Both modes are incompatible and must not be mixed in one CAN network. -This bit has no impact to CAN 2.0B. -This bit is only writeable if RESET=1. - 23 - 1 - read-write - - - TSNEXT - Transmit buffer Secondary NEXT -0 - no action -1 - STB slot filled, select next slot. -After all frame bytes are written to the TBUF registers, the host controller has to set -TSNEXT to signal that this slot has been filled. Then the CAN-CTRL core connects the TBUF -registers to the next slot. Once a slot is marked as filled a transmission can be started -using TSONE or TSALL. -It is possible to set TSNEXT and TSONE or TSALL together in one write access. -TSNEXT has to be set by the host controller and is automatically reset by the CAN-CTRL -core immediately after it was set. -Setting TSNEXT is meaningless if TBSEL=0. In this case TSNEXT is ignored and -automatically cleared. It does not do any harm. -If all slots of the STB are filled, TSNEXT stays set until a slot becomes free. -TSNEXT has no meaning in TTCAN mode and is fixed to 0. - 22 - 1 - read-write - - - TSMODE - Transmit buffer Secondary operation MODE -0 - FIFO mode -1 - priority decision mode -In FIFO mode frames are transmitted in the order in that they are written into the STB. -In priority decision mode the frame with the highest priority in the STB is automatically -transmitted first. The ID of a frame is used for the priority decision. A lower ID means a -higher priority of a frame. A frame in the PTB has always the highest priority regardless of -the ID. -TSMODE shall be switched only if the STB if empty - 21 - 1 - read-write - - - TTTBM - TTCAN Transmit Buffer Mode -If TTEN=0 then TTTBM is ignored, otherwise the following is valid: -0 - separate PTB and STB, behavior defined by TSMODE -1 - full TTCAN support: buffer slots selectable by TBPTR and TTPTR -For event-driven CAN communication (TTEN=0), the system provides PTB and STB and -the behavior of the STB is defined by TSMODE. Then TTTBM is ignored. -For time-triggered CAN communication (TTEN=1) with full support of all features including -time-triggered transmissions, TTTBM=1 needs to be chosen. Then the all TB slots are -addressable using TTPTR and TBPTR. -For time-triggered CAN communication (TTEN=1) with only support of reception timestamps, TTTBM=0 can be chosen. Then the transmit buffer acts as in event-driven mode -and the behavior can be selected by TSMODE. -TTTBM shall be switched only if the TBUF is empty. - 20 - 1 - read-write - - - TSSTAT - Transmission Secondary STATus bits -If TTEN=0 or TTTBM=0: -00 – STB is empty -01 – STB is less than or equal to half full -10 – STB is more than half full -11 – STB is full -If the STB is disabled using STB_DISABLE, then TSSTAT=00. -If TTEN=1 and TTTBM=1: -00 – PTB and STB are empty -01 – PTB and STB are not empty and not full -11 – PTB and STB are full - 16 - 2 - read-only - - - TBSEL - Transmit Buffer Select -Selects the transmit buffer to be loaded with a message. Use the TBUF registers for -access. TBSEL needs to be stable all the time the TBUF registers are written and when -TSNEXT is set. -0 - PTB (high-priority buffer) -1 - STB -The bit will be reset to the hardware reset value if (TTEN=1 and TTTBM=1) - 15 - 1 - read-write - - - LOM - Listen Only Mode -0 - Disabled -1 - Enabled -LOM cannot be set if TPE, TSONE or TSALL is set. No transmission can be started if LOM -is enabled and LBME is disabled. -LOM=1 and LBME=0 disables all transmissions. -LOM=1 and LBME=1 disables the ACK for received frames and error frames, but enables -the transmission of own frames. - 14 - 1 - read-write - - - STBY - Transceiver Standby Mode -0 - Disabled -1 - Enabled -This register bit is connected to the output signal stby which can be used to control a -standby mode of a transceiver. -STBY cannot be set to 1 if TPE=1, TSONE=1 or TSALL=1. -If the host sets STBY to 0 then the host needs to wait for the time required by the -transceiver to start up before the host requests a new transmission. - 13 - 1 - read-write - - - TPE - Transmit Primary Enable -1 - Transmission enable for the message in the high-priority PTB -0 - No transmission for the PTB -If TPE is set, the message from the PTB will be transmitted at the next possible transmit -position. A started transmission from the STB will be completed before, but pending new -messages are delayed until the PTB message has been transmitted. -TPE stays set until the message has been transmitted successfully or it is aborted using -TPA. -The host controller can set TPE to 1 but can not reset it to 0. This would only be possible -using TPA and aborting the message. -The bit will be reset to the hardware reset value if RESET=1, STBY=1, (LOM=1 and -LBME=0) or (TTEN=1 and TTTBM=1). - 12 - 1 - read-write - - - TPA - Transmit Primary Abort -1 – Aborts a transmission from PTB which has been requested by TPE=1 but not -started yet. (The data bytes of the message remains in the PTB.) -0 – no abort -The bit has to be set by the host controller and will be reset by CAN-CTRL. Setting TPA -automatically de-asserts TPE. -The host controller can set TPA to 1 but can not reset it to 0. -During the short time while the CAN-CTRL core resets the bit, it cannot be set by the -host. -The bit will be reset to the hardware reset value if RESET=1 or (TTEN=1 and TTTBM=1). -TPA should not be set simultaneously with TPE. - 11 - 1 - read-write - - - TSONE - Transmit Secondary ONE frame -1 – Transmission enable of one in the STB. In FIFO mode this is the oldest message -and in priority mode this is the one with the highest priority. -TSONE in priority mode is difficult to handle, because it is not always clear which -message will be transmitted if new messages are written to the STB meanwhile. -The controller starts the transmission as soon as the bus becomes vacant and -no request of the PTB (bit TPE) is pending. -0 – No transmission for the STB. -TSONE stays set until the message has been transmitted successfully or it is aborted -using TSA. -The host controller can set TSONE to 1 but can not reset it to 0. This would only be -possible using TSA and aborting the message. -The bit will be reset to the hardware reset value if RESET=1, STBY=1, (LOM=1 and -LBME=0) or (TTEN=1 and TTTBM=1). - 10 - 1 - read-write - - - TSALL - Transmit Secondary ALL frames -1 – Transmission enable of all messages in the STB. -The controller starts the transmission as soon as the bus becomes vacant and -no request of the PTB (bit TPE) is pending. -0 – No transmission for the STB. -TSALL stays set until all messages have been transmitted successfully or they are aborted -using TSA. -The host controller can set TSALL to 1 but can not reset it to 0. This would only be -possible using TSA and aborting the messages. -The bit will be reset to the hardware reset value if RESET=1, STBY=1, (LOM=1 and -LBME=0) or (TTEN=1 and TTTBM=1). -If during a transmission the STB is loaded with a new frame then the new frame will be -transmitted too. In other words: a transmission initiated by TSALL is finished when the -STB becomes empty. - 9 - 1 - read-write - - - TSA - Transmit Secondary Abort -1 – Aborts a transmission from STB which has been requested but not started yet. -For a TSONE transmission, only one frame is aborted while for a TSALL -Transmission, all frames are aborted. -One or all message slots will be released which updates TSSTAT. -All aborted messages are lost because they are not accessible any more. -If in priority mode a TSONE transmission is aborted, then it is not clear which -frame will be aborted if new frames are written to the STB meanwhile. -0 – no abort -The bit has to be set by the host controller and will be reset by CAN-CTRL. Setting TSA,automatically de-asserts TSONE or TSALL respectively. -The host controller can set TSA to 1 but can not reset it to 0. -The bit will be reset to the hardware reset value if RESET=1. -TSA should not be set simultaneously with TSONE or TSALL. - 8 - 1 - read-write - - - RESET - RESET request bit -1 - The host controller performs a local reset of CAN-CTRL. -0 - no local reset of CAN-CTRLThe some register (e.g for node configuration) can only be modified if RESET=1. -Bit RESET forces several components to a reset state. -RESET is automatically set if the node enters “bus off” state. -Note that a CAN node will participate in CAN communication after RESET is switched to 0after 11 CAN bit times. -This delay is required by the CAN standard (bus idle time).If RESET is set to 1 and immediately set to 0, then it takes some time until RESET can beread as 0 and becomes inactive. -The reason is clock domain crossing from host to CAN clockdomain. RESET is held active as long as needed depending on the relation between host andCAN clock. - 7 - 1 - read-write - - - LBME - Loop Back Mode, External -0 - Disabled -1 - EnabledLBME should not be enabled while a transmission is active - 6 - 1 - read-write - - - LBMI - Loop Back Mode, Internal -0 - Disabled1 - EnabledLBMI should not be enabled while a transmission is active. - 5 - 1 - read-write - - - TPSS - Transmission Primary Single Shot mode for PTB -0 - Disabled -1 - Enabled - 4 - 1 - read-write - - - TSSS - Transmission Secondary Single Shot mode for STB -0 - Disabled -1 - Enabled - 3 - 1 - read-write - - - RACTIVE - Reception ACTIVE (Receive Status bit) -1 - The controller is currently receiving a frame. -0 - No receive activity. - 2 - 1 - read-only - - - TACTIVE - Transmission ACTIVE (Transmit Status bit) -1 - The controller is currently transmitting a frame. -0 - No transmit activity. - 1 - 1 - read-only - - - BUSOFF - Bus Off (Bus Status bit) -1 - The controller status is “bus off”. -0 - The controller status is “bus on”. -Writing a 1 to BUSOFF will reset TECNT and RECNT. This should be done only for debugging. -See Chapter 3.9.10.6 for details. - 0 - 1 - read-write - - - - - RTIE - Receive and Transmit Interrupt Enable Register RTIE - 0xa4 - 8 - 0xFE - 0xFF - - - RIE - Receive Interrupt Enable -0 – Disabled, 1 – Enabled - 7 - 1 - read-write - - - ROIE - RB Overrun Interrupt Enable -0 – Disabled, 1 – Enabled - 6 - 1 - read-write - - - RFIE - RB Full Interrupt Enable -0 – Disabled, 1 – Enabled - 5 - 1 - read-write - - - RAFIE - RB Almost Full Interrupt Enable -0 – Disabled, 1 – Enabled - 4 - 1 - read-write - - - TPIE - Transmission Primary Interrupt Enable -0 – Disabled, 1 – Enabled - 3 - 1 - read-write - - - TSIE - Transmission Secondary Interrupt Enable -0 – Disabled, 1 – Enabled - 2 - 1 - read-write - - - EIE - Error Interrupt Enable -0 – Disabled, 1 – Enabled - 1 - 1 - read-write - - - TSFF - If TTEN=0 or TTTBM=0: Transmit Secondary buffer Full Flag -1 - The STB is filled with the maximal number of messages. -0 - The STB is not filled with the maximal number of messages. -If the STB is disabled using STB_DISABLE, then TSFF=0. -If TTEN=1 and TTTBM=1: Transmit buffer Slot Full Flag -1 - The buffer slot selected by TBPTR is filled. -0 - The buffer slot selected by TBPTR is empty. - 0 - 1 - read-only - - - - - RTIF - Receive and Transmit Interrupt Flag Register RTIF (0xa5) - 0xa5 - 8 - 0x00 - 0xFF - - - RIF - Receive Interrupt Flag -1 - Data or a remote frame has been received and is available in the receive buffer. -0 - No frame has been received. - 7 - 1 - write-only - - - ROIF - RB Overrun Interrupt Flag -1 - At least one received message has been overwritten in the RB. -0 - No RB overwritten. -In case of an overrun both ROIF and RFIF will be set. - 6 - 1 - write-only - - - RFIF - RB Full Interrupt Flag -1 - All RBs are full. If no RB will be released until the next valid message is received, -the oldest message will be lost. -0 - The RB FIFO is not full. - 5 - 1 - write-only - - - RAFIF - RB Almost Full Interrupt Flag -1 - number of filled RB slots >= AFWL_i -0 - number of filled RB slots < AFWL_i - 4 - 1 - write-only - - - TPIF - Transmission Primary Interrupt Flag -1 - The requested transmission of the PTB has been successfully completed. -0 - No transmission of the PTB has been completed. -In TTCAN mode, TPIF will never be set. Then only TSIF is valid. - 3 - 1 - write-only - - - TSIF - Transmission Secondary Interrupt Flag -1 - The requested transmission of the STB has been successfully completed. -0 - No transmission of the STB has been completed successfully. -In TTCAN mode TSIF will signal all successful transmissions, regardless of storage location of -the message. - 2 - 1 - write-only - - - EIF - Error Interrupt Flag -1 - The border of the error warning limit has been crossed in either direction, -or the BUSOFF bit has been changed in either direction. -0 - There has been no change. - 1 - 1 - write-only - - - AIF - Abort Interrupt Flag -1 - After setting TPA or TSA the appropriated message(s) have been aborted. -It is recommended to not set both TPA and TSA simultaneously because both -source AIF. -0 - No abort has been executed. -The AIF does not have an associated enable register. - 0 - 1 - write-only - - - - - ERRINT - ERRor INTerrupt Enable and Flag Register ERRINT - 0xa6 - 8 - 0x00 - 0xFF - - - EWARN - Error WARNing limit reached -1 - One of the error counters RECNT or TECNT is equal or bigger than EWL0 - The values in both counters are less than EWL. - 7 - 1 - read-only - - - EPASS - Error Passive mode active -0 - not active (node is error active) -1 - active (node is error passive) - 6 - 1 - read-only - - - EPIE - Error Passive Interrupt Enable - 5 - 1 - read-write - - - EPIF - Error Passive Interrupt Flag. EPIF will be activated if the error status changes from error -active to error passive or vice versa and if this interrupt is enabled. - 4 - 1 - write-only - - - ALIE - Arbitration Lost Interrupt Enable - 3 - 1 - read-write - - - ALIF - Arbitration Lost Interrupt Flag - 2 - 1 - write-only - - - BEIE - Bus Error Interrupt Enable - 1 - 1 - read-write - - - BEIF - Bus Error Interrupt Flag - 0 - 1 - write-only - - - - - LIMIT - Warning Limits Register LIMIT - 0xa7 - 8 - 0x1B - 0xFF - - - AFWL - receive buffer Almost Full Warning Limit -AFWL defines the internal warning limit AFWL_i with being the number of availableRB slots. -AFWL_i is compared to the number of filled RB slots and triggers RAFIF if equal. Thevalid range of . -AFWL = 0 is meaningless and automatically treated as 0x1. (Note that AFWL is meant in this rule and not AFWL_i.) -AFWL_i > nRB is meaningless and automatically treated as nRB. -AFWL_i = nRB is a valid value, but note that RFIF also exists. - 4 - 4 - read-write - - - EWL - Programmable Error Warning Limit = (EWL+1)*8. Possible Limit values: 8, 16, … 128. -The value of EWL controls EIF. - 0 - 4 - read-write - - - - - S_PRESC - Bit Timing Register(Slow Speed) - 0xa8 - 32 - 0x01020203 - 0xFF7F7FFF - - - S_PRESC - Prescaler (slow speed) -The prescaler divides the system clock to get the time quanta clock tq_clk.Valid range PRESC=[0x00, 0xff] results in divider values 1 to 256. - 24 - 8 - read-write - - - S_SJW - Synchronization Jump Width (slow speed) -The Synchronization Jump Width is the maximum time forshortening or lengthening the Bit Time for resynchronization, where TQ is a timequanta. - 16 - 7 - read-write - - - S_SEG_2 - Bit Timing Segment 2 (slow speed) -Time after the sample point. - 8 - 7 - read-write - - - S_SEG_1 - Bit Timing Segment 1 (slow speed) -The sample point will be set to after start of bit time. - 0 - 8 - read-write - - - - - F_PRESC - Bit Timing Register(Fast Speed) - 0xac - 32 - 0x01020203 - 0xFF0F0F0F - - - F_PRESC - Prescaler (fast speed) -The prescaler divides the system clock to get the time quanta clock tq_clk.Valid range PRESC=[0x00, 0xff] results in divider values 1 to 256. - 24 - 8 - read-write - - - F_SJW - Synchronization Jump Width (fast speed) -The Synchronization Jump Width is the maximum time forshortening or lengthening the Bit Time for resynchronization, where TQ is a timequanta. - 16 - 4 - read-write - - - F_SEG_2 - Bit Timing Segment 2 (fast speed) -Time after the sample point - 8 - 4 - read-write - - - F_SEG_1 - Bit Timing Segment 1 (fast speed) -The sample point will be set to after start of bit time. - 0 - 4 - read-write - - - - - EALCAP - Error and Arbitration Lost Capture Register EALCAP - 0xb0 - 8 - 0x00 - 0xFF - - - KOER - Kind Of ERror (Error code) -000 - no error -001 - BIT ERROR -010 - FORM ERROR -011 - STUFF ERROR -100 - ACKNOWLEDGEMENT ERROR -101 - CRC ERROR -110 - OTHER ERROR(dominant bits after own error flag, received active Error Flag too long,dominant bit during Passive-Error-Flag after ACK error) -111 - not used -KOER is updated with each new error. Therefore it stays untouched when frames aresuccessfully transmitted or received. - 5 - 3 - read-only - - - ALC - Arbitration Lost Capture (bit position in the frame where the arbitration has been lost) - 0 - 5 - read-only - - - - - TDC - Transmitter Delay Compensation Register TDC - 0xb1 - 8 - 0x00 - 0xFF - - - TDCEN - Transmitter Delay Compensation ENable -TDC will be activated during the data phase of a CAN FD frame if BRS is active if TDCEN=1. - 7 - 1 - read-write - - - SSPOFF - Secondary Sample Point OFFset -The transmitter delay plus SSPOFF defines the time of the secondary sample point for TDC. -SSPOFF is given as a number of TQ. - 0 - 7 - read-write - - - - - RECNT - Error Counter Registers RECNT - 0xb2 - 8 - 0x00 - 0xFF - - - RECNT - Receive Error CouNT (number of errors during reception) -RECNT is incremented and decremented as defined in the CAN specification. -RECNT does not overflow. -If TXB=1, then the error counters are frozen. - 0 - 8 - read-only - - - - - TECNT - Error Counter Registers TECNT - 0xb3 - 8 - 0x00 - 0xFF - - - TECNT - Transmit Error CouNT (number of errors during transmission) -TECNT is incremented and decremented as defined in the CAN specification. -In case of the “bus off state” TECNT may overflow. -If TXB=1, then the error counters are frozen. - 0 - 8 - read-only - - - - - ACFCTRL - Acceptance Filter Control Register ACFCTRL - 0xb4 - 8 - 0x00 - 0x2F - - - SELMASK - SELect acceptance MASK -0 - Registers ACF_x point to acceptance code -1 - Registers ACF_x point to acceptance mask. -ACFADR selects one specific acceptance filter. - 5 - 1 - read-write - - - ACFADR - acceptance filter address -ACFADR points to a specific acceptance filter. -The selected filter is accessible using theregisters ACF_x. -Bit SELMASK selects between acceptance code and mask for theselected acceptance filter. -A value of ACFADR>ACF_NUMBER-1 is meaningless and automatically treated as value ACF_NUMBER-1. -ACF_NUMBER = 16. - 0 - 4 - read-write - - - - - TIMECFG - CiA 603 Time-Stamping TIMECFG - 0xb5 - 8 - 0x00 - 0x03 - - - TIMEPOS - TIME-stamping POSition -0 – SOF1 – EOF (see Chapter 7)TIMEPOS can only be changed if TIMEEN=0, but it is possible to modify TIMPOS withthe same write access that sets TIMEEN=1. - 1 - 1 - read-write - - - TIMEEN - TIME-stamping ENable -0 – disabled -1 – enabled - 0 - 1 - read-write - - - - - ACF_EN - Acceptance Filter Enable ACF_EN - 0xb6 - 16 - 0x0000 - 0xFFFF - - - ACF_EN - Acceptance filter Enable -1 - acceptance filter enabled -0 - acceptance filter disable -Each acceptance filter (AMASK / ACODE) can be individually enabled or disabled. -Disabled filters reject a message. Only enabled filters can accept a message if the -appropriate AMASK / ACODE configuration matches. - 0 - 16 - read-write - - - - - ACF - Acceptance CODE ACODE or ACMASK - 0xb8 - 32 - 0x00000000 - 0x7FFFFFFF - - - AIDEE - Acceptance mask IDE bit check enable -1 - acceptance filter accepts either standard or extended as defined by AIDE -0 - acceptance filter accepts both standard or extended frames -Only filter 0 is affected by the power-on reset. All other filters stay uninitialized. - 30 - 1 - read-write - - - AIDE - Acceptance mask IDE bit value -If AIDEE=1 then: -1 - acceptance filter accepts only extended frames -0 - acceptance filter accepts only standard frames -Only filter 0 is affected by the power-on reset. All other filters stay uninitialized. - 29 - 1 - read-write - - - CODE_MASK - Acceptance CODE -1 - ACC bit value to compare with ID bit of the received message -0 - ACC bit value to compare with ID bit of the received message -ACODE_x(10:0) will be used for extended frames. -ACODE_x(28:0) will be used for extended frames. -Only filter 0 is affected by the power-on reset. -Acceptance MASK(if SELMASK ==1 ) -1 - acceptance check for these bits of receive identifier disabled -0 - acceptance check for these bits of receive identifier enable -AMASK_x(10:0) will be used for extended frames. -AMASK_x(28:0) will be used for extended frames. -Disabled bits result in accepting the message. Therefore the default configuration after -reset for filter 0 accepts all messages. -Only filter 0 is affected by the power-on reset. - 0 - 29 - read-write - - - - - VER - Version Information VER - 0xbc - 16 - 0x0000 - 0xFFFF - - - VERSION - Version of CAN-CTRL, given as decimal value. VER_1 holds the major version and -VER_0 the minor version.Example: version 5x16N00S00 is represented by VER_1=5 and VER_0=16 - 0 - 16 - read-write - - - - - TBSLOT - TTCAN: TB Slot Pointer TBSLOT - 0xbe - 8 - 0x00 - 0xFF - - - TBE - set TB slot to “Empty” -1 - slot selected by TBPTR shall be marked as “empty” -0 - no actionTBE is automatically reset to 0 as soon as the slot is marked as empty and TSFF=0. -If atransmission from this slot is active, then TBE stays set as long as either the transmission completes or after a transmission error or arbitration loss the - transmissionis not active any more. -If both TBF and TBE are set, then TBE wins - 7 - 1 - read-write - - - TBF - set TB slot to “Filled” -1 - slot selected by TBPTR shall be marked as “filled” -0 - no actionTBF is automatically reset to 0 as soon as the slot is marked as filled and TSFF=1. -If both TBF and TBE are set, then TBE wins. - 6 - 1 - read-write - - - TBPTR - Pointer to a TB message slot. -0x00 - Pointer to the PTB -others - Pointer to a slot in the STB -The message slot pointed to by TBPTR is readable / writable using the TBUF registers. -Write access is only possible if TSFF=0. -Setting TBF to 1 marks the selected slot asfilled and setting TBE to 1 marks the selected slot as empty. -TBSEL and TSNEXT are unused in TTCAN mode and have no meaning. -TBPTR can only point to buffer slots, that exist in the hardware. -Unusable bits ofTBPTR are fixed to 0. -TBPTR is limited to the PTB and 63 STB slots. - More slots cannot be used in TTCANmode.If TBPTR is too big and points to a slot that is not available, then TBF and TBE arereset automatically and no action takes place. - 0 - 6 - read-write - - - - - TTCFG - TTCAN: Time Trigger Configuration TTCFG - 0xbf - 8 - 0x00 - 0xFF - - - WTIE - Watch Trigger Interrupt Enable - 7 - 1 - read-write - - - WTIF - Watch Trigger Interrupt Flag -WTIF will be set if the cycle count reaches the limited defined by TT_WTRIG and WTIE is set. - 6 - 1 - read-write - - - TEIF - Trigger Error Interrupt Flag -The conditions when TEIF will be set, are defined in Chapter 6.4. There is no bit toenable or disable the handling of TEIF - 5 - 1 - read-write - - - TTIE - Time Trigger Interrupt Enable -If TTIE is set, then TTIF will be set if the cycle time is equal to the trigger timeTT_TRIG. - 4 - 1 - read-write - - - TTIF - Time Trigger Interrupt Flag -TTIF will be set if TTIE is set and the cycle time is equal to the trigger time TT_TRIG. -Writing a one to TTIF resets it. Writing a zero has no impact.TTIF will be set only once. -If TT_TRIG gets not updated, then TTIF will be not setagain in the next basic cycle. - 3 - 1 - read-write - - - T_PRESC - TTCAN Timer PRESCaler -00b - 1 -01b - 2 -10b - 4 -11b - 8 -The TTCAN time base is a CAN bittime defined by S_PRES, S_SEG_1 and S_SEG_2.With T_PRESC an additional prescaling factor of 1, 2, 4 or 8 is defined. -T_PRESC can only be modified if TTEN=0, but it is possible to modify T_PRESC and setTTEN simultaneously with one write access. - 1 - 2 - read-write - - - TTEN - Time Trigger Enable -1 - TTCAN enabled, timer is running0 - disabled - 0 - 1 - read-write - - - - - REF_MSG - TTCAN: Reference Message REF_MSG - 0xc0 - 32 - 0x00000000 - 0x9FFFFFFF - - - REF_IDE - REFerence message IDE bit. - 31 - 1 - read-write - - - REF_MSG - REFerence message IDentifier. -If REF_IDE is -1 - REF_ID(28:0) is valid (extended ID) -0 - REF_ID(10:0) is valid (standard ID) -REF_ID is used in TTCAN mode to detect a reference message. This holds for time -slaves (reception) as well as for the time master (transmission). If the reference -message is detected and there are no errors, then the Sync_Mark of this frame will -become the Ref_Mark. -REF_ID(2:0) is not tested and therefore the appropriate register bits are forced to 0. -These bits are used for up to 8 potential time masters. -CAN-CTRL recognizes the reference message only by ID. The payload is not tested. -Additional note: A time master will transmit a reference message in the same way as a -normal frame. REF_ID is intended for detection of a successful transmission of a -reference message. - 0 - 29 - read-write - - - - - TRIG_CFG - TTCAN: Trigger Configuration TRIG_CFG - 0xc4 - 16 - 0x0000 - 0xF73F - - - TEW - Transmit Enable Window -For a single shot transmit trigger there is a time of up to 16 ticks of the cycle time -where the frame is allowed to start. TWE+1 defines the number of ticks. -TEW=0 is a valid setting and shortens the transmit enable window to 1 tick - 12 - 4 - read-write - - - TTYPE - Trigger Type -000b - Immediate Trigger for immediate transmission -001b - Time Trigger for receive triggers -010b - Single Shot Transmit Trigger for exclusive time windows -011b - Transmit Start Trigger for merged arbitrating time windows -100b - Transmit Stop Trigger for merged arbitrating time windows -others - no action -The time of the trigger is defined by TT_TRIG. TTPTR selects the TB slot for the -transmit triggers. See Chapter 6.4 for more details. - 8 - 3 - read-write - - - TTPTR - Transmit Trigger TB slot Pointer -If TTPTR is too big and points to a slot that is not available, then TEIF is set and no -new trigger can be activated after a write access to TT_TRIG_1. -If TTPTR points to an empty slot, then TEIF will be set at the moment, when the -trigger time is reached. - 0 - 6 - read-write - - - - - TT_TRIG - TTCAN: Trigger Time TT_TRIG - 0xc6 - 16 - 0x0000 - 0xFFFF - - - TT_TRIG - Trigger Time -TT_TRIG(15:0) defines the cycle time for a trigger. -For a transmission trigger theearliest point of transmission of the SOF of the appropriate frame will be TT_TRIG+1. - 0 - 16 - read-write - - - - - TT_WTRIG - TTCAN: Watch Trigger Time TT_WTRIG - 0xc8 - 16 - 0x0000 - 0xFFFF - - - TT_WTRIG - Watch Trigger Time -TT_WTRIG(15:0) defines the cycle time for a watch trigger. The initial watch trigger isthe maximum cycle time 0xffff. - 0 - 16 - read-write - - - - - - - CAN1 - CAN1 - CAN - 0xf0084000 - - - CAN2 - CAN2 - CAN - 0xf0088000 - - - CAN3 - CAN3 - CAN - 0xf008c000 - - - WDG0 - WDG0 - WDOG - 0xf0090000 - - 0x10 - 0x10 - registers - - - - CTRL - Control Register - 0x10 - 32 - 0x00000000 - 0x000007FF - - - RSTTIME - The time interval of the reset stage: -0: Clock period x 2^7 -1: Clock period x 2^8 -2: Clock period x 2^9 -3: Clock period x 2^10 -4: Clock period x 2^11 -5: Clock period x 2^12 -6: Clock period x 2^13 -7: Clock period x 2^14 - 8 - 3 - read-write - - - INTTIME - The timer interval of the interrupt stage: -0: Clock period x 2^6 -1: Clock period x 2^8 -2: Clock period x 2^10 -3: Clock period x 2^11 -4: Clock period x 2^12 -5: Clock period x 2^13 -6: Clock period x 2^14 -7: Clock period x 2^15 -8: Clock period x 2^17 -9: Clock period x 2^19 -10: Clock period x 2^21 -11: Clock period x 2^23 -12: Clock period x 2^25 -13: Clock period x 2^27 -14: Clock period x 2^29 -15: Clock period x 2^31 - 4 - 4 - read-write - - - RSTEN - Enable or disable the watchdog reset -0: Disable -1: Enable - 3 - 1 - read-write - - - INTEN - Enable or disable the watchdog interrupt -0: Disable -1: Enable - 2 - 1 - read-write - - - CLKSEL - Clock source of timer: -0: EXTCLK -1: PCLK - 1 - 1 - read-write - - - EN - Enable or disable the watchdog timer -0: Disable -1: Enable - 0 - 1 - read-write - - - - - Restart - Restart Register - 0x14 - 32 - 0x00000000 - 0x0000FFFF - - - RESTART - Write the magic number -ATCWDT200_RESTART_NUM to restart the -watchdog timer. - 0 - 16 - write-only - - - - - WrEn - Write Protection Register - 0x18 - 32 - 0x00000000 - 0x0000FFFF - - - WEN - Write the magic code to disable the write -protection of the Control Register and the -Restart Register. - 0 - 16 - write-only - - - - - St - Status Register - 0x1c - 32 - 0x00000000 - 0x00000001 - - - INTEXPIRED - The status of the watchdog interrupt timer -0: timer is not expired yet -1: timer is expired - 0 - 1 - write-only - - - - - - - WDG1 - WDG1 - WDOG - 0xf0094000 - - - WDG2 - WDG2 - WDOG - 0xf0098000 - - - WDG3 - WDG3 - WDOG - 0xf009c000 - - - PWDG - PWDG - WDOG - 0xf40e8000 - - - MBX0A - MBX0A - MBX - 0xf00a0000 - - 0x0 - 0x24 - registers - - - - CR - Command Registers - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - TXRESET - Reset TX Fifo and word. - 31 - 1 - read-write - - - BARCTL - Bus Access Response Control, when bit 15:14= -00: no bus error will be generated, no wait for fifo write when fifo full and no wait for word/fifo read when word message invalid or fifo empty; or when write to word/fifo message will be ignored. - 01: bus error will be generated when: 1, access invalid address; 2, write to ready only addr; 3, write to fulled fifo or valid message; 4, read from a emptied fifo/word message. -10: no error will be generated, but bus will wait when 1, write to fulled fifo/reg message; 2, read from a emptied fifo/reg message; write to word message will overwrite the existing reg value enven word message are still valid; read from invalid word message will read out last read out message data.happen. -11: reserved. - 14 - 2 - read-write - - - BEIE - Bus Error Interrupt Enable, will enable the interrupt for any bus error as described in the SR bit 13 to bit 8. -1, enable the bus access error interrupt. -0, disable the bus access error interrupt. - 8 - 1 - read-write - - - TFMAIE - TX FIFO message available interrupt enable. -1, enable the TX FIFO massage available interrupt. -0, disable the TX FIFO message available interrupt. - 7 - 1 - read-write - - - TFMEIE - TX FIFO message empty interrupt enable. -1, enable the TX FIFO massage empty interrupt. -0, disable the TX FIFO message empty interrupt. - 6 - 1 - read-write - - - RFMAIE - RX FIFO message available interrupt enable. -1, enable the RX FIFO massage available interrupt. -0, disable the RX FIFO message available interrupt. - 5 - 1 - read-write - - - RFMFIE - RX fifo message full interrupt enable. -1, enable the RX fifo message full interrupt. -0, disable the RX fifo message full interrupt. - 4 - 1 - read-write - - - TWMEIE - TX word message empty interrupt enable. -1, enable the TX word massage empty interrupt. -0, disable the TX word message empty interrupt. - 1 - 1 - read-write - - - RWMVIE - RX word message valid interrupt enable. -1, enable the RX word massage valid interrupt. -0, disable the RX word message valid interrupt. - 0 - 1 - read-write - - - - - SR - Status Registers - 0x4 - 32 - 0x000000E2 - 0xFFFF3FFF - - - RFVC - RX FIFO valid message count - 20 - 4 - read-only - - - TFEC - TX FIFO empty message word count - 16 - 4 - read-only - - - ERRRE - bus Error for read when rx word message are still invalid, this bit is W1C bit. -1, read from word message when the word message are still invalid will cause this error bit set. -0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - 13 - 1 - write-only - - - EWTRF - bus Error for write when tx word message are still valid, this bit is W1C bit. -1, write to word message when the word message are still valid will cause this error bit set. -0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - 12 - 1 - write-only - - - ERRFE - bus Error for read when rx fifo empty, this bit is W1C bit. -1, read from a empty rx fifo will cause this error bit set. -0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - 11 - 1 - write-only - - - EWTFF - bus Error for write when tx fifo full, this bit is W1C bit. -1, write to a fulled tx fifo will cause this error bit set. -0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - 10 - 1 - write-only - - - EAIVA - bus Error for Accessing Invalid Address; this bit is W1C bit. -1, read and write to invalid address in the bus of this block, will set this bit. -0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - 9 - 1 - write-only - - - EW2RO - bus Error for Write to Read Only address; this bit is W1C bit. -1, write to read only address happened in the bus of this block. -0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - 8 - 1 - write-only - - - TFMA - TX FIFO Message slot available, the 4x32 TX FIFO message buffer to the other core full, will not trigger any interrupt. -1, TXFIFO message buffer has slot available -0, no slot available (fifo full) - 7 - 1 - read-write - - - TFME - TX FIFO Message Empty, no any data in the message FIFO buffer from other core, will not trigger any interrupt.message from other core. -1, no any message data in TXFIFO from other core. -0, there are some data in the 4x32 TX FIFO from other core yet. - 6 - 1 - read-write - - - RFMA - RX FIFO Message Available, available data in the 4x32 TX FIFO message buffer to the other core, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. -1, no any data in the 4x32 TXFIFO message buffer. -0, there are some data in the the 4x32 TXFIFO message buffer already. - 5 - 1 - read-only - - - RFMF - RX FIFO Message Full, message from other core; will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. -1, the other core had written 4x32 message in the RXFIFO. -0, no 4x32 RX FIFO message from other core yet. - 4 - 1 - read-only - - - TWME - TX word message empty, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. -1, means this core had write word message to TXREG. -0, means no valid word message in the TXREG yet. - 1 - 1 - read-only - - - RWMV - RX word message valid, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. -1, the other core had written word message in the RXREG. -0, no valid word message yet in the RXREG. - 0 - 1 - read-only - - - - - TXREG - Transmit word message to other core. - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - TXREG - Transmit word message to other core. - 0 - 32 - write-only - - - - - RXREG - Receive word message from other core. - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - RXREG - Receive word message from other core. - 0 - 32 - read-only - - - - - 1 - 0x4 - TXFIFO0 - TXWRD[%s] - no description available - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - TXFIFO - TXFIFO for sending message to other core, FIFO size, 4x32 -can write one of the word address to push data to the FIFO; -can also use 4x32 burst write from 0x010 to push 4 words to the FIFO. - 0 - 32 - write-only - - - - - 1 - 0x4 - RXFIFO0 - RXWRD[%s] - no description available - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXFIFO - RXFIFO for receiving message from other core, FIFO size, 4x32 -can read one of the word address to pop data to the FIFO; -can also use 4x32 burst read from 0x020 to read 4 words from the FIFO. - 0 - 32 - read-only - - - - - - - MBX0B - MBX0B - MBX - 0xf00a4000 - - - MBX1A - MBX1A - MBX - 0xf00a8000 - - - MBX1B - MBX1B - MBX - 0xf00ac000 - - - PTPC - PTPC - PTPC - 0xf00b0000 - - 0x0 - 0x3004 - registers - - - - 2 - 0x1000 - 0,1 - PTPC[%s] - no description available - 0x0 - - Ctrl0 - Control Register 0 - 0x0 - 32 - 0x00000000 - 0x000003FF - - - SUBSEC_DIGITAL_ROLLOVER - Format for ns counter rollover, -1-digital, overflow time 1000000000/0x3B9ACA00 -0-binary, overflow time 0x7FFFFFFF - 9 - 1 - read-write - - - CAPT_SNAP_KEEP - set will keep capture snap till software read capt_snapl. -If this bit is set, software should read capt_snaph first to avoid wrong result. -If this bit is cleared, capture result will be updated at each capture event - 8 - 1 - read-write - - - CAPT_SNAP_POS_EN - set will use posege of input capture signal to latch timestamp value - 7 - 1 - read-write - - - CAPT_SNAP_NEG_EN - No description available - 6 - 1 - read-write - - - COMP_EN - set to enable compare, will be cleared by HW when compare event triggered - 4 - 1 - read-write - - - UPDATE_TIMER - update timer with +/- ts_updt, pulse, clear after set - 3 - 1 - write-only - - - INIT_TIMER - initial timer with ts_updt, pulse, clear after set - 2 - 1 - write-only - - - FINE_COARSE_SEL - 0: coarse update, ns counter add ss_incr[7:0] each clk -1: fine update, ns counter add ss_incr[7:0] each time addend counter overflow - 1 - 1 - read-write - - - TIMER_ENABLE - No description available - 0 - 1 - read-write - - - - - ctrl1 - Control Register 1 - 0x4 - 32 - 0x00000000 - 0x000000FF - - - SS_INCR - constant value used to add ns counter; -such as for 50MHz timer clock, set it to 8'd20 - 0 - 8 - read-write - - - - - timeh - timestamp high - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - TIMESTAMP_HIGH - No description available - 0 - 32 - read-only - - - - - timel - timestamp low - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - TIMESTAMP_LOW - No description available - 0 - 32 - read-only - - - - - ts_updth - timestamp update high - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - SEC_UPDATE - together with ts_updtl, used to initial or update timestamp - 0 - 32 - read-write - - - - - ts_updtl - timestamp update low - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADD_SUB - 1 for sub; 0 for add, used only at update - 31 - 1 - read-write - - - NS_UPDATE - No description available - 0 - 31 - read-write - - - - - addend - No description available - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDEND - used in fine update mode only - 0 - 32 - read-write - - - - - tarh - No description available - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - TARGET_TIME_HIGH - used for generate compare signal if enabled - 0 - 32 - read-write - - - - - tarl - No description available - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - TARGET_TIME_LOW - No description available - 0 - 32 - read-write - - - - - pps_ctrl - No description available - 0x2c - 32 - 0x00000000 - 0x0000000F - - - PPS_CTRL - No description available - 0 - 4 - read-write - - - - - capt_snaph - No description available - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPT_SNAP_HIGH - take snapshot for input capture signal, at pos or neg or both; -the result can be kept or updated at each event according to cfg0.bit8 - 0 - 32 - read-only - - - - - capt_snapl - No description available - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPT_SNAP_LOW - No description available - 0 - 32 - read-write - - - - - - time_sel - No description available - 0x2000 - 32 - 0x00000000 - 0x0000000F - - - CAN3_TIME_SEL - No description available - 3 - 1 - read-write - - - CAN2_TIME_SEL - No description available - 2 - 1 - read-write - - - CAN1_TIME_SEL - No description available - 1 - 1 - read-write - - - CAN0_TIME_SEL - set to use ptpc1 for canx -clr to use ptpc0 for canx - 0 - 1 - read-write - - - - - int_sts - No description available - 0x2004 - 32 - 0x00000000 - 0x00070007 - - - COMP_INT_STS1 - No description available - 18 - 1 - write-only - - - CAPTURE_INT_STS1 - No description available - 17 - 1 - write-only - - - PPS_INT_STS1 - No description available - 16 - 1 - write-only - - - COMP_INT_STS0 - No description available - 2 - 1 - write-only - - - CAPTURE_INT_STS0 - No description available - 1 - 1 - write-only - - - PPS_INT_STS0 - No description available - 0 - 1 - write-only - - - - - int_en - No description available - 0x2008 - 32 - 0x00000000 - 0x00070007 - - - COMP_INT_STS1 - No description available - 18 - 1 - read-write - - - CAPTURE_INT_STS1 - No description available - 17 - 1 - read-write - - - PPS_INT_STS1 - No description available - 16 - 1 - read-write - - - COMP_INT_STS0 - No description available - 2 - 1 - read-write - - - CAPTURE_INT_STS0 - No description available - 1 - 1 - read-write - - - PPS_INT_STS0 - No description available - 0 - 1 - read-write - - - - - ptpc_can_ts_sel - No description available - 0x3000 - 32 - 0x00000000 - 0xFFFFFF00 - - - TSU_TBIN3_SEL - No description available - 26 - 6 - read-write - - - TSU_TBIN2_SEL - No description available - 20 - 6 - read-write - - - TSU_TBIN1_SEL - No description available - 14 - 6 - read-write - - - TSU_TBIN0_SEL - No description available - 8 - 6 - read-write - - - - - - - DMAMUX - DMAMUX - DMAMUX - 0xf00c0000 - - 0x0 - 0x40 - registers - - - - 16 - 0x4 - HDMA_MUX0,HDMA_MUX1,HDMA_MUX2,HDMA_MUX3,HDMA_MUX4,HDMA_MUX5,HDMA_MUX6,HDMA_MUX7,XDMA_MUX0,XDMA_MUX1,XDMA_MUX2,XDMA_MUX3,XDMA_MUX4,XDMA_MUX5,XDMA_MUX6,XDMA_MUX7 - MUXCFG[%s] - no description available - 0x0 - 32 - 0x00000000 - 0x8000007F - - - ENABLE - DMA Mux Channel Enable -Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be -used to disable or reconfigure a DMA channel. -0b - DMA Mux channel is disabled -1b - DMA Mux channel is enabled - 31 - 1 - read-write - - - SOURCE - DMA Channel Source -Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" - 0 - 7 - read-write - - - - - - - HDMA - HDMA - DMA - 0xf00c4000 - - 0x10 - 0x130 - registers - - - - DMACfg - DMAC Configuration Register - 0x10 - 32 - 0x00000000 - 0xC3FFFFFF - - - CHAINXFR - Chain transfer -0x0: Chain transfer is not configured -0x1: Chain transfer is configured - 31 - 1 - read-only - - - REQSYNC - DMA request synchronization. The DMA request synchronization should be configured to avoid signal integrity problems when the request signal is not clocked by the system bus clock, which the DMA control logic operates in. If the request synchronization is not configured, the request signal is sampled directly without synchronization. -0x0: Request synchronization is not configured -0x1: Request synchronization is configured - 30 - 1 - read-only - - - DATAWIDTH - AXI bus data width -0x0: 32 bits -0x1: 64 bits -0x2: 128 bits -0x3: 256 bits - 24 - 2 - read-only - - - ADDRWIDTH - AXI bus address width -0x18: 24 bits -0x19: 25 bits -... -0x40: 64 bits -Others: Invalid - 17 - 7 - read-only - - - CORENUM - DMA core number -0x0: 1 core -0x1: 2 cores - 16 - 1 - read-only - - - BUSNUM - AXI bus interface number -0x0: 1 AXI bus -0x1: 2 AXI busses - 15 - 1 - read-only - - - REQNUM - Request/acknowledge pair number -0x0: 0 pair -0x1: 1 pair -0x2: 2 pairs -... -0x10: 16 pairs - 10 - 5 - read-only - - - FIFODEPTH - FIFO depth -0x4: 4 entries -0x8: 8 entries -0x10: 16 entries -0x20: 32 entries -Others: Invalid - 4 - 6 - read-only - - - CHANNELNUM - Channel number -0x1: 1 channel -0x2: 2 channels -... -0x8: 8 channels -Others: Invalid - 0 - 4 - read-only - - - - - DMACtrl - DMAC Control Register - 0x20 - 32 - 0x00000000 - 0x00000001 - - - RESET - Software reset control. Write 1 to this bit to reset the DMA core and disable all channels. -Note: The software reset may cause the in-completion of AXI transaction. - 0 - 1 - write-only - - - - - ChAbort - Channel Abort Register - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - CHABORT - Write 1 to bit n to abort channel n. The bits should only be set when the corresponding channels are enabled. Otherwise, the writes will be ignored for channels that are not enabled. (N: Number of channels) - 0 - 32 - write-only - - - - - IntStatus - Interrupt Status Register - 0x30 - 32 - 0x00000000 - 0x00FFFFFF - - - TC - The terminal count status, one bit per channel. The terminal count status is set when a channel transfer finishes without the abort or error event. -0x0: Channel n has no terminal count status -0x1: Channel n has terminal count status - 16 - 8 - write-only - - - ABORT - The abort status of channel, one bit per channel. The abort status is set when a channel transfer is aborted. -0x0: Channel n has no abort status -0x1: Channel n has abort status - 8 - 8 - write-only - - - ERROR - The error status, one bit per channel. The error status is set when a channel transfer encounters the following error events: -- Bus error -- Unaligned address -- Unaligned transfer width -- Reserved configuration -0x0: Channel n has no error status -0x1: Channel n has error status - 0 - 8 - write-only - - - - - ChEN - Channel Enable Register - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - CHEN - Alias of the Enable field of all ChnCtrl registers - 0 - 32 - read-only - - - - - 8 - 0x20 - ch0,ch1,ch2,ch3,ch4,ch5,ch6,ch7 - CHCTRL[%s] - no description available - 0x40 - - Ctrl - Channel n Control Register - 0x0 - 32 - 0x00000000 - 0xEFFFFFFF - - - SRCBUSINFIDX - Bus interface index that source data is read from -0x0: Data is read from bus interface 0 -0x1: Data is read from bus interface - 31 - 1 - read-write - - - DSTBUSINFIDX - Bus interface index that destination data is written to -0x0: Data is written to bus interface 0 -0x1: Data is written to bus interface 1 - 30 - 1 - read-write - - - PRIORITY - Channel priority level -0x0: Lower priority -0x1: Higher priority - 29 - 1 - read-write - - - SRCBURSTSIZE - Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. -The burst transfer byte number is (SrcBurstSize * SrcWidth). -0x0: 1 transfer -0x1: 2 transfers -0x2: 4 transfers -0x3: 8 transfers -0x4: 16 transfers -0x5: 32 transfers -0x6: 64 transfers -0x7: 128 transfers -0x8: 256 transfers -0x9:512 transfers -0xa: 1024 transfers -0xb-0xf: Reserved, setting this field with a reserved value triggers the error exception -for XDMA, the maximum allowed value is 0xa; for HDMA, the maximum allowed value is 0x7 - 24 - 4 - read-write - - - SRCWIDTH - Source transfer width -0x0: Byte transfer -0x1: Half-word transfer -0x2: Word transfer -0x3: Double word transfer -0x4: Quad word transfer -0x5: Eight word transfer -0x6-x7: Reserved, setting this field with a reserved value triggers the error exception -for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 - 21 - 3 - read-write - - - DSTWIDTH - Destination transfer width. -Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; otherwise the error event will be triggered. For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. -See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. -0x0: Byte transfer -0x1: Half-word transfer -0x2: Word transfer -0x3: Double word transfer -0x4: Quad word transfer -0x5: Eight word transfer -0x6-x7: Reserved, setting this field with a reserved value triggers the error exception -for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 - 18 - 3 - read-write - - - SRCMODE - Source DMA handshake mode -0x0: Normal mode -0x1: Handshake mode - 17 - 1 - read-write - - - DSTMODE - Destination DMA handshake mode -0x0: Normal mode -0x1: Handshake mode - 16 - 1 - read-write - - - SRCADDRCTRL - Source address control -0x0: Increment address -0x1: Decrement address -0x2: Fixed address -0x3: Reserved, setting the field with this value triggers the error exception - 14 - 2 - read-write - - - DSTADDRCTRL - Destination address control -0x0: Increment address -0x1: Decrement address -0x2: Fixed address -0x3: Reserved, setting the field with this value triggers the error exception - 12 - 2 - read-write - - - SRCREQSEL - Source DMA request select. Select the request/ack handshake pair that the source device is connected to. - 8 - 4 - read-write - - - DSTREQSEL - Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. - 4 - 4 - read-write - - - INTABTMASK - Channel abort interrupt mask -0x0: Allow the abort interrupt to be triggered -0x1: Disable the abort interrupt - 3 - 1 - read-write - - - INTERRMASK - Channel error interrupt mask -0x0: Allow the error interrupt to be triggered -0x1: Disable the error interrupt - 2 - 1 - read-write - - - INTTCMASK - Channel terminal count interrupt mask -0x0: Allow the terminal count interrupt to be triggered -0x1: Disable the terminal count interrupt - 1 - 1 - read-write - - - ENABLE - Channel enable bit -0x0: Disable -0x1: Enable - 0 - 1 - read-write - - - - - TranSize - Channel n Transfer Size Register - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - TRANSIZE - Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. -If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated. - 0 - 32 - read-write - - - - - SrcAddr - Channel n Source Address Low Part Register - 0x8 - 32 - 0x00000001 - 0xFFFFFFFF - - - SRCADDRL - Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. -This address must be aligned to the source transfer size; otherwise, an error event will be triggered. - 0 - 32 - read-write - - - - - SrcAddrH - Channel n Source Address High Part Register - 0xc - 32 - 0x00000001 - 0xFFFFFFFF - - - SRCADDRH - High part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. -This register exists only when the address bus width is wider than 32 bits. - 0 - 32 - read-write - - - - - DstAddr - Channel n Destination Address Low Part Register - 0x10 - 32 - 0x00000001 - 0xFFFFFFFF - - - DSTADDRL - Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. -This address must be aligned to the destination transfer size; otherwise the error event will be triggered. - 0 - 32 - read-write - - - - - DstAddrH - Channel n Destination Address High Part Register - 0x14 - 32 - 0x00000001 - 0xFFFFFFFF - - - DSTADDRH - High part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. -This address must be aligned to the destination transfer size; otherwise the error event will be triggered. -This register exists only when the address bus width is wider than 32 bits. - 0 - 32 - read-write - - - - - LLPointer - Channel n Linked List Pointer Low Part Register - 0x18 - 32 - 0x00000000 - 0xFFFFFFF9 - - - LLPOINTERL - Low part of the pointer to the next descriptor. The pointer must be double word aligned. - 3 - 29 - read-write - - - LLDBUSINFIDX - Bus interface index that the next descriptor is read from -0x0: The next descriptor is read from bus interface 0 - 0 - 1 - read-write - - - - - LLPointerH - Channel n Linked List Pointer High Part Register - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - LLPOINTERH - High part of the pointer to the next descriptor. -This register exists only when the address bus width is wider than 32 bits. - 0 - 32 - read-write - - - - - - - - XDMA - XDMA - DMA - 0xf3048000 - - - RNG - RNG - RNG - 0xf00c8000 - - 0x0 - 0x40 - registers - - - - CMD - Command Register - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SFTRST - Soft Reset, Perform a software reset of the RNG This bit is self-clearing. -0 Do not perform a software reset. -1 Software reset - 6 - 1 - read-write - - - CLRERR - Clear the Error, clear the errors in the ESR register and the RNG interrupt. This bit is self-clearing. -0 Do not clear the errors and the interrupt. -1 Clear the errors and the interrupt. - 5 - 1 - read-write - - - CLRINT - Clear the Interrupt, clear the RNG interrupt if an error is not present. This bit is self-clearing. -0 Do not clear the interrupt. -1 Clear the interrupt - 4 - 1 - read-write - - - GENSD - Generate Seed, when both ST and GS triggered, ST first and GS next. - 1 - 1 - read-write - - - SLFCHK - Self Test, when both ST and GS triggered, ST first and GS next. - 0 - 1 - read-write - - - - - CTRL - Control Register - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - MIRQERR - Mask Interrupt Request for Error - 6 - 1 - read-write - - - MIRQDN - Mask Interrupt Request for Done Event, asks the interrupts generated upon the completion of the seed and self-test modes. The status of these jobs can be viewed by: -• Reading the STA and viewing the seed done and the self-test done bits (STA[SDN, STDN]). -• Viewing the RNG_CMD for the generate-seed or the self-test bits (CMD[GS,ST]) being set, indicating that the operation is still taking place. - 5 - 1 - read-write - - - AUTRSD - Auto Reseed - 4 - 1 - read-write - - - FUFMOD - FIFO underflow response mode -00 Return all zeros and set the ESR[FUFE]. -01 Return all zeros and set the ESR[FUFE]. -10 Generate the bus transfer error -11 Generate the interrupt and return all zeros (overrides the CTRL[MASKERR]). - 0 - 2 - read-write - - - - - STA - Status Register - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - SCPF - Self Check Pass Fail - 21 - 3 - read-only - - - FUNCERR - Error was detected, check ESR register for details - 16 - 1 - read-only - - - FSIZE - Fifo Size, it is 5 in this design. - 12 - 4 - read-only - - - FRNNU - Fifo Level, Indicates the number of random words currently in the output FIFO - 8 - 4 - read-only - - - NSDDN - New seed done. - 6 - 1 - read-only - - - FSDDN - 1st Seed done -When "1", Indicates that the RNG generated the first seed. - 5 - 1 - read-only - - - SCDN - Self Check Done -Indicates whether Self Test is done or not. Can be cleared by the hardware reset or a new self test is -initiated by setting the CMD[ST]. -0 Self test not completed -1 Completed a self test since the last reset. - 4 - 1 - read-only - - - RSDREQ - Reseed needed -Indicates that the RNG needs to be reseeded. This is done by setting the CMD[GS], or -automatically if the CTRL[ARS] is set. - 3 - 1 - read-only - - - IDLE - Idle, the RNG is in the idle mode, and internal clocks are disabled, in this mode, access to the FIFO is allowed. Once the FIFO is empty, the RNGB fills the FIFO and then enters idle mode again. - 2 - 1 - read-only - - - BUSY - when 1, means the RNG engine is busy for seeding or random number generation, self test and so on. - 1 - 1 - read-only - - - - - ERR - Error Registers - 0xc - 32 - 0x00000000 - 0xFFFFFF3F - - - FUFE - FIFO access error(underflow) - 5 - 1 - read-only - - - SCKERR - Self-test error -Indicates that the RNG failed the most recent self test. This bit is sticky and can only be reset by a -hardware reset or by writing 1 to the CMD[CE] - 3 - 1 - read-only - - - - - FO2B - FIFO out to bus/cpu - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - FO2B - SW read the FIFO output. - 0 - 32 - read-only - - - - - 8 - 0x4 - FO2S0,FO2S1,FO2S2,FO2S3,FO2S4,FO2S5,FO2S6,FO2S7 - R2SK[%s] - no description available - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - FO2S0 - FIFO out to KMAN, will be SDP engine key. - 0 - 32 - read-only - - - - - - - KEYM - KEYM - KEYM - 0xf00cc000 - - 0x0 - 0x50 - registers - - - - 8 - 0x4 - SFK0,SFK1,SFK2,SFK3,SFK4,SFK5,SFK6,SFK7 - SOFTMKEY[%s] - no description available - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - KEY - software symmetric key -key will be scambled to 4 variants for software to use, and replicable on same chip. -scramble keys are chip different, and not replicable on different chip -must be write sequencely from 0 - 7, otherwise key value will be treated as all 0 - 0 - 32 - read-write - - - - - 8 - 0x4 - SPK0,SPK1,SPK2,SPK3,SPK4,SPK5,SPK6,SPK7 - SOFTPKEY[%s] - no description available - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - KEY - software asymmetric key -key is derived from scrambles of fuse private key, software input key, SRK, and system security status. -This key os read once, sencondary read will read out 0 - 0 - 32 - read-write - - - - - SEC_KEY_CTL - secure key generation - 0x40 - 32 - 0x00000000 - 0x80011117 - - - LOCK_SEC_CTL - block secure state key setting being changed - 31 - 1 - read-write - - - SK_VAL - session key valid -0: session key is all 0's and not usable -1: session key is valid - 16 - 1 - read-only - - - SMK_SEL - software symmetric key selection -0: use origin value in software symmetric key -1: use scramble version of software symmetric key - 12 - 1 - read-write - - - ZMK_SEL - batt symmetric key selection -0: use scramble version of software symmetric key -1: use origin value in software symmetric key - 8 - 1 - read-write - - - FMK_SEL - fuse symmetric key selection -0: use scramble version of fuse symmetric key -1: use alnertave scramble of fuse symmetric key - 4 - 1 - read-write - - - KEY_SEL - secure symmtric key synthesize setting, key is a XOR of following -bit0: fuse mk, 0: not selected, 1:selected -bit1: zmk from batt, 0: not selected, 1:selected -bit2: software key 0: not selected, 1:selected - 0 - 3 - read-write - - - - - NSC_KEY_CTL - non-secure key generation - 0x44 - 32 - 0x00000000 - 0x80011117 - - - LOCK_NSC_CTL - block non-secure state key setting being changed - 31 - 1 - read-write - - - SK_VAL - session key valid -0: session key is all 0's and not usable -1: session key is valid - 16 - 1 - read-only - - - SMK_SEL - software symmetric key selection -0: use scramble version of software symmetric key -1: use origin value in software symmetric key - 12 - 1 - read-write - - - ZMK_SEL - batt symmetric key selection -0: use scramble version of software symmetric key -1: use origin value in software symmetric key - 8 - 1 - read-write - - - FMK_SEL - fuse symmetric key selection -0: use scramble version of fuse symmetric key -1: use origin value in fuse symmetric key - 4 - 1 - read-write - - - KEY_SEL - non-secure symmtric key synthesize setting, key is a XOR of following -bit0: fuse mk, 0: not selected, 1:selected -bit1: zmk from batt, 0: not selected, 1:selected -bit2: software key 0: not selected, 1:selected - 0 - 3 - read-write - - - - - RNG - Random number interface behavior - 0x48 - 32 - 0x00000000 - 0x00010001 - - - BLOCK_RNG_XOR - block RNG_XOR bit from changing, if this bit is written to 1, it will hold 1 until next reset -0: RNG_XOR can be changed by software -1: RNG_XOR ignore software change from software - 16 - 1 - read-write - - - RNG_XOR - control how SFK is accepted from random number generator -0: SFK value replaced by random number input -1: SFK value exclusive or with random number input,this help generate random number using 2 rings inside RNG - 0 - 1 - read-write - - - - - READ_CONTROL - key read out control - 0x4c - 32 - 0x00000000 - 0x00010001 - - - BLOCK_PK_READ - asymmetric key readout control, if this bit is written to 1, it will hold 1 until next reset -0: key can be read out -1: key cannot be read out - 16 - 1 - read-write - - - BLOCK_SMK_READ - symmetric key readout control, if this bit is written to 1, it will hold 1 until next reset -0: key can be read out -1: key cannot be read out - 0 - 1 - read-write - - - - - - - I2S0 - I2S0 - I2S - 0xf0100000 - - 0x0 - 0x80 - registers - - - - CTRL - Control Register - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SFTRST_RX - software reset the RX module if asserted to be 1'b1. Self-clear. - 18 - 1 - read-write - - - SFTRST_TX - software reset the TX module if asserted to be 1'b1. Self-clear. - 17 - 1 - read-write - - - SFTRST_CLKGEN - software reset the CLK GEN module if asserted to be 1'b1. Self-clear. - 16 - 1 - read-write - - - TXDNIE - TX buffer data needed interrupt enable -0: TXE interrupt masked -1: TXE interrupt not masked. Used to generate an interrupt request when the TXE flag is set. - 15 - 1 - read-write - - - RXDAIE - RX buffer data available interrupt enable -0: RXNE interrupt masked -1: RXNE interrupt not masked. Used to generate an interrupt request when the RXNE flag is set. - 14 - 1 - read-write - - - ERRIE - Error interrupt enable -This bit controls the generation of an interrupt when an error condition (UD, OV) occurs. -0: Error interrupt is masked -1: Error interrupt is enabled - 13 - 1 - read-write - - - TX_DMA_EN - Asserted to use DMA, else to use interrupt - 12 - 1 - read-write - - - RX_DMA_EN - Asserted to use DMA, else to use interrupt - 11 - 1 - read-write - - - TXFIFOCLR - Self-clear - 10 - 1 - read-write - - - RXFIFOCLR - Self-clear - 9 - 1 - read-write - - - TX_EN - enable for each TX data pad - 5 - 4 - read-write - - - RX_EN - enable for each RX data pad - 1 - 4 - read-write - - - I2S_EN - enable for the module - 0 - 1 - read-write - - - - - RFIFO_FILLINGS - Rx FIFO Filling Level - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - RX3 - RX3 fifo fillings - 24 - 8 - read-only - - - RX2 - RX2 fifo fillings - 16 - 8 - read-only - - - RX1 - RX1 fifo fillings - 8 - 8 - read-only - - - RX0 - RX0 fifo fillings - 0 - 8 - read-only - - - - - TFIFO_FILLINGS - Tx FIFO Filling Level - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - TX3 - TX3 fifo fillings - 24 - 8 - read-only - - - TX2 - TX2 fifo fillings - 16 - 8 - read-only - - - TX1 - TX1 fifo fillings - 8 - 8 - read-only - - - TX0 - TX0 fifo fillings - 0 - 8 - read-only - - - - - FIFO_THRESH - TX/RX FIFO Threshold setting. - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - TX - TX fifo threshold to trigger STA[tx_dn]. When tx fifo filling is smaller than or equal to the threshold, assert the tx_dn flag. - 8 - 8 - read-write - - - RX - RX fifo threshold to trigger STA[rx_da]. When rx fifo filling is greater than or equal to the threshold, assert the rx_da flag. - 0 - 8 - read-write - - - - - STA - Status Registers - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - TX_UD - Asserted when tx fifo is underflow. Should be ANDed with CTRL[tx_en] the for correct value. Write 1 to any of these 4 bits will clear the underflow error. - 13 - 4 - write-only - - - RX_OV - Asserted when rx fifo is overflow. Write 1 to any of these 4 bits will clear the overflow error. - 9 - 4 - write-only - - - TX_DN - Asserted when tx fifo data are needed. - 5 - 4 - read-only - - - RX_DA - Asserted when rx fifo data are available. - 1 - 4 - read-only - - - - - 4 - 0x4 - DATA0,DATA1,DATA2,DATA3 - RXD[%s] - no description available - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - D - No description available - 0 - 32 - read-only - - - - - 4 - 0x4 - DATA0,DATA1,DATA2,DATA3 - TXD[%s] - no description available - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - D - No description available - 0 - 32 - write-only - - - - - CFGR - Configruation Regsiters - 0x50 - 32 - 0x40000000 - 0xFFFFFFFF - - - BCLK_GATEOFF - Gate off the bclk. Asserted to gate-off the BCLK. - 30 - 1 - read-write - - - BCLK_DIV - Linear prescaler to generate BCLK from MCLK. -BCLK_DIV [8:0] = 0: BCLK=No CLK. -BCLK_DIV [8:0] = 1: BCLK=MCLK/1 -BCLK_DIV [8:0] = n: BCLK=MCLK/(n). -Note: These bits should be configured when the I2S is disabled. It is used only when the I2S is in master mode. - 21 - 9 - read-write - - - INV_BCLK_OUT - Invert the BCLK before sending it out to pad. Only valid in BCLK master mode - 20 - 1 - read-write - - - INV_BCLK_IN - Invert the BCLK pad input before using it internally. Only valid in BCLK slave mode - 19 - 1 - read-write - - - INV_FCLK_OUT - Invert the FCLK before sending it out to pad. Only valid in FCLK master mode - 18 - 1 - read-write - - - INV_FCLK_IN - Invert the FCLK pad input before using it internally. Only valid in FCLK slave mode - 17 - 1 - read-write - - - INV_MCLK_OUT - Invert the MCLK before sending it out to pad. Only valid in MCLK master mode - 16 - 1 - read-write - - - INV_MCLK_IN - Invert the MCLK pad input before using it internally. Only valid in MCLK slave mode - 15 - 1 - read-write - - - BCLK_SEL_OP - asserted to use external clk source - 14 - 1 - read-write - - - FCLK_SEL_OP - asserted to use external clk source - 13 - 1 - read-write - - - MCK_SEL_OP - asserted to use external clk source - 12 - 1 - read-write - - - FRAME_EDGE - The start edge of a frame -0: Falling edge indicates a new frame (Just like standard I2S Philips standard) -1: Rising edge indicates a new frame - 11 - 1 - read-write - - - CH_MAX - CH_MAX[4:0] s the number of channels supported in TDM mode. When not in TDM mode, it must be set as 2. -It must be an even number, so CH_MAX[0] is always 0. -5'h2: 2 channels -5'h4: 4 channels -... -5‘h10: 16 channels (max) - 6 - 5 - read-write - - - TDM_EN - TDM mode -0: not TDM mode -1: TDM mode - 5 - 1 - read-write - - - STD - I2S standard selection -00: I2S Philips standard. -01: MSB justified standard (left justified) -10: LSB justified standard (right justified) -11: PCM standard -Note: For correct operation, these bits should be configured when the I2S is disabled. - 3 - 2 - read-write - - - DATSIZ - Data length to be transferred -00: 16-bit data length -01: 24-bit data length -10: 32-bit data length -11: Not allowed -Note: For correct operation, these bits should be configured when the I2S is disabled. - 1 - 2 - read-write - - - CHSIZ - Channel length (number of bits per audio channel) -0: 16-bit wide -1: 32-bit wide -The bit write operation has a meaning only if DATSIZ = 00 otherwise the channel length is fixed to 32-bit by hardware whatever the value filled in. -Note: For correct operation, this bit should be configured when the I2S is disabled. - 0 - 1 - read-write - - - - - MISC_CFGR - Misc configuration Registers - 0x58 - 32 - 0x00042000 - 0xFFFFEC01 - - - MCLK_GATEOFF - Gate off the mclk. This mclk is the output of a glitch prone mux, so every time to switch the mclk, the gate off clock should be asserted at first. After the clock is switched, de-assert this bit to ungate off the mclk. - 13 - 1 - read-write - - - MCLKOE - Master clock output to pad enable -0: Master clock output is disabled -1: Master clock output is enabled -Note: This bit should be configured when the I2S is disabled. It is used only when the I2S is in master mode. - 0 - 1 - read-write - - - - - 4 - 0x4 - DATA0,DATA1,DATA2,DATA3 - RXDSLOT[%s] - no description available - 0x60 - 32 - 0x0000FFFF - 0x0000FFFF - - - EN - No description available - 0 - 16 - read-write - - - - - 4 - 0x4 - DATA0,DATA1,DATA2,DATA3 - TXDSLOT[%s] - no description available - 0x70 - 32 - 0x0000FFFF - 0x0000FFFF - - - EN - No description available - 0 - 16 - read-write - - - - - - - I2S1 - I2S1 - I2S - 0xf0104000 - - - I2S2 - I2S2 - I2S - 0xf0108000 - - - I2S3 - I2S3 - I2S - 0xf010c000 - - - DAO - DAO - DAO - 0xf0110000 - - 0x0 - 0x1c - registers - - - - CTRL - Control Register - 0x0 - 32 - 0x00000000 - 0x000200FF - - - HPF_EN - Whether HPF is enabled. This HPF is used to filter out the DC part. - 17 - 1 - read-write - - - MONO - Asserted to let the left and right channel output the same value. - 7 - 1 - read-write - - - RIGHT_EN - Asserted to enable the right channel - 6 - 1 - read-write - - - LEFT_EN - Asserted to enable the left channel - 5 - 1 - read-write - - - REMAP - 1: Use remap pwm version. The remap version is a version that one pwm output is tied to zero when the input pcm signal is positive or negative -0: Don't use remap pwm version - 4 - 1 - read-write - - - INVERT - all the outputs are inverted before sending to pad - 3 - 1 - read-write - - - FALSE_LEVEL - the pad output in False run mode, or when the module is disabled -0: all low -1: all high -2: P-high, N-low -3. output is not enabled - 1 - 2 - read-write - - - FALSE_RUN - the module continues to consume data, but all the pads are constant, thus no audio out - 0 - 1 - read-write - - - - - CMD - Command Register - 0x8 - 32 - 0x00000000 - 0x00000003 - - - SFTRST - Self-clear - 1 - 1 - read-write - - - RUN - Enable this module to run. - 0 - 1 - read-write - - - - - RX_CFGR - Configuration Register - 0xc - 32 - 0x00000000 - 0x000007C0 - - - CH_MAX - CH_MAX[3:0] is the number if channels supported in TDM mode. When not in TDM mode, it must be set as 2. -It must be an even number, so CH_MAX[0] is always 0. -4'h2: 2 channels -4'h4: 4 channels -etc - 6 - 5 - read-write - - - - - RXSLT - RX Slot Control Register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - EN - Slot enable for the channels. - 0 - 32 - read-write - - - - - HPF_MA - HPF A Coef Register - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - COEF - Composite value of coef A of the Order-1 HPF - 0 - 32 - read-write - - - - - HPF_B - HPF B Coef Register - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - COEF - coef B of the Order-1 HPF - 0 - 32 - read-write - - - - - - - PDM - PDM - PDM - 0xf0114000 - - 0x0 - 0x34 - registers - - - - CTRL - Control Register - 0x0 - 32 - 0x00000000 - 0x809FF7FF - - - SFTRST - software reset the module. Self-clear. - 31 - 1 - read-write - - - SOF_FEDGE - asserted if the falling edge of the ref fclk from DAO is the start of a new frame. This is used to to align DAO feedback signal. - 23 - 1 - read-write - - - USE_COEF_RAM - Asserted to use Coef RAM instead of Coef ROM - 20 - 1 - read-write - - - FILT_CRX_ERR_IE - data accessed out of boundary error interruput enable. The error happens when the module cannot calculate the enough number of data in time. - 19 - 1 - read-write - - - OFIFO_OVFL_ERR_IE - output fifo overflow error interrupt enable - 18 - 1 - read-write - - - CIC_OVLD_ERR_IE - CIC overload error interrupt enable - 17 - 1 - read-write - - - CIC_SAT_ERR_IE - Error interrupt enable -This bit controls the generation of an interrupt when an error condition (CIC saturation) occurs. -0: Error interrupt is masked -1: Error interrupt is enabled - 16 - 1 - read-write - - - DEC_AFT_CIC - decimation rate after CIC. Now it is forced to be 3. - 12 - 4 - read-write - - - CAPT_DLY - Capture cycle delay>=0, should be less than PDM_CLK_HFDIV - 7 - 4 - read-write - - - PDM_CLK_HFDIV - The clock divider will work at least 4. -0: div-by-2, -1: div-by-4 -. . . -n: div-by-2*(n+1) - 3 - 4 - read-write - - - PDM_CLK_DIV_BYPASS - asserted to bypass the pdm clock divider - 2 - 1 - read-write - - - PDM_CLK_OE - pdm_clk_output_en - 1 - 1 - read-write - - - HPF_EN - pdm high pass filter enable. This order-1 HPF only applies to the PDM mic data. - 0 - 1 - read-write - - - - - CH_CTRL - Channel Control Register - 0x4 - 32 - 0x00000000 - 0x00FF03FF - - - CH_POL - Asserted to select PDM_CLK high level captured, otherwise to select PDM_CLK low level captured. - 16 - 8 - read-write - - - CH_EN - Asserted to enable the channel. -Ch8 & 9 are refs. -Ch0-7 are pdm mics. - 0 - 10 - read-write - - - - - ST - Status Register - 0x8 - 32 - 0x00000000 - 0x0000000F - - - FILT_CRX_ERR - data accessed out of boundary error - 3 - 1 - write-only - - - OFIFO_OVFL_ERR - output fifo overflow error. The reason may be sampling frequency mismatch, either fast or slow. - 2 - 1 - write-only - - - CIC_OVLD_ERR - CIC overload error. write 1 clear - 1 - 1 - write-only - - - CIC_SAT_ERR - CIC saturation. Write 1 clear - 0 - 1 - write-only - - - - - CH_CFG - Channel Configuration Register - 0xc - 32 - 0x00000000 - 0x000FFFFF - - - CH9_TYPE - No description available - 18 - 2 - read-write - - - CH8_TYPE - No description available - 16 - 2 - read-write - - - CH7_TYPE - No description available - 14 - 2 - read-write - - - CH6_TYPE - No description available - 12 - 2 - read-write - - - CH5_TYPE - No description available - 10 - 2 - read-write - - - CH4_TYPE - No description available - 8 - 2 - read-write - - - CH3_TYPE - No description available - 6 - 2 - read-write - - - CH2_TYPE - No description available - 4 - 2 - read-write - - - CH1_TYPE - No description available - 2 - 2 - read-write - - - CH0_TYPE - Type of Channel 0 -2'b00: dec-by-3 wiith filter type0 (CIC Compenstation+norm filter) -2'b01: dec-by-3 with filter type 1 (No CIC compenstation, only norm filter) - 0 - 2 - read-write - - - - - CIC_CFG - CIC configuration register - 0x10 - 32 - 0x00000000 - 0x0000FFFF - - - POST_SCALE - the shift value after CIC results. - 10 - 6 - read-write - - - SGD - Sigma_delta_order[1:0] -2'b00: 7 -2'b01: 6 -2'b10: 5 -Others: unused - 8 - 2 - read-write - - - CIC_DEC_RATIO - CIC decimation factor - 0 - 8 - read-write - - - - - CTRL_INBUF - In Buf Control Register - 0x14 - 32 - 0x00000000 - 0x3FFFFFFF - - - MAX_PTR - The buf size-1 for each channel - 22 - 8 - read-write - - - PITCH - The spacing between starting address of adjacent channels - 11 - 11 - read-write - - - START_ADDR - The starting address of channel 0 in filter data buffer - 0 - 11 - read-write - - - - - CTRL_FILT0 - Filter 0 Control Register - 0x18 - 32 - 0x00000000 - 0x0000FFFF - - - COEF_LEN_M0 - Coef length of filter type 2'b00 in coef memory - 8 - 8 - read-write - - - COEF_START_ADDR - Starting address of Coef of filter type 2'b00 in coef memory - 0 - 8 - read-write - - - - - CTRL_FILT1 - Filter 1 Control Register - 0x1c - 32 - 0x00000000 - 0x0000FFFF - - - COEF_LEN_M1 - Coef length of filter type 2'b01 in coef memory - 8 - 8 - read-write - - - COEF_START_ADDR - Starting address of Coef of filter type 2'b01 in coef memory - 0 - 8 - read-write - - - - - RUN - Run Register - 0x20 - 32 - 0x00000000 - 0x00000001 - - - PDM_EN - Asserted to enable the module - 0 - 1 - read-write - - - - - MEMAddr - Memory Access Address - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR - 0--0x0FFFFFFF: COEF_RAM -0x10000000--0x1FFFFFFF: DATA_RAM - 0 - 32 - read-write - - - - - MEMData - Memory Access Data - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - The data write-to/read-from buffer - 0 - 32 - read-write - - - - - HPF_MA - HPF A Coef Register - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - COEF - Composite value of coef A of the Order-1 HPF - 0 - 32 - read-write - - - - - HPF_B - HPF B Coef Register - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - COEF - coef B of the Order-1 HPF - 0 - 32 - read-write - - - - - - - PWM0 - PWM0 - PWM - 0xf0200000 - - 0x0 - 0x290 - registers - - - - unlk - Shadow registers unlock register - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHUNLK - write 0xB0382607 to unlock the shadow registers of register offset from 0x04 to 0x78, -otherwise the shadow registers can not be written. - 0 - 32 - read-write - - - - - sta - Counter start register - UNION_STA - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - XSTA - pwm timer counter extended start point, should back to this value after reach xrld - 28 - 4 - read-write - - - STA - pwm timer counter start value - sta/rld will be loaded from shadow register to work register at main counter reload time, or software write unlk.shunlk - 4 - 24 - read-write - - - - - rld - Counter reload register - UNION_RLD - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - XRLD - timeout counter extended reload point, counter will reload to xsta after reach this point - 28 - 4 - read-write - - - RLD - pwm timer counter reload value - 4 - 24 - read-write - - - - - 24 - 0x4 - 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23 - CMP[%s] - no description available - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - XCMP - extended counter compare value - 28 - 4 - read-write - - - CMP - clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, -and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. - 4 - 24 - read-write - - - CMPHLF - half clock counter compare value - 3 - 1 - read-write - - - CMPJIT - jitter counter compare value - 0 - 3 - read-write - - - - - frcmd - Force output mode register - 0x78 - 32 - 0x00000000 - 0x0000FFFF - - - FRCMD - 2bit for each PWM output channel (0-7); -00: force output 0 -01: force output 1 -10: output highz -11: no force - 0 - 16 - read-write - - - - - shlk - Shadow registers lock register - 0x7c - 32 - 0x00000000 - 0x80000000 - - - SHLK - write 1 to lock all shawdow register, write access is not permitted - 31 - 1 - read-write - - - - - 24 - 0x4 - 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23 - CHCFG[%s] - no description available - 0x80 - 32 - 0x00000000 - 0xFFFF0003 - - - CMPSELEND - assign the last comparator for this output channel - 24 - 5 - read-write - - - CMPSELBEG - assign the first comparator for this output channel - 16 - 5 - read-write - - - OUTPOL - output polarity, set to 1 will invert the output - 1 - 1 - read-write - - - - - gcr - Global control register - 0xf0 - 32 - 0x00000000 - 0xFDFFFFE7 - - - FAULTI3EN - 1- enable the internal fault input 3 - 31 - 1 - read-write - - - FAULTI2EN - 1- enable the internal fault input 2 - 30 - 1 - read-write - - - FAULTI1EN - 1- enable the internal fault input 1 - 29 - 1 - read-write - - - FAULTI0EN - 1- enable the internal fault input 0 - 28 - 1 - read-write - - - DEBUGFAULT - 1- enable debug mode output protection - 27 - 1 - read-write - - - FRCPOL - polarity of input pwm_force, -1- active low -0- active high - 26 - 1 - read-write - - - HWSHDWEDG - When hardware event is selected as shawdow register effective time and the select comparator is configured as input capture mode. -This bit assign its which edge is used as compare shadow register hardware load event. -1- Falling edge -0- Rising edge - 24 - 1 - read-write - - - CMPSHDWSEL - This bitfield select one of the comparators as hardware event time to load comparator shadow registers - 19 - 5 - read-write - - - FAULTRECEDG - When hardware load is selected as output fault recover trigger and the selected channel is capture mode. -This bit assign its effective edge of fault recover trigger. -1- Falling edge -0- Rising edge - 18 - 1 - read-write - - - FAULTRECHWSEL - Selec one of the 24 comparators as fault output recover trigger. - 13 - 5 - read-write - - - FAULTE1EN - 1- enable the external fault input 1 - 12 - 1 - read-write - - - FAULTE0EN - 1- enable the external fault input 0 - 11 - 1 - read-write - - - FAULTEXPOL - external fault polarity -1-active low -0-active high - 9 - 2 - read-write - - - RLDSYNCEN - 1- pwm timer counter reset to reload value (rld) by synci is enabled - 8 - 1 - read-write - - - CEN - 1- enable the pwm timer counter -0- stop the pwm timer counter - 7 - 1 - read-write - - - FAULTCLR - 1- Write 1 to clear the fault condition. The output will recover if FAULTRECTIME is set to 2b'11. -User should write 1 to this bit after the active FAULT signal de-assert and before it re-assert again. - 6 - 1 - read-write - - - XRLDSYNCEN - 1- pwm timer extended counter (xcnt) reset to extended reload value (xrld) by synci is enabled - 5 - 1 - read-write - - - FRCTIME - This bit field select the force effective time -00: force immediately -01: force at main counter reload time -10: force at FRCSYNCI -11: no force - 1 - 2 - write-only - - - SWFRC - 1- write 1 to enable software force, if the frcsrcsel is set to 0, force will take effect - 0 - 1 - read-write - - - - - shcr - Shadow register control register - 0xf4 - 32 - 0x00000000 - 0x00001FFF - - - FRCSHDWSEL - This bitfield select one of the comparators as hardware event time to load FRCMD shadow registers - 8 - 5 - read-write - - - CNTSHDWSEL - This bitfield select one of the comparators as hardware event time to load the counter related shadow registers (STA and RLD) - 3 - 5 - read-write - - - CNTSHDWUPT - This bitfield select when the counter related shadow registers (STA and RLD) will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. - The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 1 - 2 - read-write - - - SHLKEN - 1- enable shadow registers lock feature, -0- disable shadow registers lock, shlk bit will always be 0 - 0 - 1 - read-write - - - - - 24 - 0x4 - 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23 - CAPPOS[%s] - no description available - 0x100 - 32 - 0x00000000 - 0xFFFFFFF0 - - - CAPPOS - counter value captured at input posedge - 4 - 28 - read-only - - - - - cnt - Counter - 0x170 - 32 - 0x00000000 - 0xFFFFFFFF - - - XCNT - current extended counter value - 28 - 4 - read-only - - - CNT - current clock counter value - 4 - 24 - read-only - - - - - 24 - 0x4 - 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23 - CAPNEG[%s] - no description available - 0x180 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPNEG - counter value captured at input signal falling edge - 0 - 32 - read-only - - - - - cntcopy - Counter copy - 0x1f0 - 32 - 0x00000000 - 0xFFFFFFFF - - - XCNT - current extended counter value - 28 - 4 - read-only - - - CNT - current clock counter value - 4 - 24 - read-only - - - - - 8 - 0x4 - 0,1,2,3,4,5,6,7 - PWMCFG[%s] - no description available - 0x200 - 32 - 0x00000000 - 0x1FFFFFFF - - - OEN - PWM output enable -1- output is enabled -0- output is disabled - 28 - 1 - read-write - - - FRCSHDWUPT - This bitfield select when the FRCMD shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. - The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 26 - 2 - read-write - - - FAULTMODE - This bitfield defines the PWM output status when fault condition happen -00: force output 0 -01: force output 1 -1x: output highz - 24 - 2 - read-write - - - FAULTRECTIME - This bitfield select when to recover PWM output after fault condition removed. -00: immediately -01: after pwm timer counter reload time -10: after hardware event assert, user can select one of the comparators to generate this hardware event. - The comparator can be either output compare mode or input capture mode. -11: after software write faultclr bit in GCR register - 22 - 2 - read-write - - - FRCSRCSEL - Select sources for force output -0- force output is enabled when FRCI assert -1- force output is enabled by software write swfrc to 1 - 21 - 1 - read-write - - - PAIR - 1- PWM output is in pair mode. Note the two PWM outputs need to be both set to pair mode. -0- PWM output is in indepandent mode. - 20 - 1 - read-write - - - DEADAREA - This bitfield define the PWM pair deadarea length. The unit is 0.5 cycle. The minimum length of deadarea is 1 cycle. -Note: user should configure pair bit and this bitfield before PWM output is enabled. - 0 - 20 - read-write - - - - - sr - Status register - 0x220 - 32 - 0x00000000 - 0x0FFFFFFF - - - FAULTF - fault condition flag - 27 - 1 - write-only - - - XRLDF - extended reload flag, this flag set when xcnt count to xrld value or when SYNCI assert - 26 - 1 - write-only - - - HALFRLDF - half reload flag, this flag set when cnt count to rld/2 - 25 - 1 - write-only - - - RLDF - reload flag, this flag set when cnt count to rld value or when SYNCI assert - 24 - 1 - write-only - - - CMPFX - comparator output compare or input capture flag - 0 - 24 - write-only - - - - - irqen - Interrupt request enable register - 0x224 - 32 - 0x00000000 - 0x0FFFFFFF - - - FAULTIRQE - fault condition interrupt enable - 27 - 1 - read-write - - - XRLDIRQE - extended reload flag interrupt enable - 26 - 1 - read-write - - - HALFRLDIRQE - half reload flag interrupt enable - 25 - 1 - read-write - - - RLDIRQE - reload flag interrupt enable - 24 - 1 - read-write - - - CMPIRQEX - comparator output compare or input capture flag interrupt enable - 0 - 24 - read-write - - - - - dmaen - DMA request enable register - 0x22c - 32 - 0x00000000 - 0x0FFFFFFF - - - FAULTEN - fault condition DMA request enable - 27 - 1 - read-write - - - XRLDEN - extended reload flag DMA request enable - 26 - 1 - read-write - - - HALFRLDEN - half reload flag DMA request enable - 25 - 1 - read-write - - - RLDEN - reload flag DMA request enable - 24 - 1 - read-write - - - CMPENX - comparator output compare or input capture flag DMA request enable - 0 - 24 - read-write - - - - - 24 - 0x4 - cmpcfg0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23 - CMPCFG[%s] - no description available - 0x230 - 32 - 0x00000000 - 0x000000FF - - - XCNTCMPEN - This bitfield enable the comparator to compare xcmp with xcnt. - 4 - 4 - read-write - - - CMPSHDWUPT - This bitfield select when the comparator shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. - The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 2 - 2 - read-write - - - CMPMODE - comparator mode -0- output compare mode -1- input capture mode - 1 - 1 - read-write - - - - - - - PWM1 - PWM1 - PWM - 0xf0210000 - - - PWM2 - PWM2 - PWM - 0xf0220000 - - - PWM3 - PWM3 - PWM - 0xf0230000 - - - HALL0 - HALL0 - HALL - 0xf0204000 - - 0x0 - 0x88 - registers - - - - cr - Control Register - 0x0 - 32 - 0x00000000 - 0x8001083F - - - READ - 1- load ucnt, vcnt, wcnt and tmrcnt into their read registers. Hardware auto-clear; read as 0 - 31 - 1 - write-only - - - SNAPEN - 1- load ucnt, vcnt, wcnt and tmrcnt into their snap registers when snapi input assert - 11 - 1 - read-write - - - RSTCNT - set to reset all counter and related snapshots - 4 - 1 - read-write - - - - - phcfg - Phase configure register - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - DLYSEL - This bit select delay start time: -1- start counting delay after pre-trigger -0- start counting delay after u,v,w toggle - 31 - 1 - read-write - - - DLYCNT - delay clock cycles number - 0 - 24 - read-write - - - - - wdgcfg - Watchdog configure register - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - WDGEN - 1- enable wdog counter - 31 - 1 - read-write - - - WDGTO - watch dog timeout value - 0 - 31 - read-write - - - - - uvwcfg - U,V,W configure register - 0xc - 32 - 0x00000000 - 0x07FFFFFF - - - PRECNT - the clock cycle number which the pre flag will set before the next uvw transition - 0 - 24 - read-write - - - - - trgoen - Trigger output enable register - 0x10 - 32 - 0x00000000 - 0xFFE00000 - - - WDGEN - 1- enable trigger output when wdg flag set - 31 - 1 - read-write - - - PHUPTEN - 1- enable trigger output when phupt flag set - 30 - 1 - read-write - - - PHPREEN - 1- enable trigger output when phpre flag set - 29 - 1 - read-write - - - PHDLYEN - 1- enable trigger output when phdly flag set - 28 - 1 - read-write - - - UFEN - 1- enable trigger output when u flag set - 23 - 1 - read-write - - - VFEN - 1- enable trigger output when v flag set - 22 - 1 - read-write - - - WFEN - 1- enable trigger output when w flag set - 21 - 1 - read-write - - - - - readen - Read event enable register - 0x14 - 32 - 0x00000000 - 0xFFE00000 - - - WDGEN - 1- load counters to their read registers when wdg flag set - 31 - 1 - read-write - - - PHUPTEN - 1- load counters to their read registers when phupt flag set - 30 - 1 - read-write - - - PHPREEN - 1- load counters to their read registers when phpre flag set - 29 - 1 - read-write - - - PHDLYEN - 1- load counters to their read registers when phdly flag set - 28 - 1 - read-write - - - UFEN - 1- load counters to their read registers when u flag set - 23 - 1 - read-write - - - VFEN - 1- load counters to their read registers when v flag set - 22 - 1 - read-write - - - WFEN - 1- load counters to their read registers when w flag set - 21 - 1 - read-write - - - - - dmaen - DMA enable register - 0x24 - 32 - 0x00000000 - 0xFFE00000 - - - WDGEN - 1- generate dma request when wdg flag set - 31 - 1 - read-write - - - PHUPTEN - 1- generate dma request when phupt flag set - 30 - 1 - read-write - - - PHPREEN - 1- generate dma request when phpre flag set - 29 - 1 - read-write - - - PHDLYEN - 1- generate dma request when phdly flag set - 28 - 1 - read-write - - - UFEN - 1- generate dma request when u flag set - 23 - 1 - read-write - - - VFEN - 1- generate dma request when v flag set - 22 - 1 - read-write - - - WFEN - 1- generate dma request when w flag set - 21 - 1 - read-write - - - - - sr - Status register - 0x28 - 32 - 0x00000000 - 0xFFE00000 - - - WDGF - watchdog count timeout flag - 31 - 1 - read-write - - - PHUPTF - phase update flag, will set when any of u, v, w signal toggle - 30 - 1 - read-write - - - PHPREF - phase update pre flag, will set PRECNT cycles before any of u, v, w signal toggle - 29 - 1 - read-write - - - PHDLYF - phase update delay flag, will set DLYCNT cycles after any of u, v, w signal toggle or after the phpre flag depands on DLYSEL setting - 28 - 1 - read-write - - - UF - u flag, will set when u signal toggle - 23 - 1 - read-write - - - VF - v flag, will set when v signal toggle - 22 - 1 - read-write - - - WF - w flag, will set when w signal toggle - 21 - 1 - read-write - - - - - irqen - Interrupt request enable register - 0x2c - 32 - 0x00000000 - 0xFFE00000 - - - WDGIE - 1- generate interrupt request when wdg flag set - 31 - 1 - read-write - - - PHUPTIE - 1- generate interrupt request when phupt flag set - 30 - 1 - read-write - - - PHPREIE - 1- generate interrupt request when phpre flag set - 29 - 1 - read-write - - - PHDLYIE - 1- generate interrupt request when phdly flag set - 28 - 1 - read-write - - - UFIE - 1- generate interrupt request when u flag set - 23 - 1 - read-write - - - VFIE - 1- generate interrupt request when v flag set - 22 - 1 - read-write - - - WFIE - 1- generate interrupt request when w flag set - 21 - 1 - read-write - - - - - 4 - 0x10 - current,read,snap0,snap1 - COUNT[%s] - no description available - 0x30 - - w - W counter - 0x0 - 32 - 0x00000000 - 0x0FFFFFFF - - - WCNT - wcnt counter - 0 - 28 - read-only - - - - - v - V counter - 0x4 - 32 - 0x00000000 - 0xCFFFFFFF - - - VCNT - vcnt counter - 0 - 28 - read-only - - - - - u - U counter - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIR - 1- reverse rotation -0- forward rotation - 31 - 1 - read-only - - - USTAT - this bit indicate U state - 30 - 1 - read-only - - - VSTAT - this bit indicate V state - 29 - 1 - read-only - - - WSTAT - this bit indicate W state - 28 - 1 - read-only - - - UCNT - ucnt counter - 0 - 28 - read-only - - - - - tmr - Timer counter - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - TIMER - 32 bit free run timer - 0 - 32 - read-only - - - - - - 3 - 0x8 - u,v,w - HIS[%s] - no description available - 0x70 - - his0 - history register 0 - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - UHIS0 - copy of ucnt when u signal transition from 0 to 1 - 0 - 32 - read-only - - - - - his1 - history register 1 - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - UHIS1 - copy of ucnt when u signal transition from 1 to 0 - 0 - 32 - read-only - - - - - - - - HALL1 - HALL1 - HALL - 0xf0214000 - - - HALL2 - HALL2 - HALL - 0xf0224000 - - - HALL3 - HALL3 - HALL - 0xf0234000 - - - QEI0 - QEI0 - QEI - 0xf0208000 - - 0x0 - 0x80 - registers - - - - cr - Control register - 0x0 - 32 - 0x00000000 - 0x80077F3F - - - READ - 1- load phcnt, zcnt, spdcnt and tmrcnt into their read registers. Hardware auto-clear; read as 0 - 31 - 1 - write-only - - - HRSTSPD - 1- reset spdcnt when H assert - 18 - 1 - read-write - - - HRSTPH - 1- reset phcnt when H assert - 17 - 1 - read-write - - - HRSTZ - 1- reset zcnt when H assert - 16 - 1 - read-write - - - PAUSESPD - 1- pause spdcnt when PAUSE assert - 14 - 1 - read-write - - - PAUSEPH - 1- pause phcnt when PAUSE assert - 13 - 1 - read-write - - - PAUSEZ - 1- pause zcnt when PAUSE assert - 12 - 1 - read-write - - - HRDIR1 - 1- HOMEF will set at H rising edge when dir == 1 (negative rotation direction) - 11 - 1 - read-write - - - HRDIR0 - 1- HOMEF will set at H rising edge when dir == 0 (positive rotation direction) - 10 - 1 - read-write - - - HFDIR1 - 1- HOMEF will set at H falling edge when dir == 1 (negative rotation direction) - 9 - 1 - read-write - - - HFDIR0 - 1- HOMEF will set at H falling edge when dir == 1 (positive rotation direction) - 8 - 1 - read-write - - - SNAPEN - 1- load phcnt, zcnt, spdcnt and tmrcnt into their snap registers when snapi input assert - 5 - 1 - read-write - - - RSTCNT - 1- reset zcnt, spdcnt and tmrcnt to 0. reset phcnt to phidx - 4 - 1 - read-write - - - ENCTYP - 00-abz; 01-pd; 10-ud; 11-reserved - 0 - 2 - read-write - - - - - phcfg - Phase configure register - 0x4 - 32 - 0x00000000 - 0x007FFFFF - - - ZCNTCFG - 1- zcnt will increment when phcnt upcount to phmax, decrement when phcnt downcount to 0 -0- zcnt will increment or decrement when Z input assert - 22 - 1 - read-write - - - PHCALIZ - 1- phcnt will set to phidx when Z input assert - 21 - 1 - read-write - - - PHMAX - maximum phcnt number, phcnt will rollover to 0 when it upcount to phmax - 0 - 21 - read-write - - - - - wdgcfg - Watchdog configure register - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - WDGEN - 1- enable wdog counter - 31 - 1 - read-write - - - WDGTO - watch dog timeout value - 0 - 31 - read-write - - - - - phidx - Phase index register - 0xc - 32 - 0x00000000 - 0x001FFFFF - - - PHIDX - phcnt reset value, phcnt will reset to phidx when phcaliz set to 1 - 0 - 21 - read-write - - - - - trgoen - Tigger output enable register - 0x10 - 32 - 0x00000000 - 0xF0000000 - - - WDGFEN - 1- enable trigger output when wdg flag set - 31 - 1 - read-write - - - HOMEFEN - 1- enable trigger output when homef flag set - 30 - 1 - read-write - - - POSCMPFEN - 1- enable trigger output when poscmpf flag set - 29 - 1 - read-write - - - ZPHFEN - 1- enable trigger output when zphf flag set - 28 - 1 - read-write - - - - - readen - Read event enable register - 0x14 - 32 - 0x00000000 - 0xF0000000 - - - WDGFEN - 1- load counters to their read registers when wdg flag set - 31 - 1 - read-write - - - HOMEFEN - 1- load counters to their read registers when homef flag set - 30 - 1 - read-write - - - POSCMPFEN - 1- load counters to their read registers when poscmpf flag set - 29 - 1 - read-write - - - ZPHFEN - 1- load counters to their read registers when zphf flag set - 28 - 1 - read-write - - - - - zcmp - Z comparator - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - ZCMP - zcnt postion compare value - 0 - 32 - read-write - - - - - phcmp - Phase comparator - 0x1c - 32 - 0x00000000 - 0xE01FFFFF - - - ZCMPDIS - 1- postion compare not include zcnt - 31 - 1 - read-write - - - DIRCMPDIS - 1- postion compare not include rotation direction - 30 - 1 - read-write - - - DIRCMP - 0- position compare need positive rotation -1- position compare need negative rotation - 29 - 1 - read-write - - - PHCMP - phcnt position compare value - 0 - 21 - read-write - - - - - spdcmp - Speed comparator - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - SPDCMP - spdcnt position compare value - 0 - 32 - read-write - - - - - dmaen - DMA request enable register - 0x24 - 32 - 0x00000000 - 0xF0000000 - - - WDGFEN - 1- generate dma request when wdg flag set - 31 - 1 - read-write - - - HOMEFEN - 1- generate dma request when homef flag set - 30 - 1 - read-write - - - POSCMPFEN - 1- generate dma request when poscmpf flag set - 29 - 1 - read-write - - - ZPHFEN - 1- generate dma request when zphf flag set - 28 - 1 - read-write - - - - - sr - Status register - 0x28 - 32 - 0x00000000 - 0xF0000000 - - - WDGF - watchdog flag - 31 - 1 - read-write - - - HOMEF - home flag - 30 - 1 - read-write - - - POSCMPF - postion compare match flag - 29 - 1 - read-write - - - ZPHF - z input flag - 28 - 1 - read-write - - - - - irqen - Interrupt request register - 0x2c - 32 - 0x00000000 - 0xF0000000 - - - WDGIE - 1- generate interrupt when wdg flag set - 31 - 1 - read-write - - - HOMEIE - 1- generate interrupt when homef flag set - 30 - 1 - read-write - - - POSCMPIE - 1- generate interrupt when poscmpf flag set - 29 - 1 - read-write - - - ZPHIE - 1- generate interrupt when zphf flag set - 28 - 1 - read-write - - - - - 4 - 0x10 - current,read,snap0,snap1 - COUNT[%s] - no description available - 0x30 - - z - Z counter - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - ZCNT - zcnt value - 0 - 32 - read-write - - - - - ph - Phase counter - 0x4 - 32 - 0x00000000 - 0x461FFFFF - - - DIR - 1- reverse rotation -0- forward rotation - 30 - 1 - read-only - - - ASTAT - 1- a input is high -0- a input is low - 26 - 1 - read-only - - - BSTAT - 1- b input is high -0- b input is low - 25 - 1 - read-only - - - PHCNT - phcnt value - 0 - 21 - read-only - - - - - spd - Speed counter - 0x8 - 32 - 0x00000000 - 0xEFFFFFFF - - - DIR - 1- reverse rotation -0- forward rotation - 31 - 1 - read-only - - - ASTAT - 1- a input is high -0- a input is low - 30 - 1 - read-only - - - BSTAT - 1- b input is high -0- b input is low - 29 - 1 - read-write - - - SPDCNT - spdcnt value - 0 - 28 - read-only - - - - - tmr - Timer counter - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - TMRCNT - 32 bit free run timer - 0 - 32 - read-only - - - - - - 4 - 0x4 - spdhis0,spdhis1,spdhis2,spdhis3 - SPDHIS[%s] - no description available - 0x70 - 32 - 0x00000000 - 0xFFFFFFFF - - - SPDHIS0 - copy of spdcnt, load from spdcnt after any transition from a = low, b = low - 0 - 32 - read-only - - - - - - - QEI1 - QEI1 - QEI - 0xf0218000 - - - QEI2 - QEI2 - QEI - 0xf0228000 - - - QEI3 - QEI3 - QEI - 0xf0238000 - - - TRGM0 - TRGM0 - TRGM - 0xf020c000 - - 0x0 - 0x404 - registers - - - - 20 - 0x4 - PWM_IN0,PWM_IN1,PWM_IN2,PWM_IN3,PWM_IN4,PWM_IN5,PWM_IN6,PWM_IN7,TRGM_IN0,TRGM_IN1,TRGM_IN2,TRGM_IN3,TRGM_IN4,TRGM_IN5,TRGM_IN6,TRGM_IN7,TRGM_IN8,TRGM_IN9,TRGM_IN10,TRGM_IN11 - FILTCFG[%s] - no description available - 0x0 - 32 - 0x00000000 - 0x0001FFFF - - - OUTINV - 1- Filter will invert the output -0- Filter will not invert the output - 16 - 1 - read-write - - - MODE - This bitfields defines the filter mode -000-bypass; -100-rapid change mode; -101-delay filter mode; -110-stalbe low mode; -111-stable high mode - 13 - 3 - read-write - - - SYNCEN - set to enable sychronization input signal with TRGM clock - 12 - 1 - read-write - - - FILTLEN - This bitfields defines the filter counter length. - 0 - 12 - read-write - - - - - 64 - 0x4 - TRGM_OUT0,TRGM_OUT1,TRGM_OUT2,TRGM_OUT3,TRGM_OUT4,TRGM_OUT5,TRGM_OUT6,TRGM_OUT7,TRGM_OUT8,TRGM_OUT9,TRGM_OUT10,TRGM_OUT11,TRGM_OUTX0,TRGM_OUTX1,PWM_SYNCI,PWM_FRCI,PWM_FRCSYNCI,PWM_SHRLDSYNCI,PWM_FAULTI0,PWM_FAULTI1,PWM_FAULTI2,PWM_FAULTI3,PWM_IN8,PWM_IN9,PWM_IN10,PWM_IN11,PWM_IN12,PWM_IN13,PWM_IN14,PWM_IN15,PWM_IN16,PWM_IN17,PWM_IN18,PWM_IN19,PWM_IN20,PWM_IN21,PWM_IN22,PWM_IN23,QEI_A,QEI_B,QEI_Z,QEI_H,QEI_PAUSE,QEI_SNAPI,HALL_U,HALL_V,HALL_W,HALL_SNAPI,ADC0_STRGI,ADC1_STRGI,ADC2_STRGI,ADC3_STRGI,ADCx_PTRGI0A,ADCx_PTRGI0B,ADCx_PTRGI0C,GPTMRa_SYNCI,GPTMRa_IN2,GPTMRa_IN3,GPTMRb_SYNCI,GPTMRb_IN2,GPTMRb_IN3,CMPx_WIN,CAN_PTPC0_CAP,CAN_PTPC1_CAP - TRGOCFG[%s] - no description available - 0x100 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - 4 - 0x4 - 0,1,2,3 - DMACFG[%s] - no description available - 0x200 - 32 - 0x00000000 - 0x0000001F - - - DMASRCSEL - This field selects one of the DMA requests as the DMA request output. - 0 - 5 - read-write - - - - - GCR - General Control Register - 0x400 - 32 - 0x00000000 - 0x00000FFF - - - TRGOPEN - The bitfield enable the TRGM outputs. - 0 - 12 - read-write - - - - - - - TRGM1 - TRGM1 - TRGM - 0xf021c000 - - - TRGM2 - TRGM2 - TRGM - 0xf022c000 - - - TRGM3 - TRGM3 - TRGM - 0xf023c000 - - - SYNT - SYNT - SYNT - 0xf0240000 - - 0x0 - 0x30 - registers - - - - gcr - Global control register - 0x0 - 32 - 0x00000000 - 0x00000003 - - - CRST - 1- Reset counter - 1 - 1 - read-write - - - CEN - 1- Enable counter - 0 - 1 - read-write - - - - - rld - Counter reload register - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - RLD - counter reload value - 0 - 32 - read-write - - - - - cnt - Counter - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - CNT - counter - 0 - 32 - read-only - - - - - 4 - 0x4 - 0,1,2,3 - CMP[%s] - no description available - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - CMP - comparator value, the output will assert when counter count to this value - 0 - 32 - read-write - - - - - - - LCDC - LCDC - LCDC - 0xf1000000 - - 0x0 - 0x404 - registers - - - - CTRL - Control Register - 0x0 - 32 - 0x00000000 - 0xFFF0001F - - - SW_RST - Software reset, high active. When write 1 ,all internal logical will be reset. -0b - No action -1b - All LCDC internal registers are forced into their reset state. Interface registers are not affected. - 31 - 1 - read-write - - - DISP_ON - Display panel On/Off mode. -0b - Display Off. -1b - Display On. -Display can be set off at any time, but it can only be set on after VS_BLANK status is asserted. -So a good procedure to stop and turn on the display is: -1) clr VS_BLANK status -2) assert software reset -3) de-assert software reset -4) set display off -5) check VS_BLANK status until it is asserted, -6)reset the module, change settings -7) set display on - 30 - 1 - read-write - - - LINE_PATTERN - LCDIF line output order. -000b - RGB. -001b - RBG. -010b - GBR. -011b - GRB. -100b - BRG. -101b - BGR. - 27 - 3 - read-write - - - DISP_MODE - LCDIF operating mode. -00b - Normal mode. Panel content controlled by layer configuration. -01b - Test Mode1.(BGND Color Display) -10b - Test Mode2.(Column Color Bar) -11b - Test Mode3.(Row Color Bar) - 25 - 2 - read-write - - - BGDCL4CLR - background color for clear mode when the alpha channel is 0 - 24 - 1 - read-write - - - ARQOS - ARQOS for bus fabric arbitration - 20 - 4 - read-write - - - INV_PXDATA - Indicates if value at the output (pixel data output) needs to be negated. -0b - Output is to remain same as the data inside memory -1b - Output to be negated from the data inside memory - 4 - 1 - read-write - - - INV_PXCLK - Polarity change of Pixel Clock. -0b - LCDC outputs data on the rising edge, and Display samples data on the falling edge -1b - LCDC outputs data on the falling edge, Display samples data on the rising edge - 3 - 1 - read-write - - - INV_HREF - Polarity of HREF -0b - HREF signal active HIGH, indicating active pixel data -1b - HREF signal active LOW - 2 - 1 - read-write - - - INV_VSYNC - Polarity of VSYNC -0b - VSYNC signal active HIGH -1b - VSYNC signal active LOW - 1 - 1 - read-write - - - INV_HSYNC - Polarity of HSYNC -0b - HSYNC signal active HIGH -1b - HSYNC signal active LOW - 0 - 1 - read-write - - - - - BGND_CL - Background Color Register - 0x4 - 32 - 0x00000000 - 0x00FFFFFF - - - R - Red component of the default color displayed in the sectors where no layer is active. - 16 - 8 - read-write - - - G - Green component of the default color displayed in the sectors where no layer is active. - 8 - 8 - read-write - - - B - Blue component of the default color displayed in the sectors where no layer is active. - 0 - 8 - read-write - - - - - DISP_WN_SIZE - Display Window Size Register - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - Y - Sets the display size vertical resolution in pixels. - 16 - 12 - read-write - - - X - Sets the display size horizontal resolution in pixels. - 0 - 12 - read-write - - - - - HSYNC_PARA - HSYNC Config Register - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - FP - HSYNC front-porch pulse width (in pixel clock cycles). If zero, indicates no front-porch for HSYNC - 22 - 9 - read-write - - - BP - HSYNC back-porch pulse width (in pixel clock cycles). If zero, indicates no back-porch for HSYNC - 11 - 9 - read-write - - - PW - HSYNC active pulse width (in pixel clock cycles). Pulse width has a minimum value of 1. - 0 - 9 - read-write - - - - - VSYNC_PARA - VSYNC Config Register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - FP - VSYNC front-porch pulse width (in horizontal line cycles). If zero, means no front-porch for VSYNC - 22 - 9 - read-write - - - BP - VSYNC back-porch pulse width (in horizontal line cycles). If zero, means no back-porch for VSYNC - 11 - 9 - read-write - - - PW - VSYNC active pulse width (in horizontal line cycles). Pulse width has a minimum value of 1. - 0 - 9 - read-write - - - - - DMA_ST - DMA Status Register - 0x14 - 32 - 0x00000000 - 0xFFFFFF00 - - - DMA_ERR - plane n axi error. W1C. - 24 - 8 - write-only - - - DMA1_DONE - Plane n frame 1 dma done. W1C. - 16 - 8 - write-only - - - DMA0_DONE - Plane n frame 0 dma done. W1C. - 8 - 8 - write-only - - - - - ST - Status Register - 0x18 - 32 - 0x00000000 - 0x0000000F - - - URGENT_UNDERRUN - Asserted when the output buffer urgent underrun condition encountered - 3 - 1 - write-only - - - VS_BLANK - Asserted when in vertical blanking period. At the start of VSYNC - 2 - 1 - write-only - - - UNDERRUN - Asserted when the output buffer underrun condition encountered - 1 - 1 - write-only - - - VSYNC - Asserted when in vertical blanking period. At the end of VSYNC - 0 - 1 - write-only - - - - - INT_EN - Interrupt Enable Register - 0x1c - 32 - 0x00000000 - 0xFFFFFF0F - - - DMA_ERR - Interrupt enable for DMA error - 24 - 8 - read-write - - - DMA_DONE - Interrupt enable for DMA done - 16 - 8 - read-write - - - URGENT_UNDERRUN - Asserted when the output buffer urgent underrun condition encountered - 3 - 1 - read-write - - - VS_BLANK - Interrupt enable for start of sof - 2 - 1 - read-write - - - UNDERRUN - Interrupt enable for underrun - 1 - 1 - read-write - - - VSYNC - Interrupt enable for end of sof - 0 - 1 - read-write - - - - - TXFIFO - TX FIFO Register - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - THRSH - Threshold to start the lcd raster (0--0x7F) - 0 - 8 - read-write - - - - - 8 - 0x40 - 0,1,2,3,4,5,6,7 - LAYER[%s] - no description available - 0x200 - - LAYCTRL - Layer Control Register - 0x0 - 32 - 0x00000000 - 0x000FFFFD - - - PACK_DIR - The byte sequence of the 4 bytes in a 32-bit word. -1: {A0, A1, A2, A3} byte re-ordered. -0: {A3, A2, A1, A0} the normal case with no byte re-order - 19 - 1 - read-write - - - SHADOW_LOAD_EN - Shadow Load Enable -The SHADOW_LOAD_EN bit is written to 1 by software after all DMA control registers are written. If set to 1, shadowed control registers are updated to the active control registers on internal logical VSYNC of next frame. If set to 0, shadowed control registers are not loaded into the active control registers. The previous active control register settings will be used to process the next frame. Hardware will automatically clear this bit, when the shadow registers are loaded to the active control regsisters. - 16 - 1 - read-write - - - YUV_FORMAT - The YUV422 input format selection. -00b - The YVYU422 8bit sequence is U1,Y1,V1,Y2 -01b - The YVYU422 8bit sequence is V1,Y1,U1,Y2 -10b - The YVYU422 8bit sequence is Y1,U1,Y2,V1 -11b - The YVYU422 8bit sequence is Y1,V1,Y2,U1 -If not YUV422 mode, -FORMAT[0]: asserted to exchange sequence inside the bytes. Org [15:8]-->New[8:15], Org [7:0]-->New[0:7]. (First exchange) -FORMAT[1]: asserted to exchange the sequence of the odd and even 8 bits. Org Even [7:0]-->New[15:8], Org Odd [15:8]-->New[7:0]. (Second exchange) - 14 - 2 - read-write - - - PIXFORMAT - Layer encoding format (bit per pixel) -0000b - 1 bpp (pixel width must be multiples of 32), pixel sequence is from LSB to MSB in 32b word. -0001b - 2 bpp (pixel width must be multiples of 16), pixel sequence is from LSB to MSB in 32b word. -0010b - 4 bpp (pixel width must be multiples of 8), pixel sequence is from LSB to MSB in 32b word. -0011b - 8 bpp (pixel width must be multiples of 4), pixel sequence is from LSB to MSB in 32b word. -0100b - 16 bpp (RGB565), the low byte contains the full R component. -0111b - YCbCr422 (Only layer 0/1 can support this format), byte sequence determined by LAYCTRL[YUV_FORMAT] -1001b - 32 bpp (ARGB8888), byte sequence as B,G,R,A -1011b - Y8 (pixel width must be multiples of 4), byte sequence as Y1,Y2,Y3,Y4 - 10 - 4 - read-write - - - LOCALPHA_OP - The usage of the LOCALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) -0: the LOCALPHA[7:0] is invalid, use the alpha value from the data stream -1: the LOCALPHA[7:0] is used to override the alpha value in the data stream (useful when the data stream has no alpha info) -2: the LOCALPHA[7:0] is used to scale the alpha value from the data stream -Others: Reserved - 8 - 2 - read-write - - - INALPHA_OP - The usage of the INALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) -0: the INALPHA[7:0] is invalid, use the alpha value from previous pipeline -1: the INALPHA[7:0] is used to override the alpha value from previous pipeline. (useful when the corresponding data stream has no alpha info) -2: the INALPHA[7:0] is used to scale the alpha value from previous pipeline -Others: Reserved - 6 - 2 - read-write - - - AB_MODE - Alpha Blending Mode -0: SKBlendMode_Clear; -1: SKBlendMode_Src ; -2: SKBlendMode_Dst -3: SKBlendMode_SrcOver -4: SKBlendMode_DstOver -5: SKBlendMode_SrcIn -6: SKBlendMode_DstIn -7: SKBlendMode_SrcOut -8: SKBlendMode_DstOut -9: SKBlendMode_SrcATop -10: SKBlendMode_DstATop -11: SKBlendMode_Xor -12: SKBlendMode_Plus (The conventional blending mode) -13: SKBlendMode_Modulate -14: SRC org -15: DST org -Others: Reserved. - 2 - 4 - read-write - - - EN - Asserted when the layer is enabled. If this layer is not enabled, it means a bypassing plane. - 0 - 1 - read-write - - - - - ALPHAS - Layer Alpha Register - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCD - The system alpha value for the data stream of current layer stream (SRC) - 8 - 8 - read-write - - - IND - The system alpha value for the input stream from previous stage (DST) - 0 - 8 - read-write - - - - - LAYSIZE - Layer Size Register - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - HEIGHT - Height of the layer in pixels - 16 - 12 - read-write - - - WIDTH - Width of the layer in pixels (Note: not actual width-1) -The layer width must be in multiples of the number of pixels that can be stored in 32 bits, and therefore differs depending on color encoding. For example, if 2 bits per pixel format is used, then the layer width must be configured in multiples of 16. - 0 - 12 - read-write - - - - - LAYPOS - Layer Position Register - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - Y - The vertical position of top row of the layer, where 0 is the top row of the panel, positive values are below the top row of the panel. - 16 - 16 - read-write - - - X - The horizontal position of left-hand column of the layer, where 0 is the left-hand column of the panel, positive values are to the right the left-hand column of the panel. - 0 - 16 - read-write - - - - - START0 - Layer Buffer Pointer Register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR0 - Input buffer Start address 0 - 0 - 32 - read-write - - - - - LINECFG - Layer Bus Config Register - 0x18 - 32 - 0x00000000 - 0xE0FFFFFF - - - MPT_SIZE - Maximal Per Transfer Data Size: -0: 64 bytes -1: 128 bytes -2: 256 bytes -3: 512 bytes -4: 1024 bytes - 29 - 3 - read-write - - - MAX_OT - the number of outstanding axi read transactions. -If zero, it means max 8. - 21 - 3 - read-write - - - PITCH - Number of bytes between 2 vertically adjacent pixels in system memory. Byte granularity is supported, but SW should align to 64B boundary. - 0 - 16 - read-write - - - - - BG_CL - Layer Background Color Register - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - ARGB - ARGB8888. It is only useful in the last active stage in the pipeline. - 0 - 32 - read-write - - - - - CSC_COEF0 - Layer Color Space Conversion Config Register 0 - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - YCBCR_MODE - This bit changes the behavior when performing U/V converting. -0b - Converting YUV to RGB data -1b - Converting YCbCr to RGB data - 31 - 1 - read-write - - - ENABLE - Enable the CSC unit in the LCDC plane data path. -0b - The CSC is bypassed and the input pixels are RGB data already -1b - The CSC is enabled and the pixels will be converted to RGB data -This bit will be shadowed. - 30 - 1 - read-write - - - C0 - Two's compliment Y multiplier coefficient C0. YUV=0x100 (1.000) YCbCr=0x12A (1.164) - 18 - 11 - read-write - - - UV_OFFSET - Two's compliment phase offset implicit for CbCr data UV_OFFSET. Generally used for YCbCr to RGB conversion. -YCbCr=0x180, YUV=0x000 (typically -128 or 0x180 to indicate normalized -0.5 to 0.5 range). - 9 - 9 - read-write - - - Y_OFFSET - Two's compliment amplitude offset implicit in the Y data Y_OFFSET. For YUV, this is typically 0 and for YCbCr, this is -typically -16 (0x1F0). - 0 - 9 - read-write - - - - - CSC_COEF1 - Layer Color Space Conversion Config Register 1 - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - C1 - Two's compliment Red V/Cr multiplier coefficient C1. YUV=0x123 (1.140) YCbCr=0x198 (1.596). - 16 - 11 - read-write - - - C4 - Two's compliment Blue U/Cb multiplier coefficient C4. YUV=0x208 (2.032) YCbCr=0x204 (2.017). - 0 - 11 - read-write - - - - - CSC_COEF2 - Layer Color Space Conversion Config Register 2 - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - C2 - Two's compliment Green V/Cr multiplier coefficient C2. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813). - 16 - 11 - read-write - - - C3 - Two's compliment Green U/Cb multiplier coefficient C3. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392). - 0 - 11 - read-write - - - - - - CLUT_LOAD - Clut Load Control Register - 0x400 - 32 - 0x00000000 - 0x0000007F - - - SEL_NUM - Selected CLUT Number -The SEL_CLUT_NUM is used to select which plane's CLUT need to be updated. The hardware can only backup one CLUT setting and load, so the SEL_CLUT_NUM can't be changed when CLUT_LOAD[UPDATE_EN] is 1. -. 3'h0 - PLANE 0 -. 3'h1 - PLANE 1 -. ------ -. 3'h7 - PLANE 7 -CLUT 8 can be modified via APB even when display is on. -Currently CLUT for plane 0..7 cannot be modified via APB when display is on. Can only be updated via CLUT_LOAD[UPDATE_EN] bit. - 4 - 3 - read-write - - - UPDATE_EN - CLUT Update Enable -The bit is written to 1 when software want to update the Color Look Up Tables during display. -If set to 1, software update selected CLUT due to SEL_CLUT_NUM setting, the table will be copied from CLUT8 during vertical blanking period after SHADOW_LOAD_EN is set to 1. -If set to 0, software can update CLUT8 directly according to the CLUT memory map. -Hardware will automatically clear this bit when selected CLUT is updated according to SEL_CLUT_NUM. - 0 - 1 - read-write - - - - - - - CAM0 - CAM0 - CAM - 0xf1008000 - - 0x0 - 0x490 - registers - - - - CR1 - Control Register - 0x0 - 32 - 0x00000000 - 0xBF9AAFFF - - - COLOR_EXT - If asserted, will change the output color to ARGB8888 mode. Used by input color as RGB565, RGB888, YUV888, etc. -The byte sequence is B,G,R,A. Depends on correct CR2[ClrBitFormat] configuration. - 29 - 1 - read-write - - - INV_PIXCLK - invert pixclk pad input before it is used - 28 - 1 - read-write - - - INV_HSYNC - invert hsync pad input before it is used - 27 - 1 - read-write - - - INV_VSYNC - invert vsync pad input before it is used - 26 - 1 - read-write - - - SWAP16_EN - SWAP 16-Bit Enable. This bit enables the swapping of 16-bit data. Data is packed from 8-bit or 10-bit to 32-bit first (according to the setting of PACK_DIR) and then swapped as 16-bit words before being put into the RX FIFO. The action of the bit only affects the RX FIFO. -NOTE: Example of swapping enabled: -Data input to FIFO = 0x11223344 -Data in RX FIFO = 0x 33441122 -NOTE: Example of swapping disabled: -Data input to FIFO = 0x11223344 -Data in RX FIFO = 0x11223344 -0 Disable swapping -1 Enable swapping - 25 - 1 - read-write - - - PACK_DIR - Data Packing Direction. This bit Controls how 8-bit/10-bit image data is packed into 32-bit RX FIFO. -0 Pack from LSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x44332211 in RX FIFO. -1 Pack from MSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x11223344 in RX FIFO. - 24 - 1 - read-write - - - RESTART_BUSPTR - force to restart the bus pointer at the every end of the sof period, and at the same time, clr the fifo pointer - 23 - 1 - read-write - - - ASYNC_RXFIFO_CLR - ASynchronous Rx FIFO Clear. -When asserted, this bit clears RXFIFO immediately. -It will be auto-cleared. - 20 - 1 - read-write - - - SYNC_RXFIFO_CLR - Synchronous Rx FIFO Clear. -When asserted, this bit clears RXFIFO on every SOF. - 19 - 1 - read-write - - - SOF_INT_POL - SOF Interrupt Polarity. This bit controls the condition that generates an SOF interrupt. -0 SOF interrupt is generated on SOF falling edge -1 SOF interrupt is generated on SOF rising edge - 17 - 1 - read-write - - - INV_DATA - Invert Data Input. This bit enables or disables internal inverters on the data lines. -0 CAM_D data lines are directly applied to internal circuitry -1 CAM_D data lines are inverted before applied to internal circuitry - 15 - 1 - read-write - - - STORAGE_MODE - 00: Normal Mode (one plane mode) -01: Two Plane Mode (Y, UV plane) -10: Y-only Mode, byte sequence as Y0,Y1,Y2,Y3 -11: Binary Mode, bit sequence is from LSB to MSB when CR20[BIG_END]=0 - 10 - 2 - read-write - - - COLOR_FORMATS - input color formats: -0010b:24bit:RGB888 -0011b:24bit:RGB666 -0100b:16bit:RGB565 -0101b:16bit:RGB444 -0110b:16bit:RGB555 -0111b: 16bit: YCbCr422 (Y0 Cb Y1 Cr, each 8-bit) -YUV -YCrCb -Note: YUV420 is not supported. -1000b: 24bit: YUV444 - 3 - 4 - read-write - - - SENSOR_BIT_WIDTH - the bit width of the sensor -0: 8 bits -1: 10 bits -3:24bits -Others: Undefined - 0 - 3 - read-write - - - - - INT_EN - Interrupt Enable Register - 0x4 - 32 - 0x00000000 - 0xFFFFFF5F - - - ERR_CL_BWID_CFG_INT_EN - The unsupported color (color_formats[3:0]) and bitwidth (sensor_bit_width[2:0]) configuation interrupt enable - 13 - 1 - read-write - - - HIST_DONE_INT_EN - Enable hist done int - 12 - 1 - read-write - - - HRESP_ERR_EN - Hresponse Error Enable. This bit enables the hresponse error interrupt. -0 Disable hresponse error interrupt -1 Enable hresponse error interrupt - 11 - 1 - read-write - - - EOF_INT_EN - End-of-Frame Interrupt Enable. This bit enables and disables the EOF interrupt. -0 EOF interrupt is disabled. -1 EOF interrupt is generated when RX count value is reached. - 9 - 1 - read-write - - - RF_OR_INTEN - RxFIFO Overrun Interrupt Enable. This bit enables the RX FIFO overrun interrupt. -0 RxFIFO overrun interrupt is disabled -1 RxFIFO overrun interrupt is enabled - 6 - 1 - read-write - - - FB2_DMA_DONE_INTEN - Frame Buffer2 DMA Transfer Done Interrupt Enable. This bit enables the interrupt of Frame Buffer2 DMA -transfer done. -0 Frame Buffer2 DMA Transfer Done interrupt disable -1 Frame Buffer2 DMA Transfer Done interrupt enable - 3 - 1 - read-write - - - FB1_DMA_DONE_INTEN - Frame Buffer1 DMA Transfer Done Interrupt Enable. This bit enables the interrupt of Frame Buffer1 DMA -transfer done. -0 Frame Buffer1 DMA Transfer Done interrupt disable -1 Frame Buffer1 DMA Transfer Done interrupt enable - 2 - 1 - read-write - - - SOF_INT_EN - Start Of Frame (SOF) Interrupt Enable. This bit enables the SOF interrupt. -0 SOF interrupt disable -1 SOF interrupt enable - 0 - 1 - read-write - - - - - CR2 - Control 2 Register - 0x10 - 32 - 0x00000000 - 0xFFFF8FEF - - - FRMCNT_15_0 - Frame Counter. This is a 16-bit Frame Counter -(Wraps around automatically after reaching the maximum) - 16 - 16 - read-only - - - FRMCNT_RST - Frame Count Reset. Resets the Frame Counter. -0 Do not reset -1 Reset frame counter immediately - 15 - 1 - read-write - - - RXFF_LEVEL - RxFIFO Full Level. When the number of data in RxFIFO reaches this level, a RxFIFO full interrupt is generated, or an RXFIFO DMA request is sent. -000 4 Double words -001 8 Double words -010 16 Double words -011 24 Double words -100 32 Double words -101 48 Double words -110 64 Double words -111 96 Double words - 9 - 3 - read-write - - - DMA_REQ_EN_RFF - DMA Request Enable for RxFIFO. This bit enables the dma request from RxFIFO to the embedded DMA controller. -0 Disable the dma request -1 Enable the dma request. The UV Rx FIFO is only enabled to filling data in 2 plane mode. - 5 - 1 - read-write - - - CLRBITFORMAT - Input Byte & bit sequence same as OV5640, except for Raw mode. Used only for internal ARGB conversion. - 0 - 4 - read-write - - - - - STA - Status Register - 0x24 - 32 - 0x00000000 - 0xFFFFA7FC - - - ERR_CL_BWID_CFG - The unsupported color (color_formats[3:0]) and bitwidth (sensor_bit_width[2:0]) configuation found - 19 - 1 - write-only - - - HIST_DONE - hist cal done - 18 - 1 - write-only - - - RF_OR_INT - RxFIFO Overrun Interrupt Status. Indicates the overflow status of the RxFIFO register. (Cleared by writing -1) -0 RXFIFO has not overflowed. -1 RXFIFO has overflowed. - 13 - 1 - write-only - - - DMA_TSF_DONE_FB2 - DMA Transfer Done in Frame Buffer2. Indicates that the DMA transfer from RxFIFO to Frame Buffer2 is completed. It can trigger an interrupt if the corresponding enable bit is set in CAM_CR1. This bit can be cleared by by writing 1 or reflashing the RxFIFO dma controller in CAM_CR3. (Cleared by writing 1) -0 DMA transfer is not completed. -1 DMA transfer is completed. - 10 - 1 - write-only - - - DMA_TSF_DONE_FB1 - DMA Transfer Done in Frame Buffer1. Indicates that the DMA transfer from RxFIFO to Frame Buffer1 is completed. It can trigger an interrupt if the corresponding enable bit is set in CAM_CR1. This bit can be cleared by by writing 1 or reflashing the RxFIFO dma controller in CAM_CR3. (Cleared by writing 1) -0 DMA transfer is not completed. -1 DMA transfer is completed. - 9 - 1 - write-only - - - EOF_INT - End of Frame (EOF) Interrupt Status. Indicates when EOF is detected. (Cleared by writing 1) -0 EOF is not detected. -1 EOF is detected. - 7 - 1 - write-only - - - SOF_INT - Start of Frame Interrupt Status. Indicates when SOF is detected. (Cleared by writing 1) -0 SOF is not detected. -1 SOF is detected. - 6 - 1 - write-only - - - HRESP_ERR_INT - Hresponse Error Interrupt Status. Indicates that a hresponse error has been detected. (Cleared by writing -1) -0 No hresponse error. -1 Hresponse error is detected. - 2 - 1 - write-only - - - - - DMASA_FB1 - Pixel DMA Frame Buffer 1 Address - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - PTR - DMA Start Address in Frame Buffer1. Indicates the start address to write data. The embedded DMA controller will read data from RxFIFO and write it from this address through AHB bus. The address should be double words aligned. -In Two-Plane Mode, Y buffer1 - 2 - 30 - read-write - - - - - DMASA_FB2 - Pixel DMA Frame Buffer 2 Address - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - PTR - DMA Start Address in Frame Buffer2. Indicates the start address to write data. The embedded DMA controller will read data from RxFIFO and write it from this address through AHB bus. The address should be double words aligned. -In Two-Plane Mode, Y buffer2 - 2 - 30 - read-write - - - - - BUF_PARA - Buffer Parameters Register - 0x38 - 32 - 0x00000000 - 0xFFFFFFFF - - - LINEBSP_STRIDE - Line Blank Space Stride. Indicates the space between the end of line image storage and the start of a new line storage in the frame buffer. -The width of the line storage in frame buffer(in double words) minus the width of the image(in double words) is the stride. The stride should be double words aligned. The embedded DMA controller will skip the stride before starting to write the next row of the image. - 0 - 16 - read-write - - - - - IDEAL_WN_SIZE - Ideal Image Size Register - 0x3c - 32 - 0x00000000 - 0xFFFFFFFF - - - HEIGHT - Image Height. Indicates how many active pixels in a column of the image from the sensor. - 16 - 16 - read-write - - - WIDTH - Image Width. Indicates how many active pixels in a line of the image from the sensor. -The number of bytes to be transferred is re-calculated automatically in hardware based on cr1[color_ext] and cr1[store_mode]. Default value is 2*pixel number. -As the input data from the sensor is 8-bit/pixel format, the IMAGE_WIDTH should be a multiple of 8 pixels. - 0 - 16 - read-write - - - - - CR18 - Control CR18 Register - 0x4c - 32 - 0x00000000 - 0xFFFFE7BF - - - CAM_ENABLE - CAM global enable signal. Only when this bit is 1, CAM can start to receive the data and store to memory. - 31 - 1 - read-write - - - AWQOS - AWQOS for bus fabric arbitration - 7 - 4 - read-write - - - - - DMASA_UV1 - Pixel UV DMA Frame Buffer 1 Address - 0x50 - 32 - 0x00000000 - 0xFFFFFFFF - - - PTR - Two Plane UV Buffer Start Address 1 - 2 - 30 - read-write - - - - - DMASA_UV2 - Pixel UV DMA Frame Buffer 2 Address - 0x54 - 32 - 0x00000000 - 0xFFFFFFFF - - - PTR - Two Plane UV Buffer Start Address 2 - 2 - 30 - read-write - - - - - CR20 - Control CR20 Register - 0x58 - 32 - 0x00000000 - 0xFFFFFFFF - - - BINARY_EN - binary picture output enable - 31 - 1 - read-write - - - HISTOGRAM_EN - histogarm enable - 30 - 1 - read-write - - - BIG_END - Asserted when binary output is in big-endian type, which mean the right most data is at the LSBs. Take function only inside the 32-bit word. - 8 - 1 - read-write - - - THRESHOLD - Threshold to generate binary color. Bin 1 is output if the pixel is greater than the threshold. - 0 - 8 - read-write - - - - - CSC_COEF0 - Color Space Conversion Config Register 0 - 0x70 - 32 - 0x00000000 - 0xFFFFFFFF - - - YCBCR_MODE - This bit changes the behavior when performing U/V converting. -0b - Converting YUV to RGB data -1b - Converting YCbCr to RGB data - 31 - 1 - read-write - - - ENABLE - Enable the CSC unit -0b - The CSC is bypassed and the input pixels are RGB data already -1b - The CSC is enabled and the pixels will be converted to RGB data - 30 - 1 - read-write - - - C0 - Two's compliment Y multiplier coefficient. YUV=0x100 (1.000) YCbCr=0x12A (1.164) - 18 - 11 - read-write - - - UV_OFFSET - Two's compliment phase offset implicit for CbCr data. Generally used for YCbCr to RGB conversion. -YCbCr=0x180, YUV=0x000 (typically -128 or 0x180 to indicate normalized -0.5 to 0.5 range). - 9 - 9 - read-write - - - Y_OFFSET - Two's compliment amplitude offset implicit in the Y data. For YUV, this is typically 0 and for YCbCr, this is -typically -16 (0x1F0). - 0 - 9 - read-write - - - - - CSC_COEF1 - Color Space Conversion Config Register 1 - 0x74 - 32 - 0x00000000 - 0xFFFFFFFF - - - C1 - Two's compliment Red V/Cr multiplier coefficient. YUV=0x123 (1.140) YCbCr=0x198 (1.596). - 16 - 11 - read-write - - - C4 - Two's compliment Blue U/Cb multiplier coefficient. YUV=0x208 (2.032) YCbCr=0x204 (2.017). - 0 - 11 - read-write - - - - - CSC_COEF2 - Color Space Conversion Config Register 2 - 0x78 - 32 - 0x00000000 - 0xFFFFFFFF - - - C2 - Two's compliment Green V/Cr multiplier coefficient. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813). - 16 - 11 - read-write - - - C3 - Two's compliment Green U/Cb multiplier coefficient. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392). - 0 - 11 - read-write - - - - - CLRKEY_LOW - Low Color Key Register - 0x7c - 32 - 0x00000000 - 0xFFFFFFFF - - - LIMIT - Low range of color key applied to PS buffer. To disable PS colorkeying, set the low colorkey to 0xFFFFFF and the high colorkey to 0x000000. - 0 - 24 - read-write - - - - - CLRKEY_HIGH - High Color Key Register - 0x80 - 32 - 0x00000000 - 0xFFFFFFFF - - - LIMIT - Low range of color key applied to PS buffer. To disable PS colorkeying, set the low colorkey to 0xFFFFFF and the high colorkey to 0x000000. - 0 - 24 - read-write - - - - - 256 - 0x4 - DATA0,DATA1,DATA2,DATA3,DATA4,DATA5,DATA6,DATA7,DATA8,DATA9,DATA10,DATA11,DATA12,DATA13,DATA14,DATA15,DATA16,DATA17,DATA18,DATA19,DATA20,DATA21,DATA22,DATA23,DATA24,DATA25,DATA26,DATA27,DATA28,DATA29,DATA30,DATA31,DATA32,DATA33,DATA34,DATA35,DATA36,DATA37,DATA38,DATA39,DATA40,DATA41,DATA42,DATA43,DATA44,DATA45,DATA46,DATA47,DATA48,DATA49,DATA50,DATA51,DATA52,DATA53,DATA54,DATA55,DATA56,DATA57,DATA58,DATA59,DATA60,DATA61,DATA62,DATA63,DATA64,DATA65,DATA66,DATA67,DATA68,DATA69,DATA70,DATA71,DATA72,DATA73,DATA74,DATA75,DATA76,DATA77,DATA78,DATA79,DATA80,DATA81,DATA82,DATA83,DATA84,DATA85,DATA86,DATA87,DATA88,DATA89,DATA90,DATA91,DATA92,DATA93,DATA94,DATA95,DATA96,DATA97,DATA98,DATA99,DATA100,DATA101,DATA102,DATA103,DATA104,DATA105,DATA106,DATA107,DATA108,DATA109,DATA110,DATA111,DATA112,DATA113,DATA114,DATA115,DATA116,DATA117,DATA118,DATA119,DATA120,DATA121,DATA122,DATA123,DATA124,DATA125,DATA126,DATA127,DATA128,DATA129,DATA130,DATA131,DATA132,DATA133,DATA134,DATA135,DATA136,DATA137,DATA138,DATA139,DATA140,DATA141,DATA142,DATA143,DATA144,DATA145,DATA146,DATA147,DATA148,DATA149,DATA150,DATA151,DATA152,DATA153,DATA154,DATA155,DATA156,DATA157,DATA158,DATA159,DATA160,DATA161,DATA162,DATA163,DATA164,DATA165,DATA166,DATA167,DATA168,DATA169,DATA170,DATA171,DATA172,DATA173,DATA174,DATA175,DATA176,DATA177,DATA178,DATA179,DATA180,DATA181,DATA182,DATA183,DATA184,DATA185,DATA186,DATA187,DATA188,DATA189,DATA190,DATA191,DATA192,DATA193,DATA194,DATA195,DATA196,DATA197,DATA198,DATA199,DATA200,DATA201,DATA202,DATA203,DATA204,DATA205,DATA206,DATA207,DATA208,DATA209,DATA210,DATA211,DATA212,DATA213,DATA214,DATA215,DATA216,DATA217,DATA218,DATA219,DATA220,DATA221,DATA222,DATA223,DATA224,DATA225,DATA226,DATA227,DATA228,DATA229,DATA230,DATA231,DATA232,DATA233,DATA234,DATA235,DATA236,DATA237,DATA238,DATA239,DATA240,DATA241,DATA242,DATA243,DATA244,DATA245,DATA246,DATA247,DATA248,DATA249,DATA250,DATA251,DATA252,DATA253,DATA254,DATA255 - HISTOGRAM_FIFO[%s] - no description available - 0x90 - 32 - 0x00000000 - 0xFFFFFFFF - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - - - CAM1 - CAM1 - CAM - 0xf100c000 - - - PDMA - PDMA - PDMA - 0xf1010000 - - 0x0 - 0xc0 - registers - - - - CTRL - Control Register - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - ARQOS - QoS for AXI read bus - 19 - 4 - read-write - - - AWQOS - QoS for AXI write bus - 15 - 4 - read-write - - - PACK_DIR - Decide the byte sequence of the 32-bit output word {A3, A2, A1, A0}. The bit sequence ina byte is not changed. -2'b00: no change {A3, A2, A1, A0} -2'b01: {A2, A3, A0, A1} -2'b10: {A1, A0, A3, A2} -2'b11: {A0, A1, A2, A3} - 13 - 2 - read-write - - - AXIERR_IRQ_EN - Enable interrupt of AXI bus error - 12 - 1 - read-write - - - PDMA_DONE_IRQ_EN - Enable interrupt of PDMA_DONE - 11 - 1 - read-write - - - CLKGATE - Assert this bit to gate off clock when the module is not working. If reset to zero, the internal clock is always on. - 9 - 1 - read-write - - - IRQ_EN - Enable normal interrupt - 6 - 1 - read-write - - - BS16 - Asserted when the Block Size is 16x16, else 8x8 - 5 - 1 - read-write - - - P1_EN - Plane 1 Enable - 4 - 1 - read-write - - - P0_EN - Plane 0 Enable - 3 - 1 - read-write - - - PDMA_SFTRST - Software Reset. -Write 1 to clear PDMA internal logic. -Write 0 to exit software reset mode. - 1 - 1 - read-write - - - PDMA_EN - 1b - Enabled - 0 - 1 - read-write - - - - - STAT - Status Register - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - BLOCKY - Y block that is processing - 24 - 8 - read-only - - - BLOCKX - X block that is processing - 16 - 8 - read-only - - - PDMA_DONE - PDMA one image done - 9 - 1 - write-only - - - AXI_ERR_ID - AXI error ID - 5 - 4 - read-only - - - AXI_0_WRITE_ERR - AXI0 write err - 4 - 1 - write-only - - - AXI_1_READ_ERR - AXI1 read err - 3 - 1 - write-only - - - AXI_0_READ_ERR - AXI0 read err - 2 - 1 - write-only - - - IRQ - Asserted to indicate a IRQ event - 0 - 1 - read-only - - - - - OUT_CTRL - Out Layer Control Register - 0x8 - 32 - 0x00000000 - 0xFFFFFF3F - - - DSTALPHA - The destination (P1) system ALPHA value. - 24 - 8 - read-write - - - SRCALPHA - The source (P0) system ALPHA value. - 16 - 8 - read-write - - - DSTALPHA_OP - The usage of the DSTALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel embedded in the stream indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) -0: the DSTALPHA[7:0] is invalid, use the alpha value embedded in the stream -1: the DSTALPHA[7:0] is used to override the alpha value embedded in the stream. (useful when the corresponding data stream has no alpha info) -2: the DSTALPHA[7:0] is used to scale the alpha value embedded in the stream -Others: Reserved - 14 - 2 - read-write - - - SRCALPHA_OP - The usage of the SRCALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel embedded in the stream indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) -0: the SRCALPHA[7:0] is invalid, use the alpha value embedded in the stream -1: the SRCALPHA[7:0] is used to override the alpha value embedded in the stream . (useful when the corresponding data stream has no alpha info) -2: the SRCALPHA[7:0] is used to scale the alpha value embedded in the stream -Others: Reserved - 12 - 2 - read-write - - - ABLEND_MODE - Alpha Blending Mode -0: SKBlendMode_Clear (If PS1_CTRL[BKGNDCL4CLR] is asserted, use PS1_BKGRND color to fill the range determined by PS1, else fill the range determined by PS1 with zero); -1: SKBlendMode_Src ; -2: SKBlendMode_Dst -3: SKBlendMode_SrcOver -4: SKBlendMode_DstOver -5: SKBlendMode_SrcIn -6: SKBlendMode_DstIn -7: SKBlendMode_SrcOut -8: SKBlendMode_DstOut -9: SKBlendMode_SrcATop -10: SKBlendMode_DstATop -11: SKBlendMode_Xor -12: SKBlendMode_Plus (The conventional belding mode) -13: SKBlendMode_Modulate -14: SRC org -15: DST org -Others: Reserved. - 8 - 4 - read-write - - - FORMAT - Output buffer format. -0x0 ARGB8888 - 32-bit pixles, byte sequence as B,G,R,A -0xE RGB565 - 16-bit pixels, byte sequence as B,R -0x12 UYVY1P422 - 16-bit pixels (1-plane , byte sequence as U0,Y0,V0,Y1) - 0 - 6 - read-write - - - - - OUT_BUF - Output buffer address - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR - Current address pointer for the output frame buffer. The address can have any byte alignment. 64B alignment is recommended for optimal performance. - 0 - 32 - read-write - - - - - OUT_PITCH - Outlayer Pitch Register - 0x14 - 32 - 0x00000000 - 0x0000FFFF - - - BYTELEN - Indicates the number of bytes in memory between two vertically adjacent pixels. - 0 - 16 - read-write - - - - - OUT_LRC - Output Lower Right Corner Register - 0x18 - 32 - 0x00000000 - 0x3FFF3FFF - - - Y - This field indicates the lower right Y-coordinate (in pixels) of the output frame buffer. -The value is the height of the output image size. - 16 - 14 - read-write - - - X - This field indicates the lower right X-coordinate (in pixels) of the output frame buffer. -Should be the width of the output image size. - 0 - 14 - read-write - - - - - 2 - 0x8 - 0,1 - OUT_PS[%s] - no description available - 0x1c - - ULC - Layer Upper Left Corner Register - 0x0 - 32 - 0x00000000 - 0x3FFF3FFF - - - Y - This field indicates the upper left Y-coordinate (in pixels) of the processed surface in the output frame buffer. - 16 - 14 - read-write - - - X - This field indicates the upper left X-coordinate (in pixels) of the processed surface in the output frame buffer. - 0 - 14 - read-write - - - - - LRC - Layer Lower Right Corner Register - 0x4 - 32 - 0x00000000 - 0x3FFF3FFF - - - Y - This field indicates the lower right Y-coordinate (in pixels) of the processed surface in the output frame buffer. - 16 - 14 - read-write - - - X - This field indicates the lower right X-coordinate (in pixels) of the processed surface in the output frame buffer. - 0 - 14 - read-write - - - - - - 2 - 0x30 - 0,1 - PS[%s] - no description available - 0x30 - - CTRL - Layer Control Register - 0x0 - 32 - 0x00000000 - 0x001FFFFF - - - INB13_SWAP - Swap bit[31:24] and bit [15:8] before pack_dir operation. - 20 - 1 - read-write - - - PACK_DIR - Decide the byte sequence of the 32-bit word {A3, A2, A1, A0}. The bit sequence ina byte is not changed. -2'b00: no change {A3, A2, A1, A0} -2'b01: {A2, A3, A0, A1} -2'b10: {A1, A0, A3, A2} -2'b11: {A0, A1, A2, A3} - 18 - 2 - read-write - - - BKGCL4CLR - Enable to use background color for clear area - 17 - 1 - read-write - - - YCBCR_MODE - YCbCr mode or YUV mode - 16 - 1 - read-write - - - BYPASS - Asserted to bypass the CSC stage - 15 - 1 - read-write - - - VFLIP - Indicates that the input should be flipped vertically (effect applied before rotation). - 14 - 1 - read-write - - - HFLIP - Indicates that the input should be flipped horizontally (effect applied before rotation). - 13 - 1 - read-write - - - ROTATE - Indicates the clockwise rotation to be applied at the input buffer. The rotation effect is defined as occurring -after the FLIP_X and FLIP_Y permutation. -0x0 ROT_0 -0x1 ROT_90 -0x2 ROT_180 -0x3 ROT_270 - 11 - 2 - read-write - - - DECY - Verticle pre decimation filter control. -0x0 DISABLE - Disable pre-decimation filter. -0x1 DECY2 - Decimate PS by 2. -0x2 DECY4 - Decimate PS by 4. -0x3 DECY8 - Decimate PS by 8. - 9 - 2 - read-write - - - DECX - Horizontal pre decimation filter control. -0x0 DISABLE - Disable pre-decimation filter. -0x1 DECX2 - Decimate PS by 2. -0x2 DECX4 - Decimate PS by 4. -0x3 DECX8 - Decimate PS by 8. - 7 - 2 - read-write - - - HW_BYTE_SWAP - Swap bytes in half-words. For each 16 bit half-word, the two bytes will be swapped. - 6 - 1 - read-write - - - FORMAT - PS buffer format. To select between YUV and YCbCr formats, see bit 16 of this register. -0x0 ARGB888 - 32-bit pixels, byte sequence as B,G,R,A -0xE RGB565 - 16-bit pixels, byte sequence as B,R -0x13 YUYV1P422 - 16-bit pixels (1-plane byte sequence Y0,U0,Y1,V0 interleaved bytes) - 0 - 6 - read-write - - - - - BUF - Layer data buffer address - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR - Address pointer for the PS RGB or Y (luma) input buffer. - 0 - 32 - read-write - - - - - PITCH - Layer data pitch register - 0x10 - 32 - 0x00000000 - 0x0000FFFF - - - BYTELEN - Indicates the number of bytes in memory between two vertically adjacent pixels. - 0 - 16 - read-write - - - - - BKGD - Layer background color register - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - COLOR - Background color (in 32bpp format) for any pixels not within the scaled range of the picture, but within the buffer range specified by the PS ULC/LRC. The top 8-bit is the alpha channel. - 0 - 32 - read-write - - - - - SCALE - Layer scale register - 0x18 - 32 - 0x00000000 - 0x7FFF7FFF - - - Y - This is a two bit integer and 12 bit fractional representation (##.####_####_####) of the X scaling factor for the PS source buffer. The maximum value programmed should be 2 since scaling down by a factor greater than 2 is not supported with the bilinear filter. Decimation and the bilinear filter should be used together to achieve scaling by more than a factor of 2. - 16 - 15 - read-write - - - X - This is a two bit integer and 12 bit fractional representation (##.####_####_####) of the Y scaling factor for the PS source buffer. The maximum value programmed should be 2 since scaling down by a factor greater than 2 is not supported with the bilinear filter. Decimation and the bilinear filter should be used together to achieve scaling by more than a factor of 2. - 0 - 15 - read-write - - - - - OFFSET - Layer offset register - 0x1c - 32 - 0x00000000 - 0x0FFF0FFF - - - Y - This is a 12 bit fractional representation (0.####_####_####) of the Y scaling offset. This represents a fixed pixel offset which gets added to the scaled address to determine source data for the scaling engine. -It is applied after the decimation filter stage, and before the bilinear filter stage. - 16 - 12 - read-write - - - X - This is a 12 bit fractional representation (0.####_####_####) of the X scaling offset. This represents a fixed pixel offset which gets added to the scaled address to determine source data for the scaling engine. -It is applied after the decimation filter stage, and before the bilinear filter stage. - 0 - 12 - read-write - - - - - CLRKEY_LOW - Layer low color key register - 0x20 - 32 - 0x00000000 - 0x00FFFFFF - - - LIMIT - Low range of color key applied to PS buffer. To disable PS colorkeying, set the low colorkey to 0xFFFFFF and the high colorkey to 0x000000. - 0 - 24 - read-write - - - - - CLRKEY_HIGH - Layer high color key register - 0x24 - 32 - 0x00000000 - 0x00FFFFFF - - - LIMIT - High range of color key applied to PS buffer. To disable PS colorkeying, set the low colorkey to 0xFFFFFF and the high colorkey to 0x000000 - 0 - 24 - read-write - - - - - ORG - Layer original size register - 0x28 - 32 - 0x00000000 - 0x3FFF3FFF - - - HIGHT - The number of vertical pixels of the original frame (not -1) - 16 - 14 - read-write - - - WIDTH - The number of horizontal pixels of the original frame (not -1) - 0 - 14 - read-write - - - - - - YUV2RGB_COEF0 - YUV2RGB coefficients register 0 - 0xa0 - 32 - 0x00000000 - 0x1FFFFFFF - - - C0 - Two's compliment Y multiplier coefficient C0. YUV=0x100 (1.000) YCbCr=0x12A (1.164) - 18 - 11 - read-write - - - UV_OFFSET - Two's compliment phase offset implicit for CbCr data UV_OFFSET. Generally used for YCbCr to RGB conversion. -YCbCr=0x180, YUV=0x000 (typically -128 or 0x180 to indicate normalized -0.5 to 0.5 range). - 9 - 9 - read-write - - - Y_OFFSET - Two's compliment amplitude offset implicit in the Y data Y_OFFSET. For YUV, this is typically 0 and for YCbCr, this is -typically -16 (0x1F0). - 0 - 9 - read-write - - - - - YUV2RGB_COEF1 - YUV2RGB coefficients register 1 - 0xa4 - 32 - 0x00000000 - 0x07FF07FF - - - C1 - Two's compliment Red V/Cr multiplier coefficient C1. YUV=0x123 (1.140) YCbCr=0x198 (1.596). - 16 - 11 - read-write - - - C4 - Two's compliment Blue U/Cb multiplier coefficient C4. YUV=0x208 (2.032) YCbCr=0x204 (2.017). - 0 - 11 - read-write - - - - - YUV2RGB_COEF2 - YUV2RGB coefficients register 2 - 0xa8 - 32 - 0x00000000 - 0x07FF07FF - - - C2 - Two's compliment Green V/Cr multiplier coefficient C2. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813). - 16 - 11 - read-write - - - C3 - Two's compliment Green U/Cb multiplier coefficient C3. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392). - 0 - 11 - read-write - - - - - RGB2YUV_COEF0 - RGB2YUV coefficients register 0 - 0xac - 32 - 0x00000000 - 0xFFFFFFFF - - - YCBCR_MODE - Asserted to use YCrCb mode - 31 - 1 - read-write - - - ENABLE - Asserted to enable this RGB2YUV CSC stage - 30 - 1 - read-write - - - C0 - CSC parameters C0 - 18 - 11 - read-write - - - UV_OFFSET - CSC parameters UV_OFFSET - 9 - 9 - read-write - - - Y_OFFSET - CSC parameters Y_OFFSET - 0 - 9 - read-write - - - - - RGB2YUV_COEF1 - RGB2YUV coefficients register 1 - 0xb0 - 32 - 0x00000000 - 0x07FF07FF - - - C1 - CSC parameters C1 - 16 - 11 - read-write - - - C4 - CSC parameters C4 - 0 - 11 - read-write - - - - - RGB2YUV_COEF2 - RGB2YUV coefficients register 2 - 0xb4 - 32 - 0x00000000 - 0x07FF07FF - - - C2 - CSC parameters C2 - 16 - 11 - read-write - - - C3 - CSC parameters C3 - 0 - 11 - read-write - - - - - RGB2YUV_COEF3 - RGB2YUV coefficients register 3 - 0xb8 - 32 - 0x00000000 - 0x07FF07FF - - - C6 - CSC parameters C6 - 16 - 11 - read-write - - - C5 - CSC parameters C5 - 0 - 11 - read-write - - - - - RGB2YUV_COEF4 - RGB2YUV coefficients register 4 - 0xbc - 32 - 0x00000000 - 0x07FF07FF - - - C8 - CSC parameters C8 - 16 - 11 - read-write - - - C7 - CSC parameters C7 - 0 - 11 - read-write - - - - - - - JPEG - JPEG - JPEG - 0xf1014000 - - 0x0 - 0xa0 - registers - - - - InDMA_MISC - In DMA Misc Control Register - 0x0 - 32 - 0x00000000 - 0xFFFFFFFC - - - ARQOS - QoS for AXI read channel - 19 - 4 - read-write - - - MAX_OT - max_ot when input are RGB pixels. -For 16 bits per pixel, it can be set as 4. -For 32 bits per pixel, it will be set as 2. - 15 - 4 - read-write - - - INB13_SWAP - Swap bit[31:24] and bit [15:8] before pack dir operation. Only work for pixel data. - 14 - 1 - read-write - - - PACK_DIR - Decide the byte sequence of the 32-bit word {A3, A2, A1, A0}. The bit sequence in a byte is not changed. Only work for pixel data. -2'b00: no change {A3, A2, A1, A0} -2'b01: {A2, A3, A0, A1} -2'b10: {A1, A0, A3, A2} -2'b11: {A0, A1, A2, A3} - 12 - 2 - read-write - - - INDMA_RENEW - Renew In DMA. Default is to continue the write address counter when a new DMA request comes. Asserted to reset the write address counter. - 11 - 1 - read-write - - - NXT_IRQ_EN - In DMA Next Interrupt Enable - 10 - 1 - read-write - - - IN_DMA_DONE_IRQ_EN - In DMA Done enable - 9 - 1 - read-write - - - AXI_ERR_IRQ_EN - In DMA axi bus error inetrrupt enable - 8 - 1 - read-write - - - IRQ_EN - interrupt enable for all interrupt sources of In DMA module - 7 - 1 - read-write - - - IN_DMA_ID - 0: Pixel (In) -1: ECS (In) -2: Qmem -3: HuffEnc -4: HuffMin -5: HuffBase -6: HuffSymb - 4 - 3 - read-write - - - IN_DMA_REQ - Asserted to request DMA. Automatically clear after DMA is done. - 3 - 1 - read-write - - - INDMA2D - Asserted if In_DMA_ID=Pixel. - 2 - 1 - read-write - - - - - InDMABase - In DMA Buf Address - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR - Y plane (or Encoded Bit Plane) - 0 - 32 - read-write - - - - - InDMA_Ctrl0 - In DMA Buf Control 0 Register - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - TTLEN - Total length (Low 16 bits) in Bytes -1 for transfer when In_DMA_ID!=Pixel. - 16 - 16 - read-write - - - PITCH - Pitch between the starting point of Rows. Only active when In_DMA_ID=Pixel.. - 0 - 16 - read-write - - - - - InDMA_Ctrl1 - In DMA Buf Control 1 Register - 0x10 - 32 - 0x00000000 - 0x0000FFFF - - - ROWLEN - Total length (High 16 bits) in Bytes -1 for transfer. See reference in InDMA_Ctrl0[TTLEN] - 0 - 16 - read-write - - - - - INXT_CMD - In DMA Next Command Register - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR - The address pointing to the next command - 2 - 30 - read-write - - - OP_VALID - asserted if there is either a DATA DMA phase or NXTCMD phase. Automatically cleared. Will trigger the InDMA transfer if CFG[JPEG_EN] is 1. - 1 - 1 - read-write - - - EN - NXTCMD phase Enable Bit - 0 - 1 - read-write - - - - - OutDMA_MISC - Out DMA Misc Control Register - 0x20 - 32 - 0x00000000 - 0xFFFFFFFC - - - AWQOS - No description available - 14 - 4 - read-write - - - PACK_DIR - Decide the byte sequence of the 32-bit word {A3, A2, A1, A0}. The bit sequence in a byte is not changed. All outdma data are impacted. -2'b00: no change {A3, A2, A1, A0} (This is used for ecs stream) -2'b01: {A2, A3, A0, A1} -2'b10: {A1, A0, A3, A2} -2'b11: {A0, A1, A2, A3} - 12 - 2 - read-write - - - EN_OUTCNT - Enable output counter (unit as bytes) - 11 - 1 - read-write - - - INI_OUTCNT - Asserted to ini output counter - 10 - 1 - read-write - - - ADD_ODMA_ENDINGS - Add 0xFFD9 to the ending of the odma stream when all original image pixels are processed by the encoder module. - 9 - 1 - read-write - - - NXT_IRQ_EN - Out DMA Next Interrupt Enable - 8 - 1 - read-write - - - OUT_DMA_DONE_IRQ_EN - Out DMA Done interrupt Enable - 7 - 1 - read-write - - - AXI_ERR_IRQ_EN - Out DMA axi bus error inetrrupt enable - 6 - 1 - read-write - - - IRQ_EN - interrupt enable for all interrupt sources of Out DMA module - 5 - 1 - read-write - - - OUT_DMA_ID - 0: Pixel (Out) -1: ECS (Out) - 4 - 1 - read-write - - - OUT_DMA_REQ - Asserted to enable Out DMA request - 3 - 1 - read-write - - - OUTDMA2D - Asserted if Out_DMA_ID==Pixel - 2 - 1 - read-write - - - - - OutDMABase - Out DMA Buf Address - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR - Y plane (or Encoded Bit Plane) - 0 - 32 - read-write - - - - - OutDMA_Ctrl0 - Out DMA Buf Control 0 Register - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - TTLEN - Total length (Low 16 bits) in Bytes -1 for transfer when Out_DMA_ID!=Pixel. If Out_DMA_ID=ECS, it can be any value greater than the length of the ECS, for example, the number of encoded bytes. - 16 - 16 - read-write - - - PITCH - Pitch between the starting point of Rows when Out_DMA_ID==Pixel - 0 - 16 - read-write - - - - - OutDMA_Ctrl1 - Out DMA Buf Control 1 Register - 0x30 - 32 - 0x00000000 - 0x0000FFFF - - - ROWLEN - Total length (High 16 bits) in Bytes -1 for transfer. See reference in OutDMA_Ctrl0[TTLEN] - 0 - 16 - read-write - - - - - ONXT_CMD - Out DMA Next Command Register - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR - The address pointing to the next command - 2 - 30 - read-write - - - OP_VALID - asserted if there is either a DATA DMA phase or NXTCMD phase. Automatically cleared. Will trigger the OutDMA and NXTCMD phase transfer if CFG[JPEG_EN] is 1. - 1 - 1 - read-write - - - EN - NXTCMD phase Enable Bit - 0 - 1 - read-write - - - - - CFG - Configuration Register - 0x40 - 32 - 0x00000000 - 0xFFFFFFFF - - - JD_UVSWAP - Normally the default CbCr sequence is that Cb macro block coming before Cr macro blk. If Cr macro block is first, set this bit to 1'b1. This bit only impact the color space conversion from/to RGB. - 22 - 1 - read-write - - - CFG_IPATH_SEL - 2'b0:2-plane (Y- and UV- plane) or 1-plane (Y-only) as determined by the original data, byte sequence as Y0,Y1, or U,V -2'b01:ARGB8888, byte sequence as B,G,R,A -2'b10:RGB565, byte sequence as B,R -2'b11: YUV422H, byte sequence as Y0,U0,Y1,V0 - 20 - 2 - read-write - - - CODEC_OVER_IRQ_EN - The jpg endec process done interrupt enable - 19 - 1 - read-write - - - CODEC_RESTART_ERR_IRQ_EN - The jpg endec restart error interrupt enable - 18 - 1 - read-write - - - MEM_DEBUG_CLK_SEL - asserted to use APB clock, so that the memory contents could be read out through APB interface - 17 - 1 - read-write - - - CLKGATE - Assert this bit to gate off clock when the module is not working. If reset to zero, the internal clock is always on. - 9 - 1 - read-write - - - CFG_OPATH_SEL - 2'b0:2-plane (Y- and UV- plane) or 1-plane (Y-only) as determined by the original data, byte sequence as Y0,Y1, or U,V -2'b01:ARGB8888, byte sequence as B,G,R,A -2'b10:RGB565, byte sequence as R,B -2'b11: YUV422H1P, byte sequence as Y0,U0,Y1,V0 - 7 - 2 - read-write - - - JDATA_FORMAT - 3'b000: for 420, hy=2, vy=2, hc=1, vc=1 // 6 sub-blocks per MCU -3'b001: for 422h, hy=2, vy=1, hc=1, vc=1 // 4 sub-blocks per MCU -3'b010: for 422v, hy=1, vy=2, hc=1, vc=1 // 4 sub-blocks per MCU -3'b011: for 444, hy=1, vy=1, hc=1, vc=1 // 3 sub-blocks per MCU -3'b100: for 400, hy=2, vy=2, hc=0, vc=0 // 4 sub-blocks per MCU -Others: Undefined - 4 - 3 - read-write - - - JPEG_SFTRST - Software Reset - 3 - 1 - read-write - - - START - Asserted if to start a new encoder/decoder conversion. -It will at first stop the inner JPEG module, then reset it, and then re-run it. -It is a different mode from DMA phase mode. -It cannot be configured in the DMA chain descriptor. It should be configured by the core processor. -Auto clear. - 2 - 1 - read-write - - - MODE - 1: decoder, 0:encoder - 1 - 1 - read-write - - - JPEG_EN - 1b - Enabled - 0 - 1 - read-write - - - - - STAT - Status Register - 0x44 - 32 - 0x00000000 - 0xFFFFBFFE - - - BUSY - When 1 means that the module is busy doing conversion and data transfer. - 31 - 1 - read-only - - - AXI_ERR_ID - the axi err id - 10 - 4 - read-only - - - AXI_READ_ERR - in-dma axi bus error - 9 - 1 - read-only - - - AXI_WRITE_ERR - out-dma axi bus error - 8 - 1 - read-only - - - AXI_ERR - axi bus error - 7 - 1 - write-only - - - ONXT_IRQ - OutDMA next interrupt - 6 - 1 - write-only - - - INXT_IRQ - InDMA next interrupt - 5 - 1 - write-only - - - OUT_DMA_TRANSFER_DONE - OutDMA process done - 4 - 1 - write-only - - - IN_DMA_TRANSFER_DONE - InDMA process done - 3 - 1 - write-only - - - CODEC_OVER - Coding or decoding process is over. DMA is not included. -The module is completely not busy only when in_dma_transfer_done and out_dma_transfer_done, and codec_over are all asserted. - 2 - 1 - write-only - - - RESTART_MARKER_ERROR - codec restart marker error interrupt - 1 - 1 - write-only - - - - - Width - Image width register - 0x48 - 32 - 0x00000000 - 0xFFFFFFFF - - - IMG - Image Width (it is the max index of pixel counting from 0, assuming the top left pixel is indexed as [0,0]) - 0 - 16 - read-write - - - - - Height - Image height register - 0x4c - 32 - 0x00000000 - 0xFFFFFFFF - - - IMG - Image Height (it is the max index of pixel counting from 0, assuming the top left pixel is indexed as [0,0]) - 0 - 16 - read-write - - - - - BufAddr - Buf Access Addr - 0x50 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR - ADDR[31:28] denotes the buffer type: -0x2: Qmem -0x3: HuffEnc -0x4: HuffMin -0x5: HuffBase -0x6: HuffSymb -ADDR[27:0] is the address inside the buffer - 0 - 32 - read-write - - - - - BufData - Buf Access Data - 0x54 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - The data write-to/read-from buffer. -The n-th address read will be actually the data written for n-1 th address, and the actual stored location is n-1 th address. - 0 - 32 - read-write - - - - - OutDMACnt - Out DMA Bytes Counter - 0x58 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - The out DMA counter - 0 - 32 - read-only - - - - - CSC_COEF0 - YUV2RGB coefficients Register 0 - 0x5c - 32 - 0x00000000 - 0xFFFFFFFF - - - YCBCR_MODE - This bit changes the behavior when performing U/V converting. -0b - Converting YUV to RGB data -1b - Converting YCbCr to RGB data - 31 - 1 - read-write - - - ENABLE - Enable the CSC unit. -0b - The CSC is bypassed -1b - The CSC is enabled - 30 - 1 - read-write - - - C0 - Two's compliment Y multiplier coefficient C0. YUV=0x100 (1.000) YCbCr=0x12A (1.164) - 18 - 11 - read-write - - - UV_OFFSET - Two's compliment phase offset implicit for CbCr data UV_OFFSET. Generally used for YCbCr to RGB conversion. -YCbCr=0x180, YUV=0x000 (typically -128 or 0x180 to indicate normalized -0.5 to 0.5 range). - 9 - 9 - read-write - - - Y_OFFSET - Two's compliment amplitude offset implicit in the Y data Y_OFFSET. For YUV, this is typically 0 and for YCbCr, this is -typically -16 (0x1F0). - 0 - 9 - read-write - - - - - CSC_COEF1 - YUV2RGB coefficients Register 1 - 0x60 - 32 - 0x00000000 - 0xFFFFFFFF - - - C1 - Two's compliment Red V/Cr multiplier coefficient C1. YUV=0x123 (1.140) YCbCr=0x198 (1.596). - 16 - 11 - read-write - - - C4 - Two's compliment Blue U/Cb multiplier coefficient C4. YUV=0x208 (2.032) YCbCr=0x204 (2.017). - 0 - 11 - read-write - - - - - CSC_COEF2 - YUV2RGB coefficients Register 2 - 0x64 - 32 - 0x00000000 - 0xFFFFFFFF - - - C2 - Two's compliment Green V/Cr multiplier coefficient C2. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813). - 16 - 11 - read-write - - - C3 - Two's compliment Green U/Cb multiplier coefficient C3. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392). - 0 - 11 - read-write - - - - - RGB2YUV_COEF0 - RGB2YUV coefficients Register 0 - 0x68 - 32 - 0x00000000 - 0xFFFFFFFF - - - YCBCR_MODE - Asserted to use YCrCb mode. Must be assigned as 1. - 31 - 1 - read-write - - - ENABLE - Asserted to enable this RGB2YCbCr CSC stage - 30 - 1 - read-write - - - C0 - CSC parameters C0 - 18 - 11 - read-write - - - UV_OFFSET - CSC parameters UV_OFFSET - 9 - 9 - read-write - - - Y_OFFSET - CSC parameters Y_OFFSET - 0 - 9 - read-write - - - - - RGB2YUV_COEF1 - RGB2YUV coefficients Register 1 - 0x6c - 32 - 0x00000000 - 0xFFFFFFFF - - - C1 - CSC parameters C1 - 16 - 11 - read-write - - - C4 - CSC parameters C4 - 0 - 11 - read-write - - - - - RGB2YUV_COEF2 - RGB2YUV coefficients Register 2 - 0x70 - 32 - 0x00000000 - 0xFFFFFFFF - - - C2 - CSC parameters C2 - 16 - 11 - read-write - - - C3 - CSC parameters C3 - 0 - 11 - read-write - - - - - RGB2YUV_COEF3 - RGB2YUV coefficients Register 3 - 0x74 - 32 - 0x00000000 - 0xFFFFFFFF - - - C6 - CSC parameters C6 - 16 - 11 - read-write - - - C5 - CSC parameters C5 - 0 - 11 - read-write - - - - - RGB2YUV_COEF4 - RGB2YUV coefficients Register 4 - 0x78 - 32 - 0x00000000 - 0xFFFFFFFF - - - C8 - CSC parameters C8 - 16 - 11 - read-write - - - C7 - CSC parameters C7 - 0 - 11 - read-write - - - - - ImgReg1 - Image Control Register 1 - 0x84 - 32 - 0x00000000 - 0xFFFFFFF7 - - - RE - Encoder Use only. -Asseted to enable the Restart Marker processing. A Restart Marker is inserted in the outputted ECS (Entropy Coded Segment) every NRST+1 MCUs - 2 - 1 - read-write - - - NCOL - Ncol is the number of color components in the image data to process minus 1. For example, for a grayscale image Ncol=0, for an RGB image, Ncol=2 - 0 - 2 - read-write - - - - - ImgReg2 - Image Control Register 2 - 0x88 - 32 - 0x00000000 - 0xFFFFFFFF - - - NMCU - Encoder Use only. -The number of NMCU to be generated in encoder mode - 0 - 26 - read-write - - - - - ImgReg3 - Image Control Register 3 - 0x8c - 32 - 0x00000000 - 0xFFFFFFFF - - - NRST - Encoder use only. -It is the number of MCUs between two Restart Markers (if enabled) minus 1. The content of this register is ignored if the Re bit inregister 1 is not set. - 0 - 16 - read-write - - - - - 4 - 0x4 - Reg40,Reg41,Reg42,Reg43 - IMGREG[%s] - no description available - 0x90 - 32 - 0x00000000 - 0xFFFFFFFF - - - NBLOCK - Encoder use only. -The number of data units (8x8 blocks of data) of the color componet contained in the MCU minus 1. - 4 - 4 - read-write - - - QT - Encoder use only. -The selection of the quantization table. - 2 - 2 - read-write - - - HA - Encoder use only. -The selection of the Huffman table for the encoding of the AC coefficients in the data units belonging to the color component. - 1 - 1 - read-write - - - HD - Encoder use only. -The selection of the Huffman table for the encoding of the DC coefficients in the data units belonging to the color component. - 0 - 1 - read-write - - - - - - - ENET0 - ENET0 - ENET - 0xf2000000 - - 0x0 - 0x1058 - registers - - - - MACCFG - MAC Configuration Register - 0x0 - 32 - 0x00000000 - 0x7FFFFFFF - - - SARC - Source Address Insertion or Replacement Control - This field controls the source address insertion or replacement for all transmitted frames. -Bit 30 specifies which MAC Address register (0 or 1) is used for source address insertion or replacement based on the values of Bits [29:28]: -- 2'b0x: The input signals mti_sa_ctrl_i and ati_sa_ctrl_i control the SA field generation. -- 2'b10: - If Bit 30 is set to 0, the MAC inserts the content of the MAC Address 0 registers (registers 16 and 17) in the SA field of all transmitted frames. - - If Bit 30 is set to 1 and the Enable MAC Address Register 1 option is selected during core configuration, - the MAC inserts the content of the MAC Address 1 registers (registers 18 and 19) in the SA field of all transmitted frames. -- 2'b11: - If Bit 30 is set to 0, the MAC replaces the content of the MAC Address 0 registers (registers 16 and 17) in the SA field of all transmitted frames. - - If Bit 30 is set to 1 and the Enable MAC Address Register 1 option is selected during core configuration, - the MAC replaces the content of the MAC Address 1 registers (registers 18 and 19) in the SA field of all transmitted frames. -Note: - Changes to this field take effect only on the start of a frame. -If you write this register field when a frame is being transmitted, only the subsequent frame can use the updated value, -that is, the current frame does not use the updated value. -- These bits are reserved and RO when the Enable SA, VLAN, and CRC Insertion on TX feature is not selected during core configuration. - 28 - 3 - read-write - - - TWOKPE - IEEE 802.3as Support for 2K Packets - When set, the MAC considers all frames, with up to 2,000 bytes length, as normal packets. -When Bit 20 (JE) is not set, the MAC considers all received frames of size more than 2K bytes as Giant frames. -When this bit is reset and Bit 20 (JE) is not set, the MAC considers all received frames of size more than 1,518 bytes (1,522 bytes for tagged) as Giant frames. -When Bit 20 is set, setting this bit has no effect on Giant Frame status. - 27 - 1 - read-write - - - SFTERR - SMII Force Transmit Error - When set, this bit indicates to the PHY to force a transmit error in the SMII frame being transmitted. This bit is reserved if the SMII PHY port is not selected during core configuration. - 26 - 1 - read-write - - - CST - CRC Stripping for Type Frames - When this bit is set, the last 4 bytes (FCS) of all frames of Ether type (Length/Type field greater than or equal to 1,536) are stripped and dropped before forwarding the frame to the application. -This function is not valid when the IP Checksum Engine (Type 1) is enabled in the MAC receiver. This function is valid when Type 2 Checksum Offload Engine is enabled. - 25 - 1 - read-write - - - TC - Transmit Configuration in RGMII, SGMII, or SMII - When set, this bit enables the transmission of duplex mode, link speed, and link up or down information to the PHY in the RGMII, SMII, - or SGMII port. When this bit is reset, no such information is driven to the PHY. -This bit is reserved (and RO) if the RGMII, SMII, or SGMII PHY port is not selected during core configuration. - 24 - 1 - read-write - - - WD - Watchdog Disable - When this bit is set, the MAC disables the watchdog timer on the receiver. The MAC can receive frames of up to 16,383 bytes. - 23 - 1 - read-write - - - JD - Jabber Disable - When this bit is set, the MAC disables the jabber timer on the transmitter. The MAC can transfer frames of up to 16,383 bytes. -When this bit is reset, the MAC cuts off the transmitter if the application sends out more than 2,048 bytes of data (10,240 if JE is set high) during transmission. - 22 - 1 - read-write - - - BE - Frame Burst Enable - When this bit is set, the MAC allows frame bursting during transmission in the GMII half-duplex mode. This bit is reserved (and RO) in the 10/100 Mbps only or full-duplex-only configurations. - 21 - 1 - read-write - - - JE - Jumbo Frame Enable - When this bit is set, the MAC allows Jumbo frames of 9,018 bytes (9,022 bytes for VLAN tagged frames) without reporting a giant frame error in the receive frame status. - 20 - 1 - read-write - - - IFG - Inter-Frame Gap - These bits control the minimum IFG between frames during transmission. -- 000: 96 bit times -- 001: 88 bit times -- 010: 80 bit times - ... -- 111: 40 bit times In the half-duplex mode, the minimum IFG can be configured only for 64 bit times (IFG = 100). -Lower values are not considered. -In the 1000-Mbps mode, the minimum IFG supported is 64 bit times (and above) in the GMAC-CORE configuration and 80 bit times (and above) in other configurations. - When a JAM pattern is being transmitted because of backpressure activation, the MAC does not consider the minimum IFG. - 17 - 3 - read-write - - - DCRS - Disable Carrier Sense During Transmission - When set high, this bit makes the MAC transmitter ignore the (G)MII CRS signal during frame transmission in the half-duplex mode. - This request results in no errors generated because of Loss of Carrier or No Carrier during such transmission. -When this bit is low, the MAC transmitter generates such errors because of Carrier Sense and can even abort the transmissions. - 16 - 1 - read-write - - - PS - Port Select - This bit selects the Ethernet line speed. -- 0: For 1000 Mbps operations -- 1: For 10 or 100 Mbps operations In 10 or 100 Mbps operations, this bit, along with FES bit, selects the exact line speed. -In the 10/100 Mbps-only (always 1) or 1000 Mbps-only (always 0) configurations, this bit is read-only with the appropriate value. In default 10/100/1000 Mbps configuration, -this bit is R_W. The mac_portselect_o or mac_speed_o[1] signal reflects the value of this bit. - 15 - 1 - read-write - - - FES - Speed - This bit selects the speed in the MII, RMII, SMII, RGMII, SGMII, or RevMII interface: -- 0: 10 Mbps -- 1: 100 Mbps This bit is reserved (RO) by default and is enabled only when the parameter SPEED_SELECT = Enabled. -This bit generates link speed encoding when Bit 24 (TC) is set in the RGMII, SMII, or SGMII mode. -This bit is always enabled for RGMII, SGMII, SMII, or RevMII interface. -In configurations with RGMII, SGMII, SMII, or RevMII interface, this bit is driven as an output signal (mac_speed_o[0]) to reflect the value of this bit in the mac_speed_o signal. -In configurations with RMII, MII, or GMII interface, you can optionally drive this bit as an output signal (mac_speed_o[0]) to reflect its value in the mac_speed_o signal. - 14 - 1 - read-write - - - DO - Disable Receive Own - When this bit is set, the MAC disables the reception of frames when the phy_txen_o is asserted in the half-duplex mode. -When this bit is reset, the MAC receives all packets that are given by the PHY while transmitting. -This bit is not applicable if the MAC is operating in the full-duplex mode. This bit is reserved (RO with default value) if the MAC is configured for the full-duplex-only operation. - 13 - 1 - read-write - - - LM - Loopback Mode - When this bit is set, the MAC operates in the loopback mode at GMII or MII. -The (G)MII Receive clock input (clk_rx_i) is required for the loopback to work properly, because the Transmit clock is not looped-back internally. - 12 - 1 - read-write - - - DM - Duplex Mode - When this bit is set, the MAC operates in the full-duplex mode where it can transmit and receive simultaneously. - 11 - 1 - read-write - - - IPC - Checksum Offload -When this bit is set, the MAC calculates the 16-bit one’s complement of the one’s complement sum of all received Ethernet frame payloads. -It also checks whether the IPv4 Header checksum (assumed to be bytes 25–26 or 29–30 (VLAN-tagged) -of the received Ethernet frame) is correct for the received frame and gives the status in the receive status word. -The MAC also appends the 16-bit checksum calculated for the IP header datagram payload (bytes after the IPv4 header) -and appends it to the Ethernet frame transferred to the application (when Type 2 COE is deselected). -When this bit is reset, this function is disabled. -When Type 2 COE is selected, this bit, when set, enables the IPv4 header checksum checking and IPv4 or IPv6 TCP, UDP, or ICMP payload checksum checking. - 10 - 1 - read-write - - - DR - Disable Retry -When this bit is set, the MAC attempts only one transmission. -When a collision occurs on the GMII or MII interface, -the MAC ignores the current frame transmission and reports a Frame Abort with excessive collision error in the transmit frame status. -When this bit is reset, the MAC attempts retries based on the settings of the BL field (Bits [6:5]). - 9 - 1 - read-write - - - LUD - Link Up or Down - This bit indicates whether the link is up or down during the transmission of configuration in the RGMII, SGMII, or SMII interface: -- 0: Link Down -- 1: Link Up - 8 - 1 - read-write - - - ACS - Automatic Pad or CRC Stripping - When this bit is set, the MAC strips the Pad or FCS field on the incoming frames only if the value of the length field is less than 1,536 bytes. -All received frames with length field greater than or equal to 1,536 bytes are passed to the application without stripping the Pad or FCS field. -When this bit is reset, the MAC passes all incoming frames, without modifying them, to the Host. - 7 - 1 - read-write - - - BL - Back-Off Limit - The Back-Off limit determines the random integer number (r) of slot time delays - (4,096 bit times for 1000 Mbps and 512 bit times for 10/100 Mbps) for which the MAC waits before rescheduling a transmission attempt during retries after a collision. -This bit is applicable only in the half-duplex mode and is reserved (RO) in the full-duplex-only configuration. -- 00: k= min (n, 10) -- 01: k = min (n, 8) -- 10: k = min (n, 4) -- 11: k = min (n, 1) where n = retransmission attempt. The random integer r takes the value in the range 0 ≤ r < 2k - 5 - 2 - read-write - - - DC - Deferral Check - When this bit is set, the deferral check function is enabled in the MAC. -The MAC issues a Frame Abort status, along with the excessive deferral error bit set in the transmit frame status, -when the transmit state machine is deferred for more than 24,288 bit times in the 10 or 100 Mbps mode. - If the MAC is configured for 1000 Mbps operation or if the Jumbo frame mode is enabled in the 10 or 100 Mbps mode, - the threshold for deferral is 155,680 bits times. Deferral begins when the transmitter is ready to transmit, -but it is prevented because of an active carrier sense signal (CRS) on GMII or MII. The defer time is not cumulative. -For example, if the transmitter defers for 10,000 bit times because the CRS signal is active and then the CRS signal becomes inactive, -the transmitter transmits and collision happens. -Because of collision, the transmitter needs to back off and then defer again after back off completion. -In such a scenario, the deferral timer is reset to 0 and it is restarted. - 4 - 1 - read-write - - - TE - Transmitter Enable - When this bit is set, the transmit state machine of the MAC is enabled for transmission on the GMII or MII. When this bit is reset, - the MAC transmit state machine is disabled after the completion of the transmission of the current frame, and does not transmit any further frames. - 3 - 1 - read-write - - - RE - Receiver Enable - When this bit is set, the receiver state machine of the MAC is enabled for receiving frames from the GMII or MII. When this bit is reset, -the MAC receive state machine is disabled after the completion of the reception of the current frame, and does not receive any further frames from the GMII or MII. - 2 - 1 - read-write - - - PRELEN - Preamble Length for Transmit frames - These bits control the number of preamble bytes that are added to the beginning of every Transmit frame. - The preamble reduction occurs only when the MAC is operating in the full-duplex mode. -- 2'b00: 7 bytes of preamble -- 2'b01: 5 bytes of preamble -- 2'b10: 3 bytes of preamble -- 2'b11: Reserved - 0 - 2 - read-write - - - - - MACFF - MAC Frame Filter - 0x4 - 32 - 0x00000000 - 0x803087FF - - - RA - Receive All - When this bit is set, the MAC Receiver module passes all received frames, irrespective of whether they pass the address filter or not, to the Application. -The result of the SA or DA filtering is updated (pass or fail) in the corresponding bits in the Receive Status Word. When this bit is reset, -the Receiver module passes only those frames to the Application that pass the SA or DA address filter. - 31 - 1 - read-write - - - DNTU - Drop non-TCP/UDP over IP Frames - When set, this bit enables the MAC to drop the non-TCP or UDP over IP frames. The MAC forward only those frames that are processed by the Layer 4 filter. -When reset, this bit enables the MAC to forward all non-TCP or UDP over IP frames. - 21 - 1 - read-write - - - IPFE - Layer 3 and Layer 4 Filter Enable - When set, this bit enables the MAC to drop frames that do not match the enabled Layer 3 and Layer 4 filters. If Layer 3 or Layer 4 filters are not enabled for matching, -this bit does not have any effect. When reset, the MAC forwards all frames irrespective of the match status of the Layer 3 and Layer 4 fields. - 20 - 1 - read-write - - - VTFE - VLAN Tag Filter Enable - When set, this bit enables the MAC to drop VLAN tagged frames that do not match the VLAN Tag comparison. -When reset, the MAC forwards all frames irrespective of the match status of the VLAN Tag. - 15 - 1 - read-write - - - HPF - Hash or Perfect Filter - When this bit is set, it configures the address filter to pass a frame if it matches either the perfect filtering or the hash filtering as set by the HMC or HUC bits. -When this bit is low and the HUC or HMC bit is set, the frame is passed only if it matches the Hash filter. - 10 - 1 - read-write - - - SAF - Source Address Filter Enable - When this bit is set, the MAC compares the SA field of the received frames with the values programmed in the enabled SA registers. If the comparison fails, - the MAC drops the frame. When this bit is reset, the MAC forwards the received frame to the application with updated SAF bit of the Rx Status depending on the SA address comparison. - 9 - 1 - read-write - - - SAIF - SA Inverse Filtering -When this bit is set, the Address Check block operates in inverse filtering mode for the SA address comparison. The frames whose SA matches the SA registers are marked as failing the SA Address filter. -When this bit is reset, frames whose SA does not match the SA registers are marked as failing the SA Address filter. - 8 - 1 - read-write - - - PCF - Pass Control Frames - These bits control the forwarding of all control frames (including unicast and multicast Pause frames). -- 00: MAC filters all control frames from reaching the application. -- 01: MAC forwards all control frames except Pause frames to application even if they fail the Address filter. -- 10: MAC forwards all control frames to application even if they fail the Address Filter. -- 11: MAC forwards control frames that pass the Address Filter. -The following conditions should be true for the Pause frames processing: -- Condition 1: The MAC is in the full-duplex mode and flow control is enabled by setting Bit 2 (RFE) of Register 6 (Flow Control Register) to 1. -- Condition 2: The destination address (DA) of the received frame matches the special multicast address or the MAC Address 0 when Bit 3 (UP) of the Register 6 (Flow Control Register) is set. -- Condition 3: The Type field of the received frame is 0x8808 and the OPCODE field is 0x0001. -Note: This field should be set to 01 only when the Condition 1 is true, -that is, the MAC is programmed to operate in the full-duplex mode and the RFE bit is enabled. -Otherwise, the Pause frame filtering may be inconsistent. -When Condition 1 is false, the Pause frames are considered as generic control frames. -Therefore, to pass all control frames (including Pause frames) when the full-duplex mode and flow control is not enabled, -you should set the PCF field to 10 or 11 (as required by the application). - 6 - 2 - read-write - - - DBF - Disable Broadcast Frames - When this bit is set, the AFM module blocks all incoming broadcast frames. In addition, it overrides all other filter settings. -When this bit is reset, the AFM module passes all received broadcast frames. - 5 - 1 - read-write - - - PM - Pass All Multicast -When set, this bit indicates that all received frames with a multicast destination address (first bit in the destination address field is '1') are passed. -When reset, filtering of multicast frame depends on HMC bit. - 4 - 1 - read-write - - - DAIF - DA Inverse Filtering - When this bit is set, the Address Check block operates in inverse filtering mode for the DA address comparison for both unicast and multicast frames. -When reset, normal filtering of frames is performed. - 3 - 1 - read-write - - - HMC - Hash Multicast -When set, the MAC performs destination address filtering of received multicast frames according to the hash table. When reset, -the MAC performs a perfect destination address filtering for multicast frames, that is, it compares the DA field with the values programmed in DA registers. - 2 - 1 - read-write - - - HUC - Hash Unicast - When set, the MAC performs destination address filtering of unicast frames according to the hash table. -When reset, the MAC performs a perfect destination address filtering for unicast frames, that is, it compares the DA field with the values programmed in DA registers. - 1 - 1 - read-write - - - PR - Promiscuous Mode -When this bit is set, the Address Filter module passes all incoming frames irrespective of the destination or source address. - The SA or DA Filter Fails status bits of the Receive Status Word are always cleared when PR is set. - 0 - 1 - read-write - - - - - HASH_H - Hash Table High Register - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - HTH - Hash Table High - This field contains the upper 32 bits of the Hash table. - 0 - 32 - read-write - - - - - HASH_L - Hash Table Low Register - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - HTL - Hash Table Low - This field contains the lower 32 bits of the Hash table. - 0 - 32 - read-write - - - - - GMII_ADDR - GMII Address Register - 0x10 - 32 - 0x00000000 - 0x0000FFFF - - - PA - Physical Layer Address - This field indicates which of the 32 possible PHY devices are being accessed. For RevMII, this field gives the PHY Address of the RevMII module. - 11 - 5 - read-write - - - GR - GMII Register - These bits select the desired GMII register in the selected PHY device. For RevMII, these bits select the desired CSR register in the RevMII Registers set. - 6 - 5 - read-write - - - CR - CSR Clock Range - The CSR Clock Range selection determines the frequency of the MDC clock according to the CSR clock frequency used in your design. -The CSR clock corresponding to different GMAC configurations is given in Table 9-2 on page 564. -The suggested range of CSR clock frequency applicable for each value (when Bit[5] = 0) -ensures that the MDC clock is approximately between the frequency range 1.0 MHz–2.5 MHz. -- 0000: The CSR clock frequency is 60–100 MHz and the MDC clock frequency is CSR clock/42. -- 0001: The CSR clock frequency is 100–150 MHz and the MDC clock frequency is CSR clock/62. -- 0010: The CSR clock frequency is 20–35 MHz and the MDC clock frequency is CSR clock/16. -- 0011: The CSR clock frequency is 35–60 MHz and the MDC clock frequency is CSR clock/26. -- 0100: The CSR clock frequency is 150–250 MHz and the MDC clock frequency is CSR clock/102. -- 0101: The CSR clock frequency is 250–300 MHz and the MDC clock is CSR clock/124. -- 0110, 0111: Reserved -When Bit 5 is set, you can achieve higher frequency of the MDC clock than the frequency limit of 2.5 MHz (specified in the IEEE Std 802.3) and program a clock divider of lower value. -For example, -when CSR clock is of 100 MHz frequency and you program these bits as 1010, -then the resultant MDC clock is of 12.5 MHz which is outside the limit of IEEE 802.3 specified range. -Program the following values only if the interfacing chips support faster MDC clocks. -- 1000: CSR clock/4 -- 1001: CSR clock/6 -- 1010: CSR clock/8 -- 1011: CSR clock/10 -- 1100: CSR clock/12 -- 1101: CSR clock/14 -- 1110: CSR clock/16 -- 1111: CSR clock/18 These bits are not used for accessing RevMII. These bits are read-only if the RevMII interface is selected as single PHY interface. - 2 - 4 - read-write - - - GW - GMII Write - When set, this bit indicates to the PHY or RevMII that this is a Write operation using the GMII Data register. If this bit is not set, -it indicates that this is a Read operation, that is, placing the data in the GMII Data register. - 1 - 1 - read-write - - - GB - GMII Busy - This bit should read logic 0 before writing to Register 4 and Register 5. -During a PHY or RevMII register access, the software sets this bit to 1’b1 to indicate that a Read or Write access is in progress. - Register 5 is invalid until this bit is cleared by the MAC. -Therefore, Register 5 (GMII Data) should be kept valid until the MAC clears this bit during a PHY Write operation. -Similarly for a read operation, the contents of Register 5 are not valid until this bit is cleared. -The subsequent read or write operation should happen only after the previous operation is complete. -Because there is no acknowledgment from the PHY to MAC after a read or write operation is completed, -there is no change in the functionality of this bit even when the PHY is not present. - 0 - 1 - read-write - - - - - GMII_DATA - GMII Data Register - 0x14 - 32 - 0x00000000 - 0x0000FFFF - - - GD - GMII Data - This field contains the 16-bit data value read from the PHY or RevMII after a Management Read operation -or the 16-bit data value to be written to the PHY or RevMII before a Management Write operation. - 0 - 16 - read-write - - - - - FLOWCTRL - Flow Control Register - 0x18 - 32 - 0x00000000 - 0xFFFF00BF - - - PT - Pause Time - This field holds the value to be used in the Pause Time field in the transmit control frame. -If the Pause Time bits is configured to be double-synchronized to the (G)MII clock domain, - then consecutive writes to this register should be performed only after at least four clock cycles in the destination clock domain. - 16 - 16 - read-write - - - DZPQ - Disable Zero-Quanta Pause - When this bit is set, it disables the automatic generation of the Zero-Quanta Pause frames on the de-assertion of -the flow-control signal from the FIFO layer (MTL or external sideband flow control signal sbd_flowctrl_i/mti_flowctrl_i). -When this bit is reset, normal operation with automatic Zero-Quanta Pause frame generation is enabled. - 7 - 1 - read-write - - - PLT - Pause Low Threshold - This field configures the threshold of the Pause timer at which the input flow control signal mti_flowctrl_i (or sbd_flowctrl_i) is checked for automatic retransmission of the Pause frame. -The threshold values should be always less than the Pause Time configured in Bits[31:16]. - For example, if PT = 100H (256 slot-times), and PLT = 01, -then a second Pause frame is automatically transmitted if the mti_flowctrl_i signal is asserted at 228 (256 – 28) slot times after the first Pause frame is transmitted. -The following list provides the threshold values for different values: -- 00: The threshold is Pause time minus 4 slot times (PT – 4 slot times). -- 01: The threshold is Pause time minus 28 slot times (PT – 28 slot times). -- 10: The threshold is Pause time minus 144 slot times (PT – 144 slot times). -- 11: The threshold is Pause time minus 256 slot times (PT – 256 slot times). The slot time is defined as the time taken to transmit 512 bits (64 bytes) on the GMII or MII interface. - 4 - 2 - read-write - - - UP - Unicast Pause Frame Detect A pause frame is processed when it has the unique multicast address specified in the IEEE Std 802.3. -When this bit is set, the MAC can also detect Pause frames with unicast address of the station. -This unicast address should be as specified in the MAC Address0 High Register and MAC Address0 Low Register. -When this bit is reset, the MAC only detects Pause frames with unique multicast address. - 3 - 1 - read-write - - - RFE - Receive Flow Control Enable - When this bit is set, the MAC decodes the received Pause frame and disables its transmitter for a specified (Pause) time. When this bit is reset, the decode function of the Pause frame is disabled. - 2 - 1 - read-write - - - TFE - Transmit Flow Control Enable -In the full-duplex mode, when this bit is set, the MAC enables the flow control operation to transmit Pause frames. -When this bit is reset, the flow control operation in the MAC is disabled, and the MAC does not transmit any Pause frames. -In the half-duplex mode, when this bit is set, the MAC enables the backpressure operation. When this bit is reset, the backpressure feature is disabled. - 1 - 1 - read-write - - - FCB_BPA - Flow Control Busy or Backpressure Activate - This bit initiates a Pause frame in the full-duplex mode and activates the backpressure function in the half-duplex mode if the TFE bit is set. -In the full-duplex mode, this bit should be read as 1'b0 before writing to the Flow Control register. - To initiate a Pause frame, the Application must set this bit to 1'b1. -During a transfer of the Control Frame, this bit continues to be set to signify that a frame transmission is in progress. -After the completion of Pause frame transmission, the MAC resets this bit to 1'b0. -The Flow Control register should not be written to until this bit is cleared. In the half-duplex mode, -when this bit is set (and TFE is set), then backpressure is asserted by the MAC. -During backpressure, when the MAC receives a new frame, the transmitter starts sending a JAM pattern resulting in a collision. -This control register bit is logically ORed with the mti_flowctrl_i input signal for the backpressure function. -When the MAC is configured for the full-duplex mode, the BPA is automatically disabled. - 0 - 1 - read-write - - - - - VLAN_TAG - VLAN Tag Register - 0x1c - 32 - 0x00000000 - 0x000FFFFF - - - VTHM - VLAN Tag Hash Table Match Enable - When set, the most significant four bits of the VLAN tag’s CRC are used to index the content of Register 354 (VLAN Hash Table Register). -A value of 1 in the VLAN Hash Table register, corresponding to the index, indicates that the frame matched the VLAN hash table. -When Bit 16 (ETV) is set, the CRC of the 12-bit VLAN Identifier (VID) is used for comparison whereas when ETV is reset, -the CRC of the 16-bit VLAN tag is used for comparison. When reset, the VLAN Hash Match operation is not performed. - 19 - 1 - read-write - - - ESVL - Enable S-VLAN - When this bit is set, the MAC transmitter and receiver also consider the S-VLAN (Type = 0x88A8) frames as valid VLAN tagged frames. - 18 - 1 - read-write - - - VTIM - VLAN Tag Inverse Match Enable -When set, this bit enables the VLAN Tag inverse matching. The frames that do not have matching VLAN Tag are marked as matched. When reset, this bit enables the VLAN Tag perfect matching. - The frames with matched VLAN Tag are marked as matched. - 17 - 1 - read-write - - - ETV - Enable 12-Bit VLAN Tag Comparison - When this bit is set, a 12-bit VLAN identifier is used for comparing and filtering instead of the complete 16-bit VLAN tag. - Bits [11:0] of VLAN tag are compared with the corresponding field in the received VLAN-tagged frame. Similarly, when enabled, -only 12 bits of the VLAN tag in the received frame are used for hash-based VLAN filtering. -When this bit is reset, all 16 bits of the 15th and 16th bytes of the received VLAN frame are used for comparison and VLAN hash filtering. - 16 - 1 - read-write - - - VL - VLAN Tag Identifier for Receive Frames - This field contains the 802.1Q VLAN tag to identify the VLAN frames and is compared to the 15th and 16th bytes of the frames being received for VLAN frames. -The following list describes the bits of this field: - - Bits [15:13]: User Priority -- Bit 12: Canonical Format Indicator (CFI) or Drop Eligible Indicator (DEI) -- Bits[11:0]: VLAN tag’s VLAN Identifier (VID) field When the ETV bit is set, only the VID (Bits[11:0]) is used for comparison. - If VL (VL[11:0] if ETV is set) is all zeros, the MAC does not check the fifteenth and 16th bytes for VLAN tag comparison, - and declares all frames with a Type field value of 0x8100 or 0x88a8 as VLAN frames. - 0 - 16 - read-write - - - - - RWKFRMFILT - Remote Wake-Up Frame Filter Register - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - WKUPFRMFILT - This is the address through which the application writes or reads the remote wake-up frame filter registers (wkupfmfilter_reg). -The wkupfmfilter_reg register is a pointer to eight wkupfmfilter_reg registers. -The wkupfmfilter_reg register is loaded by sequentially loading the eight register values. -Eight sequential writes to this address (0x0028) write all wkupfmfilter_reg registers. - Similarly, eight sequential reads from this address (0x0028) read all wkupfmfilter_reg registers - 0 - 32 - read-write - - - - - PMT_CSR - PMT Control and Status Register - 0x2c - 32 - 0x00000000 - 0x9F000267 - - - RWKFILTRST - Remote Wake-Up Frame Filter Register Pointer Reset -When this bit is set, it resets the remote wake-up frame filter register pointer to 3’b000. It is automatically cleared after 1 clock cycle. - 31 - 1 - read-write - - - RWKPTR - Remote Wake-up FIFO Pointer -This field gives the current value (0 to 31) of the Remote Wake-up Frame filter register pointer. When the value of this pointer is equal to 7, 15, 23 or 31, -the contents of the Remote Wake-up Frame Filter Register are transferred to the clk_rx_i domain when a write occurs to that register. - The maximum value of the pointer is 7, 15, 23 and 31 respectively depending on the number of Remote Wakeup Filters selected during configuration. - 24 - 5 - read-write - - - GLBLUCAST - Global Unicast -When set, enables any unicast packet filtered by the MAC (DAF) address recognition to be a remote wake-up frame. - 9 - 1 - read-write - - - RWKPRCVD - Remote Wake-Up Frame Received -When set, this bit indicates the power management event is generated because of the reception of a remote wake-up frame. This bit is cleared by a Read into this register. - 6 - 1 - read-write - - - MGKPRCVD - Magic Packet Received -When set, this bit indicates that the power management event is generated because of the reception of a magic packet. This bit is cleared by a Read into this register. - 5 - 1 - read-write - - - RWKPKTEN - Remote Wake-Up Frame Enable -When set, enables generation of a power management event because of remote wake-up frame reception. - 2 - 1 - read-write - - - MGKPKTEN - Magic Packet Enable -When set, enables generation of a power management event because of magic packet reception. - 1 - 1 - read-write - - - PWRDWN - Power Down -When set, the MAC receiver drops all received frames until it receives the expected magic packet or remote wake-up frame. -This bit is then self-cleared and the power-down mode is disabled. -The Software can also clear this bit before the expected magic packet or remote wake-up frame is received. -The frames, received by the MAC after this bit is cleared, are forwarded to the application. -This bit must only be set when the Magic Packet Enable, Global Unicast, or Remote Wake-Upr Fame Enable bit is set high. -Note: You can gate-off the CSR clock during the power-down mode. -However, when the CSR clock is gated-off, you cannot perform any read or write operations on this register. Therefore, the Software cannot clear this bit. - 0 - 1 - read-write - - - - - LPI_CSR - LPI Control and Status Register - 0x30 - 32 - 0x00000000 - 0x000F030F - - - LPITXA - LPI TX Automate -This bit controls the behavior of the MAC when it is entering or coming out of the LPI mode on the transmit side. -This bit is not functional in the GMAC-CORE configuration in which the Tx clock gating is done during the LPI mode. If the LPITXA and LPIEN bits are set to 1, -the MAC enters the LPI mode only after all outstanding frames (in the core) and pending frames (in the application interface) have been transmitted. -The MAC comes out of the LPI mode when the application sends any frame for transmission or the application issues a TX FIFO Flush command. - In addition, the MAC automatically clears the LPIEN bit when it exits the LPI state. -If TX FIFO Flush is set in Bit 20 of Register 6 (Operation Mode Register), -when the MAC is in the LPI mode, the MAC exits the LPI mode. -When this bit is 0, the LPIEN bit directly controls behavior of the MAC when it is entering or coming out of the LPI mode. - 19 - 1 - read-write - - - PLSEN - PHY Link Status Enable -This bit enables the link status received on the RGMII, SGMII, or SMII receive paths to be used for activating the LPI LS TIMER. -When set, the MAC uses the link-status bits of Register 54 (SGMII/RGMII/SMII Control and Status Register) and Bit 17 (PLS) for the LPI LS Timer trigger. - When cleared, the MAC ignores the link-status bits of Register 54 and takes only the PLS bit. This bit is RO and reserved if you have not selected the RGMII, SGMII, or SMII PHY interface. - 18 - 1 - read-write - - - PLS - PHY Link Status -This bit indicates the link status of the PHY. The MAC Transmitter asserts the LPI pattern only when the link status is up (okay) at least for the time indicated by the LPI LS TIMER. -When set, the link is considered to be okay (up) and when reset, the link is considered to be down. - 17 - 1 - read-write - - - LPIEN - LPI Enable -When set, this bit instructs the MAC Transmitter to enter the LPI state. When reset, this bit instructs the MAC to exit the LPI state and resume normal transmission. -This bit is cleared when the LPITXA bit is set and the MAC exits the LPI state because of the arrival of a new packet for transmission. - 16 - 1 - read-write - - - RLPIST - Receive LPI State -When set, this bit indicates that the MAC is receiving the LPI pattern on the GMII or MII interface. - 9 - 1 - read-write - - - TLPIST - Transmit LPI State -When set, this bit indicates that the MAC is transmitting the LPI pattern on the GMII or MII interface. - 8 - 1 - read-write - - - RLPIEX - Receive LPI Exit -When set, this bit indicates that the MAC Receiver has stopped receiving the LPI pattern on the GMII or MII interface, exited the LPI state, and resumed the normal reception. -This bit is cleared by a read into this register. -Note: This bit may not get set if the MAC stops receiving the LPI pattern for a very short duration, such as, less than 3 clock cycles of CSR clock. - 3 - 1 - read-write - - - RLPIEN - Receive LPI Entry -When set, this bit indicates that the MAC Receiver has received an LPI pattern and entered the LPI state. This bit is cleared by a read into this register. -Note: This bit may not get set if the MAC stops receiving the LPI pattern for a very short duration, such as, less than 3 clock cycles of CSR clock. - 2 - 1 - read-write - - - TLPIEX - Transmit LPI Exit -When set, this bit indicates that the MAC transmitter has exited the LPI state after the user has cleared the LPIEN bit and the LPI TW Timer has expired. This bit is cleared by a read into this register. - 1 - 1 - read-write - - - TLPIEN - Transmit LPI Entry - When set, this bit indicates that the MAC Transmitter has entered the LPI state because of the setting of the LPIEN bit. This bit is cleared by a read into this register. - 0 - 1 - read-write - - - - - LPI_TCR - LPI Timers Control Register - 0x34 - 32 - 0x00000000 - 0x03FFFFFF - - - LST - LPI LS TIMER -This field specifies the minimum time (in milliseconds) for which the link status from the PHY should be up (OKAY) before the LPI pattern can be transmitted to the PHY. - The MAC does not transmit the LPI pattern even when the LPIEN bit is set unless the LPI LS Timer reaches the programmed terminal count. -The default value of the LPI LS Timer is 1000 (1 sec) as defined in the IEEE standard. - 16 - 10 - read-write - - - TWT - LPI TW TIMER -This field specifies the minimum time (in microseconds) for which the MAC waits after it stops transmitting - the LPI pattern to the PHY and before it resumes the normal transmission. -The TLPIEX status bit is set after the expiry of this timer. - 0 - 16 - read-write - - - - - INTR_STATUS - Interrupt Status Register - 0x38 - 32 - 0x00000000 - 0x00000EFF - - - GPIIS - GPI Interrupt Status -When the GPIO feature is enabled, this bit is set when any active event (LL or LH) occurs on the GPIS field (Bits [3:0]) - of Register 56 (General Purpose IO Register) and the corresponding GPIE bit is enabled. -This bit is cleared on reading lane 0 (GPIS) of Register 56 (General Purpose IO Register). - When the GPIO feature is not enabled, this bit is reserved. - 11 - 1 - read-only - - - LPIIS - LPI Interrupt Status -When the Energy Efficient Ethernet feature is enabled, this bit is set for any LPI state entry or exit in the MAC Transmitter or Receiver. -This bit is cleared on reading Bit 0 of Register 12 (LPI Control and Status Register). In all other modes, this bit is reserved. - 10 - 1 - read-only - - - TSIS - Timestamp Interrupt Status -When the Advanced Timestamp feature is enabled, this bit is set when any of the following conditions is true: -- The system time value equals or exceeds the value specified in the Target Time High and Low registers. -- There is an overflow in the seconds register. - - The Auxiliary snapshot trigger is asserted. This bit is cleared on reading Bit 0 of Register 458 (Timestamp Status Register). - 9 - 1 - read-only - - - MMCRXIPIS - MMC Receive Checksum Offload Interrupt Status -This bit is set high when an interrupt is generated in the MMC Receive Checksum Offload Interrupt Register. This bit is cleared when all the bits in this interrupt register are cleared. - 7 - 1 - read-only - - - MMCTXIS - MMC Transmit Interrupt Status -This bit is set high when an interrupt is generated in the MMC Transmit Interrupt Register. This bit is cleared when all the bits in this interrupt register are cleared. - 6 - 1 - read-only - - - MMCRXIS - MMC Receive Interrupt Status -This bit is set high when an interrupt is generated in the MMC Receive Interrupt Register. This bit is cleared when all the bits in this interrupt register are cleared. - 5 - 1 - read-only - - - MMCIS - MMC Interrupt Status -This bit is set high when any of the Bits [7:5] is set high and cleared only when all of these bits are low. - 4 - 1 - read-only - - - PMTIS - PMT Interrupt Status -This bit is set when a magic packet or remote wake-up frame is received in the power-down mode (see Bits 5 and 6 in the PMT Control and Status Register). -This bit is cleared when both Bits[6:5] are cleared because of a read operation to the PMT Control and Status register. - 3 - 1 - read-only - - - PCSANCIS - PCS Auto-Negotiation Complete -This bit is set when the Auto-negotiation is completed in the TBI, RTBI, or SGMII PHY interface (Bit 5 in Register 49 (AN Status Register)). -This bit is cleared when you perform a read operation to the AN Status register. - 2 - 1 - read-only - - - PCSLCHGIS - PCS Link Status Changed -This bit is set because of any change in Link Status in the TBI, RTBI, or SGMII PHY interface (Bit 2 in Register 49 (AN Status Register)). -This bit is cleared when you perform a read operation on the AN Status register. - 1 - 1 - read-only - - - RGSMIIIS - RGMII or SMII Interrupt Status -This bit is set because of any change in value of the Link Status of RGMII or SMII interface (Bit 3 in Register 54 (SGMII/RGMII/SMII Control and Status Register)). -This bit is cleared when you perform a read operation on the SGMII/RGMII/SMII Control and Status Register. - 0 - 1 - read-only - - - - - INTR_MASK - Interrupt Mask Register - 0x3c - 32 - 0x00000000 - 0x0000060F - - - LPIIM - LPI Interrupt Mask -When set, this bit disables the assertion of the interrupt signal because of the setting of the LPI Interrupt Status bit in Register 14 (Interrupt Status Register). - 10 - 1 - read-write - - - TSIM - Timestamp Interrupt Mask - When set, this bit disables the assertion of the interrupt signal because of the setting of Timestamp Interrupt Status bit in Register 14 (Interrupt Status Register). - 9 - 1 - read-write - - - PMTIM - PMT Interrupt Mask - When set, this bit disables the assertion of the interrupt signal because of the setting of PMT Interrupt Status bit in Register 14 (Interrupt Status Register). - 3 - 1 - read-write - - - PCSANCIM - PCS AN Completion Interrupt Mask -When set, this bit disables the assertion of the interrupt signal because of the setting of PCS Auto-negotiation complete bit in Register 14 (Interrupt Status Register). - 2 - 1 - read-write - - - PCSLCHGIM - PCS Link Status Interrupt Mask -When set, this bit disables the assertion of the interrupt signal because of the setting of the PCS Link-status changed bit in Register 14 (Interrupt Status Register). - 1 - 1 - read-write - - - RGSMIIIM - RGMII or SMII Interrupt Mask -When set, this bit disables the assertion of the interrupt signal because of the setting of the RGMII or SMII Interrupt Status bit in Register 14 (Interrupt Status Register). - 0 - 1 - read-write - - - - - MAC_ADDR_0_HIGH - MAC Address 0 High Register - 0x40 - 32 - 0x00000000 - 0x8000FFFF - - - AE - Address Enable - This bit is RO. The bit value is fixed at 1. - 31 - 1 - read-only - - - ADDRHI - MAC Address0 [47:32] - This field contains the upper 16 bits (47:32) of the first 6-byte MAC address. The MAC uses this field for filtering the received frames and inserting the MAC address in the Transmit Flow Control (Pause) Frames. - 0 - 16 - read-write - - - - - MAC_ADDR_0_LOW - MAC Address 0 Low Register - 0x44 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDRLO - MAC Address0 [31:0] - This field contains the lower 32 bits of the first 6-byte MAC address. This is used by the MAC for filtering the received frames and inserting the MAC address in the Transmit Flow Control (Pause) Frames. - 0 - 32 - read-write - - - - - 4 - 0x8 - 1,2,3,4 - MAC_ADDR[%s] - no description available - 0x48 - - HIGH - MAC Address High Register - 0x0 - 32 - 0x00000000 - 0xFF00FFFF - - - AE - Address Enable -When this bit is set, the address filter module uses the second MAC address for perfect filtering. When this bit is reset, the address filter module ignores the address for filtering. - 31 - 1 - read-write - - - SA - Source Address -When this bit is set, the MAC Address1[47:0] is used to compare with the SA fields of the received frame. When this bit is reset, the MAC Address1[47:0] is used to compare with the DA fields of the received frame. - 30 - 1 - read-write - - - MBC - Mask Byte Control -These bits are mask control bits for comparison of each of the MAC Address bytes. -When set high, the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. -Each bit controls the masking of the bytes as follows: -- Bit 29: Register 18[15:8] -- Bit 28: Register 18[7:0] -- Bit 27: Register 19[31:24] - -... -- Bit 24: Register 19[7:0] -You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address. - 24 - 6 - read-write - - - ADDRHI - MAC Address1 [47:32] -This field contains the upper 16 bits (47:32) of the second 6-byte MAC address. - 0 - 16 - read-write - - - - - LOW - MAC Address Low Register - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDRLO - MAC Address1 [31:0] -This field contains the lower 32 bits of the second 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process. - 0 - 32 - read-write - - - - - - XMII_CSR - SGMII/RGMII/SMII Control and Status Register - 0xd8 - 32 - 0x00000000 - 0x0000003F - - - FALSCARDET - False Carrier Detected - This bit indicates whether the SMII PHY detected false carrier (1'b1). This bit is reserved when the MAC is configured for the SGMII or RGMII PHY interface. - 5 - 1 - read-write - - - JABTO - Jabber Timeout - This bit indicates whether there is jabber timeout error (1'b1) in the received frame. This bit is reserved when the MAC is configured for the SGMII or RGMII PHY interface. - 4 - 1 - read-write - - - LNKSTS - Link Status - This bit indicates whether the link between the local PHY and the remote PHY is up or down. -It gives the status of the link between the SGMII of MAC and the SGMII of the local PHY. -The status bits are received from the local PHY during ANEG betweent he MAC and PHY on the SGMII link. - 3 - 1 - read-write - - - LNKSPEED - Link Speed - This bit indicates the current speed of the link: -- 00: 2.5 MHz -- 01: 25 MHz -- 10: 125 MHz Bit 2 is reserved when the MAC is configured for the SMII PHY interface. - 1 - 2 - read-write - - - LNKMOD - Link Mode - This bit indicates the current mode of operation of the link: -- 1’b0: Half-duplex mode -- 1’b1: Full-duplex mode - 0 - 1 - read-write - - - - - WDOG_WTO - Watchdog Timeout Register - 0xdc - 32 - 0x00000000 - 0x00013FFF - - - PWE - Programmable Watchdog Enable - When this bit is set and Bit 23 (WD) of Register 0 (MAC Configuration Register) is reset, -the WTO field (Bits[13:0]) is used as watchdog timeout for a received frame. -When this bit is cleared, the watchdog timeout for a received frame is controlled by the setting of Bit 23 (WD) and Bit 20 (JE) in Register 0 (MAC Configuration Register). - 16 - 1 - read-write - - - WTO - Watchdog Timeout -When Bit 16 (PWE) is set and Bit 23 (WD) of Register 0 (MAC Configuration Register) is reset, -this field is used as watchdog timeout for a received frame. - If the length of a received frame exceeds the value of this field, such frame is terminated and declared as an error frame. -Note: When Bit 16 (PWE) is set, the value in this field should be more than 1,522 (0x05F2). -Otherwise, the IEEE Std 802.3-specified valid tagged frames are declared as error frames and are dropped. - 0 - 14 - read-write - - - - - mmc_cntrl - MMC Control establishes the operating mode of MMC. - 0x100 - 32 - 0x00000000 - 0x0000013F - - - UCDBC - Update MMC Counters for Dropped Broadcast Frames -When set, the MAC updates all related MMC Counters for Broadcast frames that are dropped because of the setting of Bit 5 (DBF) of Register 1 (MAC Frame Filter). - When reset, the MMC Counters are not updated for dropped Broadcast frames. - 8 - 1 - read-write - - - CNTPRSTLVL - Full-Half Preset -When this bit is low and Bit 4 is set, all MMC counters get preset to almost-half value. All octet counters get preset to 0x7FFF_F800 (half -- 2KBytes) and all frame-counters gets preset to 0x7FFF_FFF0 (half -- 16). When this bit is high and Bit 4 is set, all MMC counters get preset to almost-full value. All octet counters get preset to 0xFFFF_F800 (full -- 2KBytes) and all frame-counters gets preset to 0xFFFF_FFF0 (full -- 16). For 16-bit counters, the almost-half preset values are 0x7800 and 0x7FF0 for the respective octet and frame counters. Similarly, the almost-full preset values for the 16-bit counters are 0xF800 and 0xFFF0. - 5 - 1 - read-write - - - CNTPRST - Counters Preset -When this bit is set, all counters are initialized or preset to almost full or almost half according to Bit 5. This bit is cleared automatically after 1 clock cycle. -This bit, along with Bit 5, is useful for debugging and testing the assertion of interrupts because of MMC counter becoming half-full or full. - 4 - 1 - read-write - - - CNTFREEZ - MMC Counter Freeze -When this bit is set, it freezes all MMC counters to their current value. -Until this bit is reset to 0, no MMC counter is updated because of any transmitted or received frame. - If any MMC counter is read with the Reset on Read bit set, then that counter is also cleared in this mode. - 3 - 1 - read-write - - - RSTONRD - Reset on Read -When this bit is set, the MMC counters are reset to zero after Read (self-clearing after reset). The counters are cleared when the least significant byte lane (Bits[7:0]) is read. - 2 - 1 - read-write - - - CNTSTOPRO - Counter Stop Rollover -When this bit is set, the counter does not roll over to zero after reaching the maximum value. - 1 - 1 - read-write - - - CNTRST - Counters Reset -When this bit is set, all counters are reset. This bit is cleared automatically after 1 clock cycle - 0 - 1 - read-write - - - - - mmc_intr_rx - MMC Receive Interrupt - 0x104 - 32 - 0x00000000 - 0x03FFFFFF - - - RXCTRLFIS - MMC Receive Control Frame Counter Interrupt Status -This bit is set when the rxctrlframes_g counter reaches half of the maximum value or the maximum value. - 25 - 1 - read-write - - - RXRCVERRFIS - MMC Receive Error Frame Counter Interrupt Status -This bit is set when the rxrcverror counter reaches half of the maximum value or the maximum value. - 24 - 1 - read-write - - - RXWDOGFIS - MMC Receive Watchdog Error Frame Counter Interrupt Status -This bit is set when the rxwatchdog error counter reaches half of the maximum value or the maximum value. - 23 - 1 - read-write - - - RXVLANGBFIS - MMC Receive VLAN Good Bad Frame Counter Interrupt Status -This bit is set when the rxvlanframes_gb counter reaches half of the maximum value or the maximum value. - 22 - 1 - read-write - - - RXFOVFIS - MMC Receive FIFO Overflow Frame Counter Interrupt Status -This bit is set when the rxfifooverflow counter reaches half of the maximum value or the maximum value. - 21 - 1 - read-write - - - RXPAUSFIS - MMC Receive Pause Frame Counter Interrupt Status -This bit is set when the rxpauseframes counter reaches half of the maximum value or the maximum value. - 20 - 1 - read-write - - - RXORANGEFIS - MMC Receive Out Of Range Error Frame Counter Interrupt Status. -This bit is set when the rxoutofrangetype counter reaches half of the maximum value or the maximum value. - 19 - 1 - read-write - - - RXLENERFIS - MMC Receive Length Error Frame Counter Interrupt Status -This bit is set when the rxlengtherror counter reaches half of the maximum value or the maximum value. - 18 - 1 - read-write - - - RXUCGFIS - MMC Receive Unicast Good Frame Counter Interrupt Status -This bit is set when the rxunicastframes_g counter reaches half of the maximum value or the maximum value. - 17 - 1 - read-write - - - RX1024TMAXOCTGBFIS - MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status. -This bit is set when the rx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. - 16 - 1 - read-write - - - RX512T1023OCTGBFIS - MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the rx512to1023octets_gb counter reaches half of the maximum value or the maximum value. - 15 - 1 - read-write - - - RX256T511OCTGBFIS - MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the rx256to511octets_gb counter reaches half of the maximum value or the maximum value. - 14 - 1 - read-write - - - RX128T255OCTGBFIS - MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the rx128to255octets_gb counter reaches half of the maximum value or the maximum value. - 13 - 1 - read-write - - - RX65T127OCTGBFIS - MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the rx65to127octets_gb counter reaches half of the maximum value or the maximum value. - 12 - 1 - read-write - - - RX64OCTGBFIS - MMC Receive 64 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the rx64octets_gb counter reaches half of the maximum value or the maximum value. - 11 - 1 - read-write - - - RXOSIZEGFIS - MMC Receive Oversize Good Frame Counter Interrupt Status -This bit is set when the rxoversize_g counter reaches half of the maximum value or the maximum value. - 10 - 1 - read-write - - - RXUSIZEGFIS - MMC Receive Undersize Good Frame Counter Interrupt Status -This bit is set when the rxundersize_g counter reaches half of the maximum value or the maximum value. - 9 - 1 - read-write - - - RXJABERFIS - MMC Receive Jabber Error Frame Counter Interrupt Status -This bit is set when the rxjabbererror counter reaches half of the maximum value or the maximum value. - 8 - 1 - read-write - - - RXRUNTFIS - MMC Receive Runt Frame Counter Interrupt Status -This bit is set when the rxrunterror counter reaches half of the maximum value or the maximum value. - 7 - 1 - read-write - - - RXALGNERFIS - MMC Receive Alignment Error Frame Counter Interrupt Status -This bit is set when the rxalignmenterror counter reaches half of the maximum value or the maximum value. - 6 - 1 - read-write - - - RXCRCERFIS - MMC Receive CRC Error Frame Counter Interrupt Status -This bit is set when the rxcrcerror counter reaches half of the maximum value or the maximum value. - 5 - 1 - read-write - - - RXMCGFIS - MMC Receive Multicast Good Frame Counter Interrupt Status -This bit is set when the rxmulticastframes_g counter reaches half of the maximum value or the maximum value. - 4 - 1 - read-write - - - RXBCGFIS - MMC Receive Broadcast Good Frame Counter Interrupt Status -This bit is set when the rxbroadcastframes_g counter reaches half of the maximum value or the maximum value. - 3 - 1 - read-write - - - RXGOCTIS - MMC Receive Good Octet Counter Interrupt Status -This bit is set when the rxoctetcount_g counter reaches half of the maximum value or the maximum value. - 2 - 1 - read-write - - - RXGBOCTIS - MMC Receive Good Bad Octet Counter Interrupt Status -This bit is set when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value. - 1 - 1 - read-write - - - RXGBFRMIS - MMC Receive Good Bad Frame Counter Interrupt Status -This bit is set when the rxframecount_gb counter reaches half of the maximum value or the maximum value. - 0 - 1 - read-write - - - - - mmc_intr_tx - MMC Transmit Interrupt - 0x108 - 32 - 0x00000000 - 0x03FFFFFF - - - TXOSIZEGFIS - MMC Transmit Oversize Good Frame Counter Interrupt Status -This bit is set when the txoversize_g counter reaches half of the maximum value or the maximum value. - 25 - 1 - read-write - - - TXVLANGFIS - MMC Transmit VLAN Good Frame Counter Interrupt Status -This bit is set when the txvlanframes_g counter reaches half of the maximum value or the maximum value. - 24 - 1 - read-write - - - TXPAUSFIS - MMC Transmit Pause Frame Counter Interrupt Status -This bit is set when the txpauseframeserror counter reaches half of the maximum value or the maximum value. - 23 - 1 - read-write - - - TXEXDEFFIS - MMC Transmit Excessive Deferral Frame Counter Interrupt Status -This bit is set when the txexcessdef counter reaches half of the maximum value or the maximum value. - 22 - 1 - read-write - - - TXGFRMIS - MMC Transmit Good Frame Counter Interrupt Status -This bit is set when the txframecount_g counter reaches half of the maximum value or the maximum value. - 21 - 1 - read-write - - - TXGOCTIS - MMC Transmit Good Octet Counter Interrupt Status -This bit is set when the txoctetcount_g counter reaches half of the maximum value or the maximum value. - 20 - 1 - read-write - - - TXCARERFIS - MMC Transmit Carrier Error Frame Counter Interrupt Status -This bit is set when the txcarriererror counter reaches half of the maximum value or the maximum value. - 19 - 1 - read-write - - - TXEXCOLFIS - MMC Transmit Excessive Collision Frame Counter Interrupt Status -This bit is set when the txexesscol counter reaches half of the maximum value or the maximum value. - 18 - 1 - read-write - - - TXLATCOLFIS - MMC Transmit Late Collision Frame Counter Interrupt Status -This bit is set when the txlatecol counter reaches half of the maximum value or the maximum value. - 17 - 1 - read-write - - - TXDEFFIS - MMC Transmit Deferred Frame Counter Interrupt Status -This bit is set when the txdeferred counter reaches half of the maximum value or the maximum value. - 16 - 1 - read-write - - - TXMCOLGFIS - MMC Transmit Multiple Collision Good Frame Counter Interrupt Status -This bit is set when the txmulticol_g counter reaches half of the maximum value or the maximum value. - 15 - 1 - read-write - - - TXSCOLGFIS - MMC Transmit Single Collision Good Frame Counter Interrupt Status -This bit is set when the txsinglecol_g counter reaches half of the maximum value or the maximum value. - 14 - 1 - read-write - - - TXUFLOWERFIS - MMC Transmit Underflow Error Frame Counter Interrupt Status -This bit is set when the txunderflowerror counter reaches half of the maximum value or the maximum value. - 13 - 1 - read-write - - - TXBCGBFIS - MMC Transmit Broadcast Good Bad Frame Counter Interrupt Status -This bit is set when the txbroadcastframes_gb counter reaches half of the maximum value or the maximum value. - 12 - 1 - read-write - - - TXMCGBFIS - MMC Transmit Multicast Good Bad Frame Counter Interrupt Status -The bit is set when the txmulticastframes_gb counter reaches half of the maximum value or the maximum value. - 11 - 1 - read-write - - - TXUCGBFIS - MMC Transmit Unicast Good Bad Frame Counter Interrupt Status -This bit is set when the txunicastframes_gb counter reaches half of the maximum value or the maximum value. - 10 - 1 - read-write - - - TX1024TMAXOCTGBFIS - MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status -This bit is set when the tx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. - 9 - 1 - read-write - - - TX512T1023OCTGBFIS - MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the tx512to1023octets_gb counter reaches half of the maximum value or the maximum value. - 8 - 1 - read-write - - - TX256T511OCTGBFIS - MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the tx256to511octets_gb counter reaches half of the maximum value or the maximum value. - 7 - 1 - read-write - - - TX128T255OCTGBFIS - MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the tx128to255octets_gb counter reaches half of the maximum value or the maximum value. - 6 - 1 - read-write - - - TX65T127OCTGBFIS - MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the tx65to127octets_gb counter reaches half the maximum value, and also when it reaches the maximum value. - 5 - 1 - read-write - - - TX64OCTGBFIS - MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the tx64octets_gb counter reaches half of the maximum value or the maximum value. - 4 - 1 - read-write - - - TXMCGFIS - MMC Transmit Multicast Good Frame Counter Interrupt Status -This bit is set when the txmulticastframes_g counter reaches half of the maximum value or the maximum value. - 3 - 1 - read-write - - - TXBCGFIS - MMC Transmit Broadcast Good Frame Counter Interrupt Status -This bit is set when the txbroadcastframes_g counter reaches half of the maximum value or the maximum value. - 2 - 1 - read-write - - - TXGBFRMIS - MMC Transmit Good Bad Frame Counter Interrupt Status -This bit is set when the txframecount_gb counter reaches half of the maximum value or the maximum value. - 1 - 1 - read-write - - - TXGBOCTIS - MMC Transmit Good Bad Octet Counter Interrupt Status -This bit is set when the txoctetcount_gb counter reaches half of the maximum value or the maximum value. - 0 - 1 - read-write - - - - - mmc_intr_mask_rx - MMC Receive Interrupt mask - 0x10c - 32 - 0x00000000 - 0x03FFFFFE - - - RXCTRLFIM - MMC Receive Control Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxctrlframes_g counter reaches half of the maximum value or the maximum value. - 25 - 1 - read-write - - - RXRCVERRFIM - MMC Receive Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxrcverror counter reaches half of the maximum value or the maximum value. - 24 - 1 - read-write - - - RXWDOGFIM - MMC Receive Watchdog Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxwatchdog counter reaches half of the maximum value or the maximum value. - 23 - 1 - read-write - - - RXVLANGBFIM - MMC Receive VLAN Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxvlanframes_gb counter reaches half of the maximum value or the maximum value. - 22 - 1 - read-write - - - RXFOVFIM - MMC Receive FIFO Overflow Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxfifooverflow counter reaches half of the maximum value or the maximum value. - 21 - 1 - read-write - - - RXPAUSFIM - MMC Receive Pause Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxpauseframes counter reaches half of the maximum value or the maximum value. - 20 - 1 - read-write - - - RXORANGEFIM - MMC Receive Out Of Range Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxoutofrangetype counter reaches half of the maximum value or the maximum value. - 19 - 1 - read-write - - - RXLENERFIM - MMC Receive Length Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxlengtherror counter reaches half of the maximum value or the maximum value. - 18 - 1 - read-write - - - RXUCGFIM - MMC Receive Unicast Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxunicastframes_g counter reaches half of the maximum value or the maximum value. - 17 - 1 - read-write - - - RX1024TMAXOCTGBFIM - MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask. -Setting this bit masks the interrupt when the rx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. - 16 - 1 - read-write - - - RX512T1023OCTGBFIM - MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rx512to1023octets_gb counter reaches half of the maximum value or the maximum value. - 15 - 1 - read-write - - - RX256T511OCTGBFIM - MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rx256to511octets_gb counter reaches half of the maximum value or the maximum value. - 14 - 1 - read-write - - - RX128T255OCTGBFIM - MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rx128to255octets_gb counter reaches half of the maximum value or the maximum value. - 13 - 1 - read-write - - - RX65T127OCTGBFIM - MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rx65to127octets_gb counter reaches half of the maximum value or the maximum value. - 12 - 1 - read-write - - - RX64OCTGBFIM - MMC Receive 64 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rx64octets_gb counter reaches half of the maximum value or the maximum value. - 11 - 1 - read-write - - - RXOSIZEGFIM - MMC Receive Oversize Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxoversize_g counter reaches half of the maximum value or the maximum value. - 10 - 1 - read-write - - - RXUSIZEGFIM - MMC Receive Undersize Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxundersize_g counter reaches half of the maximum value or the maximum value. - 9 - 1 - read-write - - - RXJABERFIM - MMC Receive Jabber Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxjabbererror counter reaches half of the maximum value or the maximum value. - 8 - 1 - read-write - - - RXRUNTFIM - MMC Receive Runt Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxrunterror counter reaches half of the maximum value or the maximum value. - 7 - 1 - read-write - - - RXALGNERFIM - MMC Receive Alignment Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxalignmenterror counter reaches half of the maximum value or the maximum value. - 6 - 1 - read-write - - - RXCRCERFIM - MMC Receive CRC Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxcrcerror counter reaches half of the maximum value or the maximum value. - 5 - 1 - read-write - - - RXMCGFIM - MMC Receive Multicast Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxmulticastframes_g counter reaches half of the maximum value or the maximum value. - 4 - 1 - read-write - - - RXBCGFIM - MMC Receive Broadcast Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxbroadcastframes_g counter reaches half of the maximum value or the maximum value. - 3 - 1 - read-write - - - RXGOCTIM - MMC Receive Good Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxoctetcount_g counter reaches half of the maximum value or the maximum value. - 2 - 1 - read-write - - - RXGBOCTIM - MMC Receive Good Bad Octet Counter Interrupt Mask. -Setting this bit masks the interrupt when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value. - 1 - 1 - read-write - - - - - mmc_intr_mask_tx - MMC Transmit Interrupt Mask - 0x110 - 32 - 0x00000000 - 0x03FFFFFF - - - TXOSIZEGFIM - MMC Transmit Oversize Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txoversize_g counter reaches half of the maximum value or the maximum value. - 25 - 1 - read-write - - - TXVLANGFIM - MMC Transmit VLAN Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txvlanframes_g counter reaches half of the maximum value or the maximum value. - 24 - 1 - read-write - - - TXPAUSFIM - MMC Transmit Pause Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txpauseframes counter reaches half of the maximum value or the maximum value. - 23 - 1 - read-write - - - TXEXDEFFIM - MMC Transmit Excessive Deferral Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txexcessdef counter reaches half of the maximum value or the maximum value. - 22 - 1 - read-write - - - TXGFRMIM - MMC Transmit Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txframecount_g counter reaches half of the maximum value or the maximum value. - 21 - 1 - read-write - - - TXGOCTIM - MMC Transmit Good Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the txoctetcount_g counter reaches half of the maximum value or the maximum value. - 20 - 1 - read-write - - - TXCARERFIM - MMC Transmit Carrier Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txcarriererror counter reaches half of the maximum value or the maximum value. - 19 - 1 - read-write - - - TXEXCOLFIM - MMC Transmit Excessive Collision Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txexcesscol counter reaches half of the maximum value or the maximum value. - 18 - 1 - read-write - - - TXLATCOLFIM - MMC Transmit Late Collision Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txlatecol counter reaches half of the maximum value or the maximum value. - 17 - 1 - read-write - - - TXDEFFIM - MMC Transmit Deferred Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txdeferred counter reaches half of the maximum value or the maximum value. - 16 - 1 - read-write - - - TXMCOLGFIM - MMC Transmit Multiple Collision Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txmulticol_g counter reaches half of the maximum value or the maximum value. - 15 - 1 - read-write - - - TXSCOLGFIM - MMC Transmit Single Collision Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txsinglecol_g counter reaches half of the maximum value or the maximum value. - 14 - 1 - read-write - - - TXUFLOWERFIM - MMC Transmit Underflow Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txunderflowerror counter reaches half of the maximum value or the maximum value. - 13 - 1 - read-write - - - TXBCGBFIM - MMC Transmit Broadcast Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txbroadcastframes_gb counter reaches half of the maximum value or the maximum value. - 12 - 1 - read-write - - - TXMCGBFIM - MMC Transmit Multicast Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txmulticastframes_gb counter reaches half of the maximum value or the maximum value. - 11 - 1 - read-write - - - TXUCGBFIM - MMC Transmit Unicast Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txunicastframes_gb counter reaches half of the maximum value or the maximum value. - 10 - 1 - read-write - - - TX1024TMAXOCTGBFIM - MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the tx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. - 9 - 1 - read-write - - - TX512T1023OCTGBFIM - MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the tx512to1023octets_gb counter reaches half of the maximum value or the maximum value. - 8 - 1 - read-write - - - TX256T511OCTGBFIM - MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the tx256to511octets_gb counter reaches half of the maximum value or the maximum value. - 7 - 1 - read-write - - - TX128T255OCTGBFIM - MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the tx128to255octets_gb counter reaches half of the maximum value or the maximum value. - 6 - 1 - read-write - - - TX65T127OCTGBFIM - MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the tx65to127octets_gb counter reaches half of the maximum value or the maximum value. - 5 - 1 - read-write - - - TX64OCTGBFIM - MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the tx64octets_gb counter reaches half of the maximum value or the maximum value. - 4 - 1 - read-write - - - TXMCGFIM - MMC Transmit Multicast Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txmulticastframes_g counter reaches half of the maximum value or the maximum value. - 3 - 1 - read-write - - - TXBCGFIM - MMC Transmit Broadcast Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txbroadcastframes_g counter reaches half of the maximum value or the maximum value. - 2 - 1 - read-write - - - TXGBFRMIM - MMC Transmit Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txframecount_gb counter reaches half of the maximum value or the maximum value. - 1 - 1 - read-write - - - TXGBOCTIM - MMC Transmit Good Bad Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the txoctetcount_gb counter reaches half of the maximum value or the maximum value. - 0 - 1 - read-write - - - - - tx64octets_gb - Number of good and bad frames transmitted with length 64 bytes, -exclusive of preamble and retried frames. - 0x124 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames transmitted with length 64 bytes, exclusive of preamble and retried frames. - 0 - 32 - read-write - - - - - tx65to127octets_gb - Number of good and bad frames transmitted with length between -65 and 127 (inclusive) bytes, exclusive of preamble and retried -frames. - 0x128 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames transmitted with length between 65 and 127 (inclusive) bytes, exclusive of preamble and retried frames. - 0 - 32 - read-write - - - - - tx128to255octets_gb - Number of good and bad frames transmitted with length between -128 and 255 (inclusive) bytes, exclusive of preamble and retried -frames. - 0x12c - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames transmitted with length between 128 and 255 (inclusive) bytes, exclusive of preamble and retried frames. - 0 - 32 - read-write - - - - - tx256to511octets_gb - Number of good and bad frames transmitted with length between -256 and 511 (inclusive) bytes, exclusive of preamble and retried -frames. - 0x130 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames transmitted with length between 256 and 511 (inclusive) bytes, exclusive of preamble and retried frames. - 0 - 32 - read-write - - - - - tx512to1023octets_gb - Number of good and bad frames transmitted with length between -512 and 1,023 (inclusive) bytes, exclusive of preamble and retried -frames. - 0x134 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames transmitted with length between 512 and 1,023 (inclusive) bytes, exclusive of preamble and retried frames. - 0 - 32 - read-write - - - - - tx1024tomaxoctets_gb - Number of good and bad frames transmitted with length between -1,024 and maxsize (inclusive) bytes, exclusive of preamble and -retried frames. - 0x138 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames transmitted with length between 1,024 and maxsize (inclusive) bytes, exclusive of preamble and retried frames. - 0 - 32 - read-write - - - - - rxframecount_gb - Number of good and bad frames received - 0x180 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames received. - 0 - 32 - read-write - - - - - mmc_ipc_intr_mask_rx - MMC IPC Receive Checksum Offload Interrupt Mask maintains -the mask for the interrupt generated from the receive IPC statistic -counters. - 0x200 - 32 - 0x00000000 - 0x3FFF3FFF - - - RXICMPEROIM - MMC Receive ICMP Error Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxicmp_err_octets counter reaches half of the maximum value or the maximum value. - 29 - 1 - read-write - - - RXICMPGOIM - MMC Receive ICMP Good Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxicmp_gd_octets counter reaches half of the maximum value or the maximum value. - 28 - 1 - read-write - - - RXTCPEROIM - MMC Receive TCP Error Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxtcp_err_octets counter reaches half of the maximum value or the maximum value. - 27 - 1 - read-write - - - RXTCPGOIM - MMC Receive TCP Good Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxtcp_gd_octets counter reaches half of the maximum value or the maximum value. - 26 - 1 - read-write - - - RXUDPEROIM - MMC Receive UDP Good Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxudp_err_octets counter reaches half of the maximum value or the maximum value. - 25 - 1 - read-write - - - RXUDPGOIM - MMC Receive IPV6 No Payload Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxudp_gd_octets counter reaches half of the maximum value or the maximum value. - 24 - 1 - read-write - - - RXIPV6NOPAYOIM - MMC Receive IPV6 Header Error Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv6_nopay_octets counter reaches half of the maximum value or the maximum value. - 23 - 1 - read-write - - - RXIPV6HEROIM - MMC Receive IPV6 Good Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum value. - 22 - 1 - read-write - - - RXIPV6GOIM - MMC Receive IPV6 Good Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv6_gd_octets counter reaches half of the maximum value or the maximum value. - 21 - 1 - read-write - - - RXIPV4UDSBLOIM - MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_udsbl_octets counter reaches half of the maximum value or the maximum value. - 20 - 1 - read-write - - - RXIPV4FRAGOIM - MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_frag_octets counter reaches half of the maximum value or the maximum value. - 19 - 1 - read-write - - - RXIPV4NOPAYOIM - MMC Receive IPV4 No Payload Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_nopay_octets counter reaches half of the maximum value or the maximum value. - 18 - 1 - read-write - - - RXIPV4HEROIM - MMC Receive IPV4 Header Error Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_hdrerr_octets counter reaches half of the maximum value or the maximum value. - 17 - 1 - read-write - - - RXIPV4GOIM - MMC Receive IPV4 Good Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_gd_octets counter reaches half of the maximum value or the maximum value. - 16 - 1 - read-write - - - RXICMPERFIM - MMC Receive ICMP Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxicmp_err_frms counter reaches half of the maximum value or the maximum value. - 13 - 1 - read-write - - - RXICMPGFIM - MMC Receive ICMP Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxicmp_gd_frms counter reaches half of the maximum value or the maximum value. - 12 - 1 - read-write - - - RXTCPERFIM - MMC Receive TCP Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxtcp_err_frms counter reaches half of the maximum value or the maximum value. - 11 - 1 - read-write - - - RXTCPGFIM - MMC Receive TCP Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxtcp_gd_frms counter reaches half of the maximum value or the maximum value. - 10 - 1 - read-write - - - RXUDPERFIM - MMC Receive UDP Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxudp_err_frms counter reaches half of the maximum value or the maximum value. - 9 - 1 - read-write - - - RXUDPGFIM - MMC Receive UDP Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxudp_gd_frms counter reaches half of the maximum value or the maximum value. - 8 - 1 - read-write - - - RXIPV6NOPAYFIM - MMC Receive IPV6 No Payload Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv6_nopay_frms counter reaches half of the maximum value or the maximum value. - 7 - 1 - read-write - - - RXIPV6HERFIM - MMC Receive IPV6 Header Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv6_hdrerr_frms counter reaches half of the maximum value or the maximum value. - 6 - 1 - read-write - - - RXIPV6GFIM - MMC Receive IPV6 Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv6_gd_frms counter reaches half of the maximum value or the maximum value. - 5 - 1 - read-write - - - RXIPV4UDSBLFIM - MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_udsbl_frms counter reaches half of the maximum value or the maximum value. - 4 - 1 - read-write - - - RXIPV4FRAGFIM - MMC Receive IPV4 Fragmented Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_frag_frms counter reaches half of the maximum value or the maximum value. - 3 - 1 - read-write - - - RXIPV4NOPAYFIM - MMC Receive IPV4 No Payload Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_nopay_frms counter reaches half of the maximum value or the maximum value. - 2 - 1 - read-write - - - RXIPV4HERFIM - MMC Receive IPV4 Header Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_hdrerr_frms counter reaches half of the maximum value or the maximum value. - 1 - 1 - read-write - - - RXIPV4GFIM - MMC Receive IPV4 Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_gd_frms counter reaches half of the maximum value or the maximum value. - 0 - 1 - read-write - - - - - mmc_ipc_intr_rx - MMC Receive Checksum Offload Interrupt maintains the interrupt -that the receive IPC statistic counters generate. See Table 4-25 -for further detail. - 0x208 - 32 - 0x00000000 - 0x3FFF3FFF - - - RXICMPEROIS - MMC Receive ICMP Error Octet Counter Interrupt Status -This bit is set when the rxicmp_err_octets counter reaches half of the maximum value or the maximum value. - 29 - 1 - read-write - - - RXICMPGOIS - MMC Receive ICMP Good Octet Counter Interrupt Status -This bit is set when the rxicmp_gd_octets counter reaches half of the maximum value or the maximum value. - 28 - 1 - read-write - - - RXTCPEROIS - MMC Receive TCP Error Octet Counter Interrupt Status -This bit is set when the rxtcp_err_octets counter reaches half of the maximum value or the maximum value. - 27 - 1 - read-write - - - RXTCPGOIS - MMC Receive TCP Good Octet Counter Interrupt Status -This bit is set when the rxtcp_gd_octets counter reaches half of the maximum value or the maximum value - 26 - 1 - read-write - - - RXUDPEROIS - MMC Receive UDP Error Octet Counter Interrupt Status -This bit is set when the rxudp_err_octets counter reaches half of the maximum value or the maximum value. - 25 - 1 - read-write - - - RXUDPGOIS - MMC Receive UDP Good Octet Counter Interrupt Status -This bit is set when the rxudp_gd_octets counter reaches half of the maximum value or the maximum value. - 24 - 1 - read-write - - - RXIPV6NOPAYOIS - MMC Receive IPV6 No Payload Octet Counter Interrupt Status -This bit is set when the rxipv6_nopay_octets counter reaches half of the maximum value or the maximum value. - 23 - 1 - read-write - - - RXIPV6HEROIS - MMC Receive IPV6 Header Error Octet Counter Interrupt Status -This bit is set when the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum value. - 22 - 1 - read-write - - - RXIPV6GOIS - MMC Receive IPV6 Good Octet Counter Interrupt Status -This bit is set when the rxipv6_gd_octets counter reaches half of the maximum value or the maximum value. - 21 - 1 - read-write - - - RXIPV4UDSBLOIS - MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status -This bit is set when the rxipv4_udsbl_octets counter reaches half of the maximum value or the maximum value. - 20 - 1 - read-write - - - RXIPV4FRAGOIS - MMC Receive IPV4 Fragmented Octet Counter Interrupt Status -This bit is set when the rxipv4_frag_octets counter reaches half of the maximum value or the maximum value. - 19 - 1 - read-write - - - RXIPV4NOPAYOIS - MMC Receive IPV4 No Payload Octet Counter Interrupt Status -This bit is set when the rxipv4_nopay_octets counter reaches half of the maximum value or the maximum value. - 18 - 1 - read-write - - - RXIPV4HEROIS - MMC Receive IPV4 Header Error Octet Counter Interrupt Status -This bit is set when the rxipv4_hdrerr_octets counter reaches half of the maximum value or the maximum value. - 17 - 1 - read-write - - - RXIPV4GOIS - MMC Receive IPV4 Good Octet Counter Interrupt Status -This bit is set when the rxipv4_gd_octets counter reaches half of the maximum value or the maximum value. - 16 - 1 - read-write - - - RXICMPERFIS - MMC Receive ICMP Error Frame Counter Interrupt Status -This bit is set when the rxicmp_err_frms counter reaches half of the maximum value or the maximum value. - 13 - 1 - read-write - - - RXICMPGFIS - MMC Receive ICMP Good Frame Counter Interrupt Status -This bit is set when the rxicmp_gd_frms counter reaches half of the maximum value or the maximum value. - 12 - 1 - read-write - - - RXTCPERFIS - MMC Receive TCP Error Frame Counter Interrupt Status -This bit is set when the rxtcp_err_frms counter reaches half of the maximum value or the maximum value. - 11 - 1 - read-write - - - RXTCPGFIS - MMC Receive TCP Good Frame Counter Interrupt Status -This bit is set when the rxtcp_gd_frms counter reaches half of the maximum value or the maximum value. - 10 - 1 - read-write - - - RXUDPERFIS - MMC Receive UDP Error Frame Counter Interrupt Status -This bit is set when the rxudp_err_frms counter reaches half of the maximum value or the maximum value. - 9 - 1 - read-write - - - RXUDPGFIS - MMC Receive UDP Good Frame Counter Interrupt Status -This bit is set when the rxudp_gd_frms counter reaches half of the maximum value or the maximum value. - 8 - 1 - read-write - - - RXIPV6NOPAYFIS - MMC Receive IPV6 No Payload Frame Counter Interrupt Status -This bit is set when the rxipv6_nopay_frms counter reaches half of the maximum value or the maximum value. - 7 - 1 - read-write - - - RXIPV6HERFIS - MMC Receive IPV6 Header Error Frame Counter Interrupt Status -This bit is set when the rxipv6_hdrerr_frms counter reaches half of the maximum value or the maximum value. - 6 - 1 - read-write - - - RXIPV6GFIS - MMC Receive IPV6 Good Frame Counter Interrupt Status -This bit is set when the rxipv6_gd_frms counter reaches half of the maximum value or the maximum value. - 5 - 1 - read-write - - - RXIPV4UDSBLFIS - MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Status -This bit is set when the rxipv4_udsbl_frms counter reaches half of the maximum value or the maximum value. - 4 - 1 - read-write - - - RXIPV4FRAGFIS - MMC Receive IPV4 Fragmented Frame Counter Interrupt Status -This bit is set when the rxipv4_frag_frms counter reaches half of the maximum value or the maximum value. - 3 - 1 - read-write - - - RXIPV4NOPAYFIS - MMC Receive IPV4 No Payload Frame Counter Interrupt Status -This bit is set when the rxipv4_nopay_frms counter reaches half of the maximum value or the maximum value. - 2 - 1 - read-write - - - RXIPV4HERFIS - MMC Receive IPV4 Header Error Frame Counter Interrupt Status -This bit is set when the rxipv4_hdrerr_frms counter reaches half of the maximum value or the maximum value. - 1 - 1 - read-write - - - RXIPV4GFIS - MMC Receive IPV4 Good Frame Counter Interrupt Status -This bit is set when the rxipv4_gd_frms counter reaches half of the maximum value or the maximum value. - 0 - 1 - read-write - - - - - rxipv4_gd_fms - Number of good IPv4 datagrams received with the TCP, UDP, or -ICMP payload - 0x210 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good IPv4 datagrams received with the TCP, UDP, or ICMP payload - 0 - 32 - read-write - - - - - 1 - 0x20 - 0 - L3_L4_CFG[%s] - no description available - 0x400 - - L3_L4_CTRL - Layer 3 and Layer 4 Control Register - 0x0 - 32 - 0x00000000 - 0x003DFFFD - - - L4DPIM0 - Layer 4 Destination Port Inverse Match Enable - When set, this bit indicates that the Layer 4 Destination Port number field is enabled for inverse matching. -When reset, this bit indicates that the Layer 4 Destination Port number field is enabled for perfect matching. - This bit is valid and applicable only when Bit 20 (L4DPM0) is set high. - 21 - 1 - read-write - - - L4DPM0 - Layer 4 Destination Port Match Enable - When set, this bit indicates that the Layer 4 Destination Port number field is enabled for matching. -When reset, the MAC ignores the Layer 4 Destination Port number field for matching. - 20 - 1 - read-write - - - L4SPIM0 - Layer 4 Source Port Inverse Match Enable -When set, this bit indicates that the Layer 4 Source Port number field is enabled for inverse matching. -When reset, this bit indicates that the Layer 4 Source Port number field is enabled for perfect matching. -This bit is valid and applicable only when Bit 18 (L4SPM0) is set high. - 19 - 1 - read-write - - - L4SPM0 - Layer 4 Source Port Match Enable -When set, this bit indicates that the Layer 4 Source Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Source Port number field for matching. - 18 - 1 - read-write - - - L4PEN0 - Layer 4 Protocol Enable -When set, this bit indicates that the Source and Destination Port number fields for UDP frames are used for matching. -When reset, this bit indicates that the Source and Destination Port number fields for TCP frames are used for matching. -The Layer 4 matching is done only when either L4SPM0 or L4DPM0 bit is set high. - 16 - 1 - read-write - - - L3HDBM0 - Layer 3 IP DA Higher Bits Match - IPv4 Frames: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 frames. The following list describes the values of this field: -- 0: No bits are masked. -- 1: LSb[0] is masked. -- 2: Two LSbs [1:0] are masked. - ... -- 31: All bits except MSb are masked. IPv6 Frames: Bits [12:11] of this field correspond to Bits [6:5] of L3HSBM0, -which indicate the number of lower bits of IP Source or Destination Address that are masked in the IPv6 frames. -The following list describes the concatenated values of the L3HDBM0[1:0] and L3HSBM0 bits: -- 0: No bits are masked. -- 1: LSb[0] is masked. -- 2: Two LSbs [1:0] are masked. - … -- 127: All bits except MSb are masked. This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. - 11 - 5 - read-write - - - L3HSBM0 - Layer 3 IP SA Higher Bits Match - IPv4 Frames: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 frames. The following list describes the values of this field: -- 0: No bits are masked. -- 1: LSb[0] is masked. -- 2: Two LSbs [1:0] are masked. - ... -- 31: All bits except MSb are masked. IPv6 Frames: This field contains Bits [4:0] of the field that indicates the number of higher bits of IP Source or Destination Address matched in the IPv6 frames. -This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. - 6 - 5 - read-write - - - L3DAIM0 - Layer 3 IP DA Inverse Match Enable -When set, this bit indicates that the Layer 3 IP Destination Address field is enabled for inverse matching. -When reset, this bit indicates that the Layer 3 IP Destination Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 4 (L3DAM0) is set high. - 5 - 1 - read-write - - - L3DAM0 - Layer 3 IP DA Match Enable -When set, this bit indicates that Layer 3 IP Destination Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Destination Address field for matching. -Note: When Bit 0 (L3PEN0) is set, you should set either this bit or Bit 2 (L3SAM0) because either IPv6 DA or SA can be checked for filtering. - 4 - 1 - read-write - - - L3SAIM0 - Layer 3 IP SA Inverse Match Enable -When set, this bit indicates that the Layer 3 IP Source Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Source Address field is enabled for perfect matching. -This bit is valid and applicable only when Bit 2 (L3SAM0) is set high. - 3 - 1 - read-write - - - L3SAM0 - Layer 3 IP SA Match Enable -When set, this bit indicates that the Layer 3 IP Source Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Source Address field for matching. - 2 - 1 - read-write - - - L3PEN0 - Layer 3 Protocol Enable - When set, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv6 frames. -When reset, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv4 frames. -The Layer 3 matching is done only when either L3SAM0 or L3DAM0 bit is set high. - 0 - 1 - read-write - - - - - L4_Addr - Layer 4 Address Register - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - L4DP0 - Layer 4 Destination Port Number Field -When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), -this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 frames. -When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), -this field contains the value to be matched with the UDP Destination Port Number field in the IPv4 or IPv6 frames. - 16 - 16 - read-write - - - L4SP0 - Layer 4 Source Port Number Field - When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), - this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 frames. -When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), -this field contains the value to be matched with the UDP Source Port Number field in the IPv4 or IPv6 frames. - 0 - 16 - read-write - - - - - L3_Addr_0 - Layer 3 Address 0 Register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - L3A00 - Layer 3 Address 0 Field - When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), -this field contains the value to be matched with Bits [31:0] of the IP Source Address field in the IPv6 frames. -When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), -this field contains the value to be matched with Bits [31:0] of the IP Destination Address field in the IPv6 frames. -When Bit 0 (L3PEN0) is reset and Bit 2 (L3SAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), -this field contains the value to be matched with the IP Source Address field in the IPv4 frames. - 0 - 32 - read-write - - - - - L3_Addr_1 - Layer 3 Address 1 Register - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - L3A10 - Layer 3 Address 1 Field - When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), -this field contains the value to be matched with Bits [63:32] of the IP Source Address field in the IPv6 frames. -When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), -this field contains the value to be matched with Bits [63:32] of the IP Destination Address field in the IPv6 frames. -When Bit 0 (L3PEN0) is reset and Bit 4 (L3DAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), - this field contains the value to be matched with the IP Destination Address field in the IPv4 frames. - 0 - 32 - read-write - - - - - L3_Addr_2 - Layer 3 Address 2 Register - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - L3A20 - Layer 3 Address 2 Field - When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), -this field contains the value to be matched with Bits [95:64] of the IP Source Address field in the IPv6 frames. -When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), -this field contains value to be matched with Bits [95:64] of the IP Destination Address field in the IPv6 frames. -When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. - 0 - 32 - read-write - - - - - L3_Addr_3 - Layer 3 Address 3 Register - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - L3A30 - Layer 3 Address 3 Field When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), -this field contains the value to be matched with Bits [127:96] of the IP Source Address field in the IPv6 frames. - When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), -this field contains the value to be matched with Bits [127:96] of the IP Destination Address field in the IPv6 frames. -When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. - 0 - 32 - read-write - - - - - - VLAN_TAG_INC_RPL - VLAN Tag Inclusion or Replacement Register - 0x584 - 32 - 0x00000000 - 0x000FFFFF - - - CSVL - C-VLAN or S-VLAN - When this bit is set, S-VLAN type (0x88A8) is inserted or replaced in the 13th and 14th bytes of transmitted frames. When this bit is reset, C-VLAN type (0x8100) is inserted or replaced in the transmitted frames. - 19 - 1 - read-write - - - VLP - VLAN Priority Control -When this bit is set, the control Bits [17:16] are used for VLAN deletion, insertion, or replacement. When this bit is reset, the mti_vlan_ctrl_i control input is used, and Bits [17:16] are ignored. - 18 - 1 - read-write - - - VLC - VLAN Tag Control in Transmit Frames -- 2’b00: No VLAN tag deletion, insertion, or replacement -- 2’b01: VLAN tag deletion The MAC removes the VLAN type (bytes 13 and 14) and VLAN tag (bytes 15 and 16) of all transmitted frames with VLAN tags. -- 2’b10: VLAN tag insertion The MAC inserts VLT in bytes 15 and 16 of the frame after inserting the Type value (0x8100/0x88a8) in bytes 13 and 14. -This operation is performed on all transmitted frames, irrespective of whether they already have a VLAN tag. -- 2’b11: VLAN tag replacement The MAC replaces VLT in bytes 15 and 16 of all VLAN-type transmitted frames (Bytes 13 and 14 are 0x8100/0x88a8). -Note: Changes to this field take effect only on the start of a frame. -If you write this register field when a frame is being transmitted, only the subsequent frame can use the updated value, that is, the current frame does not use the updated value. - 16 - 2 - read-write - - - VLT - VLAN Tag for Transmit Frames - This field contains the value of the VLAN tag to be inserted or replaced. The value must only be changed when the transmit lines are inactive or during the initialization phase. - Bits[15:13] are the User Priority, Bit 12 is the CFI/DEI, and Bits[11:0] are the VLAN tag’s VID field. - 0 - 16 - read-write - - - - - VLAN_HASH - VLAN Hash Table Register - 0x588 - 32 - 0x00000000 - 0x0000FFFF - - - VLHT - VLAN Hash Table - This field contains the 16-bit VLAN Hash Table. - 0 - 16 - read-write - - - - - TS_CTRL - Timestamp Control Register - 0x700 - 32 - 0x00000000 - 0x1F07FF3F - - - ATSEN3 - Auxiliary Snapshot 3 Enable -This field controls capturing the Auxiliary Snapshot Trigger 3. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[3] input is enabled. When this bit is reset, the events on this input are ignored. -This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration or the selected number in the Number of IEEE 1588 Auxiliary Snapshot Inputs option is less than four. - 28 - 1 - read-write - - - ATSEN2 - Auxiliary Snapshot 2 Enable -This field controls capturing the Auxiliary Snapshot Trigger 2. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[2] input is enabled. When this bit is reset, the events on this input are ignored. -This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration or the selected number in the Number of IEEE 1588 Auxiliary Snapshot Inputs option is less than three. - 27 - 1 - read-write - - - ATSEN1 - Auxiliary Snapshot 1 Enable -This field controls capturing the Auxiliary Snapshot Trigger 1. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[1] input is enabled. When this bit is reset, the events on this input are ignored. -This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration or the selected number in the Number of IEEE 1588 Auxiliary Snapshot Inputs option is less than two. - 26 - 1 - read-write - - - ATSEN0 - Auxiliary Snapshot 0 Enable -This field controls capturing the Auxiliary Snapshot Trigger 0. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[0] input is enabled. When this bit is reset, the events on this input are ignored. - 25 - 1 - read-write - - - ATSFC - Auxiliary Snapshot FIFO Clear -When set, it resets the pointers of the Auxiliary Snapshot FIFO. This bit is cleared when the pointers are reset and the FIFO is empty. When this bit is high, auxiliary snapshots get stored in the FIFO. -This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration. - 24 - 1 - read-write - - - TSENMACADDR - Enable MAC address for PTP Frame Filtering -When set, the DA MAC address (that matches any MAC Address register) is used to filter the PTP frames when PTP is directly sent over Ethernet. - 18 - 1 - read-write - - - SNAPTYPSEL - Select PTP packets for Taking Snapshots - These bits along with Bits 15 and 14 decide the set of PTP packet types for which snapshot needs to be taken. - 16 - 2 - read-write - - - TSMSTRENA - Enable Snapshot for Messages Relevant to Master -When set, the snapshot is taken only for the messages relevant to the master node. Otherwise, the snapshot is taken for the messages relevant to the slave node. - 15 - 1 - read-write - - - TSEVNTENA - Enable Timestamp Snapshot for Event Messages -When set, the timestamp snapshot is taken only for event messages (SYNC, Delay_Req, Pdelay_Req, or Pdelay_Resp). When reset, the snapshot is taken for all messages except Announce, Management, and Signaling. - 14 - 1 - read-write - - - TSIPV4ENA - Enable Processing of PTP Frames Sent over IPv4-UDP - When set, the MAC receiver processes the PTP packets encapsulated in UDP over IPv4 packets. When this bit is clear, the MAC ignores the PTP transported over UDP-IPv4 packets. This bit is set by default. - 13 - 1 - read-write - - - TSIPV6ENA - Enable Processing of PTP Frames Sent over IPv6-UDP -When set, the MAC receiver processes PTP packets encapsulated in UDP over IPv6 packets. When this bit is clear, the MAC ignores the PTP transported over UDP-IPv6 packets. - 12 - 1 - read-write - - - TSIPENA - Enable Processing of PTP over Ethernet Frames -When set, the MAC receiver processes the PTP packets encapsulated directly in the Ethernet frames. When this bit is clear, the MAC ignores the PTP over Ethernet packets - 11 - 1 - read-write - - - TSVER2ENA - Enable PTP packet Processing for Version 2 Format -When set, the PTP packets are processed using the 1588 version 2 format. Otherwise, the PTP packets are processed using the version 1 format. - 10 - 1 - read-write - - - TSCTRLSSR - Timestamp Digital or Binary Rollover Control -When set, the Timestamp Low register rolls over after 0x3B9A_C9FF value (that is, 1 nanosecond accuracy) and increments the timestamp (High) seconds. - When reset, the rollover value of sub-second register is 0x7FFF_FFFF. -The sub-second increment has to be programmed correctly depending on the PTP reference clock frequency and the value of this bit. - 9 - 1 - read-write - - - TSENALL - Enable Timestamp for All Frames -When set, the timestamp snapshot is enabled for all frames received by the MAC. - 8 - 1 - read-write - - - TSADDREG - Addend Reg Update -When set, the content of the Timestamp Addend register is updated in the PTP block for fine correction. This is cleared when the update is completed. -This register bit should be zero before setting it. - 5 - 1 - read-write - - - TSTRIG - Timestamp Interrupt Trigger Enable -When set, the timestamp interrupt is generated when the System Time becomes greater than the value written in the Target Time register. -This bit is reset after the generation of the Timestamp Trigger Interrupt. - 4 - 1 - read-write - - - TSUPDT - Timestamp Update -When set, the system time is updated (added or subtracted) with the value specified in Register 452 (System Time – Seconds Update Register) -and Register 453 (System Time – Nanoseconds Update Register). This bit should be read zero before updating it. -This bit is reset when the update is completed in hardware. The “Timestamp Higher Word” register (if enabled during core configuration) is not updated. - 3 - 1 - read-write - - - TSINIT - Timestamp Initialize -When set, the system time is initialized (overwritten) with the value specified in the Register 452 (System Time – Seconds Update Register) -and Register 453 (System Time – Nanoseconds Update Register). This bit should be read zero before updating it. -This bit is reset when the initialization is complete. -The “Timestamp Higher Word” register (if enabled during core configuration) can only be initialized. - 2 - 1 - read-write - - - TSCFUPDT - Timestamp Fine or Coarse Update -When set, this bit indicates that the system times update should be done using the fine update method. When reset, it indicates the system timestamp update should be done using the Coarse method. - 1 - 1 - read-write - - - TSENA - Timestamp Enable -When set, the timestamp is added for the transmit and receive frames. When disabled, timestamp is not added for the transmit and receive frames and the Timestamp Generator is also suspended. -You need to initialize the Timestamp (system time) after enabling this mode. On the receive side, the MAC processes the 1588 frames only if this bit is set. - 0 - 1 - read-write - - - - - SUB_SEC_INCR - Sub-Second Increment Register - 0x704 - 32 - 0x00000000 - 0x000000FF - - - SSINC - Sub-second Increment Value -The value programmed in this field is accumulated every clock cycle (of clk_ptp_i) with the contents of the sub-second register. -For example, when PTP clock is 50 MHz (period is 20 ns), you should program 20 (0x14) -when the System Time- Nanoseconds register has an accuracy of 1 ns [Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register)]. -When TSCTRLSSR is clear, the Nanoseconds register has a resolution of ~0.465ns. -In this case, you should program a value of 43 (0x2B) that is derived by 20ns/0.465. - 0 - 8 - read-write - - - - - SYST_SEC - System Time - Seconds Register - 0x708 - 32 - 0x00000000 - 0xFFFFFFFF - - - TSS - Timestamp Second - The value in this field indicates the current value in seconds of the System Time maintained by the MAC. - 0 - 32 - read-only - - - - - SYST_NSEC - System Time - Nanoseconds Register - 0x70c - 32 - 0x00000000 - 0x7FFFFFFF - - - TSSS - Timestamp Sub Seconds - The value in this field has the sub second representation of time, with an accuracy of 0.46 ns. -When Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register), each bit represents 1 ns and the maximum value is 0x3B9A_C9FF, after which it rolls-over to zero. - 0 - 31 - read-only - - - - - SYST_SEC_UPD - System Time - Seconds Update Register - 0x710 - 32 - 0x00000000 - 0xFFFFFFFF - - - TSS - Timestamp Second - The value in this field indicates the time in seconds to be initialized or added to the system time. - 0 - 32 - read-write - - - - - SYST_NSEC_UPD - System Time - Nanoseconds Update Register - 0x714 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDSUB - Add or Subtract Time - When this bit is set, the time value is subtracted with the contents of the update register. When this bit is reset, the time value is added with the contents of the update register. - 31 - 1 - read-write - - - TSSS - Timestamp Sub Seconds -The value in this field has the sub second representation of time, with an accuracy of 0.46 ns. -When Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register), each bit represents 1 ns and the programmed value should not exceed 0x3B9A_C9FF. - 0 - 31 - read-write - - - - - TS_ADDEND - Timestamp Addend Register - 0x718 - 32 - 0x00000000 - 0xFFFFFFFF - - - TSAR - Timestamp Addend Register -This field indicates the 32-bit time value to be added to the Accumulator register to achieve time synchronization. - 0 - 32 - read-write - - - - - TGTTM_SEC - Target Time Seconds Register - 0x71c - 32 - 0x00000000 - 0xFFFFFFFF - - - TSTR - Target Time Seconds Register - This register stores the time in seconds. -When the timestamp value matches or exceeds both Target Timestamp registers, -then based on Bits [6:5] of Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). - 0 - 32 - read-write - - - - - TGTTM_NSEC - Target Time Nanoseconds Register - 0x720 - 32 - 0x00000000 - 0xFFFFFFFF - - - TRGTBUSY - Target Time Register Busy - The MAC sets this bit when the PPSCMD field (Bit [3:0]) in Register 459 (PPS Control Register) is programmed to 010 or 011. -Programming the PPSCMD field to 010 or 011, instructs the MAC to synchronize the Target Time Registers to the PTP clock domain. -The MAC clears this bit after synchronizing the Target Time Registers to the PTP clock domain -The application must not update the Target Time Registers when this bit is read as 1. -Otherwise, the synchronization of the previous programmed time gets corrupted. This bit is reserved when the Enable Flexible Pulse-Per-Second Output feature is not selected. - 31 - 1 - read-write - - - TTSLO - Target Timestamp Low Register -This register stores the time in (signed) nanoseconds. -When the value of the timestamp matches the both Target Timestamp registers, -then based on the TRGTMODSEL0 field (Bits [6:5]) in Register 459 (PPS Control Register), -the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). -This value should not exceed 0x3B9A_C9FF when Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register). -The actual start or stop time of the PPS signal output may have an error margin up to one unit of sub-second increment value. - 0 - 31 - read-write - - - - - SYSTM_H_SEC - System Time - Higher Word Seconds Register - 0x724 - 32 - 0x00000000 - 0x0000FFFF - - - TSHWR - Timestamp Higher Word Register -This field contains the most significant 16-bits of the timestamp seconds value. This register is optional and can be selected using the Enable IEEE 1588 Higher Word Register option during core configuration. -The register is directly written to initialize the value. This register is incremented when there is an overflow from the 32-bits of the System Time - Seconds register. - 0 - 16 - read-write - - - - - TS_STATUS - Timestamp Status Register - 0x728 - 32 - 0x00000000 - 0x3F0F03FF - - - ATSNS - Number of Auxiliary Timestamp Snapshots -This field indicates the number of Snapshots available in the FIFO. A value equal to the selected depth of FIFO (4, 8, or 16) indicates that the Auxiliary Snapshot FIFO is full. -These bits are cleared (to 00000) when the Auxiliary snapshot FIFO clear bit is set. -This bit is valid only if the Add IEEE 1588 Auxiliary Snapshot option is selected during core configuration. - 25 - 5 - read-only - - - ATSSTM - Auxiliary Timestamp Snapshot Trigger Missed - This bit is set when the Auxiliary timestamp snapshot FIFO is full and external trigger was set. -This indicates that the latest snapshot is not stored in the FIFO. This bit is valid only if the Add IEEE 1588 Auxiliary Snapshot option is selected during core configuration. - 24 - 1 - read-only - - - ATSSTN - Auxiliary Timestamp Snapshot Trigger Identifier -These bits identify the Auxiliary trigger inputs for which the timestamp available in the Auxiliary Snapshot Register is applicable. -When more than one bit is set at the same time, it means that corresponding auxiliary triggers were sampled at the same clock. -These bits are applicable only if the number of Auxiliary snapshots is more than one. -One bit is assigned for each trigger as shown in the following list: -- Bit 16: Auxiliary trigger 0 -- Bit 17: Auxiliary trigger 1 -- Bit 18: Auxiliary trigger 2 -- Bit 19: Auxiliary trigger 3 - The software can read this register to find the triggers that are set when the timestamp is taken. - 16 - 4 - read-only - - - TSTRGTERR3 - Timestamp Target Time Error -This bit is set when the target time, being programmed in Register 496 and Register 497, is already elapsed. This bit is cleared when read by the application. - 9 - 1 - read-only - - - TSTARGT3 - Timestamp Target Time Reached for Target Time PPS3 -When set, this bit indicates that the value of system time is greater than or equal to the value specified in Register 496 (PPS3 Target Time High Register) and Register 497 (PPS3 Target Time Low Register). - 8 - 1 - read-only - - - TSTRGTERR2 - No description available - 7 - 1 - read-only - - - TSTARGT2 - No description available - 6 - 1 - read-only - - - TSTRGTERR1 - No description available - 5 - 1 - read-only - - - TSTARGT1 - No description available - 4 - 1 - read-only - - - TSTRGTERR - No description available - 3 - 1 - read-only - - - AUXTSTRIG - No description available - 2 - 1 - read-only - - - TSTARGT - No description available - 1 - 1 - read-only - - - TSSOVF - No description available - 0 - 1 - read-only - - - - - PPS_CTRL - PPS Control Register - 0x72c - 32 - 0x00000000 - 0x6767677F - - - TRGTMODSEL3 - Target Time Register Mode for PPS3 Output -This field indicates the Target Time registers (register 496 and 497) mode for PPS3 output signal. This field is similar to the TRGTMODSEL0 field. - 29 - 2 - read-write - - - PPSCMD3 - Flexible PPS3 Output Control -This field controls the flexible PPS3 output (ptp_pps_o[3]) signal. This field is similar to PPSCMD0[2:0] in functionality. - 24 - 3 - write-only - - - TRGTMODSEL2 - Target Time Register Mode for PPS2 Output -This field indicates the Target Time registers (register 488 and 489) mode for PPS2 output signal. This field is similar to the TRGTMODSEL0 field. - 21 - 2 - read-write - - - PPSCMD2 - Flexible PPS2 Output Control -This field controls the flexible PPS2 output (ptp_pps_o[2]) signal. This field is similar to PPSCMD0[2:0] in functionality. - 16 - 3 - write-only - - - TRGTMODSEL1 - Target Time Register Mode for PPS1 Output -This field indicates the Target Time registers (register 480 and 481) mode for PPS1 output signal. This field is similar to the TRGTMODSEL0 field. - 13 - 2 - read-write - - - PPSCMD1 - Flexible PPS1 Output Control -This field controls the flexible PPS1 output (ptp_pps_o[1]) signal. This field is similar to PPSCMD0[2:0] in functionality. - 8 - 3 - write-only - - - TRGTMODSEL0 - Target Time Register Mode for PPS0 Output - This field indicates the Target Time registers (register 455 and 456) mode for PPS0 output signal: -- 00: Indicates that the Target Time registers are programmed only for generating the interrupt event. -- 01: Reserved -- 10: Indicates that the Target Time registers are programmed for generating the interrupt event and starting or stopping the generation of the PPS0 output signal. -- 11: Indicates that the Target Time registers are programmed only for starting or stopping the generation of the PPS0 output signal. No interrupt is asserted. - 5 - 2 - read-write - - - PPSEN0 - Flexible PPS Output Mode Enable -When set low, Bits [3:0] function as PPSCTRL (backward compatible). When set high, Bits[3:0] function as PPSCMD. - 4 - 1 - read-write - - - PPSCTRLCMD0 - PPSCTRL0: PPS0 Output Frequency Control -This field controls the frequency of the PPS0 output (ptp_pps_o[0]) signal. -The default value of PPSCTRL is 0000, and the PPS output is 1 pulse (of width clk_ptp_i) every second. -For other values of PPSCTRL, the PPS output becomes a generated clock of following frequencies: -- 0001: The binary rollover is 2 Hz, and the digital rollover is 1 Hz. -- 0010: The binary rollover is 4 Hz, and the digital rollover is 2 Hz. -- 0011: The binary rollover is 8 Hz, and the digital rollover is 4 Hz. -- 0100: The binary rollover is 16 Hz, and the digital rollover is 8 Hz. - ... -- 1111: The binary rollover is 32.768 KHz, and the digital rollover is 16.384 KHz. -Note: In the binary rollover mode, the PPS output (ptp_pps_o) has a duty cycle of 50 percent with these frequencies. -In the digital rollover mode, the PPS output frequency is an average number. -The actual clock is of different frequency that gets synchronized every second. For example: -- When PPSCTRL = 0001, the PPS (1 Hz) has a low period of 537 ms and a high period of 463 ms -- When PPSCTRL = 0010, the PPS (2 Hz) is a sequence of: - - One clock of 50 percent duty cycle and 537 ms period - - Second clock of 463 ms period (268 ms low and 195 ms high) -- When PPSCTRL = 0011, the PPS (4 Hz) is a sequence of: - - Three clocks of 50 percent duty cycle and 268 ms period - - Fourth clock of 195 ms period (134 ms low and 61 ms high) -PPSCMD0: Flexible PPS0 Output Control -0000: No Command -0001: START Single Pulse -This command generates single pulse rising at the start point defined in -Target Time Registers and of a duration defined -in the PPS0 Width Register. -0010: START Pulse Train -This command generates the train of pulses rising at the start point -defined in the Target Time Registers and of a duration defined in the -PPS0 Width Register and repeated at interval defined in the PPS -Interval Register. By default, the PPS pulse train is free-running unless -stopped by ‘STOP Pulse train at time’ or ‘STOP Pulse Train -immediately’ commands. -0011: Cancel START -This command cancels the START Single Pulse and START Pulse Train -commands if the system time has not crossed the programmed start -time. -0100: STOP Pulse train at time -This command stops the train of pulses initiated by the START Pulse -Train command (PPSCMD = 0010) after the time programmed in the -Target Time registers elapses. -0101: STOP Pulse Train immediately -This command immediately stops the train of pulses initiated by the -START Pulse Train command (PPSCMD = 0010). -0110: Cancel STOP Pulse train -This command cancels the STOP pulse train at time command if the -programmed stop time has not elapsed. The PPS pulse train becomes -free-running on the successful execution of this command. -0111-1111: Reserved -Note: These bits get cleared automatically - 0 - 4 - read-write - - - - - AUX_TS_NSEC - Auxiliary Timestamp - Nanoseconds Register - 0x730 - 32 - 0x00000000 - 0x7FFFFFFF - - - AUXTSLO - Contains the lower 31 bits (nano-seconds field) of the auxiliary timestamp. - 0 - 31 - read-only - - - - - AUX_TS_SEC - Auxiliary Timestamp - Seconds Register - 0x734 - 32 - 0x00000000 - 0xFFFFFFFF - - - AUXTSHI - Contains the lower 32 bits of the Seconds field of the auxiliary timestamp. - 0 - 32 - read-only - - - - - PPS0_INTERVAL - PPS Interval Register - 0x760 - 32 - 0x00000000 - 0xFFFFFFFF - - - PPSINT - PPS0 Output Signal Interval -These bits store the interval between the rising edges of PPS0 signal output in terms of units of sub-second increment value. -You need to program one value less than the required interval. -For example, if the PTP reference clock is 50 MHz (period of 20ns), -and desired interval between rising edges of PPS0 signal output is 100ns - (that is, five units of sub-second increment value), then you should program value 4 (5 – 1) in this register. - 0 - 32 - read-write - - - - - PPS0_WIDTH - PPS Width Register - 0x764 - 32 - 0x00000000 - 0xFFFFFFFF - - - PPSWIDTH - PPS0 Output Signal Width -These bits store the width between the rising edge and corresponding falling edge of the PPS0 signal output in terms of units of sub-second increment value. -You need to program one value less than the required interval. -For example, if PTP reference clock is 50 MHz (period of 20ns), -and desired width between the rising and corresponding falling edges of PPS0 signal output is 80ns - (that is, four units of sub-second increment value), then you should program value 3 (4 – 1) in this register. - 0 - 32 - read-write - - - - - 3 - 0x20 - 1,2,3 - PPS[%s] - no description available - 0x780 - - TGTTM_SEC - PPS Target Time Seconds Register - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - TSTRH1 - PPS1 Target Time Seconds Register -This register stores the time in seconds. -When the timestamp value matches or exceeds both Target Timestamp registers, -then based on Bits [14:13], TRGTMODSEL1, of Register 459 (PPS Control Register), -the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). - 0 - 32 - read-write - - - - - TGTTM_NSEC - PPS Target Time Nanoseconds Register - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - TRGTBUSY1 - PPS1 Target Time Register Busy -The MAC sets this bit when the PPSCMD1 field (Bits [10:8]) in Register 459 (PPS Control Register) is programmed to 010 or 011. -Programming the PPSCMD1 field to 010 or 011 instructs the MAC to synchronize the Target Time Registers to the PTP clock domain. -The MAC clears this bit after synchronizing the Target Time Registers to the PTP clock domain -The application must not update the Targeers wht Time Registen this bit is read as 1. -Otherwise, the synchronization of the previous programmed time gets corrupted. - 31 - 1 - read-write - - - TTSL1 - Target Time Low for PPS1 Register -This register stores the time in (signed) nanoseconds. -When the value of the timestamp matches the both Target Timestamp registers, -then based on the TRGTMODSEL1 field (Bits [14:13]) in Register 459 (PPS Control Register), - the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). - This value should not exceed 0x3B9A_C9FF when Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register). -The actual start or stop time of the PPS signal output may have an error margin up to one unit of sub-second increment value. - 0 - 31 - read-write - - - - - INTERVAL - PPS Interval Register - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - PPSINT - PPS1 Output Signal Interval -These bits store the interval between the rising edges of PPS1 signal output in terms of units of sub-second increment value. -You need to program one value less than the required interval. For example, if the PTP reference clock is 50 MHz (period of 20ns), - and desired interval between rising edges of PPS1 signal output is 100ns (that is, five units of sub-second increment value), -then you should program value 4 (5 – 1) in this register. - 0 - 32 - read-write - - - - - WIDTH - PPS Width Register - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - PPSWIDTH - PPS1 Output Signal Width -These bits store the width between the rising edge and corresponding falling edge of the PPS1 signal output in terms of units of sub-second increment value. -You need to program one value less than the required interval. For example, - if PTP reference clock is 50 MHz (period of 20ns), -and desired width between the rising and corresponding falling edges of PPS1 signal output is 80ns (that is, four units of sub-second increment value), -then you should program value 3 (4 – 1) in this register. - 0 - 32 - read-write - - - - - - DMA_BUS_MODE - Bus Mode Register - 0x1000 - 32 - 0x00000000 - 0xBFFFFFFF - - - RIB - Rebuild INCRx Burst -When this bit is set high and the AHB master gets an EBT (Retry, Split, or Losing bus grant), - the AHB master interface rebuilds the pending beats of any burst transfer initiated with INCRx. -The AHB master interface rebuilds the beats with a combination of specified bursts with INCRx and SINGLE. -By default, the AHB master interface rebuilds pending beats of an EBT with an unspecified (INCR) burst. - 31 - 1 - read-write - - - PRWG - Channel Priority -Weights This field sets the priority weights for Channel 0 during the round-robin arbitration between the DMA channels for the system bus. -- 00: The priority weight is 1. -- 01: The priority weight is 2. -- 10: The priority weight is 3. -- 11: The priority weight is 4. This field is present in all DWC_gmac configurations except GMAC-AXI when you select the AV feature. Otherwise, this field is reserved and read-only (RO). - 28 - 2 - read-write - - - TXPR - Transmit Priority -When set, this bit indicates that the transmit DMA has higher priority than the receive DMA during arbitration for the system-side bus. In the GMAC-AXI configuration, this bit is reserved and read-only (RO). - 27 - 1 - read-write - - - MB - Mixed Burst -When this bit is set high and the FB bit is low, the AHB master interface starts all bursts of length more than 16 with INCR (undefined burst), -whereas it reverts to fixed burst transfers (INCRx and SINGLE) for burst length of 16 and less. - 26 - 1 - read-write - - - AAL - Address-Aligned Beats -When this bit is set high and the FB bit is equal to 1, -the AHB or AXI interface generates all bursts aligned to the start address LS bits. If the FB bit is equal to 0, - the first burst (accessing the start address of data buffer) is not aligned, but subsequent bursts are aligned to the address. - 25 - 1 - read-write - - - PBLX8 - PBLx8 Mode -When set high, this bit multiplies the programmed PBL value (Bits [22:17] and Bits[13:8]) eight times. -Therefore, the DMA transfers the data in 8, 16, 32, 64, 128, and 256 beats depending on the PBL value. - 24 - 1 - read-write - - - USP - Use Separate PBL -When set high, this bit configures the Rx DMA to use the value configured in Bits [22:17] as PBL. -The PBL value in Bits [13:8] is applicable only to the Tx DMA operations. -When reset to low, the PBL value in Bits [13:8] is applicable for both DMA engines. - 23 - 1 - read-write - - - RPBL - Rx DMA PBL -This field indicates the maximum number of beats to be transferred in one Rx DMA transaction. -This is the maximum value that is used in a single block Read or Write. -The Rx DMA always attempts to burst as specified in the RPBL bit each time it starts a Burst transfer on the host bus. - You can program RPBL with values of 1, 2, 4, 8, 16, and 32. Any other value results in undefined behavior. -This field is valid and applicable only when USP is set high. - 17 - 6 - read-write - - - FB - Fixed Burst - This bit controls whether the AHB or AXI master interface performs fixed burst transfers or not. -When set, the AHB interface uses only SINGLE, INCR4, INCR8, or INCR16 during start of the normal burst transfers. -When reset, the AHB or AXI interface uses SINGLE and INCR burst transfer operations. - 16 - 1 - read-write - - - PR - Priority Ratio - These bits control the priority ratio in the weighted round-robin arbitration between the Rx DMA and Tx DMA. - These bits are valid only when Bit 1 (DA) is reset. The priority ratio is Rx:Tx or Tx:Rx depending on whether Bit 27 (TXPR) is reset or set. -- 00: The Priority Ratio is 1:1. -- 01: The Priority Ratio is 2:1. -- 10: The Priority Ratio is 3:1. -- 11: The Priority Ratio is 4:1. - 14 - 2 - read-write - - - PBL - Programmable Burst Length -These bits indicate the maximum number of beats to be transferred in one DMA transaction. -This is the maximum value that is used in a single block Read or Write. -The DMA always attempts to burst as specified in PBL each time it starts a Burst transfer on the host bus. -PBL can be programmed with permissible values of 1, 2, 4, 8, 16, and 32. -Any other value results in undefined behavior. When USP is set high, this PBL value is applicable only for Tx DMA transactions. -If the number of beats to be transferred is more than 32, then perform the following steps: 1. Set the PBLx8 mode. 2. Set the PBL. - 8 - 6 - read-write - - - ATDS - Alternate Descriptor Size -When set, the size of the alternate descriptor (described in “Alternate or Enhanced Descriptors” on page 545) increases to 32 bytes (8 DWORDS). -This is required when the Advanced Timestamp feature or the IPC Full Checksum Offload Engine (Type 2) is enabled in the receiver. -The enhanced descriptor is not required if the Advanced Timestamp and IPC Full Checksum Offload Engine (Type 2) features are not enabled. - In such case, you can use the 16 bytes descriptor to save 4 bytes of memory. -This bit is present only when you select the Alternate Descriptor feature and any one of the following features during core configuration: -- Advanced Timestamp feature - IPC Full Checksum Offload Engine (Type 2) feature Otherwise, this bit is reserved and is read-only. -When reset, the descriptor size reverts back to 4 DWORDs (16 bytes). - 7 - 1 - read-write - - - DSL - Descriptor Skip Length -This bit specifies the number of Word, Dword, or Lword (depending on the 32-bit, 64-bit, or 128-bit bus) to skip between two unchained descriptors. -The address skipping starts from the end of current descriptor to the start of next descriptor. -When the DSL value is equal to zero, the descriptor table is taken as contiguous by the DMA in Ring mode. - 2 - 5 - read-write - - - DA - DMA Arbitration Scheme -This bit specifies the arbitration scheme between the transmit and receive paths of Channel 0. -- 0: Weighted round-robin with Rx:Tx or Tx:Rx The priority between the paths is according to the priority specified in Bits [15:14] (PR) and priority weights specified in Bit 27 (TXPR). -- 1: Fixed priority The transmit path has priority over receive path when Bit 27 (TXPR) is set. Otherwise, receive path has priority over the transmit path. - 1 - 1 - read-write - - - SWR - Software Reset - When this bit is set, the MAC DMA Controller resets the logic and all internal registers of the MAC. -It is cleared automatically after the reset operation is complete in all of the DWC_gmac clock domains. -Before reprogramming any register of the DWC_gmac, you should read a zero (0) value in this bit. -Note: - The Software reset function is driven only by this bit. -Bit 0 of Register 64 (Channel 1 Bus Mode Register) or Register 128 (Channel 2 Bus Mode Register) has no impact on the Software reset function. -- The reset operation is completed only when all resets in all active clock domains are de-asserted. -Therefore, it is essential that all PHY inputs clocks (applicable for the selected PHY interface) are present for the software reset completion. -The time to complete the software reset operation depends on the frequency of the slowest active clock. - 0 - 1 - read-write - - - - - DMA_TX_POLL_DEMAND - Transmit Poll Demand Register - 0x1004 - 32 - 0x00000000 - 0xFFFFFFFF - - - TPD - Transmit Poll Demand -When these bits are written with any value, -the DMA reads the current descriptor to which the Register 18 (Current Host Transmit Descriptor Register) is pointing. - If that descriptor is not available (owned by the Host), -the transmission returns to the Suspend state and Bit 2 (TU) of Register 5 (Status Register) is asserted. -If the descriptor is available, the transmission resumes. - 0 - 32 - read-write - - - - - DMA_RX_POLL_DEMAND - Receive Poll Demand Register - 0x1008 - 32 - 0x00000000 - 0xFFFFFFFF - - - RPD - Receive Poll Demand -When these bits are written with any value, -the DMA reads the current descriptor to which the Register 19 (Current Host Receive Descriptor Register) is pointing. - If that descriptor is not available (owned by the Host), -the reception returns to the Suspended state and Bit 7 (RU) of Register 5 (Status Register) is asserted. -If the descriptor is available, the Rx DMA returns to the active state. - 0 - 32 - read-write - - - - - DMA_RX_DESC_LIST_ADDR - Receive Descriptor List Address Register - 0x100c - 32 - 0x00000000 - 0xFFFFFFFF - - - RDESLA - Start of Receive List -This field contains the base address of the first descriptor in the Receive Descriptor list. -The LSB bits (1:0, 2:0, or 3:0) for 32-bit, 64-bit, or 128-bit bus width are ignored and internally taken as all-zero by the DMA. Therefore, these LSB bits are read-only (RO). - 0 - 32 - read-write - - - - - DMA_TX_DESC_LIST_ADDR - Transmit Descriptor List Address Register - 0x1010 - 32 - 0x00000000 - 0xFFFFFFFF - - - TDESLA - Start of Transmit List -This field contains the base address of the first descriptor in the Transmit Descriptor list. -The LSB bits (1:0, 2:0, 3:0) for 32-bit, 64-bit, or 128-bit bus width are ignored and are internally taken as all-zero by the DMA. Therefore, these LSB bits are read-only (RO). - 0 - 32 - read-write - - - - - DMA_STATUS - Status Register - 0x1014 - 32 - 0x00000000 - 0x7FFFE7FF - - - GLPII - GLPII: GMAC LPI Interrupt (for Channel 0) -This bit indicates an interrupt event in the LPI logic of the MAC. -To reset this bit to 1'b0, the software must read the corresponding registers in the DWC_gmac to get the exact cause of the interrupt and clear its source. -Note: GLPII status is given only in Channel 0 DMA register and is applicable only when the Energy Efficient Ethernet feature is enabled. Otherwise, this bit is reserved. -When this bit is high, the interrupt signal from the MAC (sbd_intr_o) is high. --or- GTMSI: GMAC TMS Interrupt (for Channel 1 and Channel 2) This bit indicates an interrupt event in the traffic manager and scheduler logic of DWC_gmac. -To reset this bit, the software must read the corresponding registers (Channel Status Register) to get the exact cause of the interrupt and clear its source. -Note: GTMSI status is given only in Channel 1 and Channel 2 DMA register when the AV feature is enabled and corresponding additional transmit channels are present. -Otherwise, this bit is reserved. When this bit is high, the interrupt signal from the MAC (sbd_intr_o) is high. - 30 - 1 - read-write - - - TTI - Timestamp Trigger Interrupt -This bit indicates an interrupt event in the Timestamp Generator block of the DWC_gmac. -The software must read the corresponding registers in the DWC_gmac to get the exact cause of the interrupt and clear its source to reset this bit to 1'b0. - When this bit is high, the interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high. -This bit is applicable only when the IEEE 1588 Timestamp feature is enabled. Otherwise, this bit is reserved. - 29 - 1 - read-write - - - GPI - GMAC PMT Interrupt -This bit indicates an interrupt event in the PMT module of the DWC_gmac. - The software must read the PMT Control and Status Register in the MAC to get the exact cause of interrupt and clear its source to reset this bit to 1’b0. -The interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high when this bit is high. -This bit is applicable only when the Power Management feature is enabled. -Otherwise, this bit is reserved. Note: The GPI and pmt_intr_o interrupts are generated in different clock domains. - 28 - 1 - read-write - - - GMI - GMAC MMC Interrupt - This bit reflects an interrupt event in the MMC module of the DWC_gmac. -The software must read the corresponding registers in the DWC_gmac -to get the exact cause of the interrupt and clear the source of interrupt to make this bit as 1’b0. -The interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high when this bit is high. -This bit is applicable only when the MAC Management Counters (MMC) are enabled. Otherwise, this bit is reserved. - 27 - 1 - read-write - - - GLI - GMAC Line Interface Interrupt -When set, this bit reflects any of the following interrupt events in the DWC_gmac interfaces (if present and enabled in your configuration): -- PCS (TBI, RTBI, or SGMII): Link change or auto-negotiation complete event -- SMII or RGMII: Link change event - General Purpose Input Status (GPIS): - Any LL or LH event on the gpi_i input ports To identify the exact cause of the interrupt, - the software must first read Bit 11 and Bits[2:0] of Register 14 (Interrupt Status Register) and then to clear the source of interrupt (which also clears the GLI interrupt), - read any of the following corresponding registers: -- PCS (TBI, RTBI, or SGMII): Register 49 (AN Status Register) -- SMII or RGMII: Register 54 (SGMII/RGMII/SMII Control and Status Register) -- General Purpose Input (GPI): Register 56 (General Purpose IO Register) The interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high when this bit is high. - 26 - 1 - read-write - - - EB - Error Bits -This field indicates the type of error that caused a Bus Error, for example, error response on the AHB or AXI interface. - This field is valid only when Bit 13 (FBI) is set. This field does not generate an interrupt. -- 0 0 0: Error during Rx DMA Write Data Transfer -- 0 1 1: Error during Tx DMA Read Data Transfer -- 1 0 0: Error during Rx DMA Descriptor Write Access -- 1 0 1: Error during Tx DMA Descriptor Write Access -- 1 1 0: Error during Rx DMA Descriptor Read Access -- 1 1 1: Error during Tx DMA Descriptor Read Access Note: 001 and 010 are reserved. - 23 - 3 - read-write - - - TS - Transmit Process State -This field indicates the Transmit DMA FSM state. This field does not generate an interrupt. -- 3’b000: Stopped; Reset or Stop Transmit Command issued -- 3’b001: Running; Fetching Transmit Transfer Descriptor -- 3’b010: Running; Waiting for status -- 3’b011: Running; Reading Data from host memory buffer and queuing it to transmit buffer (Tx FIFO) -- 3’b100: TIME_STAMP write state -- 3’b101: Reserved for future use -- 3’b110: Suspended; Transmit Descriptor Unavailable or Transmit Buffer Underflow -- 3’b111: Running; Closing Transmit Descriptor - 20 - 3 - read-write - - - RS - Receive Process State -This field indicates the Receive DMA FSM state. This field does not generate an interrupt. -- 3’b000: Stopped: Reset or Stop Receive Command issued -- 3’b001: Running: Fetching Receive Transfer Descriptor -- 3’b010: Reserved for future use -- 3’b011: Running: Waiting for receive packet -- 3’b100: Suspended: Receive Descriptor Unavailable -- 3’b101: Running: Closing Receive Descriptor -- 3’b110: TIME_STAMP write state -- 3’b111: Running: Transferring the receive packet data from receive buffer to host memory - 17 - 3 - read-write - - - NIS - Normal Interrupt Summary -Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in -Register 7 (Interrupt Enable Register): -- Register 5[0]: Transmit Interrupt -- Register 5[2]: Transmit Buffer Unavailable -- Register 5[6]: Receive Interrupt -- Register 5[14]: Early Receive Interrupt Only unmasked bits - (interrupts for which interrupt enable is set in Register 7) affect the Normal Interrupt Summary bit. - This is a sticky bit and must be cleared (by writing 1 to this bit) each time a corresponding bit, which causes NIS to be set, is cleared. - 16 - 1 - read-write - - - AIS - Abnormal Interrupt Summary -Abnormal Interrupt Summary bit value is the logical OR of the following -when the corresponding interrupt bits are enabled in Register 7 (Interrupt Enable Register): -- Register 5[1]: Transmit Process Stopped -- Register 5[3]: Transmit Jabber Timeout -- Register 5[4]: Receive FIFO Overflow -- Register 5[5]: Transmit Underflow -- Register 5[7]: Receive Buffer Unavailable -- Register 5[8]: Receive Process Stopped -- Register 5[9]: Receive Watchdog Timeout -- Register 5[10]: Early Transmit Interrupt -- Register 5[13]: Fatal Bus Error Only unmasked bits affect the Abnormal Interrupt Summary bit. -This is a sticky bit and must be cleared (by writing 1 to this bit) each time a corresponding bit, which causes AIS to be set, is cleared. - 15 - 1 - read-write - - - ERI - Early Receive Interrupt -This bit indicates that the DMA filled the first data buffer of the packet. This bit is cleared when the software writes 1 to this bit or Bit 6 (RI) of this register is set (whichever occurs earlier). - 14 - 1 - read-write - - - FBI - Fatal Bus Error Interrupt -This bit indicates that a bus error occurred, as described in Bits [25:23]. When this bit is set, the corresponding DMA engine disables all of its bus accesses. - 13 - 1 - read-write - - - ETI - Early Transmit Interrupt -This bit indicates that the frame to be transmitted is fully transferred to the MTL Transmit FIFO. - 10 - 1 - read-write - - - RWT - Receive Watchdog Timeout -When set, this bit indicates that the Receive Watchdog Timer expired while receiving the current frame and the current frame is truncated after the watchdog timeout. - 9 - 1 - read-write - - - RPS - Receive Process Stopped -This bit is asserted when the Receive Process enters the Stopped state. - 8 - 1 - read-write - - - RU - Receive Buffer Unavailable -This bit indicates that the host owns the Next Descriptor in the Receive List and the DMA cannot acquire it. -The Receive Process is suspended. To resume processing Receive descriptors, - the host should change the ownership of the descriptor and issue a Receive Poll Demand command. - If no Receive Poll Demand is issued, the Receive Process resumes when the next recognized incoming frame is received. -This bit is set only when the previous Receive Descriptor is owned by the DMA. - 7 - 1 - read-write - - - RI - Receive Interrupt -This bit indicates that the frame reception is complete. -When reception is complete, the Bit 31 of RDES1 (Disable Interrupt on Completion) is reset in the last Descriptor, -and the specific frame status information is updated in the descriptor. -The reception remains in the Running state. - 6 - 1 - read-write - - - UNF - Transmit Underflow -This bit indicates that the Transmit Buffer had an Underflow during frame transmission. Transmission is suspended and an Underflow Error TDES0[1] is set. - 5 - 1 - read-write - - - OVF - Receive Overflow -This bit indicates that the Receive Buffer had an Overflow during frame reception. If the partial frame is transferred to the application, the overflow status is set in RDES0[11]. - 4 - 1 - read-write - - - TJT - Transmit Jabber Timeout -This bit indicates that the Transmit Jabber Timer expired, which happens when the frame size exceeds 2,048 (10,240 bytes when the Jumbo frame is enabled). -When the Jabber Timeout occurs, the transmission process is aborted and placed in the Stopped state. This causes the Transmit Jabber Timeout TDES0[14] flag to assert. - 3 - 1 - read-write - - - TU - Transmit Buffer Unavailable -This bit indicates that the host owns the Next Descriptor in the Transmit List and the DMA cannot acquire it. Transmission is suspended. Bits[22:20] explain the Transmit Process state transitions. -To resume processing Transmit descriptors, the host should change the ownership of the descriptor by setting TDES0[31] and then issue a Transmit Poll Demand command. - 2 - 1 - read-write - - - TPS - Transmit Process Stopped -This bit is set when the transmission is stopped. - 1 - 1 - read-write - - - TI - Transmit Interrupt -This bit indicates that the frame transmission is complete. When transmission is complete, Bit 31 (OWN) of TDES0 is reset, and the specific frame status information is updated in the descriptor. - 0 - 1 - read-write - - - - - DMA_OP_MODE - Operation Mode Register - 0x1018 - 32 - 0x00000000 - 0x13F1FFFE - - - DT - Disable Dropping of TCP/IP Checksum Error Frames -When this bit is set, the MAC does not drop the frames which only have errors detected by the Receive Checksum Offload engine. - Such frames do not have any errors (including FCS error) in the Ethernet frame received by the MAC but have errors only in the encapsulated payload. -When this bit is reset, all error frames are dropped if the FEF bit is reset. If the IPC Full Checksum Offload Engine (Type 2) is disabled, this bit is reserved (RO with value 1'b0). - 28 - 1 - read-write - - - RSF - Receive Store and Forward -When this bit is set, the MTL reads a frame from the Rx FIFO only after the complete frame has been written to it, ignoring the RTC bits. - When this bit is reset, the Rx FIFO operates in the cut-through mode, subject to the threshold specified by the RTC bits. - 25 - 1 - read-write - - - DFF - Disable Flushing of Received Frames -When this bit is set, the Rx DMA does not flush any frames because of the unavailability of receive descriptors or buffers as it does normally when this bit is reset. (See “Receive Process Suspended” on page 83.) - 24 - 1 - read-write - - - RFA_2 - MSB of Threshold for Activating Flow Control -If the DWC_gmac is configured for an Rx FIFO size of 8 KB or more, -this bit (when set) provides additional threshold levels for activating the flow control in both half-duplex and full-duplex modes. -This bit (as Most Significant Bit), along with the RFA (Bits [10:9]), gives the following thresholds for activating flow control: -- 100: Full minus 5 KB, that is, FULL — 5 KB -- 101: Full minus 6 KB, that is, FULL — 6 KB -- 110: Full minus 7 KB, that is, FULL — 7 KB -- 111: Reserved This bit is reserved (and RO) if the Rx FIFO is 4 KB or less deep. - 23 - 1 - read-write - - - RFD_2 - MSB of Threshold for Deactivating Flow Control -If the DWC_gmac is configured for Rx FIFO size of 8 KB or more, - this bit (when set) provides additional threshold levels for deactivating the flow control in both half-duplex and full-duplex modes. - This bit (as Most Significant Bit) along with the RFD (Bits [12:11]) gives the following thresholds for deactivating flow control: -- 100: Full minus 5 KB, that is, FULL — 5 KB -- 101: Full minus 6 KB, that is, FULL — 6 KB -- 110: Full minus 7 KB, that is, FULL — 7 KB -- 111: Reserved This bit is reserved (and RO) if the Rx FIFO is 4 KB or less deep. - 22 - 1 - read-write - - - TSF - Transmit Store and Forward -When this bit is set, transmission starts when a full frame resides in the MTL Transmit FIFO. -When this bit is set, the TTC values specified in Bits [16:14] are ignored. -This bit should be changed only when the transmission is stopped. - 21 - 1 - read-write - - - FTF - Flush Transmit FIFO -When this bit is set, the transmit FIFO controller logic is reset to its default values and thus all data in the Tx FIFO is lost or flushed. -This bit is cleared internally when the flushing operation is complete. -The Operation Mode register should not be written to until this bit is cleared. -The data which is already accepted by the MAC transmitter is not flushed. -It is scheduled for transmission and results in underflow and runt frame transmission. - 20 - 1 - read-write - - - TTC - Transmit Threshold Control -These bits control the threshold level of the MTL Transmit FIFO. - Transmission starts when the frame size within the MTL Transmit FIFO is larger than the threshold. -In addition, full frames with a length less than the threshold are also transmitted. - These bits are used only when Bit 21 (TSF) is reset. -- 000: 64 -- 001: 128 -- 010: 192 -- 011: 256 -- 100: 40 -- 101: 32 -- 110: 24 -- 111: 16 - 14 - 3 - read-write - - - ST - Start or Stop Transmission Command -When this bit is set, transmission is placed in the Running state, and the DMA checks the Transmit List at the current position for a frame to be transmitted. -Descriptor acquisition is attempted either from the current position in the list, -which is the Transmit List Base Address set by Register 4 (Transmit Descriptor List Address Register), -or from the position retained when transmission was stopped previously. - If the DMA does not own the current descriptor, -transmission enters the Suspended state and Bit 2 (Transmit Buffer Unavailable) of Register 5 (Status Register) is set. -The Start Transmission command is effective only when transmission is stopped. -If the command is issued before setting Register 4 (Transmit Descriptor List Address Register), - then the DMA behavior is unpredictable. When this bit is reset, -the transmission process is placed in the Stopped state after completing the transmission of the current frame. -The Next Descriptor position in the Transmit List is saved, -and it becomes the current position when transmission is restarted. -To change the list address, you need to program Register 4 (Transmit Descriptor List Address Register) with a new value when this bit is reset. -The new value is considered when this bit is set again. -The stop transmission command is effective only when the transmission of the current frame is complete or the transmission is in the Suspended state. - 13 - 1 - read-write - - - RFD - Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (Fill-level of Rx FIFO) at which the flow control is de-asserted after activation. -- 00: Full minus 1 KB, that is, FULL — 1 KB -- 01: Full minus 2 KB, that is, FULL — 2 KB -- 10: Full minus 3 KB, that is, FULL — 3 KB -- 11: Full minus 4 KB, that is, FULL — 4 KB -The de-assertion is effective only after flow control is asserted. - If the Rx FIFO is 8 KB or more, an additional Bit (RFD_2) is used for more threshold levels as described in Bit 22. -These bits are reserved and read-only when the Rx FIFO depth is less than 4 KB. - 11 - 2 - read-write - - - RFA - Threshold for Activating Flow Control (in half-duplex and full-duplex modes) -These bits control the threshold (Fill level of Rx FIFO) at which the flow control is activated. -- 00: Full minus 1 KB, that is, FULL—1KB. -- 01: Full minus 2 KB, that is, FULL—2KB. -- 10: Full minus 3 KB, that is, FULL—3KB. -- 11: Full minus 4 KB, that is, FULL—4KB. -These values are applicable only to Rx FIFOs of 4 KB or more and when Bit 8 (EFC) is set high. If the Rx FIFO is 8 KB or more, -an additional Bit (RFA_2) is used for more threshold levels as described in Bit 23. -These bits are reserved and read-only when the depth of Rx FIFO is less than 4 KB. -Note: When FIFO size is exactly 4 KB, although the DWC_gmac allows you to program the value of these bits to 11, -the software should not program these bits to 2'b11. The value 2'b11 means flow control on FIFO empty condition - 9 - 2 - read-write - - - EFC - Enable HW Flow Control -When this bit is set, the flow control signal operation based on the fill-level of Rx FIFO is enabled. -When reset, the flow control operation is disabled. - This bit is not used (reserved and always reset) when the Rx FIFO is less than 4 KB. - 8 - 1 - read-write - - - FEF - Forward Error Frames -When this bit is reset, the Rx FIFO drops frames with error status (CRC error, collision error, GMII_ER, giant frame, watchdog timeout, or overflow). -However, if the start byte (write) pointer of a frame is already transferred to the read controller side (in Threshold mode), -then the frame is not dropped. In the GMAC-MTL configuration in which the Frame Length FIFO is also enabled during core configuration, -the Rx FIFO drops the error frames if that frame's start byte is not transferred (output) on the ARI bus. -When the FEF bit is set, all frames except runt error frames are forwarded to the DMA. -If the Bit 25 (RSF) is set and the Rx FIFO overflows when a partial frame is written, -then the frame is dropped irrespective of the FEF bit setting. -However, if the Bit 25 (RSF) is reset and the Rx FIFO overflows when a partial frame is written, then a partial frame may be forwarded to the DMA. -Note: When FEF bit is reset, the giant frames are dropped if the giant frame status is given in Rx Status (in Table 8-6 or Table 8-23) in the following configurations: -- The IP checksum engine (Type 1) and full checksum offload engine (Type 2) are not selected. - - The advanced timestamp feature is not selected but the extended status is selected. -The extended status is available with the following features: -- L3-L4 filter in GMAC-CORE or GMAC-MTL configurations -- Full checksum offload engine (Type 2) with enhanced descriptor format in the GMAC-DMA, GMAC-AHB, or GMAC-AXI configurations. - 7 - 1 - read-write - - - FUF - Forward Undersized Good Frames -When set, the Rx FIFO forwards Undersized frames (that is, frames with no Error and length less than 64 bytes) including pad-bytes and CRC -When reset, the Rx FIFO drops all frames of less than 64 bytes, unless a frame is already transferred because of the lower value of Receive Threshold, for example, RTC = 01. - 6 - 1 - read-write - - - DGF - Drop Giant Frames -When set, the MAC drops the received giant frames in the Rx FIFO, -that is, frames that are larger than the computed giant frame limit. -When reset, the MAC does not drop the giant frames in the Rx FIFO. -Note: This bit is available in the following configurations in which the giant frame status is not provided in Rx status and giant frames are not dropped by default: -- Configurations in which IP Checksum Offload (Type 1) is selected in Rx -- Configurations in which the IPC Full Checksum Offload Engine (Type 2) is selected in Rx with normal descriptor format -- Configurations in which the Advanced Timestamp feature is selected In all other configurations, this bit is not used (reserved and always reset). - 5 - 1 - read-write - - - RTC - Receive Threshold Control -These two bits control the threshold level of the MTL Receive FIFO. -Transfer (request) to DMA starts when the frame size within the MTL Receive FIFO is larger than the threshold. -In addition, full frames with length less than the threshold are automatically transferred. -The value of 11 is not applicable if the configured Receive FIFO size is 128 bytes. -These bits are valid only when the RSF bit is zero, and are ignored when the RSF bit is set to 1. -- 00: 64 -- 01: 32 -- 10: 96 -- 11: 128 - 3 - 2 - read-write - - - OSF - Operate on Second Frame -When this bit is set, it instructs the DMA to process the second frame of the Transmit data even before the status for the first frame is obtained. - 2 - 1 - read-write - - - SR - Start or Stop Receive -When this bit is set, the Receive process is placed in the Running state. -The DMA attempts to acquire the descriptor from the Receive list and processes the incoming frames. -The descriptor acquisition is attempted from the current position in the list, -which is the address set by the Register 3 (Receive Descriptor List Address Register) or the position retained when the Receive process was previously stopped. -If the DMA does not own the descriptor, reception is suspended and Bit 7 (Receive Buffer Unavailable) of Register 5 (Status Register) is set. -The Start Receive command is effective only when the reception has stopped. - If the command is issued before setting Register 3 (Receive Descriptor List Address Register), the DMA behavior is unpredictable. -When this bit is cleared, the Rx DMA operation is stopped after the transfer of the current frame. -The next descriptor position in the Receive list is saved and becomes the current position after the Receive process is restarted. -The Stop Receive command is effective only when the Receive process is in either the Running (waiting for receive packet) or in the Suspended state. - 1 - 1 - read-write - - - - - DMA_INTR_EN - Interrupt Enable Register - 0x101c - 32 - 0x00000000 - 0x0001E7FF - - - NIE - Normal Interrupt Summary Enable -When this bit is set, normal interrupt summary is enabled. -When this bit is reset, normal interrupt summary is disabled. -This bit enables the following interrupts in Register 5 (Status Register): - - Register 5[0]: Transmit Interrupt -- Register 5[2]: Transmit Buffer Unavailable -- Register 5[6]: Receive Interrupt - - Register 5[14]: Early Receive Interrupt - 16 - 1 - read-write - - - AIE - Abnormal Interrupt Summary Enable -When this bit is set, abnormal interrupt summary is enabled. -When this bit is reset, the abnormal interrupt summary is disabled. -This bit enables the following interrupts in Register 5 (Status Register): -- Register 5[1]: Transmit Process Stopped -- Register 5[3]: Transmit Jabber Timeout -- Register 5[4]: Receive Overflow -- Register 5[5]: Transmit Underflow -- Register 5[7]: Receive Buffer Unavailable -- Register 5[8]: Receive Process Stopped -- Register 5[9]: Receive Watchdog Timeout -- Register 5[10]: Early Transmit Interrupt - - Register 5[13]: Fatal Bus Error - 15 - 1 - read-write - - - ERE - Early Receive Interrupt Enable -When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Early Receive Interrupt is enabled. When this bit is reset, the Early Receive Interrupt is disabled. - 14 - 1 - read-write - - - FBE - Fatal Bus Error Enable -When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Fatal Bus Error Interrupt is enabled. When this bit is reset, the Fatal Bus Error Enable Interrupt is disabled. - 13 - 1 - read-write - - - ETE - Early Transmit Interrupt Enable -When this bit is set with an Abnormal Interrupt Summary Enable (Bit 15), the Early Transmit Interrupt is enabled. When this bit is reset, the Early Transmit Interrupt is disabled. - 10 - 1 - read-write - - - RWE - Receive Watchdog Timeout Enable -When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Watchdog Timeout Interrupt is enabled. When this bit is reset, the Receive Watchdog Timeout Interrupt is disabled. - 9 - 1 - read-write - - - RSE - Receive Stopped Enable -When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Stopped Interrupt is enabled. When this bit is reset, the Receive Stopped Interrupt is disabled. - 8 - 1 - read-write - - - RUE - Receive Buffer Unavailable Enable -When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Buffer Unavailable Interrupt is enabled. When this bit is reset, the Receive Buffer Unavailable Interrupt is disabled. - 7 - 1 - read-write - - - RIE - Receive Interrupt Enable -When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Receive Interrupt is enabled. When this bit is reset, the Receive Interrupt is disabled. - 6 - 1 - read-write - - - UNE - Underflow Interrupt Enable -When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmit Underflow Interrupt is enabled. When this bit is reset, the Underflow Interrupt is disabled. - 5 - 1 - read-write - - - OVE - Overflow Interrupt Enable -When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Overflow Interrupt is enabled. When this bit is reset, the Overflow Interrupt is disabled. - 4 - 1 - read-write - - - TJE - Transmit Jabber Timeout Enable -When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmit Jabber Timeout Interrupt is enabled. When this bit is reset, the Transmit Jabber Timeout Interrupt is disabled. - 3 - 1 - read-write - - - TUE - Transmit Buffer Unavailable Enable -When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Transmit Buffer Unavailable Interrupt is enabled. When this bit is reset, the Transmit Buffer Unavailable Interrupt is disabled. - 2 - 1 - read-write - - - TSE - Transmit Stopped Enable -When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmission Stopped Interrupt is enabled. When this bit is reset, the Transmission Stopped Interrupt is disabled. - 1 - 1 - read-write - - - TIE - Transmit Interrupt Enable -When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Transmit Interrupt is enabled. When this bit is reset, the Transmit Interrupt is disabled. - 0 - 1 - read-write - - - - - DMA_MISS_OVF_CNT - Missed Frame And Buffer Overflow Counter Register - 0x1020 - 32 - 0x00000000 - 0x1FFFFFFF - - - ONFCNTOVF - Overflow Bit for FIFO Overflow Counter -This bit is set every time the Overflow Frame Counter (Bits[27:17]) overflows, -that is, the Rx FIFO overflows with the overflow frame counter at maximum value. -In such a scenario, the overflow frame counter is reset to all-zeros and this bit indicates that the rollover happened. - 28 - 1 - read-write - - - OVFFRMCNT - Overflow Frame Counter -This field indicates the number of frames missed by the application. This counter is incremented each time the MTL FIFO overflows. The counter is cleared when this register is read with mci_be_i[2] at 1’b1. - 17 - 11 - read-write - - - MISCNTOVF - Overflow Bit for Missed Frame Counter -This bit is set every time Missed Frame Counter (Bits[15:0]) overflows, -that is, the DMA discards an incoming frame because of the Host Receive Buffer being unavailable with the missed frame counter at maximum value. In such a scenario, - the Missed frame counter is reset to all-zeros and this bit indicates that the rollover happened. - 16 - 1 - read-write - - - MISFRMCNT - Missed Frame Counter -This field indicates the number of frames missed by the controller because of the Host Receive Buffer being unavailable. -This counter is incremented each time the DMA discards an incoming frame. The counter is cleared when this register is read with mci_be_i[0] at 1’b1. - 0 - 16 - read-write - - - - - DMA_RX_INTR_WDOG - Receive Interrupt Watchdog Timer Register - 0x1024 - 32 - 0x00000000 - 0x000000FF - - - RIWT - RI Watchdog Timer Count -This bit indicates the number of system clock cycles multiplied by 256 for which the watchdog timer is set. -The watchdog timer gets triggered with the programmed value after the Rx DMA completes the transfer -of a frame for which the RI status bit is not set because of the setting in the corresponding descriptor RDES1[31]. -When the watchdog timer runs out, the RI bit is set and the timer is stopped. -The watchdog timer is reset when the RI bit is set high because of automatic setting of RI as per RDES1[31] of any received frame. - 0 - 8 - read-write - - - - - DMA_AXI_MODE - AXI Bus Mode Register - 0x1028 - 32 - 0x00000000 - 0xC0FF30FF - - - EN_LPI - Enable Low Power Interface (LPI) -When set to 1, this bit enables the LPI mode supported by the GMAC-AXI configuration and accepts the LPI request from the AXI System Clock controller. -When set to 0, this bit disables the LPI mode and always denies the LPI request from the AXI System Clock controller. - 31 - 1 - read-write - - - LPI_XIT_FRM - Unlock on Magic Packet or Remote Wake-Up Frame -When set to 1, this bit enables the GMAC-AXI to come out of the LPI mode only when the magic packet or remote wake-up frame is received. -When set to 0, this bit enables the GMAC-AXI to come out of LPI mode when any frame is received. - 30 - 1 - read-write - - - WR_OSR_LMT - AXI Maximum Write Outstanding Request Limit -This value limits the maximum outstanding request on the AXI write interface. -Maximum outstanding requests = WR_OSR_LMT+1 Note: - Bit 22 is reserved if AXI_GM_MAX_WR_REQUESTS = 4. - Bit 23 bit is reserved if AXI_GM_MAX_WR_REQUESTS != 16. - 20 - 4 - read-write - - - RD_OSR_LMT - AXI Maximum Read Outstanding Request Limit -This value limits the maximum outstanding request on the AXI read interface. -Maximum outstanding requests = RD_OSR_LMT+1 Note: - Bit 18 is reserved if AXI_GM_MAX_RD_REQUESTS = 4. - Bit 19 is reserved if AXI_GM_MAX_RD_REQUESTS != 16. - 16 - 4 - read-write - - - ONEKBBE - 1 KB Boundary Crossing Enable for the GMAC-AXI Master -When set, the GMAC-AXI master performs burst transfers that do not cross 1 KB boundary. -When reset, the GMAC-AXI master performs burst transfers that do not cross 4 KB boundary. - 13 - 1 - read-write - - - AXI_AAL - Address-Aligned Beats -This bit is read-only bit and reflects the Bit 25 (AAL) of Register 0 (Bus Mode Register). -When this bit is set to 1, the GMAC-AXI performs address-aligned burst transfers on both read and write channels. - 12 - 1 - read-write - - - BLEN256 - AXI Burst Length 256 -When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 256 on the AXI master interface. -This bit is present only when the configuration parameter AXI_BL is set to 256. Otherwise, this bit is reserved and is read-only (RO). - 7 - 1 - read-write - - - BLEN128 - AXI Burst Length 128 -When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 128 on the AXI master interface. -This bit is present only when the configuration parameter AXI_BL is set to 128 or more. Otherwise, this bit is reserved and is read-only (RO). - 6 - 1 - read-write - - - BLEN64 - AXI Burst Length 64 -When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 64 on the AXI master interface. -This bit is present only when the configuration parameter AXI_BL is set to 64 or more. Otherwise, this bit is reserved and is read-only (RO). - 5 - 1 - read-write - - - BLEN32 - AXI Burst Length 32 -When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 32 on the AXI master interface. -This bit is present only when the configuration parameter AXI_BL is set to 32 or more. Otherwise, this bit is reserved and is read-only (RO). - 4 - 1 - read-write - - - BLEN16 - AXI Burst Length 16 -When this bit is set to 1 or UNDEF is set to 1, the GMAC-AXI is allowed to select a burst length of 16 on the AXI master interface. - 3 - 1 - read-write - - - BLEN8 - AXI Burst Length 8 -When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 8 on the AXI master interface. -Setting this bit has no effect when UNDEF is set to 1. - 2 - 1 - read-write - - - BLEN4 - AXI Burst Length 4 -When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 4 on the AXI master interface. -Setting this bit has no effect when UNDEF is set to 1. - 1 - 1 - read-write - - - UNDEF - AXI Undefined Burst Length -This bit is read-only bit and indicates the complement (invert) value of Bit 16 (FB) in Register 0 (Bus Mode Register). -- When this bit is set to 1, the GMAC-AXI is allowed to perform any burst length equal to or below the maximum allowed burst length programmed in Bits[7:3]. -- When this bit is set to 0, the GMAC-AXI is allowed to perform only fixed burst lengths as indicated by BLEN256, BLEN128, BLEN64, BLEN32, BLEN16, BLEN8, or BLEN4, or a burst length of 1. -If UNDEF is set and none of the BLEN bits is set, then GMAC-AXI is allowed to perform a burst length of 16. - 0 - 1 - read-write - - - - - DMA_BUS_STATUS - AHB or AXI Status Register - 0x102c - 32 - 0x00000000 - 0x00000003 - - - AXIRDSTS - AXI Master Read Channel Status -When high, it indicates that AXI master's read channel is active and transferring data. - 1 - 1 - read-write - - - AXWHSTS - AXI Master Write Channel or AHB Master Status -When high, it indicates that AXI master's write channel is active and transferring data in the GMAC-AXI configuration. In the GMAC-AHB configuration, - it indicates that the AHB master interface FSMs are in the non-idle state. - 0 - 1 - read-write - - - - - DMA_CURR_HOST_TX_DESC - Current Host Transmit Descriptor Register - 0x1048 - 32 - 0x00000000 - 0xFFFFFFFF - - - CURTDESAPTR - Host Transmit Descriptor Address Pointer -Cleared on Reset. Pointer updated by the DMA during operation. - 0 - 32 - read-write - - - - - DMA_CURR_HOST_RX_DESC - Current Host Receive Descriptor Register - 0x104c - 32 - 0x00000000 - 0xFFFFFFFF - - - CURRDESAPTR - Host Receive Descriptor Address Pointer -Cleared on Reset. Pointer updated by the DMA during operation. - 0 - 32 - read-write - - - - - DMA_CURR_HOST_TX_BUF - Current Host Transmit Buffer Address Register - 0x1050 - 32 - 0x00000000 - 0xFFFFFFFF - - - CURTBUFAPTR - Host Transmit Buffer Address Pointer -Cleared on Reset. Pointer updated by the DMA during operation. - 0 - 32 - read-write - - - - - DMA_CURR_HOST_RX_BUF - Current Host Receive Buffer Address Register - 0x1054 - 32 - 0x00000000 - 0xFFFFFFFF - - - CURRBUFAPTR - Host Receive Buffer Address Pointer -Cleared on Reset. Pointer updated by the DMA during operation. - 0 - 32 - read-write - - - - - - - ENET1 - ENET1 - ENET - 0xf2004000 - - - NTMR0 - NTMR0 - GPTMR - 0xf2010000 - - 0x0 - 0x20c - registers - - - - 4 - 0x40 - ch0,ch1,ch2,ch3 - CHANNEL[%s] - no description available - 0x0 - - CR - Control Register - 0x0 - 32 - 0x00000000 - 0x80007FFF - - - CNTUPT - 1- update counter to new value as CNTUPTVAL -This bit will be auto cleared after 1 cycle - 31 - 1 - write-only - - - CNTRST - 1- reset counter - 14 - 1 - read-write - - - SYNCFLW - 1- enable this channel to reset counter to reload(RLD) together with its previous channel. -This bit is not valid for channel 0. - 13 - 1 - read-write - - - SYNCIFEN - 1- SYNCI is valid on its falling edge - 12 - 1 - read-write - - - SYNCIREN - 1- SYNCI is valid on its rising edge - 11 - 1 - read-write - - - CEN - 1- counter enable - 10 - 1 - read-write - - - CMPINIT - Output compare initial poliarity -1- The channel output initial level is high -0- The channel output initial level is low -User should set this bit before set CMPEN to 1. - 9 - 1 - read-write - - - CMPEN - 1- Enable the channel output compare function. The output signal can be generated per comparator (CMPx) settings. - 8 - 1 - read-write - - - DMASEL - select one of DMA request: -00- CMP0 flag -01- CMP1 flag -10- Input signal toggle captured -11- RLD flag, counter reload; - 6 - 2 - read-write - - - DMAEN - 1- enable dma - 5 - 1 - read-write - - - SWSYNCIEN - 1- enable software sync. When this bit is set, counter will reset to RLD when swsynct bit is set - 4 - 1 - read-write - - - DBGPAUSE - 1- counter will pause if chip is in debug mode - 3 - 1 - read-write - - - CAPMODE - This bitfield define the input capture mode -100: width measure mode, timer will calculate the input signal period and duty cycle -011: capture at both rising edge and falling edge -010: capture at falling edge -001: capture at rising edge -000: No capture - 0 - 3 - read-write - - - - - 2 - 0x4 - CMP0,CMP1 - CMP[%s] - no description available - 0x4 - 32 - 0xFFFFFFF0 - 0xFFFFFFFF - - - CMP - compare value 0 - 0 - 32 - read-write - - - - - RLD - Reload register - 0xc - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - RLD - reload value - 0 - 32 - read-write - - - - - CNTUPTVAL - Counter update value register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - CNTUPTVAL - counter will be set to this value when software write cntupt bit in CR - 0 - 32 - read-write - - - - - CAPPOS - Capture rising edge register - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPPOS - This register contains the counter value captured at input signal rising edge - 0 - 32 - read-only - - - - - CAPNEG - Capture falling edge register - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPNEG - This register contains the counter value captured at input signal falling edge - 0 - 32 - read-only - - - - - CAPPRD - PWM period measure register - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPPRD - This register contains the input signal period when channel is configured to input capture measure mode. - 0 - 32 - read-only - - - - - CAPDTY - PWM duty cycle measure register - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - MEAS_HIGH - This register contains the input signal duty cycle when channel is configured to input capture measure mode. - 0 - 32 - read-only - - - - - CNT - Counter - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - COUNTER - 32 bit counter value - 0 - 32 - read-only - - - - - - SR - Status register - 0x200 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH3CMP1F - channel 3 compare value 1 match flag - 15 - 1 - write-only - - - CH3CMP0F - channel 3 compare value 1 match flag - 14 - 1 - write-only - - - CH3CAPF - channel 3 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. - 13 - 1 - write-only - - - CH3RLDF - channel 3 counter reload flag - 12 - 1 - write-only - - - CH2CMP1F - channel 2 compare value 1 match flag - 11 - 1 - write-only - - - CH2CMP0F - channel 2 compare value 1 match flag - 10 - 1 - write-only - - - CH2CAPF - channel 2 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. - 9 - 1 - write-only - - - CH2RLDF - channel 2 counter reload flag - 8 - 1 - write-only - - - CH1CMP1F - channel 1 compare value 1 match flag - 7 - 1 - write-only - - - CH1CMP0F - channel 1 compare value 1 match flag - 6 - 1 - write-only - - - CH1CAPF - channel 1 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. - 5 - 1 - write-only - - - CH1RLDF - channel 1 counter reload flag - 4 - 1 - write-only - - - CH0CMP1F - channel 1 compare value 1 match flag - 3 - 1 - write-only - - - CH0CMP0F - channel 1 compare value 1 match flag - 2 - 1 - write-only - - - CH0CAPF - channel 1 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. - 1 - 1 - write-only - - - CH0RLDF - channel 1 counter reload flag - 0 - 1 - write-only - - - - - IRQEN - Interrupt request enable register - 0x204 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH3CMP1EN - 1- generate interrupt request when ch3cmp1f flag is set - 15 - 1 - read-write - - - CH3CMP0EN - 1- generate interrupt request when ch3cmp0f flag is set - 14 - 1 - read-write - - - CH3CAPEN - 1- generate interrupt request when ch3capf flag is set - 13 - 1 - read-write - - - CH3RLDEN - 1- generate interrupt request when ch3rldf flag is set - 12 - 1 - read-write - - - CH2CMP1EN - 1- generate interrupt request when ch2cmp1f flag is set - 11 - 1 - read-write - - - CH2CMP0EN - 1- generate interrupt request when ch2cmp0f flag is set - 10 - 1 - read-write - - - CH2CAPEN - 1- generate interrupt request when ch2capf flag is set - 9 - 1 - read-write - - - CH2RLDEN - 1- generate interrupt request when ch2rldf flag is set - 8 - 1 - read-write - - - CH1CMP1EN - 1- generate interrupt request when ch1cmp1f flag is set - 7 - 1 - read-write - - - CH1CMP0EN - 1- generate interrupt request when ch1cmp0f flag is set - 6 - 1 - read-write - - - CH1CAPEN - 1- generate interrupt request when ch1capf flag is set - 5 - 1 - read-write - - - CH1RLDEN - 1- generate interrupt request when ch1rldf flag is set - 4 - 1 - read-write - - - CH0CMP1EN - 1- generate interrupt request when ch0cmp1f flag is set - 3 - 1 - read-write - - - CH0CMP0EN - 1- generate interrupt request when ch0cmp0f flag is set - 2 - 1 - read-write - - - CH0CAPEN - 1- generate interrupt request when ch0capf flag is set - 1 - 1 - read-write - - - CH0RLDEN - 1- generate interrupt request when ch0rldf flag is set - 0 - 1 - read-write - - - - - GCR - Global control register - 0x208 - 32 - 0x00000000 - 0x0000000F - - - SWSYNCT - set this bitfield to trigger software counter sync event - 0 - 4 - read-write - - - - - - - NTMR1 - NTMR1 - GPTMR - 0xf2014000 - - - GPTMR0 - GPTMR0 - GPTMR - 0xf3000000 - - - GPTMR1 - GPTMR1 - GPTMR - 0xf3004000 - - - GPTMR2 - GPTMR2 - GPTMR - 0xf3008000 - - - GPTMR3 - GPTMR3 - GPTMR - 0xf300c000 - - - GPTMR4 - GPTMR4 - GPTMR - 0xf3010000 - - - GPTMR5 - GPTMR5 - GPTMR - 0xf3014000 - - - GPTMR6 - GPTMR6 - GPTMR - 0xf3018000 - - - GPTMR7 - GPTMR7 - GPTMR - 0xf301c000 - - - PTMR - PTMR - GPTMR - 0xf40e0000 - - - USB0 - USB0 - USB - 0xf2020000 - - 0x80 - 0x1a8 - registers - - - - GPTIMER0LD - General Purpose Timer #0 Load Register - 0x80 - 32 - 0x00000000 - 0x00FFFFFF - - - GPTLD - GPTLD -General Purpose Timer Load Value -These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. -This value represents the time in microseconds minus 1 for the timer duration. -Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. -NOTE: Max value is 0xFFFFFF or 16.777215 seconds. - 0 - 24 - read-write - - - - - GPTIMER0CTRL - General Purpose Timer #0 Controller Register - 0x84 - 32 - 0x00000000 - 0xC1FFFFFF - - - GPTRUN - GPTRUN -General Purpose Timer Run -GPTCNT bits are not effected when setting or clearing this bit. -0 - Stop counting -1 - Run - 31 - 1 - read-write - - - GPTRST - GPTRST -General Purpose Timer Reset -0 - No action -1 - Load counter value from GPTLD bits in n_GPTIMER0LD - 30 - 1 - write-only - - - GPTMODE - GPTMODE -General Purpose Timer Mode -In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is -reset by software; -In repeat mode, the timer will count down to zero, generate an interrupt and automatically reload the -counter value from GPTLD bits to start again. -0 - One Shot Mode -1 - Repeat Mode - 24 - 1 - read-write - - - GPTCNT - GPTCNT -General Purpose Timer Counter. -This field is the count value of the countdown timer. - 0 - 24 - read-only - - - - - GPTIMER1LD - General Purpose Timer #1 Load Register - 0x88 - 32 - 0x00000000 - 0x00FFFFFF - - - GPTLD - GPTLD -General Purpose Timer Load Value -These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. -This value represents the time in microseconds minus 1 for the timer duration. -Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. -NOTE: Max value is 0xFFFFFF or 16.777215 seconds. - 0 - 24 - read-write - - - - - GPTIMER1CTRL - General Purpose Timer #1 Controller Register - 0x8c - 32 - 0x00000000 - 0xC1FFFFFF - - - GPTRUN - GPTRUN -General Purpose Timer Run -GPTCNT bits are not effected when setting or clearing this bit. -0 - Stop counting -1 - Run - 31 - 1 - read-write - - - GPTRST - GPTRST -General Purpose Timer Reset -0 - No action -1 - Load counter value from GPTLD bits in USB_n_GPTIMER1LD - 30 - 1 - write-only - - - GPTMODE - GPTMODE -General Purpose Timer Mode -In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is -reset by software. In repeat mode, the timer will count down to zero, generate an interrupt and -automatically reload the counter value from GPTLD bits to start again. -0 - One Shot Mode -1 - Repeat Mode - 24 - 1 - read-write - - - GPTCNT - GPTCNT -General Purpose Timer Counter. -This field is the count value of the countdown timer. - 0 - 24 - read-only - - - - - SBUSCFG - System Bus Config Register - 0x90 - 32 - 0x00000000 - 0x00000007 - - - AHBBRST - AHBBRST -AHB master interface Burst configuration -These bits control AHB master transfer type sequence (or priority). -NOTE: This register overrides n_BURSTSIZE register when its value is not zero. -000 - Incremental burst of unspecified length only -001 - INCR4 burst, then single transfer -010 - INCR8 burst, INCR4 burst, then single transfer -011 - INCR16 burst, INCR8 burst, INCR4 burst, then single transfer -100 - Reserved, don't use -101 - INCR4 burst, then incremental burst of unspecified length -110 - INCR8 burst, INCR4 burst, then incremental burst of unspecified length -111 - INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length - 0 - 3 - read-write - - - - - USBCMD - USB Command Register - 0x140 - 32 - 0x00080000 - 0x00FFEB7F - - - ITC - ITC -Interrupt Threshold Control -Read/Write. -The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. -ITC contains the maximum interrupt interval measured in micro-frames. Valid values are -shown below. -Value Maximum Interrupt Interval -00000000 - Immediate (no threshold) -00000001 - 1 micro-frame -00000010 - 2 micro-frames -00000100 - 4 micro-frames -00001000 - 8 micro-frames -00010000 - 16 micro-frames -00100000 - 32 micro-frames -01000000 - 64 micro-frames - 16 - 8 - read-write - - - FS_2 - FS_2 -Frame List Size - (Read/Write or Read Only). [host mode only] -This field is Read/Write only if Programmable Frame List Flag in the HCCPARAMS registers is set to one. -This field specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. -NOTE: This field is made up from USBCMD bits 15, 3 and 2. -Value Meaning -0b000 - 1024 elements (4096 bytes) Default value -0b001 - 512 elements (2048 bytes) -0b010 - 256 elements (1024 bytes) -0b011 - 128 elements (512 bytes) -0b100 - 64 elements (256 bytes) -0b101 - 32 elements (128 bytes) -0b110 - 16 elements (64 bytes) -0b111 - 8 elements (32 bytes) - 15 - 1 - read-write - - - ATDTW - ATDTW -Add dTD TripWire - Read/Write. [device mode only] -This bit is used as a semaphore to ensure proper addition of a new dTD to an active (primed) endpoint's -linked list. This bit is set and cleared by software. -This bit would also be cleared by hardware when state machine is hazard region for which adding a dTD -to a primed endpoint may go unrecognized. - 14 - 1 - read-write - - - SUTW - SUTW -Setup TripWire - Read/Write. [device mode only] -This bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted. -If the setup lockout mode is off (SLOM bit in USB core register n_USBMODE, see USBMODE ) then -there is a hazard when new setup data arrives while the DCD is copying the setup data payload -from the QH for a previous setup packet. This bit is set and cleared by software. -This bit would also be cleared by hardware when a hazard detected. - 13 - 1 - read-write - - - ASPE - ASPE -Asynchronous Schedule Park Mode Enable - Read/Write. -If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this bit defaults to a 1h and is R/W. -Otherwise the bit must be a zero and is RO. Software uses this bit to enable or disable Park mode. -When this bit is one, Park mode is enabled. When this bit is a zero, Park mode is disabled. -NOTE: ASPE bit reset value: '0b' for OTG controller . - 11 - 1 - read-write - - - ASP - ASP -Asynchronous Schedule Park Mode Count - Read/Write. -If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this field defaults to 3h and is R/W. Otherwise it defaults to zero and is Read-Only. -It contains a count of the number of successive transactions the host controller is allowed to -execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. -Valid values are 1h to 3h. Software must not write a zero to this bit when Park Mode Enable is a one as this will result in undefined behavior. -This field is set to 3h in all controller core. - 8 - 2 - read-write - - - IAA - IAA -Interrupt on Async Advance Doorbell - Read/Write. -This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. Software must write a 1 to this bit to ring the doorbell. -When the host controller has evicted all appropriate cached schedule states, -it sets the Interrupt on Async Advance status bit in the USBSTS register. -If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold. -The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one. -Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results. -This bit is only used in host mode. Writing a one to this bit when device mode is selected will have undefined results. - 6 - 1 - read-write - - - ASE - ASE -Asynchronous Schedule Enable - Read/Write. Default 0b. -This bit controls whether the host controller skips processing the Asynchronous Schedule. -Only the host controller uses this bit. -Values Meaning -0 - Do not process the Asynchronous Schedule. -1 - Use the ASYNCLISTADDR register to access the Asynchronous Schedule. - 5 - 1 - read-write - - - PSE - PSE -Periodic Schedule Enable- Read/Write. Default 0b. -This bit controls whether the host controller skips processing the Periodic Schedule. -Only the host controller uses this bit. -Values Meaning -0 - Do not process the Periodic Schedule -1 - Use the PERIODICLISTBASE register to access the Periodic Schedule. - 4 - 1 - read-write - - - FS_1 - FS_1 -See description at bit 15 - 2 - 2 - read-write - - - RST - RST -Controller Reset (RESET) - Read/Write. Software uses this bit to reset the controller. -This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register. -Host operation mode: -When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. -Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. -Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. -Attempting to reset an actively running host controller will result in undefined behavior. -Device operation mode: -When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. -Writing a one to this bit when the device is in the attached state is not recommended, because the effect on an attached host is undefined. -In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0. - 1 - 1 - read-write - - - RS - RS -Run/Stop (RS) - Read/Write. Default 0b. 1=Run. 0=Stop. -Host operation mode: -When set to '1b', the Controller proceeds with the execution of the schedule. The Controller continues execution as long as this bit is set to a one. -When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. -The HC Halted bit in the status register indicates when the Controller has finished the transaction and has entered the stopped state. -Software should not write a one to this field unless the controller is in the Halted state (that is, HCHalted in the USBSTS register is a one). -Device operation mode: -Writing a one to this bit will cause the controller to enable a pull-up on D+ and initiate an attach event. -This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. -Software should use this bit to prevent an attach event before the controller has been properly initialized. Writing a 0 to this will cause a detach event. - 0 - 1 - read-write - - - - - USBSTS - USB Status Register - 0x144 - 32 - 0x00000000 - 0x030DF1FF - - - TI1 - TI1 -General Purpose Timer Interrupt 1(GPTINT1)--R/WC. -This bit is set when the counter in the GPTIMER1CTRL register transitions to zero, writing a one to this -bit will clear it. - 25 - 1 - read-write - - - TI0 - TI0 -General Purpose Timer Interrupt 0(GPTINT0)--R/WC. -This bit is set when the counter in the GPTIMER0CTRL register transitions to zero, writing a one to this -bit clears it. - 24 - 1 - read-write - - - UPI - USB Host Periodic Interrupt – RWC. Default = 0b. -This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction -where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. -This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. -A short packet is when the actual number of bytes received was less than expected. -This bit is not used by the device controller and will always be zero. - 19 - 1 - read-write - - - UAI - USB Host Asynchronous Interrupt – RWC. Default = 0b. -This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction -where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set AND the TD was from the asynchronous schedule. -This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. -A short packet is when the actual number of bytes received was less than expected. -This bit is not used by the device controller and will always be zero - 18 - 1 - read-write - - - NAKI - NAKI -NAK Interrupt Bit--RO. -This bit is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and -corresponding TX/RX Endpoint NAK Enable bit are set. This bit is automatically cleared by hardware -when all Enabled TX/RX Endpoint NAK bits are cleared. - 16 - 1 - read-only - - - AS - AS -Asynchronous Schedule Status - Read Only. -This bit reports the current real status of the Asynchronous Schedule. When set to zero the asynchronous schedule status is disabled and if set to one the status is enabled. -The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. -When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (1) or disabled (0). -Only used in the host operation mode. - 15 - 1 - read-only - - - PS - PS -Periodic Schedule Status - Read Only. -This bit reports the current real status of the Periodic Schedule. When set to zero the periodic schedule is disabled, and if set to one the status is enabled. -The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. -When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (1) or disabled (0). -Only used in the host operation mode. - 14 - 1 - read-only - - - RCL - RCL -Reclamation - Read Only. -This is a read-only status bit used to detect an empty asynchronous schedule. -Only used in the host operation mode. - 13 - 1 - read-only - - - HCH - HCH -HCHaIted - Read Only. -This bit is a zero whenever the Run/Stop bit is a one. - The Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, - either by software or by the Controller hardware (for example, an internal error). -Only used in the host operation mode. -Default value is '0b' for OTG core . -This is because OTG core is not operating as host in default. Please see CM bit in USB_n_USBMODE -register. -NOTE: HCH bit reset value: '0b' for OTG controller core . - 12 - 1 - read-only - - - SLI - SLI -DCSuspend - R/WC. -When a controller enters a suspend state from an active state, this bit will be set to a one. The device controller clears the bit upon exiting from a suspend state. -Only used in device operation mode. - 8 - 1 - read-write - - - SRI - SRI -SOF Received - R/WC. -When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. -When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. -Therefore, this bit will be set roughly every 1ms in device FS mode and every 125ms in HS mode and will be synchronized to the actual SOF that is received. -Because the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp. -In host mode, this bit will be set every 125us and can be used by host controller driver as a time base. -Software writes a 1 to this bit to clear it. - 7 - 1 - read-write - - - URI - URI -USB Reset Received - R/WC. -When the device controller detects a USB Reset and enters the default state, this bit will be set to a one. -Software can write a 1 to this bit to clear the USB Reset Received status bit. -Only used in device operation mode. - 6 - 1 - read-write - - - AAI - AAI -Interrupt on Async Advance - R/WC. -System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule -by writing a one to the Interrupt on Async Advance Doorbell bit in the n_USBCMD register. This status bit indicates the assertion of that interrupt source. -Only used in host operation mode. - 5 - 1 - read-write - - - SEI - System Error – RWC. Default = 0b. -In the BVCI implementation of the USBHS core, this bit is not used, and will always be cleared to '0b'. -In the AMBA implementation, this bit will be set to '1b' when an Error response is seen by the master interface (HRESP[1:0]=ERROR) - 4 - 1 - read-write - - - FRI - FRI -Frame List Rollover - R/WC. -The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to -zero. The exact value at which the rollover occurs depends on the frame list size. For example. If the -frame list size (as programmed in the Frame List Size field of the USB_n_USBCMD register) is 1024, the -Frame Index Register rolls over every time FRINDEX [13] toggles. Similarly, if the size is 512, the Host -Controller sets this bit to a one every time FHINDEX [12] toggles. -Only used in host operation mode. - 3 - 1 - read-write - - - PCI - PCI -Port Change Detect - R/WC. -The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, -or the Force Port Resume bit is set as the result of a J-K transition on the suspended port. -The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. -When the port controller exits the full or high-speed operation states due to Reset or Suspend events, -the notification mechanisms are the USB Reset Received bit and the DCSuspend bits Respectively. - 2 - 1 - read-write - - - UEI - UEI -USB Error Interrupt (USBERRINT) - R/WC. -When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. -This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. - 1 - 1 - read-write - - - UI - UI -USB Interrupt (USBINT) - R/WC. -This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB -transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. -This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when -the actual number of bytes received was less than the expected number of bytes. - 0 - 1 - read-write - - - - - USBINTR - Interrupt Enable Register - 0x148 - 32 - 0x00000000 - 0x030D01FF - - - TIE1 - TIE1 -General Purpose Timer #1 Interrupt Enable -When this bit is one and the TI1 bit in n_USBSTS register is a one the controller will issue an interrupt. - 25 - 1 - read-write - - - TIE0 - TIE0 -General Purpose Timer #0 Interrupt Enable -When this bit is one and the TI0 bit in n_USBSTS register is a one the controller will issue an interrupt. - 24 - 1 - read-write - - - UPIE - UPIE -USB Host Periodic Interrupt Enable -When this bit is one, and the UPI bit in the n_USBSTS register is one, host controller will issue an -interrupt at the next interrupt threshold. - 19 - 1 - read-write - - - UAIE - UAIE -USB Host Asynchronous Interrupt Enable -When this bit is one, and the UAI bit in the n_USBSTS register is one, host controller will issue an -interrupt at the next interrupt threshold. - 18 - 1 - read-write - - - NAKE - NAKE -NAK Interrupt Enable -When this bit is one and the NAKI bit in n_USBSTS register is a one the controller will issue an interrupt. - 16 - 1 - read-only - - - SLE - SLE -Sleep Interrupt Enable -When this bit is one and the SLI bit in n_n_USBSTS register is a one the controller will issue an interrupt. -Only used in device operation mode. - 8 - 1 - read-write - - - SRE - SRE -SOF Received Interrupt Enable -When this bit is one and the SRI bit in n_USBSTS register is a one the controller will issue an interrupt. - 7 - 1 - read-write - - - URE - URE -USB Reset Interrupt Enable -When this bit is one and the URI bit in n_USBSTS register is a one the controller will issue an interrupt. -Only used in device operation mode. - 6 - 1 - read-write - - - AAE - AAE -Async Advance Interrupt Enable -When this bit is one and the AAI bit in n_USBSTS register is a one the controller will issue an interrupt. -Only used in host operation mode. - 5 - 1 - read-write - - - SEE - SEE -System Error Interrupt Enable -When this bit is one and the SEI bit in n_USBSTS register is a one the controller will issue an interrupt. -Only used in host operation mode. - 4 - 1 - read-write - - - FRE - FRE -Frame List Rollover Interrupt Enable -When this bit is one and the FRI bit in n_USBSTS register is a one the controller will issue an interrupt. -Only used in host operation mode. - 3 - 1 - read-write - - - PCE - PCE -Port Change Detect Interrupt Enable -When this bit is one and the PCI bit in n_USBSTS register is a one the controller will issue an interrupt. - 2 - 1 - read-write - - - UEE - UEE -USB Error Interrupt Enable -When this bit is one and the UEI bit in n_USBSTS register is a one the controller will issue an interrupt. - 1 - 1 - read-write - - - UE - UE -USB Interrupt Enable -When this bit is one and the UI bit in n_USBSTS register is a one the controller will issue an interrupt. - 0 - 1 - read-write - - - - - FRINDEX - USB Frame Index Register - 0x14c - 32 - 0x00000000 - 0x00003FFF - - - FRINDEX - FRINDEX -Frame Index. -The value, in this register, increments at the end of each time frame (micro-frame). Bits [N: 3] are used for the Frame List current index. -This means that each location of the frame list is accessed 8 times (frames or micro-frames) before moving to the next index. -The following illustrates values of N based on the value of the Frame List Size field in the USBCMD register, when used in host mode. -USBCMD [Frame List Size] Number Elements N -In device mode the value is the current frame number of the last frame transmitted. It is not used as an index. -In either mode bits 2:0 indicate the current microframe. -The bit field values description below is represented as (Frame List Size) Number Elements N. -00000000000000 - (1024) 12 -00000000000001 - (512) 11 -00000000000010 - (256) 10 -00000000000011 - (128) 9 -00000000000100 - (64) 8 -00000000000101 - (32) 7 -00000000000110 - (16) 6 -00000000000111 - (8) 5 - 0 - 14 - read-write - - - - - DEVICEADDR - Device Address Register - UNION_154 - 0x154 - 32 - 0x00000000 - 0xFF000000 - - - USBADR - USBADR -Device Address. -These bits correspond to the USB device address - 25 - 7 - read-write - - - USBADRA - USBADRA -Device Address Advance. Default=0. -When this bit is '0', any writes to USBADR are instantaneous. - When this bit is written to a '1' at the same time or before USBADR is written, the write to the USBADR field is staged and held in a hidden register. -After an IN occurs on endpoint 0 and is ACKed, USBADR will be loaded from the holding register. -Hardware will automatically clear this bit on the following conditions: -1) IN is ACKed to endpoint 0. (USBADR is updated from staging register). -2) OUT/SETUP occur to endpoint 0. (USBADR is not updated). -3) Device Reset occurs (USBADR is reset to 0). -NOTE: After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. -This mechanism will ensure this specification is met when the DCD can not write of the device address within 2ms from the SET_ADDRESS status phase. -If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), -the USBADR will be programmed instantly at the correct time and meet the 2ms USB requirement. - 24 - 1 - read-write - - - - - PERIODICLISTBASE - Frame List Base Address Register - UNION_154 - 0x154 - 32 - 0x00000000 - 0xFFFFF000 - - - BASEADR - BASEADR -Base Address (Low). -These bits correspond to memory address signals [31:12], respectively. -Only used by the host controller. - 12 - 20 - read-write - - - - - ASYNCLISTADDR - Next Asynch. Address Register - UNION_158 - 0x158 - 32 - 0x00000000 - 0xFFFFFFE0 - - - ASYBASE - ASYBASE -Link Pointer Low (LPL). -These bits correspond to memory address signals [31:5], respectively. This field may only reference a -Queue Head (QH). -Only used by the host controller. - 5 - 27 - read-write - - - - - ENDPTLISTADDR - Endpoint List Address Register - UNION_158 - 0x158 - 32 - 0x00000000 - 0xFFFFF800 - - - EPBASE - EPBASE -Endpoint List Pointer(Low). These bits correspond to memory address signals [31:11], respectively. -This field will reference a list of up to 32 Queue Head (QH) (that is, one queue head per endpoint & direction). - 11 - 21 - read-write - - - - - BURSTSIZE - Programmable Burst Size Register - 0x160 - 32 - 0x00000000 - 0x0000FFFF - - - TXPBURST - TXPBURST -Programmable TX Burst Size. -Default value is determined by TXBURST bits in n_HWTXBUF. -This register represents the maximum length of a the burst in 32-bit words while moving data from system -memory to the USB bus. - 8 - 8 - read-write - - - RXPBURST - RXPBURST -Programmable RX Burst Size. -Default value is determined by TXBURST bits in n_HWRXBUF. -This register represents the maximum length of a the burst in 32-bit words while moving data from the -USB bus to system memory. - 0 - 8 - read-write - - - - - TXFILLTUNING - TX FIFO Fill Tuning Register - 0x164 - 32 - 0x00000000 - 0x003F1F7F - - - TXFIFOTHRES - TXFIFOTHRES -FIFO Burst Threshold. (Read/Write) -This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. -The minimum value is 2 and this value should be a low as possible to maximize USB performance. -A higher value can be used in systems with unpredictable latency and/or insufficient bandwidth -where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory. -This value is ignored if the Stream Disable bit in USB_n_USBMODE register is set. - 16 - 6 - read-write - - - TXSCHHEALTH - TXSCHHEALTH -Scheduler Health Counter. (Read/Write To Clear) -Table continues on the next page -This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES -before running out of time to send the packet before the next Start-Of-Frame. -This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. -Writing to this register will clear the counter and this counter will max. at 31. - 8 - 5 - read-write - - - TXSCHOH - TXSCHOH -Scheduler Overhead. (Read/Write) [Default = 0] -This register adds an additional fixed offset to the schedule time estimator described above as Tff. -As an approximation, the value chosen for this register should limit the number of back-off events captured -in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. -Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization. -The time unit represented in this register is 1.267us when a device is connected in High-Speed Mode. -The time unit represented in this register is 6.333us when a device is connected in Low/Full Speed Mode. -Default value is '08h' for OTG controller core . - 0 - 7 - read-write - - - - - ENDPTNAK - Endpoint NAK Register - 0x178 - 32 - 0x00000000 - 0xFFFFFFFF - - - EPTN - EPTN -TX Endpoint NAK - R/WC. -Each TX endpoint has 1 bit in this field. The bit is set when the -device sends a NAK handshake on a received IN token for the corresponding endpoint. -Bit [N] - Endpoint #[N], N is 0-7 - 16 - 16 - read-write - - - EPRN - EPRN -RX Endpoint NAK - R/WC. -Each RX endpoint has 1 bit in this field. The bit is set when the -device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. -Bit [N] - Endpoint #[N], N is 0-7 - 0 - 16 - read-write - - - - - ENDPTNAKEN - Endpoint NAK Enable Register - 0x17c - 32 - 0x00000000 - 0xFFFFFFFF - - - EPTNE - EPTNE -TX Endpoint NAK Enable - R/W. -Each bit is an enable bit for the corresponding TX Endpoint NAK bit. If this bit is set and the -corresponding TX Endpoint NAK bit is set, the NAK Interrupt bit is set. -Bit [N] - Endpoint #[N], N is 0-7 - 16 - 16 - read-write - - - EPRNE - EPRNE -RX Endpoint NAK Enable - R/W. -Each bit is an enable bit for the corresponding RX Endpoint NAK bit. If this bit is set and the -corresponding RX Endpoint NAK bit is set, the NAK Interrupt bit is set. -Bit [N] - Endpoint #[N], N is 0-7 - 0 - 16 - read-write - - - - - PORTSC1 - Port Status & Control - 0x184 - 32 - 0x00000000 - 0x3DFF1FFF - - - STS - STS -Serial Transceiver Select -1 Serial Interface Engine is selected -0 Parallel Interface signals is selected -Serial Interface Engine can be used in combination with UTMI+/ULPI physical interface to provide FS/LS signaling instead of the parallel interface signals. -When this bit is set '1b', serial interface engine will be used instead of parallel interface signals. - 29 - 1 - read-write - - - PTW - PTW -Parallel Transceiver Width -This bit has no effect if serial interface engine is used. -0 - Select the 8-bit UTMI interface [60MHz] -1 - Select the 16-bit UTMI interface [30MHz] - 28 - 1 - read-write - - - PSPD - PSPD -Port Speed - Read Only. -This register field indicates the speed at which the port is operating. -00 - Full Speed -01 - Low Speed -10 - High Speed -11 - Undefined - 26 - 2 - read-only - - - PFSC - PFSC -Port Force Full Speed Connect - Read/Write. Default = 0b. -When this bit is set to '1b', the port will be forced to only connect at Full Speed, It disables the chirp -sequence that allows the port to identify itself as High Speed. -0 - Normal operation -1 - Forced to full speed - 24 - 1 - read-write - - - PHCD - PHCD -PHY Low Power Suspend - Clock Disable (PLPSCD) - Read/Write. Default = 0b. -When this bit is set to '1b', the PHY clock is disabled. Reading this bit will indicate the status of the PHY -clock. -NOTE: The PHY clock cannot be disabled if it is being used as the system clock. -In device mode, The PHY can be put into Low Power Suspend when the device is not running (USBCMD -Run/Stop=0b) or the host has signalled suspend (PORTSC1 SUSPEND=1b). PHY Low power suspend -will be cleared automatically when the host initials resume. Before forcing a resume from the device, the -device controller driver must clear this bit. -In host mode, the PHY can be put into Low Power Suspend when the downstream device has been put -into suspend mode or when no downstream device is connected. Low power suspend is completely -under the control of software. -0 - Enable PHY clock -1 - Disable PHY clock - 23 - 1 - read-write - - - WKOC - WKOC -Wake on Over-current Enable (WKOC_E) - Read/Write. Default = 0b. -Writing this bit to a one enables the port to be sensitive to over-current conditions as wake-up events. -This field is zero if Port Power(PORTSC1) is zero. - 22 - 1 - read-write - - - WKDC - WKDC -Wake on Disconnect Enable (WKDSCNNT_E) - Read/Write. Default=0b. Writing this bit to a one enables -the port to be sensitive to device disconnects as wake-up events. -This field is zero if Port Power(PORTSC1) is zero or in device mode. - 21 - 1 - read-write - - - WKCN - WKCN -Wake on Connect Enable (WKCNNT_E) - Read/Write. Default=0b. -Writing this bit to a one enables the port to be sensitive to device connects as wake-up events. -This field is zero if Port Power(PORTSC1) is zero or in device mode. - 20 - 1 - read-write - - - PTC - PTC -Port Test Control - Read/Write. Default = 0000b. -Refer to Port Test Mode for the operational model for using these test modes and the USB Specification Revision 2.0, Chapter 7 for details on each test mode. -The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. -Writing the PTC field to any of the FORCE_ENABLE_{HS/FS/LS} values will force the port into the connected and enabled state at the selected speed. -Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. -NOTE: Low speed operations are not supported as a peripheral device. -Any other value than zero indicates that the port is operating in test mode. -Value Specific Test -0000 - TEST_MODE_DISABLE -0001 - J_STATE -0010 - K_STATE -0011 - SE0 (host) / NAK (device) -0100 - Packet -0101 - FORCE_ENABLE_HS -0110 - FORCE_ENABLE_FS -0111 - FORCE_ENABLE_LS -1000-1111 - Reserved - 16 - 4 - read-write - - - PP - PP -Port Power (PP)-Read/Write or Read Only. -The function of this bit depends on the value of the Port Power Switching (PPC) field in the HCSPARAMS register. The behavior is as follows: -PPC -PP Operation -0 -1b Read Only - Host controller does not have port power control switches. Each port is hard-wired to power. -1 -1b/0b - Read/Write. OTG controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on). -When power is not available on a port (that is, PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. -When an over-current condition is detected on a powered port and PPC is a one, -the PP bit in each affected port may be transitional by the host controller driver from a one to a zero (removing power from the port). -This feature is implemented in all controller cores (PPC = 1). - 12 - 1 - read-write - - - LS - LS -Line Status-Read Only. These bits reflect the current logical levels of the D+ (bit 11) and D- (bit 10) signal -lines. -In host mode, the use of linestate by the host controller driver is not necessary (unlike EHCI), because -the port controller state machine and the port routing manage the connection of LS and FS. -In device mode, the use of linestate by the device controller driver is not necessary. -The encoding of the bits are: -Bits [11:10] Meaning -00 - SE0 -01 - K-state -10 - J-state -11 - Undefined - 10 - 2 - read-only - - - HSP - HSP -High-Speed Port - Read Only. Default = 0b. -When the bit is one, the host/device connected to the port is in high-speed mode and if set to zero, the -host/device connected to the port is not in a high-speed mode. -NOTE: HSP is redundant with PSPD(bit 27, 26) but remained for compatibility. - 9 - 1 - read-only - - - PR - PR -Port Reset - Read/Write or Read Only. Default = 0b. -In Host Mode: Read/Write. 1=Port is in Reset. 0=Port is not in Reset. Default 0. -When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. -This bit will automatically change to zero after the reset sequence is complete. -This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timed in the driver. -In Device Mode: This bit is a read only status bit. Device reset from the USB bus is also indicated in the USBSTS register. - 8 - 1 - read-write - - - SUSP - SUSP -Suspend - Read/Write or Read Only. Default = 0b. -1=Port in suspend state. 0=Port not in suspend state. -In Host Mode: Read/Write. -Port Enabled Bit and Suspend bit of this register define the port states as follows: -Bits [Port Enabled, Suspend] Port State -0x Disable -10 Enable -11 Suspend -When in suspend state, downstream propagation of data is blocked on this port, except for port reset. -The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. -In the suspend state, the port is sensitive to resume detection. -Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB. -The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. The host controller ignores a write of zero to this bit. -If host software sets this bit to a one when the port is not enabled (that is, Port enabled bit is a zero) the results are undefined. -This field is zero if Port Power(PORTSC1) is zero in host mode. -In Device Mode: Read Only. -In device mode this bit is a read only status bit. - 7 - 1 - read-write - - - FPR - FPR -Force Port Resume -Read/Write. 1= Resume detected/driven on port. 0=No resume (K-state) detected driven on port. Default = 0. -In Host Mode: -Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one if a J-to-K transition is detected while the port is in the Suspend state. -When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. -This bit will automatically change to zero after the resume sequence is complete. -This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the resume duration is timed in the driver. -Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. -The resume signaling (Full-speed 'K') is driven on the port as long as this bit remains a one. This bit will remain a one until the port has switched to the high-speed idle. -Writing a zero has no effect because the port controller will time the resume operation, clear the bit the port control state switches to HS or FS idle. -This field is zero if Port Power(PORTSC1) is zero in host mode. -This bit is not-EHCI compatible. -In Device mode: -After the device has been in Suspend State for 5ms or more, software must set this bit to one to drive resume signaling before clearing. -The Device Controller will set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. -The bit will be cleared when the device returns to normal operation. - Also, when this bit wil be cleared because a K-to-J transition detected, the Port Change Detect bit in the USBSTS register is also set to one. - 6 - 1 - read-write - - - OCC - OCC -Over-current Change-R/WC. Default=0. -This bit is set '1b' by hardware when there is a change to Over-current Active. Software can clear this bit by writing a one to this bit position. - 5 - 1 - read-write - - - OCA - OCA -Over-current Active-Read Only. Default 0. -This bit will automatically transition from one to zero when the over current condition is removed. -0 - This port does not have an over-current condition. -1 - This port currently has an over-current condition - 4 - 1 - read-only - - - PEC - PEC -Port Enable/Disable Change-R/WC. 1=Port enabled/disabled status has changed. 0=No change. Default = 0. -In Host Mode: -For the root hub, this bit is set to a one only when a port is disabled due to disconnect on the port or -due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). -Software clears this by writing a one to it. -This field is zero if Port Power(PORTSC1) is zero. -In Device mode: -The device port is always enabled, so this bit is always '0b'. - 3 - 1 - read-write - - - PE - PE -Port Enabled/Disabled-Read/Write. 1=Enable. 0=Disable. Default 0. -In Host Mode: -Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. -Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. -Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. -When the port is disabled, (0b) downstream propagation of data is blocked except for reset. -This field is zero if Port Power(PORTSC1) is zero in host mode. -In Device Mode: -The device port is always enabled, so this bit is always '1b'. - 2 - 1 - read-write - - - CSC - CSC -Connect Status Change-R/WC. 1 =Change in Current Connect Status. 0=No change. Default 0. -In Host Mode: -Indicates a change has occurred in the port's Current Connect Status. -The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. -For example, the insertion status changes twice before system software has cleared the changed condition, -hub hardware will be 'setting' an already-set bit (that is, the bit will remain set). Software clears this bit by writing a one to it. -This field is zero if Port Power(PORTSC1) is zero in host mode. -In Device Mode: -This bit is undefined in device controller mode. - 1 - 1 - read-write - - - CCS - CCS -Current Connect Status-Read Only. -In Host Mode: -1=Device is present on port. 0=No device is present. Default = 0. -This value reflects the current state of the port, and may not correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set. -This field is zero if Port Power(PORTSC1) is zero in host mode. -In Device Mode: -1=Attached. 0=Not Attached. Default=0. -A one indicates that the device successfully attached and is operating in either high speed or full speed as indicated by the High Speed Port bit in this register. -A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. -It does not state the device being disconnected or Suspended. - 0 - 1 - read-write - - - - - OTGSC - On-The-Go Status & control Register - 0x1a4 - 32 - 0x00000000 - 0x07070723 - - - ASVIE - ASVIE -A Session Valid Interrupt Enable - Read/Write. - 26 - 1 - read-write - - - AVVIE - AVVIE -A VBus Valid Interrupt Enable - Read/Write. -Setting this bit enables the A VBus valid interrupt. - 25 - 1 - read-write - - - IDIE - IDIE -USB ID Interrupt Enable - Read/Write. -Setting this bit enables the USB ID interrupt. - 24 - 1 - read-write - - - ASVIS - ASVIS -A Session Valid Interrupt Status - Read/Write to Clear. -This bit is set when VBus has either risen above or fallen below the A session valid threshold. -Software must write a one to clear this bit. - 18 - 1 - read-write - - - AVVIS - AVVIS -A VBus Valid Interrupt Status - Read/Write to Clear. -This bit is set when VBus has either risen above or fallen below the VBus valid threshold on an A device. -Software must write a one to clear this bit. - 17 - 1 - read-write - - - IDIS - IDIS -USB ID Interrupt Status - Read/Write. -This bit is set when a change on the ID input has been detected. -Software must write a one to clear this bit. - 16 - 1 - read-write - - - ASV - ASV -A Session Valid - Read Only. -Indicates VBus is above the A session valid threshold. - 10 - 1 - read-only - - - AVV - AVV -A VBus Valid - Read Only. -Indicates VBus is above the A VBus valid threshold. - 9 - 1 - read-only - - - ID - ID -USB ID - Read Only. -0 = A device, 1 = B device - 8 - 1 - read-only - - - IDPU - IDPU -ID Pullup - Read/Write -This bit provide control over the ID pull-up resistor; 0 = off, 1 = on [default]. When this bit is 0, the ID input -will not be sampled. - 5 - 1 - read-write - - - VC - VC -VBUS Charge - Read/Write. -Setting this bit causes the VBus line to be charged. This is used for VBus pulsing during SRP. - 1 - 1 - read-write - - - VD - VD -VBUS_Discharge - Read/Write. -Setting this bit causes VBus to discharge through a resistor. - 0 - 1 - read-write - - - - - USBMODE - USB Device Mode Register - 0x1a8 - 32 - 0x00000000 - 0x0000001F - - - SDIS - SDIS -Stream Disable Mode. (0 - Inactive [default]; 1 - Active) -Device Mode: Setting to a '1' disables double priming on both RX and TX for low bandwidth systems. -This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. -Note: In High Speed Mode, all packets received are responded to with a NYET handshake when stream disable is active. -Host Mode: Setting to a '1' ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems -where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the TX latency is filled to capacity before the packet is launched onto the USB. -NOTE: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING and TXTTFILLTUNING [MPH Only] to characterize the adjustments needed for -the scheduler when using this feature. -NOTE: The use of this feature substantially limits of the overall USB performance that can be achieved. - 4 - 1 - read-write - - - SLOM - SLOM -Setup Lockout Mode. In device mode, this bit controls behavior of the setup lock mechanism. See Control Endpoint Operation Model . -0 - Setup Lockouts On (default); -1 - Setup Lockouts Off. DCD requires use of Setup Data Buffer Tripwire in USBCMD. - 3 - 1 - read-write - - - ES - ES -Endian Select - Read/Write. This bit can change the byte alignment of the transfer buffers to match the -host microprocessor. The bit fields in the microprocessor interface and the data structures are unaffected -by the value of this bit because they are based upon the 32-bit word. -Bit Meaning -0 - Little Endian [Default] -1 - Big Endian - 2 - 1 - read-write - - - CM - CM -Controller Mode - R/WO. Controller mode is defaulted to the proper mode for host only and device only -implementations. For those designs that contain both host & device capability, the controller defaults to -an idle state and needs to be initialized to the desired operating mode after reset. For combination host/ -device controllers, this register can only be written once after reset. If it is necessary to switch modes, -software must reset the controller by writing to the RESET bit in the USBCMD register before -reprogramming this register. -For OTG controller core, reset value is '00b'. -00 - Idle [Default for combination host/device] -01 - Reserved -10 - Device Controller [Default for device only controller] -11 - Host Controller [Default for host only controller] - 0 - 2 - read-write - - - - - ENDPTSETUPSTAT - Endpoint Setup Status Register - 0x1ac - 32 - 0x00000000 - 0x0000FFFF - - - ENDPTSETUPSTAT - ENDPTSETUPSTAT -Setup Endpoint Status. For every setup transaction that is received, a corresponding bit in this register is set to one. -Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. -The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lock out mechanism is engaged. -This register is only used in device mode. - 0 - 16 - read-write - - - - - ENDPTPRIME - Endpoint Prime Register - 0x1b0 - 32 - 0x00000000 - 0xFFFFFFFF - - - PETB - PETB -Prime Endpoint Transmit Buffer - R/WS. For each endpoint a corresponding bit is used to request that a -buffer is prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. -Software should write a one to the corresponding bit when posting a new transfer descriptor to an -endpoint queue head. Hardware automatically uses this bit to begin parsing for a new transfer descriptor -from the queue head and prepare a transmit buffer. Hardware clears this bit when the associated -endpoint(s) is (are) successfully primed. -NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD -is retired, and the dQH is updated. -PETB[N] - Endpoint #N, N is in 0..7 - 16 - 16 - read-write - - - PERB - PERB -Prime Endpoint Receive Buffer - R/WS. For each endpoint, a corresponding bit is used to request a buffer prepare for a receive operation for when a USB host initiates a USB OUT transaction. -Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint queue head. -Hardware automatically uses this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. -Hardware clears this bit when the associated endpoint(s) is (are) successfully primed. -NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD -is retired, and the dQH is updated. -PERB[N] - Endpoint #N, N is in 0..7 - 0 - 16 - read-write - - - - - ENDPTFLUSH - Endpoint Flush Register - 0x1b4 - 32 - 0x00000000 - 0xFFFFFFFF - - - FETB - FETB -Flush Endpoint Transmit Buffer - R/WS. Writing one to a bit(s) in this register causes the associated endpoint(s) to clear any primed buffers. -If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. -Hardware clears this register after the endpoint flush operation is successful. -FETB[N] - Endpoint #N, N is in 0..7 - 16 - 16 - read-write - - - FERB - FERB -Flush Endpoint Receive Buffer - R/WS. Writing one to a bit(s) causes the associated endpoint(s) to clear any primed buffers. - If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. -Hardware clears this register after the endpoint flush operation is successful. -FERB[N] - Endpoint #N, N is in 0..7 - 0 - 16 - read-write - - - - - ENDPTSTAT - Endpoint Status Register - 0x1b8 - 32 - 0x00000000 - 0xFFFFFFFF - - - ETBR - ETBR -Endpoint Transmit Buffer Ready -- Read Only. One bit for each endpoint indicates status of the respective endpoint buffer. -This bit is set to one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. -There is always a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. -This delay time varies based upon the current USB traffic and the number of bits set in the ENDPRIME register. -Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. -NOTE: These bits are momentarily cleared by hardware during hardware endpoint re-priming operations when a dTD is retired, and the dQH is updated. -ETBR[N] - Endpoint #N, N is in 0..7 - 16 - 16 - read-only - - - ERBR - ERBR -Endpoint Receive Buffer Ready -- Read Only. One bit for each endpoint indicates status of the respective -endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a -corresponding bit in the ENDPRIME register. There is always a delay between setting a bit in the -ENDPRIME register and endpoint indicating ready. This delay time varies based upon the current USB -traffic and the number of bits set in the ENDPRIME register. Buffer ready is cleared by USB reset, by the -USB DMA system, or through the ENDPTFLUSH register. -NOTE: These bits are momentarily cleared by hardware during hardware endpoint re-priming operations -when a dTD is retired, and the dQH is updated. -ERBR[N] - Endpoint #N, N is in 0..7 - 0 - 16 - read-only - - - - - ENDPTCOMPLETE - Endpoint Complete Register - 0x1bc - 32 - 0x00000000 - 0xFFFFFFFF - - - ETCE - ETCE -Endpoint Transmit Complete Event - R/WC. Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. -If the corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the USBINT . Writing one clears the corresponding bit in this register. -ETCE[N] - Endpoint #N, N is in 0..7 - 16 - 16 - read-write - - - ERCE - ERCE -Endpoint Receive Complete Event - RW/C. Each bit indicates a received event (OUT/SETUP) occurred -and software should read the corresponding endpoint queue to determine the transfer status. If the -corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the -USBINT . Writing one clears the corresponding bit in this register. -ERCE[N] - Endpoint #N, N is in 0..7 - 0 - 16 - read-write - - - - - 8 - 0x4 - ENDPTCTRL0,ENDPTCTRL1,ENDPTCTRL2,ENDPTCTRL3,ENDPTCTRL4,ENDPTCTRL5,ENDPTCTRL6,ENDPTCTRL7 - ENDPTCTRL[%s] - no description available - 0x1c0 - 32 - 0x00000000 - 0x00CD00CD - - - TXE - TXE -TX Endpoint Enable -0 Disabled [Default] -1 Enabled -An Endpoint should be enabled only after it has been configured. - 23 - 1 - read-write - - - TXR - TXR -TX Data Toggle Reset (WS) -Write 1 - Reset PID Sequence -Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order -to synchronize the data PID's between the Host and device. - 22 - 1 - write-only - - - TXT - TXT -TX Endpoint Type - Read/Write -00 Control -01 Isochronous -10 Bulk -11 Interrupt - 18 - 2 - read-write - - - TXS - TXS -TX Endpoint Stall - Read/Write -0 End Point OK -1 End Point Stalled -This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured -as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. -Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. -This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. -NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. -In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: -continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. - 16 - 1 - read-write - - - RXE - RXE -RX Endpoint Enable -0 Disabled [Default] -1 Enabled -An Endpoint should be enabled only after it has been configured. - 7 - 1 - read-write - - - RXR - RXR -RX Data Toggle Reset (WS) -Write 1 - Reset PID Sequence -Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order -to synchronize the data PID's between the host and device. - 6 - 1 - write-only - - - RXT - RXT -RX Endpoint Type - Read/Write -00 Control -01 Isochronous -10 Bulk -11 Interrupt - 2 - 2 - read-write - - - RXS - RXS -RX Endpoint Stall - Read/Write -0 End Point OK. [Default] -1 End Point Stalled -This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control -Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit -is cleared. -Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This -control will continue to STALL until this bit is either cleared by software or automatically cleared as above -for control endpoints. -NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the -ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it -is unlikely the DCD software will observe this delay. However, should the DCD observe that the -stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit -until it is set or until a new setup has been received by checking the associated endptsetupstat -Bit. - 0 - 1 - read-write - - - - - OTG_CTRL0 - No description available - 0x200 - 32 - 0x00000000 - 0x020B3F90 - - - OTG_WKDPDMCHG_EN - No description available - 25 - 1 - read-write - - - AUTORESUME_EN - No description available - 19 - 1 - read-write - - - OTG_VBUS_WAKEUP_EN - No description available - 17 - 1 - read-write - - - OTG_ID_WAKEUP_EN - No description available - 16 - 1 - read-write - - - OTG_VBUS_SOURCE_SEL - No description available - 13 - 1 - read-write - - - OTG_UTMI_SUSPENDM_SW - default 0 for naneng usbphy - 12 - 1 - read-write - - - OTG_UTMI_RESET_SW - default 1 for naneng usbphy - 11 - 1 - read-write - - - OTG_WAKEUP_INT_ENABLE - No description available - 10 - 1 - read-write - - - OTG_POWER_MASK - No description available - 9 - 1 - read-write - - - OTG_OVER_CUR_POL - No description available - 8 - 1 - read-write - - - OTG_OVER_CUR_DIS - No description available - 7 - 1 - read-write - - - SER_MODE_SUSPEND_EN - for naneng usbphy, only switch to serial mode when suspend - 4 - 1 - read-write - - - - - PHY_CTRL0 - No description available - 0x210 - 32 - 0x00000000 - 0x02007007 - - - GPIO_ID_SEL_N - No description available - 25 - 1 - read-write - - - ID_DIG_OVERRIDE - No description available - 14 - 1 - read-write - - - SESS_VALID_OVERRIDE - No description available - 13 - 1 - read-write - - - VBUS_VALID_OVERRIDE - No description available - 12 - 1 - read-write - - - ID_DIG_OVERRIDE_EN - No description available - 2 - 1 - read-write - - - SESS_VALID_OVERRIDE_EN - No description available - 1 - 1 - read-write - - - VBUS_VALID_OVERRIDE_EN - No description available - 0 - 1 - read-write - - - - - PHY_CTRL1 - No description available - 0x214 - 32 - 0x00000000 - 0x00100002 - - - UTMI_CFG_RST_N - No description available - 20 - 1 - read-write - - - UTMI_OTG_SUSPENDM - OTG suspend, not utmi_suspendm - 1 - 1 - read-write - - - - - TOP_STATUS - No description available - 0x220 - 32 - 0x00000000 - 0x80000000 - - - WAKEUP_INT_STATUS - No description available - 31 - 1 - read-write - - - - - PHY_STATUS - No description available - 0x224 - 32 - 0x00000000 - 0x800000F5 - - - UTMI_CLK_VALID - No description available - 31 - 1 - read-write - - - LINE_STATE - No description available - 6 - 2 - read-write - - - HOST_DISCONNECT - No description available - 5 - 1 - read-write - - - ID_DIG - No description available - 4 - 1 - read-write - - - UTMI_SESS_VALID - No description available - 2 - 1 - read-write - - - VBUS_VALID - No description available - 0 - 1 - read-write - - - - - - - USB1 - USB1 - USB - 0xf2024000 - - - SDXC0 - SDXC0 - SDXC - 0xf2030000 - - 0x0 - 0x548 - registers - - - - SDMASA - No description available - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - BLOCKCNT_SDMASA - 32-bit Block Count (SDMA System Address) -- SDMA System Address (Host Version 4 Enable = 0): This register contains the system memory address for an SDMA transfer in the 32-bit addressing mode. -When the Host Controller stops an SDMA transfer, this register points to the system address of the next contiguous data position. -It can be accessed only if no transaction is executing. Reading this register during data transfers may -return an invalid value. -- 32-bit Block Count (Host Version 4 Enable = 1): From the Host Controller Version 4.10 specification, this register is redefined as 32-bit Block Count. -The Host Controller decrements the block count of this register for every block transfer and the data transfer stops when the count reaches zero. -This register must be accessed when no transaction is executing. Reading this register during data transfers may return invalid value. -Following are the values for BLOCKCNT_SDMASA: -- 0xFFFF_FFFF: 4G - 1 Block -- -- 0x0000_0002: 2 Blocks -- 0x0000_0001: 1 Block -- 0x0000_0000: Stop Count -Note: -- For Host Version 4 Enable = 0, the Host driver does not program the system address in this register while operating in ADMA mode. -The system address must be programmed in the ADMA System Address register. -- For Host Version 4 Enable = 0, the Host driver programs a non-zero 32-bit block count value in this register when Auto CMD23 is enabled for non-DMA and ADMA modes. -Auto CMD23 cannot be used with SDMA. -- This register must be programmed with a non-zero value for data transfer if the 32-bit Block count register is used instead of the 16-bit Block count register. - 0 - 32 - read-write - - - - - BLK_ATTR - No description available - 0x4 - 32 - 0x00020210 - 0xFFFF7FFF - - - BLOCK_CNT - 16-bit Block Count -- If the Host Version 4 Enable bit is set 0 or the 16-bit Block Count register is set to non-zero, the 16-bit Block Count register is selected. -- If the Host Version 4 Enable bit is set 1 and the 16-bit Block Count register is set to zero, the 32-bit Block Count register is selected. -Following are the values for BLOCK_CNT: -- 0x0: Stop Count -- 0x1: 1 Block -- 0x2: 2 Blocks -- . -- 0xFFFF: 65535 Blocks -Note: For Host Version 4 Enable = 0, this register must be set to 0000h before programming the 32-bit block count register when Auto CMD23 is enabled for non-DMA and ADMA modes. - 16 - 16 - read-write - - - SDMA_BUF_BDARY - SDMA Buffer Boundary -These bits specify the size of contiguous buffer in system memory. -The SDMA transfer waits at every boundary specified by these fields and the Host Controller generates the DMA interrupt to request the Host Driver to update the SDMA System Address register. -Values: -- 0x0 (BYTES_4K): 4K bytes SDMA Buffer Boundary -- 0x1 (BYTES_8K): 8K bytes SDMA Buffer Boundary -- 0x2 (BYTES_16K): 16K bytes SDMA Buffer Boundary -- 0x3 (BYTES_32K): 32K bytes SDMA Buffer Boundary -- 0x4 (BYTES_64K): 64K bytes SDMA Buffer Boundary -- 0x5 (BYTES_128K): 128K bytes SDMA Buffer Boundary -- 0x6 (BYTES_256K): 256K bytes SDMA Buffer Boundary -- 0x7 (BYTES_512K): 512K bytes SDMA Buffer Boundary - 12 - 3 - read-write - - - XFER_BLOCK_SIZE - Transfer Block Size -These bits specify the block size of data transfers. In case of memory, it is set to 512 bytes. It can be accessed only if no transaction is executing. -Read operations during transfers may return an invalid value, and write operations are ignored. Following are the values for XFER_BLOCK_SIZE: -- 0x1: 1 byte -- 0x2: 2 bytes -- 0x3: 3 bytes -- . -- 0x1FF: 511 byte -- 0x200: 512 byt es -- . -- 0x800: 2048 bytes -Note: This register must be programmed with a non-zero value for data transfer. - 0 - 12 - read-write - - - - - CMD_ARG - No description available - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - ARGUMNET - Command Argument -These bits specify the SD/eMMC command argument that is specified in bits 39-8 of the Command format. - 0 - 32 - read-write - - - - - CMD_XFER - No description available - 0xc - 32 - 0x00000000 - 0x3FFF01FF - - - CMD_INDEX - Command Index -These bits are set to the command number that is specified in bits 45-40 of the Command Format. - 24 - 6 - read-write - - - CMD_TYPE - Command Type -These bits indicate the command type. -Note: While issuing Abort CMD using CMD12/CMD52 or reset CMD using CMD0/CMD52, CMD_TYPE field shall be set to 0x3. -Values: -0x3 (ABORT_CMD): Abort -0x2 (RESUME_CMD): Resume -0x1 (SUSPEND_CMD): Suspend -0x0 (NORMAL_CMD): Normal - 22 - 2 - read-write - - - DATA_PRESENT_SEL - Data Present Select -This bit is set to 1 to indicate that data is present and that the data is transferred using the DAT line. This bit is set to 0 in the following instances: -Command using the CMD line -Command with no data transfer but using busy signal on the DAT[0] line -Resume Command -Values: -0x0 (NO_DATA): No Data Present -0x1 (DATA): Data Present - 21 - 1 - read-write - - - CMD_IDX_CHK_ENABLE - Command Index Check Enable -This bit enables the Host Controller to check the index field in the response to verify if it has the same value as the command index. -If the value is not the same, it is reported as a Command Index error. -Note: -Index Check enable must be set to 0 for the command with no response, R2 response, R3 response and R4 response. -For the tuning command, this bit must always be set to enable the index check. -Values: -0x0 (DISABLED): Disable -0x1 (ENABLED): Enable - 20 - 1 - read-write - - - CMD_CRC_CHK_ENABLE - Command CRC Check Enable -This bit enables the Host Controller to check the CRC field in the response. If an error is detected, it is reported as a Command CRC error. -Note: -CRC Check enable must be set to 0 for the command with no response, R3 response, and R4 response. -For the tuning command, this bit must always be set to 1 to enable the CRC check. -Values: -0x0 (DISABLED): Disable -0x1 (ENABLED): Enable - 19 - 1 - read-write - - - SUB_CMD_FLAG - Sub Command Flag -This bit distinguishes between a main command and a sub command. -Values: -0x0 (MAIN): Main Command -0x1 (SUB): Sub Command - 18 - 1 - read-write - - - RESP_TYPE_SELECT - Response Type Select -This bit indicates the type of response expected from the card. -Values: -0x0 (NO_RESP): No Response -0x1 (RESP_LEN_136): Response Length 136 -0x2 (RESP_LEN_48): Response Length 48 -0x3 (RESP_LEN_48B): Response Length 48; Check Busy after response - 16 - 2 - read-write - - - RESP_INT_DISABLE - Response Interrupt Disable -The Host Controller supports response check function to avoid overhead of response error check by the Host driver. -Response types of only R1 and R5 can be checked by the Controller. -If Host Driver checks the response error, set this bit to 0 and wait for Command Complete Interrupt and then check the response register. -If the Host Controller checks the response error, set this bit to 1 and set the Response Error Check Enable bit to 1. -The Command Complete Interrupt is disabled by this bit regardless of the Command Complete Signal Enable. -Note: During tuning (when the Execute Tuning bit in the Host Control2 register is set), the Command Complete Interrupt is not generated irrespective of the Response Interrupt Disable setting. -Values: -- 0x0 (ENABLED): Response Interrupt is enabled -- 0x1 (DISABLED): Response Interrupt is disabled - 8 - 1 - read-write - - - RESP_ERR_CHK_ENABLE - Response Error Check Enable -The Host Controller supports response check function to avoid overhead of response error check by Host driver. Response types of only R1 and R5 can be checked by the Controller. -If the Host Controller checks the response error, set this bit to 1 and set Response Interrupt Disable to 1. If an error is detected, the Response Error interrupt is generated in the Error Interrupt Status register. -Note: -- Response error check must not be enabled for any response type other than R1 and R5. -- Response check must not be enabled for the tuning command. -Values: -- 0x0 (DISABLED): Response Error Check is disabled -- 0x1 (ENABLED): Response Error Check is enabled - 7 - 1 - read-write - - - RESP_TYPE - Response Type R1/R5 -This bit selects either R1 or R5 as a response type when the Response Error Check is selected. -Error statuses checked in R1: -OUT_OF_RANGE -ADDRESS_ERROR -BLOCK_LEN_ERROR -WP_VIOLATION -CARD_IS_LOCKED -COM_CRC_ERROR -CARD_ECC_FAILED -CC_ERROR -ERROR -Response Flags checked in R5: -COM_CRC_ERROR -ERROR -FUNCTION_NUMBER -OUT_OF_RANGE -Values: -0x0 (RESP_R1): R1 (Memory) -0x1 (RESP_R5): R5 (SDIO) - 6 - 1 - read-write - - - MULTI_BLK_SEL - Multi/Single Block Select -This bit is set when issuing multiple-block transfer commands using the DAT line. If this bit is set to 0, it is not necessary to set the Block Count register. -Values: -0x0 (SINGLE): Single Block -0x1 (MULTI): Multiple Block - 5 - 1 - read-write - - - DATA_XFER_DIR - Data Transfer Direction Select -This bit defines the direction of DAT line data transfers. -This bit is set to 1 by the Host Driver to transfer data from the SD/eMMC card to the Host Controller and it is set to 0 for all other commands. -Values: -0x1 (READ): Read (Card to Host) -0x0 (WRITE): Write (Host to Card) - 4 - 1 - read-write - - - AUTO_CMD_ENABLE - Auto Command Enable -This field determines use of Auto Command functions. -Note: In SDIO, this field must be set as 00b (Auto Command Disabled). -Values: -0x0 (AUTO_CMD_DISABLED): Auto Command Disabled -0x1 (AUTO_CMD12_ENABLED): Auto CMD12 Enable -0x2 (AUTO_CMD23_ENABLED): Auto CMD23 Enable -0x3 (AUTO_CMD_AUTO_SEL): Auto CMD Auto Sel - 2 - 2 - read-write - - - BLOCK_COUNT_ENABLE - Block Count Enable -This bit is used to enable the Block Count register, which is relevant for multiple block transfers. -If this bit is set to 0, the Block Count register is disabled, which is useful in executing an infinite transfer. -The Host Driver must set this bit to 0 when ADMA is used. -Values: -0x1 (ENABLED): Enable -0x0 (DISABLED): Disable - 1 - 1 - read-write - - - DMA_ENABLE - DMA Enable -This bit enables the DMA functionality. If this bit is set to 1, a DMA operation begins when the Host Driver writes to the Command register. -You can select one of the DMA modes by using DMA Select in the Host Control 1 register. -Values: -0x1 (ENABLED): DMA Data transfer -0x0 (DISABLED): No data transfer or Non-DMA data transfer - 0 - 1 - read-write - - - - - 4 - 0x4 - RESP01,RESP23,RESP45,RESP67 - RESP[%s] - no description available - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - RESP01 - Command Response -These bits reflect 39-8 bits of SD/eMMC Response Field. -Note: For Auto CMD, the 32-bit response (bits 39-8 of the Response Field) is updated in the RESP[RESP67] register. - 0 - 32 - read-only - - - - - BUF_DATA - No description available - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - BUF_DATA - Buffer Data -These bits enable access to the Host Controller packet buffer. - 0 - 32 - read-write - - - - - PSTATE - No description available - 0x24 - 32 - 0x00000000 - 0x19FF0FFF - - - SUB_CMD_STAT - Sub Command Status -This bit is used to distinguish between a main command and a sub command status. -Values: -0x0 (FALSE): Main Command Status -0x1 (TRUE): Sub Command Status - 28 - 1 - read-only - - - CMD_ISSUE_ERR - Command Not Issued by Error -This bit is set if a command cannot be issued after setting the command register due to an error except the Auto CMD12 error. -Values: -0x0 (FALSE): No error for issuing a command -0x1 (TRUE): Command cannot be issued - 27 - 1 - read-only - - - CMD_LINE_LVL - Command-Line Signal Level -This bit is used to check the CMD line level to recover from errors and for debugging. These bits reflect the value of the sd_cmd_in signal. - 24 - 1 - read-only - - - DAT_3_0 - DAT[3:0] Line Signal Level -This bit is used to check the DAT line level to recover from errors and for debugging. These bits reflect the value of the sd_dat_in (lower nibble) signal. - 20 - 4 - read-only - - - WR_PROTECT_SW_LVL - Write Protect Switch Pin Level -This bit is supported only for memory and combo cards. This bit reflects the synchronized value of the card_write_prot signal. -Values: -0x0 (FALSE): Write protected -0x1 (TRUE): Write enabled - 19 - 1 - read-only - - - CARD_DETECT_PIN_LEVEL - Card Detect Pin Level -This bit reflects the inverse synchronized value of the card_detect_n signal. -Values: -0x0 (FALSE): No card present -0x1 (TRUE): Card Present - 18 - 1 - read-only - - - CARD_STABLE - Card Stable -This bit indicates the stability of the Card Detect Pin Level. A card is not detected if this bit is set to 1 and the value of the CARD_INSERTED bit is 0. -Values: -0x0 (FALSE): Reset or Debouncing -0x1 (TRUE): No Card or Inserted - 17 - 1 - read-only - - - CARD_INSERTED - Card Inserted -This bit indicates whether a card has been inserted. The Host Controller debounces this signal so that Host Driver need not wait for it to stabilize. -Values: -0x0 (FALSE): Reset, Debouncing, or No card -0x1 (TRUE): Card Inserted - 16 - 1 - read-only - - - BUF_RD_ENABLE - Buffer Read Enable -This bit is used for non-DMA transfers. This bit is set if valid data exists in the Host buffer. -Values: -0x0 (DISABLED): Read disable -0x1 (ENABLED): Read enable - 11 - 1 - read-only - - - BUF_WR_ENABLE - Buffer Write Enable -This bit is used for non-DMA transfers. This bit is set if space is available for writing data. -Values: -0x0 (DISABLED): Write disable -0x1 (ENABLED): Write enable - 10 - 1 - read-only - - - RD_XFER_ACTIVE - Read Transfer Active -This bit indicates whether a read transfer is active for SD/eMMC mode. -Values: -0x0 (INACTIVE): No valid data -0x1 (ACTIVE): Transferring data - 9 - 1 - read-only - - - WR_XFER_ACTIVE - Write Transfer Active -This status indicates whether a write transfer is active for SD/eMMC mode. -Values: -0x0 (INACTIVE): No valid data -0x1 (ACTIVE): Transferring data - 8 - 1 - read-only - - - DAT_7_4 - DAT[7:4] Line Signal Level -This bit is used to check the DAT line level to recover from errors and for debugging. These bits reflect the value of the sd_dat_in (upper nibble) signal. - 4 - 4 - read-only - - - RE_TUNE_REQ - Re-Tuning Request -SDXC does not generate retuning request. The software must maintain the Retuning timer. - 3 - 1 - read-only - - - DAT_LINE_ACTIVE - DAT Line Active ( -This bit indicates whether one of the DAT lines on the SD/eMMC bus is in use. -In the case of read transactions, this bit indicates whether a read transfer is executing on the SD/eMMC bus. -In the case of write transactions, this bit indicates whether a write transfer is executing on the SD/eMMC bus. -For a command with busy, this status indicates whether the command executing busy is executing on an SD or eMMC bus. -Values: -0x0 (INACTIVE): DAT Line Inactive -0x1 (ACTIVE): DAT Line Active - 2 - 1 - read-only - - - DAT_INHIBIT - Command Inhibit (DAT) -This bit is generated if either DAT line active or Read transfer active is set to 1. -If this bit is set to 0, it indicates that the Host Controller can issue subsequent SD/eMMC commands. -Values: -0x0 (READY): Can issue command which used DAT line -0x1 (NOT_READY): Cannot issue command which used DAT line - 1 - 1 - read-only - - - CMD_INHIBIT - Command Inhibit (CMD) -This bit indicates the following : -If this bit is set to 0, it indicates that the CMD line is not in use and the Host controller can issue an SD/eMMC command using the CMD line. -This bit is set when the command register is written. This bit is cleared when the command response is received. -This bit is not cleared by the response of auto CMD12/23 but cleared by the response of read/write command. -Values: -0x0 (READY): Host Controller is ready to issue a command -0x1 (NOT_READY): Host Controller is not ready to issue a command - 0 - 1 - read-only - - - - - PROT_CTRL - No description available - 0x28 - 32 - 0x00000000 - 0x070F0F3E - - - CARD_REMOVAL - Wakeup Event Enable on SD Card Removal -This bit enables wakeup event through Card Removal assertion in the Normal Interrupt Status register. -For the SDIO card, Wake Up Support (FN_WUS) in the Card Information Structure (CIS) register does not affect this bit. -Values: -0x0 (DISABLED): Disable -0x1 (ENABLED): Enable - 26 - 1 - read-write - - - CARD_INSERT - Wakeup Event Enable on SD Card Insertion -This bit enables wakeup event through Card Insertion assertion in the Normal Interrupt Status register. -FN_WUS (Wake Up Support) in CIS does not affect this bit. -Values: -0x0 (DISABLED): Disable -0x1 (ENABLED): Enable - 25 - 1 - read-write - - - CARD_INT - Wakeup Event Enable on Card Interrupt -This bit enables wakeup event through a Card Interrupt assertion in the Normal Interrupt Status register. -This bit can be set to 1 if FN_WUS (Wake Up Support) in CIS is set to 1. -Values: -0x0 (DISABLED): Disable -0x1 (ENABLED): Enable - 24 - 1 - read-write - - - INT_AT_BGAP - Interrupt At Block Gap -This bit is valid only in the 4-bit mode of an SDIO card and is used to select a sample point in the interrupt cycle. -Setting to 1 enables interrupt detection at the block gap for a multiple block transfer. -Values: -0x0 (DISABLE): Disabled -0x1 (ENABLE): Enabled - 19 - 1 - read-write - - - RD_WAIT_CTRL - Read Wait Control -This bit is used to enable the read wait protocol to stop read data using DAT[2] line if the card supports read wait. -Otherwise, the Host Controller has to stop the card clock to hold the read data. In UHS-II mode, Read Wait is disabled. -Values: -0x0 (DISABLE): Disable Read Wait Control -0x1 (ENABLE): Enable Read Wait Control - 18 - 1 - read-write - - - CONTINUE_REQ - Continue Request -This bit is used to restart the transaction, which was stopped using the Stop At Block Gap Request. -The Host Controller automatically clears this bit when the transaction restarts. -If stop at block gap request is set to 1, any write to this bit is ignored. -Values: -0x0 (NO_AFFECT): No Affect -0x1 (RESTART): Restart - 17 - 1 - read-write - - - STOP_BG_REQ - Stop At Block Gap Request -This bit is used to stop executing read and write transactions at the next block gap for non-DMA, SDMA, and ADMA transfers. -Values: -0x0 (XFER): Transfer -0x1 (STOP): Stop - 16 - 1 - read-write - - - SD_BUS_VOL_VDD1 - SD Bus Voltage Select for VDD1/eMMC Bus Voltage Select for VDD -These bits enable the Host Driver to select the voltage level for an SD/eMMC card. -Before setting this register, the Host Driver checks the Voltage Support bits in the Capabilities register. -If an unsupported voltage is selected, the Host System does not supply the SD Bus voltage. -The value set in this field is available on the SDXC output signal (sd_vdd1_sel), which is used by the voltage switching circuitry. -SD Bus Voltage Select options: -0x7 : 3.3V(Typical) -0x6 : 3.0V(Typical) -0x5 : 1.8V(Typical) for Embedded -0x4 : 0x0 - Reserved -eMMC Bus Voltage Select options: -0x7 : 3.3V(Typical) -0x6 : 1.8V(Typical) -0x5 : 1.2V(Typical) -0x4 : 0x0 - Reserved -Values: -0x7 (V_3_3): 3.3V (Typ.) -0x6 (V_3_0): 3.0V (Typ.) -0x5 (V_1_8): 1.8V (Typ.) for Embedded -0x4 (RSVD4): Reserved -0x3 (RSVD3): Reserved -0x2 (RSVD2): Reserved -0x1 (RSVD1): Reserved -0x0 (RSVD0): Reserved - 9 - 3 - read-write - - - SD_BUS_PWR_VDD1 - SD Bus Power for VDD1 -This bit enables VDD1 power of the card. -This setting is available on the sd_vdd1_on output of SDXC so that it can be used to control the VDD1 power supply of the card. -Before setting this bit, the SD Host Driver sets the SD Bus Voltage Select bit. If the Host Controller detects a No Card state, this bit is cleared. -In SD mode, if this bit is cleared, the Host Controller stops the SD Clock by clearing the SD_CLK_EN bit in the SYS_CTRL register. -Values: -0x0 (OFF): Power off -0x1 (ON): Power on - 8 - 1 - read-write - - - EXT_DAT_XFER - Extended Data Transfer Width -This bit controls 8-bit bus width mode of embedded device. -Values: -0x1 (EIGHT_BIT): 8-bit Bus Width -0x0 (DEFAULT): Bus Width is selected by the Data Transfer Width - 5 - 1 - read-write - - - DMA_SEL - DMA Select -This field is used to select the DMA type. -When Host Version 4 Enable is 1 in Host Control 2 register: -0x0 : SDMA is selected -0x1 : Reserved -0x2 : ADMA2 is selected -0x3 : ADMA2 or ADMA3 is selected -When Host Version 4 Enable is 0 in Host Control 2 register: -0x0 : SDMA is selected -0x1 : Reserved -0x2 : 32-bit Address ADMA2 is selected -0x3 : 64-bit Address ADMA2 is selected -Values: -0x0 (SDMA): SDMA is selected -0x1 (RSVD_BIT): Reserved -0x2 (ADMA2): ADMA2 is selected -0x3 (ADMA2_3): ADMA2 or ADMA3 is selected - 3 - 2 - read-write - - - HIGH_SPEED_EN - High Speed Enable -this bit is used to determine the selection of preset value for High Speed mode. -Before setting this bit, the Host Driver checks the High Speed Support in the Capabilities register. -Note: SDXC always outputs the sd_cmd_out and sd_dat_out lines at the rising edge of cclk_tx clock irrespective of this bit. -Values: -0x1 (HIGH_SPEED): High Speed mode -0x0 (NORMAL_SPEED): Normal Speed mode - 2 - 1 - read-write - - - DAT_XFER_WIDTH - Data Transfer Width -For SD/eMMC mode,this bit selects the data transfer width of the Host Controller. -The Host Driver sets it to match the data width of the SD/eMMC card. In UHS-II mode, this bit is irrelevant. -Values: -0x1 (FOUR_BIT): 4-bit mode -0x0 (ONE_BIT): 1-bit mode - 1 - 1 - read-write - - - - - SYS_CTRL - No description available - 0x2c - 32 - 0x00000000 - 0x070FFFEF - - - SW_RST_DAT - Software Reset For DAT line -This bit is used in SD/eMMC mode and it resets only a part of the data circuit and the DMA circuit is also reset. -The following registers and bits are cleared by this bit: -Buffer Data Port register --Buffer is cleared and initialized. -Present state register --Buffer Read Enable --Buffer Write Enable --Read Transfer Active --Write Transfer Active --DAT Line Active --Command Inhibit (DAT) -Block Gap Control register --Continue Request --Stop At Block Gap Request -Normal Interrupt status register --Buffer Read Ready --Buffer Write Ready --DMA Interrupt --Block Gap Event --Transfer Complete -In UHS-II mode, this bit shall be set to 0 -Values: -0x0 (FALSE): Work -0x1 (TRUE): Reset - 26 - 1 - read-write - - - SW_RST_CMD - Software Reset For CMD line -This bit resets only a part of the command circuit to be able to issue a command. -It bit is also used to initialize a UHS-II command circuit. -This reset is effective only for a command issuing circuit (including response error statuses related to Command Inhibit (CMD) control) and does not affect the data transfer circuit. -Host Controller can continue data transfer even after this reset is executed while handling subcommand-response errors. -The following registers and bits are cleared by this bit: -Present State register : Command Inhibit (CMD) bit -Normal Interrupt Status register : Command Complete bit -Error Interrupt Status : Response error statuses related to Command Inhibit (CMD) bit -Values: -0x0 (FALSE): Work -0x1 (TRUE): Reset - 25 - 1 - read-write - - - SW_RST_ALL - Software Reset For All -This reset affects the entire Host Controller except for the card detection circuit. -During its initialization, the Host Driver sets this bit to 1 to reset the Host Controller. -All registers are reset except the capabilities register. -If this bit is set to 1, the Host Driver must issue reset command and reinitialize the card. -Values: -0x0 (FALSE): Work -0x1 (TRUE): Reset - 24 - 1 - read-write - - - TOUT_CNT - Data Timeout Counter Value. -This value determines the interval by which DAT line timeouts are detected. -The Timeout clock frequency is generated by dividing the base clock TMCLK value by this value. -When setting this register, prevent inadvertent timeout events by clearing the Data Timeout Error Status Enable (in the Error Interrupt Status Enable register). -The values for these bits are: -0xF : Reserved -0xE : TMCLK x 2^27 -......... -0x1 : TMCLK x 2^14 -0x0 : TMCLK x 2^13 -Note: During a boot operating in an eMMC mode, an application must configure the boot data timeout value (approximately 1 sec) in this bit. - 16 - 4 - read-write - - - FREQ_SEL - SDCLK/RCLK Frequency Select -These bits are used to select the frequency of the SDCLK signal. -These bits depend on setting of Preset Value Enable in the Host Control 2 register. -If Preset Value Enable = 0, these bits are set by the Host Driver. -If Preset Value Enable = 1, these bits are automatically set to a value specified in one of the Preset Value register. -The value is reflected on the lower 8-bit of the card_clk_freq_selsignal. -10-bit Divided Clock Mode: -0x3FF : 1/2046 Divided clock -.......... -N : 1/2N Divided Clock -.......... -0x002 : 1/4 Divided Clock -0x001 : 1/2 Divided Clock -0x000 : Base clock (10MHz - 255 MHz) -Programmable Clock Mode : Enables the Host System to select a fine grain SD clock frequency: -0x3FF : Base clock * M /1024 -.......... -N-1 : Base clock * M /N -.......... -0x002 : Base clock * M /3 -0x001 : Base clock * M /2 -0x000 : Base clock * M - 8 - 8 - read-write - - - UPPER_FREQ_SEL - These bits specify the upper 2 bits of 10-bit SDCLK/RCLK Frequency Select control. -The value is reflected on the upper 2 bits of the card_clk_freq_sel signal. - 6 - 2 - read-write - - - CLK_GEN_SELECT - Clock Generator Select -This bit is used to select the clock generator mode in SDCLK/RCLK Frequency Select. -If Preset Value Enable = 0, this bit is set by the Host Driver. -If Preset Value Enable = 1, this bit is automatically set to a value specified in one of the Preset Value registers. -The value is reflected on the card_clk_gen_sel signal. -Values: -0x0 (FALSE): Divided Clock Mode -0x1 (TRUE): Programmable Clock Mode - 5 - 1 - read-write - - - PLL_ENABLE - PLL Enable -This bit is used to activate the PLL (applicable when Host Version 4 Enable = 1). -When Host Version 4 Enable = 0, INTERNAL_CLK_EN bit may be used to activate PLL. The value is reflected on the card_clk_en signal. -Note: If this bit is not used to to active the PLL when Host Version 4 Enable = 1, it is recommended to set this bit to '1' . -Values: -0x0 (FALSE): PLL is in low power mode -0x1 (TRUE): PLL is enabled - 3 - 1 - read-write - - - SD_CLK_EN - SD/eMMC Clock Enable -This bit stops the SDCLK or RCLK when set to 0. -The SDCLK/RCLK Frequency Select bit can be changed when this bit is set to 0. -The value is reflected on the clk2card_on pin. -Values: -0x0 (FALSE): Disable providing SDCLK/RCLK -0x1 (TRUE): Enable providing SDCLK/RCLK - 2 - 1 - read-write - - - INTERNAL_CLK_STABLE - Internal Clock Stable -This bit enables the Host Driver to check the clock stability twice after the Internal Clock Enable bit is set and after the PLL Enable bit is set. -This bit reflects the synchronized value of the intclk_stable signal after the Internal Clock Enable bit is set to 1, -and also reflects the synchronized value of the card_clk_stable signal after the PLL Enable bit is set to 1. -Values: -0x0 (FALSE): Not Ready -0x1 (TRUE): Ready - 1 - 1 - read-write - - - INTERNAL_CLK_EN - Internal Clock Enable -This bit is set to 0 when the Host Driver is not using the Host Controller or the Host Controller awaits a wakeup interrupt. -The Host Controller must stop its internal clock to enter a very low power state. -However, registers can still be read and written to. The value is reflected on the intclk_en signal. -Note: If this bit is not used to control the internal clock (base clock and master clock), it is recommended to set this bit to '1' . -Values: -0x0 (FALSE): Stop -0x1 (TRUE): Oscillate - 0 - 1 - read-write - - - - - INT_STAT - No description available - 0x30 - 32 - 0x00000000 - 0x1FFFF1FF - - - BOOT_ACK_ERR - Boot Acknowledgment Error -This bit is set when there is a timeout for boot acknowledgement or when detecting boot ack status having a value other than 010. This is applicable only when boot acknowledgement is expected in eMMC mode. -In SD/UHS-II mode, this bit is irrelevant. - 28 - 1 - read-write - - - RESP_ERR - Response Error -Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver during DMA execution. -If Response Error Check Enable is set to 1 in the Transfer Mode register, Host Controller Checks R1 or R5 response. If an error is detected in a response, this bit is set to 1.This is applicable in SD/eMMC mode. -Values: -0x0 (FALSE): No error -0x1 (TRUE): Error - 27 - 1 - read-write - - - TUNING_ERR - Tuning Error -This bit is set when an unrecoverable error is detected in a tuning circuit except during the tuning procedure -(occurrence of an error during tuning procedure is indicated by Sampling Clock Select in the Host Control 2 register). -By detecting Tuning Error, Host Driver needs to abort a command executing and perform tuning. -To reset tuning circuit, Sampling Clock Select is set to 0 before executing tuning procedure. -The Tuning Error is higher priority than the other error interrupts generated during data transfer. -By detecting Tuning Error, the Host Driver must discard data transferred by a current read/write command and retry data transfer after the Host Controller retrieved from the tuning circuit error. -This is applicable in SD/eMMC mode. -Values: -0x0 (FALSE): No error -0x1 (TRUE): Error - 26 - 1 - read-write - - - ADMA_ERR - ADMA Error -This bit is set when the Host Controller detects error during ADMA-based data transfer. The error could be due to following reasons: -Error response received from System bus (Master I/F) -ADMA3,ADMA2 Descriptors invalid -CQE Task or Transfer descriptors invalid -When the error occurs, the state of the ADMA is saved in the ADMA Error Status register. -In eMMC CQE mode: -The Host Controller generates this Interrupt when it detects an invalid descriptor data (Valid=0) at the ST_FDS state. -ADMA Error State in the ADMA Error Status indicates that an error has occurred in ST_FDS state. -The Host Driver may find that Valid bit is not set at the error descriptor. -Values: -0x0 (FALSE): No error -0x1 (TRUE): Error - 25 - 1 - read-write - - - AUTO_CMD_ERR - Auto CMD Error -This error status is used by Auto CMD12 and Auto CMD23 in SD/eMMC mode. -This bit is set when detecting that any of the bits D00 to D05 in Auto CMD Error Status register has changed from 0 to 1. -D07 is effective in case of Auto CMD12. Auto CMD Error Status register is valid while this bit is set to 1 and may be cleared by clearing of this bit. -Values: -0x0 (FALSE): No error -0x1 (TRUE): Error - 24 - 1 - read-write - - - CUR_LMT_ERR - Current Limit Error -By setting the SD Bus Power bit in the Power Control register, the Host Controller is requested to supply power for the SD Bus. -If the Host Controller supports the Current Limit function, it can be protected from an illegal card by stopping power supply to the card in which case this bit indicates a failure status. -A reading of 1 for this bit means that the Host Controller is not supplying power to the SD card due to some failure. -A reading of 0 for this bit means that the Host Controller is supplying power and no error has occurred. -The Host Controller may require some sampling time to detect the current limit. -SDXC Host Controller does not support this function, this bit is always set to 0. -Values: -0x0 (FALSE): No error -0x1 (TRUE): Power Fail - 23 - 1 - read-write - - - DATA_END_BIT_ERR - Data End Bit Error -This error occurs in SD/eMMC mode either when detecting 0 at the end bit position of read data that uses the DAT line or at the end bit position of the CRC status. -Values: -0x0 (FALSE): No error -0x1 (TRUE): Error - 22 - 1 - read-write - - - DATA_CRC_ERR - Data CRC Error -This error occurs in SD/eMMC mode when detecting CRC error when transferring read data which uses the DAT line, -when detecting the Write CRC status having a value of other than 010 or when write CRC status timeout. -Values: -0x0 (FALSE): No error -0x1 (TRUE): Error - 21 - 1 - read-write - - - DATA_TOUT_ERR - Data Timeout Error -This bit is set in SD/eMMC mode when detecting one of the following timeout conditions: -Busy timeout for R1b, R5b type -Busy timeout after Write CRC status -Write CRC Status timeout -Read Data timeout -Values: -0x0 (FALSE): No error -0x1 (TRUE): Time out - 20 - 1 - read-write - - - CMD_IDX_ERR - Command Index Error -This bit is set if a Command Index error occurs in the command respons in SD/eMMC mode. -Values: -0x0 (FALSE): No error -0x1 (TRUE): Error - 19 - 1 - read-write - - - CMD_END_BIT_ERR - Command End Bit Error -This bit is set when detecting that the end bit of a command response is 0 in SD/eMMC mode. -Values: -0x0 (FALSE): No error -0x1 (TRUE): End Bit error generated - 18 - 1 - read-write - - - CMD_CRC_ERR - Command CRC Error -Command CRC Error is generated in SD/eMMC mode for following two cases. -If a response is returned and the Command Timeout Error is set to 0 (indicating no timeout), this bit is set to 1 when detecting a CRC error in the command response. -The Host Controller detects a CMD line conflict by monitoring the CMD line when a command is issued. -If the Host Controller drives the CMD line to 1 level, -but detects 0 level on the CMD line at the next SD clock edge, then the Host Controller aborts the command (stop driving CMD line) and set this bit to 1. -The Command Timeout Error is also set to 1 to distinguish a CMD line conflict. -Values: -0x0 (FALSE): No error -0x1 (TRUE): CRC error generated - 17 - 1 - read-write - - - CMD_TOUT_ERR - Command Timeout Error -In SD/eMMC Mode,this bit is set only if no response is returned within 64 SD clock cycles from the end bit of the command. -If the Host Controller detects a CMD line conflict, along with Command CRC Error bit, this bit is set to 1, without waiting for 64 SD/eMMC card clock cycles. -Values: -0x0 (FALSE): No error -0x1 (TRUE): Time out - 16 - 1 - read-write - - - ERR_INTERRUPT - Error Interrupt -If any of the bits in the Error Interrupt Status register are set, then this bit is set. -Values: -0x0 (FALSE): No Error -0x1 (TRUE): Error - 15 - 1 - read-only - - - CQE_EVENT - Command Queuing Event -This status is set if Command Queuing/Crypto related event has occurred in eMMC/SD mode. Read CQHCI's CQIS/CRNQIS register for more details. -Values: -0x0 (FALSE): No Event -0x1 (TRUE): Command Queuing Event is detected - 14 - 1 - read-write - - - FX_EVENT - FX Event -This status is set when R[14] of response register is set to 1 and Response Type R1/R5 is set to 0 in Transfer Mode register. This interrupt is used with response check function. -Values: -0x0 (FALSE): No Event -0x1 (TRUE): FX Event is detected - 13 - 1 - read-only - - - RE_TUNE_EVENT - Re-tuning Event -This bit is set if the Re-Tuning Request changes from 0 to 1. Re-Tuning request is not supported. - 12 - 1 - read-only - - - CARD_INTERRUPT - Card Interrupt -This bit reflects the synchronized value of: -DAT[1] Interrupt Input for SD Mode -DAT[2] Interrupt Input for UHS-II Mode -Values: -0x0 (FALSE): No Card Interrupt -0x1 (TRUE): Generate Card Interrupt - 8 - 1 - read-only - - - CARD_REMOVAL - Card Removal -This bit is set if the Card Inserted in the Present State register changes from 1 to 0. -Values: -0x0 (FALSE): Card state stable or Debouncing -0x1 (TRUE): Card Removed - 7 - 1 - read-write - - - CARD_INSERTION - Card Insertion -This bit is set if the Card Inserted in the Present State register changes from 0 to 1. -Values: -0x0 (FALSE): Card state stable or Debouncing -0x1 (TRUE): Card Inserted - 6 - 1 - read-write - - - BUF_RD_READY - Buffer Read Ready -This bit is set if the Buffer Read Enable changes from 0 to 1. -Values: -0x0 (FALSE): Not ready to read buffer -0x1 (TRUE): Ready to read buffer - 5 - 1 - read-write - - - BUF_WR_READY - Buffer Write Ready -This bit is set if the Buffer Write Enable changes from 0 to 1. -Values: -0x0 (FALSE): Not ready to write buffer -0x1 (TRUE): Ready to write buffer - 4 - 1 - read-write - - - DMA_INTERRUPT - DMA Interrupt -This bit is set if the Host Controller detects the SDMA Buffer Boundary during transfer. -In case of ADMA, by setting the Int field in the descriptor table, the Host controller generates this interrupt. -This interrupt is not generated after a Transfer Complete. -Values: -0x0 (FALSE): No DMA Interrupt -0x1 (TRUE): DMA Interrupt is generated - 3 - 1 - read-write - - - BGAP_EVENT - Block Gap Event -This bit is set when both read/write transaction is stopped at block gap due to a Stop at Block Gap Request. -Values: -0x0 (FALSE): No Block Gap Event -0x1 (TRUE): Transaction stopped at block gap - 2 - 1 - read-write - - - XFER_COMPLETE - Transfer Complete -This bit is set when a read/write transfer and a command with status busy is completed. -Values: -0x0 (FALSE): Not complete -0x1 (TRUE): Command execution is completed - 1 - 1 - read-write - - - CMD_COMPLETE - Command Complete -In an SD/eMMC Mode, this bit is set when the end bit of a response except for Auto CMD12 and Auto CMD23. -This interrupt is not generated when the Response Interrupt Disable in Transfer Mode Register is set to 1. -Values: -0x0 (FALSE): No command complete -0x1 (TRUE): Command Complete - 0 - 1 - read-write - - - - - INT_STAT_EN - No description available - 0x34 - 32 - 0x00000000 - 0x1FFF71FF - - - BOOT_ACK_ERR_STAT_EN - Boot Acknowledgment Error (eMMC Mode only) -Setting this bit to 1 enables setting of Boot Acknowledgment Error in Error Interrupt Status register (INT_STAT). -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 28 - 1 - read-write - - - RESP_ERR_STAT_EN - Response Error Status Enable (SD Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 27 - 1 - read-write - - - TUNING_ERR_STAT_EN - Tuning Error Status Enable (UHS-I Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 26 - 1 - read-write - - - ADMA_ERR_STAT_EN - ADMA Error Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 25 - 1 - read-write - - - AUTO_CMD_ERR_STAT_EN - Auto CMD Error Status Enable (SD/eMMC Mode only). -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 24 - 1 - read-write - - - CUR_LMT_ERR_STAT_EN - Current Limit Error Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 23 - 1 - read-write - - - DATA_END_BIT_ERR_STAT_EN - Data End Bit Error Status Enable (SD/eMMC Mode only). -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 22 - 1 - read-write - - - DATA_CRC_ERR_STAT_EN - Data CRC Error Status Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 21 - 1 - read-write - - - DATA_TOUT_ERR_STAT_EN - Data Timeout Error Status Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 20 - 1 - read-write - - - CMD_IDX_ERR_STAT_EN - Command Index Error Status Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 19 - 1 - read-write - - - CMD_END_BIT_ERR_STAT_EN - Command End Bit Error Status Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 18 - 1 - read-write - - - CMD_CRC_ERR_STAT_EN - Command CRC Error Status Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 17 - 1 - read-write - - - CMD_TOUT_ERR_STAT_EN - Command Timeout Error Status Enable (SD/eMMC Mode only). -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 16 - 1 - read-write - - - CQE_EVENT_STAT_EN - CQE Event Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 14 - 1 - read-write - - - FX_EVENT_STAT_EN - FX Event Status Enable -This bit is added from Version 4.10. -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 13 - 1 - read-write - - - RE_TUNE_EVENT_STAT_EN - Re-Tuning Event (UHS-I only) Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 12 - 1 - read-write - - - CARD_INTERRUPT_STAT_EN - Card Interrupt Status Enable -If this bit is set to 0, the Host Controller clears the interrupt request to the System. -The Card Interrupt detection is stopped when this bit is cleared and restarted when this bit is set to 1. -The Host Driver may clear the Card Interrupt Status Enable before servicing the Card Interrupt and may set this bit again after all interrupt requests from the card are cleared to prevent inadvertent interrupts. -By setting this bit to 0, interrupt input must be masked by implementation so that the interrupt input is not affected by external signal in any state (for example, floating). -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 8 - 1 - read-write - - - CARD_REMOVAL_STAT_EN - Card Removal Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 7 - 1 - read-write - - - CARD_INSERTION_STAT_EN - Card Insertion Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 6 - 1 - read-write - - - BUF_RD_READY_STAT_EN - Buffer Read Ready Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 5 - 1 - read-write - - - BUF_WR_READY_STAT_EN - Buffer Write Ready Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 4 - 1 - read-write - - - DMA_INTERRUPT_STAT_EN - DMA Interrupt Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 3 - 1 - read-write - - - BGAP_EVENT_STAT_EN - Block Gap Event Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 2 - 1 - read-write - - - XFER_COMPLETE_STAT_EN - Transfer Complete Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 1 - 1 - read-write - - - CMD_COMPLETE_STAT_EN - Command Complete Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 0 - 1 - read-write - - - - - INT_SIGNAL_EN - No description available - 0x38 - 32 - 0x00000000 - 0x1FFF71FF - - - BOOT_ACK_ERR_SIGNAL_EN - Boot Acknowledgment Error (eMMC Mode only). -Setting this bit to 1 enables generating interrupt signal when Boot Acknowledgment Error in Error Interrupt Status register is set. -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 28 - 1 - read-write - - - RESP_ERR_SIGNAL_EN - Response Error Signal Enable (SD Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 27 - 1 - read-write - - - TUNING_ERR_SIGNAL_EN - Tuning Error Signal Enable (UHS-I Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 26 - 1 - read-write - - - ADMA_ERR_SIGNAL_EN - ADMA Error Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 25 - 1 - read-write - - - AUTO_CMD_ERR_SIGNAL_EN - Auto CMD Error Signal Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 24 - 1 - read-write - - - CUR_LMT_ERR_SIGNAL_EN - Current Limit Error Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 23 - 1 - read-write - - - DATA_END_BIT_ERR_SIGNAL_EN - Data End Bit Error Signal Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 22 - 1 - read-write - - - DATA_CRC_ERR_SIGNAL_EN - Data CRC Error Signal Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 21 - 1 - read-write - - - DATA_TOUT_ERR_SIGNAL_EN - Data Timeout Error Signal Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 20 - 1 - read-write - - - CMD_IDX_ERR_SIGNAL_EN - Command Index Error Signal Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): No error -0x1 (TRUE): Error - 19 - 1 - read-write - - - CMD_END_BIT_ERR_SIGNAL_EN - Command End Bit Error Signal Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 18 - 1 - read-write - - - CMD_CRC_ERR_SIGNAL_EN - Command CRC Error Signal Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 17 - 1 - read-write - - - CMD_TOUT_ERR_SIGNAL_EN - Command Timeout Error Signal Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 16 - 1 - read-write - - - CQE_EVENT_SIGNAL_EN - Command Queuing Engine Event Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 14 - 1 - read-write - - - FX_EVENT_SIGNAL_EN - FX Event Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 13 - 1 - read-write - - - RE_TUNE_EVENT_SIGNAL_EN - Re-Tuning Event (UHS-I only) Signal Enable. -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 12 - 1 - read-write - - - CARD_INTERRUPT_SIGNAL_EN - Card Interrupt Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 8 - 1 - read-write - - - CARD_REMOVAL_SIGNAL_EN - Card Removal Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 7 - 1 - read-write - - - CARD_INSERTION_SIGNAL_EN - Card Insertion Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 6 - 1 - read-write - - - BUF_RD_READY_SIGNAL_EN - Buffer Read Ready Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 5 - 1 - read-write - - - BUF_WR_READY_SIGNAL_EN - Buffer Write Ready Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 4 - 1 - read-write - - - DMA_INTERRUPT_SIGNAL_EN - DMA Interrupt Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 3 - 1 - read-write - - - BGAP_EVENT_SIGNAL_EN - Block Gap Event Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 2 - 1 - read-write - - - XFER_COMPLETE_SIGNAL_EN - Transfer Complete Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 1 - 1 - read-write - - - CMD_COMPLETE_SIGNAL_EN - Command Complete Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 0 - 1 - read-write - - - - - AC_HOST_CTRL - No description available - 0x3c - 32 - 0x00000000 - 0xDCCF00BF - - - PRESET_VAL_ENABLE - Preset Value Enable -This bit enables automatic selection of SDCLK frequency and Driver strength Preset Value registers. -When Preset Value Enable is set, SDCLK frequency generation (Frequency Select and Clock Generator Select) and the driver strength selection are performed by the controller. -These values are selected from set of Preset Value registers based on selected speed mode. -Values: -0x0 (FALSE): SDCLK and Driver Strength are controlled by Host Driver -0x1 (TRUE): Automatic Selection by Preset Value are Enabled - 31 - 1 - read-write - - - ASYNC_INT_ENABLE - Asynchronous Interrupt Enable -This bit can be set if a card supports asynchronous interrupts and Asynchronous Interrupt Support is set to 1 in the Capabilities register. -Values: -0x0 (FALSE): Disabled -0x1 (TRUE): Enabled - 30 - 1 - read-write - - - HOST_VER4_ENABLE - Host Version 4 Enable -This bit selects either Version 3.00 compatible mode or Version 4 mode. -Functions of following fields are modified for Host Version 4 mode: -SDMA Address: SDMA uses ADMA System Address (05Fh-058h) instead of SDMA System Address register (003h-000h) -ADMA2/ADMA3 selection: ADMA3 is selected by DMA select in Host Control 1 register -64-bit ADMA Descriptor Size: 128-bit descriptor is used instead of 96-bit descriptor when 64-bit Addressing is set to 1 -Selection of 32-bit/64-bit System Addressing: Either 32-bit or 64-bit system addressing is selected by 64-bit Addressing bit in this register -32-bit Block Count: SDMA System Address register (003h-000h) is modified to 32-bit Block Count register -Note: It is recommended not to program ADMA3 Integrated Descriptor Address registers, -UHS-II registers and Command Queuing registers (if applicable) while operating in Host version less than 4 mode (Host Version 4 Enable = 0). -Values: -0x0 (FALSE): Version 3.00 compatible mode -0x1 (TRUE): Version 4 mode - 28 - 1 - read-write - - - CMD23_ENABLE - CMD23 Enable -If the card supports CMD23, this bit is set to 1. This bit is used to select Auto CMD23 or Auto CMD12 for ADMA3 data transfer. -Values: -0x0 (FALSE): Auto CMD23 is disabled -0x1 (TRUE): Auto CMD23 is enabled - 27 - 1 - read-write - - - ADMA2_LEN_MODE - ADMA2 Length Mode -This bit selects ADMA2 Length mode to be either 16-bit or 26-bit. -Values: -0x0 (FALSE): 16-bit Data Length Mode -0x1 (TRUE): 26-bit Data Length Mode - 26 - 1 - read-write - - - SAMPLE_CLK_SEL - Sampling Clock Select -This bit is used by the Host Controller to select the sampling clock in SD/eMMC mode to receive CMD and DAT. -This bit is set by the tuning procedure and is valid after the completion of tuning (when Execute Tuning is cleared). -Setting this bit to 1 means that tuning is completed successfully and setting this bit to 0 means that tuning has failed. -The value is reflected on the sample_cclk_sel pin. -Values: -0x0 (FALSE): Fixed clock is used to sample data -0x1 (TRUE): Tuned clock is used to sample data - 23 - 1 - read-write - - - EXEC_TUNING - Execute Tuning -This bit is set to 1 to start the tuning procedure in UHS-I/eMMC speed modes and this bit is automatically cleared when tuning procedure is completed. -Values: -0x0 (FALSE): Not Tuned or Tuning completed -0x1 (TRUE): Execute Tuning - 22 - 1 - read-write - - - SIGNALING_EN - 1.8V Signaling Enable -This bit controls voltage regulator for I/O cell in UHS-I/eMMC speed modes. -Setting this bit from 0 to 1 starts changing the signal voltage from 3.3V to 1.8V. -Host Controller clears this bit if switching to 1.8 signaling fails. The value is reflected on the uhs1_swvolt_en pin. -Note: This bit must be set for all UHS-I speed modes (SDR12/SDR25/SDR50/SDR104/DDR50). -Values: -0x0 (V_3_3): 3.3V Signalling -0x1 (V_1_8): 1.8V Signalling - 19 - 1 - read-write - - - UHS_MODE_SEL - UHS Mode/eMMC Speed Mode Select -These bits are used to select UHS mode in the SD mode of operation. In eMMC mode, these bits are used to select eMMC Speed mode. -UHS Mode (SD/UHS-II mode only): -0x0 (SDR12): SDR12/Legacy -0x1 (SDR25): SDR25/High Speed SDR -0x2 (SDR50): SDR50 -0x3 (SDR104): SDR104/HS200 -0x4 (DDR50): DDR50/High Speed DDR -0x5 (RSVD5): Reserved -0x6 (RSVD6): Reserved -0x7 (UHS2): UHS-II/HS400 -eMMC Speed Mode (eMMC mode only): -0x0: Legacy -0x1: High Speed SDR -0x2: Reserved -0x3: HS200 -0x4: High Speed DDR -0x5: Reserved -0x6: Reserved -0x7: HS400 - 16 - 3 - read-write - - - CMD_NOT_ISSUED_AUTO_CMD12 - Command Not Issued By Auto CMD12 Error -If this bit is set to 1, CMD_wo_DAT is not executed due to an Auto CMD12 Error (D04-D01) in this register. -This bit is set to 0 when Auto CMD Error is generated by Auto CMD23. -Values: -0x1 (TRUE): Not Issued -0x0 (FALSE): No Error - 7 - 1 - read-only - - - AUTO_CMD_RESP_ERR - Auto CMD Response Error -This bit is set when Response Error Check Enable in the Transfer Mode register is set to 1 and an error is detected in R1 response of either Auto CMD12 or CMD13. -This status is ignored if any bit between D00 to D04 is set to 1. -Values: -0x1 (TRUE): Error -0x0 (FALSE): No Error - 5 - 1 - read-only - - - AUTO_CMD_IDX_ERR - Auto CMD Index Error -This bit is set if the command index error occurs in response to a command. -Values: -0x1 (TRUE): Error -0x0 (FALSE): No Error - 4 - 1 - read-only - - - AUTO_CMD_EBIT_ERR - Auto CMD End Bit Error -This bit is set when detecting that the end bit of command response is 0. -Values: -0x1 (TRUE): End Bit Error Generated -0x0 (FALSE): No Error - 3 - 1 - read-only - - - AUTO_CMD_CRC_ERR - Auto CMD CRC Error -This bit is set when detecting a CRC error in the command response. -Values: -0x1 (TRUE): CRC Error Generated -0x0 (FALSE): No Error - 2 - 1 - read-only - - - AUTO_CMD_TOUT_ERR - Auto CMD Timeout Error -This bit is set if no response is returned with 64 SDCLK cycles from the end bit of the command. -If this bit is set to 1, error status bits (D04-D01) are meaningless. -Values: -0x1 (TRUE): Time out -0x0 (FALSE): No Error - 1 - 1 - read-only - - - AUTO_CMD12_NOT_EXEC - Auto CMD12 Not Executed -If multiple memory block data transfer is not started due to a command error, this bit is not set because it is not necessary to issue an Auto CMD12. -Setting this bit to 1 means that the Host Controller cannot issue Auto CMD12 to stop multiple memory block data transfer, due to some error. - If this bit is set to 1, error status bits (D04-D01) is meaningless. -This bit is set to 0 when Auto CMD Error is generated by Auto CMD23. -Values: -0x1 (TRUE): Not Executed -0x0 (FALSE): Executed - 0 - 1 - read-only - - - - - CAPABILITIES1 - No description available - 0x40 - 32 - 0x00000000 - 0xE7EFFFBF - - - SLOT_TYPE_R - Slot Type -These bits indicate usage of a slot by a specific Host System. -Values: -0x0 (REMOVABLE_SLOT): Removable Card Slot -0x1 (EMBEDDED_SLOT): Embedded Slot for one Device -0x2 (SHARED_SLOT): Shared Bus Slot (SD mode) -0x3 (UHS2_EMBEDDED_SLOT): UHS-II Multiple Embedded Devices - 30 - 2 - read-only - - - ASYNC_INT_SUPPORT - Asynchronous Interrupt Support (SD Mode only) -Values: -0x0 (FALSE): Asynchronous Interrupt Not Supported -0x1 (TRUE): Asynchronous Interrupt Supported - 29 - 1 - read-only - - - VOLT_18 - Voltage Support for 1.8V -Values: -0x0 (FALSE): 1.8V Not Supported -0x1 (TRUE): 1.8V Supported - 26 - 1 - read-only - - - VOLT_30 - Voltage Support for SD 3.0V or Embedded 1.2V -Values: -0x0 (FALSE): SD 3.0V or Embedded 1.2V Not Supported -0x1 (TRUE): SD 3.0V or Embedded Supported - 25 - 1 - read-only - - - VOLT_33 - Voltage Support for 3.3V -Values: -0x0 (FALSE): 3.3V Not Supported -0x1 (TRUE): 3.3V Supported - 24 - 1 - read-only - - - SUS_RES_SUPPORT - Suspense/Resume Support -This bit indicates whether the Host Controller supports Suspend/Resume functionality. -If this bit is 0, the Host Driver does not issue either Suspend or Resume commands because the Suspend and Resume mechanism is not supported. -Values: -0x0 (FALSE): Not Supported -0x1 (TRUE): Supported - 23 - 1 - read-only - - - SDMA_SUPPORT - SDMA Support -This bit indicates whether the Host Controller is capable of using SDMA to transfer data between the system memory and the Host Controller directly. -Values: -0x0 (FALSE): SDMA not Supported -0x1 (TRUE): SDMA Supported - 22 - 1 - read-only - - - HIGH_SPEED_SUPPORT - High Speed Support -This bit indicates whether the Host Controller and the Host System supports High Speed mode and they can supply the SD Clock frequency from 25 MHz to 50 MHz. -Values: -0x0 (FALSE): High Speed not Supported -0x1 (TRUE): High Speed Supported - 21 - 1 - read-only - - - ADMA2_SUPPORT - ADMA2 Support -This bit indicates whether the Host Controller is capable of using ADMA2. -Values: -0x0 (FALSE): ADMA2 not Supported -0x1 (TRUE): ADMA2 Supported - 19 - 1 - read-only - - - EMBEDDED_8_BIT - 8-bit Support for Embedded Device -This bit indicates whether the Host Controller is capable of using an 8-bit bus width mode. This bit is not effective when the Slot Type is set to 10b. -Values: -0x0 (FALSE): 8-bit Bus Width not Supported -0x1 (TRUE): 8-bit Bus Width Supported - 18 - 1 - read-only - - - MAX_BLK_LEN - Maximum Block Length -This bit indicates the maximum block size that the Host driver can read and write to the buffer in the Host Controller. -The buffer transfers this block size without wait cycles. The transfer block length is always 512 bytes for the SD Memory irrespective of this bit -Values: -0x0 (ZERO): 512 Byte -0x1 (ONE): 1024 Byte -0x2 (TWO): 2048 Byte -0x3 (THREE): Reserved - 16 - 2 - read-only - - - BASE_CLK_FREQ - Base Clock Frequency for SD clock -These bits indicate the base (maximum) clock frequency for the SD Clock. The definition of these bits depend on the Host Controller Version. -6-Bit Base Clock Frequency: This mode is supported by the Host Controller version 1.00 and 2.00. -The upper 2 bits are not effective and are always 0. The unit values are 1 MHz. The supported clock range is 10 MHz to 63 MHz. --0x00 : Get information through another method --0x01 : 1 MHz --0x02 : 2 MHz --............. --0x3F : 63 MHz --0x40-0xFF : Not Supported -8-Bit Base Clock Frequency: This mode is supported by the Host Controller version 3.00. The unit values are 1 MHz. The supported clock range is 10 MHz to 255 MHz. --0x00 : Get information through another method --0x01 : 1 MHz --0x02 : 2 MHz --............ --0xFF : 255 MHz -If the frequency is 16.5 MHz, the larger value is set to 0001001b (17 MHz) because the Host Driver uses this value to calculate the clock divider value and it does not exceed the upper limit of the SD Clock frequency. -If these bits are all 0, the Host system has to get information using a different method. - 8 - 8 - read-only - - - TOUT_CLK_UNIT - Timeout Clock Unit -This bit shows the unit of base clock frequency used to detect Data TImeout Error. -Values: -0x0 (KHZ): KHz -0x1 (MHZ): MHz - 7 - 1 - read-only - - - TOUT_CLK_FREQ - Timeout Clock Frequency -This bit shows the base clock frequency used to detect Data Timeout Error. The Timeout Clock unit defines the unit of timeout clock frequency. It can be KHz or MHz. -0x00 : Get information through another method -0x01 : 1KHz / 1MHz -0x02 : 2KHz / 2MHz -0x03 : 3KHz / 3MHz - ........... -0x3F : 63KHz / 63MHz - 0 - 6 - read-only - - - - - CAPABILITIES2 - No description available - 0x44 - 32 - 0x00000000 - 0x18FFEF7F - - - VDD2_18V_SUPPORT - 1.8V VDD2 Support -This bit indicates support of VDD2 for the Host System. -0x0 (FALSE): 1.8V VDD2 is not Supported -0x1 (TRUE): 1.8V VDD2 is Supported - 28 - 1 - read-only - - - ADMA3_SUPPORT - ADMA3 Support -This bit indicates whether the Host Controller is capable of using ADMA3. -Values: -0x0 (FALSE): ADMA3 not Supported -0x1 (TRUE): ADMA3 Supported - 27 - 1 - read-only - - - CLK_MUL - Clock Multiplier -These bits indicate the clock multiplier of the programmable clock generator. Setting these bits to 0 means that the Host Controller does not support a programmable clock generator. -0x0: Clock Multiplier is not Supported -0x1: Clock Multiplier M = 2 -0x2: Clock Multiplier M = 3 - ......... -0xFF: Clock Multiplier M = 256 - 16 - 8 - read-only - - - RE_TUNING_MODES - Re-Tuning Modes (UHS-I only) -These bits select the re-tuning method and limit the maximum data length. -Values: -0x0 (MODE1): Timer -0x1 (MODE2): Timer and Re-Tuning Request (Not supported) -0x2 (MODE3): Auto Re-Tuning (for transfer) -0x3 (RSVD_MODE): Reserved - 14 - 2 - read-only - - - USE_TUNING_SDR50 - Use Tuning for SDR50 (UHS-I only) -Values: -0x0 (ZERO): SDR50 does not require tuning -0x1 (ONE): SDR50 requires tuning - 13 - 1 - read-only - - - RETUNE_CNT - Timer Count for Re-Tuning (UHS-I only) -0x0: Re-Tuning Timer disabled -0x1: 1 seconds -0x2: 2 seconds -0x3: 4 seconds - ........ -0xB: 1024 seconds -0xC: Reserved -0xD: Reserved -0xE: Reserved -0xF: Get information from other source - 8 - 4 - read-only - - - DRV_TYPED - Driver Type D Support (UHS-I only) -This bit indicates support of Driver Type D for 1.8 Signaling. -Values: -0x0 (FALSE): Driver Type D is not supported -0x1 (TRUE): Driver Type D is supported - 6 - 1 - read-only - - - DRV_TYPEC - Driver Type C Support (UHS-I only) -This bit indicates support of Driver Type C for 1.8 Signaling. -Values: -0x0 (FALSE): Driver Type C is not supported -0x1 (TRUE): Driver Type C is supported - 5 - 1 - read-only - - - DRV_TYPEA - Driver Type A Support (UHS-I only) -This bit indicates support of Driver Type A for 1.8 Signaling. -Values: -0x0 (FALSE): Driver Type A is not supported -0x1 (TRUE): Driver Type A is supported - 4 - 1 - read-only - - - UHS2_SUPPORT - UHS-II Support (UHS-II only) -This bit indicates whether Host Controller supports UHS-II. -Values: -0x0 (FALSE): UHS-II is not supported -0x1 (TRUE): UHS-II is supported - 3 - 1 - read-only - - - DDR50_SUPPORT - DDR50 Support (UHS-I only) -Values: -0x0 (FALSE): DDR50 is not supported -0x1 (TRUE): DDR50 is supported - 2 - 1 - read-only - - - SDR104_SUPPORT - SDR104 Support (UHS-I only) -This bit mentions that SDR104 requires tuning. -Values: -0x0 (FALSE): SDR104 is not supported -0x1 (TRUE): SDR104 is supported - 1 - 1 - read-only - - - SDR50_SUPPORT - SDR50 Support (UHS-I only) -This bit indicates that SDR50 is supported. The bit 13 (USE_TUNING_SDR50) indicates whether SDR50 requires tuning or not. -Values: -0x0 (FALSE): SDR50 is not supported -0x1 (TRUE): SDR50 is supported - 0 - 1 - read-only - - - - - CURR_CAPABILITIES1 - No description available - 0x48 - 32 - 0x00000000 - 0x00FFFFFF - - - MAX_CUR_18V - Maximum Current for 1.8V -This bit specifies the Maximum Current for 1.8V VDD1 power supply for the card. -0: Get information through another method -1: 4mA -2: 8mA -3: 13mA -....... -255: 1020mA - 16 - 8 - read-only - - - MAX_CUR_30V - Maximum Current for 3.0V -This bit specifies the Maximum Current for 3.0V VDD1 power supply for the card. -0: Get information through another method -1: 4mA -2: 8mA -3: 13mA -....... -255: 1020mA - 8 - 8 - read-only - - - MAX_CUR_33V - Maximum Current for 3.3V -This bit specifies the Maximum Current for 3.3V VDD1 power supply for the card. -0: Get information through another method -1: 4mA -2: 8mA -3: 13mA -....... -255: 1020mA - 0 - 8 - read-only - - - - - CURR_CAPABILITIES2 - No description available - 0x4c - 32 - 0x00000000 - 0x000000FF - - - MAX_CUR_VDD2_18V - Maximum Current for 1.8V VDD2 -This bit specifies the Maximum Current for 1.8V VDD2 power supply for the UHS-II card. -0: Get information through another method -1: 4mA -2: 8mA -3: 13mA -....... -255: 1020mA - 0 - 8 - read-only - - - - - FORCE_EVENT - No description available - 0x50 - 32 - 0x00000000 - 0x1FFF00BF - - - FORCE_BOOT_ACK_ERR - Force Event for Boot Ack error -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Boot ack Error Status is set - 28 - 1 - write-only - - - FORCE_RESP_ERR - Force Event for Response Error (SD Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Response Error Status is set - 27 - 1 - write-only - - - FORCE_TUNING_ERR - Force Event for Tuning Error (UHS-I Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Tuning Error Status is set - 26 - 1 - write-only - - - FORCE_ADMA_ERR - Force Event for ADMA Error -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): ADMA Error Status is set - 25 - 1 - write-only - - - FORCE_AUTO_CMD_ERR - Force Event for Auto CMD Error (SD/eMMC Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Auto CMD Error Status is set - 24 - 1 - write-only - - - FORCE_CUR_LMT_ERR - Force Event for Current Limit Error -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Current Limit Error Status is set - 23 - 1 - write-only - - - FORCE_DATA_END_BIT_ERR - Force Event for Data End Bit Error (SD/eMMC Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Data End Bit Error Status is set - 22 - 1 - write-only - - - FORCE_DATA_CRC_ERR - Force Event for Data CRC Error (SD/eMMC Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Data CRC Error Status is set - 21 - 1 - write-only - - - FORCE_DATA_TOUT_ERR - Force Event for Data Timeout Error (SD/eMMC Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Data Timeout Error Status is set - 20 - 1 - write-only - - - FORCE_CMD_IDX_ERR - Force Event for Command Index Error (SD/eMMC Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Command Index Error Status is set - 19 - 1 - write-only - - - FORCE_CMD_END_BIT_ERR - Force Event for Command End Bit Error (SD/eMMC Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Command End Bit Error Status is set - 18 - 1 - write-only - - - FORCE_CMD_CRC_ERR - Force Event for Command CRC Error (SD/eMMC Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Command CRC Error Status is set - 17 - 1 - write-only - - - FORCE_CMD_TOUT_ERR - Force Event for Command Timeout Error (SD/eMMC Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Command Timeout Error Status is set - 16 - 1 - write-only - - - FORCE_CMD_NOT_ISSUED_AUTO_CMD12 - Force Event for Command Not Issued By Auto CMD12 Error -Values: -0x1 (TRUE): Command Not Issued By Auto CMD12 Error Status is set -0x0 (FALSE): Not Affected - 7 - 1 - write-only - - - FORCE_AUTO_CMD_RESP_ERR - Force Event for Auto CMD Response Error -Values: -0x1 (TRUE): Auto CMD Response Error Status is set -0x0 (FALSE): Not Affected - 5 - 1 - write-only - - - FORCE_AUTO_CMD_IDX_ERR - Force Event for Auto CMD Index Error -Values: -0x1 (TRUE): Auto CMD Index Error Status is set -0x0 (FALSE): Not Affected - 4 - 1 - write-only - - - FORCE_AUTO_CMD_EBIT_ERR - Force Event for Auto CMD End Bit Error -Values: -0x1 (TRUE): Auto CMD End Bit Error Status is set -0x0 (FALSE): Not Affected - 3 - 1 - write-only - - - FORCE_AUTO_CMD_CRC_ERR - Force Event for Auto CMD CRC Error -Values: -0x1 (TRUE): Auto CMD CRC Error Status is set -0x0 (FALSE): Not Affected - 2 - 1 - write-only - - - FORCE_AUTO_CMD_TOUT_ERR - Force Event for Auto CMD Timeout Error -Values: -0x1 (TRUE): Auto CMD Timeout Error Status is set -0x0 (FALSE): Not Affected - 1 - 1 - write-only - - - FORCE_AUTO_CMD12_NOT_EXEC - Force Event for Auto CMD12 Not Executed -Values: -0x1 (TRUE): Auto CMD12 Not Executed Status is set -0x0 (FALSE): Not Affected - 0 - 1 - write-only - - - - - ADMA_ERR_STAT - No description available - 0x54 - 32 - 0x00000000 - 0x00000007 - - - ADMA_LEN_ERR - ADMA Length Mismatch Error States -This error occurs in the following instances: -While the Block Count Enable is being set, the total data length specified by the Descriptor table is different from that specified by the Block Count and Block Length -When the total data length cannot be divided by the block length -Values: -0x0 (NO_ERR): No Error -0x1 (ERROR): Error - 2 - 1 - read-only - - - ADMA_ERR_STATES - ADMA Error States -These bits indicate the state of ADMA when an error occurs during ADMA data transfer. -Values: -0x0 (ST_STOP): Stop DMA - SYS_ADR register points to a location next to the error descriptor -0x1 (ST_FDS): Fetch Descriptor - SYS_ADR register points to the error descriptor -0x2 (UNUSED): Never set this state -0x3 (ST_TFR): Transfer Data - SYS_ADR register points to a location next to the error descriptor - 0 - 2 - read-only - - - - - ADMA_SYS_ADDR - No description available - 0x58 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADMA_SA - ADMA System Address -These bits indicate the lower 32 bits of the ADMA system address. -SDMA: If Host Version 4 Enable is set to 1, this register stores the system address of the data location -ADMA2: This register stores the byte address of the executing command of the descriptor table -ADMA3: This register is set by ADMA3. ADMA2 increments the address of this register that points to the next line, every time a Descriptor line is fetched. - 0 - 32 - read-write - - - - - 11 - 0x2 - INIT,DS,HS,SDR12,SDR25,SDR50,SDR104,DDR50,rsv8,rsv9,UHS2 - PRESET[%s] - no description available - 0x60 - 16 - 0x0000 - 0x07FF - - - CLK_GEN_SEL_VAL - Clock Generator Select Value -This bit is effective when the Host Controller supports a programmable clock generator. -Values: -0x0 (FALSE): Host Controller Ver2.0 Compatible Clock Generator -0x1 (PROG): Programmable Clock Generator - 10 - 1 - read-only - - - FREQ_SEL_VAL - SDCLK/RCLK Frequency Select Value -10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System. - 0 - 10 - read-only - - - - - ADMA_ID_ADDR - No description available - 0x78 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADMA_ID_ADDR - ADMA Integrated Descriptor Address -These bits indicate the lower 32-bit of the ADMA Integrated Descriptor address. -The start address of Integrated Descriptor is set to these register bits. -The ADMA3 fetches one Descriptor Address and increments these bits to indicate the next Descriptor address. - 0 - 32 - read-write - - - - - P_EMBEDDED_CNTRL - No description available - 0xe6 - 16 - 0x0000 - 0x0FFF - - - REG_OFFSET_ADDR - Offset Address of Embedded Control register. - 0 - 12 - read-only - - - - - P_VENDOR_SPECIFIC_AREA - No description available - 0xe8 - 16 - 0x0000 - 0x0FFF - - - REG_OFFSET_ADDR - Base offset Address for Vendor-Specific registers. - 0 - 12 - read-only - - - - - P_VENDOR2_SPECIFIC_AREA - No description available - 0xea - 16 - 0x0000 - 0xFFFF - - - REG_OFFSET_ADDR - Base offset Address for Command Queuing registers. - 0 - 16 - read-only - - - - - SLOT_INTR_STATUS - No description available - 0xfc - 16 - 0x0000 - 0x00FF - - - INTR_SLOT - Interrupt signal for each Slot -These status bits indicate the logical OR of Interrupt signal and Wakeup signal for each slot. -A maximum of 8 slots can be defined. If one interrupt signal is associated with multiple slots, the Host Driver can identify the interrupt that is generated by reading these bits. - By a power on reset or by setting Software Reset For All bit, the interrupt signals are de-asserted and this status reads 00h. -Bit 00: Slot 1 -Bit 01: Slot 2 -Bit 02: Slot 3 -.......... -.......... -Bit 07: Slot 8 -Note: MSHC Host Controller support single card slot. This register shall always return 0. - 0 - 8 - read-only - - - - - CQVER - No description available - 0x180 - 32 - 0x00000000 - 0x00000FFF - - - EMMC_VER_MAHOR - This bit indicates the eMMC major version (1st digit left of decimal point) in BCD format. - 8 - 4 - read-only - - - EMMC_VER_MINOR - This bit indicates the eMMC minor version (1st digit right of decimal point) in BCD format. - 4 - 4 - read-only - - - EMMC_VER_SUFFIX - This bit indicates the eMMC version suffix (2nd digit right of decimal point) in BCD format. - 0 - 4 - read-only - - - - - CQCAP - No description available - 0x184 - 32 - 0x00000000 - 0x1000F3FF - - - CRYPTO_SUPPORT - Crypto Support -This bit indicates whether the Host Controller supports cryptographic operations. -Values: -0x0 (FALSE): Crypto not Supported -0x1 (TRUE): Crypto Supported - 28 - 1 - read-only - - - ITCFMUL - Internal Timer Clock Frequency Multiplier (ITCFMUL) -This field indicates the frequency of the clock used for interrupt coalescing timer and for determining the SQS -polling period. See ITCFVAL definition for details. Values 0x5 to 0xF are reserved. -Values: -0x0 (CLK_1KHz): 1KHz clock -0x1 (CLK_10KHz): 10KHz clock -0x2 (CLK_100KHz): 100KHz clock -0x3 (CLK_1MHz): 1MHz clock -0x4 (CLK_10MHz): 10MHz clock - 12 - 4 - read-only - - - ITCFVAL - Internal Timer Clock Frequency Value (ITCFVAL) -This field scales the frequency of the timer clock provided by ITCFMUL. The Final clock frequency of actual timer clock is calculated as ITCFVAL* ITCFMUL. - 0 - 10 - read-only - - - - - CQCFG - No description available - 0x188 - 32 - 0x00000000 - 0x00001101 - - - DCMD_EN - This bit indicates to the hardware whether the Task -Descriptor in slot #31 of the TDL is a data transfer descriptor or a direct-command descriptor. CQE uses this bit when a task is issued in slot #31, to determine how to decode the Task Descriptor. -Values: -0x1 (SLOT31_DCMD_ENABLE): Task descriptor in slot #31 is a DCMD Task Descriptor -0x0 (SLOT31_DCMD_DISABLE): Task descriptor in slot #31 is a data Transfer Task Descriptor - 12 - 1 - read-write - - - TASK_DESC_SIZE - Bit Value Description -This bit indicates the size of task descriptor used in host memory. This bit can only be configured when Command Queuing Enable bit is 0 (command queuing is disabled). -Values: -0x1 (TASK_DESC_128b): Task descriptor size is 128 bits -0x0 (TASK_DESC_64b): Task descriptor size is 64 bit - 8 - 1 - read-write - - - CQ_EN - No description available - 0 - 1 - read-write - - - - - CQCTL - No description available - 0x18c - 32 - 0x00000000 - 0x00000101 - - - CLR_ALL_TASKS - Clear all tasks -This bit can only be written when the controller is halted. This bit does not clear tasks in the device. The software has to use the CMDQ_TASK_MGMT command to clear device's queue. -Values: -0x1 (CLEAR_ALL_TASKS): Clears all the tasks in the controller -0x0 (NO_EFFECT): Programming 0 has no effect - 8 - 1 - read-write - - - HALT - Halt request and resume -Values: -0x1 (HALT_CQE): Software writes 1 to this bit when it wants to acquire software control over the eMMC bus and to disable CQE from issuing command on the bus. -For example, issuing a Discard Task command (CMDQ_TASK_MGMT). -When the software writes 1, CQE completes the ongoing task (if any in progress). -After the task is completed and the CQE is in idle state, CQE does not issue new commands and indicates to the software by setting this bit to 1. -The software can poll on this bit until it is set to 1 and only then send commands on the eMMC bus. -0x0 (RESUME_CQE): Software writes 0 to this bit to exit from the halt state and resume CQE activity - 0 - 1 - read-write - - - - - CQIS - No description available - 0x190 - 32 - 0x00000000 - 0x0000000F - - - TCL - Task cleared interrupt -This status bit is asserted (if CQISE.TCL_STE=1) when a task clear operation is completed by CQE. -The completed task clear operation is either an individual task clear (by writing CQTCLR) or clearing of all tasks (by writing CQCTL). -A value of 1 clears this status bit. -Values: -0x1 (SET): TCL Interrupt is set -0x0 (NOTSET): TCL Interrupt is not set - 3 - 1 - read-write - - - RED - Response error detected interrupt -This status bit is asserted (if CQISE.RED_STE=1) when a response is received with an error bit set in the device status -field. Configure the CQRMEM register to identify device status bit fields that may trigger an interrupt and that are masked. -A value of 1 clears this status bit. -Values: -0x1 (SET): RED Interrupt is set -0x0 (NOTSET): RED Interrupt is not set - 2 - 1 - read-write - - - TCC - Task complete interrupt -This status bit is asserted (if CQISE.TCC_STE=1) when at least one of the following conditions are met: -A task is completed and the INT bit is set in its Task Descriptor -Interrupt caused by Interrupt Coalescing logic due to timeout -Interrupt Coalescing logic reached the configured threshold -A value of 1 clears this status bit - 1 - 1 - read-write - - - HAC - Halt complete interrupt -This status bit is asserted (only if CQISE.HAC_STE=1) when halt bit in the CQCTL register transitions from 0 to 1 indicating that the host controller has completed its current ongoing task and has entered halt state. -A value of 1 clears this status bit. -Values: -0x1 (SET): HAC Interrupt is set -0x0 (NOTSET): HAC Interrupt is not set - 0 - 1 - read-write - - - - - CQISE - No description available - 0x194 - 32 - 0x00000000 - 0x0000000F - - - TCL_STE - Task cleared interrupt status enable -Values: -0x1 (INT_STS_ENABLE): CQIS.TCL is set when its interrupt condition is active -0x0 (INT_STS_DISABLE): CQIS.TCL is disabled - 3 - 1 - read-write - - - RED_STE - Response error detected interrupt status enable -Values: -0x1 (INT_STS_ENABLE): CQIS.RED is set when its interrupt condition is active -0x0 (INT_STS_DISABLE): CQIS.RED is disabled - 2 - 1 - read-write - - - TCC_STE - Task complete interrupt status enable -Values: -0x1 (INT_STS_ENABLE): CQIS.TCC is set when its interrupt condition is active -0x0 (INT_STS_DISABLE): CQIS.TCC is disabled - 1 - 1 - read-write - - - HAC_STE - Halt complete interrupt status enable -Values: -0x1 (INT_STS_ENABLE): CQIS.HAC is set when its interrupt condition is active -0x0 (INT_STS_DISABLE): CQIS.HAC is disabled - 0 - 1 - read-write - - - - - CQISGE - No description available - 0x198 - 32 - 0x00000000 - 0x0000000F - - - TCL_SGE - Task cleared interrupt signal enable -Values: -0x1 (INT_SIG_ENABLE): CQIS.TCL interrupt signal generation is active -0x0 (INT_SIG_DISABLE): CQIS.TCL interrupt signal generation is disabled - 3 - 1 - read-write - - - RED_SGE - Response error detected interrupt signal enable -Values: -0x1 (INT_SIG_ENABLE): CQIS.RED interrupt signal generation is active -0x0 (INT_SIG_DISABLE): CQIS.RED interrupt signal generation is disabled - 2 - 1 - read-write - - - TCC_SGE - Task complete interrupt signal enable -Values: -0x1 (INT_SIG_ENABLE): CQIS.TCC interrupt signal generation is active -0x0 (INT_SIG_DISABLE): CQIS.TCC interrupt signal generation is disabled - 1 - 1 - read-write - - - HAC_SGE - Halt complete interrupt signal enable -Values: -0x1 (INT_SIG_ENABLE): CQIS.HAC interrupt signal generation is active -0x0 (INT_SIG_DISABLE): CQIS.HAC interrupt signal generation is disabled - 0 - 1 - read-write - - - - - CQIC - No description available - 0x19c - 32 - 0x00000000 - 0x80119FFF - - - INTC_EN - Interrupt Coalescing Enable Bit -Values: -0x1 (ENABLE_INT_COALESCING): Interrupt coalescing mechanism is active. Interrupts are counted and timed, and coalesced interrupts are generated -0x0 (DISABLE_INT_COALESCING): Interrupt coalescing mechanism is disabled (Default) - 31 - 1 - read-write - - - INTC_STAT - Interrupt Coalescing Status Bit -This bit indicates to the software whether any tasks (with INT=0) have completed and counted towards interrupt -coalescing (that is, this is set if and only if INTC counter > 0). -Values: -0x1 (INTC_ATLEAST1_COMP): At least one INT0 task completion has been counted (INTC counter > 0) -0x0 (INTC_NO_TASK_COMP): INT0 Task completions have not occurred since last counter reset (INTC counter == 0) - 20 - 1 - read-only - - - INTC_RST - Counter and Timer Reset -When host driver writes 1, the interrupt coalescing timer and counter are reset. -Values: -0x1 (ASSERT_INTC_RESET): Interrupt coalescing timer and counter are reset -0x0 (NO_EFFECT): No Effect - 16 - 1 - write-only - - - INTC_TH_WEN - Interrupt Coalescing Counter Threshold Write Enable -When software writes 1 to this bit, the value INTC_TH is updated with the contents written on the same cycle. -Values: -0x1 (WEN_SET): Sets INTC_TH_WEN -0x0 (WEN_CLR): Clears INTC_TH_WEN - 15 - 1 - write-only - - - INTC_TH - Interrupt Coalescing Counter Threshold filed -Software uses this field to configure the number of task completions (only tasks with INT=0 in the Task Descriptor), which are required in order to generate an interrupt. -Counter Operation: As data transfer tasks with INT=0 complete, they are counted by CQE. -The counter is reset by software during the interrupt service routine. -The counter stops counting when it reaches the value configured in INTC_TH, and generates interrupt. -0x0: Interrupt coalescing feature disabled -0x1: Interrupt coalescing interrupt generated after 1 task when INT=0 completes -0x2: Interrupt coalescing interrupt generated after 2 tasks when INT=0 completes -........ -0x1f: Interrupt coalescing interrupt generated after 31 tasks when INT=0 completes -To write to this field, the INTC_TH_WEN bit must be set during the same write operation. - 8 - 5 - write-only - - - TOUT_VAL_WEN - When software writes 1 to this bit, the value TOUT_VAL is updated with the contents written on the same cycle. -Values: -0x1 (WEN_SET): Sets TOUT_VAL_WEN -0x0 (WEN_CLR): clears TOUT_VAL_WEN - 7 - 1 - write-only - - - TOUT_VAL - Interrupt Coalescing Timeout Value -Software uses this field to configure the maximum time allowed between the completion of a task on the bus and the generation of an interrupt. -Timer Operation: The timer is reset by software during the interrupt service routine. -It starts running when the first data transfer task with INT=0 is completed, after the timer was reset. -When the timer reaches the value configured in ICTOVAL field, it generates an interrupt and stops. -The timer's unit is equal to 1024 clock periods of the clock whose frequency is specified in the Internal Timer Clock Frequency field CQCAP register. -0x0: Timer is disabled. Timeout-based interrupt is not generated -0x1: Timeout on 01x1024 cycles of timer clock frequency -0x2: Timeout on 02x1024 cycles of timer clock frequency -........ -0x7f: Timeout on 127x1024 cycles of timer clock frequency -In order to write to this field, the TOUT_VAL_WEN bit must -be set at the same write operation. - 0 - 7 - read-write - - - - - CQTDLBA - No description available - 0x1a0 - 32 - 0x00000000 - 0xFFFFFFFF - - - TDLBA - This register stores the LSB bits (31:0) of the byte address of the head of the Task Descriptor List in system memory. -The size of the task descriptor list is 32 * (Task Descriptor size + Transfer Descriptor size) as configured by the host driver. -This address is set on 1 KB boundary. The lower 10 bits of this register are set to 0 by the software and are ignored by CQE - 0 - 32 - read-write - - - - - CQTDBR - No description available - 0x1a8 - 32 - 0x00000000 - 0xFFFFFFFF - - - DBR - The software configures TDLBA and TDLBAU, and enable -CQE in CQCFG before using this register. -Writing 1 to bit n of this register triggers CQE to start processing the task encoded in slot n of the TDL. -Writing 0 by the software does not have any impact on the hardware, and does not change the value of the register bit. -CQE always processes tasks according to the order submitted to the list by CQTDBR write transactions. -CQE processes Data Transfer tasks by reading the Task Descriptor and sending QUEUED_TASK_PARAMS (CMD44) and QUEUED_TASK_ADDRESS (CMD45) commands to -the device. CQE processes DCMD tasks (in slot #31, when enabled) by reading the Task Descriptor, and generating the command encoded by its index and argument. -The corresponding bit is cleared to 0 by CQE in one of the following events: -A task execution is completed (with success or error). -The task is cleared using CQTCLR register. -All tasks are cleared using CQCTL register. -CQE is disabled using CQCFG register. -Software may initiate multiple tasks at the same time (batch submission) by writing 1 to multiple bits of this register in the same transaction. -In the case of batch submission, CQE processes the tasks in order of the task index, starting with the lowest index. -If one or more tasks in the batch are marked with QBR, the ordering of execution is based on said processing order. - 0 - 32 - read-write - - - - - CQTCN - No description available - 0x1ac - 32 - 0x00000000 - 0xFFFFFFFF - - - TCN - Task Completion Notification -Each of the 32 bits are bit mapped to the 32 tasks. -Bit-N(1): Task-N has completed execution (with success or errors) -Bit-N(0): Task-N has not completed, could be pending or not submitted. -On task completion, software may read this register to know tasks that have completed. After reading this register, -software may clear the relevant bit fields by writing 1 to the corresponding bits. - 0 - 32 - read-write - - - - - CQDQS - No description available - 0x1b0 - 32 - 0x00000000 - 0xFFFFFFFF - - - DQS - Device Queue Status -Each of the 32 bits are bit mapped to the 32 tasks. -Bit-N(1): Device has marked task N as ready for execution -Bit-N(0): Task-N is not ready for execution. This task could be pending in device or not submitted. -Host controller updates this register with response of the Device Queue Status command. - 0 - 32 - read-write - - - - - CQDPT - No description available - 0x1b4 - 32 - 0x00000000 - 0xFFFFFFFF - - - DPT - Device-Pending Tasks -Each of the 32 bits are bit mapped to the 32 tasks. -Bit-N(1): Task-N has been successfully queued into the device and is awaiting execution -Bit-N(0): Task-N is not yet queued. -Bit n of this register is set if and only if QUEUED_TASK_PARAMS (CMD44) and QUEUED_TASK_ADDRESS (CMD45) were sent for this specific task and if this task has not been executed. -The controller sets this bit after receiving a successful response for CMD45. CQE clears this bit after the task has completed execution. -Software reads this register in the task-discard procedure to determine if the task is queued in the device - 0 - 32 - read-write - - - - - CQTCLR - No description available - 0x1b8 - 32 - 0x00000000 - 0xFFFFFFFF - - - TCLR - Writing 1 to bit n of this register orders CQE to clear a task that the software has previously issued. -This bit can only be written when CQE is in Halt state as indicated in CQCFG register Halt bit. -When software writes 1 to a bit in this register, CQE updates the value to 1, and starts clearing the data structures related to the task. -CQE clears the bit fields (sets a value of 0) in CQTCLR and in CQTDBR once the clear operation is complete. -Software must poll on the CQTCLR until it is leared to verify that a clear operation was done. - 0 - 32 - read-write - - - - - CQSSC1 - No description available - 0x1c0 - 32 - 0x00000000 - 0x000FFFFF - - - SQSCMD_BLK_CNT - This field indicates when SQS CMD is sent while data transfer is in progress. -A value of 'n' indicates that CQE sends status command on the CMD line, during the transfer of data block BLOCK_CNTn, on the data lines, where BLOCK_CNT is the number of blocks in the current transaction. -0x0: SEND_QUEUE_STATUS (CMD13) command is not sent during the transaction. Instead, it is sent only when the data lines are idle. -0x1: SEND_QUEUE_STATUS command is to be sent during the last block of the transaction. -0x2: SEND_QUEUE_STATUS command when last 2 blocks are pending. -0x3: SEND_QUEUE_STATUS command when last 3 blocks are pending. -........ -0xf: SEND_QUEUE_STATUS command when last 15 blocks are pending. -Should be programmed only when CQCFG.CQ_EN is 0 - 16 - 4 - read-write - - - SQSCMD_IDLE_TMR - This field configures the polling period to be used when using periodic SEND_QUEUE_STATUS (CMD13) polling. -Periodic polling is used when tasks are pending in the device, but no data transfer is in progress. -When a SEND_QUEUE_STATUS response indicates that no task is ready for execution, CQE counts the configured time until it issues the next SEND_QUEUE_STATUS. -Timer units are clock periods of the clock whose frequency is specified in the Internal Timer Clock Frequency field CQCAP register. -The minimum value is 0001h (1 clock period) and the maximum value is FFFFh (65535 clock periods). -For example, a CQCAP field value of 0 indicates a 19.2 MHz clock frequency (period = 52.08 ns). -If the setting in CQSSC1.CIT is 1000h, the calculated polling period is 4096*52.08 ns= 213.33 us. -Should be programmed only when CQCFG.CQ_EN is '0' - 0 - 16 - read-write - - - - - CQSSC2 - No description available - 0x1c4 - 32 - 0x00000000 - 0x0000FFFF - - - SQSCMD_RCA - This field provides CQE with the contents of the 16-bit RCA field in SEND_QUEUE_STATUS (CMD13) command argument. -CQE copies this field to bits 31:16 of the argument when transmitting SEND_ QUEUE_STATUS (CMD13) command. - 0 - 16 - read-write - - - - - CQCRDCT - No description available - 0x1c8 - 32 - 0x00000000 - 0xFFFFFFFF - - - DCMD_RESP - This register contains the response of the command generated by the last direct command (DCMD) task that was sent. -Contents of this register are valid only after bit 31 of CQTDBR register is cleared by the controller. - 0 - 32 - read-only - - - - - CQRMEM - No description available - 0x1d0 - 32 - 0x00000000 - 0xFFFFFFFF - - - RESP_ERR_MASK - The bits of this field are bit mapped to the device response. -This bit is used as an interrupt mask on the device status filed that is received in R1/R1b responses. -1: When a R1/R1b response is received, with a bit i in the device status set, a RED interrupt is generated. -0: When a R1/R1b response is received, bit i in the device status is ignored. -The reset value of this register is set to trigger an interrupt on all "Error" type bits in the device status. -Note: Responses to CMD13 (SQS) encode the QSR so that they are ignored by this logic. - 0 - 32 - read-write - - - - - CQTERRI - No description available - 0x1d4 - 32 - 0x00000000 - 0x1F3F9F3F - - - TRANS_ERR_TASKID - This field captures the ID of the task that was executed and whose data transfer has errors. - 24 - 5 - read-only - - - TRANS_ERR_CMD_INDX - This field captures the index of the command that was executed and whose data transfer has errors. - 16 - 6 - read-only - - - RESP_ERR_FIELDS_VALID - This bit is updated when an error is detected while a command transaction was in progress. -Values: -0x1 (SET): Response-related error is detected. Check contents of RESP_ERR_TASKID and RESP_ERR_CMD_INDX fields -0x0 (NOT_SET): Ignore contents of RESP_ERR_TASKID and RESP_ERR_CMD_INDX - 15 - 1 - read-only - - - RESP_ERR_TASKID - This field captures the ID of the task which was executed on the command line when the error occurred. - 8 - 5 - read-only - - - RESP_ERR_CMD_INDX - This field captures the index of the command that was executed on the command line when the error occurred - 0 - 6 - read-only - - - - - CQCRI - No description available - 0x1d8 - 32 - 0x00000000 - 0x0000003F - - - CMD_RESP_INDX - Last Command Response index -This field stores the index of the last received command response. Controller updates the value every time a command response is received - 0 - 6 - read-only - - - - - CQCRA - No description available - 0x1dc - 32 - 0x00000000 - 0xFFFFFFFF - - - CMD_RESP_ARG - Last Command Response argument -This field stores the argument of the last received command response. Controller updates the value every time a command response is received. - 0 - 32 - read-only - - - - - MSHC_VER_ID - No description available - 0x500 - 32 - 0x00000000 - 0xFFFFFFFF - - - VER_ID - No description available - 0 - 32 - read-only - - - - - MSHC_VER_TYPE - No description available - 0x504 - 32 - 0x00000000 - 0xFFFFFFFF - - - VER_TYPE - No description available - 0 - 32 - read-only - - - - - EMMC_BOOT_CTRL - No description available - 0x52c - 32 - 0x00000000 - 0xF181070F - - - BOOT_TOUT_CNT - Boot Ack Timeout Counter Value. -This value determines the interval by which boot ack timeout (50 ms) is detected when boot ack is expected during boot operation. -0xF : Reserved -0xE : TMCLK x 2^27 - ............ -0x1 : TMCLK x 2^14 -0x0 : TMCLK x 2^13 - 28 - 4 - read-write - - - BOOT_ACK_ENABLE - Boot Acknowledge Enable -When this bit set, SDXC checks for boot acknowledge start pattern of 0-1-0 during boot operation. This bit is applicable for both mandatory and alternate boot mode. -Values: -0x1 (TRUE): Boot Ack enable -0x0 (FALSE): Boot Ack disable - 24 - 1 - read-write - - - VALIDATE_BOOT - Validate Mandatory Boot Enable bit -This bit is used to validate the MAN_BOOT_EN bit. -Values: -0x1 (TRUE): Validate Mandatory boot enable bit -0x0 (FALSE): Ignore Mandatory boot Enable bit - 23 - 1 - write-only - - - MAN_BOOT_EN - Mandatory Boot Enable -This bit is used to initiate the mandatory boot operation. The application sets this bit along with VALIDATE_BOOT bit. -Writing 0 is ignored. The SDXC clears this bit after the boot transfer is completed or terminated. -Values: -0x1 (MAN_BOOT_EN): Mandatory boot enable -0x0 (MAN_BOOT_DIS): Mandatory boot disable - 16 - 1 - read-write - - - CQE_PREFETCH_DISABLE - Enable or Disable CQE's PREFETCH feature -This field allows Software to disable CQE's data prefetch feature when set to 1. -Values: -0x0 (PREFETCH_ENABLE): CQE can Prefetch data for sucessive WRITE transfers and pipeline sucessive READ transfers -0x1 (PREFETCH_DISABLE): Prefetch for WRITE and Pipeline for READ are disabled - 10 - 1 - read-write - - - CQE_ALGO_SEL - Scheduler algorithm selected for execution -This bit selects the Algorithm used for selecting one of the many ready tasks for execution. -Values: -0x0 (PRI_REORDER_PLUS_FCFS): Priority based reordering with FCFS to resolve equal priority tasks -0x1 (FCFS_ONLY): First come First serve, in the order of DBR rings - 9 - 1 - read-write - - - ENH_STROBE_ENABLE - Enhanced Strobe Enable -This bit instructs SDXC to sample the CMD line using data strobe for HS400 mode. -Values: -0x1 (ENH_STB_FOR_CMD): CMD line is sampled using data strobe for HS400 mode -0x0 (NO_STB_FOR_CMD): CMD line is sampled using cclk_rx for HS400 mode - 8 - 1 - read-write - - - EMMC_RST_N_OE - Output Enable control for EMMC Device Reset signal PAD -control. -This field drived sd_rst_n_oe output of SDXC -Values: -0x1 (ENABLE): sd_rst_n_oe is 1 -0x0 (DISABLE): sd_rst_n_oe is 0 - 3 - 1 - read-write - - - EMMC_RST_N - EMMC Device Reset signal control. -This register field controls the sd_rst_n output of SDXC -Values: -0x1 (RST_DEASSERT): Reset to eMMC device is deasserted -0x0 (RST_ASSERT): Reset to eMMC device asserted (active low) - 2 - 1 - read-write - - - DISABLE_DATA_CRC_CHK - Disable Data CRC Check -This bit controls masking of CRC16 error for Card Write in eMMC mode. -This is useful in bus testing (CMD19) for an eMMC device. In bus testing, an eMMC card does not send CRC status for a block, -which may generate CRC error. This CRC error can be masked using this bit during bus testing. -Values: -0x1 (DISABLE): DATA CRC check is disabled -0x0 (ENABLE): DATA CRC check is enabled - 1 - 1 - read-write - - - CARD_IS_EMMC - eMMC Card present -This bit indicates the type of card connected. An application program this bit based on the card connected to SDXC. -Values: -0x1 (EMMC_CARD): Card connected to SDXC is an eMMC card -0x0 (NON_EMMC_CARD): Card connected to SDXCis a non-eMMC card - 0 - 1 - read-write - - - - - AUTO_TUNING_CTRL - No description available - 0x540 - 32 - 0x00000000 - 0x7F1F0F1F - - - SWIN_TH_VAL - Sampling window threshold value setting -The maximum value that can be set here depends on the length of delayline used for tuning. A delayLine with 32 taps -can use values from 0x0 to 0x1F. -This field is valid only when SWIN_TH_EN is '1'. Should be programmed only when SAMPLE_CLK_SEL is '0' -0x0 : Threshold values is 0x1, windows of length 1 tap and above can be selected as sampling window. -0x1 : Threshold values is 0x2, windows of length 2 taps and above can be selected as sampling window. -0x2 : Threshold values is 0x1, windows of length 3 taps and above can be selected as sampling window. -........ -0x1F : Threshold values is 0x1, windows of length 32 taps and above can be selected as sampling window. - 24 - 7 - read-write - - - POST_CHANGE_DLY - Time taken for phase switching and stable clock output. -Specifies the maximum time (in terms of cclk cycles) that the delay line can take to switch its output phase after a change in tuning_cclk_sel or autotuning_cclk_sel. -Values: -0x0 (LATENCY_LT_1): Less than 1-cycle latency -0x1 (LATENCY_LT_2): Less than 2-cycle latency -0x2 (LATENCY_LT_3): Less than 3-cycle latency -0x3 (LATENCY_LT_4): Less than 4-cycle latency - 19 - 2 - read-write - - - PRE_CHANGE_DLY - Maximum Latency specification between cclk_tx and cclk_rx. -Values: -0x0 (LATENCY_LT_1): Less than 1-cycle latency -0x1 (LATENCY_LT_2): Less than 2-cycle latency -0x2 (LATENCY_LT_3): Less than 3-cycle latency -0x3 (LATENCY_LT_4): Less than 4-cycle latency - 17 - 2 - read-write - - - TUNE_CLK_STOP_EN - Clock stopping control for Tuning and auto-tuning circuit. -When enabled, clock gate control output of SDXC (clk2card_on) is pulled low before changing phase select codes on tuning_cclk_sel and autotuning_cclk_sel. -This effectively stops the Device/Card clock, cclk_rx and also drift_cclk_rx. Changing phase code when clocks are stopped ensures glitch free phase switching. - Set this bit to 0 if the PHY or delayline can guarantee glitch free switching. -Values: -0x1 (ENABLE_CLK_STOPPING): Clocks stopped during phase code change -0x0 (DISABLE_CLK_STOPPING): Clocks not stopped. PHY ensures glitch free phase switching - 16 - 1 - read-write - - - WIN_EDGE_SEL - This field sets the phase for Left and Right edges for drift monitoring. [Left edge offset + Right edge offset] must not be less than total taps of delayLine. -0x0: User selection disabled. Tuning calculated edges are used. -0x1: Right edge Phase is center + 2 stages, Left edge Phase is center - 2 stages. -0x2: Right edge Phase is center + 3 stages, Left edge Phase is center - 3 stagess -... -0xF: Right edge Phase is center + 16 stages, Left edge Phase is center - 16 stages. - 8 - 4 - read-write - - - SW_TUNE_EN - This fields enables software-managed tuning flow. -Values: -0x1 (SW_TUNING_ENABLE): Software-managed tuning enabled. AUTO_TUNING_STAT.CENTER_PH_CODE Field is now writable. -0x0 (SW_TUNING_DISABLE): Software-managed tuning disabled - 4 - 1 - read-write - - - RPT_TUNE_ERR - Framing errors are not generated when executing tuning. -This debug bit allows users to report these errors. -Values: -0x1 (DEBUG_ERRORS): Debug mode for reporting framing errors -0x0 (ERRORS_DISABLED): Default mode where as per SDXC no errors are reported. - 3 - 1 - read-write - - - SWIN_TH_EN - Sampling window Threshold enable -Selects the tuning mode -Field should be programmed only when SAMPLE_CLK_SEL is '0' -Values: -0x1 (THRESHOLD_MODE): Tuning engine selects the first complete sampling window that meets the threshold -set by SWIN_TH_VAL field -0x0 (LARGEST_WIN_MODE): Tuning engine sweeps all taps and settles at the largest window - 2 - 1 - read-write - - - CI_SEL - Selects the interval when the corrected center phase select code can be driven on tuning_cclk_sel output. -Values: -0x0 (WHEN_IN_BLK_GAP): Driven in block gap interval -0x1 (WHEN_IN_IDLE): Driven at the end of the transfer - 1 - 1 - read-write - - - AT_EN - Setting this bit enables Auto tuning engine. This bit is enabled by default when core is configured with mode3 retuning support. -Clear this bit to 0 when core is configured to have Mode3 re-tuning but SW wishes to disable mode3 retuning. -This field should be programmed only when SYS_CTRL.SD_CLK_EN is 0. -Values: -0x1 (AT_ENABLE): AutoTuning is enabled -0x0 (AT_DISABLE): AutoTuning is disabled - 0 - 1 - read-write - - - - - AUTO_TUNING_STAT - No description available - 0x544 - 32 - 0x00000000 - 0x00FFFFFF - - - L_EDGE_PH_CODE - Left Edge Phase code. Reading this field returns the phase code value used by Auto-tuning engine to sample data on Left edge of sampling window. - 16 - 8 - read-only - - - R_EDGE_PH_CODE - Right Edge Phase code. Reading this field returns the phase code value used by Auto-tuning engine to sample data on Right edge of sampling window. - 8 - 8 - read-only - - - CENTER_PH_CODE - Centered Phase code. Reading this field returns the current value on tuning_cclk_sel output. Setting AUTO_TUNING_CTRL.SW_TUNE_EN enables software to write to this field and its contents are reflected on tuning_cclk_sel - 0 - 8 - read-write - - - - - - - SDXC1 - SDXC1 - SDXC - 0xf2034000 - - - CONCTL - CONCTL - CONCTL - 0xf2040000 - - 0x0 - 0x18 - registers - - - - ctrl0 - No description available - 0x0 - 32 - 0x00000000 - 0xFF0FFFFF - - - ENET1_RXCLK_DLY_SEL - No description available - 15 - 5 - read-write - - - ENET1_TXCLK_DLY_SEL - No description available - 10 - 5 - read-write - - - ENET0_RXCLK_DLY_SEL - No description available - 5 - 5 - read-write - - - ENET0_TXCLK_DLY_SEL - No description available - 0 - 5 - read-write - - - - - ctrl2 - No description available - 0x8 - 32 - 0x00000000 - 0x2008F400 - - - ENET0_LPI_IRQ_EN - ENET0 LPI IRQ Enable - 29 - 1 - read-write - - - ENET0_REFCLK_OE - No description available - 19 - 1 - read-write - - - ENET0_PHY_INTF_SEL - 000:Reserved -001:RGMII -100:RMII -111:Reserved - 13 - 3 - read-write - - - ENET0_FLOWCTRL - No description available - 12 - 1 - read-write - - - ENET0_RMII_TXCLK_SEL - default to use internal clk. -set from pad， two option here: - internal 50MHz clock out to pad then in; - use external clock; - 10 - 1 - read-write - - - - - ctrl3 - No description available - 0xc - 32 - 0x00000000 - 0x2008F400 - - - ENET1_LPI_IRQ_EN - ENET1 LPI Interrupt Enable - 29 - 1 - read-write - - - ENET1_REFCLK_OE - No description available - 19 - 1 - read-write - - - ENET1_PHY_INTF_SEL - No description available - 13 - 3 - read-write - - - ENET1_FLOWCTRL - No description available - 12 - 1 - read-write - - - ENET1_RMII_TXCLK_SEL - No description available - 10 - 1 - read-write - - - - - ctrl4 - No description available - 0x10 - 32 - 0x00000000 - 0xDFFFF800 - - - SDXC0_SYS_IRQ_EN - system irq enable - 31 - 1 - read-write - - - SDXC0_WKP_IRQ_EN - wakeup irq enable - 30 - 1 - read-write - - - SDXC0_CARDCLK_INV_EN - card clock inverter enable - 28 - 1 - read-write - - - SDXC0_GPR_TUNING_CARD_CLK_SEL - for card clock DLL, default 0 - 23 - 5 - read-write - - - SDXC0_GPR_TUNING_STROBE_SEL - for strobe DLL, default 7taps(1ns) - 18 - 5 - read-write - - - SDXC0_GPR_STROBE_IN_ENABLE - enable strobe clock, maybe used when update strobe DLL - 17 - 1 - read-write - - - SDXC0_GPR_CCLK_RX_DLY_SW_SEL - No description available - 12 - 5 - read-write - - - SDXC0_GPR_CCLK_RX_DLY_SW_FORCE - force use sw DLL config - 11 - 1 - read-write - - - - - ctrl5 - No description available - 0x14 - 32 - 0x00000000 - 0xDFFFF800 - - - SDXC1_SYS_IRQ_EN - system irq enable - 31 - 1 - read-write - - - SDXC1_WKP_IRQ_EN - wakeup irq enable - 30 - 1 - read-write - - - SDXC1_CARDCLK_INV_EN - card clock inverter enable - 28 - 1 - read-write - - - SDXC1_GPR_TUNING_CARD_CLK_SEL - No description available - 23 - 5 - read-write - - - SDXC1_GPR_TUNING_STROBE_SEL - No description available - 18 - 5 - read-write - - - SDXC1_GPR_STROBE_IN_ENABLE - No description available - 17 - 1 - read-write - - - SDXC1_GPR_CCLK_RX_DLY_SW_SEL - No description available - 12 - 5 - read-write - - - SDXC1_GPR_CCLK_RX_DLY_SW_FORCE - No description available - 11 - 1 - read-write - - - - - - - I2C0 - I2C0 - I2C - 0xf3020000 - - 0x4 - 0x30 - registers - - - - Cfg - Configuration Register - 0x10 - 32 - 0x00000001 - 0xFFFFFFFF - - - FIFOSIZE - FIFO Size: -0: 2 bytes -1: 4 bytes -2: 8 bytes -3: 16 bytes - 0 - 2 - read-only - - - - - IntEn - Interrupt Enable Register - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - CMPL - Set to enable the Completion Interrupt. -Master: interrupts when a transaction is issued from this master and completed without losing the bus arbitration. -Slave: interrupts when a transaction addressing the controller is completed. - 9 - 1 - read-write - - - BYTERECV - Set to enable the Byte Receive Interrupt. -Interrupts when a byte of data is received -Auto-ACK will be disabled if this interrupt is enabled, that is, the software needs to ACK/NACK the received byte manually. - 8 - 1 - read-write - - - BYTETRANS - Set to enable the Byte Transmit Interrupt. -Interrupts when a byte of data is transmitted. - 7 - 1 - read-write - - - START - Set to enable the START Condition Interrupt. -Interrupts when a START condition/repeated START condition is detected. - 6 - 1 - read-write - - - STOP - Set to enable the STOP Condition Interrupt -Interrupts when a STOP condition is detected. - 5 - 1 - read-write - - - ARBLOSE - Set to enable the Arbitration Lose Interrupt. -Master: interrupts when the controller loses the bus arbitration -Slave: not available in this mode. - 4 - 1 - read-write - - - ADDRHIT - Set to enable the Address Hit Interrupt. -Master: interrupts when the addressed slave returned an ACK. -Slave: interrupts when the controller is addressed. - 3 - 1 - read-write - - - FIFOHALF - Set to enable the FIFO Half Interrupt. -Receiver: Interrupts when the FIFO is half-empty, i.e, there is >= 1/2 entries in the FIFO. -Transmitter: Interrupts when the FIFO is half-empty, i.e. there is <= 1/2 entries in the FIFO. -This interrupt depends on the transaction direction; don’t enable this interrupt unless the transfer direction is determined, otherwise unintended interrupts may be triggered. - 2 - 1 - read-write - - - FIFOFULL - Set to enable the FIFO Full Interrupt. -Interrupts when the FIFO is full. - 1 - 1 - read-write - - - FIFOEMPTY - Set to enabled the FIFO Empty Interrupt -Interrupts when the FIFO is empty. - 0 - 1 - read-write - - - - - Status - Status Register - 0x18 - 32 - 0x00000001 - 0xFFFFFFFF - - - LINESDA - Indicates the current status of the SDA line on the bus -1: high -0: low - 14 - 1 - read-only - - - LINESCL - Indicates the current status of the SCL line on the bus -1: high -0: low - 13 - 1 - read-only - - - GENCALL - Indicates that the address of the current transaction is a general call address: -1: General call -0: Not general call - 12 - 1 - read-only - - - BUSBUSY - Indicates that the bus is busy -The bus is busy when a START condition is on bus and it ends when a STOP condition is seen on bus -1: Busy -0: Not busy - 11 - 1 - read-only - - - ACK - Indicates the type of the last received/transmitted acknowledgement bit: -1: ACK -0: NACK - 10 - 1 - read-only - - - CMPL - Transaction Completion -Master: Indicates that a transaction has been issued from this master and completed without losing the bus arbitration -Slave: Indicates that a transaction addressing the controller has been completed. This status bit must be cleared to receive the next transaction; otherwise, the next incoming transaction will be blocked. - 9 - 1 - write-only - - - BYTERECV - Indicates that a byte of data has been received. - 8 - 1 - write-only - - - BYTETRANS - Indicates that a byte of data has been transmitted. - 7 - 1 - write-only - - - START - Indicates that a START Condition or a repeated START condition has been transmitted/received. - 6 - 1 - write-only - - - STOP - Indicates that a STOP Condition has been transmitted/received. - 5 - 1 - write-only - - - ARBLOSE - Indicates that the controller has lost the bus arbitration. - 4 - 1 - write-only - - - ADDRHIT - Master: indicates that a slave has responded to the transaction. -Slave: indicates that a transaction is targeting the controller (including the General Call). - 3 - 1 - write-only - - - FIFOHALF - Transmitter: Indicates that the FIFO is half-empty. - 2 - 1 - read-only - - - FIFOFULL - Indicates that the FIFO is full. - 1 - 1 - read-only - - - FIFOEMPTY - Indicates that the FIFO is empty. - 0 - 1 - read-only - - - - - Addr - Address Register - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR - The slave address. -For 7-bit addressing mode, the most significant 3 bits are ignored and only the least-significant 7 bits of Addr are valid - 0 - 10 - read-write - - - - - Data - Data Register - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - Write this register to put one byte of data to the FIFO. -Read this register to get one byte of data from the FIFO. - 0 - 8 - read-write - - - - - Ctrl - Control Register - 0x24 - 32 - 0x00001E00 - 0x000F9FFF - - - PHASE_START - Enable this bit to send a START condition at the beginning of transaction. -Master mode only. - 12 - 1 - read-write - - - PHASE_ADDR - Enable this bit to send the address after START condition. -Master mode only. - 11 - 1 - read-write - - - PHASE_DATA - Enable this bit to send the data after Address phase. -Master mode only. - 10 - 1 - read-write - - - PHASE_STOP - Enable this bit to send a STOP condition at the end of a transaction. -Master mode only. - 9 - 1 - read-write - - - DIR - Transaction direction -Master: Set this bit to determine the direction for the next transaction. -0: Transmitter -1: Receiver -Slave: The direction of the last received transaction. -0: Receiver -1: Transmitter - 8 - 1 - read-write - - - DATACNT - Data counts in bytes. -Master: The number of bytes to transmit/receive. 0 means max length. DataCnt will be decreased by one for each byte transmitted/received. -Slave: the meaning of DataCnt depends on the DMA mode: -If DMA is not enabled, DataCnt is the number of bytes transmitted/received from the bus master. It is reset to 0 when the controller is addressed and then increased by one for each byte of data transmitted/received. -If DMA is enabled, DataCnt is the number of bytes to transmit/receive. It will not be reset to 0 when the slave is addressed and it will be decreased by one for each byte of data transmitted/received. - 0 - 8 - read-write - - - - - Cmd - Command Register - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - CMD - Write this register with the following values to perform the corresponding actions: -0x0: no action -0x1: issue a data transaction (Master only) -0x2: respond with an ACK to the received byte -0x3: respond with a NACK to the received byte -0x4: clear the FIFO -0x5: reset the I2C controller (abort current transaction, set the SDA and SCL line to the open-drain mode, reset the Status Register and the Interrupt Enable Register, and empty the FIFO) -When issuing a data transaction by writing 0x1 to this register, the CMD field stays at 0x1 for the duration of the entire transaction, and it is only cleared to 0x0 after when the transaction has completed or when the controller loses the arbitration. -Note: No transaction will be issued by the controller when all phases (Start, Address, Data and Stop) are disabled. - 0 - 3 - read-write - - - - - Setup - Setup Register - 0x2c - 32 - 0x05252100 - 0xFFFFFFFF - - - T_SUDAT - T_SUDAT defines the data setup time before releasing the SCL. -Setup time = (2 * tpclk) + (2 + T_SP + T_SUDAT) * tpclk* (TPM+1) -tpclk = PCLK period -TPM = The multiplier value in Timing Parameter Multiplier Register - 24 - 5 - read-write - - - T_SP - T_SP defines the pulse width of spikes that must be suppressed by the input filter. -Pulse width = T_SP * tpclk* (TPM+1) - 21 - 3 - read-write - - - T_HDDAT - T_HDDAT defines the data hold time after SCL goes LOW -Hold time = (2 * tpclk) + (2 + T_SP + T_HDDAT) * tpclk* (TPM+1) - 16 - 5 - read-write - - - T_SCLRADIO - The LOW period of the generated SCL clock is defined by the combination of T_SCLRatio and T_SCLHi values. When T_SCLRatio = 0, the LOW period is equal to HIGH period. When T_SCLRatio = 1, the LOW period is roughly two times of HIGH period. -SCL LOW period = (2 * tpclk) + (2 + T_SP + T_SCLHi * ratio) * tpclk * (TPM+1) -1: ratio = 2 -0: ratio = 1 -This field is only valid when the controller is in the master mode. - 13 - 1 - read-write - - - T_SCLHI - The HIGH period of generated SCL clock is defined by T_SCLHi. -SCL HIGH period = (2 * tpclk) + (2 + T_SP + T_SCLHi) * tpclk* (TPM+1) -The T_SCLHi value must be greater than T_SP and T_HDDAT values. -This field is only valid when the controller is in the master mode. - 4 - 9 - read-write - - - DMAEN - Enable the direct memory access mode data transfer. -1: Enable -0: Disable - 3 - 1 - read-write - - - MASTER - Configure this device as a master or a slave. -1: Master mode -0: Slave mode - 2 - 1 - read-write - - - ADDRESSING - I2C addressing mode: -1: 10-bit addressing mode -0: 7-bit addressing mode - 1 - 1 - read-write - - - IICEN - Enable the I2C controller. -1: Enable -0: Disable - 0 - 1 - read-write - - - - - TPM - I2C Timing Paramater Multiplier - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - TPM - A multiplication value for I2C timing parameters. All the timing parameters in the Setup Register are multiplied by (TPM+1). - 0 - 5 - read-write - - - - - - - I2C1 - I2C1 - I2C - 0xf3024000 - - - I2C2 - I2C2 - I2C - 0xf3028000 - - - I2C3 - I2C3 - I2C - 0xf302c000 - - - SDP - SDP - SDP - 0xf304c000 - - 0x0 - 0x60 - registers - - - - SDPCR - SDP control register - 0x0 - 32 - 0x30000000 - 0xFFFE0001 - - - SFTRST - soft reset. -Write 1 then 0, to reset the SDP block. - 31 - 1 - read-write - - - CLKGAT - Clock Gate for the SDP main logic. -Write to 1 will clock gate for most logic of the SDP block, dynamic power saving when not use SDP block. - 30 - 1 - read-write - - - CIPDIS - Cipher Disable, read the info, whether the CIPHER features is besing disable in this chip or not. -1, Cipher is disabled in this chip. -0, Cipher is enabled in this chip. - 29 - 1 - read-only - - - HASDIS - HASH Disable, read the info, whether the HASH features is besing disable in this chip or not. -1, HASH is disabled in this chip. -0, HASH is enabled in this chip. - 28 - 1 - read-only - - - CIPHEN - Cipher Enablement, controlled by SW. -1, Cipher is Enabled. -0, Cipher is Disabled. - 23 - 1 - read-write - - - HASHEN - HASH Enablement, controlled by SW. -1, HASH is Enabled. -0, HASH is Disabled. - 22 - 1 - read-write - - - MCPEN - Memory Copy Enablement, controlled by SW. -1, Memory copy is Enabled. -0, Memory copy is Disabled. - 21 - 1 - read-write - - - CONFEN - Constant Fill to memory, controlled by SW. -1, Constant fill is Enabled. -0, Constant fill is Disabled. - 20 - 1 - read-write - - - DCRPDI - Decryption Disable bit, Write to 1 to disable the decryption. - 19 - 1 - read-write - - - TSTPKT0IRQ - Test purpose for interrupt when Packet counter reachs "0", but CHAIN=1 in the current packet. - 17 - 1 - read-write - - - INTEN - Interrupt Enablement, controlled by SW. -1, SDP interrupt is enabled. -0, SDP interrupt is disabled. - 0 - 1 - read-write - - - - - MODCTRL - Mod control register. - 0x4 - 32 - 0x00000000 - 0xFFFFF7FF - - - AESALG - AES algorithem selection. -0x0 = AES 128; -0x1 = AES 256; -0x8 = SM4； -Others, reserved. - 28 - 4 - read-write - - - AESMOD - AES mode selection. -0x0 = ECB; -0x1 = CBC; -Others, reserved. - 24 - 4 - read-write - - - AESKS - AES Key Selection. -These regisgers are being used to select the AES key that stored in the 16x128 key ram of the SDP, or select the key from the OTP. Detail as following: -0x00: key from the 16x128, this is the key read address, valid for AES128; AES256 will use 128 bit from this address and 128 bit key from next address as 256 bit AES key. -0x01: key from the 16x128, this is the key read address, valid for AES128, not valid for AES286. -.... -0x0E: key from the 16x128, this is the key read address, valid for AES128; AES256 will use 128 from this add and 128 from next add for the AES key. -0x0F: key from the 16x128, this is the key read address, valid for AES128, not valid for AES286. -0x20: kman_sk0[127:0] from the key manager for AES128; AES256 will use kman_sk0[255:0] as AES key. -0x21: kman_sk0[255:128] from the key manager for AES128; not valid for AES256. -0x22: kman_sk1[127:0] from the key manager for AES128; AES256 will use kman_sk1[255:0] as AES key. -0x23: kman_sk1[255:128] from the key manager for AES128; not valid for AES256. -0x24: kman_sk2[127:0] from the key manager for AES128; AES256 will use kman_sk2[255:0] as AES key. -0x25: kman_sk2[255:128] from the key manager for AES128; not valid for AES256. -0x26: kman_sk3[127:0] from the key manager for AES128; AES256 will use kman_sk3[255:0] as AES key. -0x27: kman_sk3[255:128] from the key manager for AES128; not valid for AES256. -0x30: exip0_key[127:0] from OTP for AES128; AES256 will use exip0_key[255:0] as AES key. -0x31: exip0_key[255:128] from OTP for AES128; not valid for AES256. -0x32: exip1_key[127:0] from OTP for AES128; AES256 will use exip1_key[255:0] as AES key. -0x33: exip1_key[255:128] from OTP for AES128; not valid for AES256. -Other values, reserved. - 18 - 6 - read-write - - - AESDIR - AES direction -1x1, AES Decryption -1x0, AES Encryption. - 16 - 1 - read-write - - - HASALG - HASH Algorithem selection. -0x0 SHA1 — -0x1 CRC32 — -0x2 SHA256 — - 12 - 4 - read-write - - - HASCHK - HASH Check Enable Bit. -1x1, HASH check need, hash result will compare with the HASHRSLT 0-7 registers; -1x0, HASH check is not enabled, HASHRSLT0-7 store the HASH result. -For SHA1, will use HASHRSLT0-3 words, and HASH 256 will use HASH0-7 words. - 10 - 1 - read-write - - - HASOUT - When hashing is enabled, this bit controls the input or output data of the AES engine is hashed. -0 INPUT HASH -1 OUTPUT HASH - 9 - 1 - read-write - - - DINSWP - Decide whether the SDP byteswaps the input data (big-endian data); -When all bits are set, the data is assumed to be in the big-endian format - 4 - 2 - read-write - - - DOUTSWP - Decide whether the SDP byteswaps the output data (big-endian data); When all bits are set, the data is assumed to be in the big-endian format - 2 - 2 - read-write - - - KEYSWP - Decide whether the SDP byteswaps the Key (big-endian data). -When all bits are set, the data is assumed to be in the big-endian format - 0 - 2 - read-write - - - - - PKTCNT - packet counter registers. - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - CNTVAL - This read-only field shows the current (instantaneous) value of the packet counter - 16 - 8 - read-only - - - CNTINCR - The value written to this field is added to the spacket count. - 0 - 8 - read-write - - - - - STA - Status Registers - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - TAG - packet tag. - 24 - 8 - read-only - - - IRQ - interrupt Request, requested when error happen, or when packet processing done, packet counter reach to zero. - 23 - 1 - write-only - - - CHN1PKT0 - the chain buffer "chain" bit is "1", while packet counter is "0", now, waiting for new buffer data. - 20 - 1 - write-only - - - AESBSY - AES Busy - 19 - 1 - read-only - - - HASBSY - Hashing Busy - 18 - 1 - read-only - - - PKTCNT0 - Packet Counter registers reachs to ZERO now. - 17 - 1 - write-only - - - PKTDON - Packet processing done, will trigger this itnerrrupt when the "PKTINT" bit set in the packet control word. - 16 - 1 - write-only - - - ERRSET - Working mode setup error. - 5 - 1 - write-only - - - ERRPKT - Packet head access error, or status update error. - 4 - 1 - write-only - - - ERRSRC - Source Buffer Access Error - 3 - 1 - write-only - - - ERRDST - Destination Buffer Error - 2 - 1 - write-only - - - ERRHAS - Hashing Check Error - 1 - 1 - write-only - - - ERRCHAIN - buffer chain error happen when packet's CHAIN bit=0, but the Packet counter is still not zero. - 0 - 1 - write-only - - - - - KEYADDR - Key Address - 0x10 - 32 - 0x00000040 - 0xFFFFFFFF - - - INDEX - To write a key to the SDP KEY RAM, the software must first write the desired key index/subword to this register. -Key index pointer. The valid indices are 0-[number_keys]. -In the SDP, there is a 16x128 key ram can store 16 AES128 keys or 8 AES 256 Keys; this index is for addressing the 16 128-bit key addresses. - 16 - 8 - read-write - - - SUBWRD - Key subword pointer. The valid indices are 0-3. After each write to the key data register, this field -increments; To write a key, the software must first write the desired key index/subword to this register. - 0 - 2 - read-write - - - - - KEYDAT - Key Data - 0x14 - 32 - 0x00000030 - 0xFFFFFFFF - - - KEYDAT - This register provides the write access to the key/key subword specified by the key index register. -Writing this location updates the selected subword for the key located at the index -specified by the key index register. The write also triggers the SUBWORD field of the -KEY register to increment to the next higher word in the key - 0 - 32 - read-write - - - - - 4 - 0x4 - CIPHIV0,CIPHIV1,CIPHIV2,CIPHIV3 - CIPHIV[%s] - no description available - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - CIPHIV - cipher initialization vector. - 0 - 32 - read-write - - - - - 8 - 0x4 - HASWRD0,HASWRD1,HASWRD2,HASWRD3,HASWRD4,HASWRD5,HASWRD6,HASWRD7 - HASWRD[%s] - no description available - 0x28 - 32 - 0x00000030 - 0xFFFFFFFF - - - HASWRD - Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. -If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. - 0 - 32 - read-write - - - - - CMDPTR - Command Pointer - 0x48 - 32 - 0x00000000 - 0xFFFFFFFF - - - CMDPTR - current command addresses the register points to the multiword -descriptor that is to be executed (or is currently being executed) - 0 - 32 - read-write - - - - - NPKTPTR - Next Packet Address Pointer - 0x4c - 32 - 0x00000000 - 0xFFFFFFFF - - - NPKTPTR - Next Packet Address Pointer - 0 - 32 - read-write - - - - - PKTCTL - Packet Control Registers - 0x50 - 32 - 0x00000000 - 0xFFFFFFFF - - - PKTTAG - packet tag - 24 - 8 - read-write - - - CIPHIV - Load Initial Vector for the AES in this packet. - 6 - 1 - read-write - - - HASFNL - Hash Termination packet - 5 - 1 - read-write - - - HASINI - Hash Initialization packat - 4 - 1 - read-write - - - CHAIN - whether the next command pointer register must be loaded into the channel's current descriptor -pointer. - 3 - 1 - read-write - - - DCRSEMA - whether the channel's semaphore must be decremented at the end of the current operation. -When the semaphore reaches a value of zero, no more operations are issued from the channel. - 2 - 1 - read-write - - - PKTINT - Reflects whether the channel must issue an interrupt upon the completion of the packet - 1 - 1 - read-write - - - - - PKTSRC - Packet Memory Source Address - 0x54 - 32 - 0x00000000 - 0xFFFFFFFF - - - PKTSRC - Packet Memory Source Address - 0 - 32 - read-write - - - - - PKTDST - Packet Memory Destination Address - 0x58 - 32 - 0x00000000 - 0xFFFFFFFF - - - PKTDST - Packet Memory Destination Address - 0 - 32 - read-write - - - - - PKTBUF - Packet buffer size. - 0x5c - 32 - 0x00000000 - 0xFFFFFFFF - - - PKTBUF - No description available - 0 - 32 - read-write - - - - - - - FEMC - FEMC - FEMC - 0xf3050000 - - 0x0 - 0x154 - registers - - - - CTRL - Control Register - 0x0 - 32 - 0x00000000 - 0x1FFF0007 - - - BTO - Bus timeout cycles -AXI Bus timeout cycle is as following (255*(2^BTO)): -00000b - 255*1 -00001-11110b - 255*2 - 255*2^30 -11111b - 255*2^31 - 24 - 5 - read-write - - - CTO - Command Execution timeout cycles -When Command Execution time exceed this timeout cycles, IPCMDERR or AXICMDERR interrupt is -generated. When CTO is set to zero, timeout cycle is 256*1024 cycle. otherwisee timeout cycle is -CTO*1024 cycle. - 16 - 8 - read-write - - - DQS - DQS (read strobe) mode -0b - Dummy read strobe loopbacked internally -1b - Dummy read strobe loopbacked from DQS pad - 2 - 1 - read-write - - - DIS - Module Disable -0b - Module enabled -1b - Module disabled - 1 - 1 - read-write - - - RST - Software Reset -Reset all internal logic in SEMC except configuration register - 0 - 1 - read-write - - - - - IOCTRL - IO Mux Control Register - 0x4 - 32 - 0x00000000 - 0x000000F0 - - - IO_CSX - IO_CSX output selection -0001b - SDRAM CS1 -0110b - SRAM CE# - 4 - 4 - read-write - - - - - BMW0 - Bus (AXI) Weight Control Register 0 - 0x8 - 32 - 0x00000000 - 0x00FFFFFF - - - RWS - Weight of slave hit with Read/Write Switch. This weight score is valid when queue command's slave is -same as current executing command with read/write operation switch. - 16 - 8 - read-write - - - SH - Weight of Slave Hit without read/write switch. This weight score is valid when queue command's slave is -same as current executing command without read/write operation switch. - 8 - 8 - read-write - - - AGE - Weight of AGE calculation. Each command in queue has an age signal to indicate its wait period. It is -multiplied by WAGE to get weight score. - 4 - 4 - read-write - - - QOS - Weight of QOS calculation. AXI bus access has AxQOS signal set, which is used as a priority indicator -for the associated write or read transaction. A higher value indicates a higher priority transaction. AxQOS -is multiplied by WQOS to get weight score. - 0 - 4 - read-write - - - - - BMW1 - Bus (AXI) Weight Control Register 1 - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - BR - Weight of Bank Rotation. This weight score is valid when queue command's bank is not same as current -executing command. - 24 - 8 - read-write - - - RWS - Weight of slave hit with Read/Write Switch. This weight score is valid when queue command's slave is -same as current executing command with read/write operation switch. - 16 - 8 - read-write - - - PH - Weight of Slave Hit without read/write switch. This weight score is valid when queue command's slave is -same as current executing command without read/write operation switch. - 8 - 8 - read-write - - - AGE - Weight of AGE calculation. Each command in queue has an age signal to indicate its wait period. It is -multiplied by WAGE to get weight score. - 4 - 4 - read-write - - - QOS - Weight of QOS calculation. AXI bus access has AxQOS signal set, which is used as a priority indicator -for the associated write or read transaction. A higher value indicates a higher priority transaction. AxQOS -is multiplied by WQOS to get weight score. - 0 - 4 - read-write - - - - - 7 - 0x4 - BASE0,BASE1,rsv2,rsv3,rsv4,rsv5,BASE6 - BR[%s] - no description available - 0x10 - 32 - 0x00000000 - 0xFFFFF03F - - - BASE - Base Address -This field determines high position 20 bits of SoC level Base Address. SoC level Base Address low -position 12 bits are all zero. - 12 - 20 - read-write - - - SIZE - Memory size -00000b - 4KB -00001b - 8KB -00010b - 16KB -00011b - 32KB -00100b - 64KB -00101b - 128KB -00110b - 256KB -00111b - 512KB -01000b - 1MB -01001b - 2MB -01010b - 4MB -01011b - 8MB -01100b - 16MB -01101b - 32MB -01110b - 64MB -01111b - 128MB -10000b - 256MB -10001b - 512MB -10010b - 1GB -10011b - 2GB -10100-11111b - 4GB - 1 - 5 - read-write - - - VLD - Valid - 0 - 1 - read-write - - - - - INTEN - Interrupt Enable Register - 0x38 - 32 - 0x00000000 - 0x0000000F - - - AXIBUSERR - AXI BUS error interrupt enable -0b - Interrupt is disabled -1b - Interrupt is enabled - 3 - 1 - read-write - - - AXICMDERR - AXI command error interrupt enable -0b - Interrupt is disabled -1b - Interrupt is enabled - 2 - 1 - read-write - - - IPCMDERR - IP command error interrupt enable -0b - Interrupt is disabled -1b - Interrupt is enabled - 1 - 1 - read-write - - - IPCMDDONE - IP command done interrupt enable -0b - Interrupt is disabled -1b - Interrupt is enabled - 0 - 1 - read-write - - - - - INTR - Interrupt Status Register - 0x3c - 32 - 0x00000000 - 0x0000000F - - - AXIBUSERR - AXI bus error interrupt -AXI Bus error interrupt is generated in following cases: -• AXI address is invalid -• AXI 8-bit or 16-bit WRAP write/read - 3 - 1 - write-only - - - AXICMDERR - AXI command error interrupt -AXI command error interrupt is generated when AXI command execution timeout. - 2 - 1 - write-only - - - IPCMDERR - IP command error done interrupt -IP command error interrupt is generated in following case: -• IP Command Address target invalid device space -• IP Command Code unsupported -• IP Command triggered when previous command - 1 - 1 - write-only - - - IPCMDDONE - IP command normal done interrupt - 0 - 1 - write-only - - - - - SDRCTRL0 - SDRAM Control Register 0 - 0x40 - 32 - 0x00000000 - 0x00004FFB - - - BANK2 - 2 Bank selection bit -0b - SDRAM device has 4 banks. -1b - SDRAM device has 2 banks. - 14 - 1 - read-write - - - CAS - CAS Latency -00b - 1 -01b - 1 -10b - 2 -11b - 3 - 10 - 2 - read-write - - - COL - Column address bit number -00b - 12 bit -01b - 11 bit -10b - 10 bit -11b - 9 bit - 8 - 2 - read-write - - - COL8 - Column 8 selection bit -0b - Column address bit number is decided by COL field. -1b - Column address bit number is 8. COL field is ignored. - 7 - 1 - read-write - - - BURSTLEN - Burst Length -000b - 1 -001b - 2 -010b - 4 -011b - 8 -100b - 8 -101b - 8 -110b - 8 -111b - 8 - 4 - 3 - read-write - - - HIGHBAND - high band select -0: use data[15:0] for 16bit SDRAM; -1: use data[31:16] for 16bit SDRAM; -only used when Port Size is 16bit(PORTSZ=01b) - 3 - 1 - read-write - - - PORTSZ - Port Size -00b - 8bit -01b - 16bit -10b - 32bit - 0 - 2 - read-write - - - - - SDRCTRL1 - SDRAM Control Register 1 - 0x44 - 32 - 0x00000000 - 0x00FFFFFF - - - ACT2PRE - ACT to Precharge minimum time -It is promised ACT2PRE+1 clock cycles delay between ACTIVE command to PRECHARGE/PRECHARGE_ALL command. - 20 - 4 - read-write - - - CKEOFF - CKE OFF minimum time -It is promised clock suspend last at leat CKEOFF+1 clock cycles. - 16 - 4 - read-write - - - WRC - Write recovery time -It is promised WRC+1 clock cycles delay between WRITE command to PRECHARGE/PRECHARGE_ALL command. This could help to meet tWR timing requirement by SDRAM device. - 13 - 3 - read-write - - - RFRC - Refresh recovery time -It is promised RFRC+1 clock cycles delay between REFRESH command to ACTIVE command. Thiscould help to meet tRFC timing requirement by SDRAM device. - 8 - 5 - read-write - - - ACT2RW - ACT to Read/Write wait time -It is promised ACT2RW+1 clock cycles delay between ACTIVE command to READ/WRITE command.This could help to meet tRCD timing requirement by SDRAM device. - 4 - 4 - read-write - - - PRE2ACT - PRECHARGE to ACT/Refresh wait time -It is promised PRE2ACT+1 clock cycles delay between PRECHARGE/PRECHARGE_ALL commandto ACTIVE/REFRESH command. This could help to meet tRP timing requirement by SDRAM device. - 0 - 4 - read-write - - - - - SDRCTRL2 - SDRAM Control Register 2 - 0x48 - 32 - 0x00000000 - 0xFFFFFFFF - - - ITO - SDRAM Idle timeout -It closes all opened pages if the SDRAM idle time lasts more than idle timeout period. SDRAM is -considered idle when there is no AXI Bus transfer and no SDRAM command pending. -00000000b - IDLE timeout period is 256*Prescale period. -00000001-11111111b - IDLE timeout period is ITO*Prescale period. - 24 - 8 - read-write - - - ACT2ACT - ACT to ACT wait time -It is promised ACT2ACT+1 clock cycles delay between ACTIVE command to ACTIVE command. This -could help to meet tRRD timing requirement by SDRAM device. - 16 - 8 - read-write - - - REF2REF - Refresh to Refresh wait time -It is promised REF2REF+1 clock cycles delay between REFRESH command to REFRESH command. -This could help to meet tRFC timing requirement by SDRAM device. - 8 - 8 - read-write - - - SRRC - Self Refresh Recovery time -It is promised SRRC+1 clock cycles delay between Self-REFRESH command to any command. - 0 - 8 - read-write - - - - - SDRCTRL3 - SDRAM Control Register 3 - 0x4c - 32 - 0x00000000 - 0xFFFFFF0F - - - UT - Refresh urgent threshold -Internal refresh request is generated on every Refresh period. Before internal request timer count up to -urgent request threshold, the refresh request is considered as normal refresh request. Normal refresh -request is handled in lower priority than any pending AXI command or IP command to SDRAM device. -When internal request timer count up to this urgent threshold, refresh request is considered as urgent -refresh request. Urgent refresh request is handled in higher priority than any pending AXI command or IP -command to SDRAM device. -NOTE: When urgent threshold is no less than refresh period, refresh request is always considered as -urgent refresh request. -Refresh urgent threshold is as follwoing: -00000000b - 256*Prescaler period -00000001-11111111b - UT*Prescaler period - 24 - 8 - read-write - - - RT - Refresh timer period -Refresh timer period is as following: -00000000b - 256*Prescaler period -00000001-11111111b - RT*Prescaler period - 16 - 8 - read-write - - - PRESCALE - Prescaler timer period -Prescaler timer period is as following: -00000000b - 256*16 clock cycles -00000001-11111111b - PRESCALE*16 clock cycles - 8 - 8 - read-write - - - REBL - Refresh burst length -It could send multiple Auto-Refresh command in one burst when REBL is set to non-zero. The -number of Auto-Refresh command cycle sent to all SDRAM device in one refresh period is as following. -000b - 1 -001b - 2 -010b - 3 -011b - 4 -100b - 5 -101b - 6 -110b - 7 -111b - 8 - 1 - 3 - read-write - - - REN - Refresh enable - 0 - 1 - read-write - - - - - SRCTRL0 - SRAM control register 0 - 0x70 - 32 - 0x00000000 - 0x00000F01 - - - ADVH - ADV hold state -0b - ADV is high during address hold state -1b - ADV is low during address hold state - 11 - 1 - read-write - - - ADVP - ADV polarity -0b - ADV is active low -1b - ADV is active high - 10 - 1 - read-write - - - ADM - address data mode -00b - address and data MUX mode -11b - address and data non-MUX mode - 8 - 2 - read-write - - - PORTSZ - port size -0b - 8bit -1b - 16bit - 0 - 1 - read-write - - - - - SRCTRL1 - SRAM control register 1 - 0x74 - 32 - 0x00000000 - 0xFFFFFFFF - - - OEH - OE high time, is OEH+1 clock cycles - 28 - 4 - read-write - - - OEL - OE low time, is OEL+1 clock cycles - 24 - 4 - read-write - - - WEH - WE high time, is WEH+1 clock cycles - 20 - 4 - read-write - - - WEL - WE low time, is WEL+1 clock cycles - 16 - 4 - read-write - - - AH - Address hold time, is AH+1 clock cycles - 12 - 4 - read-write - - - AS - Address setup time, is AS+1 clock cycles - 8 - 4 - read-write - - - CEH - Chip enable hold time, is CEH+1 clock cycles - 4 - 4 - read-write - - - CES - Chip enable setup time, is CES+1 clock cycles - 0 - 4 - read-write - - - - - SADDR - IP Command Control Register 0 - 0x90 - 32 - 0x00000000 - 0xFFFFFFFF - - - SA - Slave address - 0 - 32 - read-write - - - - - DATSZ - IP Command Control Register 1 - 0x94 - 32 - 0x00000000 - 0x00000007 - - - DATSZ - Data Size in Byte -When IP command is not a write/read operation, DATSZ field would be ignored. -000b - 4 -001b - 1 -010b - 2 -011b - 3 -100b - 4 -101b - 4 -110b - 4 -111b - 4 - 0 - 3 - read-write - - - - - BYTEMSK - IP Command Control Register 2 - 0x98 - 32 - 0x00000000 - 0x0000000F - - - BM3 - Byte Mask for Byte 3 (IPTXD bit 31:24) -0b - Byte Unmasked -1b - Byte Masked - 3 - 1 - read-write - - - BM2 - Byte Mask for Byte 2 (IPTXD bit 23:16) -0b - Byte Unmasked -1b - Byte Masked - 2 - 1 - read-write - - - BM1 - Byte Mask for Byte 1 (IPTXD bit 15:8) -0b - Byte Unmasked -1b - Byte Masked - 1 - 1 - read-write - - - BM0 - Byte Mask for Byte 0 (IPTXD bit 7:0) -0b - Byte Unmasked -1b - Byte Masked - 0 - 1 - read-write - - - - - IPCMD - IP Command Register - 0x9c - 32 - 0x00000000 - 0xFFFFFFFF - - - KEY - This field should be written with 0x5AA5 when trigging an IP command for all device types. The memory -device is selected by BRx settings and IPCR0 registers. - 16 - 16 - write-only - - - CMD - SDRAM Commands: -• 0x8: READ -• 0x9: WRITE -• 0xA: MODESET -• 0xB: ACTIVE -• 0xC: AUTO REFRESH -• 0xD: SELF REFRESH -• 0xE: PRECHARGE -• 0xF: PRECHARGE ALL -• Others: RSVD -NOTE: SELF REFRESH is sent to all SDRAM devices because they shared same CLK pin. - 0 - 16 - read-write - - - - - IPTX - TX DATA Register - 0xa0 - 32 - 0x00000000 - 0xFFFFFFFF - - - DAT - Data - 0 - 32 - read-write - - - - - IPRX - RX DATA Register - 0xb0 - 32 - 0x00000000 - 0xFFFFFFFF - - - DAT - Data - 0 - 32 - read-write - - - - - STAT0 - Status Register 0 - 0xc0 - 32 - 0x00000000 - 0x00000001 - - - IDLE - Indicating whether it is in IDLE state. -When IDLE=1, it is in IDLE state. There is no pending AXI command in internal queue and no -pending device access. - 0 - 1 - read-only - - - - - DLYCFG - Delay Line Config Register - 0x150 - 32 - 0x00000000 - 0x0000203F - - - OE - delay clock output enable, should be set after setting DLYEN and DLYSEL - 13 - 1 - read-write - - - DLYSEL - delay line select, 0 for 1 cell, 31 for all 32 cells - 1 - 5 - read-write - - - DLYEN - delay line enable - 0 - 1 - read-write - - - - - - - SYSCTL - SYSCTL - SYSCTL - 0xf4000000 - - 0x0 - 0x3000 - registers - - - - 350 - 0x4 - cpu0_core,cpu0_subsys,rsv2,rsv3,rsv4,rsv5,rsv6,rsv7,cpu1_core,cpx1_subsys,rsv10,rsv11,rsv12,rsv13,rsv14,rsv15,rsv16,rsv17,rsv18,rsv19,rsv20,pow_con,pow_vis,pow_cpu0,pow_cpu1,rst_soc,rst_con,rst_vis,rst_cpu0,rst_cpu1,rsv30,rsv31,clk_src_xtal,clk_src_pll0,clk_src_pll0clk0,clk_src_pll1,clk_src_pll1clk0,clk_src_pll1clk1,clk_src_pll2,clk_src_pll2clk0,clk_src_pll2clk1,clk_src_pll3,clk_src_pll3clk0,clk_src_pll4,clk_src_pll4clk0,rsv45,rsv46,rsv47,rsv48,rsv49,rsv50,rsv51,rsv52,rsv53,rsv54,rsv55,rsv56,rsv57,rsv58,rsv59,rsv60,rsv61,rsv62,rsv63,clk_top_cpu0,clk_top_mchtmr0,clk_top_cpu1,clk_top_mchtmr1,clk_top_axi,clk_top_conn,clk_top_vis,clk_top_ahb,clk_top_femc,clk_top_xpi0,clk_top_xpi1,clk_top_gptmr0,clk_top_gptmr1,clk_top_gptmr2,clk_top_gptmr3,clk_top_gptmr4,clk_top_gptmr5,clk_top_gptmr6,clk_top_gptmr7,clk_top_uart0,clk_top_uart1,clk_top_uart2,clk_top_uart3,clk_top_uart4,clk_top_uart5,clk_top_uart6,clk_top_uart7,clk_top_uart8,clk_top_uart9,clk_top_uart10,clk_top_uart11,clk_top_uart12,clk_top_uart13,clk_top_uart14,clk_top_uart15,clk_top_i2c0,clk_top_i2c1,clk_top_i2c2,clk_top_i2c3,clk_top_spi0,clk_top_spi1,clk_top_spi2,clk_top_spi3,clk_top_can0,clk_top_can1,clk_top_can2,clk_top_can3,clk_top_ptpc,clk_top_ana0,clk_top_ana1,clk_top_ana2,clk_top_aud0,clk_top_aud1,clk_top_aud2,clk_top_lcdc,clk_top_cam0,clk_top_cam1,clk_top_enet0,clk_top_enet1,clk_top_ptp0,clk_top_ptp1,clk_top_ref0,clk_top_ref1,clk_top_ntmr0,clk_top_ntmr1,clk_top_sdxc0,clk_top_sdxc1,rsv131,rsv132,rsv133,rsv134,rsv135,rsv136,rsv137,rsv138,rsv139,rsv140,rsv141,rsv142,rsv143,rsv144,rsv145,rsv146,rsv147,rsv148,rsv149,rsv150,rsv151,rsv152,rsv153,rsv154,rsv155,rsv156,rsv157,rsv158,rsv159,rsv160,rsv161,rsv162,rsv163,rsv164,rsv165,rsv166,rsv167,rsv168,rsv169,rsv170,rsv171,rsv172,rsv173,rsv174,rsv175,rsv176,rsv177,rsv178,rsv179,rsv180,rsv181,rsv182,rsv183,rsv184,rsv185,rsv186,rsv187,rsv188,rsv189,rsv190,rsv191,clk_top_adc0,clk_top_adc1,clk_top_adc2,clk_top_adc3,clk_top_i2s0,clk_top_i2s1,clk_top_i2s2,clk_top_i2s3,rsv200,rsv201,rsv202,rsv203,rsv204,rsv205,rsv206,rsv207,rsv208,rsv209,rsv210,rsv211,rsv212,rsv213,rsv214,rsv215,rsv216,rsv217,rsv218,rsv219,rsv220,rsv221,rsv222,rsv223,rsv224,rsv225,rsv226,rsv227,rsv228,rsv229,rsv230,rsv231,rsv232,rsv233,rsv234,rsv235,rsv236,rsv237,rsv238,rsv239,rsv240,rsv241,rsv242,rsv243,rsv244,rsv245,rsv246,rsv247,rsv248,rsv249,rsv250,rsv251,rsv252,rsv253,rsv254,rsv255,ahbapb_bus,axi_bus,conn_bus,vis_bus,femc,rom,lmm0,lmm1,mchtmr0,mchtmr1,axi_sram0,axi_sram1,xpi0,xpi1,sdp,rng,keym,hdma,xdma,gpio,mbx0,mbx1,wdg0,wdg1,wdg2,wdg3,gptmr0,gptmr1,gptmr2,gptmr3,gptmr4,gptmr5,gptmr6,gptmr7,uart0,uart1,uart2,uart3,uart4,uart5,uart6,uart7,uart8,uart9,uart10,uart11,uart12,uart13,uart14,uart15,i2c0,i2c1,i2c2,i2c3,spi0,spi1,spi2,spi3,can0,can1,can2,can3,ptpc,adc0,adc1,adc2,adc3,acmp,i2s0,i2s1,i2s2,i2s3,pdm,dao,synt,mot0,mot1,mot2,mot3,lcdc,cam0,cam1,jpeg,pdma,enet0,enet1,ntmr0,ntmr1,sdxc0,sdxc1,usb0,usb1,ref0,ref1 - RESOURCE[%s] - no description available - 0x0 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - 3 - 0x10 - 0,1,2 - GROUP0[%s] - no description available - 0x800 - - VALUE - Goup setting - 0x0 - 32 - 0x00000023 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral -0: peripheral is not needed -1: periphera is needed - 0 - 32 - read-write - - - - - SET - Goup setting - 0x4 - 32 - 0x00000023 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral -0: peripheral is not needed -1: periphera is needed - 0 - 32 - read-write - - - - - CLEAR - Goup setting - 0x8 - 32 - 0x00000023 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral -0: peripheral is not needed -1: periphera is needed - 0 - 32 - read-write - - - - - TOGGLE - Goup setting - 0xc - 32 - 0x00000023 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral -0: peripheral is not needed -1: periphera is needed - 0 - 32 - read-write - - - - - - 3 - 0x10 - 0,1,2 - GROUP1[%s] - no description available - 0x840 - - VALUE - Goup setting - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral -0: peripheral is not needed -1: periphera is needed - 0 - 32 - read-write - - - - - SET - Goup setting - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral -0: peripheral is not needed -1: periphera is needed - 0 - 32 - read-write - - - - - CLEAR - Goup setting - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral -0: peripheral is not needed -1: periphera is needed - 0 - 32 - read-write - - - - - TOGGLE - Goup setting - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral -0: peripheral is not needed -1: periphera is needed - 0 - 32 - read-write - - - - - - 2 - 0x10 - cpu0,cpu1 - AFFILIATE[%s] - no description available - 0x900 - - VALUE - Affiliate of Group - 0x0 - 32 - 0x00000001 - 0x0000000F - - - LINK - Affiliate groups of cpu0 -bit0: cpu0 depends on logic node0 -bit1: cpu0 depends on logic node1 -bit2: cpu0 depends on logic node2 -bit3: cpu0 depends on logic node3 - 0 - 4 - read-write - - - - - SET - Affiliate of Group - 0x4 - 32 - 0x00000001 - 0x0000000F - - - LINK - Affiliate groups of cpu0 -bit0: cpu0 depends on logic node0 -bit1: cpu0 depends on logic node1 -bit2: cpu0 depends on logic node2 -bit3: cpu0 depends on logic node3 - 0 - 4 - read-write - - - - - CLEAR - Affiliate of Group - 0x8 - 32 - 0x00000001 - 0x0000000F - - - LINK - Affiliate groups of cpu0 -bit0: cpu0 depends on logic node0 -bit1: cpu0 depends on logic node1 -bit2: cpu0 depends on logic node2 -bit3: cpu0 depends on logic node3 - 0 - 4 - read-write - - - - - TOGGLE - Affiliate of Group - 0xc - 32 - 0x00000001 - 0x0000000F - - - LINK - Affiliate groups of cpu0 -bit0: cpu0 depends on logic node0 -bit1: cpu0 depends on logic node1 -bit2: cpu0 depends on logic node2 -bit3: cpu0 depends on logic node3 - 0 - 4 - read-write - - - - - - 2 - 0x10 - cpu0,cpu1 - RETENTION[%s] - no description available - 0x920 - - VALUE - Retention Control - 0x0 - 32 - 0x0000000F - 0x0003FFFF - - - LINK - retention setting while system sleep, each bit represents a resource -bit0: soc_pow -bit1: soc_rst -bit2: cpu0_pow -bit3: cpu0_rst -bit4: cpu1_pow -bit5: cpu1_rst -bit6: con_pow -bit7: con_rst -bit8: vis_pow -bit9: vis_rst -bit10: xtal -bit11: pll0 -bit12: pll1 -bit13: pll2 -bit14: pll3 -bit15: pll4 - 0 - 18 - read-write - - - - - SET - Retention Control - 0x4 - 32 - 0x0000000F - 0x0003FFFF - - - LINK - retention setting while system sleep - 0 - 18 - read-write - - - - - CLEAR - Retention Control - 0x8 - 32 - 0x0000000F - 0x0003FFFF - - - LINK - retention setting while system sleep - 0 - 18 - read-write - - - - - TOGGLE - Retention Control - 0xc - 32 - 0x0000000F - 0x0003FFFF - - - LINK - retention setting while system sleep - 0 - 18 - read-write - - - - - - 4 - 0x10 - cpu0,cpu1,con,vis - POWER[%s] - no description available - 0x1000 - - status - Power Setting - 0x0 - 32 - 0x80000000 - 0xC0001100 - - - FLAG - flag represents power cycle happened from last clear of this bit -0: power domain did not edurance power cycle since last clear of this bit -1: power domain enduranced power cycle since last clear of this bit - 31 - 1 - read-write - - - FLAG_WAKE - flag represents wakeup power cycle happened from last clear of this bit -0: power domain did not edurance wakeup power cycle since last clear of this bit -1: power domain enduranced wakeup power cycle since last clear of this bit - 30 - 1 - read-write - - - LF_DISABLE - low fanout power switch disable -0: low fanout power switches are turned on -1: low fanout power switches are truned off - 12 - 1 - read-only - - - LF_ACK - low fanout power switch feedback -0: low fanout power switches are turned on -1: low fanout power switches are truned off - 8 - 1 - read-only - - - - - lf_wait - Power Setting - 0x4 - 32 - 0x00000255 - 0x000FFFFF - - - WAIT - wait time for low fan out power switch turn on, default value is 255 -0: 0 clock cycle -1: 1 clock cycles -. . . -clock cycles count on 24MHz - 0 - 20 - read-write - - - - - off_wait - Power Setting - 0xc - 32 - 0x00000015 - 0x000FFFFF - - - WAIT - wait time for power switch turn off, default value is 15 -0: 0 clock cycle -1: 1 clock cycles -. . . -clock cycles count on 24MHz - 0 - 20 - read-write - - - - - - 5 - 0x10 - soc,con,vis,cpu0,cpu1 - RESET[%s] - no description available - 0x1400 - - control - Reset Setting - 0x0 - 32 - 0x80000000 - 0xC0000011 - - - FLAG - flag represents reset happened from last clear of this bit -0: domain did not edurance reset cycle since last clear of this bit -1: domain enduranced reset cycle since last clear of this bit - 31 - 1 - read-write - - - FLAG_WAKE - flag represents wakeup reset happened from last clear of this bit -0: domain did not edurance wakeup reset cycle since last clear of this bit -1: domain enduranced wakeup reset cycle since last clear of this bit - 30 - 1 - read-write - - - HOLD - perform reset and hold in reset, until ths bit cleared by software -0: reset is released for function -1: reset is assert and hold - 4 - 1 - read-write - - - RESET - perform reset and release imediately -0: reset is released -1 reset is asserted and will release automatically - 0 - 1 - read-write - - - - - config - Reset Setting - 0x4 - 32 - 0x00643203 - 0x00FFFFFF - - - PRE_WAIT - wait cycle numbers before assert reset -0: wait 0 cycle -1: wait 1 cycles -. . . -Note, clock cycle is base on 24M - 16 - 8 - read-write - - - RSTCLK_NUM - reset clock number(must be even number) -0: 0 cycle -1: 0 cycles -2: 2 cycles -3: 2 cycles -. . . -Note, clock cycle is base on 24M - 8 - 8 - read-write - - - POST_WAIT - time guard band for reset release -0: wait 0 cycle -1: wait 1 cycles -. . . -Note, clock cycle is base on 24M - 0 - 8 - read-write - - - - - counter - Reset Setting - 0xc - 32 - 0x00000000 - 0x000FFFFF - - - COUNTER - self clear trigger counter, reset triggered when counter value is 1, write 0 will cancel reset -0: wait 0 cycle -1: wait 1 cycles -. . . -Note, clock cycle is base on 24M - 0 - 20 - read-write - - - - - - 67 - 0x4 - clk_top_cpu0,clk_top_mchtmr0,clk_top_cpu1,clk_top_mchtmr,clk_top_axi,clk_top_conn,clk_top_vis,clk_top_ahb,clk_top_femc,clk_top_xpi0,clk_top_xpi1,clk_top_gptmr0,clk_top_gptmr1,clk_top_gptmr2,clk_top_gptmr3,clk_top_gptmr4,clk_top_gptmr5,clk_top_gptmr6,clk_top_gptmr7,clk_top_uart0,clk_top_uart1,clk_top_uart2,clk_top_uart3,clk_top_uart4,clk_top_uart5,clk_top_uart6,clk_top_uart7,clk_top_uart8,clk_top_uart9,clk_top_uart10,clk_top_uart11,clk_top_uart12,clk_top_uart13,clk_top_uart14,clk_top_uart15,clk_top_i2c0,clk_top_i2c1,clk_top_i2c2,clk_top_i2c3,clk_top_spi0,clk_top_spi1,clk_top_spi2,clk_top_spi3,clk_top_can0,clk_top_can1,clk_top_can2,clk_top_can3,clk_top_ptpc,clk_top_ana0,clk_top_ana1,clk_top_ana2,clk_top_aud0,clk_top_aud1,clk_top_aud2,clk_top_lcdc,clk_top_cam0,clk_top_cam1,clk_top_enet0,clk_top_enet1,clk_top_ptp0,clk_top_ptp1,clk_top_ref0,clk_top_ref1,clk_top_ntmr0,clk_top_ntmr1,clk_top_sdxc0,clk_top_sdxc1 - CLOCK[%s] - no description available - 0x1800 - 32 - 0x00000000 - 0xC0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0:osc0_clk0 -1:pll0_clk0 -2:pll1_clk0 -3:pll1_clk1 -4:pll2_clk0 -5:pll2_clk1 -6:pll3_clk0 -7:pll4_clk0 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by1 -1: divider by 2 -2 divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - 4 - 0x4 - clk_top_adc0,clk_top_adc1,clk_top_adc2,clk_top_adc3 - ADCCLK[%s] - no description available - 0x1c00 - 32 - 0x00000000 - 0xC0000700 - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0: ahb clock -1: adc clock 0 -2: adc clock 1 -3: adc clock 2 - 8 - 3 - read-write - - - - - 4 - 0x4 - clk_top_i2s0,clk_top_i2s1,clk_top_i2s2,clk_top_i2s3 - I2SCLK[%s] - no description available - 0x1c10 - 32 - 0x00000000 - 0xC0000700 - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0: ahb clock -1: i2s clock 0 -2: i2s clock 1 -3: i2s clock 2 - 8 - 3 - read-write - - - - - global00 - Clock senario - 0x2000 - 32 - 0x00000000 - 0x0000000F - - - PRESET - global clock override request -bit0: override to preset0 -bit1: override to preset1 -bit2: override to preset2 -bit3: override to preset3 - 0 - 4 - read-write - - - - - 4 - 0x20 - slice0,slice1,slice2,slice3 - MONITOR[%s] - no description available - 0x2400 - - control - Clock measure and monitor control - 0x0 - 32 - 0x00000000 - 0x89FFD7FF - - - VALID - result is ready for read -0: not ready -1: result is ready - 31 - 1 - read-write - - - DIV_BUSY - divider is applying new setting - 27 - 1 - read-only - - - OUTEN - enable clock output - 24 - 1 - read-write - - - DIV - output divider - 16 - 8 - read-write - - - HIGH - clock frequency higher than upper limit - 15 - 1 - read-write - - - LOW - clock frequency lower than lower limit - 14 - 1 - read-write - - - START - start measurement - 12 - 1 - read-write - - - MODE - work mode, -0: register value will be compared to measurement -1: upper and lower value will be recordered in register - 10 - 1 - read-write - - - ACCURACY - measurement accuracy, -0: resolution is 1kHz -1: resolution is 1Hz - 9 - 1 - read-write - - - REFERENCE - reference clock selection, -0: 32k -1: 24M - 8 - 1 - read-write - - - SELECTION - clock measurement selection - 0 - 8 - read-write - - - - - current - Clock measure result - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - FREQUENCY - self updating measure result - 0 - 32 - read-only - - - - - low_limit - Clock lower limit - 0x8 - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - FREQUENCY - lower frequency - 0 - 32 - read-write - - - - - high_limit - Clock upper limit - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - FREQUENCY - upper frequency - 0 - 32 - read-write - - - - - - 2 - 0x400 - cpu0,cpu1 - CPU[%s] - no description available - 0x2800 - - LP - No description available - 0x0 - 32 - 0x00001200 - 0xFF013703 - - - WAKE_CNT - CPU0 wake up counter, counter saturated at 255, write 0x00 to clear - 24 - 8 - read-write - - - HALT - halt request for CPU0, -0: CPU0 will start to execute after reset or receive wakeup request -1: CPU0 will not start after reset, or wakeup after WFI - 16 - 1 - read-write - - - WAKE - CPU0 is waking up -0: CPU0 wake up not asserted -1: CPU0 wake up asserted - 13 - 1 - read-only - - - EXEC - CPU0 is executing -0: CPU0 is not executing -1: CPU0 is executing - 12 - 1 - read-only - - - WAKE_FLAG - CPU0 wakeup flag, indicate a wakeup event got active, write 1 to clear this bit -0: CPU0 wakeup not happened -1: CPU0 wakeup happened - 10 - 1 - read-write - - - SLEEP_FLAG - CPU0 sleep flag, indicate a sleep event got active, write 1 to clear this bit -0: CPU0 sleep not happened -1: CPU0 sleep happened - 9 - 1 - read-write - - - RESET_FLAG - CPU0 reset flag, indicate a reset event got active, write 1 to clear this bit -0: CPU0 sleep not happened -1: CPU0 sleep happened - 8 - 1 - read-write - - - MODE - Low power mode, system behavior after WFI -00: CPU clock stop after WFI -01: System enter low power mode after WFI -10: Keep running after WFI -11: reserved - 0 - 2 - read-write - - - - - LOCK - No description available - 0x4 - 32 - 0x00000002 - 0x0000FFFE - - - GPR - Lock bit for CPU_DATA0 to CPU_DATA13, once set, this bit will not clear untile next reset - 2 - 14 - read-write - - - LOCK - Lock bit for CPU_LOCK - 1 - 1 - read-write - - - - - 14 - 0x4 - GPR0,GPR1,GPR2,GPR3,GPR4,GPR5,GPR6,GPR7,GPR8,GPR9,GPR10,GPR11,GPR12,GPR13 - GPR[%s] - no description available - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - register for software to handle resume, can save resume address or status - 0 - 32 - read-write - - - - - 8 - 0x4 - STATUS0,STATUS1,STATUS2,STATUS3,STATUS4,STATUS5,STATUS6,STATUS7 - WAKEUP_STATUS[%s] - no description available - 0x40 - 32 - 0x00000000 - 0xFFFFFFFF - - - STATUS - IRQ values - 0 - 32 - read-only - - - - - 8 - 0x4 - ENABLE0,ENABLE1,ENABLE2,ENABLE3,ENABLE4,ENABLE5,ENABLE6,ENABLE7 - WAKEUP_ENABLE[%s] - no description available - 0x80 - 32 - 0x00000000 - 0xFFFFFFFF - - - ENABLE - IRQ wakeup enable - 0 - 32 - read-write - - - - - - - - IOC - IOC - IOC - 0xf4040000 - - 0x0 - 0xf60 - registers - - - - 492 - 0x8 - pa00,pa01,pa02,pa03,pa04,pa05,pa06,pa07,pa08,pa09,pa10,pa11,pa12,pa13,pa14,pa15,pa16,pa17,pa18,pa19,pa20,pa21,pa22,pa23,pa24,pa25,pa26,pa27,pa28,pa29,pa30,pa31,pb00,pb01,pb02,pb03,pb04,pb05,pb06,pb07,pb08,pb09,pb10,pb11,pb12,pb13,pb14,pb15,pb16,pb17,pb18,pb19,pb20,pb21,pb22,pb23,pb24,pb25,pb26,pb27,pb28,pb29,pb30,pb31,pc00,pc01,pc02,pc03,pc04,pc05,pc06,pc07,pc08,pc09,pc10,pc11,pc12,pc13,pc14,pc15,pc16,pc17,pc18,pc19,pc20,pc21,pc22,pc23,pc24,pc25,pc26,pc27,pc28,pc29,pc30,pc31,pd00,pd01,pd02,pd03,pd04,pd05,pd06,pd07,pd08,pd09,pd10,pd11,pd12,pd13,pd14,pd15,pd16,pd17,pd18,pd19,pd20,pd21,pd22,pd23,pd24,pd25,pd26,pd27,pd28,pd29,pd30,pd31,pe00,pe01,pe02,pe03,pe04,pe05,pe06,pe07,pe08,pe09,pe10,pe11,pe12,pe13,pe14,pe15,pe16,pe17,pe18,pe19,pe20,pe21,pe22,pe23,pe24,pe25,pe26,pe27,pe28,pe29,pe30,pe31,pf00,pf01,pf02,pf03,pf04,pf05,pf06,pf07,pf08,pf09,pf10,rsv171,rsv172,rsv173,rsv174,rsv175,rsv176,rsv177,rsv178,rsv179,rsv180,rsv181,rsv182,rsv183,rsv184,rsv185,rsv186,rsv187,rsv188,rsv189,rsv190,rsv191,rsv192,rsv193,rsv194,rsv195,rsv196,rsv197,rsv198,rsv199,rsv200,rsv201,rsv202,rsv203,rsv204,rsv205,rsv206,rsv207,rsv208,rsv209,rsv210,rsv211,rsv212,rsv213,rsv214,rsv215,rsv216,rsv217,rsv218,rsv219,rsv220,rsv221,rsv222,rsv223,rsv224,rsv225,rsv226,rsv227,rsv228,rsv229,rsv230,rsv231,rsv232,rsv233,rsv234,rsv235,rsv236,rsv237,rsv238,rsv239,rsv240,rsv241,rsv242,rsv243,rsv244,rsv245,rsv246,rsv247,rsv248,rsv249,rsv250,rsv251,rsv252,rsv253,rsv254,rsv255,rsv256,rsv257,rsv258,rsv259,rsv260,rsv261,rsv262,rsv263,rsv264,rsv265,rsv266,rsv267,rsv268,rsv269,rsv270,rsv271,rsv272,rsv273,rsv274,rsv275,rsv276,rsv277,rsv278,rsv279,rsv280,rsv281,rsv282,rsv283,rsv284,rsv285,rsv286,rsv287,rsv288,rsv289,rsv290,rsv291,rsv292,rsv293,rsv294,rsv295,rsv296,rsv297,rsv298,rsv299,rsv300,rsv301,rsv302,rsv303,rsv304,rsv305,rsv306,rsv307,rsv308,rsv309,rsv310,rsv311,rsv312,rsv313,rsv314,rsv315,rsv316,rsv317,rsv318,rsv319,rsv320,rsv321,rsv322,rsv323,rsv324,rsv325,rsv326,rsv327,rsv328,rsv329,rsv330,rsv331,rsv332,rsv333,rsv334,rsv335,rsv336,rsv337,rsv338,rsv339,rsv340,rsv341,rsv342,rsv343,rsv344,rsv345,rsv346,rsv347,rsv348,rsv349,rsv350,rsv351,rsv352,rsv353,rsv354,rsv355,rsv356,rsv357,rsv358,rsv359,rsv360,rsv361,rsv362,rsv363,rsv364,rsv365,rsv366,rsv367,rsv368,rsv369,rsv370,rsv371,rsv372,rsv373,rsv374,rsv375,rsv376,rsv377,rsv378,rsv379,rsv380,rsv381,rsv382,rsv383,rsv384,rsv385,rsv386,rsv387,rsv388,rsv389,rsv390,rsv391,rsv392,rsv393,rsv394,rsv395,rsv396,rsv397,rsv398,rsv399,rsv400,rsv401,rsv402,rsv403,rsv404,rsv405,rsv406,rsv407,rsv408,rsv409,rsv410,rsv411,rsv412,rsv413,rsv414,rsv415,px00,px01,px02,px03,px04,px05,px06,px07,px08,px09,px10,px11,rsv428,rsv429,rsv430,rsv431,rsv432,rsv433,rsv434,rsv435,rsv436,rsv437,rsv438,rsv439,rsv440,rsv441,rsv442,rsv443,rsv444,rsv445,rsv446,rsv447,py00,py01,py02,py03,py04,py05,py06,py07,py08,py09,py10,py11,rsv460,rsv461,rsv462,rsv463,rsv464,rsv465,rsv466,rsv467,rsv468,rsv469,rsv470,rsv471,rsv472,rsv473,rsv474,rsv475,rsv476,rsv477,rsv478,rsv479,pz00,pz01,pz02,pz03,pz04,pz05,pz06,pz07,pz08,pz09,pz10,pz11 - PAD[%s] - no description available - 0x0 - - FUNC_CTL - ALT SELECT - 0x0 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_CTL - PAD SETTINGS - 0x4 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only available in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - - - - PIOC - PIOC - IOC - 0xf40d8000 - - - BIOC - BIOC - IOC - 0xf5010000 - - - OTPSHW - OTPSHW - OTP - 0xf4080000 - - 0x0 - 0xc08 - registers - - - - 128 - 0x4 - SHADOW000,SHADOW001,SHADOW002,SHADOW003,SHADOW004,SHADOW005,SHADOW006,SHADOW007,SHADOW008,SHADOW009,SHADOW010,SHADOW011,SHADOW012,SHADOW013,SHADOW014,SHADOW015,SHADOW016,SHADOW017,SHADOW018,SHADOW019,SHADOW020,SHADOW021,SHADOW022,SHADOW023,SHADOW024,SHADOW025,SHADOW026,SHADOW027,SHADOW028,SHADOW029,SHADOW030,SHADOW031,SHADOW032,SHADOW033,SHADOW034,SHADOW035,SHADOW036,SHADOW037,SHADOW038,SHADOW039,SHADOW040,SHADOW041,SHADOW042,SHADOW043,SHADOW044,SHADOW045,SHADOW046,SHADOW047,SHADOW048,SHADOW049,SHADOW050,SHADOW051,SHADOW052,SHADOW053,SHADOW054,SHADOW055,SHADOW056,SHADOW057,SHADOW058,SHADOW059,SHADOW060,SHADOW061,SHADOW062,SHADOW063,SHADOW064,SHADOW065,SHADOW066,SHADOW067,SHADOW068,SHADOW069,SHADOW070,SHADOW071,SHADOW072,SHADOW073,SHADOW074,SHADOW075,SHADOW076,SHADOW077,SHADOW078,SHADOW079,SHADOW080,SHADOW081,SHADOW082,SHADOW083,SHADOW084,SHADOW085,SHADOW086,SHADOW087,SHADOW088,SHADOW089,SHADOW090,SHADOW091,SHADOW092,SHADOW093,SHADOW094,SHADOW095,SHADOW096,SHADOW097,SHADOW098,SHADOW099,SHADOW100,SHADOW101,SHADOW102,SHADOW103,SHADOW104,SHADOW105,SHADOW106,SHADOW107,SHADOW108,SHADOW109,SHADOW110,SHADOW111,SHADOW112,SHADOW113,SHADOW114,SHADOW115,SHADOW116,SHADOW117,SHADOW118,SHADOW119,SHADOW120,SHADOW121,SHADOW122,SHADOW123,SHADOW124,SHADOW125,SHADOW126,SHADOW127 - SHADOW[%s] - no description available - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - 8 - 0x4 - LOCK00,LOCK01,LOCK02,LOCK03,LOCK04,LOCK05,LOCK06,LOCK07 - SHADOW_LOCK[%s] - no description available - 0x200 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK - lock for pmic part shadow registers, 2 bits per 32 bit word, lock behavior is different between different fuse types -00: not locked -01: soft locked -10: not locked, and cannot lock in furture -11: double locked - 0 - 32 - read-write - - - - - 128 - 0x4 - FUSE000,FUSE001,FUSE002,FUSE003,FUSE004,FUSE005,FUSE006,FUSE007,FUSE008,FUSE009,FUSE010,FUSE011,FUSE012,FUSE013,FUSE014,FUSE015,FUSE016,FUSE017,FUSE018,FUSE019,FUSE020,FUSE021,FUSE022,FUSE023,FUSE024,FUSE025,FUSE026,FUSE027,FUSE028,FUSE029,FUSE030,FUSE031,FUSE032,FUSE033,FUSE034,FUSE035,FUSE036,FUSE037,FUSE038,FUSE039,FUSE040,FUSE041,FUSE042,FUSE043,FUSE044,FUSE045,FUSE046,FUSE047,FUSE048,FUSE049,FUSE050,FUSE051,FUSE052,FUSE053,FUSE054,FUSE055,FUSE056,FUSE057,FUSE058,FUSE059,FUSE060,FUSE061,FUSE062,FUSE063,FUSE064,FUSE065,FUSE066,FUSE067,FUSE068,FUSE069,FUSE070,FUSE071,FUSE072,FUSE073,FUSE074,FUSE075,FUSE076,FUSE077,FUSE078,FUSE079,FUSE080,FUSE081,FUSE082,FUSE083,FUSE084,FUSE085,FUSE086,FUSE087,FUSE088,FUSE089,FUSE090,FUSE091,FUSE092,FUSE093,FUSE094,FUSE095,FUSE096,FUSE097,FUSE098,FUSE099,FUSE100,FUSE101,FUSE102,FUSE103,FUSE104,FUSE105,FUSE106,FUSE107,FUSE108,FUSE109,FUSE110,FUSE111,FUSE112,FUSE113,FUSE114,FUSE115,FUSE116,FUSE117,FUSE118,FUSE119,FUSE120,FUSE121,FUSE122,FUSE123,FUSE124,FUSE125,FUSE126,FUSE127 - FUSE[%s] - no description available - 0x400 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - 8 - 0x4 - LOCK00,LOCK01,LOCK02,LOCK03,LOCK04,LOCK05,LOCK06,LOCK07 - FUSE_LOCK[%s] - no description available - 0x600 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK - lock for fuse array, 2 bits per 32 bit word, lock behavior is different between different fuse types -00: not locked -01: soft locked -10: not locked, and cannot lock in furture -11: double locked - 0 - 32 - read-write - - - - - UNLOCK - UNLOCK - 0x800 - 32 - 0x00000000 - 0xFFFFFFFF - - - UNLOCK - unlock word for fuse array operation -write "OPEN" to unlock fuse array, write any other value will lock write to fuse. -Please make sure 24M crystal is running and 2.5V LDO working properly - 0 - 32 - read-write - - - - - DATA - DATA - 0x804 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - data register for non-blocking access -this register hold dat read from fuse array or data to by programmed to fuse array - 0 - 32 - read-write - - - - - ADDR - ADDR - 0x808 - 32 - 0x00000000 - 0x0000007F - - - ADDR - word address to be read or write - 0 - 7 - read-write - - - - - CMD - CMD - 0x80c - 32 - 0x00000000 - 0xFFFFFFFF - - - CMD - command to access fure array -"BLOW" will update fuse word at ADDR to value hold in DATA -"READ" will fetch fuse value in at ADDR to DATA register - 0 - 32 - read-write - - - - - LOAD_REQ - LOAD Request - 0xa00 - 32 - 0x00000007 - 0x0000000F - - - REQUEST - reload request for 4 regions -bit0: region0 -bit1: region1 -bit2: region2 -bit3: region3 - 0 - 4 - read-write - - - - - LOAD_COMP - LOAD complete - 0xa04 - 32 - 0x00000007 - 0x0000000F - - - COMPLETE - reload complete sign for 4 regions -bit0: region 0 -bit1: region1 -bit2: region2 -bit3: region3 - 0 - 4 - read-write - - - - - 4 - 0x4 - LOAD_REGION0,LOAD_REGION1,LOAD_REGION2,LOAD_REGION3 - REGION[%s] - no description available - 0xa20 - 32 - 0x00000800 - 0x00007F7F - - - STOP - stop address of load region, fuse word at end address will NOT be reloaded -region0: fixed at 8 -region1: fixed at 16 -region2: fixed at 0, -region3: usrer configurable - 8 - 7 - read-write - - - START - start address of load region, fuse word at start address will be reloaded -region0: fixed at 0 -region1: fixed at 8 -region2: fixed at 16, -region3: usrer configurable - 0 - 7 - read-write - - - - - INT_FLAG - interrupt flag - 0xc00 - 32 - 0x00000000 - 0x00000007 - - - WRITE - fuse write flag, write 1 to clear -0: fuse is not written or writing -1: value in DATA register is programmed into fuse - 2 - 1 - read-write - - - READ - fuse read flag, write 1 to clear -0: fuse is not read or reading -1: fuse value is put in DATA register - 1 - 1 - read-write - - - LOAD - fuse load flag, write 1 to clear -0: fuse is not loaded or loading -1: fuse loaded - 0 - 1 - read-write - - - - - INT_EN - interrupt enable - 0xc04 - 32 - 0x00000000 - 0x00000007 - - - WRITE - fuse write interrupt enable -0: fuse write interrupt is not enable -1: fuse write interrupt is enable - 2 - 1 - read-write - - - READ - fuse read interrupt enable -0: fuse read interrupt is not enable -1: fuse read interrupt is enable - 1 - 1 - read-write - - - LOAD - fuse load interrupt enable -0: fuse load interrupt is not enable -1: fuse load interrupt is enable - 0 - 1 - read-write - - - - - - - OTP - OTP - OTP - 0xf40c8000 - - - PPOR - PPOR - PPOR - 0xf40c0000 - - 0x0 - 0x20 - registers - - - - RESET_FLAG - flag indicate reset source - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - FLAG - reset reason of last hard reset, write 1 to clear each bit -0: brownout -1: temperature(not available) -2: resetpin(not available) -4: debug reset -5: jtag reset -8: cpu0 lockup(not available) -9: cpu1 lockup(not available) -10: cpu0 request(not available) -11: cpu1 request(not available) -16: watch dog 0 -17: watch dog 1 -18: watch dog 2 -19: watch dog 3 -20: pmic watch dog -31: software - 0 - 32 - write-only - - - - - RESET_STATUS - reset source status - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - STATUS - current status of reset sources -0: brownout -1: temperature(not available) -2: resetpin(not available) -4: debug reset -5: jtag reset -8: cpu0 lockup(not available) -9: cpu1 lockup(not available) -10: cpu0 request(not available) -11: cpu1 request(not available) -16: watch dog 0 -17: watch dog 1 -18: watch dog 2 -19: watch dog 3 -20: pmic watch dog -31: software - 0 - 32 - read-write - - - - - RESET_HOLD - reset hold attribute - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - STATUS - hold arrtibute, when set, SOC keep in reset status until reset source release, or, reset will be released after SOC enter reset status -0: brownout -1: temperature(not available) -2: resetpin(not available) -4: debug reset -5: jtag reset -8: cpu0 lockup(not available) -9: cpu1 lockup(not available) -10: cpu0 request(not available) -11: cpu1 request(not available) -16: watch dog 0 -17: watch dog 1 -18: watch dog 2 -19: watch dog 3 -20: pmic watch dog -31: software - 0 - 32 - read-write - - - - - RESET_ENABLE - reset source enable - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - ENABLE - enable of reset sources -0: brownout -1: temperature(not available) -2: resetpin(not available) -4: debug reset -5: jtag reset -8: cpu0 lockup(not available) -9: cpu1 lockup(not available) -10: cpu0 request(not available) -11: cpu1 request(not available) -16: watch dog 0 -17: watch dog 1 -18: watch dog 2 -19: watch dog 3 -20: pmic watch dog -31: software - 0 - 32 - read-write - - - - - RESET_HOT - reset type triggered by reset - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - TYPE - reset type of reset sources, 0 for cold/warm reset, all system control setting cleared including clock, ioc; 1 for hot reset, system control, ioc setting kept, peripheral setting cleared. -0: brownout -1: temperature(not available) -2: resetpin(not available) -4: debug reset -5: jtag reset -8: cpu0 lockup(not available) -9: cpu1 lockup(not available) -10: cpu0 request(not available) -11: cpu1 request(not available) -16: watch dog 0 -17: watch dog 1 -18: watch dog 2 -19: watch dog 3 -20: pmic watch dog -31: software - 0 - 32 - read-write - - - - - RESET_COLD - reset type attribute - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - FLAG - perform cold or warm reset of chip, 0 for warm reset, fuse value and debug connection preserved; 1 for cold reset, fuse value reloaded and debug connection corrupted. This bit is ignored when hot reset selected -0: brownout -1: temperature(not available) -2: resetpin(not available) -4: debug reset -5: jtag reset -8: cpu0 lockup(not available) -9: cpu1 lockup(not available) -10: cpu0 request(not available) -11: cpu1 request(not available) -16: watch dog 0 -17: watch dog 1 -18: watch dog 2 -19: watch dog 3 -20: pmic watch dog -31: software - 0 - 32 - read-write - - - - - SOFTWARE_RESET - Software reset counter - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - COUNTER - counter decrease in 24MHz and stop at 0, trigger reset when value reach 2, software can write 0 to cancel reset - 0 - 32 - read-write - - - - - - - PCFG - PCFG - PCFG - 0xf40c4000 - - 0x0 - 0x70 - registers - - - - BANDGAP - BANGGAP control - 0x0 - 32 - 0x00101010 - 0x831F1F1F - - - VBG_TRIMMED - Bandgap trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value -0: bandgap is not trimmed -1: bandgap is trimmed - 31 - 1 - read-write - - - LOWPOWER_MODE - Banggap work in low power mode, banggap function limited -0: banggap works in normal mode -1: banggap works in low power mode - 25 - 1 - read-write - - - POWER_SAVE - Banggap work in power save mode, banggap function normally -0: banggap works in high performance mode -1: banggap works in power saving mode - 24 - 1 - read-write - - - VBG_1P0_TRIM - Banggap 1.0V output trim value - 16 - 5 - read-write - - - VBG_P65_TRIM - Banggap 1.0V output trim value - 8 - 5 - read-write - - - VBG_P50_TRIM - Banggap 1.0V output trim value - 0 - 5 - read-write - - - - - LDO1P1 - 1V LDO config - 0x4 - 32 - 0x0000044C - 0x00000FFF - - - VOLT - LDO output voltage in mV, value valid through 700-1320, , step 20mV. Hardware select voltage no less than target if not on valid steps, with maximum 1320mV. -700: 700mV -720: 720mV -. . . -1320:1320mV - 0 - 12 - read-write - - - - - LDO2P5 - 2.5V LDO config - 0x8 - 32 - 0x000009C4 - 0x10010FFF - - - READY - Ready flag, will set 1ms after enabled or voltage change -0: LDO is not ready for use -1: LDO is ready - 28 - 1 - read-only - - - ENABLE - LDO enable -0: turn off LDO -1: turn on LDO - 16 - 1 - read-write - - - VOLT - LDO output voltage in mV, value valid through 2125-2900, step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 2900mV. -2125: 2125mV -2150: 2150mV -. . . -2900:2900mV - 0 - 12 - read-write - - - - - DCDC_MODE - DCDC mode select - 0x10 - 32 - 0x00B010B0 - 0x10070FFF - - - READY - Ready flag -0: DCDC is applying new change -1: DCDC is ready - 28 - 1 - read-only - - - MODE - DCDC work mode -XX0: turn off -001: basic mode -011: generic mode -101: automatic mode -111: expert mode - 16 - 3 - read-write - - - VOLT - DCDC voltage in mV in normal mode, value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. -600: 600mV -625: 625mV -. . . -1375:1375mV - 0 - 12 - read-write - - - - - DCDC_LPMODE - DCDC low power mode - 0x14 - 32 - 0x00B010B0 - 0x00000FFF - - - STBY_VOLT - DCDC voltage in mV in standby mode, , value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. -600: 600mV -625: 625mV -. . . -1375:1375mV - 0 - 12 - read-write - - - - - DCDC_PROT - DCDC protection - 0x18 - 32 - 0x00000000 - 0x11818191 - - - ILIMIT_LP - over current setting for low power mode -0:250mA -1:200mA - 28 - 1 - read-write - - - OVERLOAD_LP - over current in low power mode -0: current is below setting -1: overcurrent happened in low power mode - 24 - 1 - read-only - - - DISABLE_POWER_LOSS - disable power loss protection -0: power loss protection enabled, DCDC shuts down when power loss -1: power loss protection disabled, DCDC try working after power voltage drop - 23 - 1 - read-write - - - POWER_LOSS_FLAG - power loss -0: input power is good -1: input power is too low - 16 - 1 - read-only - - - DISABLE_OVERVOLTAGE - output over voltage protection -0: protection enabled, DCDC will shut down is output voltage is unexpected high -1: protection disabled, DCDC continue to adjust output voltage - 15 - 1 - read-write - - - OVERVOLT_FLAG - output over voltage flag -0: output is normal -1: output is unexpected high - 8 - 1 - read-only - - - DISABLE_SHORT - disable output short circuit protection -0: short circuits protection enabled, DCDC shut down if short circuit on output detected -1: short circuit protection disabled - 7 - 1 - read-write - - - SHORT_CURRENT - short circuit current setting -0: 2.0A, -1: 1.3A - 4 - 1 - read-write - - - SHORT_FLAG - short circuit flag -0: current is within limit -1: short circuits detected - 0 - 1 - read-only - - - - - DCDC_CURRENT - DCDC current estimation - 0x1c - 32 - 0x00000000 - 0x0000811F - - - ESTI_EN - enable current measure - 15 - 1 - read-write - - - VALID - Current level valid -0: data is invalid -1: data is valid - 8 - 1 - read-only - - - LEVEL - DCDC current level, current level is num * 50mA - 0 - 5 - read-only - - - - - DCDC_ADVMODE - DCDC advance setting - 0x20 - 32 - 0x00EF1C6E - 0x073F006F - - - EN_RCSCALE - Enable RC scale - 24 - 3 - read-write - - - DC_C - Loop C number - 20 - 2 - read-write - - - DC_R - Loop R number - 16 - 4 - read-write - - - EN_FF_DET - enable feed forward detect -0: feed forward detect is disabled -1: feed forward detect is enabled - 6 - 1 - read-write - - - EN_FF_LOOP - enable feed forward loop -0: feed forward loop is disabled -1: feed forward loop is enabled - 5 - 1 - read-write - - - EN_DCM_EXIT - avoid over voltage -0: stay in DCM mode when voltage excess -1: change to CCM mode when voltage excess - 3 - 1 - read-write - - - EN_SKIP - enable skip on narrow pulse -0: do not skip narrow pulse -1: skip narrow pulse - 2 - 1 - read-write - - - EN_IDLE - enable skip when voltage is higher than threshold -0: do not skip -1: skip if voltage is excess - 1 - 1 - read-write - - - EN_DCM - DCM mode -0: CCM mode -1: DCM mode - 0 - 1 - read-write - - - - - DCDC_ADVPARAM - DCDC advance parameter - 0x24 - 32 - 0x00EF1C6E - 0x00007F7F - - - MIN_DUT - minimum duty cycle - 8 - 7 - read-write - - - MAX_DUT - maximum duty cycle - 0 - 7 - read-write - - - - - DCDC_MISC - DCDC misc parameter - 0x28 - 32 - 0x00070100 - 0x13170317 - - - EN_HYST - hysteres enable - 28 - 1 - read-write - - - HYST_SIGN - hysteres sign - 25 - 1 - read-write - - - HYST_THRS - hysteres threshold - 24 - 1 - read-write - - - RC_SCALE - Loop RC scale threshold - 20 - 1 - read-write - - - DC_FF - Loop feed forward number - 16 - 3 - read-write - - - OL_THRE - overload for threshold for lod power mode - 8 - 2 - read-write - - - OL_HYST - current hysteres range -0: 12.5mV -1: 25mV - 4 - 1 - read-write - - - DELAY - enable delay -0: delay disabled, -1: delay enabled - 2 - 1 - read-write - - - CLK_SEL - clock selection -0: select DCDC internal oscillator -1: select RC24M oscillator - 1 - 1 - read-write - - - EN_STEP - enable stepping in voltage change -0: stepping disabled, -1: steping enabled - 0 - 1 - read-write - - - - - DCDC_DEBUG - DCDC Debug - 0x2c - 32 - 0x00005DBF - 0x000FFFFF - - - UPDATE_TIME - DCDC voltage change time in 24M clock cycles, default value is 1mS - 0 - 20 - read-write - - - - - DCDC_START_TIME - DCDC ramp time - 0x30 - 32 - 0x0001193F - 0x000FFFFF - - - START_TIME - Start delay for DCDC to turn on, in 24M clock cycles, default value is 3mS - 0 - 20 - read-write - - - - - DCDC_RESUME_TIME - DCDC resume time - 0x34 - 32 - 0x00008C9F - 0x000FFFFF - - - RESUME_TIME - Resume delay for DCDC to recover from low power mode, in 24M clock cycles, default value is 1.5mS - 0 - 20 - read-write - - - - - POWER_TRAP - SOC power trap - 0x40 - 32 - 0x00000000 - 0x80010001 - - - TRIGGERED - Low power trap status, thit bit will set when power related low power flow triggered, write 1 to clear this flag. -0: low power trap is not triggered -1: low power trap triggered - 31 - 1 - read-write - - - RETENTION - DCDC enter standby mode, which will reduce voltage for memory content retention -0: Shutdown DCDC -1: reduce DCDC voltage - 16 - 1 - read-write - - - TRAP - Enable trap of SOC power supply, trap is used to hold SOC in low power mode for DCDC to enter further low power mode, this bit will self-clear when power related low pwer flow triggered -0: trap not enabled, pmic side low power function disabled -1: trap enabled, STOP operation leads to PMIC low power flow if SOC is not retentioned. - 0 - 1 - read-write - - - - - WAKE_CAUSE - Wake up source - 0x44 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAUSE - wake up cause, each bit represents one wake up source, write 1 to clear the register bit -0: wake up source is not active during last wakeup -1: wake up source is active furing last wakeup -bit 0: pmic_enable -bit 1: debug wakeup -bit 4: fuse interrupt -bit 7: UART interrupt -bit 8: TMR interrupt -bit 9: WDG interrupt -bit10: GPIO in PMIC interrupt -bit11: Security monitor interrupt -bit12: Security in PMIC event -bit16: Security violation in BATT -bit17: GPIO in BATT interrupt -bit18: BATT Button interrupt -bit19: RTC alarm interrupt - 0 - 32 - read-write - - - - - WAKE_MASK - Wake up mask - 0x48 - 32 - 0x00000000 - 0xFFFFFFFF - - - MASK - mask for wake up sources, each bit represents one wakeup source -0: allow source to wake up system -1: disallow source to wakeup system -bit 0: pmic_enable -bit 1: debug wakeup -bit 4: fuse interrupt -bit 7: UART interrupt -bit 8: TMR interrupt -bit 9: WDG interrupt -bit10: GPIO in PMIC interrupt -bit11: Security monitor interrupt -bit12: Security in PMIC event -bit16: Security violation in BATT -bit17: GPIO in BATT interrupt -bit18: BATT Button interrupt -bit19: RTC alarm interrupt - 0 - 32 - read-write - - - - - SCG_CTRL - Clock gate control in PMIC - 0x4c - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - SCG - control whether clock being gated during PMIC low power flow, 2 bits for each peripheral -00,01: reserved -10: clock is always off -11: clock is always on -bit0-1: fuse -bit2-3: sram -bit4-5: vad -bit6-7:gpio -bit8-9:ioc -bit10-11: timer -bit12-13:wdog -bit14-15:uart -bit16-17:debug - 0 - 32 - read-write - - - - - DEBUG_STOP - Debug stop config - 0x50 - 32 - 0x00000001 - 0x00000003 - - - CPU1 - Stop peripheral when CPU1 enter debug mode -0: peripheral keep running when CPU1 in debug mode -1: peripheral enter debug mode when CPU1 enter debug - 1 - 1 - read-write - - - CPU0 - Stop peripheral when CPU0 enter debug mode -0: peripheral keep running when CPU0 in debug mode -1: peripheral enter debug mode when CPU0 enter debug - 0 - 1 - read-write - - - - - RC24M - RC 24M config - 0x60 - 32 - 0x00000316 - 0x8000071F - - - RC_TRIMMED - RC24M trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value -0: RC is not trimmed -1: RC is trimmed - 31 - 1 - read-write - - - TRIM_C - Coarse trim for RC24M, bigger value means faster - 8 - 3 - read-write - - - TRIM_F - Fine trim for RC24M, bigger value means faster - 0 - 5 - read-write - - - - - RC24M_TRACK - RC 24M track mode - 0x64 - 32 - 0x00000000 - 0x00010011 - - - SEL24M - Select track reference -0: select 32K as reference -1: select 24M XTAL as reference - 16 - 1 - read-write - - - RETURN - Retrun default value when XTAL loss -0: remain last tracking value -1: switch to default value - 4 - 1 - read-write - - - TRACK - track mode -0: RC24M free running -1: track RC24M to external XTAL - 0 - 1 - read-write - - - - - TRACK_TARGET - RC 24M track target - 0x68 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRE_DIV - Divider for reference source - 16 - 16 - read-write - - - TARGET - Target frequency multiplier of divided source - 0 - 16 - read-write - - - - - STATUS - RC 24M track status - 0x6c - 32 - 0x00000000 - 0x0011871F - - - SEL32K - track is using XTAL32K -0: track is not using XTAL32K -1: track is using XTAL32K - 20 - 1 - read-only - - - SEL24M - track is using XTAL24M -0: track is not using XTAL24M -1: track is using XTAL24M - 16 - 1 - read-only - - - EN_TRIM - default value takes effect -0: default value is invalid -1: default value is valid - 15 - 1 - read-only - - - TRIM_C - default coarse trim value - 8 - 3 - read-only - - - TRIM_F - default fine trim value - 0 - 5 - read-only - - - - - - - PSEC - PSEC - PSEC - 0xf40cc000 - - 0x0 - 0x18 - registers - - - - SECURE_STATE - Secure state - 0x0 - 32 - 0x00000000 - 0x000300F0 - - - ALLOW_NSC - Non-secure state allow -0: system is not healthy to enter non-secure state, request to enter non-secure state will cause a fail state -1: system is healthy to enter non-secure state - 17 - 1 - read-only - - - ALLOW_SEC - Secure state allow -0: system is not healthy to enter secure state, request to enter non-secure state will cause a fail state -1: system is healthy to enter secure state - 16 - 1 - read-only - - - PMIC_FAIL - PMIC secure state one hot indicator -0: secure state is not in fail state -1: secure state is in fail state - 7 - 1 - read-write - - - PMIC_NSC - PMIC secure state one hot indicator -0: secure state is not in non-secure state -1: secure state is in non-secure state - 6 - 1 - read-write - - - PMIC_SEC - PMIC secure state one hot indicator -0: secure state is not in secure state -1: secure state is in secure state - 5 - 1 - read-write - - - PMIC_INS - PMIC secure state one hot indicator -0: secure state is not in inspect state -1: secure state is in inspect state - 4 - 1 - read-write - - - - - SECURE_STATE_CONFIG - secure state configuration - 0x4 - 32 - 0x00000000 - 0x00000009 - - - LOCK - Lock bit of allow restart setting, once locked, lock bit itself and configuration register will keep value until next reset -0: not locked, register can be modified -1: register locked, write access to the register is ignored - 3 - 1 - read-write - - - ALLOW_RESTART - allow secure state restart from fail state -0: restart is not allowed, only hardware reset can recover secure state -1: software is allowed to switch to inspect state from fail state - 0 - 1 - read-write - - - - - VIOLATION_CONFIG - Security violation config - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK_NSC - Lock bit non-secure violation setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified -1: register locked, write access to the configuration is ignored - 31 - 1 - read-write - - - NSC_VIO_CFG - configuration of non-secure state violations, each bit represents one security event -0: event is not a security violation -1: event is a security violation - 16 - 15 - read-write - - - LOCK_SEC - Lock bit secure violation setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified -1: register locked, write access to the configuration is ignored - 15 - 1 - read-write - - - SEC_VIO_CFG - configuration of secure state violations, each bit represents one security event -0: event is not a security violation -1: event is a security violation - 0 - 15 - read-write - - - - - ESCALATE_CONFIG - Escalate behavior on security event - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK_NSC - Lock bit non-secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified -1: register locked, write access to the configuration is ignored - 31 - 1 - read-write - - - NSC_VIO_CFG - configuration of non-secure state escalates, each bit represents one security event -0: event is not a security escalate -1: event is a security escalate - 16 - 15 - read-write - - - LOCK_SEC - Lock bit secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified -1: register locked, write access to the configuration is ignored - 15 - 1 - read-write - - - SEC_VIO_CFG - configuration of secure state escalates, each bit represents one security event -0: event is not a security escalate -1: event is a security escalate - 0 - 15 - read-write - - - - - EVENT - Event and escalate status - 0x10 - 32 - 0x00000000 - 0xFFFF000C - - - EVENT - local event statue, each bit represents one security event - 16 - 16 - read-only - - - PMIC_ESC_NSC - PMIC is escalating non-secure event - 3 - 1 - read-only - - - PMIC_ESC_SEC - PMIC is escalting secure event - 2 - 1 - read-only - - - - - LIFECYCLE - Lifecycle - 0x14 - 32 - 0x00000000 - 0x000000FF - - - LIFECYCLE - lifecycle status, -bit7: lifecycle_debate, -bit6: lifecycle_scribe, -bit5: lifecycle_no_ret, -bit4: lifecycle_return, -bit3: lifecycle_secure, -bit2: lifecycle_nonsec, -bit1: lifecycle_create, -bit0: lifecycle_unknow - 0 - 8 - read-only - - - - - - - PMON - PMON - PMON - 0xf40d0000 - - 0x0 - 0x48 - registers - - - - 4 - 0x8 - glitch0,glitch1,clock0,clock1 - MONITOR[%s] - no description available - 0x0 - - CONTROL - Glitch and clock monitor control - 0x0 - 32 - 0x00000000 - 0x00000011 - - - ACTIVE - select glitch works in active mode or passve mode. -0: passive mode, depends on power glitch destroy DFF value -1: active mode, check glitch by DFF chain - 4 - 1 - read-write - - - ENABLE - enable glitch detector -0: detector disabled -1: detector enabled - 0 - 1 - read-write - - - - - STATUS - Glitch and clock monitor status - 0x4 - 32 - 0x00000000 - 0x00000001 - - - FLAG - flag for glitch detected, write 1 to clear this flag -0: glitch not detected -1: glitch detected - 0 - 1 - read-write - - - - - - IRQ_FLAG - No description available - 0x40 - 32 - 0x00000000 - 0x0000000F - - - FLAG - interrupt flag, each bit represents for one monitor, write 1 to clear interrupt flag -0: no monitor interrupt -1: monitor interrupt happened - 0 - 4 - read-write - - - - - IRQ_ENABLE - No description available - 0x44 - 32 - 0x00000000 - 0x0000000F - - - ENABLE - interrupt enable, each bit represents for one monitor -0: monitor interrupt disabled -1: monitor interrupt enabled - 0 - 4 - read-write - - - - - - - PGPR - PGPR - PGPR - 0xf40d4000 - - 0x0 - 0x40 - registers - - - - PMIC_GPR00 - Generic control - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR01 - Generic control - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR02 - Generic control - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR03 - Generic control - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR04 - Generic control - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR05 - Generic control - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR06 - Generic control - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR07 - Generic control - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR08 - Generic control - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR09 - Generic control - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR10 - Generic control - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR11 - Generic control - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR12 - Generic control - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR13 - Generic control - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR14 - Generic control - 0x38 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR15 - Generic control - 0x3c - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - - - VAD - VAD - VAD - 0xf40ec000 - - 0x0 - 0xa4 - registers - - - - CTRL - Control Register - 0x0 - 32 - 0x00000000 - 0x0FF7FBFF - - - CAPT_DLY - Capture cycle delay>=0, should be less than PDM_CLK_HFDIV - 24 - 4 - read-write - - - PDM_CLK_HFDIV - The clock divider will work at least 4. -0: div-by-2, -1: div-by-4 -. . . -n: div-by-2*(n+1) - 20 - 4 - read-write - - - VAD_IE - VAD event interrupt enable - 18 - 1 - read-write - - - OFIFO_AV_IE - OFIFO data available interrupt enable - 17 - 1 - read-write - - - MEMBUF_EMPTY_IE - Buf empty interrupt enable - 16 - 1 - read-write - - - OFIFO_OVFL_ERR_IE - OFIFO overflow error interrupt enable - 15 - 1 - read-write - - - IIR_OVLD_ERR_IE - IIR overload error interrupt enable - 14 - 1 - read-write - - - IIR_OVFL_ERR_IE - IIR overflow error interrupt enable - 13 - 1 - read-write - - - CIC_OVLD_ERR_IE - CIC overload Interrupt Enable - 12 - 1 - read-write - - - CIC_SAT_ERR_IE - CIC saturation Interrupt Enable - 11 - 1 - read-write - - - MEMBUF_DISABLE - asserted to disable membuf - 9 - 1 - read-write - - - FIFO_THRSH - OFIFO threshold to generate ofifo_av (when fillings >= threshold) (fifo size: max 16 items, 16*32bits) - 5 - 4 - read-write - - - PDM_CLK_DIV_BYPASS - asserted to bypass the pdm clock divider - 4 - 1 - read-write - - - PDM_CLK_OE - pdm_clk_output_en - 3 - 1 - read-write - - - CH_POL - Asserted to select PDM_CLK high level captured, otherwise to select PDM_CLK low level captured. - 1 - 2 - read-write - - - CHNUM - the number of channels to be stored in buffer. Asserted to enable 2 channels. - 0 - 1 - read-write - - - - - FILTCTRL - Filter Control Register - 0x4 - 32 - 0x00000000 - 0x000007FF - - - DECRATIO - the decimation ratio of iir after CIC -1 -2: means dec-by-3 - 8 - 3 - read-write - - - IIR_SLOT_EN - IIR slot enable - 0 - 8 - read-write - - - - - DEC_CTRL0 - Decision Control Register 0 - 0x8 - 32 - 0x00000000 - 0xFFFF03FF - - - NOISE_TOL - the value of amplitude for noise determination when calculationg ZCR - 16 - 16 - read-write - - - BLK_CFG - asserted to have 3 sub-blocks, otherwise to have 2 sub-blocks - 9 - 1 - read-write - - - SUBBLK_LEN - length of sub-block - 0 - 9 - read-write - - - - - DEC_CTRL1 - Decision Control Register 1 - 0xc - 32 - 0x00000000 - 0x003FFFFF - - - ZCR_HIGH - ZCR high limit - 11 - 11 - read-write - - - ZCR_LOW - ZCR low limit - 0 - 11 - read-write - - - - - DEC_CTRL2 - Decision Control Register 2 - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - AMP_HIGH - amplitude high limit - 16 - 16 - read-write - - - AMP_LOW - amplitude low limit - 0 - 16 - read-write - - - - - ST - Status - 0x18 - 32 - 0x00000000 - 0x000000FF - - - VAD - VAD event found - 7 - 1 - write-only - - - OFIFO_AV - OFIFO data available - 6 - 1 - read-only - - - MEMBUF_EMPTY - Buf empty - 5 - 1 - write-only - - - OFIFO_OVFL - OFIFO overflow - 4 - 1 - write-only - - - IIR_OVLD - IIR overloading - 3 - 1 - write-only - - - IIR_OVFL - IIR oberflow - 2 - 1 - write-only - - - CIC_OVLD_ERR - CIC overload - 1 - 1 - write-only - - - CIC_SAT_ERR - CIC saturation - 0 - 1 - write-only - - - - - OFIFO - Out FIFO - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - D - The PCM data. -When there is only one channel, the samples are from Ch0, and the 2 samples in the 32-bits are: bit [31:16]: the samples earlier in time ([T-1]). Bit [15:0]: the samples later in time ([T]). -When there is two channels, the samples in the 32-bits are: bit [31:16]: the samples belong to Ch 1 (when ch_pol[1:0]==2, the data is captured at the positive part of the pdm clk). bit [15:0]: the samples belong to Ch 0 (when ch_pol[1:0]==2, the data is captured at the negtive part of the pdm clk). - 0 - 32 - read-write - - - - - RUN - Run Command Register - 0x20 - 32 - 0x00000000 - 0x00000003 - - - SFTRST - software reset. Self-clear - 1 - 1 - read-write - - - VAD_EN - module enable - 0 - 1 - read-write - - - - - OFIFO_CTRL - Out FIFO Control Register - 0x24 - 32 - 0x00000000 - 0x00000001 - - - EN - Asserted to enable OFIFO - 0 - 1 - read-write - - - - - CIC_CFG - CIC Configuration Register - 0x28 - 32 - 0x00000000 - 0x0000FC00 - - - POST_SCALE - the shift value after CIC results. - 10 - 6 - read-write - - - - - 1 - 0x4 - STE_ACT - COEF[%s] - no description available - 0xa0 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - The current detected short time energy - 0 - 32 - read-only - - - - - - - PLLCTL - PLLCTL - PLLCTL - 0xf4100000 - - 0x0 - 0x300 - registers - - - - XTAL - Crystal control and status - 0x0 - 32 - 0x00000000 - 0x300FFFFF - - - RESPONSE - Crystal oscillator status -0: Oscillator is not stable -1: Oscillator is stable for use - 29 - 1 - read-only - - - ENABLE - Crystal oscillator enable status -0: Oscillator is off -1: Oscillator is on - 28 - 1 - read-only - - - RAMP_TIME - Rampup time of XTAL oscillator in cycles of IRC24M clock -0: 0 cycle -1: 1 cycle -2: 2 cycle -1048575: 1048575 cycles - 0 - 20 - read-write - - - - - 5 - 0x80 - pll0,pll1,pll2,pll3,pll4 - PLL[%s] - no description available - 0x80 - - CFG0 - PLLx config0 - 0x0 - 32 - 0x00140460 - 0xBF77FFE8 - - - SS_RSTPTR - reset pointer, for sscg, lock when lock_en[31]&~pll_ana_pd&~pll_lock_comb - 31 - 1 - read-write - - - REFDIV - refclk diverder, lock when lock_en[24]&~pll_ana_pd - 24 - 6 - read-write - - - POSTDIV1 - lock when lock_en[20]&~pll_ana_pd - 20 - 3 - read-write - - - SS_SPREAD - lock when lock_en[14]&~pll_ana_pd - 14 - 5 - read-write - - - SS_DIVVAL - sscg divval, lock when lock_en[8]&~pll_ana_pd - 8 - 6 - read-write - - - SS_DOWNSPREAD - Downspread control -1’b0 –> Center-Spread -1’b1 –> Downspread - 7 - 1 - read-write - - - SS_RESET - No description available - 6 - 1 - read-write - - - SS_DISABLE_SSCG - No description available - 5 - 1 - read-write - - - DSMPD - 1: int mode; 0: frac mode - 3 - 1 - read-write - - - - - CFG1 - PLLx config1 - 0x4 - 32 - 0x80000000 - 0x86008000 - - - PLLCTRL_HW_EN - 1: hardware controll PLL settings, software can update register, but result unknown; suggested only update fbdiv and frac value -0: full software control PLL settings - 31 - 1 - read-write - - - CLKEN_SW - the clock enable used to gate pll output, should be set after lock, and clear before power down pll. -pll_clock_enable = pllctrl_hw_en ? (pll_lock_comb & enable & pll_clk_enable_chg) : clken_sw; - 26 - 1 - read-write - - - PLLPD_SW - pll power down. -pll_ana_pd = pllctrl_hw_en ? (pll_pd_soc|pll_pd_chg) : pllpd_sw; -pll_pd_soc is just delay of soc enable, for soc to control pll on/off; -pll_pd_chg is used to power down pll when div_chg_mode is 1, if software update pll parameter(fbdiv or frac), pll_ctrl will power down pll, update parameter, then power up pll. response to soc will not de-asserted at this sequence - 25 - 1 - read-write - - - LOCK_CNT_CFG - used to wait lock if set larger than lock time; -default 1500 24M cycle if refdiv is 1, 4500 cycle if refdiv is 3 - 15 - 1 - read-write - - - - - CFG2 - PLLx config2 - 0x8 - 32 - 0x00000000 - 0x00000FFF - - - FBDIV_INT - fbdiv used in int mode - 0 - 12 - read-write - - - - - FREQ - PLLx frac mode frequency adjust - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - FRAC - PLL output frequency is : -Fout = Fref/refdiv*(fbdiv + frac/2^24)/postdiv1 -for default refdiv=1 and postdiv1=1, 24MHz refclk -Fout is 24*fbdiv in int mode -if frac is set to 0x800000, Fout is 24*(fbdiv+0.5) -Fout is 24*fbdiv in int mode -if frac is set to 0x200000, Fout is 24*(fbdiv+0.125) - 8 - 24 - read-write - - - FBDIV_FRAC - fbdiv used in frac mode - 0 - 8 - read-write - - - - - LOCK - PLLx lock control - 0x10 - 32 - 0x00000000 - 0x81104100 - - - LOCK_SS_RSTPTR - lock bit of field ss_rstptr -0: field is open foe software to change -1: field is locked, not changeable - 31 - 1 - read-write - - - LOCK_REFDIV - lock bit of field refdiv -0: field is open foe software to change -1: field is locked, not changeable - 24 - 1 - read-write - - - LOCK_POSTDIV1 - lock bit of field postdiv1 -0: field is open foe software to change -1: field is locked, not changeable - 20 - 1 - read-write - - - LOCK_SS_SPEAD - lock bit of field ss_spead -0: field is open foe software to change -1: field is locked, not changeable - 14 - 1 - read-write - - - LOCK_SS_DIVVAL - lock bit of field ss_divval -0: field is open foe software to change -1: field is locked, not changeable - 8 - 1 - read-write - - - - - STATUS - PLLx status - 0x20 - 32 - 0x00000000 - 0x08000007 - - - ENABLE - enable from SYSCTL block - 27 - 1 - read-only - - - RESPONSE - response to SYSCTL, PLL is power down when both enable and response are 0. - 2 - 1 - read-only - - - PLL_LOCK_COMB - No description available - 1 - 1 - read-only - - - PLL_LOCK_SYNC - No description available - 0 - 1 - read-only - - - - - DIV0 - PLLx divider0 control - 0x40 - 32 - 0x00000000 - 0xB00000FF - - - BUSY - Busy flag -0: divider is working -1: divider is changing status - 31 - 1 - read-only - - - RESPONSE - Crystal oscillator status -0: Oscillator is not stable -1: Oscillator is stable for use - 29 - 1 - read-only - - - ENABLE - Crystal oscillator enable status -0: Oscillator is off -1: Oscillator is on - 28 - 1 - read-only - - - DIV - Divider -0: divide by 1 -1: divide by2 -. . . -255: divide by 256 - 0 - 8 - read-write - - - - - DIV1 - PLLx divider1 control - 0x44 - 32 - 0x00000000 - 0xB00000FF - - - BUSY - Busy flag -0: divider is working -1: divider is changing status - 31 - 1 - read-only - - - RESPONSE - Crystal oscillator status -0: Oscillator is not stable -1: Oscillator is stable for use - 29 - 1 - read-only - - - ENABLE - Crystal oscillator enable status -0: Oscillator is off -1: Oscillator is on - 28 - 1 - read-only - - - DIV - Divider -0: divide by 1 -1: divide by2 -. . . -255: divide by 256 - 0 - 8 - read-write - - - - - - - - BPOR - BPOR - BPOR - 0xf5004000 - - 0x0 - 0x10 - registers - - - - POR_CAUSE - Power on cause - 0x0 - 32 - 0x00000000 - 0x0000001F - - - CAUSE - Power on cause, each bit represnts one cause, write 1 to clear each bit -bit0: wakeup button -bit1: security violation -bit2: RTC alarm 0 -bit3: RTC alarm 1 -bit4: GPIO - 0 - 5 - read-write - - - - - POR_SELECT - Power on select - 0x4 - 32 - 0x00000000 - 0x0000001F - - - SELECT - Power on cause select, each bit represnts one cause, value 1 enables corresponding cause -bit0: wakeup button -bit1: security violation -bit2: RTC alarm 0 -bit3: RTC alarm 1 -bit4: GPIO - 0 - 5 - read-write - - - - - POR_CONFIG - Power on reset config - 0x8 - 32 - 0x00000000 - 0x00000001 - - - RETENTION - retention battery domain setting -0: battery reset on reset pin reset happen -1: battery domain retention when reset pin reset happen - 0 - 1 - read-write - - - - - POR_CONTROL - Power down control - 0xc - 32 - 0x00000000 - 0x0000FFFF - - - COUNTER - Chip power down counter, counter decreasing if value is not 0, power down of chip happens on counter value is 1 - 0 - 16 - read-write - - - - - - - BCFG - BCFG - BCFG - 0xf5008000 - - 0x0 - 0x14 - registers - - - - VBG_CFG - Bandgap config - 0x0 - 32 - 0x00000000 - 0x831F1F1F - - - VBG_TRIMMED - Bandgap trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value -0: bandgap is not trimmed -1: bandgap is trimmed - 31 - 1 - read-write - - - LP_MODE - Bandgap works in low power mode -0: not in low power mode -1: bandgap work in low power mode - 25 - 1 - read-write - - - POWER_SAVE - Bandgap works in power save mode -0: not in power save mode -1: bandgap work in power save mode - 24 - 1 - read-write - - - VBG_1P0 - Bandgap 1.0V output trim - 16 - 5 - read-write - - - VBG_P65 - Bandgap 0.65V output trim - 8 - 5 - read-write - - - VBG_P50 - Bandgap 0.50V output trim - 0 - 5 - read-write - - - - - LDO_CFG - LDO config - 0x4 - 32 - 0x00010000 - 0x03370FFF - - - RES_TRIM - Resistor trim - 24 - 2 - read-write - - - CP_TRIM - Capacitor trim - 20 - 2 - read-write - - - EN_SL - enable selfload, this bit helps improve LDO performance when current less than 200nA -0: self load disabled -1: selfload enabled - 18 - 1 - read-write - - - DIS_PD - disable pull down resistor, enable pull down may lead to more power but better response -0: pulldown resistor enabled -1: pulldown resistor disabled - 17 - 1 - read-write - - - ENABLE - LDO enable -0: LDO is disabled -1: LDO is enabled - 16 - 1 - read-write - - - VOLT - LDO voltage setting in mV, valid range through 600mV to 1100mV, step 20mV. Hardware select voltage no less than target if not on valid steps, with maximum 1100mV. -600: 600mV -620: 620mV -. . . -1100:1100mV - 0 - 12 - read-write - - - - - IRC32K_CFG - On-chip 32k oscillator config - 0x8 - 32 - 0x00000000 - 0x80C001FF - - - IRC_TRIMMED - IRC32K trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value -0: irc is not trimmed -1: irc is trimmed - 31 - 1 - read-write - - - CAPEX7_TRIM - IRC32K bit 7 - 23 - 1 - read-write - - - CAPEX6_TRIM - IRC32K bit 6 - 22 - 1 - read-write - - - CAP_TRIM - capacitor trim bits - 0 - 9 - read-write - - - - - XTAL32K_CFG - XTAL 32K config - 0xc - 32 - 0x00000000 - 0x00001313 - - - HYST_EN - crystal 32k hysteres enable - 12 - 1 - read-write - - - GMSEL - crystal 32k gm selection - 8 - 2 - read-write - - - CFG - crystal 32k config - 4 - 1 - read-write - - - AMP - crystal 32k amplifier - 0 - 2 - read-write - - - - - CLK_CFG - Clock config - 0x10 - 32 - 0x00000000 - 0x10010010 - - - XTAL_SEL - crystal selected - 28 - 1 - read-only - - - KEEP_IRC - force irc32k run - 16 - 1 - read-write - - - FORCE_XTAL - force switch to crystal - 4 - 1 - read-write - - - - - - - BUTN - BUTN - BUTN - 0xf500c000 - - 0x0 - 0xc - registers - - - - BTN_STATUS - Button status - 0x0 - 32 - 0x00000000 - 0x77770FFF - - - XWCLICK - wake button click status when power button held, write 1 to clear flag -bit0: clicked -bit1: double clicked -bit2: tripple clicked - 28 - 3 - read-write - - - WCLICK - wake button click status, write 1 to clear flag -bit0: clicked -bit1: double clicked -bit2: tripple clicked - 24 - 3 - read-write - - - XPCLICK - power button click status when wake button held, write 1 to clear flag -bit0: clicked -bit1: double clicked -bit2: tripple clicked - 20 - 3 - read-write - - - PCLICK - power button click status, write 1 to clear flag -bit0: clicked -bit1: double clicked -bit2: tripple clicked - 16 - 3 - read-write - - - DBTN - Dual button press status, write 1 to clear flag -bit0: button pressed -bit1: button confirmd -bit2: button long pressed -bit3: button long long pressed - 8 - 4 - read-write - - - WBTN - Wake button press status, write 1 to clear flag -bit0: button pressed -bit1: button confirmd -bit2: button long pressed -bit3: button long long pressed - 4 - 4 - read-write - - - PBTN - Power button press status, write 1 to clear flag -bit0: button pressed -bit1: button confirmd -bit2: button long pressed -bit3: button long long pressed - 0 - 4 - read-write - - - - - BTN_IRQ_MASK - Button interrupt mask - 0x4 - 32 - 0x00000000 - 0x77770FFF - - - XWCLICK - wake button click status when power button held interrupt enable -bit0: clicked -bit1: double clicked -bit2: tripple clicked - 28 - 3 - read-write - - - WCLICK - wake button click interrupt enable -bit0: clicked -bit1: double clicked -bit2: tripple clicked - 24 - 3 - read-write - - - XPCLICK - power button click status when wake button held interrupt enable -bit0: clicked -bit1: double clicked -bit2: tripple clicked - 20 - 3 - read-write - - - PCLICK - power button click interrupt enable -bit0: clicked -bit1: double clicked -bit2: tripple clicked - 16 - 3 - read-write - - - DBTN - Dual button press interrupt enable -bit0: button pressed -bit1: button confirmd -bit2: button long pressed -bit3: button long long pressed - 8 - 4 - read-write - - - WBTN - Wake button press interrupt enable -bit0: button pressed -bit1: button confirmd -bit2: button long pressed -bit3: button long long pressed - 4 - 4 - read-write - - - PBTN - Power button press interrupt enable -bit0: button pressed -bit1: button confirmd -bit2: button long pressed -bit3: button long long pressed - 0 - 4 - read-write - - - - - LED_INTENSE - Debounce setting - 0x8 - 32 - 0x00000000 - 0x000F000F - - - RLED - Rbutton brightness 0 - 16 - 4 - read-write - - - PLED - Pbutton brightness 0 - 0 - 4 - read-write - - - - - - - BGPR - BGPR - BGPR - 0xf5018000 - - 0x0 - 0x20 - registers - - - - 8 - 0x4 - 0,1,2,3,4,5,6,7 - GPR[%s] - no description available - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - Generic control - 0 - 32 - read-write - - - - - - - RTCSHW - RTCSHW - RTC - 0xf501c000 - - 0x0 - 0x28 - registers - - - - SECOND - Second counter - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SECOND - second counter - 0 - 32 - read-write - - - - - SUBSEC - Sub-second counter - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - SUBSEC - sub second counter - 0 - 32 - read-only - - - - - SEC_SNAP - Second counter snap shot - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - SEC_SNAP - second snap shot, write to take snap shot - 0 - 32 - read-write - - - - - SUB_SNAP - Sub-second counter snap shot - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - SUB_SNAP - sub second snap shot, write to take snap shot - 0 - 32 - read-write - - - - - ALARM0 - RTC alarm0 - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - ALARM - Alarm time for second counter, on each alarm match, alarm increase ALARM0_INC - 0 - 32 - read-write - - - - - ALARM0_INC - Alarm0 incremental - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - INCREASE - adder when ARLAM0 happen, helps to create periodical alarm - 0 - 32 - read-write - - - - - ALARM1 - RTC alarm1 - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - ALARM - Alarm time for second counter, on each alarm match, alarm increase ALARM0_INC - 0 - 32 - read-write - - - - - ALARM1_INC - Alarm1 incremental - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - INCREASE - adder when ARLAM0 happen, helps to create periodical alarm - 0 - 32 - read-write - - - - - ALARM_FLAG - RTC alarm flag - 0x20 - 32 - 0x00000000 - 0x00000003 - - - ALARM1 - alarm1 happen - 1 - 1 - read-write - - - ALARM0 - alarm0 happen - 0 - 1 - read-write - - - - - ALARM_EN - RTC alarm enable - 0x24 - 32 - 0x00000000 - 0x00000003 - - - ENABLE1 - alarm1 mask -0: alarm1 disabled -1: alarm1 enabled - 1 - 1 - read-write - - - ENABLE0 - alarm0 mask -0: alarm0 disabled -1: alarm0 enabled - 0 - 1 - read-write - - - - - - - RTC - RTC - RTC - 0xf5044000 - - - BSEC - BSEC - BSEC - 0xf5040000 - - 0x0 - 0x14 - registers - - - - SECURE_STATE - Secure state - 0x0 - 32 - 0x00000000 - 0x0003000F - - - ALLOW_NSC - Non-secure state allow -0: system is not healthy to enter non-secure state, request to enter non-secure state will cause a fail state -1: system is healthy to enter non-secure state - 17 - 1 - read-only - - - ALLOW_SEC - Secure state allow -0: system is not healthy to enter secure state, request to enter non-secure state will cause a fail state -1: system is healthy to enter secure state - 16 - 1 - read-only - - - BATT_FAIL - BATT secure state one hot indicator -0: secure state is not in fail state -1: secure state is in fail state - 3 - 1 - read-write - - - BATT_NSC - BATT secure state one hot indicator -0: secure state is not in non-secure state -1: secure state is in non-secure state - 2 - 1 - read-write - - - BATT_SEC - BATT secure state one hot indicator -0: secure state is not in secure state -1: secure state is in secure state - 1 - 1 - read-write - - - BATT_INS - BATT secure state one hot indicator -0: secure state is not in inspect state -1: secure state is in inspect state - 0 - 1 - read-write - - - - - SECURE_STATE_CONFIG - secure state configuration - 0x4 - 32 - 0x00000000 - 0x00000009 - - - LOCK - Lock bit of allow restart setting, once locked, lock bit itself and configuration register will keep value until next reset -0: not locked, register can be modified -1: register locked, write access to the register is ignored - 3 - 1 - read-write - - - ALLOW_RESTART - allow secure state restart from fail state -0: restart is not allowed, only hardware reset can recover secure state -1: software is allowed to switch to inspect state from fail state - 0 - 1 - read-write - - - - - VIOLATION_CONFIG - Security violation config - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK_NSC - Lock bit non-secure violation setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified -1: register locked, write access to the configuration is ignored - 31 - 1 - read-write - - - NSC_VIO_CFG - configuration of non-secure state violations, each bit represents one security event -0: event is not a security violation -1: event is a security violation - 16 - 15 - read-write - - - LOCK_SEC - Lock bit secure violation setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified -1: register locked, write access to the configuration is ignored - 15 - 1 - read-write - - - SEC_VIO_CFG - configuration of secure state violations, each bit represents one security event -0: event is not a security violation -1: event is a security violation - 0 - 15 - read-write - - - - - ESCALATE_CONFIG - Escalate behavior on security event - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK_NSC - Lock bit non-secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified -1: register locked, write access to the configuration is ignored - 31 - 1 - read-write - - - NSC_VIO_CFG - configuration of non-secure state escalates, each bit represents one security event -0: event is not a security escalate -1: event is a security escalate - 16 - 15 - read-write - - - LOCK_SEC - Lock bit secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified1: register locked, write access to the configuration is ignored - 15 - 1 - read-write - - - SEC_VIO_CFG - configuration of secure state escalates, each bit represents one security event -0: event is not a security escalate -1: event is a security escalate - 0 - 15 - read-write - - - - - EVENT - Event and escalate status - 0x10 - 32 - 0x00000000 - 0xFFFF0003 - - - EVENT - local event statue, each bit represents one security event - 16 - 16 - read-only - - - BATT_ESC_NSC - BATT is escalating non-secure event - 1 - 1 - read-only - - - BATT_ESC_SEC - BATT is escalting ssecure event - 0 - 1 - read-only - - - - - - - BKEY - BKEY - BKEY - 0xf5048000 - - 0x0 - 0x4c - registers - - - - 2 - 0x20 - 0,1 - KEY[%s] - no description available - 0x0 - - 8 - 0x4 - 0,1,2,3,4,5,6,7 - DATA[%s] - no description available - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - security key data - 0 - 32 - read-write - - - - - - 2 - 0x4 - KEY0,KEY1 - ECC[%s] - no description available - 0x40 - 32 - 0x00000000 - 0xC000FFFF - - - WLOCK - write lock to key0 -0: write enable -1: write ignored - 31 - 1 - read-write - - - RLOCK - read lock to key0 -0: key read enable -1: key always read as 0 - 30 - 1 - read-write - - - ECC - Parity check bits for key0 - 0 - 16 - read-write - - - - - SELECT - Key selection - 0x48 - 32 - 0x00000000 - 0x00000001 - - - SELECT - select key, key0 treated as secure key, in non-scure mode, only key1 can be selected -0: select key0 in secure mode, key1 in non-secure mode -1: select key1 in secure or nonsecure mode - 0 - 1 - read-write - - - - - - - BMON - BMON - BMON - 0xf504c000 - - 0x0 - 0x20 - registers - - - - 2 - 0x10 - glitch0,clock0 - MONITOR[%s] - no description available - 0x0 - - CONTROL - Glitch and clock monitor control - 0x0 - 32 - 0x00000000 - 0x00000011 - - - ACTIVE - select glitch works in active mode or passve mode. -0: passive mode, depends on power glitch destroy DFF value -1: active mode, check glitch by DFF chain - 4 - 1 - read-write - - - ENABLE - enable glitch detector -0: detector disabled -1: detector enabled - 0 - 1 - read-write - - - - - STATUS - Glitch and clock monitor status - 0x4 - 32 - 0x00000000 - 0x00000001 - - - FLAG - flag for glitch detected, write 1 to clear this flag -0: glitch not detected -1: glitch detected - 0 - 1 - read-write - - - - - - - - TAMP - TAMP - TAMP - 0xf5050000 - - 0x0 - 0x88 - registers - - - - 6 - 0x10 - tamp0,tamp1,tamp2,tamp3,tamp4,tamp5 - TAMP[%s] - no description available - 0x0 - - CONTROL - Tamper n control - 0x0 - 32 - 0x00000000 - 0x801F03F7 - - - LOCK - lock tamper setting -0: tamper setting can be changed -1: tamper setting will last to next battery domain power cycle - 31 - 1 - read-write - - - BYPASS - bypass tamper violation filter -0: filter applied -1: filter not used - 20 - 1 - read-write - - - FILTER - filter length -0: 1 cycle -1: 2 cycle -15: 65526 cycle - 16 - 4 - read-write - - - VALUE - pin value for passive tamper - 8 - 2 - read-write - - - SPEED - tamper speed selection, (2^SPEED) changes per second -0: 1 shift per second -1: 2 shifts per second -. . . -15: 32768 shifts per second - 4 - 4 - read-write - - - RECOVER - tamper will recover itself if tamper LFSR goes wrong -0: tamper will not recover -1: tamper will recover - 2 - 1 - read-write - - - ACTIVE - select active or passive tamper -0: passive tamper -1: active tamper - 1 - 1 - read-write - - - ENABLE - enable tamper -0: tamper disableed -1: tamper enabled - 0 - 1 - read-write - - - - - POLY - Tamper n Polynomial of LFSR - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - POLY - tamper LFSR polyminal, this is a write once register, once write content is locked, and readout value is "1" - 0 - 32 - read-write - - - - - LFSR - Tamper n LFSR shift register - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - LFSR - LFSR for active tamper, write only register, always read 0 - 0 - 32 - write-only - - - - - - TAMP_FLAG - Tamper flag - 0x80 - 32 - 0x00000000 - 0x00000FFF - - - FLAG - tamper flag, each bit represents one tamper pin, write 1 to clear the flag -Note, clear can only be cleared when tamper disappeared - 0 - 12 - read-write - - - - - IRQ_EN - Tamper interrupt enable - 0x84 - 32 - 0x00000000 - 0x80000FFF - - - LOCK - lock bit for IRQ enable -0: enable bits can be changed -1: enable bits hold until next battery domain power cycle - 31 - 1 - read-write - - - IRQ_EN - interrupt enable, each bit represents one tamper pin -0: interrupt disabled -1: interrupt enabled - 0 - 12 - read-write - - - - - - - MONO - MONO - MONO - 0xf5054000 - - 0x0 - 0x8 - registers - - - - MONOL - Low part of monotonic counter - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - COUNTER - low part of monotonica counter, write to this counter will cause counter increase by 1 - 0 - 32 - read-write - - - - - MONOH - High part of monotonic counter - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - EPOCH - Fuse value for high part of monotonica - 16 - 16 - read-write - - - COUNTER - high part of monotonica counter, write to this counter will cause counter increase by 1 if low part overflow - 0 - 16 - read-write - - - - - - -