diff --git a/.github/workflows/build.yaml b/.github/workflows/build.yaml index c4f5611f35a..f85395fd886 100644 --- a/.github/workflows/build.yaml +++ b/.github/workflows/build.yaml @@ -144,7 +144,7 @@ jobs: username: ${{ github.repository_owner }} password: ${{ secrets.GITHUB_TOKEN }} - name: Build and Push - uses: docker/build-push-action@v6.9.0 + uses: docker/build-push-action@v6.10.0 id: build_haos_builder with: context: . diff --git a/.github/workflows/test.yaml b/.github/workflows/test.yaml index cf66c86ac66..7b7804fe508 100644 --- a/.github/workflows/test.yaml +++ b/.github/workflows/test.yaml @@ -93,7 +93,7 @@ jobs: tests/junit_reports/*.xml - name: Publish test report - uses: mikepenz/action-junit-report@v4 + uses: mikepenz/action-junit-report@v5 if: always() with: report_paths: 'tests/junit_reports/*.xml' diff --git a/Documentation/kernel.md b/Documentation/kernel.md index cf269dfc2fa..f8af6272d53 100644 --- a/Documentation/kernel.md +++ b/Documentation/kernel.md @@ -3,22 +3,22 @@ | Board | Version | |-------|---------| -| Open Virtual Appliance | 6.6.54 | -| Raspberry Pi | 6.6.31 | -| Raspberry Pi 0-W | 6.6.31 | -| Raspberry Pi 2 | 6.6.31 | -| Raspberry Pi 3 | 6.6.31 | -| Raspberry Pi 4 | 6.6.31 | -| Raspberry Pi 5 | 6.6.31 | -| Home Assistant Yellow | 6.6.31 | -| Home Assistant Green | 6.6.54 | -| Tinker Board | 6.6.54 | -| ODROID-C2 | 6.6.54 | -| ODROID-C4 | 6.6.54 | -| ODROID-M1 | 6.6.54 | -| ODROID-M1S | 6.6.54 | -| ODROID-N2 | 6.6.54 | -| ODROID-XU4 | 6.6.54 | -| Generic aarch64 | 6.6.54 | -| Generic x86-64 | 6.6.54 | -| Khadas VIM3 | 6.6.54 | +| Open Virtual Appliance | 6.6.63 | +| Raspberry Pi | 6.6.51 | +| Raspberry Pi 0-W | 6.6.51 | +| Raspberry Pi 2 | 6.6.51 | +| Raspberry Pi 3 | 6.6.51 | +| Raspberry Pi 4 | 6.6.51 | +| Raspberry Pi 5 | 6.6.51 | +| Home Assistant Yellow | 6.6.51 | +| Home Assistant Green | 6.6.63 | +| Tinker Board | 6.6.63 | +| ODROID-C2 | 6.6.63 | +| ODROID-C4 | 6.6.63 | +| ODROID-M1 | 6.6.63 | +| ODROID-M1S | 6.6.63 | +| ODROID-N2 | 6.6.63 | +| ODROID-XU4 | 6.6.63 | +| Generic aarch64 | 6.6.63 | +| Generic x86-64 | 6.6.63 | +| Khadas VIM3 | 6.6.63 | diff --git a/buildroot b/buildroot index d59d09ad381..1d7407c66b2 160000 --- a/buildroot +++ b/buildroot @@ -1 +1 @@ -Subproject commit d59d09ad3817bb4892dcbbd5794599982c2d3ea6 +Subproject commit 1d7407c66b22a34a6ac9b896a10c55fc4b9f2521 diff --git a/buildroot-external/Config.in b/buildroot-external/Config.in index 16cc12b661a..1227e1c654a 100644 --- a/buildroot-external/Config.in +++ b/buildroot-external/Config.in @@ -2,6 +2,7 @@ source "$BR2_EXTERNAL_HASSOS_PATH/package/bluetooth-rtl8723/Config.in" source "$BR2_EXTERNAL_HASSOS_PATH/package/eq3_char_loop/Config.in" source "$BR2_EXTERNAL_HASSOS_PATH/package/gasket/Config.in" source "$BR2_EXTERNAL_HASSOS_PATH/package/generic_raw_uart/Config.in" +source "$BR2_EXTERNAL_HASSOS_PATH/package/hailo8-firmware/Config.in" source "$BR2_EXTERNAL_HASSOS_PATH/package/hardkernel-boot/Config.in" source "$BR2_EXTERNAL_HASSOS_PATH/package/hassio/Config.in" source "$BR2_EXTERNAL_HASSOS_PATH/package/khadas-boot/Config.in" diff --git a/buildroot-external/board/hardkernel/patches/uboot/0001-HACK-mmc-meson-gx-limit-f_max-to-24-MHz-on-the-first.patch b/buildroot-external/board/hardkernel/patches/uboot/0001-HACK-mmc-meson-gx-limit-f_max-to-24-MHz-on-the-first.patch new file mode 100644 index 00000000000..6ea9730ff97 --- /dev/null +++ b/buildroot-external/board/hardkernel/patches/uboot/0001-HACK-mmc-meson-gx-limit-f_max-to-24-MHz-on-the-first.patch @@ -0,0 +1,81 @@ +From 024796cbf752d2e210341ae8609792803641eb92 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Jan=20=C4=8Cerm=C3=A1k?= +Date: Thu, 7 Nov 2024 12:39:02 +0100 +Subject: [PATCH] HACK: mmc: meson-gx: limit f_max to 24 MHz on the first try +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +To initialize some eMMCs cards properly, ODROID N2 needed to have +maximum clock rate limited to 24 MHz. This was working good until ODROID +released eMMC modules with Kingson chips which do not initialize at the +limited frequency at all - instead it seems it's best for the if +no limit is set (which would result in using 52 MHz anyway). + +Instead of hard-limiting the frequency, add a boolean flag that caps the +frequency to the proven 24 MHz, and if mmc_select_mode_and_width fails, +remove this cap and use f_max set to 100 MHz, as limited in upstream +U-Boot. + +Signed-off-by: Jan Čermák +--- + drivers/mmc/meson_gx_mmc.c | 2 ++ + drivers/mmc/mmc.c | 11 +++++++++++ + include/mmc.h | 2 ++ + 3 files changed, 15 insertions(+) + +diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c +index fcf4f03d1e..715dce3522 100644 +--- a/drivers/mmc/meson_gx_mmc.c ++++ b/drivers/mmc/meson_gx_mmc.c +@@ -283,6 +283,8 @@ static int meson_mmc_probe(struct udevice *dev) + cfg->b_max = 511; /* max 512 - 1 blocks */ + cfg->name = dev->name; + ++ mmc->meson_gx_f_max_hack = true; ++ + mmc->priv = pdata; + upriv->mmc = mmc; + +diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c +index d96db7a0f8..c8dc676612 100644 +--- a/drivers/mmc/mmc.c ++++ b/drivers/mmc/mmc.c +@@ -1652,6 +1652,10 @@ int mmc_set_clock(struct mmc *mmc, uint clock, bool disable) + clock = mmc->cfg->f_min; + } + ++ /* Apply 24 MHz limit that fixes issues with some cards on meson. */ ++ if (mmc->meson_gx_f_max_hack && clock > 24000000) ++ clock = 24000000; ++ + mmc->clock = clock; + mmc->clk_disable = disable; + +@@ -2647,6 +2651,13 @@ static int mmc_startup(struct mmc *mmc) + if (err) + return err; + err = mmc_select_mode_and_width(mmc, mmc->card_caps); ++ if (err && mmc->meson_gx_f_max_hack) { ++ /* Some eMMCs (namely Kingston) do not initialize at limited frequency. */ ++ printf("Card failed to initialize at %d Hz, disabling meson_gx hack.\n", ++ mmc->clock); ++ mmc->meson_gx_f_max_hack = false; ++ err = mmc_select_mode_and_width(mmc, mmc->card_caps); ++ } + } + #endif + if (err) +diff --git a/include/mmc.h b/include/mmc.h +index 1022db3ffa..0ea48c6fd9 100644 +--- a/include/mmc.h ++++ b/include/mmc.h +@@ -739,6 +739,8 @@ struct mmc { + u8 hs400_tuning; + + enum bus_mode user_speed_mode; /* input speed mode from user */ ++ ++ bool meson_gx_f_max_hack; + }; + + #if CONFIG_IS_ENABLED(DM_MMC) diff --git a/buildroot-external/board/hardkernel/patches/uboot/0001-HACK-mmc-meson-gx-limit-to-24MHz.patch b/buildroot-external/board/hardkernel/patches/uboot/0001-HACK-mmc-meson-gx-limit-to-24MHz.patch deleted file mode 100644 index c56843027f5..00000000000 --- a/buildroot-external/board/hardkernel/patches/uboot/0001-HACK-mmc-meson-gx-limit-to-24MHz.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 11f015e13ef0442b6d2bb734954291abde415f73 Mon Sep 17 00:00:00 2001 -From: Neil Armstrong -Date: Mon, 2 Sep 2019 15:42:04 +0200 -Subject: [PATCH] HACK: mmc: meson-gx: limit to 24MHz - -Signed-off-by: Neil Armstrong ---- - drivers/mmc/meson_gx_mmc.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c -index fcf4f03d1e..6ded4b619b 100644 ---- a/drivers/mmc/meson_gx_mmc.c -+++ b/drivers/mmc/meson_gx_mmc.c -@@ -279,7 +279,7 @@ static int meson_mmc_probe(struct udevice *dev) - cfg->host_caps = MMC_MODE_8BIT | MMC_MODE_4BIT | - MMC_MODE_HS_52MHz | MMC_MODE_HS; - cfg->f_min = DIV_ROUND_UP(SD_EMMC_CLKSRC_24M, CLK_MAX_DIV); -- cfg->f_max = 100000000; /* 100 MHz */ -+ cfg->f_max = SD_EMMC_CLKSRC_24M; - cfg->b_max = 511; /* max 512 - 1 blocks */ - cfg->name = dev->name; - --- -2.43.0 - diff --git a/buildroot-external/board/pc/generic-x86-64/kernel.config b/buildroot-external/board/pc/generic-x86-64/kernel.config index 7518b6ae068..ecd02ea9099 100644 --- a/buildroot-external/board/pc/generic-x86-64/kernel.config +++ b/buildroot-external/board/pc/generic-x86-64/kernel.config @@ -172,3 +172,6 @@ CONFIG_DLN2_ADC=m CONFIG_IIO=m CONFIG_BMP280=m + +# Required for some PCIe devices such as ath12k +CONFIG_IRQ_REMAP=y diff --git a/buildroot-external/board/pc/ova/kernel.config b/buildroot-external/board/pc/ova/kernel.config index b0225957680..44ed52d1a6d 100644 --- a/buildroot-external/board/pc/ova/kernel.config +++ b/buildroot-external/board/pc/ova/kernel.config @@ -124,4 +124,19 @@ CONFIG_DWMAC_INTEL=m CONFIG_I6300ESB_WDT=y CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_CHARDEV=m CONFIG_I2C_MUX=y +CONFIG_I2C_TINY_USB=m + +CONFIG_I2C_DLN2=m +CONFIG_GPIO_DLN2=m +CONFIG_MFD_DLN2=m +CONFIG_DLN2_ADC=m + +CONFIG_IIO=m +CONFIG_BMP280=m + +# Required for some PCIe devices such as ath12k +CONFIG_IRQ_REMAP=y diff --git a/buildroot-external/board/raspberrypi/cmdline.txt b/buildroot-external/board/raspberrypi/cmdline.txt index 669314f907c..55e3300d091 100644 --- a/buildroot-external/board/raspberrypi/cmdline.txt +++ b/buildroot-external/board/raspberrypi/cmdline.txt @@ -1 +1 @@ -dwc_otg.lpm_enable=0 console=tty0 usb-storage.quirks=174c:55aa:u,2109:0715:u,152d:0578:u,152d:0579:u,152d:1561:u,174c:0829:u,14b0:0206:u,174c:225c:u,7825:a2a4:u,152d:0562:u,125f:a88a:u +dwc_otg.lpm_enable=0 console=tty0 usb-storage.quirks=174c:55aa:u,2109:0715:u,152d:0578:u,152d:0579:u,152d:1561:u,174c:0829:u,14b0:0206:u,174c:225c:u,7825:a2a4:u,152d:0562:u,125f:a88a:u,152d:a583:u diff --git a/buildroot-external/board/raspberrypi/patches/uboot/0001-rpi-Use-CONFIG_OF_BOARD-instead-of-CONFIG_EMBED.patch b/buildroot-external/board/raspberrypi/patches/uboot/2024.01/0001-rpi-Use-CONFIG_OF_BOARD-instead-of-CONFIG_EMBED.patch similarity index 100% rename from buildroot-external/board/raspberrypi/patches/uboot/0001-rpi-Use-CONFIG_OF_BOARD-instead-of-CONFIG_EMBED.patch rename to buildroot-external/board/raspberrypi/patches/uboot/2024.01/0001-rpi-Use-CONFIG_OF_BOARD-instead-of-CONFIG_EMBED.patch diff --git a/buildroot-external/board/raspberrypi/patches/uboot/0002-rpi-add-NVMe-to-boot-order.patch b/buildroot-external/board/raspberrypi/patches/uboot/2024.01/0002-rpi-add-NVMe-to-boot-order.patch similarity index 100% rename from buildroot-external/board/raspberrypi/patches/uboot/0002-rpi-add-NVMe-to-boot-order.patch rename to buildroot-external/board/raspberrypi/patches/uboot/2024.01/0002-rpi-add-NVMe-to-boot-order.patch diff --git a/buildroot-external/board/raspberrypi/patches/uboot/0003-Revert-nvme-Correct-the-prps-per-page-calculation-me.patch b/buildroot-external/board/raspberrypi/patches/uboot/2024.01/0003-Revert-nvme-Correct-the-prps-per-page-calculation-me.patch similarity index 100% rename from buildroot-external/board/raspberrypi/patches/uboot/0003-Revert-nvme-Correct-the-prps-per-page-calculation-me.patch rename to buildroot-external/board/raspberrypi/patches/uboot/2024.01/0003-Revert-nvme-Correct-the-prps-per-page-calculation-me.patch diff --git a/buildroot-external/board/raspberrypi/patches/uboot/0004-usb-xhci-brcm-Make-driver-compatible-with-downstream.patch b/buildroot-external/board/raspberrypi/patches/uboot/2024.01/0004-usb-xhci-brcm-Make-driver-compatible-with-downstream.patch similarity index 100% rename from buildroot-external/board/raspberrypi/patches/uboot/0004-usb-xhci-brcm-Make-driver-compatible-with-downstream.patch rename to buildroot-external/board/raspberrypi/patches/uboot/2024.01/0004-usb-xhci-brcm-Make-driver-compatible-with-downstream.patch diff --git a/buildroot-external/board/raspberrypi/patches/uboot/0005-nvme-improve-readability-of-nvme_setup_prps.patch b/buildroot-external/board/raspberrypi/patches/uboot/2024.01/0005-nvme-improve-readability-of-nvme_setup_prps.patch similarity index 100% rename from buildroot-external/board/raspberrypi/patches/uboot/0005-nvme-improve-readability-of-nvme_setup_prps.patch rename to buildroot-external/board/raspberrypi/patches/uboot/2024.01/0005-nvme-improve-readability-of-nvme_setup_prps.patch diff --git a/buildroot-external/board/raspberrypi/patches/uboot/0006-nvme-Use-pointer-for-CPU-addressed-buffers.patch b/buildroot-external/board/raspberrypi/patches/uboot/2024.01/0006-nvme-Use-pointer-for-CPU-addressed-buffers.patch similarity index 100% rename from buildroot-external/board/raspberrypi/patches/uboot/0006-nvme-Use-pointer-for-CPU-addressed-buffers.patch rename to buildroot-external/board/raspberrypi/patches/uboot/2024.01/0006-nvme-Use-pointer-for-CPU-addressed-buffers.patch diff --git a/buildroot-external/board/raspberrypi/patches/uboot/0007-nvme-translate-virtual-addresses-into-the-bus-s-addr.patch b/buildroot-external/board/raspberrypi/patches/uboot/2024.01/0007-nvme-translate-virtual-addresses-into-the-bus-s-addr.patch similarity index 100% rename from buildroot-external/board/raspberrypi/patches/uboot/0007-nvme-translate-virtual-addresses-into-the-bus-s-addr.patch rename to buildroot-external/board/raspberrypi/patches/uboot/2024.01/0007-nvme-translate-virtual-addresses-into-the-bus-s-addr.patch diff --git a/buildroot-external/board/raspberrypi/patches/uboot/0008-Revert-pci-Check-region-ranges-are-addressable.patch b/buildroot-external/board/raspberrypi/patches/uboot/2024.01/0008-Revert-pci-Check-region-ranges-are-addressable.patch similarity index 100% rename from buildroot-external/board/raspberrypi/patches/uboot/0008-Revert-pci-Check-region-ranges-are-addressable.patch rename to buildroot-external/board/raspberrypi/patches/uboot/2024.01/0008-Revert-pci-Check-region-ranges-are-addressable.patch diff --git a/buildroot-external/board/raspberrypi/patches/uboot/2024.10/0001-rpi-add-NVMe-to-boot-order.patch b/buildroot-external/board/raspberrypi/patches/uboot/2024.10/0001-rpi-add-NVMe-to-boot-order.patch new file mode 100644 index 00000000000..4a93de5a24c --- /dev/null +++ b/buildroot-external/board/raspberrypi/patches/uboot/2024.10/0001-rpi-add-NVMe-to-boot-order.patch @@ -0,0 +1,23 @@ +From 3d9bd29941ce291e44aab60be1339d4c116ebda5 Mon Sep 17 00:00:00 2001 +From: Stefan Agner +Date: Tue, 29 Dec 2020 23:34:52 +0100 +Subject: [PATCH] rpi: add NVMe to boot order + +The Compute Module 4 I/O Board can support a NVMe. Add NVMe to the boot +order. + +Signed-off-by: Stefan Agner +--- + board/raspberrypi/rpi/rpi.env | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/board/raspberrypi/rpi/rpi.env b/board/raspberrypi/rpi/rpi.env +index 30228285ed..89f6c5a839 100644 +--- a/board/raspberrypi/rpi/rpi.env ++++ b/board/raspberrypi/rpi/rpi.env +@@ -74,4 +74,4 @@ pxefile_addr_r=0x02500000 + fdt_addr_r=0x02600000 + ramdisk_addr_r=0x02700000 + +-boot_targets=mmc usb pxe dhcp ++boot_targets=mmc nvme usb pxe dhcp diff --git a/buildroot-external/board/raspberrypi/patches/uboot/2024.10/0002-Revert-nvme-Correct-the-prps-per-page-calculation-me.patch b/buildroot-external/board/raspberrypi/patches/uboot/2024.10/0002-Revert-nvme-Correct-the-prps-per-page-calculation-me.patch new file mode 100644 index 00000000000..ee08921a954 --- /dev/null +++ b/buildroot-external/board/raspberrypi/patches/uboot/2024.10/0002-Revert-nvme-Correct-the-prps-per-page-calculation-me.patch @@ -0,0 +1,37 @@ +From ab13da2df9f86517df45da293ed8002e07a3d5ec Mon Sep 17 00:00:00 2001 +From: Stefan Agner +Date: Thu, 23 Sep 2021 23:43:31 +0200 +Subject: [PATCH] Revert "nvme: Correct the prps per page calculation method" + +This reverts commit 859b33c948945f7904f60a2c12a3792d356d51ad. + +If there is more than one PRP List the last entry is a pointer to +the next list. From the NVM Express specification: + +"The last entry within a memory page, as indicated by the memory page +size in the CC.MPS field, shall be a PRP List pointer if there is more +than a single memory page of data to be transferred." + +For the purpose of calculating the number of pages required for PRP +lists we should always assume that the last entry is required for +the next PRP list. + +Signed-off-by: Stefan Agner +Cc: Wesley Sheng +--- + drivers/nvme/nvme.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c +index 7c58ceb78f..0b2496cf26 100644 +--- a/drivers/nvme/nvme.c ++++ b/drivers/nvme/nvme.c +@@ -52,7 +52,7 @@ static int nvme_setup_prps(struct nvme_dev *dev, u64 *prp2, + u64 *prp_pool; + int length = total_len; + int i, nprps; +- u32 prps_per_page = page_size >> 3; ++ u32 prps_per_page = (page_size >> 3) - 1; + u32 num_pages; + + length -= (page_size - offset); diff --git a/buildroot-external/board/raspberrypi/patches/uboot/2024.10/0003-usb-xhci-brcm-Make-driver-compatible-with-downstream.patch b/buildroot-external/board/raspberrypi/patches/uboot/2024.10/0003-usb-xhci-brcm-Make-driver-compatible-with-downstream.patch new file mode 100644 index 00000000000..96f127e6790 --- /dev/null +++ b/buildroot-external/board/raspberrypi/patches/uboot/2024.10/0003-usb-xhci-brcm-Make-driver-compatible-with-downstream.patch @@ -0,0 +1,27 @@ +From 9de58838106829b8caa47b6fd6b42ba3435c2ce6 Mon Sep 17 00:00:00 2001 +From: Stefan Agner +Date: Thu, 7 Oct 2021 12:02:39 +0200 +Subject: [PATCH] usb: xhci-brcm: Make driver compatible with downstream device + tree + +The downstream device tree uses just "generic-xhci" as compatible +string. Use this string to make U-Boot work with the downstream Kernel. + +Signed-off-by: Stefan Agner +--- + drivers/usb/host/xhci-brcm.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/usb/host/xhci-brcm.c b/drivers/usb/host/xhci-brcm.c +index 2ffad148de..2a063ccc9e 100644 +--- a/drivers/usb/host/xhci-brcm.c ++++ b/drivers/usb/host/xhci-brcm.c +@@ -81,7 +81,7 @@ static int xhci_brcm_deregister(struct udevice *dev) + } + + static const struct udevice_id xhci_brcm_ids[] = { +- { .compatible = "brcm,generic-xhci" }, ++ { .compatible = "generic-xhci" }, + { } + }; + diff --git a/buildroot-external/board/raspberrypi/patches/uboot/2024.10/0004-nvme-improve-readability-of-nvme_setup_prps.patch b/buildroot-external/board/raspberrypi/patches/uboot/2024.10/0004-nvme-improve-readability-of-nvme_setup_prps.patch new file mode 100644 index 00000000000..6c54abcf236 --- /dev/null +++ b/buildroot-external/board/raspberrypi/patches/uboot/2024.10/0004-nvme-improve-readability-of-nvme_setup_prps.patch @@ -0,0 +1,43 @@ +From 8c5910539c7e4e97f233789c2489c800f87ddf81 Mon Sep 17 00:00:00 2001 +From: Stefan Agner +Date: Thu, 23 Sep 2021 23:52:44 +0200 +Subject: [PATCH] nvme: improve readability of nvme_setup_prps() + +Improve readability by introducing consts, reuse consts where +appropriate and adding variables with discriptive name. + +Signed-off-by: Stefan Agner +--- + drivers/nvme/nvme.c | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c +index 0b2496cf26..b1d8eecdca 100644 +--- a/drivers/nvme/nvme.c ++++ b/drivers/nvme/nvme.c +@@ -47,12 +47,12 @@ static int nvme_wait_csts(struct nvme_dev *dev, u32 mask, u32 val) + static int nvme_setup_prps(struct nvme_dev *dev, u64 *prp2, + int total_len, u64 dma_addr) + { +- u32 page_size = dev->page_size; ++ const u32 page_size = dev->page_size; ++ const u32 prps_per_page = (page_size >> 3) - 1; + int offset = dma_addr & (page_size - 1); + u64 *prp_pool; + int length = total_len; + int i, nprps; +- u32 prps_per_page = (page_size >> 3) - 1; + u32 num_pages; + + length -= (page_size - offset); +@@ -91,8 +91,8 @@ static int nvme_setup_prps(struct nvme_dev *dev, u64 *prp2, + i = 0; + while (nprps) { + if ((i == (prps_per_page - 1)) && nprps > 1) { +- *(prp_pool + i) = cpu_to_le64((ulong)prp_pool + +- page_size); ++ u64 next_prp_list = (u64)prp_pool + page_size; ++ *(prp_pool + i) = cpu_to_le64(next_prp_list); + i = 0; + prp_pool += page_size; + } diff --git a/buildroot-external/board/raspberrypi/patches/uboot/2024.10/0005-nvme-Use-pointer-for-CPU-addressed-buffers.patch b/buildroot-external/board/raspberrypi/patches/uboot/2024.10/0005-nvme-Use-pointer-for-CPU-addressed-buffers.patch new file mode 100644 index 00000000000..db89d2005d3 --- /dev/null +++ b/buildroot-external/board/raspberrypi/patches/uboot/2024.10/0005-nvme-Use-pointer-for-CPU-addressed-buffers.patch @@ -0,0 +1,258 @@ +From e3f73d6ddba46f3b4ec8833c11f9ad831e57d394 Mon Sep 17 00:00:00 2001 +From: Stefan Agner +Date: Thu, 23 Sep 2021 23:58:35 +0200 +Subject: [PATCH] nvme: Use pointer for CPU addressed buffers + +Pass buffers which use CPU addressing as void pointers. This aligns with +DMA APIs which use void pointers as argument. It will avoid unnecessary +type casts when adding support bus address translations. + +Signed-off-by: Stefan Agner +--- + drivers/nvme/nvme.c | 50 ++++++++++++++++++++-------------------- + drivers/nvme/nvme_show.c | 4 ++-- + include/nvme.h | 12 +++++----- + 3 files changed, 33 insertions(+), 33 deletions(-) + +diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c +index b1d8eecdca..f626a472ff 100644 +--- a/drivers/nvme/nvme.c ++++ b/drivers/nvme/nvme.c +@@ -45,11 +45,11 @@ static int nvme_wait_csts(struct nvme_dev *dev, u32 mask, u32 val) + } + + static int nvme_setup_prps(struct nvme_dev *dev, u64 *prp2, +- int total_len, u64 dma_addr) ++ int total_len, void *buffer) + { + const u32 page_size = dev->page_size; + const u32 prps_per_page = (page_size >> 3) - 1; +- int offset = dma_addr & (page_size - 1); ++ int offset = (uintptr_t)buffer & (page_size - 1); + u64 *prp_pool; + int length = total_len; + int i, nprps; +@@ -63,10 +63,10 @@ static int nvme_setup_prps(struct nvme_dev *dev, u64 *prp2, + } + + if (length) +- dma_addr += (page_size - offset); ++ buffer += (page_size - offset); + + if (length <= page_size) { +- *prp2 = dma_addr; ++ *prp2 = (u64)buffer; + return 0; + } + +@@ -96,11 +96,11 @@ static int nvme_setup_prps(struct nvme_dev *dev, u64 *prp2, + i = 0; + prp_pool += page_size; + } +- *(prp_pool + i++) = cpu_to_le64(dma_addr); +- dma_addr += page_size; ++ *(prp_pool + i++) = cpu_to_le64((u64)buffer); ++ buffer += page_size; + nprps--; + } +- *prp2 = (ulong)dev->prp_pool; ++ *prp2 = (u64)dev->prp_pool; + + flush_dcache_range((ulong)dev->prp_pool, (ulong)dev->prp_pool + + num_pages * page_size); +@@ -447,42 +447,42 @@ static int nvme_alloc_sq(struct nvme_dev *dev, u16 qid, + } + + int nvme_identify(struct nvme_dev *dev, unsigned nsid, +- unsigned cns, dma_addr_t dma_addr) ++ unsigned int cns, void *buffer) + { + struct nvme_command c; + u32 page_size = dev->page_size; +- int offset = dma_addr & (page_size - 1); ++ int offset = (uintptr_t)buffer & (page_size - 1); + int length = sizeof(struct nvme_id_ctrl); + int ret; + + memset(&c, 0, sizeof(c)); + c.identify.opcode = nvme_admin_identify; + c.identify.nsid = cpu_to_le32(nsid); +- c.identify.prp1 = cpu_to_le64(dma_addr); ++ c.identify.prp1 = cpu_to_le64((u64)buffer); + + length -= (page_size - offset); + if (length <= 0) { + c.identify.prp2 = 0; + } else { +- dma_addr += (page_size - offset); +- c.identify.prp2 = cpu_to_le64(dma_addr); ++ buffer += (page_size - offset); ++ c.identify.prp2 = cpu_to_le64((u64)buffer); + } + + c.identify.cns = cpu_to_le32(cns); + +- invalidate_dcache_range(dma_addr, +- dma_addr + sizeof(struct nvme_id_ctrl)); ++ invalidate_dcache_range((uintptr_t)buffer, ++ (uintptr_t)buffer + sizeof(struct nvme_id_ctrl)); + + ret = nvme_submit_admin_cmd(dev, &c, NULL); + if (!ret) +- invalidate_dcache_range(dma_addr, +- dma_addr + sizeof(struct nvme_id_ctrl)); ++ invalidate_dcache_range((uintptr_t)buffer, ++ (uintptr_t)buffer + sizeof(struct nvme_id_ctrl)); + + return ret; + } + + int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid, +- dma_addr_t dma_addr, u32 *result) ++ void *buffer, u32 *result) + { + struct nvme_command c; + int ret; +@@ -490,7 +490,7 @@ int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid, + memset(&c, 0, sizeof(c)); + c.features.opcode = nvme_admin_get_features; + c.features.nsid = cpu_to_le32(nsid); +- c.features.prp1 = cpu_to_le64(dma_addr); ++ c.features.prp1 = cpu_to_le64((u64)buffer); + c.features.fid = cpu_to_le32(fid); + + ret = nvme_submit_admin_cmd(dev, &c, result); +@@ -510,13 +510,13 @@ int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid, + } + + int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11, +- dma_addr_t dma_addr, u32 *result) ++ void *buffer, u32 *result) + { + struct nvme_command c; + + memset(&c, 0, sizeof(c)); + c.features.opcode = nvme_admin_set_features; +- c.features.prp1 = cpu_to_le64(dma_addr); ++ c.features.prp1 = cpu_to_le64((u64)buffer); + c.features.fid = cpu_to_le32(fid); + c.features.dword11 = cpu_to_le32(dword11); + +@@ -567,7 +567,7 @@ static int nvme_set_queue_count(struct nvme_dev *dev, int count) + u32 q_count = (count - 1) | ((count - 1) << 16); + + status = nvme_set_features(dev, NVME_FEAT_NUM_QUEUES, +- q_count, 0, &result); ++ q_count, NULL, &result); + + if (status < 0) + return status; +@@ -628,7 +628,7 @@ static int nvme_get_info_from_identify(struct nvme_dev *dev) + if (!ctrl) + return -ENOMEM; + +- ret = nvme_identify(dev, 0, 1, (dma_addr_t)(long)ctrl); ++ ret = nvme_identify(dev, 0, 1, ctrl); + if (ret) { + free(ctrl); + return -EIO; +@@ -718,7 +718,7 @@ static int nvme_blk_probe(struct udevice *udev) + ns->dev = ndev; + /* extract the namespace id from the block device name */ + ns->ns_id = trailing_strtol(udev->name); +- if (nvme_identify(ndev, ns->ns_id, 0, (dma_addr_t)(long)id)) { ++ if (nvme_identify(ndev, ns->ns_id, 0, id)) { + free(id); + return -EIO; + } +@@ -752,7 +752,7 @@ static ulong nvme_blk_rw(struct udevice *udev, lbaint_t blknr, + u64 prp2; + u64 total_len = blkcnt << desc->log2blksz; + u64 temp_len = total_len; +- uintptr_t temp_buffer = (uintptr_t)buffer; ++ void *temp_buffer = buffer; + + u64 slba = blknr; + u16 lbas = 1 << (dev->max_transfer_shift - ns->lba_shift); +@@ -890,7 +890,7 @@ int nvme_init(struct udevice *udev) + char name[20]; + + memset(id, 0, sizeof(*id)); +- if (nvme_identify(ndev, i, 0, (dma_addr_t)(long)id)) { ++ if (nvme_identify(ndev, i, 0, id)) { + ret = -EIO; + goto free_id; + } +diff --git a/drivers/nvme/nvme_show.c b/drivers/nvme/nvme_show.c +index b06cb5c6d5..ad1a260f9a 100644 +--- a/drivers/nvme/nvme_show.c ++++ b/drivers/nvme/nvme_show.c +@@ -113,7 +113,7 @@ int nvme_print_info(struct udevice *udev) + if (!ctrl) + return -ENOMEM; + +- if (nvme_identify(dev, 0, 1, (dma_addr_t)(long)ctrl)) { ++ if (nvme_identify(dev, 0, 1, ctrl)) { + ret = -EIO; + goto free_ctrl; + } +@@ -128,7 +128,7 @@ int nvme_print_info(struct udevice *udev) + goto free_ctrl; + } + +- if (nvme_identify(dev, ns->ns_id, 0, (dma_addr_t)(long)id)) { ++ if (nvme_identify(dev, ns->ns_id, 0, id)) { + ret = -EIO; + goto free_id; + } +diff --git a/include/nvme.h b/include/nvme.h +index 2cdf8ce320..8ff823cd81 100644 +--- a/include/nvme.h ++++ b/include/nvme.h +@@ -18,12 +18,12 @@ struct nvme_dev; + * @dev: NVMe controller device + * @nsid: 0 for controller, namespace id for namespace to identify + * @cns: 1 for controller, 0 for namespace +- * @dma_addr: dma buffer address to store the identify result ++ * @buffer: dma buffer address to store the identify result + * @return: 0 on success, -ETIMEDOUT on command execution timeout, + * -EIO on command execution fails + */ + int nvme_identify(struct nvme_dev *dev, unsigned nsid, +- unsigned cns, dma_addr_t dma_addr); ++ unsigned int cns, void *buffer); + + /** + * nvme_get_features - retrieve the attributes of the feature specified +@@ -33,13 +33,13 @@ int nvme_identify(struct nvme_dev *dev, unsigned nsid, + * @dev: NVMe controller device + * @fid: feature id to provide data + * @nsid: namespace id the command applies to +- * @dma_addr: data structure used as part of the specified feature ++ * @buffer: data structure used as part of the specified feature + * @result: command-specific result in the completion queue entry + * @return: 0 on success, -ETIMEDOUT on command execution timeout, + * -EIO on command execution fails + */ + int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid, +- dma_addr_t dma_addr, u32 *result); ++ void *buffer, u32 *result); + + /** + * nvme_set_features - specify the attributes of the feature indicated +@@ -49,13 +49,13 @@ int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid, + * @dev: NVMe controller device + * @fid: feature id to provide data + * @dword11: command-specific input parameter +- * @dma_addr: data structure used as part of the specified feature ++ * @buffer: data structure used as part of the specified feature + * @result: command-specific result in the completion queue entry + * @return: 0 on success, -ETIMEDOUT on command execution timeout, + * -EIO on command execution fails + */ + int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11, +- dma_addr_t dma_addr, u32 *result); ++ void *buffer, u32 *result); + + /** + * nvme_scan_namespace - scan all namespaces attached to NVMe controllers diff --git a/buildroot-external/board/raspberrypi/patches/uboot/2024.10/0006-nvme-translate-virtual-addresses-into-the-bus-s-addr.patch b/buildroot-external/board/raspberrypi/patches/uboot/2024.10/0006-nvme-translate-virtual-addresses-into-the-bus-s-addr.patch new file mode 100644 index 00000000000..110cc60dd06 --- /dev/null +++ b/buildroot-external/board/raspberrypi/patches/uboot/2024.10/0006-nvme-translate-virtual-addresses-into-the-bus-s-addr.patch @@ -0,0 +1,170 @@ +From 1c9ebd44d5af878719f041d6a2329cc81674134c Mon Sep 17 00:00:00 2001 +From: Stefan Agner +Date: Fri, 24 Sep 2021 00:27:39 +0200 +Subject: [PATCH] nvme: translate virtual addresses into the bus's address + space + +So far we've been content with passing physical/CPU addresses when +configuring memory addresses into NVMe controllers, but not all +platforms have buses with transparent mappings. Specifically the +Raspberry Pi 4 might introduce an offset to memory accesses incoming +from its PCIe port. + +Introduce nvme_virt_to_bus() and nvme_bus_to_virt() to cater with these +limitations, and make sure we don't break non DM users. +For devices where PCIe's view of host memory doesn't match the memory +as seen by the CPU. + +A similar change has been introduced for XHCI controller with +commit 1a474559d90a ("xhci: translate virtual addresses into the bus's +address space"). + +Signed-off-by: Stefan Agner +--- + drivers/nvme/nvme.c | 31 +++++++++++++++++-------------- + drivers/nvme/nvme.h | 8 ++++++++ + 2 files changed, 25 insertions(+), 14 deletions(-) + +diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c +index f626a472ff..70ce63f205 100644 +--- a/drivers/nvme/nvme.c ++++ b/drivers/nvme/nvme.c +@@ -66,7 +66,7 @@ static int nvme_setup_prps(struct nvme_dev *dev, u64 *prp2, + buffer += (page_size - offset); + + if (length <= page_size) { +- *prp2 = (u64)buffer; ++ *prp2 = nvme_virt_to_bus(dev, buffer); + return 0; + } + +@@ -91,16 +91,16 @@ static int nvme_setup_prps(struct nvme_dev *dev, u64 *prp2, + i = 0; + while (nprps) { + if ((i == (prps_per_page - 1)) && nprps > 1) { +- u64 next_prp_list = (u64)prp_pool + page_size; +- *(prp_pool + i) = cpu_to_le64(next_prp_list); ++ u64 next = nvme_virt_to_bus(dev, prp_pool + page_size); ++ *(prp_pool + i) = cpu_to_le64(next); + i = 0; + prp_pool += page_size; + } +- *(prp_pool + i++) = cpu_to_le64((u64)buffer); ++ *(prp_pool + i++) = cpu_to_le64(nvme_virt_to_bus(dev, buffer)); + buffer += page_size; + nprps--; + } +- *prp2 = (u64)dev->prp_pool; ++ *prp2 = nvme_virt_to_bus(dev, dev->prp_pool); + + flush_dcache_range((ulong)dev->prp_pool, (ulong)dev->prp_pool + + num_pages * page_size); +@@ -353,6 +353,7 @@ static int nvme_configure_admin_queue(struct nvme_dev *dev) + int result; + u32 aqa; + u64 cap = dev->cap; ++ u64 dma_addr; + struct nvme_queue *nvmeq; + /* most architectures use 4KB as the page size */ + unsigned page_shift = 12; +@@ -393,8 +394,10 @@ static int nvme_configure_admin_queue(struct nvme_dev *dev) + dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES; + + writel(aqa, &dev->bar->aqa); +- nvme_writeq((ulong)nvmeq->sq_cmds, &dev->bar->asq); +- nvme_writeq((ulong)nvmeq->cqes, &dev->bar->acq); ++ dma_addr = nvme_virt_to_bus(dev, nvmeq->sq_cmds); ++ nvme_writeq(dma_addr, &dev->bar->asq); ++ dma_addr = nvme_virt_to_bus(dev, nvmeq->cqes); ++ nvme_writeq(dma_addr, &dev->bar->acq); + + result = nvme_enable_ctrl(dev); + if (result) +@@ -420,7 +423,7 @@ static int nvme_alloc_cq(struct nvme_dev *dev, u16 qid, + + memset(&c, 0, sizeof(c)); + c.create_cq.opcode = nvme_admin_create_cq; +- c.create_cq.prp1 = cpu_to_le64((ulong)nvmeq->cqes); ++ c.create_cq.prp1 = cpu_to_le64(nvme_virt_to_bus(dev, nvmeq->cqes)); + c.create_cq.cqid = cpu_to_le16(qid); + c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); + c.create_cq.cq_flags = cpu_to_le16(flags); +@@ -437,7 +440,7 @@ static int nvme_alloc_sq(struct nvme_dev *dev, u16 qid, + + memset(&c, 0, sizeof(c)); + c.create_sq.opcode = nvme_admin_create_sq; +- c.create_sq.prp1 = cpu_to_le64((ulong)nvmeq->sq_cmds); ++ c.create_sq.prp1 = cpu_to_le64(nvme_virt_to_bus(dev, nvmeq->sq_cmds)); + c.create_sq.sqid = cpu_to_le16(qid); + c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); + c.create_sq.sq_flags = cpu_to_le16(flags); +@@ -458,14 +461,14 @@ int nvme_identify(struct nvme_dev *dev, unsigned nsid, + memset(&c, 0, sizeof(c)); + c.identify.opcode = nvme_admin_identify; + c.identify.nsid = cpu_to_le32(nsid); +- c.identify.prp1 = cpu_to_le64((u64)buffer); ++ c.identify.prp1 = cpu_to_le64(nvme_virt_to_bus(dev, buffer)); + + length -= (page_size - offset); + if (length <= 0) { + c.identify.prp2 = 0; + } else { + buffer += (page_size - offset); +- c.identify.prp2 = cpu_to_le64((u64)buffer); ++ c.identify.prp2 = cpu_to_le64(nvme_virt_to_bus(dev, buffer)); + } + + c.identify.cns = cpu_to_le32(cns); +@@ -490,7 +493,7 @@ int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid, + memset(&c, 0, sizeof(c)); + c.features.opcode = nvme_admin_get_features; + c.features.nsid = cpu_to_le32(nsid); +- c.features.prp1 = cpu_to_le64((u64)buffer); ++ c.features.prp1 = cpu_to_le64(nvme_virt_to_bus(dev, buffer)); + c.features.fid = cpu_to_le32(fid); + + ret = nvme_submit_admin_cmd(dev, &c, result); +@@ -516,7 +519,7 @@ int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11, + + memset(&c, 0, sizeof(c)); + c.features.opcode = nvme_admin_set_features; +- c.features.prp1 = cpu_to_le64((u64)buffer); ++ c.features.prp1 = cpu_to_le64(nvme_virt_to_bus(dev, buffer)); + c.features.fid = cpu_to_le32(fid); + c.features.dword11 = cpu_to_le32(dword11); + +@@ -785,7 +788,7 @@ static ulong nvme_blk_rw(struct udevice *udev, lbaint_t blknr, + c.rw.slba = cpu_to_le64(slba); + slba += lbas; + c.rw.length = cpu_to_le16(lbas - 1); +- c.rw.prp1 = cpu_to_le64(temp_buffer); ++ c.rw.prp1 = cpu_to_le64(nvme_virt_to_bus(dev, temp_buffer)); + c.rw.prp2 = cpu_to_le64(prp2); + status = nvme_submit_sync_cmd(dev->queues[NVME_IO_Q], + &c, NULL, IO_TIMEOUT); +diff --git a/drivers/nvme/nvme.h b/drivers/nvme/nvme.h +index bc1d612dde..f52103c009 100644 +--- a/drivers/nvme/nvme.h ++++ b/drivers/nvme/nvme.h +@@ -7,8 +7,11 @@ + #ifndef __DRIVER_NVME_H__ + #define __DRIVER_NVME_H__ + ++#include + #include + ++#define nvme_to_dev(_dev) _dev->udev ++ + struct nvme_id_power_state { + __le16 max_power; /* centiwatts */ + __u8 rsvd2; +@@ -705,4 +708,9 @@ int nvme_init(struct udevice *udev); + */ + int nvme_shutdown(struct udevice *udev); + ++static inline dma_addr_t nvme_virt_to_bus(struct nvme_dev *dev, void *addr) ++{ ++ return dev_phys_to_bus(nvme_to_dev(dev)->parent, virt_to_phys(addr)); ++} ++ + #endif /* __DRIVER_NVME_H__ */ diff --git a/buildroot-external/board/raspberrypi/patches/uboot/2024.10/0007-Revert-pci-Check-region-ranges-are-addressable.patch b/buildroot-external/board/raspberrypi/patches/uboot/2024.10/0007-Revert-pci-Check-region-ranges-are-addressable.patch new file mode 100644 index 00000000000..131d562f92d --- /dev/null +++ b/buildroot-external/board/raspberrypi/patches/uboot/2024.10/0007-Revert-pci-Check-region-ranges-are-addressable.patch @@ -0,0 +1,44 @@ +From 418664bb1dfa61b8fc1a0292adb00ec93e1a7619 Mon Sep 17 00:00:00 2001 +From: Stefan Agner +Date: Mon, 24 Apr 2023 15:44:15 +0200 +Subject: [PATCH] Revert "pci: Check region ranges are addressable" + +This reverts commit ec8eba8c2d4e10e77699c56918d2078210aa1339. + +This commit seems to cause boot hangs when USB via XHCI is enabled on +Raspberry Pi 4 32-bit. Reverting the commit fixes USB device detection +and makes the devices boot again. + +Signed-off-by: Stefan Agner +--- + drivers/pci/pci-uclass.c | 17 +---------------- + 1 file changed, 1 insertion(+), 16 deletions(-) + +diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c +index 6571e65304..803d5c25fc 100644 +--- a/drivers/pci/pci-uclass.c ++++ b/drivers/pci/pci-uclass.c +@@ -1038,22 +1038,7 @@ static int decode_regions(struct pci_controller *hose, ofnode parent_node, + + if (!IS_ENABLED(CONFIG_SYS_PCI_64BIT) && + type == PCI_REGION_MEM && upper_32_bits(pci_addr)) { +- debug(" - pci_addr beyond the 32-bit boundary, ignoring\n"); +- continue; +- } +- +- if (!IS_ENABLED(CONFIG_PHYS_64BIT) && upper_32_bits(addr)) { +- debug(" - addr beyond the 32-bit boundary, ignoring\n"); +- continue; +- } +- +- if (~((pci_addr_t)0) - pci_addr < size) { +- debug(" - PCI range exceeds max address, ignoring\n"); +- continue; +- } +- +- if (~((phys_addr_t)0) - addr < size) { +- debug(" - phys range exceeds max address, ignoring\n"); ++ debug(" - beyond the 32-bit boundary, ignoring\n"); + continue; + } + diff --git a/buildroot-external/board/raspberrypi/patches/uboot/2024.10/0008-reset-reset-brcmstb-Add-Broadcom-STB-reset-controlle.patch b/buildroot-external/board/raspberrypi/patches/uboot/2024.10/0008-reset-reset-brcmstb-Add-Broadcom-STB-reset-controlle.patch new file mode 100644 index 00000000000..85b295cbd06 --- /dev/null +++ b/buildroot-external/board/raspberrypi/patches/uboot/2024.10/0008-reset-reset-brcmstb-Add-Broadcom-STB-reset-controlle.patch @@ -0,0 +1,145 @@ +From 81100e760c8ed3d697696de5353d51e8e1af2be4 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Jan=20=C4=8Cerm=C3=A1k?= +Date: Mon, 30 Sep 2024 17:56:45 +0200 +Subject: [PATCH] reset: reset-brcmstb: Add Broadcom STB reset controller + driver +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Add driver for the brcm,brcmstb-reset compatible used on RPi 5 by +porting the upstream Linux driver. Assert/deassert functions are adapted +to the U-Boot way of handling individual resets' IDs. + +Signed-off-by: Jan Čermák +--- + drivers/reset/Kconfig | 6 +++ + drivers/reset/Makefile | 1 + + drivers/reset/reset-brcmstb.c | 89 +++++++++++++++++++++++++++++++++++ + 3 files changed, 96 insertions(+) + create mode 100644 drivers/reset/reset-brcmstb.c + +diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig +index fe5c1214f5..10a364b2a8 100644 +--- a/drivers/reset/Kconfig ++++ b/drivers/reset/Kconfig +@@ -63,6 +63,12 @@ config RESET_BCM6345 + help + Support reset controller on BCM6345. + ++config RESET_BRCMSTB ++ bool "Broadcom STB reset controller" ++ help ++ This enables the reset controller driver for Broadcom STB SoCs using ++ a SUN_TOP_CTRL_SW_INIT style controller. ++ + config RESET_UNIPHIER + bool "Reset controller driver for UniPhier SoCs" + depends on ARCH_UNIPHIER +diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile +index 2eb639e4a6..d7e9ac1a88 100644 +--- a/drivers/reset/Makefile ++++ b/drivers/reset/Makefile +@@ -13,6 +13,7 @@ obj-$(CONFIG_TEGRA186_RESET) += tegra186-reset.o + obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o + obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o + obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o ++obj-$(CONFIG_RESET_BRCMSTB) += reset-brcmstb.o + obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o + obj-$(CONFIG_RESET_AST2500) += reset-ast2500.o + obj-$(CONFIG_RESET_AST2600) += reset-ast2600.o +diff --git a/drivers/reset/reset-brcmstb.c b/drivers/reset/reset-brcmstb.c +new file mode 100644 +index 0000000000..c0aef5f124 +--- /dev/null ++++ b/drivers/reset/reset-brcmstb.c +@@ -0,0 +1,89 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Broadcom STB generic reset controller for SW_INIT style reset controller ++ * ++ * Based on upstream Linux driver: ++ * drivers/reset/reset-brcmstb.c ++ * Author: Florian Fainelli ++ * Copyright (C) 2018 Broadcom ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define SW_INIT_SET 0x00 ++#define SW_INIT_CLEAR 0x04 ++#define SW_INIT_STATUS 0x08 ++ ++#define SW_INIT_BIT(id) BIT((id) & 0x1f) ++#define SW_INIT_BANK(id) ((id) >> 5) ++ ++/* A full bank contains extra registers that we are not utilizing but still ++ * qualify as a single bank. ++ */ ++#define SW_INIT_BANK_SIZE 0x18 ++ ++struct brcmstb_reset_priv { ++ void __iomem *base; ++}; ++ ++static int brcmstb_reset_assert(struct reset_ctl *rst) ++{ ++ unsigned int off = SW_INIT_BANK(rst->id) * SW_INIT_BANK_SIZE; ++ struct brcmstb_reset_priv *priv = dev_get_priv(rst->dev); ++ ++ writel_relaxed(SW_INIT_BIT(rst->id), priv->base + off + SW_INIT_SET); ++ ++ return 0; ++} ++ ++static int brcmstb_reset_deassert(struct reset_ctl *rst) ++{ ++ unsigned int off = SW_INIT_BANK(rst->id) * SW_INIT_BANK_SIZE; ++ struct brcmstb_reset_priv *priv = dev_get_priv(rst->dev); ++ ++ writel_relaxed(SW_INIT_BIT(rst->id), priv->base + off + SW_INIT_CLEAR); ++ /* Maximum reset delay after de-asserting a line and seeing block ++ * operation is typically 14us for the worst case, build some slack ++ * here. ++ */ ++ udelay(200); ++ ++ return 0; ++} ++ ++struct reset_ops brcmstb_reset_reset_ops = { ++ .rst_assert = brcmstb_reset_assert, ++ .rst_deassert = brcmstb_reset_deassert, ++}; ++ ++static const struct udevice_id brcmstb_reset_ids[] = { ++ { .compatible = "brcm,brcmstb-reset" }, ++ { /* sentinel */ } ++}; ++ ++static int brcmstb_reset_probe(struct udevice *dev) ++{ ++ struct brcmstb_reset_priv *priv = dev_get_priv(dev); ++ ++ priv->base = dev_remap_addr(dev); ++ if (!priv->base) ++ return -EINVAL; ++ ++ return 0; ++} ++ ++U_BOOT_DRIVER(brcmstb_reset) = { ++ .name = "brcmstb-reset", ++ .id = UCLASS_RESET, ++ .of_match = brcmstb_reset_ids, ++ .ops = &brcmstb_reset_reset_ops, ++ .probe = brcmstb_reset_probe, ++ .priv_auto = sizeof(struct brcmstb_reset_priv), ++}; diff --git a/buildroot-external/board/raspberrypi/patches/uboot/2024.10/0009-reset-reset-brcmstb-rescal-Add-Broadcom-RESCAL-reset.patch b/buildroot-external/board/raspberrypi/patches/uboot/2024.10/0009-reset-reset-brcmstb-rescal-Add-Broadcom-RESCAL-reset.patch new file mode 100644 index 00000000000..35ce4f3cad7 --- /dev/null +++ b/buildroot-external/board/raspberrypi/patches/uboot/2024.10/0009-reset-reset-brcmstb-rescal-Add-Broadcom-RESCAL-reset.patch @@ -0,0 +1,158 @@ +From eb7dd5b1afa4831e6eca2edb2650bd9db9a6d6eb Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Jan=20=C4=8Cerm=C3=A1k?= +Date: Mon, 30 Sep 2024 18:09:29 +0200 +Subject: [PATCH] reset: reset-brcmstb-rescal: Add Broadcom RESCAL reset + controller driver +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Add driver for brcm,bcm7216-pcie-sata-rescal compatible, based on +upstream Linux driver. Unlike most of other reset controllers, RESCAL +takes no reset IDs, so a custom of_xlate function is used that makes the +driver slightly different from the original implementation. + +Signed-off-by: Jan Čermák +--- + drivers/reset/Kconfig | 6 ++ + drivers/reset/Makefile | 1 + + drivers/reset/reset-brcmstb-rescal.c | 101 +++++++++++++++++++++++++++ + 3 files changed, 108 insertions(+) + create mode 100644 drivers/reset/reset-brcmstb-rescal.c + +diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig +index 10a364b2a8..fd1eb05a41 100644 +--- a/drivers/reset/Kconfig ++++ b/drivers/reset/Kconfig +@@ -69,6 +69,12 @@ config RESET_BRCMSTB + This enables the reset controller driver for Broadcom STB SoCs using + a SUN_TOP_CTRL_SW_INIT style controller. + ++config RESET_BRCMSTB_RESCAL ++ bool "Broadcom STB RESCAL reset controller" ++ help ++ This enables the RESCAL reset controller found on BCM2712 and some other ++ Broadcom STB SoCs (BCM7216). ++ + config RESET_UNIPHIER + bool "Reset controller driver for UniPhier SoCs" + depends on ARCH_UNIPHIER +diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile +index d7e9ac1a88..45cf2f1b4d 100644 +--- a/drivers/reset/Makefile ++++ b/drivers/reset/Makefile +@@ -14,6 +14,7 @@ obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o + obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o + obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o + obj-$(CONFIG_RESET_BRCMSTB) += reset-brcmstb.o ++obj-$(CONFIG_RESET_BRCMSTB_RESCAL) += reset-brcmstb-rescal.o + obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o + obj-$(CONFIG_RESET_AST2500) += reset-ast2500.o + obj-$(CONFIG_RESET_AST2600) += reset-ast2600.o +diff --git a/drivers/reset/reset-brcmstb-rescal.c b/drivers/reset/reset-brcmstb-rescal.c +new file mode 100644 +index 0000000000..37096bb9ff +--- /dev/null ++++ b/drivers/reset/reset-brcmstb-rescal.c +@@ -0,0 +1,101 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Broadcom RESCAL reset controller, based on upstream Linux driver: ++ * drivers/reset/reset-brcmstb-rescal.c ++ * ++ * Copyright (C) 2018-2020 Broadcom ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define BRCM_RESCAL_START 0x0 ++#define BRCM_RESCAL_START_BIT BIT(0) ++#define BRCM_RESCAL_CTRL 0x4 ++#define BRCM_RESCAL_STATUS 0x8 ++#define BRCM_RESCAL_STATUS_BIT BIT(0) ++ ++struct brcm_rescal_reset_priv { ++ void __iomem *base; ++}; ++ ++static int brcm_rescal_reset_assert(struct reset_ctl *rst) ++{ ++ return 0; ++} ++ ++static int brcm_rescal_reset_deassert(struct reset_ctl *rst) ++{ ++ struct brcm_rescal_reset_priv *priv = dev_get_priv(rst->dev); ++ u32 reg; ++ int ret; ++ ++ reg = readl(priv->base + BRCM_RESCAL_START); ++ writel(reg | BRCM_RESCAL_START_BIT, priv->base + BRCM_RESCAL_START); ++ reg = readl(priv->base + BRCM_RESCAL_START); ++ if (!(reg & BRCM_RESCAL_START_BIT)) { ++ printf("failed to start SATA/PCIe rescal\n"); ++ return -EIO; ++ } ++ ++ ret = read_poll_timeout(readl, reg, (reg & BRCM_RESCAL_STATUS_BIT), ++ 100, 1000, priv->base + BRCM_RESCAL_STATUS); ++ if (ret) { ++ printf("time out on SATA/PCIe rescal\n"); ++ return ret; ++ } ++ ++ reg = readl(priv->base + BRCM_RESCAL_START); ++ writel(reg & ~BRCM_RESCAL_START_BIT, priv->base + BRCM_RESCAL_START); ++ ++ return ret; ++} ++ ++static int brcm_rescal_reset_of_xlate(struct reset_ctl *reset_ctl, ++ struct ofnode_phandle_args *args) ++{ ++ /* Rescal takes no parameters. */ ++ if (args->args_count != 0) { ++ printf("Invalid args_count: %d\n", args->args_count); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++struct reset_ops brcm_rescal_reset_reset_ops = { ++ .rst_assert = brcm_rescal_reset_assert, ++ .rst_deassert = brcm_rescal_reset_deassert, ++ .of_xlate = brcm_rescal_reset_of_xlate, ++}; ++ ++static const struct udevice_id brcm_rescal_reset_ids[] = { ++ { .compatible = "brcm,bcm7216-pcie-sata-rescal" }, ++ { /* sentinel */ } ++}; ++ ++static int brcm_rescal_reset_probe(struct udevice *dev) ++{ ++ struct brcm_rescal_reset_priv *priv = dev_get_priv(dev); ++ ++ priv->base = dev_remap_addr(dev); ++ if (!priv->base) ++ return -EINVAL; ++ ++ return 0; ++} ++ ++U_BOOT_DRIVER(brcmstb_rescal_reset) = { ++ .name = "brcm-rescal-reset", ++ .id = UCLASS_RESET, ++ .of_match = brcm_rescal_reset_ids, ++ .ops = &brcm_rescal_reset_reset_ops, ++ .probe = brcm_rescal_reset_probe, ++ .priv_auto = sizeof(struct brcm_rescal_reset_priv), ++}; diff --git a/buildroot-external/board/raspberrypi/patches/uboot/2024.10/0010-pci-pcie-brcmstb-Add-basic-support-for-BCM2712-PCIe.patch b/buildroot-external/board/raspberrypi/patches/uboot/2024.10/0010-pci-pcie-brcmstb-Add-basic-support-for-BCM2712-PCIe.patch new file mode 100644 index 00000000000..499c2044288 --- /dev/null +++ b/buildroot-external/board/raspberrypi/patches/uboot/2024.10/0010-pci-pcie-brcmstb-Add-basic-support-for-BCM2712-PCIe.patch @@ -0,0 +1,386 @@ +From 6e16ad9e01d746f78f8a2391dec9aae3f39a96e5 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Jan=20=C4=8Cerm=C3=A1k?= +Date: Mon, 30 Sep 2024 18:13:09 +0200 +Subject: [PATCH] pci: pcie-brcmstb: Add basic support for BCM2712 PCIe +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Add support for BCM2712 (Raspberry Pi 5) by adapting the Raspberry Pi's +dowstream kernel driver. Apart from resets handled by dedicated reset +controllers, there are couple of hacks that were needed to be ported +over from the reference implementation, most notably the function +adjusting the controller's reference clock and the BAR2 config address +remapping. None of these seem to be present in the upstream kernel +driver so eventually it'd be worthwile to check what does +U-Boot/downstream do differently that it's not needed in upstream (and +check that upstream really works with BCM2712 - it's still not merged +yet [1]). + +Methods for handling the resets and address of the relocated hard debug +register are defined in new driver data structures that are implemented +in a similar fashion as in upstream/downstream Linux drivers. + +[1] https://lore.kernel.org/lkml/20240910151845.17308-1-svarbanov@suse.de/ + +Signed-off-by: Jan Čermák +--- + arch/arm/mach-bcm283x/init.c | 10 +- + drivers/pci/pcie_brcmstb.c | 191 +++++++++++++++++++++++++++++++++-- + 2 files changed, 189 insertions(+), 12 deletions(-) + +diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c +index 1b459707bc..2d34d67075 100644 +--- a/arch/arm/mach-bcm283x/init.c ++++ b/arch/arm/mach-bcm283x/init.c +@@ -18,7 +18,7 @@ + #ifdef CONFIG_ARM64 + #include + +-#define MEM_MAP_MAX_ENTRIES (4) ++#define MEM_MAP_MAX_ENTRIES (5) + + static struct mm_region bcm283x_mem_map[MEM_MAP_MAX_ENTRIES] = { + { +@@ -83,6 +83,14 @@ static struct mm_region bcm2712_mem_map[MEM_MAP_MAX_ENTRIES] = { + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN ++ }, { ++ /* PCIe1 memory region */ ++ .virt = 0x1B80000000UL, ++ .phys = 0x1B80000000UL, ++ .size = 0x0000400000UL, ++ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | ++ PTE_BLOCK_NON_SHARE | ++ PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* SoC bus */ + .virt = 0x107c000000UL, +diff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c +index f978c64365..df3e177629 100644 +--- a/drivers/pci/pcie_brcmstb.c ++++ b/drivers/pci/pcie_brcmstb.c +@@ -16,6 +16,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -39,6 +40,10 @@ + #define PCIE_RC_DL_MDIO_WR_DATA 0x1104 + #define PCIE_RC_DL_MDIO_RD_DATA 0x1108 + ++#define PCIE_RC_PL_PHY_CTL_15 0x184c ++#define PCIE_RC_PL_PHY_CTL_15_DIS_PLL_PD_MASK 0x400000 ++#define PCIE_RC_PL_PHY_CTL_15_PM_CLK_PERIOD_MASK 0xff ++ + #define PCIE_MISC_MISC_CTRL 0x4008 + #define MISC_CTRL_SCB_ACCESS_EN_MASK 0x1000 + #define MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000 +@@ -64,6 +69,10 @@ + #define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c + #define RC_BAR3_CONFIG_LO_SIZE_MASK 0x1f + ++#define PCIE_MISC_PCIE_CTRL 0x4064 ++#define PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK 0x1 ++#define PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_MASK 0x4 ++ + #define PCIE_MISC_PCIE_STATUS 0x4068 + #define STATUS_PCIE_PORT_MASK 0x80 + #define STATUS_PCIE_PORT_SHIFT 7 +@@ -89,9 +98,11 @@ + #define PCIE_MEM_WIN0_LIMIT_HI(win) \ + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI + ((win) * 8) + +-#define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204 + #define PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000 + ++#define PCIE_MISC_UBUS_BAR2_CONFIG_REMAP 0x40b4 ++#define PCIE_MISC_UBUS_BAR2_CONFIG_REMAP_ACCESS_ENABLE_MASK BIT(0) ++ + #define PCIE_MSI_INTR2_CLR 0x4508 + #define PCIE_MSI_INTR2_MASK_SET 0x4510 + +@@ -130,6 +141,26 @@ + #define SSC_STATUS_PLL_LOCK_MASK 0x800 + #define SSC_STATUS_PLL_LOCK_SHIFT 11 + ++#define HARD_DEBUG(pcie) ((pcie)->reg_offsets[PCIE_HARD_DEBUG]) ++ ++struct brcm_pcie; ++ ++enum { ++ PCIE_HARD_DEBUG, ++}; ++ ++enum pcie_soc_base { ++ BCM2711, ++ BCM2712, ++}; ++ ++struct pcie_cfg_data { ++ const int *offsets; ++ const enum pcie_soc_base soc_base; ++ int (*perst_set)(struct brcm_pcie *pcie, u32 val); ++ int (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val); ++}; ++ + /** + * struct brcm_pcie - the PCIe controller state + * @base: Base address of memory mapped IO registers of the controller +@@ -140,8 +171,15 @@ + struct brcm_pcie { + void __iomem *base; + ++ const int *reg_offsets; ++ enum pcie_soc_base soc_base; + int gen; + bool ssc; ++ ++ struct reset_ctl *rescal; ++ struct reset_ctl *bridge_reset; ++ int (*perst_set)(struct brcm_pcie *pcie, u32 val); ++ int (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val); + }; + + /** +@@ -367,6 +405,27 @@ static int brcm_pcie_set_ssc(void __iomem *base) + return ssc && pll ? 0 : -EIO; + } + ++static void brcm_pcie_munge_pll(struct brcm_pcie *pcie) ++{ ++ /* Upstream Linux doesn't touch these so maybe there's other way */ ++ ++ u32 tmp; ++ int i; ++ u8 regs[] = { 0x16, 0x17, 0x18, 0x19, 0x1b, 0x1c, 0x1e }; ++ u16 data[] = { 0x50b9, 0xbda1, 0x0094, 0x97b4, 0x5030, 0x5030, 0x0007 }; ++ ++ brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, SET_ADDR_OFFSET, ++ 0x1600); ++ for (i = 0; i < ARRAY_SIZE(regs); i++) { ++ brcm_pcie_mdio_read(pcie->base, MDIO_PORT0, regs[i], &tmp); ++ } ++ for (i = 0; i < ARRAY_SIZE(regs); i++) { ++ brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, regs[i], data[i]); ++ brcm_pcie_mdio_read(pcie->base, MDIO_PORT0, regs[i], &tmp); ++ } ++ udelay(200); ++} ++ + /** + * brcm_pcie_set_gen() - Limits operation to a specific generation (1, 2 or 3) + * @pcie: pointer to the PCIe controller state +@@ -426,6 +485,52 @@ static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie, + writel(tmp, base + PCIE_MEM_WIN0_LIMIT_HI(win)); + } + ++static int brcm_pcie_perst_set_generic(struct brcm_pcie *pcie, u32 val) ++{ ++ if (val) ++ setbits_le32(pcie->base + PCIE_RGR1_SW_INIT_1, RGR1_SW_INIT_1_PERST_MASK); ++ else ++ clrbits_le32(pcie->base + PCIE_RGR1_SW_INIT_1, RGR1_SW_INIT_1_PERST_MASK); ++ ++ return 0; ++} ++ ++static int brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u32 val) ++{ ++ int ret = 0; ++ ++ if (pcie->bridge_reset) { ++ if (val) ++ ret = reset_assert(pcie->bridge_reset); ++ else ++ ret = reset_deassert(pcie->bridge_reset); ++ ++ if (ret) ++ printf("PCIe BRCM: failed to %s bridge reset: err=%d\n", ++ val ? "assert" : "deassert", ret); ++ ++ return ret; ++ } ++ ++ if (val) ++ setbits_le32(pcie->base + PCIE_RGR1_SW_INIT_1, RGR1_SW_INIT_1_INIT_MASK); ++ else ++ clrbits_le32(pcie->base + PCIE_RGR1_SW_INIT_1, RGR1_SW_INIT_1_INIT_MASK); ++ ++ return ret; ++} ++ ++static int brcm_pcie_perst_set_2712(struct brcm_pcie *pcie, u32 val) ++{ ++ /* Perst bit has moved and assert value is 0 */ ++ if (val) ++ clrbits_le32(pcie->base + PCIE_MISC_PCIE_CTRL, PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_MASK); ++ else ++ setbits_le32(pcie->base + PCIE_MISC_PCIE_CTRL, PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_MASK); ++ ++ return 0; ++} ++ + static int brcm_pcie_probe(struct udevice *dev) + { + struct udevice *ctlr = pci_get_controller(dev); +@@ -441,13 +546,17 @@ static int brcm_pcie_probe(struct udevice *dev) + u16 nlw, cls, lnksta; + u32 tmp; + ++ if (pcie->rescal) ++ reset_deassert(pcie->rescal); ++ + /* + * Reset the bridge, assert the fundamental reset. Note for some SoCs, + * e.g. BCM7278, the fundamental reset should not be asserted here. + * This will need to be changed when support for other SoCs is added. + */ +- setbits_le32(base + PCIE_RGR1_SW_INIT_1, +- RGR1_SW_INIT_1_INIT_MASK | RGR1_SW_INIT_1_PERST_MASK); ++ pcie->perst_set(pcie, 1); ++ pcie->bridge_sw_init_set(pcie, 1); ++ + /* + * The delay is a safety precaution to preclude the reset signal + * from looking like a glitch. +@@ -455,14 +564,26 @@ static int brcm_pcie_probe(struct udevice *dev) + udelay(100); + + /* Take the bridge out of reset */ +- clrbits_le32(base + PCIE_RGR1_SW_INIT_1, RGR1_SW_INIT_1_INIT_MASK); ++ pcie->bridge_sw_init_set(pcie, 0); + +- clrbits_le32(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG, ++ clrbits_le32(base + HARD_DEBUG(pcie), + PCIE_HARD_DEBUG_SERDES_IDDQ_MASK); + + /* Wait for SerDes to be stable */ + udelay(100); + ++ if (pcie->soc_base == BCM2712) { ++ /* Hack from RPi downstream, unable to probe without it */ ++ /* Allow a 54MHz (xosc) refclk source */ ++ brcm_pcie_munge_pll(pcie); ++ /* Fix for L1SS errata */ ++ tmp = readl(base + PCIE_RC_PL_PHY_CTL_15); ++ tmp &= ~PCIE_RC_PL_PHY_CTL_15_PM_CLK_PERIOD_MASK; ++ /* PM clock period is 18.52ns (round down) */ ++ tmp |= 0x12; ++ writel(tmp, base + PCIE_RC_PL_PHY_CTL_15); ++ } ++ + /* Set SCB_MAX_BURST_SIZE, CFG_READ_UR_MODE, SCB_ACCESS_EN */ + clrsetbits_le32(base + PCIE_MISC_MISC_CTRL, + MISC_CTRL_MAX_BURST_SIZE_MASK, +@@ -481,6 +602,13 @@ static int brcm_pcie_probe(struct udevice *dev) + writel(upper_32_bits(rc_bar2_offset), + base + PCIE_MISC_RC_BAR2_CONFIG_HI); + ++ if (pcie->soc_base == BCM2712) { ++ /* RPi downstream kernel does do this also for 2711 - is it okay? */ ++ tmp = readl(base + PCIE_MISC_UBUS_BAR2_CONFIG_REMAP); ++ u32p_replace_bits(&tmp, 1, PCIE_MISC_UBUS_BAR2_CONFIG_REMAP_ACCESS_ENABLE_MASK); ++ writel(tmp, base + PCIE_MISC_UBUS_BAR2_CONFIG_REMAP); ++ } ++ + scb_size_val = rc_bar2_size ? + ilog2(rc_bar2_size) - 15 : 0xf; /* 0xf is 1GB */ + +@@ -507,8 +635,7 @@ static int brcm_pcie_probe(struct udevice *dev) + brcm_pcie_set_gen(pcie, pcie->gen); + + /* Unassert the fundamental reset */ +- clrbits_le32(pcie->base + PCIE_RGR1_SW_INIT_1, +- RGR1_SW_INIT_1_PERST_MASK); ++ pcie->perst_set(pcie, 0); + + /* + * Wait for 100ms after PERST# deassertion; see PCIe CEM specification +@@ -595,20 +722,23 @@ static int brcm_pcie_remove(struct udevice *dev) + void __iomem *base = pcie->base; + + /* Assert fundamental reset */ +- setbits_le32(base + PCIE_RGR1_SW_INIT_1, RGR1_SW_INIT_1_PERST_MASK); ++ pcie->perst_set(pcie, 1); + + /* Turn off SerDes */ +- setbits_le32(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG, ++ setbits_le32(base + HARD_DEBUG(pcie), + PCIE_HARD_DEBUG_SERDES_IDDQ_MASK); + + /* Shutdown bridge */ +- setbits_le32(base + PCIE_RGR1_SW_INIT_1, RGR1_SW_INIT_1_INIT_MASK); ++ /* On BCM2712 it will block access to the RESCAL, so don't do it. */ ++ if (pcie->soc_base != BCM2712) ++ pcie->bridge_sw_init_set(pcie, 1); + + return 0; + } + + static int brcm_pcie_of_to_plat(struct udevice *dev) + { ++ const struct pcie_cfg_data *data; + struct brcm_pcie *pcie = dev_get_priv(dev); + ofnode dn = dev_ofnode(dev); + u32 max_link_speed; +@@ -619,6 +749,22 @@ static int brcm_pcie_of_to_plat(struct udevice *dev) + if (!pcie->base) + return -EINVAL; + ++ data = (struct pcie_cfg_data *)dev_get_driver_data(dev); ++ ++ pcie->soc_base = data->soc_base; ++ pcie->reg_offsets = data->offsets; ++ pcie->perst_set = data->perst_set; ++ pcie->bridge_sw_init_set = data->bridge_sw_init_set; ++ ++ pcie->rescal = devm_reset_control_get_optional(dev, "rescal"); ++ if (IS_ERR(pcie->rescal)) { ++ return PTR_ERR(pcie->rescal); ++ } ++ pcie->bridge_reset = devm_reset_control_get_optional(dev, "bridge"); ++ if (IS_ERR(pcie->bridge_reset)) { ++ return PTR_ERR(pcie->bridge_reset); ++ } ++ + pcie->ssc = ofnode_read_bool(dn, "brcm,enable-ssc"); + + ret = ofnode_read_u32(dn, "max-link-speed", &max_link_speed); +@@ -635,8 +781,31 @@ static const struct dm_pci_ops brcm_pcie_ops = { + .write_config = brcm_pcie_write_config, + }; + ++static const int pcie_offsets[] = { ++ [PCIE_HARD_DEBUG] = 0x4204, ++}; ++ ++static const int pcie_offsets_bcm2712[] = { ++ [PCIE_HARD_DEBUG] = 0x4304, ++}; ++ ++static const struct pcie_cfg_data bcm2711_cfg = { ++ .offsets = pcie_offsets, ++ .soc_base = BCM2711, ++ .perst_set = brcm_pcie_perst_set_generic, ++ .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic, ++}; ++ ++static const struct pcie_cfg_data bcm2712_cfg = { ++ .offsets = pcie_offsets_bcm2712, ++ .soc_base = BCM2712, ++ .perst_set = brcm_pcie_perst_set_2712, ++ .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic, ++}; ++ + static const struct udevice_id brcm_pcie_ids[] = { +- { .compatible = "brcm,bcm2711-pcie" }, ++ { .compatible = "brcm,bcm2711-pcie", .data = (ulong)&bcm2711_cfg }, ++ { .compatible = "brcm,bcm2712-pcie", .data = (ulong)&bcm2712_cfg }, + { } + }; + diff --git a/buildroot-external/board/raspberrypi/patches/uboot/2024.10/0011-ARM-bcm2835-add-BCM2712-config-option.patch b/buildroot-external/board/raspberrypi/patches/uboot/2024.10/0011-ARM-bcm2835-add-BCM2712-config-option.patch new file mode 100644 index 00000000000..14050152020 --- /dev/null +++ b/buildroot-external/board/raspberrypi/patches/uboot/2024.10/0011-ARM-bcm2835-add-BCM2712-config-option.patch @@ -0,0 +1,47 @@ +From 61693f4e8db08d263c6036afeecd6d30e7b23660 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Jan=20=C4=8Cerm=C3=A1k?= +Date: Thu, 3 Oct 2024 11:09:53 +0200 +Subject: [PATCH] ARM: bcm2835: add BCM2712 config option +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Add config option for RPi 5's BCM2712, which can only run in 64bit mode. +Also tie the PCIe controller's option to the required reset controllers +if PCI_BRCMSTB is enabled along the BCM2712 option. + +Signed-off-by: Jan Čermák +--- + arch/arm/mach-bcm283x/Kconfig | 5 +++++ + drivers/pci/Kconfig | 2 ++ + 2 files changed, 7 insertions(+) + +diff --git a/arch/arm/mach-bcm283x/Kconfig b/arch/arm/mach-bcm283x/Kconfig +index b3287ce8bc..3b8672cfe0 100644 +--- a/arch/arm/mach-bcm283x/Kconfig ++++ b/arch/arm/mach-bcm283x/Kconfig +@@ -44,6 +44,11 @@ config BCM2711_64B + select BCM2711 + select ARM64 + ++config BCM2712 ++ bool "Broadcom BCM2712 SoC support (64-bit only)" ++ depends on ARCH_BCM283X ++ select ARM64 ++ + menu "Broadcom BCM283X family" + depends on ARCH_BCM283X + +diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig +index 22a56f4ca3..6badc60d13 100644 +--- a/drivers/pci/Kconfig ++++ b/drivers/pci/Kconfig +@@ -386,6 +386,8 @@ config PCIE_DW_ROCKCHIP + config PCI_BRCMSTB + bool "Broadcom STB PCIe controller" + depends on ARCH_BCM283X ++ select RESET_BRCMSTB if BCM2712 ++ select RESET_BRCMSTB_RESCAL if BCM2712 + help + Say Y here if you want to enable support for PCIe controller + on Broadcom set-top-box (STB) SoCs. diff --git a/buildroot-external/board/raspberrypi/patches/uboot/2024.10/0012-pci-pcie-brcmstb-HACK-add-DT-property-for-skipping-d.patch b/buildroot-external/board/raspberrypi/patches/uboot/2024.10/0012-pci-pcie-brcmstb-HACK-add-DT-property-for-skipping-d.patch new file mode 100644 index 00000000000..03e055b2906 --- /dev/null +++ b/buildroot-external/board/raspberrypi/patches/uboot/2024.10/0012-pci-pcie-brcmstb-HACK-add-DT-property-for-skipping-d.patch @@ -0,0 +1,54 @@ +From d613be9ca405b2e65ac03b137cf6351b1aae7154 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Jan=20=C4=8Cerm=C3=A1k?= +Date: Mon, 7 Oct 2024 15:13:40 +0200 +Subject: [PATCH] pci: pcie-brcmstb: HACK - add DT property for skipping device + probe +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +It appears that when pcie2 on RPi 5 is probed by U-Boot, the controller +is not initialized properly and initialization of the RP1 fails when +Linux is loaded. Add u-boot,no-probe boolean parameter that can be added +to the node that doesn't need to be probed in U-Boot now. This would +need to be sorted out when we actually need to control RP1 from U-Boot +but since we only need pcie1 for NVMe now, we can ignore the other +device. + +Signed-off-by: Jan Čermák +--- + drivers/pci/pcie_brcmstb.c | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c +index df3e177629..02d9e7a1b3 100644 +--- a/drivers/pci/pcie_brcmstb.c ++++ b/drivers/pci/pcie_brcmstb.c +@@ -175,6 +175,7 @@ struct brcm_pcie { + enum pcie_soc_base soc_base; + int gen; + bool ssc; ++ bool no_probe; + + struct reset_ctl *rescal; + struct reset_ctl *bridge_reset; +@@ -546,6 +547,11 @@ static int brcm_pcie_probe(struct udevice *dev) + u16 nlw, cls, lnksta; + u32 tmp; + ++ if (pcie->no_probe) { ++ printf("PCIe BRCM: skipping probe\n"); ++ return 0; ++ } ++ + if (pcie->rescal) + reset_deassert(pcie->rescal); + +@@ -766,6 +772,7 @@ static int brcm_pcie_of_to_plat(struct udevice *dev) + } + + pcie->ssc = ofnode_read_bool(dn, "brcm,enable-ssc"); ++ pcie->no_probe = ofnode_read_bool(dn, "u-boot,no-probe"); + + ret = ofnode_read_u32(dn, "max-link-speed", &max_link_speed); + if (ret < 0 || max_link_speed > 4) diff --git a/buildroot-external/board/raspberrypi/yellow/config.txt b/buildroot-external/board/raspberrypi/yellow/config.txt index adf5604e59b..a6a1c708459 100644 --- a/buildroot-external/board/raspberrypi/yellow/config.txt +++ b/buildroot-external/board/raspberrypi/yellow/config.txt @@ -28,6 +28,10 @@ gpu_mem=32 # Additional overlays and parameters are documented /boot/overlays/README -[all] +[cm4] device_tree=bcm2711-rpi-cm4-ha-yellow.dtb +[cm5] +device_tree=bcm2712-rpi-cm5-ha-yellow.dtb + +[all] diff --git a/buildroot-external/board/raspberrypi/yellow/patches/linux/0016-ARM-dts-bcm2712-Add-device-tree-for-CM5-on-HA-Yellow.patch b/buildroot-external/board/raspberrypi/yellow/patches/linux/0016-ARM-dts-bcm2712-Add-device-tree-for-CM5-on-HA-Yellow.patch new file mode 100644 index 00000000000..1627db086bb --- /dev/null +++ b/buildroot-external/board/raspberrypi/yellow/patches/linux/0016-ARM-dts-bcm2712-Add-device-tree-for-CM5-on-HA-Yellow.patch @@ -0,0 +1,1092 @@ +From 15124b1c4c08b408540e020d3f6fdb006ad274cd Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Jan=20=C4=8Cerm=C3=A1k?= +Date: Thu, 3 Oct 2024 13:40:53 +0200 +Subject: [PATCH] ARM: dts: bcm2712: Add device tree for CM5 on HA Yellow + +--- + arch/arm64/boot/dts/broadcom/Makefile | 1 + + .../broadcom/bcm2712-rpi-cm5-ha-yellow.dts | 1063 +++++++++++++++++ + 2 files changed, 1064 insertions(+) + create mode 100644 arch/arm64/boot/dts/broadcom/bcm2712-rpi-cm5-ha-yellow.dts + +diff --git a/arch/arm64/boot/dts/broadcom/Makefile b/arch/arm64/boot/dts/broadcom/Makefile +index 06ae79a9bcfca..89f4e9aa427a2 100644 +--- a/arch/arm64/boot/dts/broadcom/Makefile ++++ b/arch/arm64/boot/dts/broadcom/Makefile +@@ -20,6 +20,7 @@ dtb-$(CONFIG_ARCH_BCM2835) += bcm2710-rpi-3-b-plus.dtb + dtb-$(CONFIG_ARCH_BCM2835) += bcm2710-rpi-cm3.dtb + dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rpi-cm4.dtb + dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rpi-cm4-ha-yellow.dtb ++dtb-$(CONFIG_ARCH_BCM2835) += bcm2712-rpi-cm5-ha-yellow.dtb + dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rpi-cm4s.dtb + dtb-$(CONFIG_ARCH_BCM2835) += bcm2712-rpi-5-b.dtb + dtb-$(CONFIG_ARCH_BCM2835) += bcm2712d0-rpi-5-b.dtb +diff --git a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-cm5-ha-yellow.dts b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-cm5-ha-yellow.dts +new file mode 100644 +index 0000000000000..4b130f42b2358 +--- /dev/null ++++ b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-cm5-ha-yellow.dts +@@ -0,0 +1,1063 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/dts-v1/; ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define i2c0 _i2c0 ++#define i2c3 _i2c3 ++#define i2c4 _i2c4 ++#define i2c5 _i2c5 ++#define i2c6 _i2c6 ++#define i2c8 _i2c8 ++#define i2s _i2s ++#define pwm0 _pwm0 ++#define pwm1 _pwm1 ++#define spi0 _spi0 ++#define spi3 _spi3 ++#define spi4 _spi4 ++#define spi5 _spi5 ++#define spi6 _spi6 ++#define uart0 _uart0 ++#define uart2 _uart2 ++#define uart5 _uart5 ++ ++#include "bcm2712.dtsi" ++ ++#undef i2c0 ++#undef i2c3 ++#undef i2c4 ++#undef i2c5 ++#undef i2c6 ++#undef i2c8 ++#undef i2s ++#undef pwm0 ++#undef pwm1 ++#undef spi0 ++#undef spi3 ++#undef spi4 ++#undef spi5 ++#undef spi6 ++#undef uart0 ++#undef uart2 ++#undef uart3 ++#undef uart4 ++#undef uart5 ++ ++/ { ++ compatible = "raspberrypi,5-compute-module-ha-yellow", "raspberrypi,5-compute-module", "brcm,bcm2712"; ++ model = "Raspberry Pi Compute Module 5 on Home Assistant Yellow"; ++ ++ /* Will be filled by the bootloader */ ++ memory@0 { ++ device_type = "memory"; ++ reg = <0 0 0x28000000>; ++ }; ++ ++ leds: leds { ++ compatible = "gpio-leds"; ++ ++ led_pwr: led-pwr { ++ label = "PWR"; ++ gpios = <&rp1_gpio 44 GPIO_ACTIVE_LOW>; ++ default-state = "off"; ++ linux,default-trigger = "none"; ++ }; ++ ++ led_act: led-act { ++ label = "ACT"; ++ gpios = <&gio_aon 9 GPIO_ACTIVE_LOW>; ++ default-state = "off"; ++ linux,default-trigger = "mmc0"; ++ }; ++ }; ++ ++ sd_io_1v8_reg: sd_io_1v8_reg { ++ compatible = "regulator-gpio"; ++ regulator-name = "vdd-sd-io"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-boot-on; ++ regulator-always-on; ++ regulator-settling-time-us = <5000>; ++ gpios = <&gio_aon 3 GPIO_ACTIVE_HIGH>; ++ states = <1800000 0x1 ++ 3300000 0x0>; ++ status = "okay"; ++ }; ++ ++ sd_vcc_reg: sd_vcc_reg { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc-sd"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-boot-on; ++ enable-active-high; ++ gpios = <&gio_aon 4 GPIO_ACTIVE_HIGH>; ++ status = "okay"; ++ }; ++ ++ wl_on_reg: wl_on_reg { ++ compatible = "regulator-fixed"; ++ regulator-name = "wl-on-regulator"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ pinctrl-0 = <&wl_on_pins>; ++ pinctrl-names = "default"; ++ ++ gpio = <&gio 28 GPIO_ACTIVE_HIGH>; ++ ++ startup-delay-us = <150000>; ++ enable-active-high; ++ }; ++ ++ clocks: clocks { ++ }; ++ ++ cam1_clk: cam1_clk { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ cam0_clk: cam0_clk { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ cam0_reg: cam0_reg { ++ compatible = "regulator-fixed"; ++ regulator-name = "cam0_reg"; ++ enable-active-high; ++ status = "okay"; ++ gpio = <&rp1_gpio 34 0>; // CD0_IO0_MICCLK, to CAM_GPIO on connector ++ }; ++ ++ cam_dummy_reg: cam_dummy_reg { ++ compatible = "regulator-fixed"; ++ regulator-name = "cam-dummy-reg"; ++ status = "okay"; ++ }; ++ ++ dummy: dummy { ++ // A target for unwanted overlay fragments ++ }; ++ ++ ++ // A few extra labels to keep overlays happy ++ ++ i2c0if: i2c0if {}; ++ i2c0mux: i2c0mux {}; ++}; ++ ++rp1_target: &pcie2 { ++ brcm,enable-mps-rcb; ++ brcm,vdm-qos-map = <0xbbaa9888>; ++ aspm-no-l0s; ++ status = "okay"; ++}; ++ ++// Add some labels to 2712 device ++ ++// The system UART ++uart10: &_uart0 { status = "okay"; }; ++ ++// The system SPI for the bootloader EEPROM ++spi10: &_spi0 { status = "okay"; }; ++ ++i2c_rp1boot: &_i2c3 { }; ++ ++#include "rp1.dtsi" ++ ++&rp1 { ++ // PCIe address space layout: ++ // 00_00000000-00_00xxxxxx = RP1 peripherals ++ // 10_00000000-1x_xxxxxxxx = up to 64GB system RAM ++ ++ // outbound access aimed at PCIe 0_00xxxxxx -> RP1 c0_40xxxxxx ++ // This is the RP1 peripheral space ++ ranges = <0xc0 0x40000000 ++ 0x02000000 0x00 0x00000000 ++ 0x00 0x00400000>; ++ ++ dma-ranges = ++ // inbound RP1 1x_xxxxxxxx -> PCIe 1x_xxxxxxxx ++ <0x10 0x00000000 ++ 0x43000000 0x10 0x00000000 ++ 0x10 0x00000000>, ++ ++ // inbound RP1 c0_40xxxxxx -> PCIe 00_00xxxxxx ++ // This allows the RP1 DMA controller to address RP1 hardware ++ <0xc0 0x40000000 ++ 0x02000000 0x0 0x00000000 ++ 0x0 0x00400000>, ++ ++ // inbound RP1 0x_xxxxxxxx -> PCIe 1x_xxxxxxxx ++ <0x00 0x00000000 ++ 0x02000000 0x10 0x00000000 ++ 0x10 0x00000000>; ++}; ++ ++// Expose RP1 nodes as system nodes with labels ++ ++&rp1_dma { ++ status = "okay"; ++}; ++ ++&rp1_eth { ++ status = "okay"; ++ phy-handle = <&phy1>; ++ phy-reset-gpios = <&rp1_gpio 32 GPIO_ACTIVE_LOW>; ++ phy-reset-duration = <5>; ++ ++ phy1: ethernet-phy@1 { ++ reg = <0x1>; ++ brcm,powerdown-enable; ++ interrupt-parent = <&gpio>; ++ interrupts = <37 IRQ_TYPE_LEVEL_LOW>; ++ }; ++}; ++ ++gpio: &rp1_gpio { ++ status = "okay"; ++}; ++ ++aux: &dummy {}; ++ ++&rp1_usb0 { ++ pinctrl-0 = <&usb_vbus_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++}; ++ ++&rp1_usb1 { ++ status = "okay"; ++}; ++ ++#include "bcm2712-rpi.dtsi" ++ ++i2c_csi_dsi0: &i2c6 { // Note: This is for MIPI0 connector only ++ pinctrl-0 = <&rp1_i2c6_38_39>; ++ pinctrl-names = "default"; ++ clock-frequency = <100000>; ++}; ++ ++i2c_csi_dsi1: &i2c0 { // Note: This is for MIPI1 connector ++}; ++ ++i2c_csi_dsi: &i2c_csi_dsi1 { }; // An alias for compatibility ++ ++cam1_reg: &cam0_reg { // Shares CAM_GPIO with cam0_reg ++}; ++ ++csi0: &rp1_csi0 { }; ++csi1: &rp1_csi1 { }; ++dsi0: &rp1_dsi0 { }; ++dsi1: &rp1_dsi1 { }; ++dpi: &rp1_dpi { }; ++vec: &rp1_vec { }; ++dpi_gpio0: &rp1_dpi_24bit_gpio0 { }; ++dpi_gpio1: &rp1_dpi_24bit_gpio2 { }; ++dpi_18bit_cpadhi_gpio0: &rp1_dpi_18bit_cpadhi_gpio0 { }; ++dpi_18bit_cpadhi_gpio2: &rp1_dpi_18bit_cpadhi_gpio2 { }; ++dpi_18bit_gpio0: &rp1_dpi_18bit_gpio0 { }; ++dpi_18bit_gpio2: &rp1_dpi_18bit_gpio2 { }; ++dpi_16bit_cpadhi_gpio0: &rp1_dpi_16bit_cpadhi_gpio0 { }; ++dpi_16bit_cpadhi_gpio2: &rp1_dpi_16bit_cpadhi_gpio2 { }; ++dpi_16bit_gpio0: &rp1_dpi_16bit_gpio0 { }; ++dpi_16bit_gpio2: &rp1_dpi_16bit_gpio2 { }; ++ ++/* Add the IOMMUs for some RP1 bus masters */ ++ ++&csi0 { ++ iommus = <&iommu5>; ++}; ++ ++&csi1 { ++ iommus = <&iommu5>; ++}; ++ ++&dsi0 { ++ iommus = <&iommu5>; ++}; ++ ++&dsi1 { ++ iommus = <&iommu5>; ++}; ++ ++&dpi { ++ iommus = <&iommu5>; ++}; ++ ++&vec { ++ iommus = <&iommu5>; ++}; ++ ++&ddc0 { ++ status = "disabled"; ++}; ++ ++&ddc1 { ++ status = "disabled"; ++}; ++ ++&hdmi0 { ++ clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 0>, <&clk_27MHz>; ++ clock-names = "hdmi", "bvb", "audio", "cec"; ++ status = "disabled"; ++}; ++ ++&hdmi1 { ++ clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 1>, <&clk_27MHz>; ++ clock-names = "hdmi", "bvb", "audio", "cec"; ++ status = "disabled"; ++}; ++ ++&hvs { ++ clocks = <&firmware_clocks 4>, <&firmware_clocks 16>; ++ clock-names = "core", "disp"; ++}; ++ ++&mop { ++ status = "disabled"; ++}; ++ ++&moplet { ++ status = "disabled"; ++}; ++ ++&pixelvalve0 { ++ status = "disabled"; ++}; ++ ++&pixelvalve1 { ++ status = "disabled"; ++}; ++ ++&disp_intr { ++ status = "disabled"; ++}; ++ ++/* SDIO1 is used to drive the eMMC/SD card */ ++&sdio1 { ++ pinctrl-0 = <&emmc_cmddat_pulls>, <&emmc_ds_pull>; ++ pinctrl-names = "default"; ++ vqmmc-supply = <&sd_io_1v8_reg>; ++ vmmc-supply = <&sd_vcc_reg>; ++ bus-width = <8>; ++ sd-uhs-sdr50; ++ sd-uhs-ddr50; ++ sd-uhs-sdr104; ++ mmc-hs200-1_8v; ++ broken-cd; ++ supports-cqe; ++ status = "okay"; ++}; ++ ++&pinctrl_aon { ++ ant_pins: ant_pins { ++ function = "gpio"; ++ pins = "aon_gpio5", "aon_gpio6"; ++ }; ++ ++ /* Slight hack - only one PWM pin (status LED) is usable */ ++ aon_pwm_1pin: aon_pwm_1pin { ++ function = "aon_pwm"; ++ pins = "aon_gpio9"; ++ }; ++}; ++ ++&pinctrl { ++ pwr_button_pins: pwr_button_pins { ++ function = "gpio"; ++ pins = "gpio20"; ++ bias-pull-up; ++ }; ++ ++ wl_on_pins: wl_on_pins { ++ function = "gpio"; ++ pins = "gpio28"; ++ }; ++ ++ bt_shutdown_pins: bt_shutdown_pins { ++ function = "gpio"; ++ pins = "gpio29"; ++ }; ++ ++ emmc_ds_pull: emmc_ds_pull { ++ pins = "emmc_ds"; ++ bias-pull-down; ++ }; ++ ++ emmc_cmddat_pulls: emmc_cmddat_pulls { ++ pins = "emmc_cmd", "emmc_dat0", "emmc_dat1", "emmc_dat2", "emmc_dat3", ++ "emmc_dat4", "emmc_dat5", "emmc_dat6", "emmc_dat7"; ++ bias-pull-up; ++ }; ++}; ++ ++/* uarta communicates with the BT module */ ++&uarta { ++ uart-has-rtscts; ++ auto-flow-control; ++ status = "okay"; ++ clock-frequency = <96000000>; ++ pinctrl-0 = <&uarta_24_pins &bt_shutdown_pins>; ++ pinctrl-names = "default"; ++ ++ bluetooth: bluetooth { ++ compatible = "brcm,bcm43438-bt"; ++ max-speed = <3000000>; ++ shutdown-gpios = <&gio 29 GPIO_ACTIVE_HIGH>; ++ local-bd-address = [ 00 00 00 00 00 00 ]; ++ }; ++}; ++ ++&i2c_rp1boot { ++ clock-frequency = <400000>; ++ pinctrl-0 = <&i2c3_m4_agpio0_pins>; ++ pinctrl-names = "default"; ++}; ++ ++/ { ++ chosen: chosen { ++ bootargs = "reboot=w coherent_pool=1M 8250.nr_uarts=1 pci=pcie_bus_safe"; ++ stdout-path = "serial10:115200n8"; ++ }; ++ ++ fan: cooling_fan { ++ status = "disabled"; ++ compatible = "pwm-fan"; ++ #cooling-cells = <2>; ++ cooling-min-state = <0>; ++ cooling-max-state = <3>; ++ cooling-levels = <0 75 125 175 250>; ++ pwms = <&rp1_pwm1 3 41566 PWM_POLARITY_INVERTED>; ++ rpm-regmap = <&rp1_pwm1>; ++ rpm-offset = <0x3c>; ++ }; ++ ++ pwr_button { ++ compatible = "gpio-keys"; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwr_button_pins>; ++ status = "okay"; ++ ++ pwr_key: pwr { ++ label = "pwr_button"; ++ // linux,code = <205>; // KEY_SUSPEND ++ linux,code = <116>; // KEY_POWER ++ gpios = <&gio 20 GPIO_ACTIVE_LOW>; ++ debounce-interval = <50>; // ms ++ }; ++ }; ++}; ++ ++&usb { ++ power-domains = <&power RPI_POWER_DOMAIN_USB>; ++}; ++ ++/* SDIO2 drives the WLAN interface */ ++&sdio2 { ++ pinctrl-0 = <&sdio2_30_pins>, <&ant_pins>; ++ pinctrl-names = "default"; ++ bus-width = <4>; ++ vmmc-supply = <&wl_on_reg>; ++ sd-uhs-ddr50; ++ non-removable; ++ status = "okay"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ wifi: wifi@1 { ++ reg = <1>; ++ compatible = "brcm,bcm4329-fmac"; ++ local-mac-address = [00 00 00 00 00 00]; ++ }; ++}; ++ ++&rpivid { ++ status = "okay"; ++}; ++ ++&pinctrl { ++ spi10_gpio2: spi10_gpio2 { ++ function = "vc_spi0"; ++ pins = "gpio2", "gpio3", "gpio4"; ++ bias-disable; ++ }; ++ ++ spi10_cs_gpio1: spi10_cs_gpio1 { ++ function = "gpio"; ++ pins = "gpio1"; ++ bias-pull-up; ++ }; ++}; ++ ++spi10_pins: &spi10_gpio2 {}; ++spi10_cs_pins: &spi10_cs_gpio1 {}; ++ ++&spi10 { ++ pinctrl-names = "default"; ++ cs-gpios = <&gio 1 1>; ++ pinctrl-0 = <&spi10_pins &spi10_cs_pins>; ++ ++ spidev10: spidev@0 { ++ compatible = "spidev"; ++ reg = <0>; /* CE0 */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spi-max-frequency = <20000000>; ++ status = "okay"; ++ }; ++}; ++ ++// ============================================= ++// bcm2712-rpi-cm5.dtsi board specific stuff ++ ++&gio_aon { ++ // Don't use GIO_AON as an interrupt controller because it will ++ // clash with the firmware monitoring the PMIC interrupt via the VPU. ++ ++ /delete-property/ interrupt-controller; ++}; ++ ++&main_aon_irq { ++ // Don't use the MAIN_AON_IRQ interrupt controller because it will ++ // clash with the firmware monitoring the PMIC interrupt via the VPU. ++ ++ status = "disabled"; ++}; ++ ++&rp1_pwm1 { ++ status = "disabled"; ++ pinctrl-0 = <&rp1_pwm1_gpio45>; ++ pinctrl-names = "default"; ++}; ++ ++&thermal_trips { ++ cpu_tepid: cpu-tepid { ++ temperature = <50000>; ++ hysteresis = <5000>; ++ type = "active"; ++ }; ++ ++ cpu_warm: cpu-warm { ++ temperature = <60000>; ++ hysteresis = <5000>; ++ type = "active"; ++ }; ++ ++ cpu_hot: cpu-hot { ++ temperature = <67500>; ++ hysteresis = <5000>; ++ type = "active"; ++ }; ++ ++ cpu_vhot: cpu-vhot { ++ temperature = <75000>; ++ hysteresis = <5000>; ++ type = "active"; ++ }; ++}; ++ ++&cooling_maps { ++ tepid { ++ trip = <&cpu_tepid>; ++ cooling-device = <&fan 1 1>; ++ }; ++ ++ warm { ++ trip = <&cpu_warm>; ++ cooling-device = <&fan 2 2>; ++ }; ++ ++ hot { ++ trip = <&cpu_hot>; ++ cooling-device = <&fan 3 3>; ++ }; ++ ++ vhot { ++ trip = <&cpu_vhot>; ++ cooling-device = <&fan 4 4>; ++ }; ++ ++ melt { ++ trip = <&cpu_crit>; ++ cooling-device = <&fan 4 4>; ++ }; ++}; ++ ++&gio { ++ // The GPIOs above 35 are not used on Pi 5, so shrink the upper bank ++ // to reduce the clutter in gpioinfo/pinctrl ++ brcm,gpio-bank-widths = <32 4>; ++ ++ gpio-line-names = ++ "-", // GPIO_000 ++ "2712_BOOT_CS_N", // GPIO_001 ++ "2712_BOOT_MISO", // GPIO_002 ++ "2712_BOOT_MOSI", // GPIO_003 ++ "2712_BOOT_SCLK", // GPIO_004 ++ "-", // GPIO_005 ++ "-", // GPIO_006 ++ "-", // GPIO_007 ++ "-", // GPIO_008 ++ "-", // GPIO_009 ++ "-", // GPIO_010 ++ "-", // GPIO_011 ++ "-", // GPIO_012 ++ "-", // GPIO_013 ++ "-", // GPIO_014 ++ "-", // GPIO_015 ++ "-", // GPIO_016 ++ "-", // GPIO_017 ++ "-", // GPIO_018 ++ "-", // GPIO_019 ++ "PWR_GPIO", // GPIO_020 ++ "2712_G21_FS", // GPIO_021 ++ "-", // GPIO_022 ++ "-", // GPIO_023 ++ "BT_RTS", // GPIO_024 ++ "BT_CTS", // GPIO_025 ++ "BT_TXD", // GPIO_026 ++ "BT_RXD", // GPIO_027 ++ "WL_ON", // GPIO_028 ++ "BT_ON", // GPIO_029 ++ "WIFI_SDIO_CLK", // GPIO_030 ++ "WIFI_SDIO_CMD", // GPIO_031 ++ "WIFI_SDIO_D0", // GPIO_032 ++ "WIFI_SDIO_D1", // GPIO_033 ++ "WIFI_SDIO_D2", // GPIO_034 ++ "WIFI_SDIO_D3"; // GPIO_035 ++}; ++ ++&gio_aon { ++ gpio-line-names = ++ "RP1_SDA", // AON_GPIO_00 ++ "RP1_SCL", // AON_GPIO_01 ++ "RP1_RUN", // AON_GPIO_02 ++ "SD_IOVDD_SEL", // AON_GPIO_03 ++ "SD_PWR_ON", // AON_GPIO_04 ++ "ANT1", // AON_GPIO_05 ++ "ANT2", // AON_GPIO_06 ++ "-", // AON_GPIO_07 ++ "2712_WAKE", // AON_GPIO_08 ++ "2712_STAT_LED", // AON_GPIO_09 ++ "-", // AON_GPIO_10 ++ "-", // AON_GPIO_11 ++ "PMIC_INT", // AON_GPIO_12 ++ "UART_TX_FS", // AON_GPIO_13 ++ "UART_RX_FS", // AON_GPIO_14 ++ "-", // AON_GPIO_15 ++ "-", // AON_GPIO_16 ++ ++ // Pad bank0 out to 32 entries ++ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ++ ++ "HDMI0_SCL", // AON_SGPIO_00 ++ "HDMI0_SDA", // AON_SGPIO_01 ++ "HDMI1_SCL", // AON_SGPIO_02 ++ "HDMI1_SDA", // AON_SGPIO_03 ++ "PMIC_SCL", // AON_SGPIO_04 ++ "PMIC_SDA"; // AON_SGPIO_05 ++ ++ rp1_run_hog { ++ gpio-hog; ++ gpios = <2 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "RP1 RUN pin"; ++ }; ++ ++ ant1: ant1-hog { ++ gpio-hog; ++ gpios = <5 GPIO_ACTIVE_HIGH>; ++ /* internal antenna enabled */ ++ output-high; ++ line-name = "ant1"; ++ }; ++ ++ ant2: ant2-hog { ++ gpio-hog; ++ gpios = <6 GPIO_ACTIVE_HIGH>; ++ /* external antenna disabled */ ++ output-low; ++ line-name = "ant2"; ++ }; ++}; ++ ++&rp1_gpio { ++ gpio-line-names = ++ "ID_SDA", // GPIO0 ++ "ID_SCL", // GPIO1 ++ "GPIO2", // GPIO2 ++ "GPIO3", // GPIO3 ++ "GPIO4", // GPIO4 ++ "GPIO5", // GPIO5 ++ "GPIO6", // GPIO6 ++ "GPIO7", // GPIO7 ++ "GPIO8", // GPIO8 ++ "GPIO9", // GPIO9 ++ "GPIO10", // GPIO10 ++ "GPIO11", // GPIO11 ++ "GPIO12", // GPIO12 ++ "GPIO13", // GPIO13 ++ "GPIO14", // GPIO14 ++ "GPIO15", // GPIO15 ++ "GPIO16", // GPIO16 ++ "GPIO17", // GPIO17 ++ "GPIO18", // GPIO18 ++ "GPIO19", // GPIO19 ++ "GPIO20", // GPIO20 ++ "GPIO21", // GPIO21 ++ "GPIO22", // GPIO22 ++ "GPIO23", // GPIO23 ++ "GPIO24", // GPIO24 ++ "GPIO25", // GPIO25 ++ "GPIO26", // GPIO26 ++ "GPIO27", // GPIO27 ++ ++ "PCIE_PWR_EN", // GPIO28 ++ "FAN_TACH", // GPIO29 ++ "HOST_SDA", // GPIO30 ++ "HOST_SCL", // GPIO31 ++ "ETH_RST_N", // GPIO32 ++ "PCIE_DET_WAKE", // GPIO33 ++ ++ "CD0_IO0_MICCLK", // GPIO34 ++ "CD0_IO0_MICDAT0", // GPIO35 ++ "RP1_PCIE_CLKREQ_N", // GPIO36 ++ "ETH_IRQ_N", // GPIO37 ++ "SDA0", // GPIO38 ++ "SCL0", // GPIO39 ++ "-", // GPIO40 ++ "-", // GPIO41 ++ "USB_VBUS_EN", // GPIO42 ++ "USB_OC_N", // GPIO43 ++ "RP1_STAT_LED", // GPIO44 ++ "FAN_PWM", // GPIO45 ++ "-", // GPIO46 ++ "2712_WAKE", // GPIO47 ++ "-", // GPIO48 ++ "-", // GPIO49 ++ "-", // GPIO50 ++ "-", // GPIO51 ++ "-", // GPIO52 ++ "-"; // GPIO53 ++ ++ usb_vbus_pins: usb_vbus_pins { ++ function = "vbus1"; ++ pins = "gpio42", "gpio43"; ++ }; ++}; ++ ++// ============================================= ++// BCM2712D0 overrides ++ ++&gio_aon { ++ brcm,gpio-bank-widths = <15 6>; ++}; ++ ++&pinctrl { ++ compatible = "brcm,bcm2712d0-pinctrl"; ++ reg = <0x7d504100 0x20>; ++}; ++ ++&pinctrl_aon { ++ compatible = "brcm,bcm2712d0-aon-pinctrl"; ++ reg = <0x7d510700 0x1c>; ++}; ++ ++&vc4 { ++ compatible = "brcm,bcm2712d0-vc6"; ++}; ++ ++&uart10 { ++ interrupts = ; ++}; ++ ++&spi10 { ++ dmas = <&dma40 3>, <&dma40 4>; ++}; ++ ++&hdmi0 { ++ dmas = <&dma40 (12|(1<<30)|(1<<24)|(10<<16)|(15<<20))>; ++}; ++ ++&hdmi1 { ++ dmas = <&dma40 (13|(1<<30)|(1<<24)|(10<<16)|(15<<20))>; ++}; ++ ++// ============================================= ++// HA Yellow Board-specific stuff ++ ++/ { ++ chosen: chosen { ++ bootargs = "coherent_pool=1M 8250.nr_uarts=1 snd_bcm2835.enable_headphones=0"; ++ stdout-path = "serial2:115200n8"; ++ }; ++ ++ keys: gpio-keys { ++ compatible = "gpio-keys"; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&gpio_button_pins>; ++ ++ status = "okay"; ++ ++ power { ++ label = "Blue Button"; ++ linux,code = ; ++ gpios = <&rp1_gpio 26 GPIO_ACTIVE_LOW>; ++ debounce-interval = <100>; // ms ++ }; ++ ++ user { ++ label = "Red Button"; ++ linux,code = ; ++ gpios = <&rp1_gpio 27 GPIO_ACTIVE_LOW>; ++ debounce-interval = <100>; // ms ++ }; ++ }; ++}; ++ ++/* Always enable the NVMe slot. */ ++&pcie1 { ++ status = "okay"; ++}; ++ ++/* Avoid probing pcie2 in U-Boot for now, it breaks RP1. */ ++&rp1_target { ++ u-boot,no-probe; ++}; ++ ++/* ++ * Skip init of debug UART to fix garbled U-Boot output, it's not explicitly ++ * skipped in BCM2712 device tree like in BCM2711's ones. ++ */ ++&uart10 { ++ skip-init; ++}; ++ ++/* RP1 USB ports are not connected on Yellow. */ ++&rp1_usb0 { ++ status = "disabled"; ++}; ++ ++&rp1_usb1 { ++ status = "disabled"; ++}; ++ ++&leds { ++ led_act: led-act { ++ label = "act"; ++ default-state = "off"; ++ linux,default-trigger = "activity"; ++ gpios = <&gio_aon 9 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ led_pwr: led-pwr { ++ label = "pwr"; ++ default-state = "off"; ++ linux,default-trigger = "default-on"; ++ gpios = <&rp1_gpio 44 GPIO_ACTIVE_LOW>; ++ }; ++ ++ led_usr: led-usr { ++ label = "usr"; ++ linux,default-trigger = "heartbeat"; ++ default-state = "off"; ++ panic-indicator; ++ gpios = <&rp1_gpio 38 GPIO_ACTIVE_LOW>; ++ }; ++}; ++ ++&gpio { ++ gpio_button_pins: gpio_button_pins { ++ function = "gpio"; ++ pins = "gpio26", "gpio27"; ++ bias-pull-up; ++ }; ++}; ++ ++/* UART on pin header */ ++&uart0 { ++ status = "okay"; ++ pinctrl-0 = <&rp1_uart0_14_15>; ++}; ++ ++/* UART for Zigbee */ ++&uart3 { ++ status = "okay"; ++ pinctrl-0 = <&rp1_uart3_8_9 &rp1_uart3_ctsrts_10_11>; ++ uart-has-rtscts; ++}; ++ ++/* UART for USB console */ ++&uart4 { ++ status = "okay"; ++ pinctrl-0 = <&rp1_uart4_12_13>; ++}; ++ ++&usb { ++ compatible = "brcm,bcm2835-usb"; ++ dr_mode = "host"; ++ g-np-tx-fifo-size = <32>; ++ g-rx-fifo-size = <558>; ++ g-tx-fifo-size = <512 512 512 512 512 256 256>; ++ status = "okay"; ++}; ++ ++/* I2C pins on pin header */ ++&i2c1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&rp1_i2c1_2_3>; ++ clock-frequency = <100000>; ++}; ++ ++/* Board-level I2C (RTC and I2S audio) */ ++&rp1_i2c3 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&rp1_i2c3_22_23>; ++ status = "okay"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ card_codec: pcm5121@4c { ++ #sound-dai-cells = <0>; ++ compatible = "ti,pcm5121"; ++ reg = <0x4c>; ++ AVDD-supply = <&vdd_3v3_reg>; ++ DVDD-supply = <&vdd_3v3_reg>; ++ CPVDD-supply = <&vdd_3v3_reg>; ++ status = "okay"; ++ }; ++ ++ pcf85063a: rtc@51 { ++ compatible = "nxp,pcf85063a"; ++ reg = <0x51>; ++ }; ++}; ++ ++&rp1_i2s0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&rp1_i2s0_18_21>; ++ status = "okay"; ++}; ++ ++&sound { ++ compatible = "simple-audio-card"; ++ simple-audio-card,format = "i2s"; ++ simple-audio-card,name = "pcm5121-sound"; ++ status = "okay"; ++ ++ simple-audio-card,cpu { ++ sound-dai = <&rp1_i2s0>; ++ }; ++ ++ dailink0_slave: simple-audio-card,codec { ++ sound-dai = <&card_codec>; ++ }; ++}; ++ ++/ { ++ aliases: aliases { ++ blconfig = &blconfig; ++ blpubkey = &blpubkey; ++ bluetooth = &bluetooth; ++ console = &uart10; ++ ethernet0 = &rp1_eth; ++ wifi0 = &wifi; ++ fb = &fb; ++ mailbox = &mailbox; ++ mmc0 = &sdio1; ++ uart10 = &uart10; ++ serial0 = &uart0; ++ serial1 = &uart3; ++ serial2 = &uart4; ++ serial10 = &uart10; ++ i2c = &i2c_arm; ++ i2c0 = &i2c0; ++ i2c1 = &i2c1; ++ i2c2 = &i2c2; ++ i2c3 = &i2c3; ++ i2c4 = &i2c4; ++ i2c5 = &i2c5; ++ i2c6 = &i2c6; ++ i2c10 = &i2c_rp1boot; ++ // Bit-bashed i2c_gpios start at 10 ++ spi0 = &spi0; ++ spi1 = &spi1; ++ spi2 = &spi2; ++ spi3 = &spi3; ++ spi4 = &spi4; ++ spi5 = &spi5; ++ spi10 = &spi10; ++ gpio0 = &gpio; ++ gpio1 = &gio; ++ gpio2 = &gio_aon; ++ gpio3 = &pinctrl; ++ gpio4 = &pinctrl_aon; ++ usb0 = &rp1_usb0; ++ usb1 = &rp1_usb1; ++ drm-dsi1 = &dsi0; ++ drm-dsi2 = &dsi1; ++ }; ++ ++ __overrides__ { ++ bdaddr = <&bluetooth>, "local-bd-address["; ++ button_debounce = <&pwr_key>, "debounce-interval:0"; ++ uart0_console = <&uart0>,"status", <&aliases>, "console=",&uart0; ++ i2c1 = <&i2c1>, "status"; ++ i2c = <&i2c1>, "status"; ++ i2c_arm = <&i2c_arm>, "status"; ++ i2c_vc = <&i2c_vc>, "status"; ++ i2c_csi_dsi = <&i2c_csi_dsi>, "status"; ++ i2c_csi_dsi0 = <&i2c_csi_dsi0>, "status"; ++ i2c_csi_dsi1 = <&i2c_csi_dsi1>, "status"; ++ i2c1_baudrate = <&i2c1>, "clock-frequency:0"; ++ i2c_baudrate = <&i2c_arm>, "clock-frequency:0"; ++ i2c_arm_baudrate = <&i2c_arm>, "clock-frequency:0"; ++ i2c_vc_baudrate = <&i2c_vc>, "clock-frequency:0"; ++ krnbt = <&bluetooth>, "status"; ++ nvme = <&pciex1>, "status"; ++ pciex1 = <&pciex1>, "status"; ++ pciex1_gen = <&pciex1> , "max-link-speed:0"; ++ pciex1_no_l0s = <&pciex1>, "aspm-no-l0s?"; ++ pciex1_tperst_clk_ms = <&pciex1>, "brcm,tperst-clk-ms:0"; ++ pcie_tperst_clk_ms = <&pciex1>, "brcm,tperst-clk-ms:0"; ++ random = <&random>, "status"; ++ spi = <&spi0>, "status"; ++ suspend = <&pwr_key>, "linux,code:0=205"; ++ uart0 = <&uart0>, "status"; ++ wifiaddr = <&wifi>, "local-mac-address["; ++ ++ act_led_activelow = <&led_act>, "active-low?"; ++ act_led_trigger = <&led_act>, "linux,default-trigger"; ++ pwr_led_activelow = <&led_pwr>, "gpios:8"; ++ pwr_led_trigger = <&led_pwr>, "linux,default-trigger"; ++ usr_led_trigger = <&led_usr>, "linux,default-trigger"; ++ eth_led0 = <&phy1>,"led-modes:0"; ++ eth_led1 = <&phy1>,"led-modes:4"; ++ ++ ant1 = <&ant1>,"output-high?=on", ++ <&ant1>, "output-low?=off", ++ <&ant2>, "output-high?=off", ++ <&ant2>, "output-low?=on"; ++ ant2 = <&ant1>,"output-high?=off", ++ <&ant1>, "output-low?=on", ++ <&ant2>, "output-high?=on", ++ <&ant2>, "output-low?=off"; ++ noant = <&ant1>,"output-high?=off", ++ <&ant1>, "output-low?=on", ++ <&ant2>, "output-high?=off", ++ <&ant2>, "output-low?=on"; ++ }; ++}; diff --git a/buildroot-external/board/raspberrypi/yellow/patches/linux/0017-ARM-dts-bcm2712-yellow-Sync-sdio1-and-sd_io_1v8_reg-.patch b/buildroot-external/board/raspberrypi/yellow/patches/linux/0017-ARM-dts-bcm2712-yellow-Sync-sdio1-and-sd_io_1v8_reg-.patch new file mode 100644 index 00000000000..c01aaddf795 --- /dev/null +++ b/buildroot-external/board/raspberrypi/yellow/patches/linux/0017-ARM-dts-bcm2712-yellow-Sync-sdio1-and-sd_io_1v8_reg-.patch @@ -0,0 +1,50 @@ +From e29e2cfad33afa692f2f727f492dab02d5ff3948 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Jan=20=C4=8Cerm=C3=A1k?= +Date: Thu, 21 Nov 2024 14:26:20 +0100 +Subject: [PATCH] ARM: dts: bcm2712: yellow: Sync sdio1 and sd_io_1v8_reg nodes + with CM5 DTS +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +SDIO1 and its 1V8 regulator have been changed in vanilla CM5 device tree, +reflect those changes in Yellow's DTS. + +Signed-off-by: Jan Čermák +--- + .../boot/dts/broadcom/bcm2712-rpi-cm5-ha-yellow.dts | 12 ++++-------- + 1 file changed, 4 insertions(+), 8 deletions(-) + +diff --git a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-cm5-ha-yellow.dts b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-cm5-ha-yellow.dts +index 4b130f42b2358..c85d608da2043 100644 +--- a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-cm5-ha-yellow.dts ++++ b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-cm5-ha-yellow.dts +@@ -78,17 +78,11 @@ led_act: led-act { + }; + + sd_io_1v8_reg: sd_io_1v8_reg { +- compatible = "regulator-gpio"; ++ compatible = "regulator-fixed"; + regulator-name = "vdd-sd-io"; + regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; ++ regulator-max-microvolt = <1800000>; + regulator-always-on; +- regulator-settling-time-us = <5000>; +- gpios = <&gio_aon 3 GPIO_ACTIVE_HIGH>; +- states = <1800000 0x1 +- 3300000 0x0>; +- status = "okay"; + }; + + sd_vcc_reg: sd_vcc_reg { +@@ -355,6 +349,8 @@ &sdio1 { + sd-uhs-ddr50; + sd-uhs-sdr104; + mmc-hs200-1_8v; ++ mmc-hs400-1_8v; ++ mmc-hs400-enhanced-strobe; + broken-cd; + supports-cqe; + status = "okay"; diff --git a/buildroot-external/board/raspberrypi/yellow/patches/linux/0018-ARM-dts-bcm2712-yellow-Disable-SD-SDIO-modes-on-eMMC.patch b/buildroot-external/board/raspberrypi/yellow/patches/linux/0018-ARM-dts-bcm2712-yellow-Disable-SD-SDIO-modes-on-eMMC.patch new file mode 100644 index 00000000000..44bdad9f354 --- /dev/null +++ b/buildroot-external/board/raspberrypi/yellow/patches/linux/0018-ARM-dts-bcm2712-yellow-Disable-SD-SDIO-modes-on-eMMC.patch @@ -0,0 +1,44 @@ +From 9639a7a0f20cbd4a7b9968f6a3ede4727d96d297 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Jan=20=C4=8Cerm=C3=A1k?= +Date: Thu, 28 Nov 2024 18:05:55 +0100 +Subject: [PATCH] ARM: dts: bcm2712: yellow: Disable SD/SDIO modes on eMMC + interface +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +If the eMMC card is not initialized properly (probably a side-effect of its +usage in U-Boot), every command sent to it takes over 10 seconds before +timeout. With SD and SDIO modes not disabled in the device tree, it takes up +over 130 seconds before the card is reset. Disabling these two modes reduces +this by 100 seconds. + +While this is added as a partial workaround for the issue, disabling these mode +should make no harm anyway. + +Signed-off-by: Jan Čermák +--- + .../boot/dts/broadcom/bcm2712-rpi-cm5-ha-yellow.dts | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +diff --git a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-cm5-ha-yellow.dts b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-cm5-ha-yellow.dts +index c85d608da2043..189c17fe2028e 100644 +--- a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-cm5-ha-yellow.dts ++++ b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-cm5-ha-yellow.dts +@@ -851,6 +851,16 @@ &rp1_usb1 { + status = "disabled"; + }; + ++/* ++ * Yellow doesn't need to use eMMC interface as SD/SDIO, disable those ++ * modes to speed up boot. This is particularly handy to work around ++ * an issue with eMMC initialization but won't harm in general. ++ */ ++&sdio1 { ++ no-sdio; ++ no-sd; ++}; ++ + &leds { + led_act: led-act { + label = "act"; diff --git a/buildroot-external/board/raspberrypi/yellow/patches/linux/0019-ARM-dts-bcm2712-yellow-Disable-CQE-on-eMMC-interface.patch b/buildroot-external/board/raspberrypi/yellow/patches/linux/0019-ARM-dts-bcm2712-yellow-Disable-CQE-on-eMMC-interface.patch new file mode 100644 index 00000000000..581f4481cd8 --- /dev/null +++ b/buildroot-external/board/raspberrypi/yellow/patches/linux/0019-ARM-dts-bcm2712-yellow-Disable-CQE-on-eMMC-interface.patch @@ -0,0 +1,50 @@ +From 0d9aed86fbaf650cf15ea0977e05cee2980ed054 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Jan=20=C4=8Cerm=C3=A1k?= +Date: Mon, 2 Dec 2024 16:07:00 +0100 +Subject: [PATCH] ARM: dts: bcm2712: yellow: Disable CQE on eMMC interface +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Testing shows that enabling CQE causes random hangs on I/O operations, often +during the swap boostrapping on the first boot: + +[ 242.826099] Tainted: G C 6.6.51-haos-raspi #54 +[ 242.832463] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message. +[ 242.840429] INFO: task jbd2/mmcblk0p7-:300 blocked for more than 120 seconds. +[ 242.847572] Tainted: G C 6.6.51-haos-raspi #54 +[ 242.853928] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message. +[ 242.861789] INFO: task jbd2/mmcblk0p8-:344 blocked for more than 120 seconds. +[ 242.868926] Tainted: G C 6.6.51-haos-raspi #54 +[ 242.875277] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message. +[ 242.883149] INFO: task systemd-timesyn:569 blocked for more than 120 seconds. +[ 242.890282] Tainted: G C 6.6.51-haos-raspi #54 +[ 242.896628] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message. +[ 242.904522] INFO: task dockerd:606 blocked for more than 120 seconds. +[ 242.910958] Tainted: G C 6.6.51-haos-raspi #54 +[ 242.917304] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message. +[ 242.925200] INFO: task runc:[2:INIT]:1504 blocked for more than 120 seconds. +[ 242.932249] Tainted: G C 6.6.51-haos-raspi #54 +[ 242.938595] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message. + +This is a known issue currently for some SD cards but it hasn't been +acknowledged for eMMC yet. By removing the CQE capability, the issue seems to +go away. + +Signed-off-by: Jan Čermák +--- + arch/arm64/boot/dts/broadcom/bcm2712-rpi-cm5-ha-yellow.dts | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-cm5-ha-yellow.dts b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-cm5-ha-yellow.dts +index 189c17fe2028e..469d0fdc971a8 100644 +--- a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-cm5-ha-yellow.dts ++++ b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-cm5-ha-yellow.dts +@@ -352,7 +352,6 @@ &sdio1 { + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + broken-cd; +- supports-cqe; + status = "okay"; + }; + diff --git a/buildroot-external/board/raspberrypi/yellow/patches/linux/0020-ARM-dts-bcm2712-yellow-Disable-rpi_rtc.patch b/buildroot-external/board/raspberrypi/yellow/patches/linux/0020-ARM-dts-bcm2712-yellow-Disable-rpi_rtc.patch new file mode 100644 index 00000000000..777fdb81aa9 --- /dev/null +++ b/buildroot-external/board/raspberrypi/yellow/patches/linux/0020-ARM-dts-bcm2712-yellow-Disable-rpi_rtc.patch @@ -0,0 +1,32 @@ +From fc558b6a7174e2b5c37936dd8c13ca29e9273472 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Jan=20=C4=8Cerm=C3=A1k?= +Date: Mon, 2 Dec 2024 17:22:04 +0100 +Subject: [PATCH] ARM: dts: bcm2712: yellow: Disable rpi_rtc +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Yellow has its own I2C RTC and there is no way to power the new peripheral on +CM5. + +Signed-off-by: Jan Čermák +--- + arch/arm64/boot/dts/broadcom/bcm2712-rpi-cm5-ha-yellow.dts | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-cm5-ha-yellow.dts b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-cm5-ha-yellow.dts +index 469d0fdc971a8..ebdeef5f89881 100644 +--- a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-cm5-ha-yellow.dts ++++ b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-cm5-ha-yellow.dts +@@ -927,6 +927,11 @@ &i2c1 { + clock-frequency = <100000>; + }; + ++/* No way to power CM5's VBAT pin on Yellow, disable its RTC. */ ++&rpi_rtc { ++ status = "disabled"; ++}; ++ + /* Board-level I2C (RTC and I2S audio) */ + &rp1_i2c3 { + pinctrl-names = "default"; diff --git a/buildroot-external/board/raspberrypi/yellow/uboot.config b/buildroot-external/board/raspberrypi/yellow/uboot.config index e0bb378d5c6..9330745e055 100644 --- a/buildroot-external/board/raspberrypi/yellow/uboot.config +++ b/buildroot-external/board/raspberrypi/yellow/uboot.config @@ -1,5 +1,22 @@ +CONFIG_TARGET_RPI_4=y +CONFIG_BCM2712=y + +CONFIG_MMC_SDHCI_BCMSTB=y + +CONFIG_DM_USB_GADGET=y + +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USB_GADGET_DOWNLOAD=y + CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_CMD_LED=y + +# CONFIG_EFI_LOADER is not set +# CONFIG_TOOLS_MKEFICAPSULE is not set diff --git a/buildroot-external/configs/generic_aarch64_defconfig b/buildroot-external/configs/generic_aarch64_defconfig index 4c86e83e819..30b84126e41 100644 --- a/buildroot-external/configs/generic_aarch64_defconfig +++ b/buildroot-external/configs/generic_aarch64_defconfig @@ -16,7 +16,7 @@ BR2_ROOTFS_POST_IMAGE_SCRIPT="$(BR2_EXTERNAL_HASSOS_PATH)/scripts/post-image.sh" BR2_ROOTFS_POST_SCRIPT_ARGS="$(BR2_EXTERNAL_HASSOS_PATH)/board/arm-uefi/generic-aarch64 $(BR2_EXTERNAL_HASSOS_PATH)/board/arm-uefi/generic-aarch64/hassos-hook.sh" BR2_LINUX_KERNEL=y BR2_LINUX_KERNEL_CUSTOM_VERSION=y -BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="6.6.54" +BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="6.6.63" BR2_LINUX_KERNEL_USE_ARCH_DEFAULT_CONFIG=y BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/hassos.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/docker.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/device-support.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/device-support-wireless.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/device-support-wireless-pci.config $(BR2_EXTERNAL_HASSOS_PATH)/board/arm-uefi/generic-aarch64/kernel.config" BR2_LINUX_KERNEL_LZ4=y @@ -69,6 +69,7 @@ BR2_PACKAGE_LINUX_FIRMWARE_IWLWIFI_8000C=y BR2_PACKAGE_LINUX_FIRMWARE_IWLWIFI_8265=y BR2_PACKAGE_LINUX_FIRMWARE_IWLWIFI_9XXX=y BR2_PACKAGE_LINUX_FIRMWARE_IWLWIFI_6E=y +BR2_PACKAGE_LINUX_FIRMWARE_IWLWIFI_GL=y BR2_PACKAGE_LINUX_FIRMWARE_MWIFIEX_SD8787=y BR2_PACKAGE_LINUX_FIRMWARE_MWIFIEX_SD8797=y BR2_PACKAGE_LINUX_FIRMWARE_MWIFIEX_USB8797=y diff --git a/buildroot-external/configs/generic_x86_64_defconfig b/buildroot-external/configs/generic_x86_64_defconfig index bff4bf6a6a9..3c55948dfb7 100644 --- a/buildroot-external/configs/generic_x86_64_defconfig +++ b/buildroot-external/configs/generic_x86_64_defconfig @@ -16,7 +16,7 @@ BR2_ROOTFS_POST_IMAGE_SCRIPT="$(BR2_EXTERNAL_HASSOS_PATH)/scripts/post-image.sh" BR2_ROOTFS_POST_SCRIPT_ARGS="$(BR2_EXTERNAL_HASSOS_PATH)/board/pc/generic-x86-64 $(BR2_EXTERNAL_HASSOS_PATH)/board/pc/generic-x86-64/hassos-hook.sh" BR2_LINUX_KERNEL=y BR2_LINUX_KERNEL_CUSTOM_VERSION=y -BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="6.6.54" +BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="6.6.63" BR2_LINUX_KERNEL_DEFCONFIG="x86_64" BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/hassos.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/docker.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/device-support.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/device-support-wireless.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/device-support-wireless-pci.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/device-support-pci.config $(BR2_EXTERNAL_HASSOS_PATH)/board/pc/generic-x86-64/kernel.config" BR2_LINUX_KERNEL_LZ4=y @@ -71,6 +71,7 @@ BR2_PACKAGE_LINUX_FIRMWARE_IWLWIFI_8000C=y BR2_PACKAGE_LINUX_FIRMWARE_IWLWIFI_8265=y BR2_PACKAGE_LINUX_FIRMWARE_IWLWIFI_9XXX=y BR2_PACKAGE_LINUX_FIRMWARE_IWLWIFI_6E=y +BR2_PACKAGE_LINUX_FIRMWARE_IWLWIFI_GL=y BR2_PACKAGE_LINUX_FIRMWARE_MWIFIEX_SD8787=y BR2_PACKAGE_LINUX_FIRMWARE_MWIFIEX_SD8797=y BR2_PACKAGE_LINUX_FIRMWARE_MWIFIEX_USB8797=y diff --git a/buildroot-external/configs/green_defconfig b/buildroot-external/configs/green_defconfig index c6a5a24240e..b7f227e207c 100755 --- a/buildroot-external/configs/green_defconfig +++ b/buildroot-external/configs/green_defconfig @@ -16,7 +16,7 @@ BR2_ROOTFS_POST_IMAGE_SCRIPT="$(BR2_EXTERNAL_HASSOS_PATH)/scripts/post-image.sh" BR2_ROOTFS_POST_SCRIPT_ARGS="$(BR2_EXTERNAL_HASSOS_PATH)/board/nabucasa/green $(BR2_EXTERNAL_HASSOS_PATH)/board/nabucasa/green/hassos-hook.sh" BR2_LINUX_KERNEL=y BR2_LINUX_KERNEL_CUSTOM_VERSION=y -BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="6.6.54" +BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="6.6.63" BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/kernel-arm64-rockchip.config" BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/hassos.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/docker.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/device-support.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/device-support-wireless.config $(BR2_EXTERNAL_HASSOS_PATH)/board/nabucasa/green/kernel.config" diff --git a/buildroot-external/configs/khadas_vim3_defconfig b/buildroot-external/configs/khadas_vim3_defconfig index 9e013b6f8b9..5111150d959 100644 --- a/buildroot-external/configs/khadas_vim3_defconfig +++ b/buildroot-external/configs/khadas_vim3_defconfig @@ -16,7 +16,7 @@ BR2_ROOTFS_POST_IMAGE_SCRIPT="$(BR2_EXTERNAL_HASSOS_PATH)/scripts/post-image.sh" BR2_ROOTFS_POST_SCRIPT_ARGS="$(BR2_EXTERNAL_HASSOS_PATH)/board/khadas/vim3 $(BR2_EXTERNAL_HASSOS_PATH)/board/khadas/vim3/hassos-hook.sh" BR2_LINUX_KERNEL=y BR2_LINUX_KERNEL_CUSTOM_VERSION=y -BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="6.6.54" +BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="6.6.63" BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_EXTERNAL_HASSOS_PATH)/board/khadas/kernel-vim.config" BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/hassos.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/docker.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/device-support.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/device-support-wireless.config" diff --git a/buildroot-external/configs/odroid_c2_defconfig b/buildroot-external/configs/odroid_c2_defconfig index fc1084ecc40..7bb67cb25c8 100644 --- a/buildroot-external/configs/odroid_c2_defconfig +++ b/buildroot-external/configs/odroid_c2_defconfig @@ -16,7 +16,7 @@ BR2_ROOTFS_POST_IMAGE_SCRIPT="$(BR2_EXTERNAL_HASSOS_PATH)/scripts/post-image.sh" BR2_ROOTFS_POST_SCRIPT_ARGS="$(BR2_EXTERNAL_HASSOS_PATH)/board/hardkernel/odroid-c2 $(BR2_EXTERNAL_HASSOS_PATH)/board/hardkernel/odroid-c2/hassos-hook.sh" BR2_LINUX_KERNEL=y BR2_LINUX_KERNEL_CUSTOM_VERSION=y -BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="6.6.54" +BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="6.6.63" BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_EXTERNAL_HASSOS_PATH)/board/hardkernel/kernel-amlogic.config" BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/hassos.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/docker.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/device-support.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/device-support-wireless.config" diff --git a/buildroot-external/configs/odroid_c4_defconfig b/buildroot-external/configs/odroid_c4_defconfig index fd8cb4c0f76..f4568ab1d8e 100644 --- a/buildroot-external/configs/odroid_c4_defconfig +++ b/buildroot-external/configs/odroid_c4_defconfig @@ -16,7 +16,7 @@ BR2_ROOTFS_POST_IMAGE_SCRIPT="$(BR2_EXTERNAL_HASSOS_PATH)/scripts/post-image.sh" BR2_ROOTFS_POST_SCRIPT_ARGS="$(BR2_EXTERNAL_HASSOS_PATH)/board/hardkernel/odroid-c4 $(BR2_EXTERNAL_HASSOS_PATH)/board/hardkernel/odroid-c4/hassos-hook.sh" BR2_LINUX_KERNEL=y BR2_LINUX_KERNEL_CUSTOM_VERSION=y -BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="6.6.54" +BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="6.6.63" BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_EXTERNAL_HASSOS_PATH)/board/hardkernel/kernel-amlogic.config" BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/hassos.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/docker.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/device-support.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/device-support-wireless.config" diff --git a/buildroot-external/configs/odroid_m1_defconfig b/buildroot-external/configs/odroid_m1_defconfig index 5592ef84002..65cabb6fae7 100644 --- a/buildroot-external/configs/odroid_m1_defconfig +++ b/buildroot-external/configs/odroid_m1_defconfig @@ -16,7 +16,7 @@ BR2_ROOTFS_POST_IMAGE_SCRIPT="$(BR2_EXTERNAL_HASSOS_PATH)/scripts/post-image.sh" BR2_ROOTFS_POST_SCRIPT_ARGS="$(BR2_EXTERNAL_HASSOS_PATH)/board/hardkernel/odroid-m1 $(BR2_EXTERNAL_HASSOS_PATH)/board/hardkernel/odroid-m1/hassos-hook.sh" BR2_LINUX_KERNEL=y BR2_LINUX_KERNEL_CUSTOM_VERSION=y -BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="6.6.54" +BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="6.6.63" BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/kernel-arm64-rockchip.config" BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/hassos.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/docker.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/device-support.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/device-support-wireless.config $(BR2_EXTERNAL_HASSOS_PATH)/board/hardkernel/odroid-m1/kernel.config" diff --git a/buildroot-external/configs/odroid_m1s_defconfig b/buildroot-external/configs/odroid_m1s_defconfig index 0a801f40b83..be3f465d72f 100644 --- a/buildroot-external/configs/odroid_m1s_defconfig +++ b/buildroot-external/configs/odroid_m1s_defconfig @@ -16,7 +16,7 @@ BR2_ROOTFS_POST_IMAGE_SCRIPT="$(BR2_EXTERNAL_HASSOS_PATH)/scripts/post-image.sh" BR2_ROOTFS_POST_SCRIPT_ARGS="$(BR2_EXTERNAL_HASSOS_PATH)/board/hardkernel/odroid-m1s $(BR2_EXTERNAL_HASSOS_PATH)/board/hardkernel/odroid-m1s/hassos-hook.sh" BR2_LINUX_KERNEL=y BR2_LINUX_KERNEL_CUSTOM_VERSION=y -BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="6.6.54" +BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="6.6.63" BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/kernel-arm64-rockchip.config" BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/hassos.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/docker.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/device-support.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/device-support-wireless.config $(BR2_EXTERNAL_HASSOS_PATH)/board/hardkernel/odroid-m1s/kernel.config" diff --git a/buildroot-external/configs/odroid_n2_defconfig b/buildroot-external/configs/odroid_n2_defconfig index 680d6c9e242..1235ea55050 100644 --- a/buildroot-external/configs/odroid_n2_defconfig +++ b/buildroot-external/configs/odroid_n2_defconfig @@ -16,7 +16,7 @@ BR2_ROOTFS_POST_IMAGE_SCRIPT="$(BR2_EXTERNAL_HASSOS_PATH)/scripts/post-image.sh" BR2_ROOTFS_POST_SCRIPT_ARGS="$(BR2_EXTERNAL_HASSOS_PATH)/board/hardkernel/odroid-n2 $(BR2_EXTERNAL_HASSOS_PATH)/board/hardkernel/odroid-n2/hassos-hook.sh" BR2_LINUX_KERNEL=y BR2_LINUX_KERNEL_CUSTOM_VERSION=y -BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="6.6.54" +BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="6.6.63" BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_EXTERNAL_HASSOS_PATH)/board/hardkernel/kernel-amlogic.config" BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/hassos.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/docker.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/device-support.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/device-support-wireless.config $(BR2_EXTERNAL_HASSOS_PATH)/board/hardkernel/odroid-n2/kernel.config" diff --git a/buildroot-external/configs/odroid_xu4_defconfig b/buildroot-external/configs/odroid_xu4_defconfig index 49b072ef294..3816fde18a8 100644 --- a/buildroot-external/configs/odroid_xu4_defconfig +++ b/buildroot-external/configs/odroid_xu4_defconfig @@ -17,7 +17,7 @@ BR2_ROOTFS_POST_IMAGE_SCRIPT="$(BR2_EXTERNAL_HASSOS_PATH)/scripts/post-image.sh" BR2_ROOTFS_POST_SCRIPT_ARGS="$(BR2_EXTERNAL_HASSOS_PATH)/board/hardkernel/odroid-xu4 $(BR2_EXTERNAL_HASSOS_PATH)/board/hardkernel/odroid-xu4/hassos-hook.sh" BR2_LINUX_KERNEL=y BR2_LINUX_KERNEL_CUSTOM_VERSION=y -BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="6.6.54" +BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="6.6.63" BR2_LINUX_KERNEL_DEFCONFIG="exynos" BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/hassos.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/docker.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/device-support.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/device-support-wireless.config $(BR2_EXTERNAL_HASSOS_PATH)/board/hardkernel/odroid-xu4/kernel.config" BR2_LINUX_KERNEL_LZ4=y diff --git a/buildroot-external/configs/ova_defconfig b/buildroot-external/configs/ova_defconfig index 9a4fc0eeefc..5734e5c781b 100644 --- a/buildroot-external/configs/ova_defconfig +++ b/buildroot-external/configs/ova_defconfig @@ -16,7 +16,7 @@ BR2_ROOTFS_POST_IMAGE_SCRIPT="$(BR2_EXTERNAL_HASSOS_PATH)/scripts/post-image.sh" BR2_ROOTFS_POST_SCRIPT_ARGS="$(BR2_EXTERNAL_HASSOS_PATH)/board/pc/ova $(BR2_EXTERNAL_HASSOS_PATH)/board/pc/ova/hassos-hook.sh" BR2_LINUX_KERNEL=y BR2_LINUX_KERNEL_CUSTOM_VERSION=y -BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="6.6.54" +BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="6.6.63" BR2_LINUX_KERNEL_DEFCONFIG="x86_64" BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/hassos.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/docker.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/device-support.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/device-support-pci.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/device-support-wireless.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/device-support-wireless-pci.config $(BR2_EXTERNAL_HASSOS_PATH)/board/pc/ova/kernel.config" BR2_LINUX_KERNEL_LZ4=y @@ -73,6 +73,7 @@ BR2_PACKAGE_LINUX_FIRMWARE_IWLWIFI_8000C=y BR2_PACKAGE_LINUX_FIRMWARE_IWLWIFI_8265=y BR2_PACKAGE_LINUX_FIRMWARE_IWLWIFI_9XXX=y BR2_PACKAGE_LINUX_FIRMWARE_IWLWIFI_6E=y +BR2_PACKAGE_LINUX_FIRMWARE_IWLWIFI_GL=y BR2_PACKAGE_LINUX_FIRMWARE_MWIFIEX_SD8787=y BR2_PACKAGE_LINUX_FIRMWARE_MWIFIEX_SD8797=y BR2_PACKAGE_LINUX_FIRMWARE_MWIFIEX_USB8797=y diff --git a/buildroot-external/configs/rpi2_defconfig b/buildroot-external/configs/rpi2_defconfig index 13d1f87ceff..3b0a636ecc5 100644 --- a/buildroot-external/configs/rpi2_defconfig +++ b/buildroot-external/configs/rpi2_defconfig @@ -18,7 +18,7 @@ BR2_ROOTFS_POST_IMAGE_SCRIPT="$(BR2_EXTERNAL_HASSOS_PATH)/scripts/post-image.sh" BR2_ROOTFS_POST_SCRIPT_ARGS="$(BR2_EXTERNAL_HASSOS_PATH)/board/raspberrypi/rpi2 $(BR2_EXTERNAL_HASSOS_PATH)/board/raspberrypi/hassos-hook.sh" BR2_LINUX_KERNEL=y BR2_LINUX_KERNEL_CUSTOM_TARBALL=y -BR2_LINUX_KERNEL_CUSTOM_TARBALL_LOCATION="https://github.com/raspberrypi/linux/archive/stable_20240529.tar.gz" +BR2_LINUX_KERNEL_CUSTOM_TARBALL_LOCATION="https://github.com/raspberrypi/linux/archive/stable_20241008.tar.gz" BR2_LINUX_KERNEL_DEFCONFIG="bcm2709" BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/hassos.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/docker.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/device-support.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/device-support-wireless.config $(BR2_EXTERNAL_HASSOS_PATH)/board/raspberrypi/kernel.config $(BR2_EXTERNAL_HASSOS_PATH)/board/raspberrypi/kernel-armv7.config" BR2_LINUX_KERNEL_LZ4=y diff --git a/buildroot-external/configs/rpi3_64_defconfig b/buildroot-external/configs/rpi3_64_defconfig index 1b01e19513f..3309a434fda 100644 --- a/buildroot-external/configs/rpi3_64_defconfig +++ b/buildroot-external/configs/rpi3_64_defconfig @@ -17,7 +17,7 @@ BR2_ROOTFS_POST_IMAGE_SCRIPT="$(BR2_EXTERNAL_HASSOS_PATH)/scripts/post-image.sh" BR2_ROOTFS_POST_SCRIPT_ARGS="$(BR2_EXTERNAL_HASSOS_PATH)/board/raspberrypi/rpi3-64 $(BR2_EXTERNAL_HASSOS_PATH)/board/raspberrypi/hassos-hook.sh" BR2_LINUX_KERNEL=y BR2_LINUX_KERNEL_CUSTOM_TARBALL=y -BR2_LINUX_KERNEL_CUSTOM_TARBALL_LOCATION="https://github.com/raspberrypi/linux/archive/stable_20240529.tar.gz" +BR2_LINUX_KERNEL_CUSTOM_TARBALL_LOCATION="https://github.com/raspberrypi/linux/archive/stable_20241008.tar.gz" BR2_LINUX_KERNEL_DEFCONFIG="bcmrpi3" BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/hassos.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/docker.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/device-support.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/device-support-wireless.config $(BR2_EXTERNAL_HASSOS_PATH)/board/raspberrypi/kernel.config" BR2_LINUX_KERNEL_LZ4=y diff --git a/buildroot-external/configs/rpi3_defconfig b/buildroot-external/configs/rpi3_defconfig index 7074e8c66e3..49217883f56 100644 --- a/buildroot-external/configs/rpi3_defconfig +++ b/buildroot-external/configs/rpi3_defconfig @@ -18,7 +18,7 @@ BR2_ROOTFS_POST_IMAGE_SCRIPT="$(BR2_EXTERNAL_HASSOS_PATH)/scripts/post-image.sh" BR2_ROOTFS_POST_SCRIPT_ARGS="$(BR2_EXTERNAL_HASSOS_PATH)/board/raspberrypi/rpi3 $(BR2_EXTERNAL_HASSOS_PATH)/board/raspberrypi/hassos-hook.sh" BR2_LINUX_KERNEL=y BR2_LINUX_KERNEL_CUSTOM_TARBALL=y -BR2_LINUX_KERNEL_CUSTOM_TARBALL_LOCATION="https://github.com/raspberrypi/linux/archive/stable_20240529.tar.gz" +BR2_LINUX_KERNEL_CUSTOM_TARBALL_LOCATION="https://github.com/raspberrypi/linux/archive/stable_20241008.tar.gz" BR2_LINUX_KERNEL_DEFCONFIG="bcm2709" BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/hassos.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/docker.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/device-support.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/device-support-wireless.config $(BR2_EXTERNAL_HASSOS_PATH)/board/raspberrypi/kernel.config $(BR2_EXTERNAL_HASSOS_PATH)/board/raspberrypi/kernel-armv7.config" BR2_LINUX_KERNEL_LZ4=y diff --git a/buildroot-external/configs/rpi4_64_defconfig b/buildroot-external/configs/rpi4_64_defconfig index 52130dbcaca..b4347b90df5 100644 --- a/buildroot-external/configs/rpi4_64_defconfig +++ b/buildroot-external/configs/rpi4_64_defconfig @@ -17,7 +17,7 @@ BR2_ROOTFS_POST_IMAGE_SCRIPT="$(BR2_EXTERNAL_HASSOS_PATH)/scripts/post-image.sh" BR2_ROOTFS_POST_SCRIPT_ARGS="$(BR2_EXTERNAL_HASSOS_PATH)/board/raspberrypi/rpi4-64 $(BR2_EXTERNAL_HASSOS_PATH)/board/raspberrypi/hassos-hook.sh" BR2_LINUX_KERNEL=y BR2_LINUX_KERNEL_CUSTOM_TARBALL=y -BR2_LINUX_KERNEL_CUSTOM_TARBALL_LOCATION="https://github.com/raspberrypi/linux/archive/stable_20240529.tar.gz" +BR2_LINUX_KERNEL_CUSTOM_TARBALL_LOCATION="https://github.com/raspberrypi/linux/archive/stable_20241008.tar.gz" BR2_LINUX_KERNEL_DEFCONFIG="bcm2711" BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/hassos.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/docker.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/device-support.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/device-support-pci.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/device-support-wireless.config $(BR2_EXTERNAL_HASSOS_PATH)/board/raspberrypi/kernel.config" BR2_LINUX_KERNEL_LZ4=y diff --git a/buildroot-external/configs/rpi4_defconfig b/buildroot-external/configs/rpi4_defconfig index 9d3fcb3454b..d3161002c89 100644 --- a/buildroot-external/configs/rpi4_defconfig +++ b/buildroot-external/configs/rpi4_defconfig @@ -18,7 +18,7 @@ BR2_ROOTFS_POST_IMAGE_SCRIPT="$(BR2_EXTERNAL_HASSOS_PATH)/scripts/post-image.sh" BR2_ROOTFS_POST_SCRIPT_ARGS="$(BR2_EXTERNAL_HASSOS_PATH)/board/raspberrypi/rpi4 $(BR2_EXTERNAL_HASSOS_PATH)/board/raspberrypi/hassos-hook.sh" BR2_LINUX_KERNEL=y BR2_LINUX_KERNEL_CUSTOM_TARBALL=y -BR2_LINUX_KERNEL_CUSTOM_TARBALL_LOCATION="https://github.com/raspberrypi/linux/archive/stable_20240529.tar.gz" +BR2_LINUX_KERNEL_CUSTOM_TARBALL_LOCATION="https://github.com/raspberrypi/linux/archive/stable_20241008.tar.gz" BR2_LINUX_KERNEL_DEFCONFIG="bcm2711" BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/hassos.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/docker.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/device-support.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/device-support-pci.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/device-support-wireless.config $(BR2_EXTERNAL_HASSOS_PATH)/board/raspberrypi/kernel.config $(BR2_EXTERNAL_HASSOS_PATH)/board/raspberrypi/kernel-armv7.config" BR2_LINUX_KERNEL_LZ4=y diff --git a/buildroot-external/configs/rpi5_64_defconfig b/buildroot-external/configs/rpi5_64_defconfig index 40072f8523d..5f0e6197a6d 100644 --- a/buildroot-external/configs/rpi5_64_defconfig +++ b/buildroot-external/configs/rpi5_64_defconfig @@ -17,7 +17,7 @@ BR2_ROOTFS_POST_IMAGE_SCRIPT="$(BR2_EXTERNAL_HASSOS_PATH)/scripts/post-image.sh" BR2_ROOTFS_POST_SCRIPT_ARGS="$(BR2_EXTERNAL_HASSOS_PATH)/board/raspberrypi/rpi5-64 $(BR2_EXTERNAL_HASSOS_PATH)/board/raspberrypi/rpi5-64/hassos-hook.sh" BR2_LINUX_KERNEL=y BR2_LINUX_KERNEL_CUSTOM_TARBALL=y -BR2_LINUX_KERNEL_CUSTOM_TARBALL_LOCATION="https://github.com/raspberrypi/linux/archive/stable_20240529.tar.gz" +BR2_LINUX_KERNEL_CUSTOM_TARBALL_LOCATION="https://github.com/raspberrypi/linux/archive/stable_20241008.tar.gz" BR2_LINUX_KERNEL_DEFCONFIG="bcm2712" BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/hassos.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/docker.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/device-support.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/device-support-pci.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/device-support-wireless.config $(BR2_EXTERNAL_HASSOS_PATH)/board/raspberrypi/kernel.config" BR2_LINUX_KERNEL_LZ4=y @@ -143,6 +143,7 @@ BR2_PACKAGE_HOST_GPTFDISK=y BR2_PACKAGE_HOST_MTOOLS=y BR2_PACKAGE_HOST_RAUC=y BR2_PACKAGE_GASKET=y +BR2_PACKAGE_HAILO8_FIRMWARE=y BR2_PACKAGE_HASSIO=y BR2_PACKAGE_HASSIO_ARCH="aarch64" BR2_PACKAGE_HASSIO_MACHINE="raspberrypi5-64" diff --git a/buildroot-external/configs/tinker_defconfig b/buildroot-external/configs/tinker_defconfig index ac44322710c..f84db4fd314 100644 --- a/buildroot-external/configs/tinker_defconfig +++ b/buildroot-external/configs/tinker_defconfig @@ -18,7 +18,7 @@ BR2_ROOTFS_POST_IMAGE_SCRIPT="$(BR2_EXTERNAL_HASSOS_PATH)/scripts/post-image.sh" BR2_ROOTFS_POST_SCRIPT_ARGS="$(BR2_EXTERNAL_HASSOS_PATH)/board/asus/tinker $(BR2_EXTERNAL_HASSOS_PATH)/board/asus/hassos-hook.sh" BR2_LINUX_KERNEL=y BR2_LINUX_KERNEL_CUSTOM_VERSION=y -BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="6.6.54" +BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="6.6.63" BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_EXTERNAL_HASSOS_PATH)/board/asus/tinker/kernel.config" BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/hassos.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/docker.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/device-support.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/device-support-wireless.config" diff --git a/buildroot-external/configs/yellow_defconfig b/buildroot-external/configs/yellow_defconfig index 7d2776916a3..f96893b47d1 100644 --- a/buildroot-external/configs/yellow_defconfig +++ b/buildroot-external/configs/yellow_defconfig @@ -17,12 +17,12 @@ BR2_ROOTFS_POST_IMAGE_SCRIPT="$(BR2_EXTERNAL_HASSOS_PATH)/scripts/post-image.sh" BR2_ROOTFS_POST_SCRIPT_ARGS="$(BR2_EXTERNAL_HASSOS_PATH)/board/raspberrypi/yellow $(BR2_EXTERNAL_HASSOS_PATH)/board/raspberrypi/hassos-hook.sh" BR2_LINUX_KERNEL=y BR2_LINUX_KERNEL_CUSTOM_TARBALL=y -BR2_LINUX_KERNEL_CUSTOM_TARBALL_LOCATION="https://github.com/raspberrypi/linux/archive/stable_20240529.tar.gz" +BR2_LINUX_KERNEL_CUSTOM_TARBALL_LOCATION="https://github.com/raspberrypi/linux/archive/stable_20241008.tar.gz" BR2_LINUX_KERNEL_DEFCONFIG="bcm2711" BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/hassos.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/docker.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/device-support.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/device-support-pci.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/device-support-wireless.config $(BR2_EXTERNAL_HASSOS_PATH)/board/raspberrypi/kernel.config" BR2_LINUX_KERNEL_LZ4=y BR2_LINUX_KERNEL_DTS_SUPPORT=y -BR2_LINUX_KERNEL_INTREE_DTS_NAME="broadcom/bcm2711-rpi-cm4-ha-yellow" +BR2_LINUX_KERNEL_INTREE_DTS_NAME="broadcom/bcm2711-rpi-cm4-ha-yellow broadcom/bcm2712-rpi-cm5-ha-yellow" BR2_LINUX_KERNEL_DTB_OVERLAY_SUPPORT=y BR2_LINUX_KERNEL_NEEDS_HOST_OPENSSL=y BR2_LINUX_KERNEL_NEEDS_HOST_LIBELF=y @@ -143,8 +143,8 @@ BR2_TARGET_ROOTFS_EROFS_PCLUSTERSIZE=262144 BR2_TARGET_UBOOT=y BR2_TARGET_UBOOT_BUILD_SYSTEM_KCONFIG=y BR2_TARGET_UBOOT_CUSTOM_VERSION=y -BR2_TARGET_UBOOT_CUSTOM_VERSION_VALUE="2024.01" -BR2_TARGET_UBOOT_BOARD_DEFCONFIG="rpi_4" +BR2_TARGET_UBOOT_CUSTOM_VERSION_VALUE="2024.10" +BR2_TARGET_UBOOT_BOARD_DEFCONFIG="rpi_arm64" BR2_TARGET_UBOOT_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_HASSOS_PATH)/bootloader/uboot.config $(BR2_EXTERNAL_HASSOS_PATH)/board/raspberrypi/uboot.config $(BR2_EXTERNAL_HASSOS_PATH)/board/raspberrypi/yellow/uboot.config" BR2_PACKAGE_HOST_DOSFSTOOLS=y BR2_PACKAGE_HOST_E2FSPROGS=y diff --git a/buildroot-external/kernel/v6.6.y/device-support.config b/buildroot-external/kernel/v6.6.y/device-support.config index 1794644fa58..d3e925ec447 100644 --- a/buildroot-external/kernel/v6.6.y/device-support.config +++ b/buildroot-external/kernel/v6.6.y/device-support.config @@ -13,6 +13,7 @@ CONFIG_USB_SERIAL_GENERIC=y CONFIG_USB_SERIAL_OPTION=m CONFIG_USB_SERIAL_SIMPLE=m CONFIG_USB_SERIAL_CP210X=m +CONFIG_USB_SERIAL_CYPRESS_M8=m CONFIG_USB_SERIAL_FTDI_SIO=m CONFIG_USB_SERIAL_PL2303=m CONFIG_USB_SERIAL_CH341=m diff --git a/buildroot-external/kernel/v6.6.y/kernel-arm64-rockchip.config b/buildroot-external/kernel/v6.6.y/kernel-arm64-rockchip.config index e528945a745..8effd5732d2 100644 --- a/buildroot-external/kernel/v6.6.y/kernel-arm64-rockchip.config +++ b/buildroot-external/kernel/v6.6.y/kernel-arm64-rockchip.config @@ -3119,7 +3119,6 @@ CONFIG_USB_SERIAL_CH341=m CONFIG_USB_SERIAL_WHITEHEAT=m CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m CONFIG_USB_SERIAL_CP210X=m -CONFIG_USB_SERIAL_CYPRESS_M8=m CONFIG_USB_SERIAL_EMPEG=m CONFIG_USB_SERIAL_FTDI_SIO=m CONFIG_USB_SERIAL_VISOR=m diff --git a/buildroot-external/meta b/buildroot-external/meta index 9abe6b8872b..f3ebd91f644 100644 --- a/buildroot-external/meta +++ b/buildroot-external/meta @@ -1,5 +1,5 @@ -VERSION_MAJOR="13" -VERSION_MINOR="2" +VERSION_MAJOR="14" +VERSION_MINOR="0" VERSION_SUFFIX="" HASSOS_NAME="Home Assistant OS" diff --git a/buildroot-external/ota/manifest.raucm.gtpl b/buildroot-external/ota/manifest.raucm.gtpl index dff6e29edf1..932257961b8 100644 --- a/buildroot-external/ota/manifest.raucm.gtpl +++ b/buildroot-external/ota/manifest.raucm.gtpl @@ -15,8 +15,7 @@ hooks=install; [image.kernel] filename=kernel.img -{{- $bootloader := (env "BOOTLOADER") }} -{{- if or (eq $bootloader "grub") (eq $bootloader "tryboot") }} +{{- if eq (env "BOOTLOADER") "tryboot" }} hooks=post-install; {{- end }} diff --git a/buildroot-external/ota/rauc-hook b/buildroot-external/ota/rauc-hook index 7f1717716bc..f366d5c7e1e 100755 --- a/buildroot-external/ota/rauc-hook +++ b/buildroot-external/ota/rauc-hook @@ -42,6 +42,16 @@ install_boot() { cp -f "${BOOT_TMP}"/*.txt "${BOOT_MNT}/" || true cp -f "${BOOT_TMP}"/grubenv "${BOOT_MNT}"/EFI/BOOT/ || true fi + + # Add CM5 support for Yellow. Can be removed in HAOS 15. + if [ "$RAUC_SYSTEM_COMPATIBLE" = "haos-yellow" ]; then + if ! grep -q "\[cm5\]" "${BOOT_MNT}/config.txt"; then + echo "Adding CM5 config to config.txt" + + # Remove old single device_tree config and add CM-specific ones + sed -i '/device_tree=bcm2711-rpi-cm4-ha-yellow.dtb/d; s/\[all\]/\[cm4\]\ndevice_tree=bcm2711-rpi-cm4-ha-yellow.dtb\n\n\[cm5\]\ndevice_tree=bcm2712-rpi-cm5-ha-yellow.dtb\n\n\[all\]/' "${BOOT_MNT}/config.txt" + fi + fi } install_spl() { @@ -125,6 +135,9 @@ case "$1" in fi ;; slot-post-install) + if [ "${RAUC_SLOT_CLASS}" = "boot" ]; then + post_install_boot + fi if [ "${RAUC_SLOT_CLASS}" = "kernel" ]; then post_install_kernel fi diff --git a/buildroot-external/package/hailo8-firmware/Config.in b/buildroot-external/package/hailo8-firmware/Config.in new file mode 100644 index 00000000000..841f660f639 --- /dev/null +++ b/buildroot-external/package/hailo8-firmware/Config.in @@ -0,0 +1,6 @@ +config BR2_PACKAGE_HAILO8_FIRMWARE + bool "Hailo-8 Firmware" + help + Firmware for Hailo-8 PCIe device found e.g. on Raspberry Pi AI + Kit and Raspberry Pi AI HAT+. Requires the hailo kernel driver + (included in Raspberry Pi's downstream kernel). diff --git a/buildroot-external/package/hailo8-firmware/hailo8-firmware.hash b/buildroot-external/package/hailo8-firmware/hailo8-firmware.hash new file mode 100644 index 00000000000..4e5aa204155 --- /dev/null +++ b/buildroot-external/package/hailo8-firmware/hailo8-firmware.hash @@ -0,0 +1 @@ +sha256 bfa576dd782359d74cabcb19e87c3a934dce03dea0785e41f86fecc9a687a92b hailo8_fw.4.18.0.bin diff --git a/buildroot-external/package/hailo8-firmware/hailo8-firmware.mk b/buildroot-external/package/hailo8-firmware/hailo8-firmware.mk new file mode 100644 index 00000000000..2b8688d8501 --- /dev/null +++ b/buildroot-external/package/hailo8-firmware/hailo8-firmware.mk @@ -0,0 +1,25 @@ +################################################################################ +# +# Hailo-8 Firmware +# +################################################################################ + +HAILO8_FIRMWARE_VERSION = 4.18.0 +HAILO8_FIRMWARE_LICENSE = PROPRIETARY +HAILO8_FIRMWARE_SOURCE= hailo8_fw.$(HAILO8_FIRMWARE_VERSION).bin +HAILO8_FIRMWARE_SITE="https://hailo-hailort.s3.eu-west-2.amazonaws.com/Hailo8/$(HAILO8_FIRMWARE_VERSION)/FW" + +define HAILO8_FIRMWARE_EXTRACT_CMDS + cp $(HAILO8_FIRMWARE_DL_DIR)/$(HAILO8_FIRMWARE_SOURCE) $(@D) +endef + +define HAILO8_FIRMWARE_BUILD_CMDS + cp $(@D)/$(HAILO8_FIRMWARE_SOURCE) $(@D)/hailo8_fw.bin +endef + +define HAILO8_FIRMWARE_INSTALL_TARGET_CMDS + $(INSTALL) -d $(TARGET_DIR)/lib/firmware/hailo + $(INSTALL) -m 0644 $(@D)/hailo8_fw.bin $(TARGET_DIR)/lib/firmware/hailo/ +endef + +$(eval $(generic-package)) diff --git a/buildroot-external/package/hassio/Config.in b/buildroot-external/package/hassio/Config.in index f7a6a84c294..7f802015e3f 100644 --- a/buildroot-external/package/hassio/Config.in +++ b/buildroot-external/package/hassio/Config.in @@ -18,4 +18,27 @@ config BR2_PACKAGE_HASSIO_MACHINE help Machine to pull containers for (used for landing page). +choice + prompt "Default Channel" + default BR2_PACKAGE_HASSIO_CHANNEL_STABLE + help + Channel to use by default. + +config BR2_PACKAGE_HASSIO_CHANNEL_STABLE + bool "Stable" + help + Stable channel. + +config BR2_PACKAGE_HASSIO_CHANNEL_BETA + bool "Beta" + help + Beta channel. + +config BR2_PACKAGE_HASSIO_CHANNEL_DEV + bool "Dev" + help + Dev channel. + +endchoice + endif diff --git a/buildroot-external/package/hassio/create-data-partition.sh b/buildroot-external/package/hassio/create-data-partition.sh index aa272486e3f..97ac0259372 100755 --- a/buildroot-external/package/hassio/create-data-partition.sh +++ b/buildroot-external/package/hassio/create-data-partition.sh @@ -3,6 +3,7 @@ set -e build_dir=$1 dst_dir=$2 +channel=$3 data_img="${dst_dir}/data.ext4" @@ -24,7 +25,7 @@ container=$(docker run --privileged -e DOCKER_TLS_CERTDIR="" \ -v "${build_dir}":/build \ -d docker:27.2-dind --storage-driver overlay2) -docker exec "${container}" sh /build/dind-import-containers.sh +docker exec "${container}" sh /build/dind-import-containers.sh "${channel}" docker stop "${container}" diff --git a/buildroot-external/package/hassio/dind-import-containers.sh b/buildroot-external/package/hassio/dind-import-containers.sh index 639d421e48f..019e83e2a10 100755 --- a/buildroot-external/package/hassio/dind-import-containers.sh +++ b/buildroot-external/package/hassio/dind-import-containers.sh @@ -1,6 +1,8 @@ #!/bin/sh set -e +channel=$1 + APPARMOR_URL="https://version.home-assistant.io/apparmor.txt" # Make sure we can talk to the Docker daemon @@ -27,3 +29,5 @@ docker tag "${supervisor}" "ghcr.io/home-assistant/${arch}-hassio-supervisor:lat # Setup AppArmor mkdir -p "/data/supervisor/apparmor" wget -O "/data/supervisor/apparmor/hassio-supervisor" "${APPARMOR_URL}" + +echo "{ \"channel\": \"${channel}\" }" > /data/supervisor/updater.json diff --git a/buildroot-external/package/hassio/hassio.mk b/buildroot-external/package/hassio/hassio.mk index 317107d840b..423be2d17d7 100644 --- a/buildroot-external/package/hassio/hassio.mk +++ b/buildroot-external/package/hassio/hassio.mk @@ -9,13 +9,20 @@ HASSIO_LICENSE = Apache License 2.0 # HASSIO_LICENSE_FILES = $(BR2_EXTERNAL_HASSOS_PATH)/../LICENSE HASSIO_SITE = $(BR2_EXTERNAL_HASSOS_PATH)/package/hassio HASSIO_SITE_METHOD = local -HASSIO_VERSION_URL = "https://version.home-assistant.io/stable.json" +HASSIO_VERSION_URL = "https://version.home-assistant.io/" +ifeq ($(BR2_PACKAGE_HASSIO_CHANNEL_STABLE),y) +HASSIO_VERSION_CHANNEL = "stable" +else ifeq ($(BR2_PACKAGE_HASSIO_CHANNEL_BETA),y) +HASSIO_VERSION_CHANNEL = "beta" +else ifeq ($(BR2_PACKAGE_HASSIO_CHANNEL_DEV),y) +HASSIO_VERSION_CHANNEL = "dev" +endif HASSIO_CONTAINER_IMAGES_ARCH = supervisor dns audio cli multicast observer core define HASSIO_CONFIGURE_CMDS # Deploy only landing page for "core" by setting version to "landingpage" - curl -s $(HASSIO_VERSION_URL) | jq '.core = "landingpage"' > $(@D)/stable.json + curl -s $(HASSIO_VERSION_URL)$(HASSIO_VERSION_CHANNEL)".json" | jq '.core = "landingpage"' > $(@D)/version.json endef define HASSIO_BUILD_CMDS @@ -23,14 +30,14 @@ define HASSIO_BUILD_CMDS $(Q)mkdir -p $(HASSIO_DL_DIR) $(foreach image,$(HASSIO_CONTAINER_IMAGES_ARCH),\ $(BR2_EXTERNAL_HASSOS_PATH)/package/hassio/fetch-container-image.sh \ - $(BR2_PACKAGE_HASSIO_ARCH) $(BR2_PACKAGE_HASSIO_MACHINE) $(@D)/stable.json $(image) "$(HASSIO_DL_DIR)" "$(@D)/images" + $(BR2_PACKAGE_HASSIO_ARCH) $(BR2_PACKAGE_HASSIO_MACHINE) $(@D)/version.json $(image) "$(HASSIO_DL_DIR)" "$(@D)/images" ) endef HASSIO_INSTALL_IMAGES = YES define HASSIO_INSTALL_IMAGES_CMDS - $(BR2_EXTERNAL_HASSOS_PATH)/package/hassio/create-data-partition.sh "$(@D)" "$(BINARIES_DIR)" + $(BR2_EXTERNAL_HASSOS_PATH)/package/hassio/create-data-partition.sh "$(@D)" "$(BINARIES_DIR)" "$(HASSIO_VERSION_CHANNEL)" endef $(eval $(generic-package)) diff --git a/buildroot-external/patches/uboot/0001-CMD-read-string-from-fileinto-env.patch b/buildroot-external/patches/uboot/0001-CMD-read-string-from-fileinto-env.patch index f768b1d5a35..fcec8f2e666 100644 --- a/buildroot-external/patches/uboot/0001-CMD-read-string-from-fileinto-env.patch +++ b/buildroot-external/patches/uboot/0001-CMD-read-string-from-fileinto-env.patch @@ -1,4 +1,4 @@ -From d44635df07c79c6e6e6832a5c59d27d27aacfa75 Mon Sep 17 00:00:00 2001 +From 01d614198feedef81ce60e61bbdf5f1ddc62be52 Mon Sep 17 00:00:00 2001 From: Pascal Vizeli Date: Sun, 5 Aug 2018 20:43:03 +0000 Subject: [PATCH] CMD: read string from fileinto env @@ -7,8 +7,8 @@ Signed-off-by: Pascal Vizeli --- cmd/Kconfig | 5 +++++ cmd/Makefile | 1 + - cmd/fileenv.c | 46 ++++++++++++++++++++++++++++++++++++++++++++++ - 3 files changed, 52 insertions(+) + cmd/fileenv.c | 45 +++++++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 51 insertions(+) create mode 100644 cmd/fileenv.c diff --git a/cmd/Kconfig b/cmd/Kconfig @@ -41,12 +41,11 @@ index 9a6790cc17..a521653ff8 100644 obj-$(CONFIG_CMD_SMC) += smccc.o diff --git a/cmd/fileenv.c b/cmd/fileenv.c new file mode 100644 -index 0000000000..9891cb05ab +index 0000000000..4154c8df0f --- /dev/null +++ b/cmd/fileenv.c -@@ -0,0 +1,46 @@ +@@ -0,0 +1,45 @@ +#include -+#include +#include +#include +#include @@ -91,6 +90,3 @@ index 0000000000..9891cb05ab + " \n" + " - Read file from fat32 and store it as env." +); --- -2.43.0 - diff --git a/buildroot-external/rootfs-overlay/usr/lib/systemd/system/systemd-time-wait-sync.service.d/timeout.conf b/buildroot-external/rootfs-overlay/usr/lib/systemd/system/systemd-time-wait-sync.service.d/timeout.conf index e367cf8625b..41d500db5b3 100644 --- a/buildroot-external/rootfs-overlay/usr/lib/systemd/system/systemd-time-wait-sync.service.d/timeout.conf +++ b/buildroot-external/rootfs-overlay/usr/lib/systemd/system/systemd-time-wait-sync.service.d/timeout.conf @@ -1,2 +1,2 @@ [Service] -TimeoutStartSec=90s +TimeoutStartSec=15s diff --git a/buildroot-external/rootfs-overlay/usr/libexec/haos-data-disk-detach b/buildroot-external/rootfs-overlay/usr/libexec/haos-data-disk-detach index 361a6745e89..dafc469a514 100755 --- a/buildroot-external/rootfs-overlay/usr/libexec/haos-data-disk-detach +++ b/buildroot-external/rootfs-overlay/usr/libexec/haos-data-disk-detach @@ -1,4 +1,5 @@ #!/bin/sh +# shellcheck disable=SC1091 # Find root using rdev command rootpart=$(rdev | cut -f 1 -d ' ') @@ -9,15 +10,53 @@ sleep 10s datapartitions=$(blkid --match-token LABEL="hassos-data" --output device) -for datapart in ${datapartitions} -do - datadev=$(lsblk -no pkname "${datapart}") - - # If major does not match our root device major, it is an external data - # disk. Rename to make sure it gets ignored. - if [ "$rootdev" != "$datadev" ] - then - echo "Found external data disk device on ${datapart}, mark it disabled..." - e2label "${datapart}" hassos-data-dis - fi -done +. /etc/os-release + +disable_data_partition() { + e2label "${1}" hassos-data-dis +} + +if [ "$VARIANT_ID" = "yellow" ]; then + emmc_data_partition="" + nvme_data_partition="" + + for datapart in ${datapartitions}; do + datadev=$(lsblk -no pkname "${datapart}") + + case "${datadev}" in + mmc*) + # Data partition on internal eMMC + if [ "$rootdev" = "$datadev" ]; then + emmc_data_partition="${datapart}" + fi + ;; + nvme0*) + # Data partition on first NVMe disk + nvme_data_partition="${datapart}" + ;; + *) + # Disable all other data disks as normally + if [ "$rootdev" != "$datadev" ]; then + echo "Found extra external data disk device on ${datapart}, marking it disabled..." + disable_data_partition "${datapart}" + fi + ;; + esac + done + + if [ -n "${emmc_data_partition}" ] && [ -n "${nvme_data_partition}" ]; then + echo "Found both eMMC and NVMe data disk devices, marking eMMC as disabled" + disable_data_partition "${emmc_data_partition}" + fi +else + for datapart in ${datapartitions}; do + datadev=$(lsblk -no pkname "${datapart}") + + # If major does not match our root device major, it is an external data + # disk. Rename to make sure it gets ignored. + if [ "$rootdev" != "$datadev" ]; then + echo "Found external data disk device on ${datapart}, marking it disabled..." + disable_data_partition "${datapart}" + fi + done +fi