diff --git a/src/asm/ari_2.s b/src/asm/ari_2.s index da19d6f..3c8d9de 100644 --- a/src/asm/ari_2.s +++ b/src/asm/ari_2.s @@ -69,39 +69,42 @@ auipc x22, 2048 #8388608+216=8388824 lui x23, 42069 #172314624 nop -|---------------------------------------| -| Register File State | -|---------------------------------------| -| x00, zero = 0x00000000 ( 0)| -| x01, ra = 0xffffffff ( -1)| -| x02, sp = 0x00000023 ( 35)| -| x03, gp = 0x00000067 ( 103)| -| x04, tp = 0x00000033 ( 51)| -| x05, t0 = 0x00000001 ( 1)| -| x06, t1 = 0xffffff00 ( -256)| -| x07, t2 = 0x00000019 ( 25)| -| x08, s0 = 0xffffff93 ( -109)| -| x09, s1 = 0x00000093 ( 147)| -| x10, a0 = 0xffff9313 ( -27885)| -| x11, a1 = 0x00009313 ( 37651)| -| x12, a2 = 0x00000000 ( 0)| -| x13, a3 = 0xffffffff ( -1)| -| x14, a4 = 0x00000067 ( 103)| -| x15, a5 = 0x00000023 ( 35)| -| x16, a6 = 0x00000004 ( 4)| -| x17, a7 = 0x00000230 ( 560)| -| x18, s2 = 0x00000006 ( 6)| -| x19, s3 = 0xfffffff0 ( -16)| -| x20, s4 = 0x00000001 ( 1)| -| x21, s5 = 0x000000d4 ( 212)| -| x22, s6 = 0x008000d8 ( 8388824)| -| x23, s7 = 0x0a455000 ( 172314624)| -| x24, s8 = 0x93130104 (-1827471100)| -| x25, s9 = 0x00000104 ( 260)| -| x26, s10 = 0x00000045 ( 69)| -| x27, s11 = 0x0000000c ( 12)| -| x28, t3 = 0x00000064 ( 100)| -| x29, t4 = 0x000001a4 ( 420)| -| x30, t5 = 0x00000045 ( 69)| -| x31, t6 = 0x00809313 ( 8426259)| -|---------------------------------------| \ No newline at end of file +trap: +beq x0, x0, trap + +#TESTASSERTOUTPUT|---------------------------------------| +#TESTASSERTOUTPUT| Register File State :) | +#TESTASSERTOUTPUT|---------------------------------------| +#TESTASSERTOUTPUT| x00, zero = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x01, ra = 0xffffffff ( -1)| +#TESTASSERTOUTPUT| x02, sp = 0x00000023 ( 35)| +#TESTASSERTOUTPUT| x03, gp = 0x00000067 ( 103)| +#TESTASSERTOUTPUT| x04, tp = 0x00000033 ( 51)| +#TESTASSERTOUTPUT| x05, t0 = 0x00000001 ( 1)| +#TESTASSERTOUTPUT| x06, t1 = 0xffffff00 ( -256)| +#TESTASSERTOUTPUT| x07, t2 = 0x00000019 ( 25)| +#TESTASSERTOUTPUT| x08, s0 = 0xffffff93 ( -109)| +#TESTASSERTOUTPUT| x09, s1 = 0x00000093 ( 147)| +#TESTASSERTOUTPUT| x10, a0 = 0xffff9313 ( -27885)| +#TESTASSERTOUTPUT| x11, a1 = 0x00009313 ( 37651)| +#TESTASSERTOUTPUT| x12, a2 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x13, a3 = 0xffffffff ( -1)| +#TESTASSERTOUTPUT| x14, a4 = 0x00000067 ( 103)| +#TESTASSERTOUTPUT| x15, a5 = 0x00000023 ( 35)| +#TESTASSERTOUTPUT| x16, a6 = 0x00000004 ( 4)| +#TESTASSERTOUTPUT| x17, a7 = 0x00000230 ( 560)| +#TESTASSERTOUTPUT| x18, s2 = 0x00000006 ( 6)| +#TESTASSERTOUTPUT| x19, s3 = 0xfffffff0 ( -16)| +#TESTASSERTOUTPUT| x20, s4 = 0x00000001 ( 1)| +#TESTASSERTOUTPUT| x21, s5 = 0x000000d4 ( 212)| +#TESTASSERTOUTPUT| x22, s6 = 0x008000d8 ( 8388824)| +#TESTASSERTOUTPUT| x23, s7 = 0x0a455000 ( 172314624)| +#TESTASSERTOUTPUT| x24, s8 = 0x93130104 (-1827471100)| +#TESTASSERTOUTPUT| x25, s9 = 0x00000104 ( 260)| +#TESTASSERTOUTPUT| x26, s10 = 0x00000045 ( 69)| +#TESTASSERTOUTPUT| x27, s11 = 0x0000000c ( 12)| +#TESTASSERTOUTPUT| x28, t3 = 0x00000064 ( 100)| +#TESTASSERTOUTPUT| x29, t4 = 0x000001a4 ( 420)| +#TESTASSERTOUTPUT| x30, t5 = 0x00000045 ( 69)| +#TESTASSERTOUTPUT| x31, t6 = 0x00809313 ( 8426259)| +#TESTASSERTOUTPUT|---------------------------------------| \ No newline at end of file diff --git a/src/asm/out/ari_1.memh b/src/asm/out/ari_1.memh index 53711e3..ea9fce7 100644 --- a/src/asm/out/ari_1.memh +++ b/src/asm/out/ari_1.memh @@ -1,37 +1,37 @@ -fff00093 // PC=0x0 line=1: addi x1, x0, -1 # x01 = -1 -02300113 // PC=0x4 line=2: addi x2, x0, 35 # x02 = 35 -00d08de7 // PC=0x8 line=3: jalr x27,x1,13 -04414193 // PC=0xc line=4: xori x3, x2, 68 # x03 = 103 -01116213 // PC=0x10 line=5: ori x4, x2, 17 # x04 = 51 -01117293 // PC=0x14 line=6: andi x5, x2, 17 # x05 = 1 -00809313 // PC=0x18 line=7: slli x6, x1, 8 # x06 = -256 -0021d393 // PC=0x1c line=8: srli x7, x3, 2 # x07 = 25 -40635413 // PC=0x20 line=9: srai x8, x6, 6 # x08 = -4 -0230a493 // PC=0x24 line=10: slti x9, x1, 35 # x09 = 1 -0230b513 // PC=0x28 line=11: sltiu x10, x1, 35 # x10 = 0 -001085b3 // PC=0x2c line=12: add x11, x1, x1 # x11 = -2 -40108633 // PC=0x30 line=13: sub x12, x1, x1 # x12 = 0 -00c0c6b3 // PC=0x34 line=14: xor x13, x1, x12 # x13 = -1 -00316733 // PC=0x38 line=15: or x14, x2, x3 # x14 = 103 -003177b3 // PC=0x3c line=16: and x15, x2, x3 # x15 = 35 -00400813 // PC=0x40 line=17: addi x16, x0, 4 # x16 = 4 -010118b3 // PC=0x44 line=18: sll x17, x2, x16 # x17 = 560 -0101d933 // PC=0x48 line=19: srl x18, x3, x16 # x18 = 6 -410359b3 // PC=0x4c line=20: sra x19, x6, x16 # x19 = -16 -0020aa33 // PC=0x50 line=21: slt x20, x1, x2 # x20 = 1 -0020bab3 // PC=0x54 line=22: sltu x21, x1, x2 # x20 = 0 -002b0663 // PC=0x58 line=24: beq x22, x2, loop_end -001b0b13 // PC=0x5c line=25: addi x22, x22, 1 -ff9ffe6f // PC=0x60 line=26: jal x28, loop_head -1a4e8e93 // PC=0x64 line=28: addi x29, x29, 420 -fffb8b93 // PC=0x68 line=30: addi x23, x23, -1 -fe8b9ee3 // PC=0x6c line=31: bne x23, x8, loop_head2 -045f0f13 // PC=0x70 line=32: addi x30, x30, 69 -01802f83 // PC=0x74 line=33: lw x31, 24(x0) #8426259 -2fe02c23 // PC=0x78 line=34: sw x30, 760(x0) #69 -3089ad03 // PC=0x7c line=35: lw x26, 776(x19) #69 -ffd8a823 // PC=0x80 line=36: sw x29, -16(x17) #420 -23000023 // PC=0x84 line=37: sb x16, 544(x0) #4 -22002c83 // PC=0x88 line=38: lw x25, 544(x0) #260 -07fe9f23 // PC=0x8c line=39: sh x31, 126(x29) #37651 -32032c03 // PC=0x90 line=40: lw x24, 800(x6) #-1827471100 +fff00093 // PC=0x0 line=3: addi x1, x0, -1 # x01 = -1 +02300113 // PC=0x4 line=4: addi x2, x0, 35 # x02 = 35 +00d08de7 // PC=0x8 line=5: jalr x27,x1,13 +04414193 // PC=0xc line=6: xori x3, x2, 68 # x03 = 103 +01116213 // PC=0x10 line=7: ori x4, x2, 17 # x04 = 51 +01117293 // PC=0x14 line=8: andi x5, x2, 17 # x05 = 1 +00809313 // PC=0x18 line=9: slli x6, x1, 8 # x06 = -256 +0021d393 // PC=0x1c line=10: srli x7, x3, 2 # x07 = 25 +40635413 // PC=0x20 line=11: srai x8, x6, 6 # x08 = -4 +0230a493 // PC=0x24 line=12: slti x9, x1, 35 # x09 = 1 +0230b513 // PC=0x28 line=13: sltiu x10, x1, 35 # x10 = 0 +001085b3 // PC=0x2c line=14: add x11, x1, x1 # x11 = -2 +40108633 // PC=0x30 line=15: sub x12, x1, x1 # x12 = 0 +00c0c6b3 // PC=0x34 line=16: xor x13, x1, x12 # x13 = -1 +00316733 // PC=0x38 line=17: or x14, x2, x3 # x14 = 103 +003177b3 // PC=0x3c line=18: and x15, x2, x3 # x15 = 35 +00400813 // PC=0x40 line=19: addi x16, x0, 4 # x16 = 4 +010118b3 // PC=0x44 line=20: sll x17, x2, x16 # x17 = 560 +0101d933 // PC=0x48 line=21: srl x18, x3, x16 # x18 = 6 +410359b3 // PC=0x4c line=22: sra x19, x6, x16 # x19 = -16 +0020aa33 // PC=0x50 line=23: slt x20, x1, x2 # x20 = 1 +0020bab3 // PC=0x54 line=24: sltu x21, x1, x2 # x20 = 0 +002b0663 // PC=0x58 line=26: beq x22, x2, loop_end +001b0b13 // PC=0x5c line=27: addi x22, x22, 1 +ff9ffe6f // PC=0x60 line=28: jal x28, loop_head +1a4e8e93 // PC=0x64 line=30: addi x29, x29, 420 +fffb8b93 // PC=0x68 line=32: addi x23, x23, -1 +fe8b9ee3 // PC=0x6c line=33: bne x23, x8, loop_head2 +045f0f13 // PC=0x70 line=34: addi x30, x30, 69 +01802f83 // PC=0x74 line=35: lw x31, 24(x0) #8426259 +2fe02c23 // PC=0x78 line=36: sw x30, 760(x0) #69 +3089ad03 // PC=0x7c line=37: lw x26, 776(x19) #69 +ffd8a823 // PC=0x80 line=38: sw x29, -16(x17) #420 +23000023 // PC=0x84 line=39: sb x16, 544(x0) #4 +22002c83 // PC=0x88 line=40: lw x25, 544(x0) #260 +07fe9f23 // PC=0x8c line=41: sh x31, 126(x29) #37651 +32032c03 // PC=0x90 line=42: lw x24, 800(x6) #-1827471100 diff --git a/src/asm/out/ari_2.memh b/src/asm/out/ari_2.memh index 1c6dbb6..8c395eb 100644 --- a/src/asm/out/ari_2.memh +++ b/src/asm/out/ari_2.memh @@ -55,3 +55,4 @@ ffd8a823 // PC=0x80 line=38: sw x29, -16(x17) #420 00800b17 // PC=0xd8 line=68: auipc x22, 2048 #8388608+216=8388824 0a455bb7 // PC=0xdc line=69: lui x23, 42069 #172314624 00000013 // PC=0xe0 line=70: nop +00000063 // PC=0xe4 line=73: beq x0, x0, trap diff --git a/src/asm/out/lb.memh b/src/asm/out/lb.memh new file mode 100644 index 0000000..da97037 --- /dev/null +++ b/src/asm/out/lb.memh @@ -0,0 +1,4 @@ +41000093 // PC=0x0 line=1: addi x1, x0, 1040 # x01 = 1040 (16 + 1024) +40000113 // PC=0x4 line=2: addi x2, x0, 1024 # x02 = 1024 +00110023 // PC=0x8 line=3: sb x1, 0(x2) # (MEM:1024) = 16 +00010183 // PC=0xc line=4: lb x3, 0(x2) # x03 = 16 diff --git a/src/asm/out/storeload_2.memh b/src/asm/out/storeload_2.memh new file mode 100644 index 0000000..b0d58af --- /dev/null +++ b/src/asm/out/storeload_2.memh @@ -0,0 +1,19 @@ +0ff00093 // PC=0x0 line=1: addi x1, x0, 255 # x01 = 255 (32'b00000000000000000000000011111111) +40000113 // PC=0x4 line=2: addi x2, x0, 1024 # x02 = 1024 +00112023 // PC=0x8 line=3: sw x1, 0(x2) # (MEM:1024) = 255 (32'b00000000000000000000000011111111) +00010183 // PC=0xc line=4: lb x3, 0(x2) # x03 = -1 (32'b11111111111111111111111111111111) +00011203 // PC=0x10 line=5: lh x4, 0(x2) # x04 = 255 (32'b00000000000000000000000011111111) +00012283 // PC=0x14 line=6: lw x5, 0(x2) # x05 = 255 (32'b00000000000000000000000011111111) +00014303 // PC=0x18 line=7: lbu x6, 0(x2) # x06 = 255 (32'b00000000000000000000000011111111) +00015383 // PC=0x1c line=8: lhu x7, 0(x2) # x07 = 255 (32'b00000000000000000000000011111111) +fff00513 // PC=0x20 line=11: addi x10, x0, -1 # x10 = -1 (32'b11111111111111111111111111111111) +40400593 // PC=0x24 line=12: addi x11, x0, 1028 # x11 = 1028 +00000613 // PC=0x28 line=15: addi x12, x0, 0 # x12 = 0 (32'b00000000000000000000000000000000) +00000693 // PC=0x2c line=16: addi x13, x0, 0 # x13 = 0 (32'b00000000000000000000000000000000) +00000713 // PC=0x30 line=17: addi x14, x0, 0 # x14 = 0 (32'b00000000000000000000000000000000) +00a5a023 // PC=0x34 line=20: sw x10, 0(x11) # (MEM:1028) = -1 (32'b11111111111111111111111111111111) +00a59223 // PC=0x38 line=21: sh x10, 4(x11) # (MEM:1032) = 65535 (32'b00000000000000001111111111111111) +00a58423 // PC=0x3c line=22: sb x10, 8(x11) # (MEM:1036) = 255 (32'b00000000000000000000000011111111) +0005a603 // PC=0x40 line=25: lw x12, 0(x11) # x12 = -1 (32'b11111111111111111111111111111111) +0045a683 // PC=0x44 line=26: lw x13, 4(x11) # x13 = 32'bXXXXXXXXXXXXXXXX1111111111111111 +0085a703 // PC=0x48 line=27: lw x14, 8(x11) # x14 = -1 (32'bXXXXXXXXXXXXXXXXXXXXXXXX11111111) diff --git a/src/asm/storeload_2.s b/src/asm/storeload_2.s new file mode 100644 index 0000000..dab70c6 --- /dev/null +++ b/src/asm/storeload_2.s @@ -0,0 +1,65 @@ +addi x1, x0, 255 # x01 = 255 (32'b00000000000000000000000011111111) +addi x2, x0, 1024 # x02 = 1024 +sw x1, 0(x2) # (MEM:1024) = 255 (32'b00000000000000000000000011111111) +lb x3, 0(x2) # x03 = -1 (32'b11111111111111111111111111111111) +lh x4, 0(x2) # x04 = 255 (32'b00000000000000000000000011111111) +lw x5, 0(x2) # x05 = 255 (32'b00000000000000000000000011111111) +lbu x6, 0(x2) # x06 = 255 (32'b00000000000000000000000011111111) +lhu x7, 0(x2) # x07 = 255 (32'b00000000000000000000000011111111) + +# test partial stores +addi x10, x0, -1 # x10 = -1 (32'b11111111111111111111111111111111) +addi x11, x0, 1028 # x11 = 1028 + +# zero out the memory +addi x12, x0, 0 # x12 = 0 (32'b00000000000000000000000000000000) +addi x13, x0, 0 # x13 = 0 (32'b00000000000000000000000000000000) +addi x14, x0, 0 # x14 = 0 (32'b00000000000000000000000000000000) + +# store partial +sw x10, 0(x11) # (MEM:1028) = -1 (32'b11111111111111111111111111111111) +sh x10, 4(x11) # (MEM:1032) = 65535 (32'b00000000000000001111111111111111) +sb x10, 8(x11) # (MEM:1036) = 255 (32'b00000000000000000000000011111111) + +# read full +lw x12, 0(x11) # x12 = -1 (32'b11111111111111111111111111111111) +lw x13, 4(x11) # x13 = 32'bXXXXXXXXXXXXXXXX1111111111111111 +lw x14, 8(x11) # x14 = -1 (32'bXXXXXXXXXXXXXXXXXXXXXXXX11111111) + + +#TESTASSERTOUTPUT|---------------------------------------| +#TESTASSERTOUTPUT| Register File State :) | +#TESTASSERTOUTPUT|---------------------------------------| +#TESTASSERTOUTPUT| x00, zero = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x01, ra = 0x000000ff ( 255)| +#TESTASSERTOUTPUT| x02, sp = 0x00000400 ( 1024)| +#TESTASSERTOUTPUT| x03, gp = 0xffffffff ( -1)| +#TESTASSERTOUTPUT| x04, tp = 0x000000ff ( 255)| +#TESTASSERTOUTPUT| x05, t0 = 0x000000ff ( 255)| +#TESTASSERTOUTPUT| x06, t1 = 0x000000ff ( 255)| +#TESTASSERTOUTPUT| x07, t2 = 0x000000ff ( 255)| +#TESTASSERTOUTPUT| x08, s0 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x09, s1 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x10, a0 = 0xffffffff ( -1)| +#TESTASSERTOUTPUT| x11, a1 = 0x00000404 ( 1028)| +#TESTASSERTOUTPUT| x12, a2 = 0xffffffff ( -1)| +#TESTASSERTOUTPUT| x13, a3 = 0xxxxxffff ( X)| +#TESTASSERTOUTPUT| x14, a4 = 0xxxxxxxff ( X)| +#TESTASSERTOUTPUT| x15, a5 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x16, a6 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x17, a7 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x18, s2 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x19, s3 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x20, s4 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x21, s5 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x22, s6 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x23, s7 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x24, s8 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x25, s9 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x26, s10 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x27, s11 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x28, t3 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x29, t4 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x30, t5 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x31, t6 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT|---------------------------------------| \ No newline at end of file diff --git a/src/asm/test/ari_2.result b/src/asm/test/ari_2.result index b91b5d7..b48284b 100644 --- a/src/asm/test/ari_2.result +++ b/src/asm/test/ari_2.result @@ -11,7 +11,7 @@ Usage: WARNING: ./tests/provided/bytewise_distributed_ram.sv:58: $readmemh(../asm/out/ari_2.memh): Not enough words in the file for the requested range [0:1023]. Running simulation of memory ../asm/out/ari_2.memh for up to 10000 cycles. Waves will be stored to rv32_simulator.fst. FST info: dumpfile rv32_simulator.fst opened for output. -Ran 10000 cycles, finishing. +!!! Infinite loop detected (over 4 iterations) - ending sim !!! #TESTASSERTOUTPUT|---------------------------------------| #TESTASSERTOUTPUT| Register File State :) | #TESTASSERTOUTPUT|---------------------------------------| @@ -23,11 +23,11 @@ Ran 10000 cycles, finishing. #TESTASSERTOUTPUT| x05, t0 = 0x00000001 ( 1)| #TESTASSERTOUTPUT| x06, t1 = 0xffffff00 ( -256)| #TESTASSERTOUTPUT| x07, t2 = 0x00000019 ( 25)| -#TESTASSERTOUTPUT| x08, s0 = 0x00000093 ( 147)| -#TESTASSERTOUTPUT| x09, s1 = 0x93130104 (-1827471100)| -#TESTASSERTOUTPUT| x10, a0 = 0x00009313 ( 37651)| -#TESTASSERTOUTPUT| x11, a1 = 0x93130104 (-1827471100)| -#TESTASSERTOUTPUT| x12, a2 = 0x00000010 ( 16)| +#TESTASSERTOUTPUT| x08, s0 = 0xffffff93 ( -109)| +#TESTASSERTOUTPUT| x09, s1 = 0x00000093 ( 147)| +#TESTASSERTOUTPUT| x10, a0 = 0xffff9313 ( -27885)| +#TESTASSERTOUTPUT| x11, a1 = 0x00009313 ( 37651)| +#TESTASSERTOUTPUT| x12, a2 = 0x00000000 ( 0)| #TESTASSERTOUTPUT| x13, a3 = 0xffffffff ( -1)| #TESTASSERTOUTPUT| x14, a4 = 0x00000067 ( 103)| #TESTASSERTOUTPUT| x15, a5 = 0x00000023 ( 35)| @@ -36,9 +36,9 @@ Ran 10000 cycles, finishing. #TESTASSERTOUTPUT| x18, s2 = 0x00000006 ( 6)| #TESTASSERTOUTPUT| x19, s3 = 0xfffffff0 ( -16)| #TESTASSERTOUTPUT| x20, s4 = 0x00000001 ( 1)| -#TESTASSERTOUTPUT| x21, s5 = 0x00000000 ( 0)| -#TESTASSERTOUTPUT| x22, s6 = 0x00000023 ( 35)| -#TESTASSERTOUTPUT| x23, s7 = 0xfffffffc ( -4)| +#TESTASSERTOUTPUT| x21, s5 = 0x000000d4 ( 212)| +#TESTASSERTOUTPUT| x22, s6 = 0x008000d8 ( 8388824)| +#TESTASSERTOUTPUT| x23, s7 = 0x0a455000 ( 172314624)| #TESTASSERTOUTPUT| x24, s8 = 0x93130104 (-1827471100)| #TESTASSERTOUTPUT| x25, s9 = 0x00000104 ( 260)| #TESTASSERTOUTPUT| x26, s10 = 0x00000045 ( 69)| diff --git a/src/asm/test/lb.result b/src/asm/test/lb.result new file mode 100644 index 0000000..f61f657 --- /dev/null +++ b/src/asm/test/lb.result @@ -0,0 +1,50 @@ +Usage: + ./rv32_simulator +initial_memory=path/to/memh/file + Additional arguments: + +initial_memory=path/to/memh/file + Required: path to a memh file that containes the assembled binary to run. + +max_cycles=NUMBER_OF_CYCLES_TO_RUN + +wave_fn=path/to/wave/file + default is rv32_simulator.fst + +final_memory=path/to/memh/file + If provided, the final memory contents will be saved here. Use this to debug your store instructions. +WARNING: ./tests/provided/bytewise_distributed_ram.sv:58: $readmemh(../asm/out/lb.memh): Not enough words in the file for the requested range [0:1023]. +Running simulation of memory ../asm/out/lb.memh for up to 10000 cycles. Waves will be stored to rv32_simulator.fst. +FST info: dumpfile rv32_simulator.fst opened for output. +Ran 10000 cycles, finishing. +#TESTASSERTOUTPUT|---------------------------------------| +#TESTASSERTOUTPUT| Register File State :) | +#TESTASSERTOUTPUT|---------------------------------------| +#TESTASSERTOUTPUT| x00, zero = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x01, ra = 0x00000410 ( 1040)| +#TESTASSERTOUTPUT| x02, sp = 0x00000400 ( 1024)| +#TESTASSERTOUTPUT| x03, gp = 0x00000010 ( 16)| +#TESTASSERTOUTPUT| x04, tp = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x05, t0 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x06, t1 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x07, t2 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x08, s0 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x09, s1 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x10, a0 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x11, a1 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x12, a2 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x13, a3 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x14, a4 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x15, a5 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x16, a6 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x17, a7 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x18, s2 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x19, s3 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x20, s4 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x21, s5 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x22, s6 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x23, s7 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x24, s8 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x25, s9 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x26, s10 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x27, s11 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x28, t3 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x29, t4 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x30, t5 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x31, t6 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT|---------------------------------------| diff --git a/src/asm/test/storeload_2.result b/src/asm/test/storeload_2.result new file mode 100644 index 0000000..f211c9d --- /dev/null +++ b/src/asm/test/storeload_2.result @@ -0,0 +1,50 @@ +Usage: + ./rv32_simulator +initial_memory=path/to/memh/file + Additional arguments: + +initial_memory=path/to/memh/file + Required: path to a memh file that containes the assembled binary to run. + +max_cycles=NUMBER_OF_CYCLES_TO_RUN + +wave_fn=path/to/wave/file + default is rv32_simulator.fst + +final_memory=path/to/memh/file + If provided, the final memory contents will be saved here. Use this to debug your store instructions. +WARNING: ./tests/provided/bytewise_distributed_ram.sv:58: $readmemh(../asm/out/storeload_2.memh): Not enough words in the file for the requested range [0:1023]. +Running simulation of memory ../asm/out/storeload_2.memh for up to 10000 cycles. Waves will be stored to rv32_simulator.fst. +FST info: dumpfile rv32_simulator.fst opened for output. +Ran 10000 cycles, finishing. +#TESTASSERTOUTPUT|---------------------------------------| +#TESTASSERTOUTPUT| Register File State :) | +#TESTASSERTOUTPUT|---------------------------------------| +#TESTASSERTOUTPUT| x00, zero = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x01, ra = 0x000000ff ( 255)| +#TESTASSERTOUTPUT| x02, sp = 0x00000400 ( 1024)| +#TESTASSERTOUTPUT| x03, gp = 0xffffffff ( -1)| +#TESTASSERTOUTPUT| x04, tp = 0x000000ff ( 255)| +#TESTASSERTOUTPUT| x05, t0 = 0x000000ff ( 255)| +#TESTASSERTOUTPUT| x06, t1 = 0x000000ff ( 255)| +#TESTASSERTOUTPUT| x07, t2 = 0x000000ff ( 255)| +#TESTASSERTOUTPUT| x08, s0 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x09, s1 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x10, a0 = 0xffffffff ( -1)| +#TESTASSERTOUTPUT| x11, a1 = 0x00000404 ( 1028)| +#TESTASSERTOUTPUT| x12, a2 = 0xffffffff ( -1)| +#TESTASSERTOUTPUT| x13, a3 = 0xxxxxffff ( X)| +#TESTASSERTOUTPUT| x14, a4 = 0xxxxxxxff ( X)| +#TESTASSERTOUTPUT| x15, a5 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x16, a6 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x17, a7 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x18, s2 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x19, s3 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x20, s4 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x21, s5 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x22, s6 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x23, s7 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x24, s8 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x25, s9 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x26, s10 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x27, s11 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x28, t3 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x29, t4 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x30, t5 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x31, t6 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT|---------------------------------------| diff --git a/src/components/Makefile b/src/components/Makefile index c1e28cb..d93bba4 100644 --- a/src/components/Makefile +++ b/src/components/Makefile @@ -109,9 +109,10 @@ test_rv32_ir_types: addi.validate itypes.validate irtypes.validate test_rv32_utypes: utypes.validate test_rv32_branch: beq.validate bne.validate blt.validate bge.validate bgeu.validate bltu.validate test_rv32_jal: jal_jalr.validate +test_rv32_load: storeload.validate storeload_2.validate test_rv32_integrated: ari_1.validate ari_2.validate -test_rv32_all: test_rv32_ir_types storeload.validate test_rv32_branch test_rv32_jal test_rv32_utypes test_rv32_integrated +test_rv32_all: test_rv32_ir_types test_rv32_load test_rv32_branch test_rv32_jal test_rv32_utypes test_rv32_integrated # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # Instruction Type Tests diff --git a/src/components/src/cpu/rv32i_multicycle_core.sv b/src/components/src/cpu/rv32i_multicycle_core.sv index d2047e4..fdd843d 100644 --- a/src/components/src/cpu/rv32i_multicycle_core.sv +++ b/src/components/src/cpu/rv32i_multicycle_core.sv @@ -98,12 +98,19 @@ module rv32i_multicycle_core( wire zero; wire equal; - - /* ---------------------- Non-Architectural Register Signals ---------------------- */ logic alu_last_ena; wire [31:0] alu_last; // Not a descriptive name, but this is what it's called in the text. + + + /* ---------------------- Non-Architectural Register Signals ---------------------- */ + + + /* -------------------------------------------------------------------------------------------------------------------*/ + /* Memory Decoder (begin) */ + /* -------------------------------------------------------------------------------------------------------------------*/ + logic [31:0] mem_data, mem_data_extended; logic mem_data_ena; - wire [31:0] mem_data; + enum logic [2:0] {MEM_SRC_PC, MEM_SRC_ALU_LAST, MEM_SRC_RESULT} mem_src; always_comb begin : mem_src_signals @@ -112,21 +119,38 @@ module rv32i_multicycle_core( MEM_SRC_ALU_LAST: mem_addr = alu_last; endcase end + + always_comb begin: mem_extended_decoder + case(funct3) + 3'b000: mem_data_extended = {{24{mem_data[7]}}, mem_data[7:0]}; // load byte, sign extend 7:0 + 3'b001: mem_data_extended = {{16{mem_data[15]}}, mem_data[15:0]}; // load byte, sign extend 15:0 + 3'b010: mem_data_extended = mem_data; // load word, 31:0 + 3'b100: mem_data_extended = {24'b0, mem_data[7:0]}; // load byte unsigned, 7:0 + 3'b101: mem_data_extended = {16'b0, mem_data[15:0]}; // load byte unsigned, 15:0 + endcase + end + + register #(.N(32), .RESET_VALUE(32'b0)) MEM_DATA_REGISTER ( + .clk(clk), .rst(rst), .ena(mem_data_ena), .d(mem_rd_data), .q(mem_data) + ); + + /* -------------------------------------------------------------------------------------------------------------------*/ + /* Memory Decoder (end) */ + /* -------------------------------------------------------------------------------------------------------------------*/ register #(.N(32), .RESET_VALUE(32'b0)) ALU_RESULT_REGISTER ( .clk(clk), .rst(rst), .ena(alu_last_ena), .d(alu_result), .q(alu_last) ); - register #(.N(32), .RESET_VALUE(32'b0)) MEM_DATA_REGISTER ( - .clk(clk), .rst(rst), .ena(mem_data_ena), .d(mem_rd_data), .q(mem_data) - ); + /* ---------------------- Result SRC Signals ---------------------- */ enum logic [2:0] { RESULT_SRC_ALU, RESULT_SRC_MEM_DATA, + RESULT_SRC_MEM_DATA_EXTENDED, RESULT_SRC_ALU_LAST, RESULT_SRC_PC_NEXT_INSTRUCTION, RESULT_SRC_IMMEDIATE @@ -137,6 +161,7 @@ module rv32i_multicycle_core( case(result_src) RESULT_SRC_ALU: result = alu_result; RESULT_SRC_MEM_DATA: result = mem_data; + RESULT_SRC_MEM_DATA_EXTENDED: result = mem_data_extended; RESULT_SRC_ALU_LAST: result = alu_last; RESULT_SRC_PC_NEXT_INSTRUCTION: result = PC_next_instruction; RESULT_SRC_IMMEDIATE: result = extended_immediate; @@ -241,8 +266,8 @@ module rv32i_multicycle_core( // mem_access is set the same for store/load during S_MEMREAD and S_MEMWRITE phases // special case for S_FETCH below where it swaps to MEM_ACCESS_WORD case(funct3) - 3'b000: mem_access = MEM_ACCESS_BYTE; - 3'b001: mem_access = MEM_ACCESS_HALF; + 3'b000, 3'b100: mem_access = MEM_ACCESS_BYTE; + 3'b001, 3'b101: mem_access = MEM_ACCESS_HALF; 3'b010: mem_access = MEM_ACCESS_WORD; endcase @@ -286,7 +311,7 @@ module rv32i_multicycle_core( // LOAD INSTRUCTION write back to RF S_MEMWB: begin set_default; - result_src = RESULT_SRC_MEM_DATA; + result_src = RESULT_SRC_MEM_DATA_EXTENDED; reg_write = 1; pc_next_src = PC_NEXT_INSTRUCTION; PC_ena = 1;