From 188b66abb4a0a068c091e0804a5b4b30de5d4e98 Mon Sep 17 00:00:00 2001
From: Daniel Sudzilouski <daniel@sudzilouski.com>
Date: Wed, 10 Jan 2024 10:58:05 -0800
Subject: [PATCH] fix register file enable bug (#14)

* add failing test for register file

* fix bug
---
 src/components/src/cpu/register_file.sv       |  2 +-
 .../tests/our/test_register_file.sv           | 20 ++++++++++++++-----
 2 files changed, 16 insertions(+), 6 deletions(-)

diff --git a/src/components/src/cpu/register_file.sv b/src/components/src/cpu/register_file.sv
index 3271f9c..8d9ded7 100644
--- a/src/components/src/cpu/register_file.sv
+++ b/src/components/src/cpu/register_file.sv
@@ -52,7 +52,7 @@ module register_file(rst, clk, wr_ena, wr_addr, wr_data, rd_addr0, rd_data0, rd_
         for(i=1;i<32;i++) begin
             register #(32) REG(
                 .clk(clk), 
-                .ena(write_addr_decoded[i]), 
+                .ena(write_addr_decoded[i] & wr_ena), 
                 .rst(rst), 
                 .d(wr_data),
                 .q(xn[i]));
diff --git a/src/components/tests/our/test_register_file.sv b/src/components/tests/our/test_register_file.sv
index 1777d7d..3f47d7b 100644
--- a/src/components/tests/our/test_register_file.sv
+++ b/src/components/tests/our/test_register_file.sv
@@ -12,7 +12,7 @@ module test_register_file;
 
 
     logic [4:0] wr_addr;
-    logic [31:0] wr_data;
+    logic [31:0] wr_data, wr_data_gen;
 
     logic[4:0] rd_addr0, rd_addr1;
     logic[31:0] rd_data0, rd_data1;
@@ -41,19 +41,29 @@ module test_register_file;
                 @(negedge clk);
                 wr_ena = 1;
                 wr_addr = i;
+                wr_data_gen = $random();
+                wr_data = wr_data_gen;
+                @(posedge clk);
+
+                 // test to make sure enable works correctly
+                @(negedge clk);
+                wr_ena = 0;
                 wr_data = $random();
-                #5; 
+                wr_addr = i;
                 @(posedge clk);
 
+                // test reading from register
+                @(negedge clk);
                 wr_ena = 0;
                 rd_addr0 = i;
                 rd_addr1 = i;
-                #5;
+                #1;
 
+            
                 // check value of register
                 $display("[register_file]: [rd_addr0: %0d], [rd_data0: %0d], [rd_addr1: %0d], [rd_data1: %0d], [exp_rd_data0: %0d]", rd_addr0, rd_data1, rd_addr1, rd_data1, wr_data);
-                assert(wr_data == rd_data0) else $fatal;
-                assert(wr_data == rd_data1) else $fatal;
+                assert(wr_data_gen == rd_data0) else $fatal;
+                assert(wr_data_gen == rd_data1) else $fatal;
                 
             end
             $display("[PASS RANDOM TEST] iteration #%d", test_cases);