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Supported Platforms
The Tower LoRa Module has a TypeABZ-78 module, i.e., the open MCU variant based on STM32L082. The schematic can be found here.
This platform uses GPIO PA12 (pin 1) to control power to VDD_TCXO (pin 48). The factory reset pin GPIO PB15 (pin 14) is disconnected. USART1 (GPIO PA9+10, pins 18+19) is connected to an unpopulated header on the top of the PCB. The SWD interface (GPIO PA13+14, pins 41+42) is connected to an unpopulated SWD connector on the bottom of the PBC. SX1276 DIO4 (pin 10) is connected to GPIO PA5 (pin 21). BOOT (pin 43) and MCU_NRST (pin 34) are connected to the unpopulated header.
The Chester platform has a TypeABZ-78 module, i.e., the open MCU variant based on STM32L082.
This platform uses GPIO PA12 (pin 1) to control power to VDD_TCXO (pin 48). The factory reset pin GPIO PB15 (pin 14) is disconnected. USART1 (GPIO PA9+10, pins 18+19) is connected to the host MCU. The SWD interface (GPIO PA13+14, pins 41+42) is connected to an SWD port. SX1276 DIO4 (pin 10) is connected to GPIO PA5 (pin 21). BOOT (pin 43) and MCU_NRST (pin 34) are connected to the host MCU.
Builds for the Chester platform have certification AT commands enabled.
The MKR WAN 1300 platform has a TypeABZ-78 module, i.e., the open MCU variant based on STM32L082. The schematic can be found here.
VDD_TCXO (pin 48) is hardwired to VDD, i.e., the TCXO IC is permanently powered on. The factory reset pin GPIO PB15 (pin 14) is connected to the host MCU. USART1 (GPIO PA9+10, pins 18+19) is routed to test points (i.e., disconnected). The SWD interface (GPIO PA13+14, pins 41+42) is connected to SWD test points. SX1276 DIO4 (pin 10) is disconnected. BOOT (pin 43) and MCU_NRST (pin 34) are connected to the host MCU.
The MKR WAN 1310 platform has a TypeABZ module. The schematic does not show which variant it is, but we assume it's the open MCU variant based on STM32L082. The schematic is available here.
This platform uses GPIO PB6 (pin 39) to control power to VDD_TCXO (pin 48). The factory reset pin GPIO PB15 (pin 14) is connected to the host MCU and shares lines with a SPI bus. USART1 (GPIO PA9+10, pins 18+19) is disconnected. The SWD interface (GPIO PA13+14, pins 41+42) is connected to SWD test points. SX1276 DIO4 (pin 10) is connected to GPIO PA5 (pin 21). BOOT (pin 43) and MCU_NRST (pin 34) are connected to the host MCU.
The B-L072Z-LRWAN1 platform has a TypeABZ-091 module, i.e., the open MCU variant based on STM32L072. The schematic is available in the user manual.
The control of VDD_TCXO (pin 48) on this platform is selectable with jumper JP9. It can be connected either to VDD or to GPIO PA12 (pin 1). The factory reset pin GPIO PB15 (pin 14) is routed to the connector CN3 (disconnected). USART1 (GPIO PA9+10, pins 18+19) is routed to connector CN3. The SWD interface (GPIO PA13+14, pins 41+42) is connected to the on-board ST-Link programmer. SX1276 DIO4 (pin 10) is routed to the connector CN2, thus left disconnected. BOOT (pin 43) is routed to connector CN2. MCU_NRST (pin 34) is connected to an on-board reset button.
| Name | Factory Reset Pin | TCXO Control | Detachable LPUART | Debug Log | Certification AT Commands |
|---|---|---|---|---|---|
| tower | Disabled | GPIO PA12 | Disabled | USART1 | Disabled |
| chester | Disabled | GPIO PA12 | Disabled | USART1 | Enabled |
| mkrwan1300 | Disabled | Always on | Disabled | Segger RTT | Disabled |
| mrkwan1310 | Disabled | GPIO PB6 | Enabled | Segger RTT | Disabled |
| bl072zlrwan1 | Disabled | GPIO PA12 | Disabled | USART1 | Disabled |