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This is a tracking bug for SIMD generation in the wasm backend; there are a number of SIMD opcodes in the final wasm-simd spec that we should be generating, but aren't. The bulk of these appear to be suboptimal code generation by the wasm backend in LLVM trunk (12.x) and have been reported to the relevant people, along with repro cases, and work is being done to improve them; it may be that some of them require additional effort or special-casing on Halide's side. At present, the instructions known missing are:
v128.constant
SIMD left-shift (i8x16.shl, etc) and right-shift (i8x16.shr_s, i8x16.shr_u, etc) when the RHS is not a constant
integer narrowing (eg i8x16.narrow_i16x8_s)
integer widening (eg i16x8.widen_low_i8x16_s)
Additionally, the wasm sign-extension opcodes (eg i32.extend8_s, not part of the SIMD spec) aren't reliably emitted.
The text was updated successfully, but these errors were encountered:
due to recent churn in the wasm-simd spec, more stuff is broken and will need attention; some things in simd_op_check that no longer get emitted (and may no longer exist):
v8x16.shuffle
v16x8.load_splat
(Basically, all of the wasm-simd ops need to be revisited once LLVM stabilizes generation of the final spec.)
This is a tracking bug for SIMD generation in the wasm backend; there are a number of SIMD opcodes in the final wasm-simd spec that we should be generating, but aren't. The bulk of these appear to be suboptimal code generation by the wasm backend in LLVM trunk (12.x) and have been reported to the relevant people, along with repro cases, and work is being done to improve them; it may be that some of them require additional effort or special-casing on Halide's side. At present, the instructions known missing are:
Additionally, the wasm sign-extension opcodes (eg i32.extend8_s, not part of the SIMD spec) aren't reliably emitted.
The text was updated successfully, but these errors were encountered: