GitHub - guyarad7/Arbiter-Verification: A comprehensive testbench for a round-robin arbiter.

This is my final project in the course Verification Engineering at Cadence & SQLink.

The project is a verification environment for a round-robin arbiter.

The code was written in SystemVerilog and UVM.

The arbiter DUT isn't included, because it wasn't written by me.

Important files:

Name		Name	Last commit message	Last commit date
Latest commit History 16 Commits
cov_work/scope		cov_work/scope
Arbiter Description.pdf		Arbiter Description.pdf
Arbiter Verification Plan.pdf		Arbiter Verification Plan.pdf
README.md		README.md
agent_host.sv		agent_host.sv
agent_response.sv		agent_response.sv
arbiter_pkg.sv		arbiter_pkg.sv
config.sv		config.sv
driver_host.sv		driver_host.sv
driver_response.sv		driver_response.sv
environment.sv		environment.sv
if_host.sv		if_host.sv
if_response.sv		if_response.sv
monitor_host.sv		monitor_host.sv
monitor_response.sv		monitor_response.sv
scoreboard.sv		scoreboard.sv
sequence_all.sv		sequence_all.sv
sequence_disable.sv		sequence_disable.sv
sequence_random.sv		sequence_random.sv
sequence_read.sv		sequence_read.sv
sequence_write.sv		sequence_write.sv
sequencer.sv		sequencer.sv
test.sv		test.sv
top.sv		top.sv
transaction.sv		transaction.sv

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