diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 3993f9cc7fd5f..6140e1e43fa03 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1241,6 +1241,7 @@ dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \
 	tegra20-colibri-eval-v3.dtb \
 	tegra20-colibri-iris.dtb \
 	tegra20-medcom-wide.dtb \
+	tegra20-p4wifi.dtb \
 	tegra20-paz00.dtb \
 	tegra20-plutux.dtb \
 	tegra20-qemu.dtb \
diff --git a/arch/arm/boot/dts/tegra20-p4wifi.dts b/arch/arm/boot/dts/tegra20-p4wifi.dts
new file mode 100644
index 0000000000000..6c55d2c24ece1
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20-p4wifi.dts
@@ -0,0 +1,1201 @@
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/input/atmel-maxtouch.h>
+#include "tegra20.dtsi"
+#include "tegra20-cpu-opp.dtsi"
+#include "tegra20-cpu-opp-microvolt.dtsi"
+/*
+ * Note that GPIO_OPEN_DRAIN flag has no effect on Tegra, the GPIO is fixed
+ * to open-drain mode in board's hardware. We set that flag just for consistency.
+ */
+#define TEGRA_I2C_GPIO_FLAGS	(GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)
+
+/ {
+	model = "Samsung Galaxy Tab 10.1 WIFI";
+	compatible = "samsung,p4wifi", "nvidia,tegra20";
+
+	aliases {
+		rtc0 = "/i2c@7000d000/tps6586x@74";
+		serial0 = &uarta;
+		serial2 = &uartc;
+		i2c0 = "/i2c@7000c000/mpu3050@68/i2c-gate/ak8975@0c";
+	};
+
+	chosen {
+		bootargs = "";
+	};
+
+	memory@0 {
+		reg = <0x00000000 0x40000000>;
+	};
+
+	reserved-memory {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		/* bootloader reads/writes magic values in this region */
+		bootloader_data: bootloader_data@1FF00000 {
+			reg = <0x1FF00000 0x00100000>;
+			no-map;
+		};
+
+		ramoops: ramoops@2E500000 {
+			compatible = "ramoops";
+			reg = <0x2E500000 0x00100000>;
+			record-size	= <0x00020000>;
+			console-size	= <0x00020000>;
+			ftrace-size	= <0x00020000>;
+			pmsg-size	= <0x00020000>;
+		};
+	};
+
+	clocks {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		clk32k_in: clock@0 {
+			compatible = "fixed-clock";
+			reg=<0>;
+			#clock-cells = <0>;
+			clock-frequency = <32768>;
+		};
+	};
+
+	power-domain-core {
+		power-supply = <&core_vdd_reg>;
+	};
+
+	host1x@50000000 {
+		compatible = "nvidia,tegra20-host1x", "simple-bus";
+
+		dc@54200000 {
+			compatible = "nvidia,tegra20-dc";
+			clocks = <&tegra_car TEGRA20_CLK_DISP1>,
+				 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
+			clock-names = "dc", "parent";
+
+			assigned-clocks = <&tegra_car TEGRA20_CLK_DISP1>;
+			assigned-clock-rates = <68750000>;
+			assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
+
+			rgb {
+				status = "okay";
+				nvidia,panel = <&cmc6230r>;
+			};
+		};
+	};
+
+	pinmux@70000014 {
+		pinctrl-names = "default";
+		pinctrl-0 = <&state_default>;
+
+		state_default: pinmux {
+			ata {
+				nvidia,pins = "ata", "atc", "atd", "ate", "gmb",
+					"gmd", "irrx", "irtx", "spid", "spie";
+				nvidia,function = "gmi";
+			};
+			atb {
+				nvidia,pins = "atb", "gma", "gme";
+				nvidia,function = "sdio4";
+			};
+			cdev1 {
+				nvidia,pins = "cdev1";
+				nvidia,function = "plla_out";
+			};
+			cdev2 {
+				nvidia,pins = "cdev2";
+				nvidia,function = "osc";
+			};
+			crtp {
+				nvidia,pins = "crtp";
+				nvidia,function = "crt";
+			};
+			csus {
+				nvidia,pins = "csus";
+				nvidia,function = "vi_sensor_clk";
+			};
+			dap1 {
+				nvidia,pins = "dap1";
+				nvidia,function = "dap1";
+			};
+			dap2 {
+				nvidia,pins = "dap2";
+				nvidia,function = "dap2";
+			};
+			dap3 {
+				nvidia,pins = "dap3";
+				nvidia,function = "dap3";
+			};
+			dap4 {
+				nvidia,pins = "dap4";
+				nvidia,function = "dap4";
+			};
+			ddc {
+				nvidia,pins ="spif", "uac";
+				nvidia,function = "rsvd4";
+			};
+			spif {
+				nvidia,pins = "spif", "uac";
+				nvidia,function = "rsvd4";
+			};
+			dta {
+				nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
+				nvidia,function = "vi";
+			};
+			dtf {
+				nvidia,pins = "dtf";
+				nvidia,function = "i2c3";
+			};
+			gmc {
+				nvidia,pins = "gmc";
+				nvidia,function = "uartd";
+			};
+			gpu {
+				nvidia,pins = "gpu";
+				nvidia,function = "uarta";
+			};
+			gpu7 {
+				nvidia,pins = "gpu7";
+				nvidia,function = "rtck";
+			};
+			gpv {
+				nvidia,pins = "gpv", "slxa", "slxk";
+				nvidia,function = "pcie";
+			};
+			hdint {
+				nvidia,pins = "hdint";
+				nvidia,function = "hdmi";
+			};
+			i2cp {
+				nvidia,pins = "i2cp";
+				nvidia,function = "i2cp";
+			};
+			kbca {
+				nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
+					"kbce", "kbcf";
+				nvidia,function = "kbc";
+			};
+			lcsn {
+				nvidia,pins = "lcsn",
+					"ld0", "ld1", "ld2", "ld3", "ld4",
+					"ld5", "ld6", "ld7", "ld8", "ld9",
+					"ld10", "ld11", "ld12", "ld13", "ld14",
+					"ld15", "ld16", "ld17", "ldc", "ldi",
+					"lhp0", "lhp1", "lhp2", "lhs",
+					"lm1", "lpp", "lpw1",
+					"lsc0", "lsck", "lsda", "lsdi",
+					"lspi", "lvp0", "lvp1", "lvs";
+				nvidia,function = "displaya";
+			};
+			lm0 {
+				nvidia,pins = "lm0", "lpw0", "lpw2", "lsc1";
+				nvidia,function = "spi3";
+			};
+			owc {
+				nvidia,pins = "owc";
+				nvidia,function = "owr";
+			};
+			pmc {
+				nvidia,pins = "pmc";
+				nvidia,function = "pwr_on";
+			};
+			rm {
+				nvidia,pins = "rm";
+				nvidia,function = "i2c1";
+			};
+			sdb {
+				nvidia,pins = "sdb", "sdc", "sdd";
+				nvidia,function = "sdio3";
+			};
+			sdio1 {
+				nvidia,pins = "sdio1";
+				nvidia,function = "sdio1";
+			};
+			slxc {
+				nvidia,pins = "slxc", "slxd";
+				nvidia,function = "spi4";
+			};
+			spdi {
+				nvidia,pins = "spdi", "spdo";
+				nvidia,function = "rsvd2";
+			};
+			spia {
+				nvidia,pins = "spia", "spib", "spic";
+				nvidia,function = "spi1";
+			};
+			spig {
+				nvidia,pins = "spig", "spih";
+				nvidia,function = "spi2_alt";
+			};
+			uaa {
+				nvidia,pins = "uaa", "uab", "uda";
+				nvidia,function = "ulpi";
+			};
+			uad {
+				nvidia,pins = "uad";
+				nvidia,function = "irda";
+			};
+			uca {
+				nvidia,pins = "uca", "ucb";
+				nvidia,function = "uartc";
+			};
+
+			ck32 {
+				nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", "pmcc", "pmcd", "pmce", "xm2c","xm2d";
+			};
+
+			conf_ata {
+				nvidia,pins = "ata", "atb", "ddc", "gma", "gmd", "gme", "gpu",
+					"irtx", "kbca", "kbcc", "kbce", "pmce", "spie", "spig",
+					"spih", "uad", "uca", "ucb";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			};
+
+			conf_owc {
+				nvidia,pins = "owc";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+			};
+
+			conf_atc {
+				nvidia,pins = "atc", "ate", "cdev1", "dap1",
+				"dap2", "dap4", "dte", "gmc", "gpu7", "gpv", "i2cp",
+				"pta", "rm", "slxc", "slxd", "slxk", "spdi", "spdo",
+				"uab", "uac";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			};
+
+			/*
+			 * pin atd is linked to gpios:
+			 *   TEGRA_GPIO_PO2 i2c@13 scl
+			 *   TEGRA_GPIO_PO3 i2c@13 sda
+			 */
+			conf_atd {
+				nvidia,pins = "atd";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			};
+
+			/*
+			 * pin uaa is linked to gpios:
+			 *   TEGRA_GPIO_PO1 usb-sel2
+			 *   TEGRA_GPIO_PO2 i2c@12 sda
+			 *   TEGRA_GPIO_PO4 i2c@12 scl
+			 *
+			 *   We want to boot with usb-sel2 high
+			 *   so that USB is in AP mode.
+			 */
+			conf_uaa {
+				nvidia,pins = "uaa";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			};
+
+			conf_uda {
+				nvidia,pins = "uda";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			};
+
+			conf_ck32 {
+				nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
+					"pmcc", "pmcd", "xm2c", "xm2d";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			};
+
+			conf_crtp {
+				nvidia,pins = "crtp", "slxa";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+			};
+
+			conf_csus {
+				nvidia,pins = "csus";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+			};
+
+			conf_dap3 {
+				nvidia,pins = "dap3", "dta", "dtb", "dtc", "dtd", "dtf",
+				"gmb", "irrx", "kbcb", "kbcd", "kbcf",
+				"sdc", "sdd", "spia", "spib", "spic", "spid", "spif";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			};
+
+			/* wifi */
+			conf_sdio1 {
+				nvidia,pins = "sdio1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			};
+
+			/* mxt1386 */
+			conf_slxc {
+				nvidia,pins = "slxc";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			};
+
+			/*
+			 * lpw0 is linked to TEGRA_GPIO_PB2 usb-sel1
+			 *   Pull mode is not supported on this pin.
+			 *   Leave it untouched.
+			 */
+			conf_lpw0 {
+				nvidia,pins = "lpw0";
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+			};
+
+			/* Pull up/down configs from v3.1.10 kernel that don't work on upstream kernel. */
+			conf_lcsn {
+				nvidia,pins =
+					/* pull up */
+					"lcsn", "ldc", "lpw1",
+					"lpw2", "lsc1", "lsck", "lsda", "lsdi",
+
+					/* pull down */
+					"ld0", "ld1", "ld2", "ld3", "ld4", "ld5", "ld6", "ld7", "ld8",
+					"ld9", "ld10", "ld11", "ld12", "ld13", "ld14", "ld15",
+					"ld16", "ld17", "ldi", "lhp0", "lhp1", "lhp2", "lpp", "lvp1",
+
+					/* pull none */
+					"lhs", "lm0", "lm1", "lsc0", "lspi", "lvs", "pmc", "sdb",
+					"hdint",
+					"lvp0";
+
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			};
+
+			conf_lvp0 {
+				nvidia,pins = "lvp0";
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+			};
+
+			drive_sdio1 {
+				nvidia,pins = "drive_sdio1";
+				nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
+				nvidia,schmitt = <TEGRA_PIN_ENABLE>;
+				nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
+				nvidia,pull-down-strength = <31>;
+				nvidia,pull-up-strength = <31>;
+				nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
+				nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
+			};
+		};
+
+		state_i2cmux_ddc: pinmux_i2cmux_ddc {
+			ddc {
+				nvidia,pins = "ddc";
+				nvidia,function = "i2c2";
+			};
+			pta {
+				nvidia,pins = "pta";
+				nvidia,function = "rsvd4";
+			};
+		};
+
+		state_i2cmux_pta: pinmux_i2cmux_pta {
+			ddc {
+				nvidia,pins = "ddc";
+				nvidia,function = "rsvd4";
+			};
+			pta {
+				nvidia,pins = "pta";
+				nvidia,function = "i2c2";
+			};
+		};
+
+		state_i2cmux_idle: pinmux_i2cmux_idle {
+			ddc {
+				nvidia,pins = "ddc";
+				nvidia,function = "rsvd4";
+			};
+			pta {
+				nvidia,pins = "pta";
+				nvidia,function = "rsvd4";
+			};
+		};
+
+		state_isa1200_on: state_isa1200_on {
+			cdev2 {
+				nvidia,pins = "cdev2";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			};
+		};
+
+		state_isa1200_off: state_isa1200_off {
+			cdev2 {
+				nvidia,pins = "cdev2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+			};
+		};
+	};
+
+	gpio: gpio@6000d000 {
+		compatible = "nvidia,tegra20-gpio";
+
+		/*
+		 * Enables wm8994 and bh1721.
+		 * According to TRM gpio A0 is linked to pinctrl dte
+		 * but this pinctrl doesn't seem to affect the GPIO.
+		 */
+		wm8994-bh1721-enable {
+			gpio-hog;
+			gpios = <TEGRA_GPIO(A, 0) GPIO_ACTIVE_HIGH>;
+			output-high;
+		};
+
+		wm8994-mic-bias {
+			gpio-hog;
+			gpios = <TEGRA_GPIO(X, 6) GPIO_ACTIVE_HIGH>;
+			output-high;
+		};
+	};
+
+	i2c@7000c000 {
+		status = "okay";
+		clock-frequency = <386000>;
+
+		assigned-clocks = <&tegra_car TEGRA20_CLK_I2C1>;
+		assigned-clock-rates = <386000>;
+		assigned-clock-parents =<&tegra_car TEGRA20_CLK_PLL_P>;
+
+		mpu3050@68 {
+			compatible = "invensense,mpu3050";
+			reg = <0x68>;
+			interrupt-parent = <&gpio>;
+			interrupts = <TEGRA_GPIO(V, 6) IRQ_TYPE_LEVEL_HIGH>;
+
+			mount-matrix = "0", "1", "0",
+					"1", "0", "0",
+					"0", "0", "1";
+
+			i2c-gate {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				kxtf9: kxtf9@f {
+					compatible = "kionix,kxtf9";
+					reg = <0x0F>;
+				};
+			};
+		};
+	};
+
+	i2c@7000c400 {
+		status = "okay";
+		clock-frequency = <100000>;
+
+		assigned-clocks = <&tegra_car TEGRA20_CLK_I2C2>;
+		assigned-clock-rates = <100000>;
+		assigned-clock-parents =<&tegra_car TEGRA20_CLK_PLL_P>;
+	};
+
+	i2cmux {
+		compatible = "i2c-mux-pinctrl";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		mux-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_HIGH
+			&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH
+			&gpio TEGRA_GPIO(J, 2) GPIO_ACTIVE_HIGH>;
+
+		i2c-parent = <&{/i2c@7000c400}>;
+
+		pinctrl-names = "ddc", "pta", "idle";
+		pinctrl-0 = <&state_i2cmux_ddc>;
+		pinctrl-1 = <&state_i2cmux_pta>;
+		pinctrl-2 = <&state_i2cmux_idle>;
+
+		i2c@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			touch@4c {
+				compatible = "atmel,maxtouch";
+				reg = <0x4c>;
+				interrupt-parent = <&gpio>;
+				interrupts = <TEGRA_GPIO(D, 4) IRQ_TYPE_LEVEL_LOW>;
+
+				reset-gpio = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_LOW>;
+
+				atmel,wakeup-method = <ATMEL_MXT_WAKEUP_I2C_SCL>;
+			};
+		};
+
+		i2c@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+	};
+
+	i2c@7000c500 {
+		status = "okay";
+		clock-frequency = <386000>;
+
+		assigned-clocks = <&tegra_car TEGRA20_CLK_I2C3>;
+		assigned-clock-rates = <386000>;
+		assigned-clock-parents =<&tegra_car TEGRA20_CLK_PLL_P>;
+	};
+
+	i2c@5 {
+		compatible = "i2c-gpio";
+		gpios = <
+			&gpio TEGRA_GPIO(Y, 2) TEGRA_I2C_GPIO_FLAGS
+			&gpio TEGRA_GPIO(Y, 0) TEGRA_I2C_GPIO_FLAGS >;
+		i2c-gpio,delay-us = <1>;
+		i2c-gpio,timeout-ms = <0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		bh1721: bh1721@23 {
+			compatible = "rohm,bh1721";
+			reg = <0x23>;
+		};
+	};
+
+	i2c@6 {
+		compatible = "i2c-gpio";
+		gpios = <
+			&gpio TEGRA_GPIO(O, 0) TEGRA_I2C_GPIO_FLAGS
+			&gpio TEGRA_GPIO(O, 7) TEGRA_I2C_GPIO_FLAGS >;
+		i2c-gpio,delay-us = <1>;
+		i2c-gpio,timeout-ms = <0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		battery: max17042-battery@36 {
+			compatible = "maxim,max17042";
+			reg = <0x36>;
+
+			interrupt-parent = <&gpio>;
+			interrupts = <TEGRA_GPIO(O, 6) IRQ_TYPE_LEVEL_HIGH>;
+
+			maxim,rsns-microohm = <10000>;
+			maxim,over-volt = <4300>;
+
+			power-supplies = <&charger>;
+		};
+	};
+
+	i2c@8 {
+		compatible = "i2c-gpio";
+		gpios = <
+			&gpio TEGRA_GPIO(G, 3) TEGRA_I2C_GPIO_FLAGS
+			&gpio TEGRA_GPIO(I, 0) TEGRA_I2C_GPIO_FLAGS >;
+		i2c-gpio,delay-us = <1>;
+		i2c-gpio,timeout-ms = <0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		wm8994: wm8994@1b {
+			compatible = "wlf,wm8994";
+			reg = <0x1B>;
+
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			wlf,ldo1ena =  <&gpio TEGRA_GPIO(X, 5) GPIO_ACTIVE_HIGH>;
+			wlf,gpio-cfg = <0xA101 0 0 0 0 0 0 0 0 0 0>;
+
+			lineout1-se;
+		};
+	};
+
+	i2c@9 {
+		compatible = "i2c-gpio";
+		gpios = <
+			&gpio TEGRA_GPIO(Y, 3) TEGRA_I2C_GPIO_FLAGS
+			&gpio TEGRA_GPIO(Y, 1) TEGRA_I2C_GPIO_FLAGS >;
+		i2c-gpio,delay-us = <1>;
+		i2c-gpio,timeout-ms = <0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		temperature-sensor@4c {
+			compatible = "onnn,nct1008";
+			reg = <0x4c>;
+			vcc-supply = <&vbus1_reg>;
+			interrupt-parent = <&gpio>;
+			interrupts = <TEGRA_GPIO(U, 6) IRQ_TYPE_LEVEL_HIGH>;
+		};
+	};
+
+	i2c@10 {
+		compatible = "i2c-gpio";
+		gpios = <
+			&gpio TEGRA_GPIO(Z, 3) TEGRA_I2C_GPIO_FLAGS
+			&gpio TEGRA_GPIO(C, 6) TEGRA_I2C_GPIO_FLAGS >;
+		i2c-gpio,delay-us = <3>;
+		i2c-gpio,timeout-ms = <0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cmc6230r: display@38 {
+			compatible = "samsung,cmc6230r";
+			reg = <0x38>;
+
+			clocks = <&tegra_car TEGRA20_CLK_DISP1>,
+				 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
+			clock-names = "dc", "parent";
+
+			mlcd-on-gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
+			ima-sleep-gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
+			ima-bypass-gpio = <&gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH>;
+			ima-pwren-gpio = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_HIGH>;
+			lvds-n-shdn-gpio = <&gpio TEGRA_GPIO(C, 1) GPIO_ACTIVE_HIGH>;
+			mlcd-on1-gpio = <&gpio TEGRA_GPIO(X, 0) GPIO_ACTIVE_HIGH>;
+			ima-n-rst-gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
+			bl-reset-gpio = <&gpio TEGRA_GPIO(R, 3) GPIO_ACTIVE_HIGH>;
+		};
+	};
+	i2c@11 {
+		compatible = "i2c-gpio";
+		gpios = <
+			&gpio TEGRA_GPIO(G, 2) TEGRA_I2C_GPIO_FLAGS
+			&gpio TEGRA_GPIO(I, 7) TEGRA_I2C_GPIO_FLAGS >;
+		i2c-gpio,delay-us = <3>;
+		i2c-gpio,timeout-ms = <0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		stmpe811@41 {
+			compatible = "st,stmpe811";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x41>;
+			interrupts = <TEGRA_GPIO(V, 5) IRQ_TYPE_LEVEL_LOW>;
+			interrupt-parent = <&gpio>;
+			interrupt-controller;
+
+			st,adc-freq = <3>;
+			st,ave-ctrl = <3>;
+			st,mod-12b = <1>;
+			st,ref-sel = <0>;
+
+			adc: stmpe_adc {
+				compatible = "st,stmpe-adc";
+				#io-channel-cells = <1>;
+				/* dont use ADC CH3-0 */
+				/* st,norequest-mask = <0x0F>; */
+			};
+		};
+	};
+
+	i2c@12 {
+		compatible = "i2c-gpio";
+		gpios = <
+			&gpio TEGRA_GPIO(O, 4) TEGRA_I2C_GPIO_FLAGS
+			&gpio TEGRA_GPIO(O, 2) TEGRA_I2C_GPIO_FLAGS >;
+		i2c-gpio,delay-us = <1>;
+		i2c-gpio,timeout-ms = <0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ak8975@c {
+				compatible = "asahi-kasei,ak8975";
+				reg = <0xc>;
+				gpios = <&gpio TEGRA_GPIO(K, 4) GPIO_ACTIVE_HIGH>;
+				/* vdd-supply = <&ldo_3v3_gnss>; */
+				mount-matrix = "-0.984807753012208",  /* x0 */
+							   "0",                   /* y0 */
+							   "-0.173648177666930",  /* z0 */
+							   "0",                   /* x1 */
+							   "-1",                  /* y1 */
+							   "0",                   /* z1 */
+							   "-0.173648177666930",  /* x2 */
+							   "0",                   /* y2 */
+							   "0.984807753012208";   /* z2 */
+		};
+	};
+
+	i2c@15 {
+		compatible = "i2c-gpio";
+		gpios = <
+			&gpio TEGRA_GPIO(I, 3) TEGRA_I2C_GPIO_FLAGS
+			&gpio TEGRA_GPIO(K, 2) TEGRA_I2C_GPIO_FLAGS >;
+		i2c-gpio,delay-us = <1>;
+		i2c-gpio,timeout-ms = <0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		@48 {
+			compatible = "samsung_p3,isa1200_vibrator";
+			reg = <0x48>;
+			enable-gpio = <&gpio TEGRA_GPIO(R, 6) GPIO_ACTIVE_HIGH>;
+
+			max-timeout = <10000>;
+			ctrl0 = <17>;
+			ctrl1 = <192>;
+			ctrl2 = <0>;
+			ctrl4 = <0>;
+			pll = <0x23>;
+			duty = <0x71>;
+			period = <0x74>;
+
+			clocks = <&tegra_car TEGRA20_CLK_CDEV2>;
+			clock-names = "vibrator-clk";
+
+			pinctrl-names = "on", "off";
+			pinctrl-0 = <&state_isa1200_on>;
+			pinctrl-1 = <&state_isa1200_off>;
+		};
+	};
+
+	dvc: i2c@7000d000 {
+		status = "okay";
+		clock-frequency = <386000>;
+
+		assigned-clocks = <&tegra_car TEGRA20_CLK_DVC>;
+		assigned-clock-rates = <386000>;
+		assigned-clock-parents =<&tegra_car TEGRA20_CLK_PLL_P>;
+
+		pmic: tps6586x@74 {
+			compatible = "ti,tps6586x";
+			reg = <0x74>;
+			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+
+			ti,system-power-controller;
+			#gpio-cells = <2>;
+			gpio-controller;
+
+			sys-supply = <&vdd_3v3_reg>;
+			vin-sm0-supply = <&sys_reg>;
+			vin-sm1-supply = <&sys_reg>;
+			vin-sm2-supply = <&sys_reg>;
+			vinldo01-supply = <&sm2_reg>;
+			vinldo23-supply = <&sm2_reg>;
+			vinldo4-supply = <&sm2_reg>;
+			vinldo678-supply = <&sm2_reg>;
+			vinldo9-supply = <&sm2_reg>;
+
+			regulators {
+				sys_reg: sys {
+					regulator-name = "vdd_sys";
+					regulator-boot-on;
+					regulator-always-on;
+				};
+
+				core_vdd_reg: sm0 {
+					regulator-name = "vdd_sm0,vdd_core";
+					regulator-min-microvolt = <950000>;
+					regulator-max-microvolt = <1300000>;
+					regulator-coupled-with = <&rtc_vdd_reg &cpu_vdd_reg>;
+					regulator-coupled-max-spread = <170000 550000>;
+					regulator-always-on;
+					regulator-boot-on;
+
+					nvidia,tegra-core-regulator;
+				};
+
+				cpu_vdd_reg: sm1 {
+					regulator-name = "vdd_sm1,vdd_cpu";
+					regulator-min-microvolt = <725000>;
+					regulator-max-microvolt = <1125000>;
+					regulator-coupled-with = <&core_vdd_reg &rtc_vdd_reg>;
+					regulator-coupled-max-spread = <550000 550000>;
+					regulator-always-on;
+					regulator-boot-on;
+
+					nvidia,tegra-cpu-regulator;
+				};
+
+				sm2_reg: sm2 {
+					regulator-name = "vdd_sm2,DBVDD,AVDD2,CPVDD";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-always-on;
+				};
+
+				/* LDO0 is not connected to anything */
+
+				ldo1 {
+					regulator-name = "vdd_ldo1,avdd_pll*";
+					regulator-min-microvolt = <1100000>;
+					regulator-max-microvolt = <1100000>;
+					regulator-always-on;
+				};
+
+				rtc_vdd_reg: ldo2 {
+					regulator-name = "vdd_ldo2,vdd_rtc,vdd_aon";
+					regulator-min-microvolt = <950000>;
+					regulator-max-microvolt = <1300000>;
+					regulator-coupled-with = <&core_vdd_reg &cpu_vdd_reg>;
+					regulator-coupled-max-spread = <170000 550000>;
+					regulator-always-on;
+					regulator-boot-on;
+
+					nvidia,tegra-rtc-regulator;
+				};
+
+				ldo3 {
+					regulator-name = "vdd_ldo3,avdd_usb*,avdd_lvds";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+					regulator-always-on;
+				};
+
+				ldo4 {
+					regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-always-on;
+				};
+
+				wlreg: ldo5 {
+					regulator-name = "vdd_ldo5,vcore_mmc";
+					regulator-min-microvolt = <2850000>;
+					regulator-max-microvolt = <2850000>;
+				};
+
+				vbus1_reg: ldo6 {
+					regulator-name = "vdd_ldo6,vddio_vi,vdd_nct1008";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+					regulator-boot-on;
+				};
+
+				ldo7 {
+					regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+				};
+
+				ldo8 {
+					regulator-name = "vdd_ldo8,avdd_hdmi_pll";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+				};
+
+				ldo9 {
+					regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
+					regulator-min-microvolt = <2850000>;
+					regulator-max-microvolt = <2850000>;
+					regulator-always-on;
+				};
+
+				ldo_rtc {
+					regulator-name = "vdd_rtc_out,vdd_cell";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+					regulator-always-on;
+				};
+			};
+		};
+	};
+
+	pmc@7000e400 {
+		nvidia,invert-interrupt;
+		nvidia,suspend-mode = <1>;
+		nvidia,cpu-pwr-good-time = <2000>;
+		nvidia,cpu-pwr-off-time = <100>;
+		nvidia,core-pwr-good-time = <126 126>;
+		nvidia,core-pwr-off-time = <15>;
+		nvidia,sys-clock-req-active-high;
+		nvidia,lp0-vec = <0x1840E000 0x2000>;
+	};
+
+	vdd_3v3_reg: regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vdd_3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+	};
+
+	charger: max8903-charger {
+		compatible = "maxim,max8903";
+		cen-gpios = <&gpio TEGRA_GPIO(X, 4) GPIO_ACTIVE_HIGH>;
+		dok-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
+		dcm-gpios = <&gpio TEGRA_GPIO(V, 4) GPIO_ACTIVE_HIGH>;
+		chg-gpios = <&gpio TEGRA_GPIO(K, 5) GPIO_ACTIVE_HIGH>;
+	};
+
+	p4wifi-usb {
+		compatible = "samsung,p4wifi-usb";
+		interrupt-parent = <&gpio>;
+		/* interrupts = <TEGRA_GPIO(W, 2) IRQ_TYPE_LEVEL_LOW>; */
+
+		vcc-supply = <&vbus1_reg>;
+
+		connect-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
+		usb-sel1-gpio =  <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>;
+		usb-sel2-gpio =  <&gpio TEGRA_GPIO(O, 1) GPIO_ACTIVE_HIGH>;
+
+		io-channels = <&adc 6>;
+		io-channel-names = "usb-cable-detect";
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		power {
+			label = "Power key";
+			gpios = <&gpio TEGRA_GPIO(S, 4) GPIO_ACTIVE_HIGH>;
+			linux,code = <116>; /* KEY_POWER */
+			gpio-key,wakeup;
+			debounce-interval = <10>;
+		};
+
+		jack_button {
+			label = "Headset jack button";
+			gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>;
+			linux,code = <240>; /* KEY_UNKNOWN */
+			debounce-interval = <30>;
+		};
+	};
+
+	keyboard: keyboard {
+		compatible = "nvidia,tegra20-kbc";
+		reg = <0x7000e200 0x100>;
+		interrupts = <0 85 0x04>;
+		clocks = <&tegra_car 36>;
+		resets = <&tegra_car 36>;
+		reset-names = "kbc";
+		nvidia,debounce-delay-ms = <10>;
+		nvidia,repeat-delay-ms = <1024>;
+		nvidia,kbc-row-pins = <0 1>;
+		nvidia,kbc-col-pins = <17>;
+		linux,keymap = <
+			MATRIX_KEY(0x00, 0x00, KEY_VOLUMEDOWN)
+			MATRIX_KEY(0x01, 0x00, KEY_VOLUMEUP) >;
+	};
+
+	headset-jack {
+		compatible = "samsung,p4wifi-headset-jack";
+
+		jack-detect-gpio = <&gpio TEGRA_GPIO(W, 3) GPIO_ACTIVE_HIGH>;
+		ear-micbias-gpio = <&gpio TEGRA_GPIO(S, 3) GPIO_ACTIVE_HIGH>;
+
+		io-channels = <&adc 4>;
+		io-channel-names = "headset-jack-detect";
+
+		jack-zones {
+			jack_zone0 {
+				adc-high = <0>;
+				delay-ms = <1>;
+				check-count = <2>;
+				jack-type = <2>; /* SEC_HEADSET_3POLE */
+			};
+			jack_zone1 {
+				adc-high = <900>;
+				delay-ms = <1>;
+				check-count = <20>;
+				jack-type = <2>; /* SEC_HEADSET_3POLE */
+			};
+			jack_zone2 {
+				adc-high = <2000>;
+				delay-ms = <1>;
+				check-count = <2>;
+				jack-type = <1>; /* SEC_HEADSET_4POLE */
+			};
+			jack_zone3 {
+				adc-high = <3800>;
+				delay-ms = <1>;
+				check-count = <2>;
+				jack-type = <1>; /* SEC_HEADSET_4POLE */
+			};
+			jack_zone4 {
+				adc-high = <0x7fffffff>;
+				delay-ms = <1>;
+				check-count = <50>;
+				jack-type = <2>; /* SEC_HEADSET_3POLE */
+			};
+		};
+
+		jack-button-zones {
+			jack_button0 {
+				code = <KEY_MEDIA>;
+				adc-low = <0>;
+				adc-high = <150>;
+			};
+			jack_button1 {
+				code = <KEY_VOLUMEUP>;
+				adc-low = <151>;
+				adc-high = <330>;
+			};
+			jack_button2 {
+				code = <KEY_VOLUMEDOWN>;
+				adc-low = <331>;
+				adc-high = <1000>;
+			};
+		};
+	};
+
+	tegra_i2s1: i2s@70002800 {
+		status = "okay";
+	};
+
+	sound {
+		compatible = "nvidia,tegra-audio-wm8994";
+		nvidia,model = "wm8994-aif1";
+
+		nvidia,i2s-controller = <&tegra_i2s1>;
+		nvidia,audio-codec = <&wm8994>;
+
+		clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
+			 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
+			 <&tegra_car TEGRA20_CLK_CDEV1>;
+		clock-names = "pll_a", "pll_a_out0", "mclk";
+	};
+
+	usb@c5000000 {
+		compatible = "nvidia,tegra20-udc";
+		status = "okay";
+		dr_mode = "peripheral";
+	};
+
+	usb-phy@c5000000 {
+		status = "okay";
+		vbus-supply = <&vbus1_reg>;
+	};
+
+	mmc@c8000000 {
+		status = "okay";
+		bus-width = <4>;
+		power-gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_HIGH>;
+		keep-power-in-suspend;
+		broken-cd;
+		no-1-8-v;
+		non-removable;
+
+		brcmf: wifi@1 {
+			compatible = "brcm,bcm4329-fmac";
+		};
+	};
+
+	mmc@c8000600 {
+		status = "okay";
+		bus-width = <8>;
+		non-removable;
+	};
+
+	uarta: serial@70006000 {
+		compatible = "nvidia,tegra20-hsuart";
+		status = "okay";
+	};
+
+	uartc: serial@70006200 {
+		compatible = "nvidia,tegra20-hsuart";
+		status = "okay";
+
+		bluetooth {
+			compatible = "brcm,bcm43438-bt";
+
+			device-wakeup-gpio = <&gpio TEGRA_GPIO(S, 1) GPIO_ACTIVE_HIGH>;
+			host-wakeup-gpios = <&gpio TEGRA_GPIO(S, 2) GPIO_ACTIVE_HIGH>;
+
+			shutdown-gpio = <&gpio TEGRA_GPIO(W, 1) GPIO_ACTIVE_HIGH>;
+
+			clocks = <&tegra_car TEGRA20_CLK_UARTC>;
+			clock-names = "uartc";
+
+			max-speed = <2000000>;
+		};
+	};
+
+	memory-controller@7000f400 {
+		emc-table@25000 {
+			reg = <25000>;
+			compatible = "nvidia,tegra20-emc-table";
+			clock-frequency = < 25000 >;
+			nvidia,emc-registers = < 0x00000002 0x00000006
+				0x00000003 0x00000003 0x00000006 0x00000004
+				0x00000002 0x0000000b 0x00000003 0x00000003
+				0x00000002 0x00000002 0x00000003 0x00000005
+				0x00000004 0x00000008 0x0000000c 0x0000004d
+				0x00000000 0x00000003 0x00000003 0x00000003
+				0x00000008 0x00000001 0x0000000b 0x00000004
+				0x00000003 0x00000008 0x00000004 0x00000008
+				0x00000002 0x00000068 0x00000004 0x00000003
+				0x00000000 0x00000000 0x00000282 0xa09404ae
+				0x0007c000 0x00000000 0x00000000 0x00000003
+				0x00000000 0x00000000 0x00000000 0x00000000 >;
+		};
+		emc-table@50000 {
+			reg = <50000>;
+			compatible = "nvidia,tegra20-emc-table";
+			clock-frequency = < 50000 >;
+			nvidia,emc-registers = < 0x00000003 0x00000007
+				0x00000003 0x00000003 0x00000006 0x00000004
+				0x00000002 0x0000000b 0x00000003 0x00000003
+				0x00000002 0x00000002 0x00000003 0x00000006
+				0x00000004 0x00000008 0x0000000c 0x0000009f
+				0x00000000 0x00000003 0x00000003 0x00000003
+				0x00000008 0x00000001 0x0000000b 0x00000007
+				0x00000003 0x00000008 0x00000004 0x00000008
+				0x00000002 0x000000d0 0x00000005 0x00000000
+				0x00000000 0x00000000 0x00000282 0xa09404ae
+				0x0007c000 0x00000000 0x00000000 0x00000005
+				0x00000000 0x00000000 0x00000000 0x00000000 >;
+		};
+		emc-table@75000 {
+			reg = <75000>;
+			compatible = "nvidia,tegra20-emc-table";
+			clock-frequency = < 75000 >;
+			nvidia,emc-registers = < 0x00000005 0x0000000a
+				0x00000004 0x00000003 0x00000006 0x00000004
+				0x00000002 0x0000000b 0x00000003 0x00000003
+				0x00000002 0x00000002 0x00000003 0x00000006
+				0x00000004 0x00000008 0x0000000c 0x000000ff
+				0x00000000 0x00000003 0x00000003 0x00000003
+				0x00000008 0x00000001 0x0000000b 0x0000000b
+				0x00000003 0x00000008 0x00000004 0x00000008
+				0x00000002 0x00000138 0x00000005 0x00000000
+				0x00000000 0x00000000 0x00000282 0xa09404ae
+				0x0007c000 0x00000000 0x00000000 0x00000007
+				0x00000000 0x00000000 0x00000000 0x00000000 >;
+		};
+		emc-table@150000 {
+			reg = <150000>;
+			compatible = "nvidia,tegra20-emc-table";
+			clock-frequency = < 150000 >;
+			nvidia,emc-registers = < 0x00000009 0x00000014
+				0x00000007 0x00000003 0x00000006 0x00000004
+				0x00000002 0x0000000b 0x00000003 0x00000003
+				0x00000002 0x00000002 0x00000003 0x00000006
+				0x00000004 0x00000008 0x0000000c 0x0000021f
+				0x00000000 0x00000003 0x00000003 0x00000003
+				0x00000008 0x00000001 0x0000000b 0x00000015
+				0x00000003 0x00000008 0x00000004 0x00000008
+				0x00000002 0x00000270 0x00000005 0x00000001
+				0x00000000 0x00000000 0x00000282 0xa06804ae
+				0x007dc010 0x00000000 0x00000000 0x0000000e
+				0x00000000 0x00000000 0x00000000 0x00000000 >;
+		};
+		emc-table@300000 {
+			reg = <300000>;
+			compatible = "nvidia,tegra20-emc-table";
+			clock-frequency = < 300000 >;
+			nvidia,emc-registers = < 0x00000012 0x00000027
+				0x0000000d 0x00000006 0x00000007 0x00000005
+				0x00000003 0x0000000b 0x00000006 0x00000006
+				0x00000003 0x00000003 0x00000003 0x00000007
+				0x00000004 0x00000009 0x0000000d 0x0000045f
+				0x00000000 0x00000004 0x00000004 0x00000006
+				0x00000008 0x00000001 0x0000000f 0x0000002a
+				0x00000003 0x0000000f 0x00000007 0x00000007
+				0x00000002 0x000004e0 0x00000006 0x00000002
+				0x00000000 0x00000000 0x00000282 0xe04e048b
+				0x007e0010 0x00000000 0x00000000 0x0000001b
+				0x00000000 0x00000000 0x00000000 0x00000000 >;
+		};
+	};
+};
+
+&emc_icc_dvfs_opp_table {
+	/delete-node/ opp@666000000;
+	/delete-node/ opp@760000000;
+};