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update opcode names
add missing register
Updated Fragment Shader ISA (markdown)
A bit more info about PSEQ
Start documenting PSEQ instruction
"general purpose registers" -> "global registers" + add some patent links
document FP20 and FX10
Render targets usage
The bit 16 of DW instruction is something else
Data write instruction encoding
Texture LOD bias register
Note on ALU source CR's addressing limitation