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Main Issues #73

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grantslape opened this issue Jun 30, 2018 · 1 comment
Open

Main Issues #73

grantslape opened this issue Jun 30, 2018 · 1 comment
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@grantslape
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  • Verilog Main still doesn't work. Possibly hierarch design to figure out where the issue is. converting project to 0.10 style fully may help with this as well.
@grantslape grantslape added the bug Something isn't working label Feb 23, 2019
@grantslape
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Additionally see #48 for more information but basically we hacked the main driver together last minute and it is WAY TOO COMPLEX and the verilog side doesn't work. The MyHDL side seems to work fine, and each individual verilog module passes unit tests.

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