From f2e9daba0b1f8ed9ce4fa9153312918268f41891 Mon Sep 17 00:00:00 2001 From: Pawel Czarnecki Date: Tue, 12 Nov 2024 14:09:29 +0100 Subject: [PATCH] modules/zstd/BUILD: increase pipeline_stages for DecoderMux proc Signed-off-by: Pawel Czarnecki --- xls/modules/zstd/BUILD | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/xls/modules/zstd/BUILD b/xls/modules/zstd/BUILD index 8717497922..94b6b3ecdb 100644 --- a/xls/modules/zstd/BUILD +++ b/xls/modules/zstd/BUILD @@ -506,7 +506,7 @@ xls_dslx_verilog( codegen_args = { "module_name": "DecoderMux", "delay_model": "asap7", - "pipeline_stages": "2", + "pipeline_stages": "3", "reset": "rst", "use_system_verilog": "false", }, @@ -520,7 +520,7 @@ xls_benchmark_ir( name = "dec_mux_opt_ir_benchmark", src = ":dec_mux_verilog.opt.ir", benchmark_ir_args = { - "pipeline_stages": "2", + "pipeline_stages": "10", "delay_model": "asap7", }, tags = ["manual"],