The Verible project's main mission is to parse SystemVerilog (IEEE 1800-2017) (as standardized in the SV-LRM) for a wide variety of applications, including developer tools.
It was born out of a need to parse un-preprocessed source files, which is suitable for single-file applications like style-linting and formatting. In doing so, it can be adapted to parse preprocessed source files, which is what real compilers and toolchains require.
The spirit of the project is that no-one should ever have to develop a SystemVerilog parser for their own application, because developing a standard-compliant parser is an enormous task due to the syntactic complexity of the language. Verible's parser is also regularly tested against an ever-growing suite of (tool-independent) language compliance tests at https://symbiflow.github.io/sv-tests/.
A lesser (but notable) objective is that the language-agnostic components of Verible be usable for rapidly developing language support tools for other languages.
For source code browsing, we recommend using the fully-indexed and searchable mirror at https://cs.opensource.google/verible/verible.
If you'd like to contribute, check out the contributing guide and the development resources.
Verible's code base is written in C++.
To build, you need the bazel build system and a C++17 compatible compiler (e.g. >= g++-9).
# Build all tools and libraries
bazel build -c opt //...You can access the generated artifacts under bazel-bin/. For instance the
syntax checker will be at
bazel-bin/verilog/tools/syntax/verible-verilog-syntax (corresponding to the
target name //verilog/tools/syntax:verible-verilog-syntax).
For simple installation, we provide regular binary releases.
If you prefer to build and install the binaries locally yourself:
# In your home directory
bazel run -c opt :install -- ~/bin
# For a system directory that requires root-access, call with -s option.
# (Do _not_ run bazel with sudo.)
bazel run -c opt :install -- -s /usr/local/binWe strongly encourage running the test suite using bazel:
# Run all tests
bazel test -c opt //...Join the Verible community!
- Developers: [email protected] (join)
- Users: [email protected] (join)
Learn more about the parser implementation here.
We provide a standalone verible-verilog-syntax tool
to help with visualizing the syntax structure as understood by the lexer and
parser. This is very useful tor troubleshooting and understand the internal
representations seen by the other tools.
The tool has an ability of exporting a concrete syntax tree in JSON format, making use of it in external tools easy. There is also a Python wrapper module and a few example scripts.
verible-verilog-lint identifies constructs or patterns
in code that are deemed undesirable according to a style guide. The main goal is
to relieve humans the burden of reviewing code for style compliance. Many
lint rules use syntax tree pattern matching to find style
violations.
Features:
- Style guide citations in diagnostics
- Rule deck configurability
- Waiver mechanisms: in-file, external waiver file
Documentation:
The verible-verilog-format formatter manages
whitespace in accordance with a particular style. The main goal is to relieve
humans of having to manually manage whitespace, wrapping, and indentation, and
to provide a tool that can be integrated into any editor to enable
editor-independent consistency.
Features (various degress of work-in-progress):
- Corrects indentation
- Corrects inter-token spacing, with syntax context awareness
- Line-wrapping to a column limit
- Support for incremental formatting, only touched changed lines.
- Interactive formatting: accept or decline formatting changes
- Tabular alignment
verible-verilog-diff compares two input files for
equivalence.
verible-verilog-project is a multi-tool that
operates on whole Verilog projects, consisting of a file list and related
configurations. This serves as a diagnostic tool for analyzing (and potentially
transforming) project-level sources.
verible-verilog-obfuscate transforms Verilog
code by replacing identifiers with obfuscated names of equal length, and
preserving all other text, including spaces. Output is written to stdout. The
resulting file size is the same as the original. This is useful for preparing
potentially sensitive test cases with tool vendors.
verible-verilog-preprocessor is a collection
of preprocessor-like tools, (but does not include a fully-featured Verilog
preprocessor yet.)
verible-verilog-kythe-extractor extracts indexing
facts fromm SV source code using the Kythe schema, which can
then enhance IDEs with linked cross-references for ease of source code
navigation.
The Verible team is interested in exploring how it can help other tool developers in providing a SystemVerilog front end, for example, emitting an abstract syntax tree (AST). If you are interested in collaborating, contact us.