Bootloader cleanup list

[jacobrosenthal]

This is bootloader setup
https://github.com/im-tomu/tomu-bootloader/blob/master/toboot/main.c

These things dont appear to get undone and need to be handled

// Enable LE and DMA interfaces. // _CMU_HFCORECLKEN0_RESETVALUE   0x00000000UL
CMU->HFCORECLKEN0 = CMU_HFCORECLKEN0_LE

//Universal Serial Bus Low Energy Clock Clock Enable // _CMU_LFCCLKEN0_RESETVALUE   0x00000000UL
CMU->LFCCLKEN0 |= CMU_LFCCLKEN0_USBLE;

/* Set HFRCO freq 21 MHz */ _CMU_AUXHFRCOCTRL_RESETVALUE   0x00000080UL
CMU->HFRCOCTRL = (4 << 8) | (DEVINFO->HFRCOCAL1 & 0xff << 0);

// _CMU_OSCENCMD_RESETVALUE   0x00000000UL
CMU->OSCENCMD = CMU_OSCENCMD_HFXODIS | CMU_OSCENCMD_AUXHFRCODIS | CMU_OSCENCMD_LFRCODIS | CMU_OSCENCMD_USHFRCODIS;

//_CMU_CMD_RESETVALUE   0x00000000UL
CMU->CMD |= CMU_CMD_HFCLKSEL_HFRCO;

// _WDOG_CMD_RESETVALUE   0x00000000UL
WDOG->CTRL = WDOG_CTRL_CLKSEL_ULFRCO | WDOG_CTRL_EN | (3 << _WDOG_CTRL_PERSEL_SHIFT);

// Enable RTC interrupts //sets NVIC_ISER I think we should clear by writing 0xFFFFFFFF ??
NVIC_EnableIRQ(RTC_IRQn);

Stuff that wasnt obvious but that doesnt need to be reset

// 	_GPIO_P_DOUTSET_RESETVALUE   0x00000000UL // writing 0 has no effect so doesnt need to be undone
GPIO->P[0].DOUTSET = (1 << 0);
// _GPIO_P_DOUTCLR_RESETVALUE   0x00000000UL  // writing 0 has no effect so doesnt need to be undone
GPIO->P[1].DOUTCLR = (1 << 7);

// Calibrate USB based on communications  _CMU_USHFRCOCONF_RESETVALUE   0x00000001UL //this is the reset value
CMU->USHFRCOCONF = CMU_USHFRCOCONF_BAND_48MHZ;

heres the where I got the reset values, we may want to bring these in and make them available for free functions where we give back the peripheral?
https://docs.silabs.com/mcu/5.6/efm32hg/group-EFM32HG-GPIO-BitFields

[fudanchii]

Apologies I might missed the context, it looks like they already reset those values back here https://github.com/im-tomu/tomu-bootloader/blob/master/toboot/main.c#L285-L315

    USB->GAHBCFG = _USB_GAHBCFG_RESETVALUE;
    USB->GINTMSK = _USB_GINTMSK_RESETVALUE;
    USB->DAINTMSK = _USB_DAINTMSK_RESETVALUE;
    USB->DOEPMSK = _USB_DOEPMSK_RESETVALUE;
    USB->DIEPMSK = _USB_DIEPMSK_RESETVALUE;
    USB->CTRL = _USB_CTRL_RESETVALUE;

    // Reset RTC settings.
    RTC->IEN = _RTC_IEN_RESETVALUE;
    RTC->COMP0 = _RTC_COMP0_RESETVALUE;
    RTC->CTRL = _RTC_CTRL_RESETVALUE;

    // Wait for LF peripheral syncronization.
    while (RTC->SYNCBUSY & _RTC_SYNCBUSY_MASK)
        ;
    while (CMU->SYNCBUSY & CMU_SYNCBUSY_LFACLKEN0)
        ;
    // Switch to default cpu clock.
    CMU->CMD = CMU_CMD_HFCLKSEL_HFRCO;
    CMU->OSCENCMD = CMU_OSCENCMD_HFXODIS | CMU_OSCENCMD_AUXHFRCODIS | CMU_OSCENCMD_LFRCODIS | CMU_OSCENCMD_USHFRCODIS;
    CMU->USBCRCTRL = _CMU_USBCRCTRL_RESETVALUE;

    // Reset clock registers used
    CMU->HFCORECLKEN0 = CMU_HFCORECLKEN0_LE;
    CMU->HFPERCLKDIV = _CMU_HFPERCLKDIV_RESETVALUE;
    CMU->HFPERCLKEN0 = _CMU_HFPERCLKEN0_RESETVALUE;
    CMU->LFCLKSEL = _CMU_LFCLKSEL_RESETVALUE;
    CMU->LFACLKEN0 = _CMU_LFACLKEN0_RESETVALUE;

    GPIO->P[0].MODEL = _GPIO_P_MODEL_RESETVALUE;
GPIO->P[1].MODEL = _GPIO_P_MODEL_RESETVALUE;

heres the where I got the reset values, we may want to bring these in and make them available for free functions where we give back the peripheral?

wondering if the reset value is the same as the one exposed from pac. I'll check if we can just leak that out.

[jacobrosenthal]

All the ones I listed are not reset to _GPIO_P_MODEL_RESETVALUE theyre set to something else or not on that list.

[fudanchii]

Right, I misread your notes. Some of them are not reset indeed.

[jacobrosenthal]

Some more research on these

// Enable LE and DMA interfaces. // _CMU_HFCORECLKEN0_RESETVALUE   0x00000000UL
//despite the comment, this is just enables low energy peripherals
//which are? WDOG PCNT0 LEUART0 RTC
CMU->HFCORECLKEN0 = CMU_HFCORECLKEN0_LE

//Universal Serial Bus Low Energy Clock Clock Enable // _CMU_LFCCLKEN0_RESETVALUE   0x00000000UL
CMU->LFCCLKEN0 |= CMU_LFCCLKEN0_USBLE;

/* Set HFRCO freq 21 MHz */ _CMU_AUXHFRCOCTRL_RESETVALUE   0x00000080UL
//HFRCO Control Register
// set to 21mhz
//tuning
// case cmuHFRCOBand_21MHz:
//      tuning = (DEVINFO->HFRCOCAL1 & _DEVINFO_HFRCOCAL1_BAND21_MASK)
//               >> _DEVINFO_HFRCOCAL1_BAND21_SHIFT;
//      break;
//
//DEVINFO_BASE   (0x0FE081B0UL)
//where is the devinfo struct for svd? dont think we have it.. sigh
//https://github.com/em32-rs/efm32hg-pac/issues/9
CMU->HFRCOCTRL = (4 << 8) | (DEVINFO->HFRCOCAL1 & 0xff << 0);

// _CMU_OSCENCMD_RESETVALUE   0x00000000UL
//Oscillator Enable/Disable Command Register
//Disables the HFXO. HFXOEN has higher priority if is selected as the source for HFCLK.
//Disables the AUXHFRCO. AUXHFRCOEN has higher priority if written simultaneously. WARNING: Do not disable this clock during a flash erase/write operation.
//Disables the LFRCO. LFRCOEN has higher priority if written simultaneously
//Disables the USHFRCO. USHFRCOEN has higher priority if written simultaneously
//lxfo is unspoken for??
CMU->OSCENCMD = CMU_OSCENCMD_HFXODIS | CMU_OSCENCMD_AUXHFRCODIS | CMU_OSCENCMD_LFRCODIS | CMU_OSCENCMD_USHFRCODIS;

//_CMU_CMD_RESETVALUE   0x00000000UL
//Selects the clock source for HFCLK. Note that selecting an oscillator that is disabled will cause the system clock to stop. Check the status register and confirm that oscillator is ready before switching
//Select HFRCO as HFCLK
CMU->CMD |= CMU_CMD_HFCLKSEL_HFRCO;

// _WDOG_CMD_RESETVALUE   0x00000000UL
//Selects ULFRCO as the WDOG oscillator, i.e. the clock on which the watchdog will run
//Timeout period of 65 watchdog clock cycles. and our clock is 1000hz? 0.065s or 65ms
WDOG->CTRL = WDOG_CTRL_CLKSEL_ULFRCO | WDOG_CTRL_EN | (3 << _WDOG_CTRL_PERSEL_SHIFT);

// Enable RTC interrupts //sets NVIC_ISER I think we should clear by writing 0xFFFFFFFF ??
//RTC->CTRL was reset but not this. do we need to undo this? 
NVIC_EnableIRQ(RTC_IRQn);