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Seems like "e.g., compile Chisel to Verilog" would be for advanced users who want to use Stage/Phase etc to manually control this process as opposed to using the Chisel default?
Under the
FIRRTL
tab, include documentation about theStage/Phase
refactor and the Dependency API.This should include:
Possible people who can provide feedback include: @chick, @davidbiancolin
This is gated by #5.
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