Inconsistence between VCD and log

[phhorrein]

Using the PeekPokeTester, I ran into an issue where the VCD output of some signals is wrong. This happens with signals which are a mix of combinatorial oepration after a register, independent of any Input.

I joined an example. The faulty signal is the io.in.ready. At time 61ns, gtkwave shows that the signal is 0, yet it is in fact 1 (and used as such in the simulation, as the io.out.bits value is written). The same occurs at time 92ns (marked 1 in gtkwave, but seen as 0 in the simulation and in the log), as if the signal needed to be delayed. I added markers in the configuration if you want to check.

Any idea where this comes from ? It's reproducible (I have the issue with a FIFO, where the full is combinatorially computed based on the usage register).

bug_report.zip