Peek/poke bulk-connected bundles?

[jkorinth]

Chisel3 implements strict last assignment, and PeekPokeTester peek/poke do not allow peeking or poking internals of a module, only value in the top-most IO. This leads to a difficult situation: If I need to bulk-connect two Modules with complex Bundle subtypes (mixed Input/Output) and need to access values in my PeekPokeTester (to monitor the connection), the only option is to replicate the entire interface as output-only and wire each element separately. Example:

                                                                                                                        
class A extends Bundle {                                                                                                
  val a = Output(UInt(8.W))                                                                                             
  val b = Input(UInt(8.W))                                                                                              
  val c = Input(Bool())                                                                                                 
}                                                                                                                       
                                                                                                                        
class Sender extends Module {                                                                                           
  val io = IO(new A)                                                                                                    
                                                                                                                        
  io.a := RegNext(42.U, init = 0.U)                                                                                     
}                                                                                                                       
                                                                                                                        
class Receiver extends Module {                                                                                         
  val io = IO(Flipped(new A))                                                                                           
                                                                                                                        
  io.b := RegNext(7.U, init = 0.U)                                                                                      
  io.c := RegNext(true.B, init = false.B)                                                                               
}                                                                                                                       
                                                                                                                        
class Test extends Module {                                                                                             
  val s = Module(new Sender)                                                                                            
  val r = Module(new Receiver)                                                                                          
  val io = IO(new Bundle {
    val f = s.io.cloneType                                                                                              
    val a = Output(UInt(8.W))                                                                                           
    val b = Output(UInt(8.W))                                                                                           
    val c = Output(Bool())                                                                                                                                                                                                                                                                                                     
  })                                                                                                                    
    

  // io.f <> s.io // does not work; next <> will re-assign to random values
  s.io <> r.io
  // this works, but is extremely tedious and breaks encapsulation                                                                                                          
  io.a := s.io.a                                                                                                        
  io.b := r.io.b                                                                                                        
  io.c := r.io.c                                                                                                        
}          

This approach may seem feasible in this tiny example, but it does not work when using complex bus interfaces with nested subbundles. How to peek/poke values in the connection between s and r in chisel3/iotesters?