Design did not meet timing

[ftqtfff]

[10:33:50] Starting bitstream generation..
[10:49:24] Run vpl: Step impl: Failed
[10:49:25] Run vpl: FINISHED. Run Status: impl ERROR

===>The following messages were generated while Compiling (bitstream) accelerator binary: network Log file: /home/ubuntu/Documents/Vitis_with_100Gbps_TCP-IP/build_dir.hw.xilinx_u280_xdma_201920_3/link/vivado/vpl/prj/prj.runs/impl_1/runme.log :
ERROR: [VPL-4] design did not meet timing - Design did not meet timing. One or more unscalable system clocks did not meet their required target frequency. Please try specifying a clock frequency lower than 250 MHz using the '--kernel_frequency' switch for the next compilation. For all system clocks, this design is using 0 nanoseconds as the threshold worst negative slack (WNS) value. List of system clocks with timing failure:
system clock: txoutclk_out[0]; slack: -0.030 ns
ERROR: [VPL 60-773] In '/home/ubuntu/Documents/Vitis_with_100Gbps_TCP-IP/build_dir.hw.xilinx_u280_xdma_201920_3/link/vivado/vpl/runme.log', caught Tcl error: problem implementing dynamic region, impl_1: route_design ERROR, please look at the run log file '/home/ubuntu/Documents/Vitis_with_100Gbps_TCP-IP/build_dir.hw.xilinx_u280_xdma_201920_3/link/vivado/vpl/prj/prj.runs/impl_1/runme.log' for more information
WARNING: [VPL 60-732] Link warning: No monitor points found for BD automation.
ERROR: [VPL 60-704] Integration error, problem implementing dynamic region, impl_1: route_design ERROR, please look at the run log file '/home/ubuntu/Documents/Vitis_with_100Gbps_TCP-IP/build_dir.hw.xilinx_u280_xdma_201920_3/link/vivado/vpl/prj/prj.runs/impl_1/runme.log' for more information
ERROR: [VPL 60-1328] Vpl run 'vpl' failed
ERROR: [VPL 60-806] Failed to finish platform linker
INFO: [v++ 60-1442] [10:49:26] Run run_link: Step vpl: Failed
Time (s): cpu = 00:08:02 ; elapsed = 05:39:19 . Memory (MB): peak = 1341.246 ; gain = 0.000 ; free physical = 48585 ; free virtual = 62358
ERROR: [v++ 60-661] v++ link run 'run_link' failed
ERROR: [v++ 60-626] Kernel link failed to complete
ERROR: [v++ 60-703] Failed to finish linking

[hoanbk2811]

I have the same issue when creating design with 2019.2 version. Did anyone solve this?

[pzcong]

@ftqtfff @hoanbk2811
Hi, I solved the "timing" issue. You can try to delete this line “CLFLAGS += --kernel_frequency 200” of Makefile.