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Even though MPU for ARC EM & ARCv2 HS (HS3x & HS4x) is very similar from functional point of view, their settings differ a little bit.
ARC EM processors only support 1, 2, 4, 8 & 16 regions (and that's what we currently have available in QEMU), while ARCv2 HS processors support 8, 16, 18, 20, 22, 24, 26, 28, 30 & 32 regions.
We need to handle that properly depending on the CPU which is being simulated.
The text was updated successfully, but these errors were encountered:
Even though MPU for ARC EM & ARCv2 HS (HS3x & HS4x) is very similar from functional point of view, their settings differ a little bit.
ARC EM processors only support 1, 2, 4, 8 & 16 regions (and that's what we currently have available in QEMU), while ARCv2 HS processors support 8, 16, 18, 20, 22, 24, 26, 28, 30 & 32 regions.
We need to handle that properly depending on the CPU which is being simulated.
The text was updated successfully, but these errors were encountered: