Fixed problem with TARGET_ARC.. preprocessor checks.

foss-for-synopsys-dwc-arc-processors · Apr 19, 2021 · 70208fc · 70208fc
1 parent 9822104
commit 70208fc
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Showing 7 changed files with 16 additions and 16 deletions.
diff --git a/target/arc/cpu.c b/target/arc/cpu.c
@@ -229,7 +229,7 @@ static void arc_cpu_realizefn(DeviceState *dev, Error **errp)
      */
     cpu->freq_hz = cpu->cfg.freq_hz;
 
-#ifdef TARGET_ARCV2
+#if defined(TARGET_ARCV2)
     cpu->isa_config = 0x02;
     switch (cpu->cfg.pc_size) {
     case 16:
@@ -295,7 +295,7 @@ static void arc_cpu_realizefn(DeviceState *dev, Error **errp)
       | (cpu->cfg.dmp_unaligned ? BIT(22) : 0) | BIT(23)
       | (cpu->cfg.code_density ? (2 << 24) : 0) | BIT(28);
 
-#elif TARGET_ARCV3
+#elif defined(TARGET_ARCV3)
     cpu->isa_config = 0x03        /* ver */
                       | (1 << 8)  /* va_size: 48-bit */
                       | (1 << 16) /* pa_size: 48-bit */

diff --git a/target/arc/cpu.h b/target/arc/cpu.h
@@ -67,10 +67,10 @@ enum exception_code_list {
     EXCP_MEMORY_ERROR,
     EXCP_INST_ERROR,
     EXCP_MACHINE_CHECK,
-#ifdef TARGET_ARCV2
+#if defined(TARGET_ARCV2)
     EXCP_TLB_MISS_I,
     EXCP_TLB_MISS_D,
-#elif TARGET_ARCV3
+#elif defined(TARGET_ARCV3)
     EXCP_IMMU_FAULT,
     EXCP_DMMU_FAULT,
 #else
@@ -252,9 +252,9 @@ typedef struct CPUARCState {
     uint32_t causecode;
     uint32_t param;
 
-#ifdef TARGET_ARCV2
+#if defined(TARGET_ARCV2)
     struct arc_mmu mmu;       /* mmu.h */
-#elif TARGET_ARCV3
+#elif defined(TARGET_ARCV3)
     struct arc_mmuv6 mmu;       /* mmu.h */
 #endif
     ARCMPU mpu;               /* mpu.h */

diff --git a/target/arc/gdbstub.c b/target/arc/gdbstub.c
@@ -30,9 +30,9 @@
 #define REG_ADDR(reg, processor_type) \
     arc_aux_reg_address_for((reg), (processor_type))
 
-#ifdef TARGET_ARCV2
+#if defined(TARGET_ARCV2)
 #define GDB_GET_REG gdb_get_reg32
-#elif TARGET_ARCV3
+#elif defined(TARGET_ARCV3)
 #define GDB_GET_REG gdb_get_reg64
 #else
     #error No target is selected.

diff --git a/target/arc/helper.c b/target/arc/helper.c
@@ -80,14 +80,14 @@ void arc_cpu_do_interrupt(CPUState *cs)
     case EXCP_MACHINE_CHECK:
         name = "Machine Check";
         break;
-#ifdef TARGET_ARCV2
+#if defined(TARGET_ARCV2)
     case EXCP_TLB_MISS_I:
         name = "TLB Miss Instruction";
         break;
     case EXCP_TLB_MISS_D:
         name = "TLB Miss Data";
         break;
-#elif TARGET_ARCV3
+#elif defined(TARGET_ARCV3)
     case EXCP_IMMU_FAULT:
         name = "Instruction MMU Fault";
         break;

diff --git a/target/arc/irq.c b/target/arc/irq.c
@@ -30,10 +30,10 @@
 #include "qemu/host-utils.h"
 
 #define CACHE_ENTRY_SIZE (TARGET_LONG_BITS / 8)
-#ifdef TARGET_ARCV2
+#if defined(TARGET_ARCV2)
 #define TARGET_LONG_LOAD(ENV, ADDR) cpu_ldl_data(ENV, ADDR)
 #define TARGET_LONG_STORE(ENV, ADDR, VALUE) cpu_stl_data(ENV, ADDR, VALUE)
-#elif TARGET_ARCV3
+#elif defined(TARGET_ARCV3)
 #define TARGET_LONG_LOAD(ENV, ADDR) cpu_ldq_data(ENV, ADDR)
 #define TARGET_LONG_STORE(ENV, ADDR, VALUE) cpu_stq_data(ENV, ADDR, VALUE)
 #else

diff --git a/target/arc/irq.h b/target/arc/irq.h
@@ -32,9 +32,9 @@ void arc_resetIRQ(ARCCPU *);
 uint32_t pack_status32(ARCStatus *);
 void unpack_status32(ARCStatus *, uint32_t);
 
-#ifdef TARGET_ARCV2
+#if defined(TARGET_ARCV2)
 #define OFFSET_FOR_VECTOR(VECNO) (VECNO << 2)
-#elif TARGET_ARCV3
+#elif defined(TARGET_ARCV3)
 #define OFFSET_FOR_VECTOR(VECNO) (VECNO << 3)
 #else
 #error Should never be reached

diff --git a/target/arc/translate.c b/target/arc/translate.c
@@ -756,9 +756,9 @@ arc_gen_SR(DisasCtxt *ctx, TCGv src2, TCGv src1)
 {
     int ret = DISAS_NEXT;
 
-#ifdef TARGET_ARCV2
+#if defined(TARGET_ARCV2)
     writeAuxReg(src2, src1);
-#elif TARGET_ARCV3
+#elif defined(TARGET_ARCV3)
     TCGv temp = tcg_temp_local_new();
     tcg_gen_andi_tl(temp, src1, 0xffffffff);
     writeAuxReg(src2, src1);