The format is based on Keep a Changelog, and this project adheres to Semantic Versioning.
(v1.3.0 targeted for 2025-01-30) (Github compare v1.2.1...master)
(2024-05-22) (Github compare v1.2.0...v1.2.1)
- Add support for DAC ad5754 component
(2023-12-13) (Github compare v1.1.0...v1.2.0)
- Add DAC AD5668 to AXI components
- Add AXI components TRCT1000 sensor and stepper motor
- Add interrupt capability to AXI bus components
- Add base clock register to avalon GPIO component, avalon and axi components must have identical register addresses
(2021-07-13) (Github compare v1.0.0...v1.1.0)
- Add AXI interface for all devices
- UART dual port RAM fixed
(2018-02-11)