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Fix tridiag_rank1_barrier_busy_wait configuration option #907

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msimberg
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It was initialized with the wrong value. Sorry about this.

I will separately rerun the benchmarks that I did for the tridiagonal solver, but now I can include the distributed results as well (with #904).

@msimberg msimberg self-assigned this Jun 14, 2023
@msimberg msimberg requested a review from albestro June 14, 2023 13:06
@msimberg msimberg assigned rasolca and unassigned rasolca Jun 14, 2023
@msimberg msimberg requested a review from rasolca June 14, 2023 13:06
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cscs-ci run

@msimberg msimberg force-pushed the fix-tridiag-rank1-busy-wait-config-option branch from da96261 to 7b1e62d Compare June 14, 2023 13:07
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cscs-ci run

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As soon as this one gets merged I'm going to rebase #904 and introduce tridiag_rank1_barrier_busy_wait parameter also in the distributed 😉

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cscs-ci stop

@msimberg msimberg force-pushed the fix-tridiag-rank1-busy-wait-config-option branch from 7b1e62d to d9adeed Compare June 14, 2023 14:42
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cscs-ci run

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cscs-ci run

@rasolca rasolca merged commit 34934c6 into eth-cscs:master Jun 16, 2023
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3 participants