ESP32-S3 SIMD instructions misassembled (LLVM-368)

[Noxime]

After running into some IllegalInstruction exceptions, I found that a number of the PIE instructions on the ESP32-S3 have the wrong instruction format. As an example, the EE.VADDS.S8.LD.INCP has wrong definition:

XtensaS3DSPInstrInfo.td

let Inst{28-23} = 0x38;
let Inst{22-20} = qu{2-0};
let Inst{19-17} = qa{2-0};
let Inst{16-14} = qx{2-0};
let Inst{13-11} = qy{2-0};
let Inst{10-4} = 0x1c;
let Inst{3-0} = as{3-0};

This does not match the instruction format from the ESP32-S3 TRM:
111000 qu[2:1] qy[0] 001 qu[0] qa[2:0] qx[1:0] qy[2:1] 1100 as[3:0] 111 qx[2]

I haven't gathered a comprehensive list, but I suspect all the instructions with format EE_Inst32 and let Inst{28-... in their body are defective, since they don't define all instruction bits (and by quick glance, have the fields in wrong places). Generally, all combined math+memory instructions (32 bit *.[LD/ST].[INCP/IP/XP])

I can PR the fixes to these tablegen files myself, but the file says it's been generated from something called AI_S6_V2.h, which cannot be found anywhere on the internet. Should this be fixed in that Espressif-internal file, or can I submit changes to the .td file manually?

[sstefan1]

Hi! I'm not sure I can share the file. Apparently the file seems to be wrong here. As soon as we fix the file, I'll commit the fixed tablegen definitions.

[sstefan1]

Hi @Noxime! The fix for this is now merged. Please check it out.

[Noxime]

Hi @Noxime! The fix for this is now merged. Please check it out.

Woo, thank you!