-
Notifications
You must be signed in to change notification settings - Fork 51
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
Question about the IRAM_ATTR usage with uart ISR #50
Comments
I hit Guru Meditation Error: Core 0 panic'ed (Illegal instruction). Exception was unhandled. Just check the npl_freertos_callout_is_active implementation:
It looks like esp_timer_is_active() also needs IRAM_ATTR. |
Hi @AxelLin , thanks for pointing out. We will review and make the needed changes . |
Similarly, esp_timer_delete() is called by npl_freertos_callout_deinit() which may need IRAM_ATTR. Just FYI, this probably needs a review as well. |
Hi @AxelLin
May i know how you are reproducing this issue ? Are you disabling flash cache or any other setting ?
Indeed we are reviewing the code , but if there are ways to reproduce the failures , then this information would be helpful for us to test the changes thoroughly before releasing. |
Regarding disabling flash cache, do you mean this?
(It's default setting N, but it's strange the doc says it's default Y: https://docs.espressif.com/projects/esp-idf/en/latest/esp32c3/api-reference/storage/spi_flash_concurrency.html#concurrency-constraints-for-flash-on-spi1) I cannot provide the code for testing. BTW, I hope to understand the IRAM_ATTR functions usage. Can you help to clarify?
Is my understanding correct? |
Hi @AxelLin , IRAM_ATTR implies the code is in IRAM . So, code in IRAM makes execution fast. Also, code in IRAM implies that it has the ability to execute the code when flash cache is disabled. e.g. while programming flash ( say nvs write ) flash cache is disabled, so we can not execute code from flash. If we place interrupt in IRAM then its entire call chain should be in IRAM. This interrupt will work even if flash cache is disabled. Basically , its good to have entire calling functions in IRAM_ATTR ( subjected to availabiity of IRAM space ) . Thanks, |
Hi @rahult-github |
I close this issue and move to esp-idf instead (since the change for esp_timer is not in nimble). |
Hi @rahult-github
In porting/nimble/src/hal_uart.c, there are IRAM_ATTR_64MCPU / IRAM_ATTR
in ISR / uart_rx_task functions. Which means all the functions called by
ISR or uart_rx_task needs to have IRAM_ATTR as well. Otherwise it could
hit "Guru Meditation Error: Core 0 panic'ed (Illegal instruction). Exception was unhandled".
Is my understanding correct?
If yes, the code in nimble/transport/uart/src/ble_hci_uart.c needs fix because ble_hci_uart_tx_char() and ble_hci_uart_rx_char() are called from an IRAM_ATTR function.
And what's the best way to fix this issue?
I'm aware the default esp-idf does not use ble_hci_uart.c, just use it to clarify if my understanding is correct.
The text was updated successfully, but these errors were encountered: