From ebd28253793dc0321450958ef2f6f62f72eccd30 Mon Sep 17 00:00:00 2001 From: zhiweijian Date: Fri, 21 Oct 2022 14:46:10 +0800 Subject: [PATCH 1/2] - update phy lib - Enable BLE pll track to fix bluetooth disconnection caused by temperature rise or fall on ESP32C3 and ESP32S3 - call pll track in controller task --- components/bt/controller/esp32c3/bt.c | 3 --- components/bt/controller/esp32s3/bt.c | 3 --- components/esp_phy/lib | 2 +- 3 files changed, 1 insertion(+), 7 deletions(-) diff --git a/components/bt/controller/esp32c3/bt.c b/components/bt/controller/esp32c3/bt.c index 57d1f6fb6763..738a07f673e4 100644 --- a/components/bt/controller/esp32c3/bt.c +++ b/components/bt/controller/esp32c3/bt.c @@ -242,7 +242,6 @@ extern bool btdm_deep_sleep_mem_init(void); extern void btdm_deep_sleep_mem_deinit(void); extern void btdm_ble_power_down_dma_copy(bool copy); extern uint8_t btdm_sleep_clock_sync(void); -extern void sdk_config_extend_set_pll_track(bool enable); #if CONFIG_MAC_BB_PD extern void esp_mac_bb_power_down(void); @@ -1092,8 +1091,6 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg) // overwrite some parameters cfg->magic = ESP_BT_CTRL_CONFIG_MAGIC_VAL; - sdk_config_extend_set_pll_track(false); - #if CONFIG_MAC_BB_PD esp_mac_bb_pd_mem_init(); #endif diff --git a/components/bt/controller/esp32s3/bt.c b/components/bt/controller/esp32s3/bt.c index 5aa1d03cddcb..6e1e3b818aa2 100644 --- a/components/bt/controller/esp32s3/bt.c +++ b/components/bt/controller/esp32s3/bt.c @@ -247,7 +247,6 @@ extern bool btdm_deep_sleep_mem_init(void); extern void btdm_deep_sleep_mem_deinit(void); extern void btdm_ble_power_down_dma_copy(bool copy); extern uint8_t btdm_sleep_clock_sync(void); -extern void sdk_config_extend_set_pll_track(bool enable); #if CONFIG_MAC_BB_PD extern void esp_mac_bb_power_down(void); @@ -1138,8 +1137,6 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg) // overwrite some parameters cfg->magic = ESP_BT_CTRL_CONFIG_MAGIC_VAL; - sdk_config_extend_set_pll_track(false); - #if CONFIG_MAC_BB_PD esp_mac_bb_pd_mem_init(); #endif diff --git a/components/esp_phy/lib b/components/esp_phy/lib index 8d3ce0243606..3daf84244605 160000 --- a/components/esp_phy/lib +++ b/components/esp_phy/lib @@ -1 +1 @@ -Subproject commit 8d3ce02436066e33e8964d34981a97fe64edae2e +Subproject commit 3daf842446056002dcdb12866001c3d567f1abd9 From 73cd69d5ad82c4c49b6d225b2a69d863a0272e7b Mon Sep 17 00:00:00 2001 From: zhiweijian Date: Fri, 28 Oct 2022 17:20:03 +0800 Subject: [PATCH 2/2] Fixed CI esp32s3.default_2_s3.Test failed --- components/esp_phy/test/test_phy_rtc.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/components/esp_phy/test/test_phy_rtc.c b/components/esp_phy/test/test_phy_rtc.c index ea24cdfbe2f5..ad04b462f8d5 100644 --- a/components/esp_phy/test/test_phy_rtc.c +++ b/components/esp_phy/test/test_phy_rtc.c @@ -81,12 +81,15 @@ static IRAM_ATTR void test_phy_rtc_cache_task(void *arg) #if SOC_BT_SUPPORTED +#if CONFIG_IDF_TARGET_ESP32 + /* Only esp32 will call bt_track_pll_cap() in the interrupt + handler, other chips will call this function in the task + */ ESP_LOGI(TAG, "Test bt_track_pll_cap()..."); spi_flash_disable_interrupts_caches_and_other_cpu(); bt_track_pll_cap(); spi_flash_enable_interrupts_caches_and_other_cpu(); -#if CONFIG_IDF_TARGET_ESP32 extern void bt_bb_init_cmplx_reg(void); ESP_LOGI(TAG, "Test bt_bb_init_cmplx_reg()..."); spi_flash_disable_interrupts_caches_and_other_cpu();