diff --git a/components/esp_adc/test_apps/adc/main/test_adc.c b/components/esp_adc/test_apps/adc/main/test_adc.c
index 4faecc01e807..f568dde6c724 100644
--- a/components/esp_adc/test_apps/adc/main/test_adc.c
+++ b/components/esp_adc/test_apps/adc/main/test_adc.c
@@ -124,7 +124,7 @@ TEST_CASE("ADC oneshot stress test that get zero even if convent done", "[adc_on
 
     int test_num = 100;
     adc_channel_t channel = ADC1_TEST_CHAN1;
-    adc_atten_t atten = ADC_ATTEN_DB_11;
+    adc_atten_t atten = ADC_ATTEN_DB_12;
     adc_unit_t unit_id = ADC_UNIT_1;
 
     adc_oneshot_unit_handle_t adc1_handle;
diff --git a/components/hal/adc_oneshot_hal.c b/components/hal/adc_oneshot_hal.c
index feddc3178ca0..1a5b56da4ebc 100644
--- a/components/hal/adc_oneshot_hal.c
+++ b/components/hal/adc_oneshot_hal.c
@@ -81,7 +81,7 @@ void adc_oneshot_hal_setup(adc_oneshot_hal_ctx_t *hal, adc_channel_t chan)
 #endif //#if SOC_ADC_ARBITER_SUPPORTED
 }
 
-static void adc_hal_onetime_start(adc_unit_t unit, uint32_t clk_src_freq_hz)
+static void adc_hal_onetime_start(adc_unit_t unit, uint32_t clk_src_freq_hz, uint32_t *read_delay_us)
 {
 #if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED
     (void)unit;
@@ -112,10 +112,8 @@ static void adc_hal_onetime_start(adc_unit_t unit, uint32_t clk_src_freq_hz)
      * A rough estimate for this step should be at least ADC_LL_DELAY_CYCLE_AFTER_DONE_SIGNAL ADC sar clock cycle.
      */
     uint32_t sar_clk = adc_ctrl_clk / ADC_LL_DIGI_SAR_CLK_DIV_DEFAULT;
-    uint32_t read_delay_us = ((1000 * 1000) / sar_clk + 1) * ADC_LL_DELAY_CYCLE_AFTER_DONE_SIGNAL;
+    *read_delay_us = ((1000 * 1000) / sar_clk + 1) * ADC_LL_DELAY_CYCLE_AFTER_DONE_SIGNAL;
     HAL_EARLY_LOGD("adc_hal", "clk_src_freq_hz: %"PRIu32", sar_clk: %"PRIu32", read_delay_us: %"PRIu32"", clk_src_freq_hz, sar_clk, read_delay_us);
-    esp_rom_delay_us(read_delay_us);
-
 #endif //ADC_LL_DELAY_CYCLE_AFTER_DONE_SIGNAL
 
 #else
@@ -127,6 +125,7 @@ bool adc_oneshot_hal_convert(adc_oneshot_hal_ctx_t *hal, int *out_raw)
 {
     bool valid = true;
     uint32_t event = 0;
+    uint32_t read_delay_us = 0;
     if (hal->unit == ADC_UNIT_1) {
         event = ADC_LL_EVENT_ADC1_ONESHOT_DONE;
     } else {
@@ -137,10 +136,11 @@ bool adc_oneshot_hal_convert(adc_oneshot_hal_ctx_t *hal, int *out_raw)
     adc_oneshot_ll_disable_all_unit();
     adc_oneshot_ll_enable(hal->unit);
 
-    adc_hal_onetime_start(hal->unit, hal->clk_src_freq_hz);
+    adc_hal_onetime_start(hal->unit, hal->clk_src_freq_hz, &read_delay_us);
     while (!adc_oneshot_ll_get_event(event)) {
         ;
     }
+    esp_rom_delay_us(read_delay_us);
     *out_raw = adc_oneshot_ll_get_raw_result(hal->unit);
 #if (SOC_ADC_PERIPH_NUM == 2)
     if (hal->unit == ADC_UNIT_2) {
diff --git a/components/hal/esp32h2/include/hal/adc_ll.h b/components/hal/esp32h2/include/hal/adc_ll.h
index 5e4fbce2b26f..dd9c8113798b 100644
--- a/components/hal/esp32h2/include/hal/adc_ll.h
+++ b/components/hal/esp32h2/include/hal/adc_ll.h
@@ -42,7 +42,7 @@ extern "C" {
                     Oneshot
 ---------------------------------------------------------------*/
 #define ADC_LL_DATA_INVERT_DEFAULT(PERIPH_NUM)         (0)
-#define ADC_LL_DELAY_CYCLE_AFTER_DONE_SIGNAL           (2)
+#define ADC_LL_DELAY_CYCLE_AFTER_DONE_SIGNAL           (5)
 
 /*---------------------------------------------------------------
                     DMA